drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <rte_string_fns.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_kvargs.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <ethdev_driver.h>
  30 #include <ethdev_pci.h>
  31 #include <rte_malloc.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_hash_crc.h>
  35 #ifdef RTE_LIB_SECURITY
  36 #include <rte_security_driver.h>
  37 #endif
  38
  39 #include "ixgbe_logs.h"
  40 #include "base/ixgbe_api.h"
  41 #include "base/ixgbe_vf.h"
  42 #include "base/ixgbe_common.h"
  43 #include "ixgbe_ethdev.h"
  44 #include "ixgbe_bypass.h"
  45 #include "ixgbe_rxtx.h"
  46 #include "base/ixgbe_type.h"
  47 #include "base/ixgbe_phy.h"
  48 #include "base/ixgbe_osdep.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE  "fiber_sdp3_no_tx_disable"
 132
 133 static const char * const ixgbe_valid_arguments[] = {
 134         IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE,
 135         NULL
 136 };
 137
 138 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 139
 140 static const char * const ixgbevf_valid_arguments[] = {
 141         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 142         NULL
 143 };
 144
 145 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 146 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 147 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 148 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 149 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 150 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 151 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 152 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 157 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 158 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 159 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 161 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 162 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 164                                 int wait_to_complete);
 165 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 166                                 struct rte_eth_stats *stats);
 167 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 168                                 struct rte_eth_xstat *xstats, unsigned n);
 169 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 170                                   struct rte_eth_xstat *xstats, unsigned n);
 171 static int
 172 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 173                 uint64_t *values, unsigned int n);
 174 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 177         struct rte_eth_xstat_name *xstats_names,
 178         unsigned int size);
 179 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 180         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 181 static int ixgbe_dev_xstats_get_names_by_id(
 182         struct rte_eth_dev *dev,
 183         const uint64_t *ids,
 184         struct rte_eth_xstat_name *xstats_names,
 185         unsigned int limit);
 186 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 187                                              uint16_t queue_id,
 188                                              uint8_t stat_idx,
 189                                              uint8_t is_rx);
 190 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 191                                  size_t fw_size);
 192 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 193                               struct rte_eth_dev_info *dev_info);
 194 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 195 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 196                                 struct rte_eth_dev_info *dev_info);
 197 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 198
 199 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 200                 uint16_t vlan_id, int on);
 201 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 202                                enum rte_vlan_type vlan_type,
 203                                uint16_t tpid_id);
 204 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 205                 uint16_t queue, bool on);
 206 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 207                 int on);
 208 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 209                                                   int mask);
 210 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 211 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 212 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 213 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 214 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 215 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 216
 217 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 219 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 220                                struct rte_eth_fc_conf *fc_conf);
 221 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 222                                struct rte_eth_fc_conf *fc_conf);
 223 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 224                 struct rte_eth_pfc_conf *pfc_conf);
 225 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 226                         struct rte_eth_rss_reta_entry64 *reta_conf,
 227                         uint16_t reta_size);
 228 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 232 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 233 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 237 static void ixgbe_dev_interrupt_handler(void *param);
 238 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 239 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 240 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 241                                               uint32_t timeout_ms);
 242
 243 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 244                         struct rte_ether_addr *mac_addr,
 245                         uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct rte_ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250 static bool is_device_supported(struct rte_eth_dev *dev,
 251                                 struct rte_pci_driver *drv);
 252
 253 /* For Virtual Function support */
 254 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 255 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 256 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 257 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 259                                    int wait_to_complete);
 260 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 261 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 262 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 263 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 264 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 265 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 266                 struct rte_eth_stats *stats);
 267 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 268 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 269                 uint16_t vlan_id, int on);
 270 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 271                 uint16_t queue, int on);
 272 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 273 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 274 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 275 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                             uint16_t queue_id);
 277 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                              uint16_t queue_id);
 279 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 280                                  uint8_t queue, uint8_t msix_vector);
 281 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 282 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 283 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 284 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 285 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 286
 287 /* For Eth VMDQ APIs support */
 288 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 289                 rte_ether_addr * mac_addr, uint8_t on);
 290 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 291 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 292                                           uint16_t queue_id);
 293 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 294                                            uint16_t queue_id);
 295 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 296                                uint8_t queue, uint8_t msix_vector);
 297 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 298
 299 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 300                                 struct rte_ether_addr *mac_addr,
 301                                 uint32_t index, uint32_t pool);
 302 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 303 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 304                                              struct rte_ether_addr *mac_addr);
 305 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 308                         struct ixgbe_5tuple_filter *filter);
 309 static int ixgbe_dev_flow_ops_get(struct rte_eth_dev *dev,
 310                                   const struct rte_flow_ops **ops);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct rte_ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 329                                  struct rte_eth_dev_module_info *modinfo);
 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 331                                    struct rte_dev_eeprom_info *info);
 332
 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 335                                 struct rte_dev_reg_info *regs);
 336
 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp,
 341                                             uint32_t flags);
 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp);
 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 346                                    struct timespec *timestamp);
 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 348                                    const struct timespec *timestamp);
 349 static void ixgbevf_dev_interrupt_handler(void *param);
 350
 351 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 352                                          struct rte_eth_udp_tunnel *udp_tunnel);
 353 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 354                                          struct rte_eth_udp_tunnel *udp_tunnel);
 355 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 356 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 357 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 358 static int devarg_handle_int(__rte_unused const char *key, const char *value,
 359                              void *extra_args);
 360
 361 /*
 362  * Define VF Stats MACRO for Non "cleared on read" register
 363  */
 364 #define UPDATE_VF_STAT(reg, last, cur)                          \
 365 {                                                               \
 366         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 367         cur += (latest - last) & UINT_MAX;                      \
 368         last = latest;                                          \
 369 }
 370
 371 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 372 {                                                                \
 373         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 374         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 375         u64 latest = ((new_msb << 32) | new_lsb);                \
 376         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 377         last = latest;                                           \
 378 }
 379
 380 #define IXGBE_SET_HWSTRIP(h, q) do {\
 381                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 382                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 383                 (h)->bitmap[idx] |= 1 << bit;\
 384         } while (0)
 385
 386 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 387                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 388                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 389                 (h)->bitmap[idx] &= ~(1 << bit);\
 390         } while (0)
 391
 392 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 393                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 394                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 395                 (r) = (h)->bitmap[idx] >> bit & 1;\
 396         } while (0)
 397
 398 /*
 399  * The set of PCI devices this driver supports
 400  */
 401 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 402         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 403         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 404         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 405         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 450 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 452 #endif
 453         { .vendor_id = 0, /* sentinel */ },
 454 };
 455
 456 /*
 457  * The set of PCI devices this driver supports (for 82599 VF)
 458  */
 459 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 470         { .vendor_id = 0, /* sentinel */ },
 471 };
 472
 473 static const struct rte_eth_desc_lim rx_desc_lim = {
 474         .nb_max = IXGBE_MAX_RING_DESC,
 475         .nb_min = IXGBE_MIN_RING_DESC,
 476         .nb_align = IXGBE_RXD_ALIGN,
 477 };
 478
 479 static const struct rte_eth_desc_lim tx_desc_lim = {
 480         .nb_max = IXGBE_MAX_RING_DESC,
 481         .nb_min = IXGBE_MIN_RING_DESC,
 482         .nb_align = IXGBE_TXD_ALIGN,
 483         .nb_seg_max = IXGBE_TX_MAX_SEG,
 484         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 485 };
 486
 487 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 488         .dev_configure        = ixgbe_dev_configure,
 489         .dev_start            = ixgbe_dev_start,
 490         .dev_stop             = ixgbe_dev_stop,
 491         .dev_set_link_up    = ixgbe_dev_set_link_up,
 492         .dev_set_link_down  = ixgbe_dev_set_link_down,
 493         .dev_close            = ixgbe_dev_close,
 494         .dev_reset            = ixgbe_dev_reset,
 495         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 496         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 497         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 498         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 499         .link_update          = ixgbe_dev_link_update,
 500         .stats_get            = ixgbe_dev_stats_get,
 501         .xstats_get           = ixgbe_dev_xstats_get,
 502         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 503         .stats_reset          = ixgbe_dev_stats_reset,
 504         .xstats_reset         = ixgbe_dev_xstats_reset,
 505         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 506         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 507         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 508         .fw_version_get       = ixgbe_fw_version_get,
 509         .dev_infos_get        = ixgbe_dev_info_get,
 510         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 511         .mtu_set              = ixgbe_dev_mtu_set,
 512         .vlan_filter_set      = ixgbe_vlan_filter_set,
 513         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 514         .vlan_offload_set     = ixgbe_vlan_offload_set,
 515         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 516         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 517         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 518         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 519         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 520         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 521         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 522         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 523         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 524         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 525         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 526         .dev_led_on           = ixgbe_dev_led_on,
 527         .dev_led_off          = ixgbe_dev_led_off,
 528         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 529         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 530         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 531         .mac_addr_add         = ixgbe_add_rar,
 532         .mac_addr_remove      = ixgbe_remove_rar,
 533         .mac_addr_set         = ixgbe_set_default_mac_addr,
 534         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 535         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 536         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 537         .reta_update          = ixgbe_dev_rss_reta_update,
 538         .reta_query           = ixgbe_dev_rss_reta_query,
 539         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 540         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 541         .flow_ops_get         = ixgbe_dev_flow_ops_get,
 542         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 543         .rxq_info_get         = ixgbe_rxq_info_get,
 544         .txq_info_get         = ixgbe_txq_info_get,
 545         .timesync_enable      = ixgbe_timesync_enable,
 546         .timesync_disable     = ixgbe_timesync_disable,
 547         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 548         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 549         .get_reg              = ixgbe_get_regs,
 550         .get_eeprom_length    = ixgbe_get_eeprom_length,
 551         .get_eeprom           = ixgbe_get_eeprom,
 552         .set_eeprom           = ixgbe_set_eeprom,
 553         .get_module_info      = ixgbe_get_module_info,
 554         .get_module_eeprom    = ixgbe_get_module_eeprom,
 555         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 556         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 557         .timesync_read_time   = ixgbe_timesync_read_time,
 558         .timesync_write_time  = ixgbe_timesync_write_time,
 559         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 560         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 561         .tm_ops_get           = ixgbe_tm_ops_get,
 562         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 563         .get_monitor_addr     = ixgbe_get_monitor_addr,
 564 };
 565
 566 /*
 567  * dev_ops for virtual function, bare necessities for basic vf
 568  * operation have been implemented
 569  */
 570 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 571         .dev_configure        = ixgbevf_dev_configure,
 572         .dev_start            = ixgbevf_dev_start,
 573         .dev_stop             = ixgbevf_dev_stop,
 574         .link_update          = ixgbevf_dev_link_update,
 575         .stats_get            = ixgbevf_dev_stats_get,
 576         .xstats_get           = ixgbevf_dev_xstats_get,
 577         .stats_reset          = ixgbevf_dev_stats_reset,
 578         .xstats_reset         = ixgbevf_dev_stats_reset,
 579         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 580         .dev_close            = ixgbevf_dev_close,
 581         .dev_reset            = ixgbevf_dev_reset,
 582         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 583         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 584         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 585         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 586         .dev_infos_get        = ixgbevf_dev_info_get,
 587         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 588         .mtu_set              = ixgbevf_dev_set_mtu,
 589         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 590         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 591         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 592         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 593         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 594         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 595         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 596         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 597         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 598         .mac_addr_add         = ixgbevf_add_mac_addr,
 599         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 600         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 601         .rxq_info_get         = ixgbe_rxq_info_get,
 602         .txq_info_get         = ixgbe_txq_info_get,
 603         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 604         .get_reg              = ixgbevf_get_regs,
 605         .reta_update          = ixgbe_dev_rss_reta_update,
 606         .reta_query           = ixgbe_dev_rss_reta_query,
 607         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 608         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 609         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 610         .get_monitor_addr     = ixgbe_get_monitor_addr,
 611 };
 612
 613 /* store statistics names and its offset in stats structure */
 614 struct rte_ixgbe_xstats_name_off {
 615         char name[RTE_ETH_XSTATS_NAME_SIZE];
 616         unsigned offset;
 617 };
 618
 619 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 620         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 621         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 622         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 623         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 624         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 625         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 626         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 627         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 628         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 629         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 630         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 631         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 632         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 633         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 634         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 635                 prc1023)},
 636         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 637                 prc1522)},
 638         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 639         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 640         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 641         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 642         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 643         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 644         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 645         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 646         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 647         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 648         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 649         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 650         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 651         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 652         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 653         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 654         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 655                 ptc1023)},
 656         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 657                 ptc1522)},
 658         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 659         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 660         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 661         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 662
 663         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 664                 fdirustat_add)},
 665         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 666                 fdirustat_remove)},
 667         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 668                 fdirfstat_fadd)},
 669         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 670                 fdirfstat_fremove)},
 671         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 672                 fdirmatch)},
 673         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 674                 fdirmiss)},
 675
 676         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 677         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 678         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 679                 fclast)},
 680         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 681         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 682         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 683         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 684         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 685                 fcoe_noddp)},
 686         {"rx_fcoe_no_direct_data_placement_ext_buff",
 687                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 688
 689         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 690                 lxontxc)},
 691         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 692                 lxonrxc)},
 693         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 694                 lxofftxc)},
 695         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 696                 lxoffrxc)},
 697         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 698 };
 699
 700 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 701                            sizeof(rte_ixgbe_stats_strings[0]))
 702
 703 /* MACsec statistics */
 704 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 705         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 706                 out_pkts_untagged)},
 707         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 708                 out_pkts_encrypted)},
 709         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 710                 out_pkts_protected)},
 711         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 712                 out_octets_encrypted)},
 713         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 714                 out_octets_protected)},
 715         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 716                 in_pkts_untagged)},
 717         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 718                 in_pkts_badtag)},
 719         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 720                 in_pkts_nosci)},
 721         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 722                 in_pkts_unknownsci)},
 723         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 724                 in_octets_decrypted)},
 725         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 726                 in_octets_validated)},
 727         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 728                 in_pkts_unchecked)},
 729         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 730                 in_pkts_delayed)},
 731         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_late)},
 733         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_ok)},
 735         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_invalid)},
 737         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_notvalid)},
 739         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_unusedsa)},
 741         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_notusingsa)},
 743 };
 744
 745 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 746                            sizeof(rte_ixgbe_macsec_strings[0]))
 747
 748 /* Per-queue statistics */
 749 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 750         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 751         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 752         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 753         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 754 };
 755
 756 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 757                            sizeof(rte_ixgbe_rxq_strings[0]))
 758 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 759
 760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 761         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 762         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 763         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 764                 pxon2offc)},
 765 };
 766
 767 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 768                            sizeof(rte_ixgbe_txq_strings[0]))
 769 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 770
 771 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 772         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 773 };
 774
 775 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 776                 sizeof(rte_ixgbevf_stats_strings[0]))
 777
 778 /*
 779  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 780  */
 781 static inline int
 782 ixgbe_is_sfp(struct ixgbe_hw *hw)
 783 {
 784         switch (hw->phy.type) {
 785         case ixgbe_phy_sfp_avago:
 786         case ixgbe_phy_sfp_ftl:
 787         case ixgbe_phy_sfp_intel:
 788         case ixgbe_phy_sfp_unknown:
 789         case ixgbe_phy_sfp_passive_tyco:
 790         case ixgbe_phy_sfp_passive_unknown:
 791                 return 1;
 792         default:
 793                 /* x550em devices may be SFP, check media type */
 794                 switch (hw->mac.type) {
 795                 case ixgbe_mac_X550EM_x:
 796                 case ixgbe_mac_X550EM_a:
 797                         switch (ixgbe_get_media_type(hw)) {
 798                         case ixgbe_media_type_fiber:
 799                         case ixgbe_media_type_fiber_qsfp:
 800                                 return 1;
 801                         default:
 802                                 break;
 803                         }
 804                 default:
 805                         break;
 806                 }
 807                 return 0;
 808         }
 809 }
 810
 811 static inline int32_t
 812 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 813 {
 814         uint32_t ctrl_ext;
 815         int32_t status;
 816
 817         status = ixgbe_reset_hw(hw);
 818
 819         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 820         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 821         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 822         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 823         IXGBE_WRITE_FLUSH(hw);
 824
 825         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 826                 status = IXGBE_SUCCESS;
 827         return status;
 828 }
 829
 830 static inline void
 831 ixgbe_enable_intr(struct rte_eth_dev *dev)
 832 {
 833         struct ixgbe_interrupt *intr =
 834                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 835         struct ixgbe_hw *hw =
 836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 837
 838         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 839         IXGBE_WRITE_FLUSH(hw);
 840 }
 841
 842 /*
 843  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 844  */
 845 static void
 846 ixgbe_disable_intr(struct ixgbe_hw *hw)
 847 {
 848         PMD_INIT_FUNC_TRACE();
 849
 850         if (hw->mac.type == ixgbe_mac_82598EB) {
 851                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 852         } else {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 854                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 856         }
 857         IXGBE_WRITE_FLUSH(hw);
 858 }
 859
 860 /*
 861  * This function resets queue statistics mapping registers.
 862  * From Niantic datasheet, Initialization of Statistics section:
 863  * "...if software requires the queue counters, the RQSMR and TQSM registers
 864  * must be re-programmed following a device reset.
 865  */
 866 static void
 867 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 868 {
 869         uint32_t i;
 870
 871         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 872                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 873                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 874         }
 875 }
 876
 877
 878 static int
 879 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 880                                   uint16_t queue_id,
 881                                   uint8_t stat_idx,
 882                                   uint8_t is_rx)
 883 {
 884 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 885 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 886 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 887
 888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 889         struct ixgbe_stat_mapping_registers *stat_mappings =
 890                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 891         uint32_t qsmr_mask = 0;
 892         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 893         uint32_t q_map;
 894         uint8_t n, offset;
 895
 896         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 897                 (hw->mac.type != ixgbe_mac_X540) &&
 898                 (hw->mac.type != ixgbe_mac_X550) &&
 899                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 900                 (hw->mac.type != ixgbe_mac_X550EM_a))
 901                 return -ENOSYS;
 902
 903         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 904                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 905                      queue_id, stat_idx);
 906
 907         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 908         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 909                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 910                 return -EIO;
 911         }
 912         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 913
 914         /* Now clear any previous stat_idx set */
 915         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 916         if (!is_rx)
 917                 stat_mappings->tqsm[n] &= ~clearing_mask;
 918         else
 919                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 920
 921         q_map = (uint32_t)stat_idx;
 922         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 923         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 924         if (!is_rx)
 925                 stat_mappings->tqsm[n] |= qsmr_mask;
 926         else
 927                 stat_mappings->rqsmr[n] |= qsmr_mask;
 928
 929         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 930                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 931                      queue_id, stat_idx);
 932         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 933                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 934
 935         /* Now write the mapping in the appropriate register */
 936         if (is_rx) {
 937                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 938                              stat_mappings->rqsmr[n], n);
 939                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 940         } else {
 941                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 942                              stat_mappings->tqsm[n], n);
 943                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 944         }
 945         return 0;
 946 }
 947
 948 static void
 949 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 950 {
 951         struct ixgbe_stat_mapping_registers *stat_mappings =
 952                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 954         int i;
 955
 956         /* write whatever was in stat mapping table to the NIC */
 957         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 958                 /* rx */
 959                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 960
 961                 /* tx */
 962                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 963         }
 964 }
 965
 966 static void
 967 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 968 {
 969         uint8_t i;
 970         struct ixgbe_dcb_tc_config *tc;
 971         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 972
 973         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 974         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 975         for (i = 0; i < dcb_max_tc; i++) {
 976                 tc = &dcb_config->tc_config[i];
 977                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 978                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 979                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 980                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 981                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 982                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 983                 tc->pfc = ixgbe_dcb_pfc_disabled;
 984         }
 985
 986         /* Initialize default user to priority mapping, UPx->TC0 */
 987         tc = &dcb_config->tc_config[0];
 988         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 989         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 990         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 991                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 992                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 993         }
 994         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 995         dcb_config->pfc_mode_enable = false;
 996         dcb_config->vt_mode = true;
 997         dcb_config->round_robin_enable = false;
 998         /* support all DCB capabilities in 82599 */
 999         dcb_config->support.capabilities = 0xFF;
1000
1001         /*we only support 4 Tcs for X540, X550 */
1002         if (hw->mac.type == ixgbe_mac_X540 ||
1003                 hw->mac.type == ixgbe_mac_X550 ||
1004                 hw->mac.type == ixgbe_mac_X550EM_x ||
1005                 hw->mac.type == ixgbe_mac_X550EM_a) {
1006                 dcb_config->num_tcs.pg_tcs = 4;
1007                 dcb_config->num_tcs.pfc_tcs = 4;
1008         }
1009 }
1010
1011 /*
1012  * Ensure that all locks are released before first NVM or PHY access
1013  */
1014 static void
1015 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1016 {
1017         uint16_t mask;
1018
1019         /*
1020          * Phy lock should not fail in this early stage. If this is the case,
1021          * it is due to an improper exit of the application.
1022          * So force the release of the faulty lock. Release of common lock
1023          * is done automatically by swfw_sync function.
1024          */
1025         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1026         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1027                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1028         }
1029         ixgbe_release_swfw_semaphore(hw, mask);
1030
1031         /*
1032          * These ones are more tricky since they are common to all ports; but
1033          * swfw_sync retries last long enough (1s) to be almost sure that if
1034          * lock can not be taken it is due to an improper lock of the
1035          * semaphore.
1036          */
1037         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1038         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1040         }
1041         ixgbe_release_swfw_semaphore(hw, mask);
1042 }
1043
1044 static void
1045 ixgbe_parse_devargs(struct ixgbe_adapter *adapter,
1046                       struct rte_devargs *devargs)
1047 {
1048         struct rte_kvargs *kvlist;
1049         uint16_t sdp3_no_tx_disable;
1050
1051         if (devargs == NULL)
1052                 return;
1053
1054         kvlist = rte_kvargs_parse(devargs->args, ixgbe_valid_arguments);
1055         if (kvlist == NULL)
1056                 return;
1057
1058         if (rte_kvargs_count(kvlist, IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE) == 1 &&
1059             rte_kvargs_process(kvlist, IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE,
1060                                devarg_handle_int, &sdp3_no_tx_disable) == 0 &&
1061             sdp3_no_tx_disable == 1)
1062                 adapter->sdp3_no_tx_disable = 1;
1063
1064         rte_kvargs_free(kvlist);
1065 }
1066
1067 /*
1068  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1069  * It returns 0 on success.
1070  */
1071 static int
1072 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1073 {
1074         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1075         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1076         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1077         struct ixgbe_hw *hw =
1078                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1079         struct ixgbe_vfta *shadow_vfta =
1080                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1081         struct ixgbe_hwstrip *hwstrip =
1082                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1083         struct ixgbe_dcb_config *dcb_config =
1084                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1085         struct ixgbe_filter_info *filter_info =
1086                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1087         struct ixgbe_bw_conf *bw_conf =
1088                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1089         uint32_t ctrl_ext;
1090         uint16_t csum;
1091         int diag, i, ret;
1092
1093         PMD_INIT_FUNC_TRACE();
1094
1095         ixgbe_dev_macsec_setting_reset(eth_dev);
1096
1097         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1098         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1099         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1100         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1101         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1102         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1103         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1104
1105         /*
1106          * For secondary processes, we don't initialise any further as primary
1107          * has already done this work. Only check we don't need a different
1108          * RX and TX function.
1109          */
1110         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1111                 struct ixgbe_tx_queue *txq;
1112                 /* TX queue function in primary, set by last queue initialized
1113                  * Tx queue may not initialized by primary process
1114                  */
1115                 if (eth_dev->data->tx_queues) {
1116                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1117                         ixgbe_set_tx_function(eth_dev, txq);
1118                 } else {
1119                         /* Use default TX function if we get here */
1120                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1121                                      "Using default TX function.");
1122                 }
1123
1124                 ixgbe_set_rx_function(eth_dev);
1125
1126                 return 0;
1127         }
1128
1129         rte_atomic32_clear(&ad->link_thread_running);
1130         ixgbe_parse_devargs(eth_dev->data->dev_private,
1131                             pci_dev->device.devargs);
1132         rte_eth_copy_pci_info(eth_dev, pci_dev);
1133         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1134
1135         /* Vendor and Device ID need to be set before init of shared code */
1136         hw->device_id = pci_dev->id.device_id;
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1139         hw->allow_unsupported_sfp = 1;
1140
1141         /* Initialize the shared code (base driver) */
1142 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1143         diag = ixgbe_bypass_init_shared_code(hw);
1144 #else
1145         diag = ixgbe_init_shared_code(hw);
1146 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1147
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1150                 return -EIO;
1151         }
1152
1153         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1154                 PMD_INIT_LOG(ERR, "\nERROR: "
1155                         "Firmware recovery mode detected. Limiting functionality.\n"
1156                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1157                         "User Guide for details on firmware recovery mode.");
1158                 return -EIO;
1159         }
1160
1161         /* pick up the PCI bus settings for reporting later */
1162         ixgbe_get_bus_info(hw);
1163
1164         /* Unlock any pending hardware semaphore */
1165         ixgbe_swfw_lock_reset(hw);
1166
1167 #ifdef RTE_LIB_SECURITY
1168         /* Initialize security_ctx only for primary process*/
1169         if (ixgbe_ipsec_ctx_create(eth_dev))
1170                 return -ENOMEM;
1171 #endif
1172
1173         /* Initialize DCB configuration*/
1174         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1175         ixgbe_dcb_init(hw, dcb_config);
1176         /* Get Hardware Flow Control setting */
1177         hw->fc.requested_mode = ixgbe_fc_none;
1178         hw->fc.current_mode = ixgbe_fc_none;
1179         hw->fc.pause_time = IXGBE_FC_PAUSE;
1180         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1181                 hw->fc.low_water[i] = IXGBE_FC_LO;
1182                 hw->fc.high_water[i] = IXGBE_FC_HI;
1183         }
1184         hw->fc.send_xon = 1;
1185
1186         /* Make sure we have a good EEPROM before we read from it */
1187         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1188         if (diag != IXGBE_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1190                 return -EIO;
1191         }
1192
1193 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1194         diag = ixgbe_bypass_init_hw(hw);
1195 #else
1196         diag = ixgbe_init_hw(hw);
1197 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1198
1199         /*
1200          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1201          * is called too soon after the kernel driver unbinding/binding occurs.
1202          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1203          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1204          * also called. See ixgbe_identify_phy_82599(). The reason for the
1205          * failure is not known, and only occuts when virtualisation features
1206          * are disabled in the bios. A delay of 100ms  was found to be enough by
1207          * trial-and-error, and is doubled to be safe.
1208          */
1209         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1210                 rte_delay_ms(200);
1211                 diag = ixgbe_init_hw(hw);
1212         }
1213
1214         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1215                 diag = IXGBE_SUCCESS;
1216
1217         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1218                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1219                              "LOM.  Please be aware there may be issues associated "
1220                              "with your hardware.");
1221                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1222                              "please contact your Intel or hardware representative "
1223                              "who provided you with this hardware.");
1224         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1225                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1226         if (diag) {
1227                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1228                 return -EIO;
1229         }
1230
1231         /* Reset the hw statistics */
1232         ixgbe_dev_stats_reset(eth_dev);
1233
1234         /* disable interrupt */
1235         ixgbe_disable_intr(hw);
1236
1237         /* reset mappings for queue statistics hw counters*/
1238         ixgbe_reset_qstat_mappings(hw);
1239
1240         /* Allocate memory for storing MAC addresses */
1241         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1242                                                hw->mac.num_rar_entries, 0);
1243         if (eth_dev->data->mac_addrs == NULL) {
1244                 PMD_INIT_LOG(ERR,
1245                              "Failed to allocate %u bytes needed to store "
1246                              "MAC addresses",
1247                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1248                 return -ENOMEM;
1249         }
1250         /* Copy the permanent MAC address */
1251         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1252                         &eth_dev->data->mac_addrs[0]);
1253
1254         /* Allocate memory for storing hash filter MAC addresses */
1255         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1256                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1257         if (eth_dev->data->hash_mac_addrs == NULL) {
1258                 PMD_INIT_LOG(ERR,
1259                              "Failed to allocate %d bytes needed to store MAC addresses",
1260                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1261                 rte_free(eth_dev->data->mac_addrs);
1262                 eth_dev->data->mac_addrs = NULL;
1263                 return -ENOMEM;
1264         }
1265
1266         /* initialize the vfta */
1267         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1268
1269         /* initialize the hw strip bitmap*/
1270         memset(hwstrip, 0, sizeof(*hwstrip));
1271
1272         /* initialize PF if max_vfs not zero */
1273         ret = ixgbe_pf_host_init(eth_dev);
1274         if (ret)
1275                 goto err_pf_host_init;
1276
1277         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1278         /* let hardware know driver is loaded */
1279         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1280         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1281         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1282         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1283         IXGBE_WRITE_FLUSH(hw);
1284
1285         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1286                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1287                              (int) hw->mac.type, (int) hw->phy.type,
1288                              (int) hw->phy.sfp_type);
1289         else
1290                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1291                              (int) hw->mac.type, (int) hw->phy.type);
1292
1293         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1294                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1295                      pci_dev->id.device_id);
1296
1297         rte_intr_callback_register(intr_handle,
1298                                    ixgbe_dev_interrupt_handler, eth_dev);
1299
1300         /* enable uio/vfio intr/eventfd mapping */
1301         rte_intr_enable(intr_handle);
1302
1303         /* enable support intr */
1304         ixgbe_enable_intr(eth_dev);
1305
1306         /* initialize filter info */
1307         memset(filter_info, 0,
1308                sizeof(struct ixgbe_filter_info));
1309
1310         /* initialize 5tuple filter list */
1311         TAILQ_INIT(&filter_info->fivetuple_list);
1312
1313         /* initialize flow director filter list & hash */
1314         ret = ixgbe_fdir_filter_init(eth_dev);
1315         if (ret)
1316                 goto err_fdir_filter_init;
1317
1318         /* initialize l2 tunnel filter list & hash */
1319         ret = ixgbe_l2_tn_filter_init(eth_dev);
1320         if (ret)
1321                 goto err_l2_tn_filter_init;
1322
1323         /* initialize flow filter lists */
1324         ixgbe_filterlist_init();
1325
1326         /* initialize bandwidth configuration info */
1327         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1328
1329         /* initialize Traffic Manager configuration */
1330         ixgbe_tm_conf_init(eth_dev);
1331
1332         return 0;
1333
1334 err_l2_tn_filter_init:
1335         ixgbe_fdir_filter_uninit(eth_dev);
1336 err_fdir_filter_init:
1337         ixgbe_disable_intr(hw);
1338         rte_intr_disable(intr_handle);
1339         rte_intr_callback_unregister(intr_handle,
1340                 ixgbe_dev_interrupt_handler, eth_dev);
1341         ixgbe_pf_host_uninit(eth_dev);
1342 err_pf_host_init:
1343         rte_free(eth_dev->data->mac_addrs);
1344         eth_dev->data->mac_addrs = NULL;
1345         rte_free(eth_dev->data->hash_mac_addrs);
1346         eth_dev->data->hash_mac_addrs = NULL;
1347         return ret;
1348 }
1349
1350 static int
1351 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1352 {
1353         PMD_INIT_FUNC_TRACE();
1354
1355         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1356                 return 0;
1357
1358         ixgbe_dev_close(eth_dev);
1359
1360         return 0;
1361 }
1362
1363 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1364 {
1365         struct ixgbe_filter_info *filter_info =
1366                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1367         struct ixgbe_5tuple_filter *p_5tuple;
1368
1369         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1370                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1371                              p_5tuple,
1372                              entries);
1373                 rte_free(p_5tuple);
1374         }
1375         memset(filter_info->fivetuple_mask, 0,
1376                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1377
1378         return 0;
1379 }
1380
1381 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1382 {
1383         struct ixgbe_hw_fdir_info *fdir_info =
1384                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1385         struct ixgbe_fdir_filter *fdir_filter;
1386
1387         rte_free(fdir_info->hash_map);
1388         rte_hash_free(fdir_info->hash_handle);
1389
1390         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1391                 TAILQ_REMOVE(&fdir_info->fdir_list,
1392                              fdir_filter,
1393                              entries);
1394                 rte_free(fdir_filter);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1401 {
1402         struct ixgbe_l2_tn_info *l2_tn_info =
1403                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1404         struct ixgbe_l2_tn_filter *l2_tn_filter;
1405
1406         rte_free(l2_tn_info->hash_map);
1407         rte_hash_free(l2_tn_info->hash_handle);
1408
1409         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1410                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1411                              l2_tn_filter,
1412                              entries);
1413                 rte_free(l2_tn_filter);
1414         }
1415
1416         return 0;
1417 }
1418
1419 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1420 {
1421         struct ixgbe_hw_fdir_info *fdir_info =
1422                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1423         char fdir_hash_name[RTE_HASH_NAMESIZE];
1424         struct rte_hash_parameters fdir_hash_params = {
1425                 .name = fdir_hash_name,
1426                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1427                 .key_len = sizeof(union ixgbe_atr_input),
1428                 .hash_func = rte_hash_crc,
1429                 .hash_func_init_val = 0,
1430                 .socket_id = rte_socket_id(),
1431         };
1432
1433         TAILQ_INIT(&fdir_info->fdir_list);
1434         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1435                  "fdir_%s", eth_dev->device->name);
1436         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1437         if (!fdir_info->hash_handle) {
1438                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1439                 return -EINVAL;
1440         }
1441         fdir_info->hash_map = rte_zmalloc("ixgbe",
1442                                           sizeof(struct ixgbe_fdir_filter *) *
1443                                           IXGBE_MAX_FDIR_FILTER_NUM,
1444                                           0);
1445         if (!fdir_info->hash_map) {
1446                 PMD_INIT_LOG(ERR,
1447                              "Failed to allocate memory for fdir hash map!");
1448                 rte_hash_free(fdir_info->hash_handle);
1449                 return -ENOMEM;
1450         }
1451         fdir_info->mask_added = FALSE;
1452
1453         return 0;
1454 }
1455
1456 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1457 {
1458         struct ixgbe_l2_tn_info *l2_tn_info =
1459                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1460         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1461         struct rte_hash_parameters l2_tn_hash_params = {
1462                 .name = l2_tn_hash_name,
1463                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1464                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1465                 .hash_func = rte_hash_crc,
1466                 .hash_func_init_val = 0,
1467                 .socket_id = rte_socket_id(),
1468         };
1469
1470         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1471         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1472                  "l2_tn_%s", eth_dev->device->name);
1473         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1474         if (!l2_tn_info->hash_handle) {
1475                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1476                 return -EINVAL;
1477         }
1478         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1479                                    sizeof(struct ixgbe_l2_tn_filter *) *
1480                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1481                                    0);
1482         if (!l2_tn_info->hash_map) {
1483                 PMD_INIT_LOG(ERR,
1484                         "Failed to allocate memory for L2 TN hash map!");
1485                 rte_hash_free(l2_tn_info->hash_handle);
1486                 return -ENOMEM;
1487         }
1488         l2_tn_info->e_tag_en = FALSE;
1489         l2_tn_info->e_tag_fwd_en = FALSE;
1490         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1491
1492         return 0;
1493 }
1494 /*
1495  * Negotiate mailbox API version with the PF.
1496  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1497  * Then we try to negotiate starting with the most recent one.
1498  * If all negotiation attempts fail, then we will proceed with
1499  * the default one (ixgbe_mbox_api_10).
1500  */
1501 static void
1502 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1503 {
1504         int32_t i;
1505
1506         /* start with highest supported, proceed down */
1507         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1508                 ixgbe_mbox_api_13,
1509                 ixgbe_mbox_api_12,
1510                 ixgbe_mbox_api_11,
1511                 ixgbe_mbox_api_10,
1512         };
1513
1514         for (i = 0;
1515                         i != RTE_DIM(sup_ver) &&
1516                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1517                         i++)
1518                 ;
1519 }
1520
1521 static void
1522 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1523 {
1524         uint64_t random;
1525
1526         /* Set Organizationally Unique Identifier (OUI) prefix. */
1527         mac_addr->addr_bytes[0] = 0x00;
1528         mac_addr->addr_bytes[1] = 0x09;
1529         mac_addr->addr_bytes[2] = 0xC0;
1530         /* Force indication of locally assigned MAC address. */
1531         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1532         /* Generate the last 3 bytes of the MAC address with a random number. */
1533         random = rte_rand();
1534         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1535 }
1536
1537 static int
1538 devarg_handle_int(__rte_unused const char *key, const char *value,
1539                   void *extra_args)
1540 {
1541         uint16_t *n = extra_args;
1542
1543         if (value == NULL || extra_args == NULL)
1544                 return -EINVAL;
1545
1546         *n = (uint16_t)strtoul(value, NULL, 0);
1547         if (*n == USHRT_MAX && errno == ERANGE)
1548                 return -1;
1549
1550         return 0;
1551 }
1552
1553 static void
1554 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1555                       struct rte_devargs *devargs)
1556 {
1557         struct rte_kvargs *kvlist;
1558         uint16_t pflink_fullchk;
1559
1560         if (devargs == NULL)
1561                 return;
1562
1563         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1564         if (kvlist == NULL)
1565                 return;
1566
1567         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1568             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1569                                devarg_handle_int, &pflink_fullchk) == 0 &&
1570             pflink_fullchk == 1)
1571                 adapter->pflink_fullchk = 1;
1572
1573         rte_kvargs_free(kvlist);
1574 }
1575
1576 /*
1577  * Virtual Function device init
1578  */
1579 static int
1580 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1581 {
1582         int diag;
1583         uint32_t tc, tcs;
1584         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1585         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1586         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1587         struct ixgbe_hw *hw =
1588                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1589         struct ixgbe_vfta *shadow_vfta =
1590                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1591         struct ixgbe_hwstrip *hwstrip =
1592                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1593         struct rte_ether_addr *perm_addr =
1594                 (struct rte_ether_addr *)hw->mac.perm_addr;
1595
1596         PMD_INIT_FUNC_TRACE();
1597
1598         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1599         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1600         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1601         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1602         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1603
1604         /* for secondary processes, we don't initialise any further as primary
1605          * has already done this work. Only check we don't need a different
1606          * RX function
1607          */
1608         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1609                 struct ixgbe_tx_queue *txq;
1610                 /* TX queue function in primary, set by last queue initialized
1611                  * Tx queue may not initialized by primary process
1612                  */
1613                 if (eth_dev->data->tx_queues) {
1614                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1615                         ixgbe_set_tx_function(eth_dev, txq);
1616                 } else {
1617                         /* Use default TX function if we get here */
1618                         PMD_INIT_LOG(NOTICE,
1619                                      "No TX queues configured yet. Using default TX function.");
1620                 }
1621
1622                 ixgbe_set_rx_function(eth_dev);
1623
1624                 return 0;
1625         }
1626
1627         rte_atomic32_clear(&ad->link_thread_running);
1628         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1629                               pci_dev->device.devargs);
1630
1631         rte_eth_copy_pci_info(eth_dev, pci_dev);
1632         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1633
1634         hw->device_id = pci_dev->id.device_id;
1635         hw->vendor_id = pci_dev->id.vendor_id;
1636         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1637
1638         /* initialize the vfta */
1639         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1640
1641         /* initialize the hw strip bitmap*/
1642         memset(hwstrip, 0, sizeof(*hwstrip));
1643
1644         /* Initialize the shared code (base driver) */
1645         diag = ixgbe_init_shared_code(hw);
1646         if (diag != IXGBE_SUCCESS) {
1647                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1648                 return -EIO;
1649         }
1650
1651         /* init_mailbox_params */
1652         hw->mbx.ops.init_params(hw);
1653
1654         /* Reset the hw statistics */
1655         ixgbevf_dev_stats_reset(eth_dev);
1656
1657         /* Disable the interrupts for VF */
1658         ixgbevf_intr_disable(eth_dev);
1659
1660         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1661         diag = hw->mac.ops.reset_hw(hw);
1662
1663         /*
1664          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1665          * the underlying PF driver has not assigned a MAC address to the VF.
1666          * In this case, assign a random MAC address.
1667          */
1668         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1669                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1670                 /*
1671                  * This error code will be propagated to the app by
1672                  * rte_eth_dev_reset, so use a public error code rather than
1673                  * the internal-only IXGBE_ERR_RESET_FAILED
1674                  */
1675                 return -EAGAIN;
1676         }
1677
1678         /* negotiate mailbox API version to use with the PF. */
1679         ixgbevf_negotiate_api(hw);
1680
1681         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1682         ixgbevf_get_queues(hw, &tcs, &tc);
1683
1684         /* Allocate memory for storing MAC addresses */
1685         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1686                                                hw->mac.num_rar_entries, 0);
1687         if (eth_dev->data->mac_addrs == NULL) {
1688                 PMD_INIT_LOG(ERR,
1689                              "Failed to allocate %u bytes needed to store "
1690                              "MAC addresses",
1691                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1692                 return -ENOMEM;
1693         }
1694
1695         /* Generate a random MAC address, if none was assigned by PF. */
1696         if (rte_is_zero_ether_addr(perm_addr)) {
1697                 generate_random_mac_addr(perm_addr);
1698                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1699                 if (diag) {
1700                         rte_free(eth_dev->data->mac_addrs);
1701                         eth_dev->data->mac_addrs = NULL;
1702                         return diag;
1703                 }
1704                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1705                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1706                              RTE_ETHER_ADDR_PRT_FMT,
1707                                  RTE_ETHER_ADDR_BYTES(perm_addr));
1708         }
1709
1710         /* Copy the permanent MAC address */
1711         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1712
1713         /* reset the hardware with the new settings */
1714         diag = hw->mac.ops.start_hw(hw);
1715         switch (diag) {
1716         case  0:
1717                 break;
1718
1719         default:
1720                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1721                 rte_free(eth_dev->data->mac_addrs);
1722                 eth_dev->data->mac_addrs = NULL;
1723                 return -EIO;
1724         }
1725
1726         rte_intr_callback_register(intr_handle,
1727                                    ixgbevf_dev_interrupt_handler, eth_dev);
1728         rte_intr_enable(intr_handle);
1729         ixgbevf_intr_enable(eth_dev);
1730
1731         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1732                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1733                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1734
1735         return 0;
1736 }
1737
1738 /* Virtual Function device uninit */
1739
1740 static int
1741 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1742 {
1743         PMD_INIT_FUNC_TRACE();
1744
1745         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1746                 return 0;
1747
1748         ixgbevf_dev_close(eth_dev);
1749
1750         return 0;
1751 }
1752
1753 static int
1754 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1755                 struct rte_pci_device *pci_dev)
1756 {
1757         char name[RTE_ETH_NAME_MAX_LEN];
1758         struct rte_eth_dev *pf_ethdev;
1759         struct rte_eth_devargs eth_da;
1760         int i, retval;
1761
1762         if (pci_dev->device.devargs) {
1763                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1764                                 &eth_da);
1765                 if (retval)
1766                         return retval;
1767         } else
1768                 memset(&eth_da, 0, sizeof(eth_da));
1769
1770         if (eth_da.nb_representor_ports > 0 &&
1771             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
1772                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
1773                             pci_dev->device.devargs->args);
1774                 return -ENOTSUP;
1775         }
1776
1777         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1778                 sizeof(struct ixgbe_adapter),
1779                 eth_dev_pci_specific_init, pci_dev,
1780                 eth_ixgbe_dev_init, NULL);
1781
1782         if (retval || eth_da.nb_representor_ports < 1)
1783                 return retval;
1784
1785         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1786         if (pf_ethdev == NULL)
1787                 return -ENODEV;
1788
1789         /* probe VF representor ports */
1790         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1791                 struct ixgbe_vf_info *vfinfo;
1792                 struct ixgbe_vf_representor representor;
1793
1794                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1795                         pf_ethdev->data->dev_private);
1796                 if (vfinfo == NULL) {
1797                         PMD_DRV_LOG(ERR,
1798                                 "no virtual functions supported by PF");
1799                         break;
1800                 }
1801
1802                 representor.vf_id = eth_da.representor_ports[i];
1803                 representor.switch_domain_id = vfinfo->switch_domain_id;
1804                 representor.pf_ethdev = pf_ethdev;
1805
1806                 /* representor port net_bdf_port */
1807                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1808                         pci_dev->device.name,
1809                         eth_da.representor_ports[i]);
1810
1811                 retval = rte_eth_dev_create(&pci_dev->device, name,
1812                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1813                         ixgbe_vf_representor_init, &representor);
1814
1815                 if (retval)
1816                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1817                                 "representor %s.", name);
1818         }
1819
1820         return 0;
1821 }
1822
1823 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1824 {
1825         struct rte_eth_dev *ethdev;
1826
1827         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1828         if (!ethdev)
1829                 return 0;
1830
1831         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1832                 return rte_eth_dev_pci_generic_remove(pci_dev,
1833                                         ixgbe_vf_representor_uninit);
1834         else
1835                 return rte_eth_dev_pci_generic_remove(pci_dev,
1836                                                 eth_ixgbe_dev_uninit);
1837 }
1838
1839 static struct rte_pci_driver rte_ixgbe_pmd = {
1840         .id_table = pci_id_ixgbe_map,
1841         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1842         .probe = eth_ixgbe_pci_probe,
1843         .remove = eth_ixgbe_pci_remove,
1844 };
1845
1846 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1847         struct rte_pci_device *pci_dev)
1848 {
1849         return rte_eth_dev_pci_generic_probe(pci_dev,
1850                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1851 }
1852
1853 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1854 {
1855         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1856 }
1857
1858 /*
1859  * virtual function driver struct
1860  */
1861 static struct rte_pci_driver rte_ixgbevf_pmd = {
1862         .id_table = pci_id_ixgbevf_map,
1863         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1864         .probe = eth_ixgbevf_pci_probe,
1865         .remove = eth_ixgbevf_pci_remove,
1866 };
1867
1868 static int
1869 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1870 {
1871         struct ixgbe_hw *hw =
1872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         struct ixgbe_vfta *shadow_vfta =
1874                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1875         uint32_t vfta;
1876         uint32_t vid_idx;
1877         uint32_t vid_bit;
1878
1879         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1880         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1881         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1882         if (on)
1883                 vfta |= vid_bit;
1884         else
1885                 vfta &= ~vid_bit;
1886         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1887
1888         /* update local VFTA copy */
1889         shadow_vfta->vfta[vid_idx] = vfta;
1890
1891         return 0;
1892 }
1893
1894 static void
1895 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1896 {
1897         if (on)
1898                 ixgbe_vlan_hw_strip_enable(dev, queue);
1899         else
1900                 ixgbe_vlan_hw_strip_disable(dev, queue);
1901 }
1902
1903 static int
1904 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1905                     enum rte_vlan_type vlan_type,
1906                     uint16_t tpid)
1907 {
1908         struct ixgbe_hw *hw =
1909                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         int ret = 0;
1911         uint32_t reg;
1912         uint32_t qinq;
1913
1914         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1915         qinq &= IXGBE_DMATXCTL_GDV;
1916
1917         switch (vlan_type) {
1918         case RTE_ETH_VLAN_TYPE_INNER:
1919                 if (qinq) {
1920                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1921                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1922                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1923                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1924                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1925                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1926                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1927                 } else {
1928                         ret = -ENOTSUP;
1929                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1930                                     " by single VLAN");
1931                 }
1932                 break;
1933         case RTE_ETH_VLAN_TYPE_OUTER:
1934                 if (qinq) {
1935                         /* Only the high 16-bits is valid */
1936                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1937                                         IXGBE_EXVET_VET_EXT_SHIFT);
1938                 } else {
1939                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1940                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1941                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1942                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1943                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1944                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1945                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1946                 }
1947
1948                 break;
1949         default:
1950                 ret = -EINVAL;
1951                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1952                 break;
1953         }
1954
1955         return ret;
1956 }
1957
1958 void
1959 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1960 {
1961         struct ixgbe_hw *hw =
1962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1963         uint32_t vlnctrl;
1964
1965         PMD_INIT_FUNC_TRACE();
1966
1967         /* Filter Table Disable */
1968         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1969         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1970
1971         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1972 }
1973
1974 void
1975 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1976 {
1977         struct ixgbe_hw *hw =
1978                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979         struct ixgbe_vfta *shadow_vfta =
1980                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1981         uint32_t vlnctrl;
1982         uint16_t i;
1983
1984         PMD_INIT_FUNC_TRACE();
1985
1986         /* Filter Table Enable */
1987         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1988         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1989         vlnctrl |= IXGBE_VLNCTRL_VFE;
1990
1991         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1992
1993         /* write whatever is in local vfta copy */
1994         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1995                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1996 }
1997
1998 static void
1999 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
2000 {
2001         struct ixgbe_hwstrip *hwstrip =
2002                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
2003         struct ixgbe_rx_queue *rxq;
2004
2005         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
2006                 return;
2007
2008         if (on)
2009                 IXGBE_SET_HWSTRIP(hwstrip, queue);
2010         else
2011                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
2012
2013         if (queue >= dev->data->nb_rx_queues)
2014                 return;
2015
2016         rxq = dev->data->rx_queues[queue];
2017
2018         if (on) {
2019                 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
2020                 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2021         } else {
2022                 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN;
2023                 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2024         }
2025 }
2026
2027 static void
2028 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2029 {
2030         struct ixgbe_hw *hw =
2031                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032         uint32_t ctrl;
2033
2034         PMD_INIT_FUNC_TRACE();
2035
2036         if (hw->mac.type == ixgbe_mac_82598EB) {
2037                 /* No queue level support */
2038                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2039                 return;
2040         }
2041
2042         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2043         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2044         ctrl &= ~IXGBE_RXDCTL_VME;
2045         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2046
2047         /* record those setting for HW strip per queue */
2048         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2049 }
2050
2051 static void
2052 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2053 {
2054         struct ixgbe_hw *hw =
2055                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056         uint32_t ctrl;
2057
2058         PMD_INIT_FUNC_TRACE();
2059
2060         if (hw->mac.type == ixgbe_mac_82598EB) {
2061                 /* No queue level supported */
2062                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2063                 return;
2064         }
2065
2066         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2067         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2068         ctrl |= IXGBE_RXDCTL_VME;
2069         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2070
2071         /* record those setting for HW strip per queue */
2072         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2073 }
2074
2075 static void
2076 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2077 {
2078         struct ixgbe_hw *hw =
2079                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         uint32_t ctrl;
2081
2082         PMD_INIT_FUNC_TRACE();
2083
2084         /* DMATXCTRL: Geric Double VLAN Disable */
2085         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2086         ctrl &= ~IXGBE_DMATXCTL_GDV;
2087         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2088
2089         /* CTRL_EXT: Global Double VLAN Disable */
2090         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2091         ctrl &= ~IXGBE_EXTENDED_VLAN;
2092         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2093
2094 }
2095
2096 static void
2097 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2098 {
2099         struct ixgbe_hw *hw =
2100                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101         uint32_t ctrl;
2102
2103         PMD_INIT_FUNC_TRACE();
2104
2105         /* DMATXCTRL: Geric Double VLAN Enable */
2106         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2107         ctrl |= IXGBE_DMATXCTL_GDV;
2108         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2109
2110         /* CTRL_EXT: Global Double VLAN Enable */
2111         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2112         ctrl |= IXGBE_EXTENDED_VLAN;
2113         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2114
2115         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2116         if (hw->mac.type == ixgbe_mac_X550 ||
2117             hw->mac.type == ixgbe_mac_X550EM_x ||
2118             hw->mac.type == ixgbe_mac_X550EM_a) {
2119                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2120                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2121                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2122         }
2123
2124         /*
2125          * VET EXT field in the EXVET register = 0x8100 by default
2126          * So no need to change. Same to VT field of DMATXCTL register
2127          */
2128 }
2129
2130 void
2131 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2132 {
2133         struct ixgbe_hw *hw =
2134                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2135         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2136         uint32_t ctrl;
2137         uint16_t i;
2138         struct ixgbe_rx_queue *rxq;
2139         bool on;
2140
2141         PMD_INIT_FUNC_TRACE();
2142
2143         if (hw->mac.type == ixgbe_mac_82598EB) {
2144                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
2145                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2146                         ctrl |= IXGBE_VLNCTRL_VME;
2147                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2148                 } else {
2149                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2150                         ctrl &= ~IXGBE_VLNCTRL_VME;
2151                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2152                 }
2153         } else {
2154                 /*
2155                  * Other 10G NIC, the VLAN strip can be setup
2156                  * per queue in RXDCTL
2157                  */
2158                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                         rxq = dev->data->rx_queues[i];
2160                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2161                         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
2162                                 ctrl |= IXGBE_RXDCTL_VME;
2163                                 on = TRUE;
2164                         } else {
2165                                 ctrl &= ~IXGBE_RXDCTL_VME;
2166                                 on = FALSE;
2167                         }
2168                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2169
2170                         /* record those setting for HW strip per queue */
2171                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2172                 }
2173         }
2174 }
2175
2176 static void
2177 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2178 {
2179         uint16_t i;
2180         struct rte_eth_rxmode *rxmode;
2181         struct ixgbe_rx_queue *rxq;
2182
2183         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2184                 rxmode = &dev->data->dev_conf.rxmode;
2185                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
2186                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2187                                 rxq = dev->data->rx_queues[i];
2188                                 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2189                         }
2190                 else
2191                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2192                                 rxq = dev->data->rx_queues[i];
2193                                 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
2194                         }
2195         }
2196 }
2197
2198 static int
2199 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2200 {
2201         struct rte_eth_rxmode *rxmode;
2202         rxmode = &dev->data->dev_conf.rxmode;
2203
2204         if (mask & RTE_ETH_VLAN_STRIP_MASK)
2205                 ixgbe_vlan_hw_strip_config(dev);
2206
2207         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2208                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
2209                         ixgbe_vlan_hw_filter_enable(dev);
2210                 else
2211                         ixgbe_vlan_hw_filter_disable(dev);
2212         }
2213
2214         if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2215                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2216                         ixgbe_vlan_hw_extend_enable(dev);
2217                 else
2218                         ixgbe_vlan_hw_extend_disable(dev);
2219         }
2220
2221         return 0;
2222 }
2223
2224 static int
2225 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2226 {
2227         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2228
2229         ixgbe_vlan_offload_config(dev, mask);
2230
2231         return 0;
2232 }
2233
2234 static void
2235 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2236 {
2237         struct ixgbe_hw *hw =
2238                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2240         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2241
2242         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2243         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2244 }
2245
2246 static int
2247 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2248 {
2249         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2250
2251         switch (nb_rx_q) {
2252         case 1:
2253         case 2:
2254                 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_64_POOLS;
2255                 break;
2256         case 4:
2257                 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_32_POOLS;
2258                 break;
2259         default:
2260                 return -EINVAL;
2261         }
2262
2263         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2264                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2265         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2266                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2267         return 0;
2268 }
2269
2270 static int
2271 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2272 {
2273         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2274         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2275         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2276         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2277
2278         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2279                 /* check multi-queue mode */
2280                 switch (dev_conf->rxmode.mq_mode) {
2281                 case RTE_ETH_MQ_RX_VMDQ_DCB:
2282                         PMD_INIT_LOG(INFO, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2283                         break;
2284                 case RTE_ETH_MQ_RX_VMDQ_DCB_RSS:
2285                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2286                         PMD_INIT_LOG(ERR, "SRIOV active,"
2287                                         " unsupported mq_mode rx %d.",
2288                                         dev_conf->rxmode.mq_mode);
2289                         return -EINVAL;
2290                 case RTE_ETH_MQ_RX_RSS:
2291                 case RTE_ETH_MQ_RX_VMDQ_RSS:
2292                         dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_RSS;
2293                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2294                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2295                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2296                                                 " invalid queue number"
2297                                                 " for VMDQ RSS, allowed"
2298                                                 " value are 1, 2 or 4.");
2299                                         return -EINVAL;
2300                                 }
2301                         break;
2302                 case RTE_ETH_MQ_RX_VMDQ_ONLY:
2303                 case RTE_ETH_MQ_RX_NONE:
2304                         /* if nothing mq mode configure, use default scheme */
2305                         dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_ONLY;
2306                         break;
2307                 default: /* RTE_ETH_MQ_RX_DCB, RTE_ETH_MQ_RX_DCB_RSS or RTE_ETH_MQ_TX_DCB*/
2308                         /* SRIOV only works in VMDq enable mode */
2309                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2310                                         " wrong mq_mode rx %d.",
2311                                         dev_conf->rxmode.mq_mode);
2312                         return -EINVAL;
2313                 }
2314
2315                 switch (dev_conf->txmode.mq_mode) {
2316                 case RTE_ETH_MQ_TX_VMDQ_DCB:
2317                         PMD_INIT_LOG(INFO, "RTE_ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2318                         dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_DCB;
2319                         break;
2320                 default: /* RTE_ETH_MQ_TX_VMDQ_ONLY or RTE_ETH_MQ_TX_NONE */
2321                         dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_ONLY;
2322                         break;
2323                 }
2324
2325                 /* check valid queue number */
2326                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2327                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2328                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2329                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2330                                         " must be less than or equal to %d.",
2331                                         nb_rx_q, nb_tx_q,
2332                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2333                         return -EINVAL;
2334                 }
2335         } else {
2336                 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB_RSS) {
2337                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2338                                           " not supported.");
2339                         return -EINVAL;
2340                 }
2341                 /* check configuration for vmdb+dcb mode */
2342                 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB) {
2343                         const struct rte_eth_vmdq_dcb_conf *conf;
2344
2345                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2346                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2347                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2348                                 return -EINVAL;
2349                         }
2350                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2351                         if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS ||
2352                                conf->nb_queue_pools == RTE_ETH_32_POOLS)) {
2353                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2354                                                 " nb_queue_pools must be %d or %d.",
2355                                                 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS);
2356                                 return -EINVAL;
2357                         }
2358                 }
2359                 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) {
2360                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2361
2362                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2363                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2364                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2365                                 return -EINVAL;
2366                         }
2367                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2368                         if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS ||
2369                                conf->nb_queue_pools == RTE_ETH_32_POOLS)) {
2370                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2371                                                 " nb_queue_pools != %d and"
2372                                                 " nb_queue_pools != %d.",
2373                                                 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS);
2374                                 return -EINVAL;
2375                         }
2376                 }
2377
2378                 /* For DCB mode check our configuration before we go further */
2379                 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_DCB) {
2380                         const struct rte_eth_dcb_rx_conf *conf;
2381
2382                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2383                         if (!(conf->nb_tcs == RTE_ETH_4_TCS ||
2384                                conf->nb_tcs == RTE_ETH_8_TCS)) {
2385                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2386                                                 " and nb_tcs != %d.",
2387                                                 RTE_ETH_4_TCS, RTE_ETH_8_TCS);
2388                                 return -EINVAL;
2389                         }
2390                 }
2391
2392                 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_DCB) {
2393                         const struct rte_eth_dcb_tx_conf *conf;
2394
2395                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2396                         if (!(conf->nb_tcs == RTE_ETH_4_TCS ||
2397                                conf->nb_tcs == RTE_ETH_8_TCS)) {
2398                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2399                                                 " and nb_tcs != %d.",
2400                                                 RTE_ETH_4_TCS, RTE_ETH_8_TCS);
2401                                 return -EINVAL;
2402                         }
2403                 }
2404
2405                 /*
2406                  * When DCB/VT is off, maximum number of queues changes,
2407                  * except for 82598EB, which remains constant.
2408                  */
2409                 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_NONE &&
2410                                 hw->mac.type != ixgbe_mac_82598EB) {
2411                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2412                                 PMD_INIT_LOG(ERR,
2413                                              "Neither VT nor DCB are enabled, "
2414                                              "nb_tx_q > %d.",
2415                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2416                                 return -EINVAL;
2417                         }
2418                 }
2419         }
2420         return 0;
2421 }
2422
2423 static int
2424 ixgbe_dev_configure(struct rte_eth_dev *dev)
2425 {
2426         struct ixgbe_interrupt *intr =
2427                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2428         struct ixgbe_adapter *adapter = dev->data->dev_private;
2429         int ret;
2430
2431         PMD_INIT_FUNC_TRACE();
2432
2433         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
2434                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
2435
2436         /* multiple queue mode checking */
2437         ret  = ixgbe_check_mq_mode(dev);
2438         if (ret != 0) {
2439                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2440                             ret);
2441                 return ret;
2442         }
2443
2444         /* set flag to update link status after init */
2445         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2446
2447         /*
2448          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2449          * allocation or vector Rx preconditions we will reset it.
2450          */
2451         adapter->rx_bulk_alloc_allowed = true;
2452         adapter->rx_vec_allowed = true;
2453
2454         return 0;
2455 }
2456
2457 static void
2458 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2459 {
2460         struct ixgbe_hw *hw =
2461                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         struct ixgbe_interrupt *intr =
2463                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2464         uint32_t gpie;
2465
2466         /* only set up it on X550EM_X */
2467         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2468                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2469                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2470                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2471                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2472                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2473         }
2474 }
2475
2476 int
2477 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2478                         uint16_t tx_rate, uint64_t q_msk)
2479 {
2480         struct ixgbe_hw *hw;
2481         struct ixgbe_vf_info *vfinfo;
2482         struct rte_eth_link link;
2483         uint8_t  nb_q_per_pool;
2484         uint32_t queue_stride;
2485         uint32_t queue_idx, idx = 0, vf_idx;
2486         uint32_t queue_end;
2487         uint16_t total_rate = 0;
2488         struct rte_pci_device *pci_dev;
2489         int ret;
2490
2491         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2492         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2493         if (ret < 0)
2494                 return ret;
2495
2496         if (vf >= pci_dev->max_vfs)
2497                 return -EINVAL;
2498
2499         if (tx_rate > link.link_speed)
2500                 return -EINVAL;
2501
2502         if (q_msk == 0)
2503                 return 0;
2504
2505         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2506         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2507         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2508         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2509         queue_idx = vf * queue_stride;
2510         queue_end = queue_idx + nb_q_per_pool - 1;
2511         if (queue_end >= hw->mac.max_tx_queues)
2512                 return -EINVAL;
2513
2514         if (vfinfo) {
2515                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2516                         if (vf_idx == vf)
2517                                 continue;
2518                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2519                                 idx++)
2520                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2521                 }
2522         } else {
2523                 return -EINVAL;
2524         }
2525
2526         /* Store tx_rate for this vf. */
2527         for (idx = 0; idx < nb_q_per_pool; idx++) {
2528                 if (((uint64_t)0x1 << idx) & q_msk) {
2529                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2530                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2531                         total_rate += tx_rate;
2532                 }
2533         }
2534
2535         if (total_rate > dev->data->dev_link.link_speed) {
2536                 /* Reset stored TX rate of the VF if it causes exceed
2537                  * link speed.
2538                  */
2539                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2540                 return -EINVAL;
2541         }
2542
2543         /* Set RTTBCNRC of each queue/pool for vf X  */
2544         for (; queue_idx <= queue_end; queue_idx++) {
2545                 if (0x1 & q_msk)
2546                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2547                 q_msk = q_msk >> 1;
2548         }
2549
2550         return 0;
2551 }
2552
2553 static int
2554 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2555 {
2556         struct ixgbe_adapter *adapter = dev->data->dev_private;
2557         int err;
2558         uint32_t mflcn;
2559
2560         ixgbe_setup_fc(hw);
2561
2562         err = ixgbe_fc_enable(hw);
2563
2564         /* Not negotiated is not an error case */
2565         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2566                 /*
2567                  *check if we want to forward MAC frames - driver doesn't
2568                  *have native capability to do that,
2569                  *so we'll write the registers ourselves
2570                  */
2571
2572                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2573
2574                 /* set or clear MFLCN.PMCF bit depending on configuration */
2575                 if (adapter->mac_ctrl_frame_fwd != 0)
2576                         mflcn |= IXGBE_MFLCN_PMCF;
2577                 else
2578                         mflcn &= ~IXGBE_MFLCN_PMCF;
2579
2580                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2581                 IXGBE_WRITE_FLUSH(hw);
2582
2583                 return 0;
2584         }
2585         return err;
2586 }
2587
2588 /*
2589  * Configure device link speed and setup link.
2590  * It returns 0 on success.
2591  */
2592 static int
2593 ixgbe_dev_start(struct rte_eth_dev *dev)
2594 {
2595         struct ixgbe_hw *hw =
2596                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2597         struct ixgbe_vf_info *vfinfo =
2598                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2599         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2600         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2601         uint32_t intr_vector = 0;
2602         int err;
2603         bool link_up = false, negotiate = 0;
2604         uint32_t speed = 0;
2605         uint32_t allowed_speeds = 0;
2606         int mask = 0;
2607         int status;
2608         uint16_t vf, idx;
2609         uint32_t *link_speeds;
2610         struct ixgbe_tm_conf *tm_conf =
2611                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2612         struct ixgbe_macsec_setting *macsec_setting =
2613                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2614
2615         PMD_INIT_FUNC_TRACE();
2616
2617         /* Stop the link setup handler before resetting the HW. */
2618         ixgbe_dev_wait_setup_link_complete(dev, 0);
2619
2620         /* disable uio/vfio intr/eventfd mapping */
2621         rte_intr_disable(intr_handle);
2622
2623         /* stop adapter */
2624         hw->adapter_stopped = 0;
2625         ixgbe_stop_adapter(hw);
2626
2627         /* reinitialize adapter
2628          * this calls reset and start
2629          */
2630         status = ixgbe_pf_reset_hw(hw);
2631         if (status != 0)
2632                 return -1;
2633         hw->mac.ops.start_hw(hw);
2634         hw->mac.get_link_status = true;
2635
2636         /* configure PF module if SRIOV enabled */
2637         ixgbe_pf_host_configure(dev);
2638
2639         ixgbe_dev_phy_intr_setup(dev);
2640
2641         /* check and configure queue intr-vector mapping */
2642         if ((rte_intr_cap_multiple(intr_handle) ||
2643              !RTE_ETH_DEV_SRIOV(dev).active) &&
2644             dev->data->dev_conf.intr_conf.rxq != 0) {
2645                 intr_vector = dev->data->nb_rx_queues;
2646                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2647                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2648                                         IXGBE_MAX_INTR_QUEUE_NUM);
2649                         return -ENOTSUP;
2650                 }
2651                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2652                         return -1;
2653         }
2654
2655         if (rte_intr_dp_is_en(intr_handle)) {
2656                 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2657                                                    dev->data->nb_rx_queues)) {
2658                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2659                                      " intr_vec", dev->data->nb_rx_queues);
2660                         return -ENOMEM;
2661                 }
2662         }
2663
2664         /* configure MSI-X for sleep until Rx interrupt */
2665         ixgbe_configure_msix(dev);
2666
2667         /* initialize transmission unit */
2668         ixgbe_dev_tx_init(dev);
2669
2670         /* This can fail when allocating mbufs for descriptor rings */
2671         err = ixgbe_dev_rx_init(dev);
2672         if (err) {
2673                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2674                 goto error;
2675         }
2676
2677         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
2678                 RTE_ETH_VLAN_EXTEND_MASK;
2679         err = ixgbe_vlan_offload_config(dev, mask);
2680         if (err) {
2681                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2682                 goto error;
2683         }
2684
2685         if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) {
2686                 /* Enable vlan filtering for VMDq */
2687                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2688         }
2689
2690         /* Configure DCB hw */
2691         ixgbe_configure_dcb(dev);
2692
2693         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2694                 err = ixgbe_fdir_configure(dev);
2695                 if (err)
2696                         goto error;
2697         }
2698
2699         /* Restore vf rate limit */
2700         if (vfinfo != NULL) {
2701                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2702                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2703                                 if (vfinfo[vf].tx_rate[idx] != 0)
2704                                         ixgbe_set_vf_rate_limit(
2705                                                 dev, vf,
2706                                                 vfinfo[vf].tx_rate[idx],
2707                                                 1 << idx);
2708         }
2709
2710         ixgbe_restore_statistics_mapping(dev);
2711
2712         err = ixgbe_flow_ctrl_enable(dev, hw);
2713         if (err < 0) {
2714                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2715                 goto error;
2716         }
2717
2718         err = ixgbe_dev_rxtx_start(dev);
2719         if (err < 0) {
2720                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2721                 goto error;
2722         }
2723
2724         /* Skip link setup if loopback mode is enabled. */
2725         if (dev->data->dev_conf.lpbk_mode != 0) {
2726                 err = ixgbe_check_supported_loopback_mode(dev);
2727                 if (err < 0) {
2728                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2729                         goto error;
2730                 } else {
2731                         goto skip_link_setup;
2732                 }
2733         }
2734
2735         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2736                 err = hw->mac.ops.setup_sfp(hw);
2737                 if (err)
2738                         goto error;
2739         }
2740
2741         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2742                 /* Turn on the copper */
2743                 ixgbe_set_phy_power(hw, true);
2744         } else {
2745                 /* Turn on the laser */
2746                 ixgbe_enable_tx_laser(hw);
2747         }
2748
2749         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2750         if (err)
2751                 goto error;
2752         dev->data->dev_link.link_status = link_up;
2753
2754         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2755         if (err)
2756                 goto error;
2757
2758         switch (hw->mac.type) {
2759         case ixgbe_mac_X550:
2760         case ixgbe_mac_X550EM_x:
2761         case ixgbe_mac_X550EM_a:
2762                 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
2763                         RTE_ETH_LINK_SPEED_2_5G |  RTE_ETH_LINK_SPEED_5G |
2764                         RTE_ETH_LINK_SPEED_10G;
2765                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2766                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2767                         allowed_speeds = RTE_ETH_LINK_SPEED_10M |
2768                                 RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G;
2769                 break;
2770         default:
2771                 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
2772                         RTE_ETH_LINK_SPEED_10G;
2773         }
2774
2775         link_speeds = &dev->data->dev_conf.link_speeds;
2776
2777         /* Ignore autoneg flag bit and check the validity of
2778          * link_speed
2779          */
2780         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2781                 PMD_INIT_LOG(ERR, "Invalid link setting");
2782                 goto error;
2783         }
2784
2785         speed = 0x0;
2786         if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
2787                 switch (hw->mac.type) {
2788                 case ixgbe_mac_82598EB:
2789                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2790                         break;
2791                 case ixgbe_mac_82599EB:
2792                 case ixgbe_mac_X540:
2793                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2794                         break;
2795                 case ixgbe_mac_X550:
2796                 case ixgbe_mac_X550EM_x:
2797                 case ixgbe_mac_X550EM_a:
2798                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2799                         break;
2800                 default:
2801                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2802                 }
2803         } else {
2804                 if (*link_speeds & RTE_ETH_LINK_SPEED_10G)
2805                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2806                 if (*link_speeds & RTE_ETH_LINK_SPEED_5G)
2807                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2808                 if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G)
2809                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2810                 if (*link_speeds & RTE_ETH_LINK_SPEED_1G)
2811                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2812                 if (*link_speeds & RTE_ETH_LINK_SPEED_100M)
2813                         speed |= IXGBE_LINK_SPEED_100_FULL;
2814                 if (*link_speeds & RTE_ETH_LINK_SPEED_10M)
2815                         speed |= IXGBE_LINK_SPEED_10_FULL;
2816         }
2817
2818         err = ixgbe_setup_link(hw, speed, link_up);
2819         if (err)
2820                 goto error;
2821
2822 skip_link_setup:
2823
2824         if (rte_intr_allow_others(intr_handle)) {
2825                 /* check if lsc interrupt is enabled */
2826                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2827                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2828                 else
2829                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2830                 ixgbe_dev_macsec_interrupt_setup(dev);
2831         } else {
2832                 rte_intr_callback_unregister(intr_handle,
2833                                              ixgbe_dev_interrupt_handler, dev);
2834                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2835                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2836                                      " no intr multiplex");
2837         }
2838
2839         /* check if rxq interrupt is enabled */
2840         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2841             rte_intr_dp_is_en(intr_handle))
2842                 ixgbe_dev_rxq_interrupt_setup(dev);
2843
2844         /* enable uio/vfio intr/eventfd mapping */
2845         rte_intr_enable(intr_handle);
2846
2847         /* resume enabled intr since hw reset */
2848         ixgbe_enable_intr(dev);
2849         ixgbe_l2_tunnel_conf(dev);
2850         ixgbe_filter_restore(dev);
2851
2852         if (tm_conf->root && !tm_conf->committed)
2853                 PMD_DRV_LOG(WARNING,
2854                             "please call hierarchy_commit() "
2855                             "before starting the port");
2856
2857         /* wait for the controller to acquire link */
2858         err = ixgbe_wait_for_link_up(hw);
2859         if (err)
2860                 goto error;
2861
2862         /*
2863          * Update link status right before return, because it may
2864          * start link configuration process in a separate thread.
2865          */
2866         ixgbe_dev_link_update(dev, 0);
2867
2868         /* setup the macsec setting register */
2869         if (macsec_setting->offload_en)
2870                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2871
2872         return 0;
2873
2874 error:
2875         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2876         ixgbe_dev_clear_queues(dev);
2877         return -EIO;
2878 }
2879
2880 /*
2881  * Stop device: disable rx and tx functions to allow for reconfiguring.
2882  */
2883 static int
2884 ixgbe_dev_stop(struct rte_eth_dev *dev)
2885 {
2886         struct rte_eth_link link;
2887         struct ixgbe_adapter *adapter = dev->data->dev_private;
2888         struct ixgbe_hw *hw =
2889                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         struct ixgbe_vf_info *vfinfo =
2891                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2892         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2893         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2894         int vf;
2895         struct ixgbe_tm_conf *tm_conf =
2896                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2897
2898         if (hw->adapter_stopped)
2899                 return 0;
2900
2901         PMD_INIT_FUNC_TRACE();
2902
2903         ixgbe_dev_wait_setup_link_complete(dev, 0);
2904
2905         /* disable interrupts */
2906         ixgbe_disable_intr(hw);
2907
2908         /* reset the NIC */
2909         ixgbe_pf_reset_hw(hw);
2910         hw->adapter_stopped = 0;
2911
2912         /* stop adapter */
2913         ixgbe_stop_adapter(hw);
2914
2915         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2916                 vfinfo[vf].clear_to_send = false;
2917
2918         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2919                 /* Turn off the copper */
2920                 ixgbe_set_phy_power(hw, false);
2921         } else {
2922                 /* Turn off the laser */
2923                 ixgbe_disable_tx_laser(hw);
2924         }
2925
2926         ixgbe_dev_clear_queues(dev);
2927
2928         /* Clear stored conf */
2929         dev->data->scattered_rx = 0;
2930         dev->data->lro = 0;
2931
2932         /* Clear recorded link status */
2933         memset(&link, 0, sizeof(link));
2934         rte_eth_linkstatus_set(dev, &link);
2935
2936         if (!rte_intr_allow_others(intr_handle))
2937                 /* resume to the default handler */
2938                 rte_intr_callback_register(intr_handle,
2939                                            ixgbe_dev_interrupt_handler,
2940                                            (void *)dev);
2941
2942         /* Clean datapath event and queue/vec mapping */
2943         rte_intr_efd_disable(intr_handle);
2944         rte_intr_vec_list_free(intr_handle);
2945
2946         /* reset hierarchy commit */
2947         tm_conf->committed = false;
2948
2949         adapter->rss_reta_updated = 0;
2950
2951         hw->adapter_stopped = true;
2952         dev->data->dev_started = 0;
2953
2954         return 0;
2955 }
2956
2957 /*
2958  * Set device link up: enable tx.
2959  */
2960 static int
2961 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2962 {
2963         struct ixgbe_hw *hw =
2964                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2965         if (hw->mac.type == ixgbe_mac_82599EB) {
2966 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2967                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2968                         /* Not supported in bypass mode */
2969                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2970                                      "by device id 0x%x", hw->device_id);
2971                         return -ENOTSUP;
2972                 }
2973 #endif
2974         }
2975
2976         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2977                 /* Turn on the copper */
2978                 ixgbe_set_phy_power(hw, true);
2979         } else {
2980                 /* Turn on the laser */
2981                 ixgbe_enable_tx_laser(hw);
2982                 ixgbe_dev_link_update(dev, 0);
2983         }
2984
2985         return 0;
2986 }
2987
2988 /*
2989  * Set device link down: disable tx.
2990  */
2991 static int
2992 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2993 {
2994         struct ixgbe_hw *hw =
2995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2996         if (hw->mac.type == ixgbe_mac_82599EB) {
2997 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2998                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2999                         /* Not supported in bypass mode */
3000                         PMD_INIT_LOG(ERR, "Set link down is not supported "
3001                                      "by device id 0x%x", hw->device_id);
3002                         return -ENOTSUP;
3003                 }
3004 #endif
3005         }
3006
3007         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
3008                 /* Turn off the copper */
3009                 ixgbe_set_phy_power(hw, false);
3010         } else {
3011                 /* Turn off the laser */
3012                 ixgbe_disable_tx_laser(hw);
3013                 ixgbe_dev_link_update(dev, 0);
3014         }
3015
3016         return 0;
3017 }
3018
3019 /*
3020  * Reset and stop device.
3021  */
3022 static int
3023 ixgbe_dev_close(struct rte_eth_dev *dev)
3024 {
3025         struct ixgbe_hw *hw =
3026                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3028         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3029         int retries = 0;
3030         int ret;
3031
3032         PMD_INIT_FUNC_TRACE();
3033         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3034                 return 0;
3035
3036         ixgbe_pf_reset_hw(hw);
3037
3038         ret = ixgbe_dev_stop(dev);
3039
3040         ixgbe_dev_free_queues(dev);
3041
3042         ixgbe_disable_pcie_master(hw);
3043
3044         /* reprogram the RAR[0] in case user changed it. */
3045         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3046
3047         /* Unlock any pending hardware semaphore */
3048         ixgbe_swfw_lock_reset(hw);
3049
3050         /* disable uio intr before callback unregister */
3051         rte_intr_disable(intr_handle);
3052
3053         do {
3054                 ret = rte_intr_callback_unregister(intr_handle,
3055                                 ixgbe_dev_interrupt_handler, dev);
3056                 if (ret >= 0 || ret == -ENOENT) {
3057                         break;
3058                 } else if (ret != -EAGAIN) {
3059                         PMD_INIT_LOG(ERR,
3060                                 "intr callback unregister failed: %d",
3061                                 ret);
3062                 }
3063                 rte_delay_ms(100);
3064         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3065
3066         /* cancel the delay handler before remove dev */
3067         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3068
3069         /* uninitialize PF if max_vfs not zero */
3070         ixgbe_pf_host_uninit(dev);
3071
3072         /* remove all the fdir filters & hash */
3073         ixgbe_fdir_filter_uninit(dev);
3074
3075         /* remove all the L2 tunnel filters & hash */
3076         ixgbe_l2_tn_filter_uninit(dev);
3077
3078         /* Remove all ntuple filters of the device */
3079         ixgbe_ntuple_filter_uninit(dev);
3080
3081         /* clear all the filters list */
3082         ixgbe_filterlist_flush();
3083
3084         /* Remove all Traffic Manager configuration */
3085         ixgbe_tm_conf_uninit(dev);
3086
3087 #ifdef RTE_LIB_SECURITY
3088         rte_free(dev->security_ctx);
3089         dev->security_ctx = NULL;
3090 #endif
3091
3092         return ret;
3093 }
3094
3095 /*
3096  * Reset PF device.
3097  */
3098 static int
3099 ixgbe_dev_reset(struct rte_eth_dev *dev)
3100 {
3101         int ret;
3102
3103         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3104          * its VF to make them align with it. The detailed notification
3105          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3106          * To avoid unexpected behavior in VF, currently reset of PF with
3107          * SR-IOV activation is not supported. It might be supported later.
3108          */
3109         if (dev->data->sriov.active)
3110                 return -ENOTSUP;
3111
3112         ret = eth_ixgbe_dev_uninit(dev);
3113         if (ret)
3114                 return ret;
3115
3116         ret = eth_ixgbe_dev_init(dev, NULL);
3117
3118         return ret;
3119 }
3120
3121 static void
3122 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3123                            struct ixgbe_hw_stats *hw_stats,
3124                            struct ixgbe_macsec_stats *macsec_stats,
3125                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3126                            uint64_t *total_qprc, uint64_t *total_qprdc)
3127 {
3128         uint32_t bprc, lxon, lxoff, total;
3129         uint32_t delta_gprc = 0;
3130         unsigned i;
3131         /* Workaround for RX byte count not including CRC bytes when CRC
3132          * strip is enabled. CRC bytes are removed from counters when crc_strip
3133          * is disabled.
3134          */
3135         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3136                         IXGBE_HLREG0_RXCRCSTRP);
3137
3138         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3139         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3140         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3141         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3142
3143         for (i = 0; i < 8; i++) {
3144                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3145
3146                 /* global total per queue */
3147                 hw_stats->mpc[i] += mp;
3148                 /* Running comprehensive total for stats display */
3149                 *total_missed_rx += hw_stats->mpc[i];
3150                 if (hw->mac.type == ixgbe_mac_82598EB) {
3151                         hw_stats->rnbc[i] +=
3152                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3153                         hw_stats->pxonrxc[i] +=
3154                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3155                         hw_stats->pxoffrxc[i] +=
3156                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3157                 } else {
3158                         hw_stats->pxonrxc[i] +=
3159                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3160                         hw_stats->pxoffrxc[i] +=
3161                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3162                         hw_stats->pxon2offc[i] +=
3163                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3164                 }
3165                 hw_stats->pxontxc[i] +=
3166                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3167                 hw_stats->pxofftxc[i] +=
3168                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3169         }
3170         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3171                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3172                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3173                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3174
3175                 delta_gprc += delta_qprc;
3176
3177                 hw_stats->qprc[i] += delta_qprc;
3178                 hw_stats->qptc[i] += delta_qptc;
3179
3180                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3181                 hw_stats->qbrc[i] +=
3182                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3183                 if (crc_strip == 0)
3184                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3185
3186                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3187                 hw_stats->qbtc[i] +=
3188                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3189
3190                 hw_stats->qprdc[i] += delta_qprdc;
3191                 *total_qprdc += hw_stats->qprdc[i];
3192
3193                 *total_qprc += hw_stats->qprc[i];
3194                 *total_qbrc += hw_stats->qbrc[i];
3195         }
3196         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3197         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3198         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3199
3200         /*
3201          * An errata states that gprc actually counts good + missed packets:
3202          * Workaround to set gprc to summated queue packet receives
3203          */
3204         hw_stats->gprc = *total_qprc;
3205
3206         if (hw->mac.type != ixgbe_mac_82598EB) {
3207                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3208                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3209                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3210                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3211                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3212                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3213                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3214                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3215         } else {
3216                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3217                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3218                 /* 82598 only has a counter in the high register */
3219                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3220                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3221                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3222         }
3223         uint64_t old_tpr = hw_stats->tpr;
3224
3225         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3226         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3227
3228         if (crc_strip == 0)
3229                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3230
3231         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3232         hw_stats->gptc += delta_gptc;
3233         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3234         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3235
3236         /*
3237          * Workaround: mprc hardware is incorrectly counting
3238          * broadcasts, so for now we subtract those.
3239          */
3240         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3241         hw_stats->bprc += bprc;
3242         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3243         if (hw->mac.type == ixgbe_mac_82598EB)
3244                 hw_stats->mprc -= bprc;
3245
3246         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3247         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3248         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3249         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3250         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3251         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3252
3253         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3254         hw_stats->lxontxc += lxon;
3255         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3256         hw_stats->lxofftxc += lxoff;
3257         total = lxon + lxoff;
3258
3259         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3260         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3261         hw_stats->gptc -= total;
3262         hw_stats->mptc -= total;
3263         hw_stats->ptc64 -= total;
3264         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3265
3266         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3267         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3268         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3269         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3270         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3271         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3272         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3273         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3274         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3275         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3276         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3277         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3278         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3279         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3280         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3281         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3282         /* Only read FCOE on 82599 */
3283         if (hw->mac.type != ixgbe_mac_82598EB) {
3284                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3285                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3286                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3287                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3288                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3289         }
3290
3291         /* Flow Director Stats registers */
3292         if (hw->mac.type != ixgbe_mac_82598EB) {
3293                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3294                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3295                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3296                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3297                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3298                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3299                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3300                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3301                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3302                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3303         }
3304         /* MACsec Stats registers */
3305         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3306         macsec_stats->out_pkts_encrypted +=
3307                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3308         macsec_stats->out_pkts_protected +=
3309                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3310         macsec_stats->out_octets_encrypted +=
3311                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3312         macsec_stats->out_octets_protected +=
3313                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3314         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3315         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3316         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3317         macsec_stats->in_pkts_unknownsci +=
3318                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3319         macsec_stats->in_octets_decrypted +=
3320                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3321         macsec_stats->in_octets_validated +=
3322                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3323         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3324         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3325         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3326         for (i = 0; i < 2; i++) {
3327                 macsec_stats->in_pkts_ok +=
3328                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3329                 macsec_stats->in_pkts_invalid +=
3330                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3331                 macsec_stats->in_pkts_notvalid +=
3332                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3333         }
3334         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3335         macsec_stats->in_pkts_notusingsa +=
3336                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3337 }
3338
3339 /*
3340  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3341  */
3342 static int
3343 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3344 {
3345         struct ixgbe_hw *hw =
3346                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347         struct ixgbe_hw_stats *hw_stats =
3348                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3349         struct ixgbe_macsec_stats *macsec_stats =
3350                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3351                                 dev->data->dev_private);
3352         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3353         unsigned i;
3354
3355         total_missed_rx = 0;
3356         total_qbrc = 0;
3357         total_qprc = 0;
3358         total_qprdc = 0;
3359
3360         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3361                         &total_qbrc, &total_qprc, &total_qprdc);
3362
3363         if (stats == NULL)
3364                 return -EINVAL;
3365
3366         /* Fill out the rte_eth_stats statistics structure */
3367         stats->ipackets = total_qprc;
3368         stats->ibytes = total_qbrc;
3369         stats->opackets = hw_stats->gptc;
3370         stats->obytes = hw_stats->gotc;
3371
3372         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3373                 stats->q_ipackets[i] = hw_stats->qprc[i];
3374                 stats->q_opackets[i] = hw_stats->qptc[i];
3375                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3376                 stats->q_obytes[i] = hw_stats->qbtc[i];
3377                 stats->q_errors[i] = hw_stats->qprdc[i];
3378         }
3379
3380         /* Rx Errors */
3381         stats->imissed  = total_missed_rx;
3382         stats->ierrors  = hw_stats->crcerrs +
3383                           hw_stats->mspdc +
3384                           hw_stats->rlec +
3385                           hw_stats->ruc +
3386                           hw_stats->roc +
3387                           hw_stats->illerrc +
3388                           hw_stats->errbc +
3389                           hw_stats->rfc +
3390                           hw_stats->fccrc +
3391                           hw_stats->fclast;
3392
3393         /*
3394          * 82599 errata, UDP frames with a 0 checksum can be marked as checksum
3395          * errors.
3396          */
3397         if (hw->mac.type != ixgbe_mac_82599EB)
3398                 stats->ierrors += hw_stats->xec;
3399
3400         /* Tx Errors */
3401         stats->oerrors  = 0;
3402         return 0;
3403 }
3404
3405 static int
3406 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3407 {
3408         struct ixgbe_hw_stats *stats =
3409                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3410
3411         /* HW registers are cleared on read */
3412         ixgbe_dev_stats_get(dev, NULL);
3413
3414         /* Reset software totals */
3415         memset(stats, 0, sizeof(*stats));
3416
3417         return 0;
3418 }
3419
3420 /* This function calculates the number of xstats based on the current config */
3421 static unsigned
3422 ixgbe_xstats_calc_num(void) {
3423         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3424                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3425                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3426 }
3427
3428 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3429         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3430 {
3431         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3432         unsigned stat, i, count;
3433
3434         if (xstats_names != NULL) {
3435                 count = 0;
3436
3437                 /* Note: limit >= cnt_stats checked upstream
3438                  * in rte_eth_xstats_names()
3439                  */
3440
3441                 /* Extended stats from ixgbe_hw_stats */
3442                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3443                         strlcpy(xstats_names[count].name,
3444                                 rte_ixgbe_stats_strings[i].name,
3445                                 sizeof(xstats_names[count].name));
3446                         count++;
3447                 }
3448
3449                 /* MACsec Stats */
3450                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3451                         strlcpy(xstats_names[count].name,
3452                                 rte_ixgbe_macsec_strings[i].name,
3453                                 sizeof(xstats_names[count].name));
3454                         count++;
3455                 }
3456
3457                 /* RX Priority Stats */
3458                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3459                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3460                                 snprintf(xstats_names[count].name,
3461                                         sizeof(xstats_names[count].name),
3462                                         "rx_priority%u_%s", i,
3463                                         rte_ixgbe_rxq_strings[stat].name);
3464                                 count++;
3465                         }
3466                 }
3467
3468                 /* TX Priority Stats */
3469                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3470                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3471                                 snprintf(xstats_names[count].name,
3472                                         sizeof(xstats_names[count].name),
3473                                         "tx_priority%u_%s", i,
3474                                         rte_ixgbe_txq_strings[stat].name);
3475                                 count++;
3476                         }
3477                 }
3478         }
3479         return cnt_stats;
3480 }
3481
3482 static int ixgbe_dev_xstats_get_names_by_id(
3483         struct rte_eth_dev *dev,
3484         const uint64_t *ids,
3485         struct rte_eth_xstat_name *xstats_names,
3486         unsigned int limit)
3487 {
3488         if (!ids) {
3489                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3490                 unsigned int stat, i, count;
3491
3492                 if (xstats_names != NULL) {
3493                         count = 0;
3494
3495                         /* Note: limit >= cnt_stats checked upstream
3496                          * in rte_eth_xstats_names()
3497                          */
3498
3499                         /* Extended stats from ixgbe_hw_stats */
3500                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3501                                 strlcpy(xstats_names[count].name,
3502                                         rte_ixgbe_stats_strings[i].name,
3503                                         sizeof(xstats_names[count].name));
3504                                 count++;
3505                         }
3506
3507                         /* MACsec Stats */
3508                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3509                                 strlcpy(xstats_names[count].name,
3510                                         rte_ixgbe_macsec_strings[i].name,
3511                                         sizeof(xstats_names[count].name));
3512                                 count++;
3513                         }
3514
3515                         /* RX Priority Stats */
3516                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3517                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3518                                         snprintf(xstats_names[count].name,
3519                                             sizeof(xstats_names[count].name),
3520                                             "rx_priority%u_%s", i,
3521                                             rte_ixgbe_rxq_strings[stat].name);
3522                                         count++;
3523                                 }
3524                         }
3525
3526                         /* TX Priority Stats */
3527                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3528                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3529                                         snprintf(xstats_names[count].name,
3530                                             sizeof(xstats_names[count].name),
3531                                             "tx_priority%u_%s", i,
3532                                             rte_ixgbe_txq_strings[stat].name);
3533                                         count++;
3534                                 }
3535                         }
3536                 }
3537                 return cnt_stats;
3538         }
3539
3540         uint16_t i;
3541         uint16_t size = ixgbe_xstats_calc_num();
3542         struct rte_eth_xstat_name xstats_names_copy[size];
3543
3544         ixgbe_dev_xstats_get_names_by_id(dev, NULL, xstats_names_copy,
3545                         size);
3546
3547         for (i = 0; i < limit; i++) {
3548                 if (ids[i] >= size) {
3549                         PMD_INIT_LOG(ERR, "id value isn't valid");
3550                         return -1;
3551                 }
3552                 strcpy(xstats_names[i].name,
3553                                 xstats_names_copy[ids[i]].name);
3554         }
3555         return limit;
3556 }
3557
3558 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3559         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3560 {
3561         unsigned i;
3562
3563         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3564                 return -ENOMEM;
3565
3566         if (xstats_names != NULL)
3567                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3568                         strlcpy(xstats_names[i].name,
3569                                 rte_ixgbevf_stats_strings[i].name,
3570                                 sizeof(xstats_names[i].name));
3571         return IXGBEVF_NB_XSTATS;
3572 }
3573
3574 static int
3575 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3576                                          unsigned n)
3577 {
3578         struct ixgbe_hw *hw =
3579                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3580         struct ixgbe_hw_stats *hw_stats =
3581                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3582         struct ixgbe_macsec_stats *macsec_stats =
3583                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3584                                 dev->data->dev_private);
3585         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3586         unsigned i, stat, count = 0;
3587
3588         count = ixgbe_xstats_calc_num();
3589
3590         if (n < count)
3591                 return count;
3592
3593         total_missed_rx = 0;
3594         total_qbrc = 0;
3595         total_qprc = 0;
3596         total_qprdc = 0;
3597
3598         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3599                         &total_qbrc, &total_qprc, &total_qprdc);
3600
3601         /* If this is a reset xstats is NULL, and we have cleared the
3602          * registers by reading them.
3603          */
3604         if (!xstats)
3605                 return 0;
3606
3607         /* Extended stats from ixgbe_hw_stats */
3608         count = 0;
3609         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3610                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3611                                 rte_ixgbe_stats_strings[i].offset);
3612                 xstats[count].id = count;
3613                 count++;
3614         }
3615
3616         /* MACsec Stats */
3617         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3618                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3619                                 rte_ixgbe_macsec_strings[i].offset);
3620                 xstats[count].id = count;
3621                 count++;
3622         }
3623
3624         /* RX Priority Stats */
3625         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3626                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3627                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3628                                         rte_ixgbe_rxq_strings[stat].offset +
3629                                         (sizeof(uint64_t) * i));
3630                         xstats[count].id = count;
3631                         count++;
3632                 }
3633         }
3634
3635         /* TX Priority Stats */
3636         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3637                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3638                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3639                                         rte_ixgbe_txq_strings[stat].offset +
3640                                         (sizeof(uint64_t) * i));
3641                         xstats[count].id = count;
3642                         count++;
3643                 }
3644         }
3645         return count;
3646 }
3647
3648 static int
3649 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3650                 uint64_t *values, unsigned int n)
3651 {
3652         if (!ids) {
3653                 struct ixgbe_hw *hw =
3654                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3655                 struct ixgbe_hw_stats *hw_stats =
3656                                 IXGBE_DEV_PRIVATE_TO_STATS(
3657                                                 dev->data->dev_private);
3658                 struct ixgbe_macsec_stats *macsec_stats =
3659                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3660                                         dev->data->dev_private);
3661                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3662                 unsigned int i, stat, count = 0;
3663
3664                 count = ixgbe_xstats_calc_num();
3665
3666                 if (!ids && n < count)
3667                         return count;
3668
3669                 total_missed_rx = 0;
3670                 total_qbrc = 0;
3671                 total_qprc = 0;
3672                 total_qprdc = 0;
3673
3674                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3675                                 &total_missed_rx, &total_qbrc, &total_qprc,
3676                                 &total_qprdc);
3677
3678                 /* If this is a reset xstats is NULL, and we have cleared the
3679                  * registers by reading them.
3680                  */
3681                 if (!ids && !values)
3682                         return 0;
3683
3684                 /* Extended stats from ixgbe_hw_stats */
3685                 count = 0;
3686                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3687                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3688                                         rte_ixgbe_stats_strings[i].offset);
3689                         count++;
3690                 }
3691
3692                 /* MACsec Stats */
3693                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3694                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3695                                         rte_ixgbe_macsec_strings[i].offset);
3696                         count++;
3697                 }
3698
3699                 /* RX Priority Stats */
3700                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3701                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3702                                 values[count] =
3703                                         *(uint64_t *)(((char *)hw_stats) +
3704                                         rte_ixgbe_rxq_strings[stat].offset +
3705                                         (sizeof(uint64_t) * i));
3706                                 count++;
3707                         }
3708                 }
3709
3710                 /* TX Priority Stats */
3711                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3712                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3713                                 values[count] =
3714                                         *(uint64_t *)(((char *)hw_stats) +
3715                                         rte_ixgbe_txq_strings[stat].offset +
3716                                         (sizeof(uint64_t) * i));
3717                                 count++;
3718                         }
3719                 }
3720                 return count;
3721         }
3722
3723         uint16_t i;
3724         uint16_t size = ixgbe_xstats_calc_num();
3725         uint64_t values_copy[size];
3726
3727         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3728
3729         for (i = 0; i < n; i++) {
3730                 if (ids[i] >= size) {
3731                         PMD_INIT_LOG(ERR, "id value isn't valid");
3732                         return -1;
3733                 }
3734                 values[i] = values_copy[ids[i]];
3735         }
3736         return n;
3737 }
3738
3739 static int
3740 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3741 {
3742         struct ixgbe_hw_stats *stats =
3743                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3744         struct ixgbe_macsec_stats *macsec_stats =
3745                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3746                                 dev->data->dev_private);
3747
3748         unsigned count = ixgbe_xstats_calc_num();
3749
3750         /* HW registers are cleared on read */
3751         ixgbe_dev_xstats_get(dev, NULL, count);
3752
3753         /* Reset software totals */
3754         memset(stats, 0, sizeof(*stats));
3755         memset(macsec_stats, 0, sizeof(*macsec_stats));
3756
3757         return 0;
3758 }
3759
3760 static void
3761 ixgbevf_update_stats(struct rte_eth_dev *dev)
3762 {
3763         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3765                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3766
3767         /* Good Rx packet, include VF loopback */
3768         UPDATE_VF_STAT(IXGBE_VFGPRC,
3769             hw_stats->last_vfgprc, hw_stats->vfgprc);
3770
3771         /* Good Rx octets, include VF loopback */
3772         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3773             hw_stats->last_vfgorc, hw_stats->vfgorc);
3774
3775         /* Good Tx packet, include VF loopback */
3776         UPDATE_VF_STAT(IXGBE_VFGPTC,
3777             hw_stats->last_vfgptc, hw_stats->vfgptc);
3778
3779         /* Good Tx octets, include VF loopback */
3780         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3781             hw_stats->last_vfgotc, hw_stats->vfgotc);
3782
3783         /* Rx Multicst Packet */
3784         UPDATE_VF_STAT(IXGBE_VFMPRC,
3785             hw_stats->last_vfmprc, hw_stats->vfmprc);
3786 }
3787
3788 static int
3789 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3790                        unsigned n)
3791 {
3792         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3793                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3794         unsigned i;
3795
3796         if (n < IXGBEVF_NB_XSTATS)
3797                 return IXGBEVF_NB_XSTATS;
3798
3799         ixgbevf_update_stats(dev);
3800
3801         if (!xstats)
3802                 return 0;
3803
3804         /* Extended stats */
3805         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3806                 xstats[i].id = i;
3807                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3808                         rte_ixgbevf_stats_strings[i].offset);
3809         }
3810
3811         return IXGBEVF_NB_XSTATS;
3812 }
3813
3814 static int
3815 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3816 {
3817         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3818                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3819
3820         ixgbevf_update_stats(dev);
3821
3822         if (stats == NULL)
3823                 return -EINVAL;
3824
3825         stats->ipackets = hw_stats->vfgprc;
3826         stats->ibytes = hw_stats->vfgorc;
3827         stats->opackets = hw_stats->vfgptc;
3828         stats->obytes = hw_stats->vfgotc;
3829         return 0;
3830 }
3831
3832 static int
3833 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3834 {
3835         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3836                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3837
3838         /* Sync HW register to the last stats */
3839         ixgbevf_dev_stats_get(dev, NULL);
3840
3841         /* reset HW current stats*/
3842         hw_stats->vfgprc = 0;
3843         hw_stats->vfgorc = 0;
3844         hw_stats->vfgptc = 0;
3845         hw_stats->vfgotc = 0;
3846         hw_stats->vfmprc = 0;
3847
3848         return 0;
3849 }
3850
3851 static int
3852 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3853 {
3854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3855         u16 eeprom_verh, eeprom_verl;
3856         u32 etrack_id;
3857         int ret;
3858
3859         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3860         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3861
3862         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3863         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3864         if (ret < 0)
3865                 return -EINVAL;
3866
3867         ret += 1; /* add the size of '\0' */
3868         if (fw_size < (size_t)ret)
3869                 return ret;
3870         else
3871                 return 0;
3872 }
3873
3874 static int
3875 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3876 {
3877         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3879         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3880
3881         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3882         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3883         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3884                 /*
3885                  * When DCB/VT is off, maximum number of queues changes,
3886                  * except for 82598EB, which remains constant.
3887                  */
3888                 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_NONE &&
3889                                 hw->mac.type != ixgbe_mac_82598EB)
3890                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3891         }
3892         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3893         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3894         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3895         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3896         dev_info->max_vfs = pci_dev->max_vfs;
3897         if (hw->mac.type == ixgbe_mac_82598EB)
3898                 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
3899         else
3900                 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS;
3901         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3902         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3903         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3904         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3905         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3906                                      dev_info->rx_queue_offload_capa);
3907         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3908         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3909
3910         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3911                 .rx_thresh = {
3912                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3913                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3914                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3915                 },
3916                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3917                 .rx_drop_en = 0,
3918                 .offloads = 0,
3919         };
3920
3921         dev_info->default_txconf = (struct rte_eth_txconf) {
3922                 .tx_thresh = {
3923                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3924                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3925                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3926                 },
3927                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3928                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3929                 .offloads = 0,
3930         };
3931
3932         dev_info->rx_desc_lim = rx_desc_lim;
3933         dev_info->tx_desc_lim = tx_desc_lim;
3934
3935         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3936         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3937         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3938
3939         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G;
3940         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3941                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3942                 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M |
3943                         RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G;
3944
3945         if (hw->mac.type == ixgbe_mac_X540 ||
3946             hw->mac.type == ixgbe_mac_X540_vf ||
3947             hw->mac.type == ixgbe_mac_X550 ||
3948             hw->mac.type == ixgbe_mac_X550_vf) {
3949                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100M;
3950         }
3951         if (hw->mac.type == ixgbe_mac_X550) {
3952                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_2_5G;
3953                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_5G;
3954         }
3955
3956         /* Driver-preferred Rx/Tx parameters */
3957         dev_info->default_rxportconf.burst_size = 32;
3958         dev_info->default_txportconf.burst_size = 32;
3959         dev_info->default_rxportconf.nb_queues = 1;
3960         dev_info->default_txportconf.nb_queues = 1;
3961         dev_info->default_rxportconf.ring_size = 256;
3962         dev_info->default_txportconf.ring_size = 256;
3963
3964         return 0;
3965 }
3966
3967 static const uint32_t *
3968 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3969 {
3970         static const uint32_t ptypes[] = {
3971                 /* For non-vec functions,
3972                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3973                  * for vec functions,
3974                  * refers to _recv_raw_pkts_vec().
3975                  */
3976                 RTE_PTYPE_L2_ETHER,
3977                 RTE_PTYPE_L3_IPV4,
3978                 RTE_PTYPE_L3_IPV4_EXT,
3979                 RTE_PTYPE_L3_IPV6,
3980                 RTE_PTYPE_L3_IPV6_EXT,
3981                 RTE_PTYPE_L4_SCTP,
3982                 RTE_PTYPE_L4_TCP,
3983                 RTE_PTYPE_L4_UDP,
3984                 RTE_PTYPE_TUNNEL_IP,
3985                 RTE_PTYPE_INNER_L3_IPV6,
3986                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3987                 RTE_PTYPE_INNER_L4_TCP,
3988                 RTE_PTYPE_INNER_L4_UDP,
3989                 RTE_PTYPE_UNKNOWN
3990         };
3991
3992         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3993             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3994             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3995             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3996                 return ptypes;
3997
3998 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3999         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
4000             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
4001                 return ptypes;
4002 #endif
4003         return NULL;
4004 }
4005
4006 static int
4007 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
4008                      struct rte_eth_dev_info *dev_info)
4009 {
4010         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4011         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4012
4013         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
4014         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
4015         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
4016         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
4017         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
4018         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
4019         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
4020         dev_info->max_vfs = pci_dev->max_vfs;
4021         if (hw->mac.type == ixgbe_mac_82598EB)
4022                 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
4023         else
4024                 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS;
4025         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
4026         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
4027                                      dev_info->rx_queue_offload_capa);
4028         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
4029         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
4030         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
4031         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
4032         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
4033
4034         dev_info->default_rxconf = (struct rte_eth_rxconf) {
4035                 .rx_thresh = {
4036                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4037                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4038                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4039                 },
4040                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4041                 .rx_drop_en = 0,
4042                 .offloads = 0,
4043         };
4044
4045         dev_info->default_txconf = (struct rte_eth_txconf) {
4046                 .tx_thresh = {
4047                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4048                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4049                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4050                 },
4051                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4052                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4053                 .offloads = 0,
4054         };
4055
4056         dev_info->rx_desc_lim = rx_desc_lim;
4057         dev_info->tx_desc_lim = tx_desc_lim;
4058
4059         return 0;
4060 }
4061
4062 static int
4063 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4064                    bool *link_up, int wait_to_complete)
4065 {
4066         struct ixgbe_adapter *adapter = container_of(hw,
4067                                                      struct ixgbe_adapter, hw);
4068         struct ixgbe_mbx_info *mbx = &hw->mbx;
4069         struct ixgbe_mac_info *mac = &hw->mac;
4070         uint32_t links_reg, in_msg;
4071         int ret_val = 0;
4072
4073         /* If we were hit with a reset drop the link */
4074         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4075                 mac->get_link_status = true;
4076
4077         if (!mac->get_link_status)
4078                 goto out;
4079
4080         /* if link status is down no point in checking to see if pf is up */
4081         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4082         if (!(links_reg & IXGBE_LINKS_UP))
4083                 goto out;
4084
4085         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4086          * before the link status is correct
4087          */
4088         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4089                 int i;
4090
4091                 for (i = 0; i < 5; i++) {
4092                         rte_delay_us(100);
4093                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4094
4095                         if (!(links_reg & IXGBE_LINKS_UP))
4096                                 goto out;
4097                 }
4098         }
4099
4100         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4101         case IXGBE_LINKS_SPEED_10G_82599:
4102                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4103                 if (hw->mac.type >= ixgbe_mac_X550) {
4104                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4105                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4106                 }
4107                 break;
4108         case IXGBE_LINKS_SPEED_1G_82599:
4109                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4110                 break;
4111         case IXGBE_LINKS_SPEED_100_82599:
4112                 *speed = IXGBE_LINK_SPEED_100_FULL;
4113                 if (hw->mac.type == ixgbe_mac_X550) {
4114                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4115                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4116                 }
4117                 break;
4118         case IXGBE_LINKS_SPEED_10_X550EM_A:
4119                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4120                 /* Since Reserved in older MAC's */
4121                 if (hw->mac.type >= ixgbe_mac_X550)
4122                         *speed = IXGBE_LINK_SPEED_10_FULL;
4123                 break;
4124         default:
4125                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4126         }
4127
4128         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4129                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4130                         mac->get_link_status = true;
4131                 else
4132                         mac->get_link_status = false;
4133
4134                 goto out;
4135         }
4136
4137         /* if the read failed it could just be a mailbox collision, best wait
4138          * until we are called again and don't report an error
4139          */
4140         if (mbx->ops.read(hw, &in_msg, 1, 0))
4141                 goto out;
4142
4143         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4144                 /* msg is not CTS and is NACK we must have lost CTS status */
4145                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4146                         mac->get_link_status = false;
4147                 goto out;
4148         }
4149
4150         /* the pf is talking, if we timed out in the past we reinit */
4151         if (!mbx->timeout) {
4152                 ret_val = -1;
4153                 goto out;
4154         }
4155
4156         /* if we passed all the tests above then the link is up and we no
4157          * longer need to check for link
4158          */
4159         mac->get_link_status = false;
4160
4161 out:
4162         *link_up = !mac->get_link_status;
4163         return ret_val;
4164 }
4165
4166 /*
4167  * If @timeout_ms was 0, it means that it will not return until link complete.
4168  * It returns 1 on complete, return 0 on timeout.
4169  */
4170 static int
4171 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4172 {
4173 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4174         struct ixgbe_adapter *ad = dev->data->dev_private;
4175         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4176
4177         while (rte_atomic32_read(&ad->link_thread_running)) {
4178                 msec_delay(1);
4179                 timeout--;
4180
4181                 if (timeout_ms) {
4182                         if (!timeout)
4183                                 return 0;
4184                 } else if (!timeout) {
4185                         /* It will not return until link complete */
4186                         timeout = WARNING_TIMEOUT;
4187                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4188                 }
4189         }
4190
4191         return 1;
4192 }
4193
4194 static void *
4195 ixgbe_dev_setup_link_thread_handler(void *param)
4196 {
4197         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4198         struct ixgbe_adapter *ad = dev->data->dev_private;
4199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4200         struct ixgbe_interrupt *intr =
4201                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4202         u32 speed;
4203         bool autoneg = false;
4204
4205         pthread_detach(pthread_self());
4206         speed = hw->phy.autoneg_advertised;
4207         if (!speed)
4208                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4209
4210         ixgbe_setup_link(hw, speed, true);
4211
4212         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4213         rte_atomic32_clear(&ad->link_thread_running);
4214         return NULL;
4215 }
4216
4217 /*
4218  * In freebsd environment, nic_uio drivers do not support interrupts,
4219  * rte_intr_callback_register() will fail to register interrupts.
4220  * We can not make link status to change from down to up by interrupt
4221  * callback. So we need to wait for the controller to acquire link
4222  * when ports start.
4223  * It returns 0 on link up.
4224  */
4225 static int
4226 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4227 {
4228 #ifdef RTE_EXEC_ENV_FREEBSD
4229         int err, i;
4230         bool link_up = false;
4231         uint32_t speed = 0;
4232         const int nb_iter = 25;
4233
4234         for (i = 0; i < nb_iter; i++) {
4235                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4236                 if (err)
4237                         return err;
4238                 if (link_up)
4239                         return 0;
4240                 msec_delay(200);
4241         }
4242
4243         return 0;
4244 #else
4245         RTE_SET_USED(hw);
4246         return 0;
4247 #endif
4248 }
4249
4250 /* return 0 means link status changed, -1 means not changed */
4251 int
4252 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4253                             int wait_to_complete, int vf)
4254 {
4255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256         struct ixgbe_adapter *ad = dev->data->dev_private;
4257         struct rte_eth_link link;
4258         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4259         struct ixgbe_interrupt *intr =
4260                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4261         bool link_up;
4262         int diag;
4263         int wait = 1;
4264         u32 esdp_reg;
4265
4266         memset(&link, 0, sizeof(link));
4267         link.link_status = RTE_ETH_LINK_DOWN;
4268         link.link_speed = RTE_ETH_SPEED_NUM_NONE;
4269         link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
4270         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4271                         RTE_ETH_LINK_SPEED_FIXED);
4272
4273         hw->mac.get_link_status = true;
4274
4275         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4276                 return rte_eth_linkstatus_set(dev, &link);
4277
4278         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4279         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4280                 wait = 0;
4281
4282 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4283 #ifdef RTE_EXEC_ENV_FREEBSD
4284         wait = 1;
4285 #endif
4286
4287         if (vf)
4288                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4289         else
4290                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4291
4292         if (diag != 0) {
4293                 link.link_speed = RTE_ETH_SPEED_NUM_100M;
4294                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
4295                 return rte_eth_linkstatus_set(dev, &link);
4296         }
4297
4298         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber &&
4299             !ad->sdp3_no_tx_disable) {
4300                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4301                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4302                         link_up = 0;
4303         }
4304
4305         if (link_up == 0) {
4306                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4307                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4308                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4309                                 /* To avoid race condition between threads, set
4310                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4311                                  * when there is no link thread running.
4312                                  */
4313                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4314                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4315                                         "ixgbe-link-handler",
4316                                         NULL,
4317                                         ixgbe_dev_setup_link_thread_handler,
4318                                         dev) < 0) {
4319                                         PMD_DRV_LOG(ERR,
4320                                                 "Create link thread failed!");
4321                                         rte_atomic32_clear(&ad->link_thread_running);
4322                                 }
4323                         } else {
4324                                 PMD_DRV_LOG(ERR,
4325                                         "Other link thread is running now!");
4326                         }
4327                 }
4328                 return rte_eth_linkstatus_set(dev, &link);
4329         }
4330
4331         link.link_status = RTE_ETH_LINK_UP;
4332         link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
4333
4334         switch (link_speed) {
4335         default:
4336         case IXGBE_LINK_SPEED_UNKNOWN:
4337                 link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
4338                 break;
4339
4340         case IXGBE_LINK_SPEED_10_FULL:
4341                 link.link_speed = RTE_ETH_SPEED_NUM_10M;
4342                 break;
4343
4344         case IXGBE_LINK_SPEED_100_FULL:
4345                 link.link_speed = RTE_ETH_SPEED_NUM_100M;
4346                 break;
4347
4348         case IXGBE_LINK_SPEED_1GB_FULL:
4349                 link.link_speed = RTE_ETH_SPEED_NUM_1G;
4350                 break;
4351
4352         case IXGBE_LINK_SPEED_2_5GB_FULL:
4353                 link.link_speed = RTE_ETH_SPEED_NUM_2_5G;
4354                 break;
4355
4356         case IXGBE_LINK_SPEED_5GB_FULL:
4357                 link.link_speed = RTE_ETH_SPEED_NUM_5G;
4358                 break;
4359
4360         case IXGBE_LINK_SPEED_10GB_FULL:
4361                 link.link_speed = RTE_ETH_SPEED_NUM_10G;
4362                 break;
4363         }
4364
4365         return rte_eth_linkstatus_set(dev, &link);
4366 }
4367
4368 static int
4369 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4370 {
4371         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4372 }
4373
4374 static int
4375 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4376 {
4377         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4378 }
4379
4380 static int
4381 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4382 {
4383         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4384         uint32_t fctrl;
4385
4386         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4387         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4388         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4389
4390         return 0;
4391 }
4392
4393 static int
4394 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4395 {
4396         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4397         uint32_t fctrl;
4398
4399         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4400         fctrl &= (~IXGBE_FCTRL_UPE);
4401         if (dev->data->all_multicast == 1)
4402                 fctrl |= IXGBE_FCTRL_MPE;
4403         else
4404                 fctrl &= (~IXGBE_FCTRL_MPE);
4405         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4406
4407         return 0;
4408 }
4409
4410 static int
4411 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4412 {
4413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4414         uint32_t fctrl;
4415
4416         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4417         fctrl |= IXGBE_FCTRL_MPE;
4418         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4419
4420         return 0;
4421 }
4422
4423 static int
4424 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4425 {
4426         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4427         uint32_t fctrl;
4428
4429         if (dev->data->promiscuous == 1)
4430                 return 0; /* must remain in all_multicast mode */
4431
4432         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4433         fctrl &= (~IXGBE_FCTRL_MPE);
4434         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4435
4436         return 0;
4437 }
4438
4439 /**
4440  * It clears the interrupt causes and enables the interrupt.
4441  * It will be called once only during nic initialized.
4442  *
4443  * @param dev
4444  *  Pointer to struct rte_eth_dev.
4445  * @param on
4446  *  Enable or Disable.
4447  *
4448  * @return
4449  *  - On success, zero.
4450  *  - On failure, a negative value.
4451  */
4452 static int
4453 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4454 {
4455         struct ixgbe_interrupt *intr =
4456                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4457
4458         ixgbe_dev_link_status_print(dev);
4459         if (on)
4460                 intr->mask |= IXGBE_EICR_LSC;
4461         else
4462                 intr->mask &= ~IXGBE_EICR_LSC;
4463
4464         return 0;
4465 }
4466
4467 /**
4468  * It clears the interrupt causes and enables the interrupt.
4469  * It will be called once only during nic initialized.
4470  *
4471  * @param dev
4472  *  Pointer to struct rte_eth_dev.
4473  *
4474  * @return
4475  *  - On success, zero.
4476  *  - On failure, a negative value.
4477  */
4478 static int
4479 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4480 {
4481         struct ixgbe_interrupt *intr =
4482                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4483
4484         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4485
4486         return 0;
4487 }
4488
4489 /**
4490  * It clears the interrupt causes and enables the interrupt.
4491  * It will be called once only during nic initialized.
4492  *
4493  * @param dev
4494  *  Pointer to struct rte_eth_dev.
4495  *
4496  * @return
4497  *  - On success, zero.
4498  *  - On failure, a negative value.
4499  */
4500 static int
4501 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4502 {
4503         struct ixgbe_interrupt *intr =
4504                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4505
4506         intr->mask |= IXGBE_EICR_LINKSEC;
4507
4508         return 0;
4509 }
4510
4511 /*
4512  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4513  *
4514  * @param dev
4515  *  Pointer to struct rte_eth_dev.
4516  *
4517  * @return
4518  *  - On success, zero.
4519  *  - On failure, a negative value.
4520  */
4521 static int
4522 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4523 {
4524         uint32_t eicr;
4525         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4526         struct ixgbe_interrupt *intr =
4527                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4528
4529         /* clear all cause mask */
4530         ixgbe_disable_intr(hw);
4531
4532         /* read-on-clear nic registers here */
4533         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4534         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4535
4536         intr->flags = 0;
4537
4538         /* set flag for async link update */
4539         if (eicr & IXGBE_EICR_LSC)
4540                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4541
4542         if (eicr & IXGBE_EICR_MAILBOX)
4543                 intr->flags |= IXGBE_FLAG_MAILBOX;
4544
4545         if (eicr & IXGBE_EICR_LINKSEC)
4546                 intr->flags |= IXGBE_FLAG_MACSEC;
4547
4548         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4549             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4550             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4551                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4552
4553         return 0;
4554 }
4555
4556 /**
4557  * It gets and then prints the link status.
4558  *
4559  * @param dev
4560  *  Pointer to struct rte_eth_dev.
4561  *
4562  * @return
4563  *  - On success, zero.
4564  *  - On failure, a negative value.
4565  */
4566 static void
4567 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4568 {
4569         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4570         struct rte_eth_link link;
4571
4572         rte_eth_linkstatus_get(dev, &link);
4573
4574         if (link.link_status) {
4575                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4576                                         (int)(dev->data->port_id),
4577                                         (unsigned)link.link_speed,
4578                         link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?
4579                                         "full-duplex" : "half-duplex");
4580         } else {
4581                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4582                                 (int)(dev->data->port_id));
4583         }
4584         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4585                                 pci_dev->addr.domain,
4586                                 pci_dev->addr.bus,
4587                                 pci_dev->addr.devid,
4588                                 pci_dev->addr.function);
4589 }
4590
4591 /*
4592  * It executes link_update after knowing an interrupt occurred.
4593  *
4594  * @param dev
4595  *  Pointer to struct rte_eth_dev.
4596  *
4597  * @return
4598  *  - On success, zero.
4599  *  - On failure, a negative value.
4600  */
4601 static int
4602 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4603 {
4604         struct ixgbe_interrupt *intr =
4605                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4606         int64_t timeout;
4607         struct ixgbe_hw *hw =
4608                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4609
4610         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4611
4612         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4613                 ixgbe_pf_mbx_process(dev);
4614                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4615         }
4616
4617         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4618                 ixgbe_handle_lasi(hw);
4619                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4620         }
4621
4622         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4623                 struct rte_eth_link link;
4624
4625                 /* get the link status before link update, for predicting later */
4626                 rte_eth_linkstatus_get(dev, &link);
4627
4628                 ixgbe_dev_link_update(dev, 0);
4629
4630                 /* likely to up */
4631                 if (!link.link_status)
4632                         /* handle it 1 sec later, wait it being stable */
4633                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4634                 /* likely to down */
4635                 else
4636                         /* handle it 4 sec later, wait it being stable */
4637                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4638
4639                 ixgbe_dev_link_status_print(dev);
4640                 if (rte_eal_alarm_set(timeout * 1000,
4641                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4642                         PMD_DRV_LOG(ERR, "Error setting alarm");
4643                 else {
4644                         /* remember original mask */
4645                         intr->mask_original = intr->mask;
4646                         /* only disable lsc interrupt */
4647                         intr->mask &= ~IXGBE_EIMS_LSC;
4648                 }
4649         }
4650
4651         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4652         ixgbe_enable_intr(dev);
4653
4654         return 0;
4655 }
4656
4657 /**
4658  * Interrupt handler which shall be registered for alarm callback for delayed
4659  * handling specific interrupt to wait for the stable nic state. As the
4660  * NIC interrupt state is not stable for ixgbe after link is just down,
4661  * it needs to wait 4 seconds to get the stable status.
4662  *
4663  * @param handle
4664  *  Pointer to interrupt handle.
4665  * @param param
4666  *  The address of parameter (struct rte_eth_dev *) registered before.
4667  *
4668  * @return
4669  *  void
4670  */
4671 static void
4672 ixgbe_dev_interrupt_delayed_handler(void *param)
4673 {
4674         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4675         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4676         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
4677         struct ixgbe_interrupt *intr =
4678                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4679         struct ixgbe_hw *hw =
4680                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4681         uint32_t eicr;
4682
4683         ixgbe_disable_intr(hw);
4684
4685         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4686         if (eicr & IXGBE_EICR_MAILBOX)
4687                 ixgbe_pf_mbx_process(dev);
4688
4689         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4690                 ixgbe_handle_lasi(hw);
4691                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4692         }
4693
4694         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4695                 ixgbe_dev_link_update(dev, 0);
4696                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4697                 ixgbe_dev_link_status_print(dev);
4698                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4699         }
4700
4701         if (intr->flags & IXGBE_FLAG_MACSEC) {
4702                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4703                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4704         }
4705
4706         /* restore original mask */
4707         intr->mask = intr->mask_original;
4708         intr->mask_original = 0;
4709
4710         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4711         ixgbe_enable_intr(dev);
4712         rte_intr_ack(intr_handle);
4713 }
4714
4715 /**
4716  * Interrupt handler triggered by NIC  for handling
4717  * specific interrupt.
4718  *
4719  * @param handle
4720  *  Pointer to interrupt handle.
4721  * @param param
4722  *  The address of parameter (struct rte_eth_dev *) registered before.
4723  *
4724  * @return
4725  *  void
4726  */
4727 static void
4728 ixgbe_dev_interrupt_handler(void *param)
4729 {
4730         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4731
4732         ixgbe_dev_interrupt_get_status(dev);
4733         ixgbe_dev_interrupt_action(dev);
4734 }
4735
4736 static int
4737 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4738 {
4739         struct ixgbe_hw *hw;
4740
4741         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4743 }
4744
4745 static int
4746 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4747 {
4748         struct ixgbe_hw *hw;
4749
4750         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4751         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4752 }
4753
4754 static int
4755 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4756 {
4757         struct ixgbe_hw *hw;
4758         uint32_t mflcn_reg;
4759         uint32_t fccfg_reg;
4760         int rx_pause;
4761         int tx_pause;
4762
4763         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4764
4765         fc_conf->pause_time = hw->fc.pause_time;
4766         fc_conf->high_water = hw->fc.high_water[0];
4767         fc_conf->low_water = hw->fc.low_water[0];
4768         fc_conf->send_xon = hw->fc.send_xon;
4769         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4770
4771         /*
4772          * Return rx_pause status according to actual setting of
4773          * MFLCN register.
4774          */
4775         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4776         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4777                 fc_conf->mac_ctrl_frame_fwd = 1;
4778         else
4779                 fc_conf->mac_ctrl_frame_fwd = 0;
4780
4781         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4782                 rx_pause = 1;
4783         else
4784                 rx_pause = 0;
4785
4786         /*
4787          * Return tx_pause status according to actual setting of
4788          * FCCFG register.
4789          */
4790         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4791         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4792                 tx_pause = 1;
4793         else
4794                 tx_pause = 0;
4795
4796         if (rx_pause && tx_pause)
4797                 fc_conf->mode = RTE_ETH_FC_FULL;
4798         else if (rx_pause)
4799                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
4800         else if (tx_pause)
4801                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
4802         else
4803                 fc_conf->mode = RTE_ETH_FC_NONE;
4804
4805         return 0;
4806 }
4807
4808 static int
4809 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4810 {
4811         struct ixgbe_hw *hw;
4812         struct ixgbe_adapter *adapter = dev->data->dev_private;
4813         int err;
4814         uint32_t rx_buf_size;
4815         uint32_t max_high_water;
4816         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4817                 ixgbe_fc_none,
4818                 ixgbe_fc_rx_pause,
4819                 ixgbe_fc_tx_pause,
4820                 ixgbe_fc_full
4821         };
4822
4823         PMD_INIT_FUNC_TRACE();
4824
4825         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4827         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4828
4829         /*
4830          * At least reserve one Ethernet frame for watermark
4831          * high_water/low_water in kilo bytes for ixgbe
4832          */
4833         max_high_water = (rx_buf_size -
4834                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4835         if ((fc_conf->high_water > max_high_water) ||
4836                 (fc_conf->high_water < fc_conf->low_water)) {
4837                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4838                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4839                 return -EINVAL;
4840         }
4841
4842         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4843         hw->fc.pause_time     = fc_conf->pause_time;
4844         hw->fc.high_water[0]  = fc_conf->high_water;
4845         hw->fc.low_water[0]   = fc_conf->low_water;
4846         hw->fc.send_xon       = fc_conf->send_xon;
4847         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4848         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4849
4850         err = ixgbe_flow_ctrl_enable(dev, hw);
4851         if (err < 0) {
4852                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4853                 return -EIO;
4854         }
4855         return err;
4856 }
4857
4858 /**
4859  *  ixgbe_pfc_enable_generic - Enable flow control
4860  *  @hw: pointer to hardware structure
4861  *  @tc_num: traffic class number
4862  *  Enable flow control according to the current settings.
4863  */
4864 static int
4865 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4866 {
4867         int ret_val = 0;
4868         uint32_t mflcn_reg, fccfg_reg;
4869         uint32_t reg;
4870         uint32_t fcrtl, fcrth;
4871         uint8_t i;
4872         uint8_t nb_rx_en;
4873
4874         /* Validate the water mark configuration */
4875         if (!hw->fc.pause_time) {
4876                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4877                 goto out;
4878         }
4879
4880         /* Low water mark of zero causes XOFF floods */
4881         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4882                  /* High/Low water can not be 0 */
4883                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4884                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4885                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4886                         goto out;
4887                 }
4888
4889                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4890                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4891                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4892                         goto out;
4893                 }
4894         }
4895         /* Negotiate the fc mode to use */
4896         ixgbe_fc_autoneg(hw);
4897
4898         /* Disable any previous flow control settings */
4899         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4900         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4901
4902         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4903         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4904
4905         switch (hw->fc.current_mode) {
4906         case ixgbe_fc_none:
4907                 /*
4908                  * If the count of enabled RX Priority Flow control >1,
4909                  * and the TX pause can not be disabled
4910                  */
4911                 nb_rx_en = 0;
4912                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4913                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4914                         if (reg & IXGBE_FCRTH_FCEN)
4915                                 nb_rx_en++;
4916                 }
4917                 if (nb_rx_en > 1)
4918                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4919                 break;
4920         case ixgbe_fc_rx_pause:
4921                 /*
4922                  * Rx Flow control is enabled and Tx Flow control is
4923                  * disabled by software override. Since there really
4924                  * isn't a way to advertise that we are capable of RX
4925                  * Pause ONLY, we will advertise that we support both
4926                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4927                  * disable the adapter's ability to send PAUSE frames.
4928                  */
4929                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4930                 /*
4931                  * If the count of enabled RX Priority Flow control >1,
4932                  * and the TX pause can not be disabled
4933                  */
4934                 nb_rx_en = 0;
4935                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4936                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4937                         if (reg & IXGBE_FCRTH_FCEN)
4938                                 nb_rx_en++;
4939                 }
4940                 if (nb_rx_en > 1)
4941                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4942                 break;
4943         case ixgbe_fc_tx_pause:
4944                 /*
4945                  * Tx Flow control is enabled, and Rx Flow control is
4946                  * disabled by software override.
4947                  */
4948                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4949                 break;
4950         case ixgbe_fc_full:
4951                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4952                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4953                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4954                 break;
4955         default:
4956                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4957                 ret_val = IXGBE_ERR_CONFIG;
4958                 goto out;
4959         }
4960
4961         /* Set 802.3x based flow control settings. */
4962         mflcn_reg |= IXGBE_MFLCN_DPF;
4963         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4964         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4965
4966         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4967         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4968                 hw->fc.high_water[tc_num]) {
4969                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4970                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4971                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4972         } else {
4973                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4974                 /*
4975                  * In order to prevent Tx hangs when the internal Tx
4976                  * switch is enabled we must set the high water mark
4977                  * to the maximum FCRTH value.  This allows the Tx
4978                  * switch to function even under heavy Rx workloads.
4979                  */
4980                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4981         }
4982         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4983
4984         /* Configure pause time (2 TCs per register) */
4985         reg = hw->fc.pause_time * 0x00010001;
4986         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4987                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4988
4989         /* Configure flow control refresh threshold value */
4990         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4991
4992 out:
4993         return ret_val;
4994 }
4995
4996 static int
4997 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4998 {
4999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
5001
5002         if (hw->mac.type != ixgbe_mac_82598EB) {
5003                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
5004         }
5005         return ret_val;
5006 }
5007
5008 static int
5009 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
5010 {
5011         int err;
5012         uint32_t rx_buf_size;
5013         uint32_t max_high_water;
5014         uint8_t tc_num;
5015         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
5016         struct ixgbe_hw *hw =
5017                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018         struct ixgbe_dcb_config *dcb_config =
5019                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5020
5021         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
5022                 ixgbe_fc_none,
5023                 ixgbe_fc_rx_pause,
5024                 ixgbe_fc_tx_pause,
5025                 ixgbe_fc_full
5026         };
5027
5028         PMD_INIT_FUNC_TRACE();
5029
5030         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
5031         tc_num = map[pfc_conf->priority];
5032         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
5033         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
5034         /*
5035          * At least reserve one Ethernet frame for watermark
5036          * high_water/low_water in kilo bytes for ixgbe
5037          */
5038         max_high_water = (rx_buf_size -
5039                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5040         if ((pfc_conf->fc.high_water > max_high_water) ||
5041             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5042                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5043                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5044                 return -EINVAL;
5045         }
5046
5047         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5048         hw->fc.pause_time = pfc_conf->fc.pause_time;
5049         hw->fc.send_xon = pfc_conf->fc.send_xon;
5050         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5051         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5052
5053         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5054
5055         /* Not negotiated is not an error case */
5056         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5057                 return 0;
5058
5059         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5060         return -EIO;
5061 }
5062
5063 static int
5064 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5065                           struct rte_eth_rss_reta_entry64 *reta_conf,
5066                           uint16_t reta_size)
5067 {
5068         uint16_t i, sp_reta_size;
5069         uint8_t j, mask;
5070         uint32_t reta, r;
5071         uint16_t idx, shift;
5072         struct ixgbe_adapter *adapter = dev->data->dev_private;
5073         struct rte_eth_dev_data *dev_data = dev->data;
5074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         uint32_t reta_reg;
5076
5077         PMD_INIT_FUNC_TRACE();
5078
5079         if (!dev_data->dev_started) {
5080                 PMD_DRV_LOG(ERR,
5081                         "port %d must be started before rss reta update",
5082                          dev_data->port_id);
5083                 return -EIO;
5084         }
5085
5086         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5087                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5088                         "NIC.");
5089                 return -ENOTSUP;
5090         }
5091
5092         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5093         if (reta_size != sp_reta_size) {
5094                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5095                         "(%d) doesn't match the number hardware can supported "
5096                         "(%d)", reta_size, sp_reta_size);
5097                 return -EINVAL;
5098         }
5099
5100         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5101                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
5102                 shift = i % RTE_ETH_RETA_GROUP_SIZE;
5103                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5104                                                 IXGBE_4_BIT_MASK);
5105                 if (!mask)
5106                         continue;
5107                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5108                 if (mask == IXGBE_4_BIT_MASK)
5109                         r = 0;
5110                 else
5111                         r = IXGBE_READ_REG(hw, reta_reg);
5112                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5113                         if (mask & (0x1 << j))
5114                                 reta |= reta_conf[idx].reta[shift + j] <<
5115                                                         (CHAR_BIT * j);
5116                         else
5117                                 reta |= r & (IXGBE_8_BIT_MASK <<
5118                                                 (CHAR_BIT * j));
5119                 }
5120                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5121         }
5122         adapter->rss_reta_updated = 1;
5123
5124         return 0;
5125 }
5126
5127 static int
5128 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5129                          struct rte_eth_rss_reta_entry64 *reta_conf,
5130                          uint16_t reta_size)
5131 {
5132         uint16_t i, sp_reta_size;
5133         uint8_t j, mask;
5134         uint32_t reta;
5135         uint16_t idx, shift;
5136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5137         uint32_t reta_reg;
5138
5139         PMD_INIT_FUNC_TRACE();
5140         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5141         if (reta_size != sp_reta_size) {
5142                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5143                         "(%d) doesn't match the number hardware can supported "
5144                         "(%d)", reta_size, sp_reta_size);
5145                 return -EINVAL;
5146         }
5147
5148         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5149                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
5150                 shift = i % RTE_ETH_RETA_GROUP_SIZE;
5151                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5152                                                 IXGBE_4_BIT_MASK);
5153                 if (!mask)
5154                         continue;
5155
5156                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5157                 reta = IXGBE_READ_REG(hw, reta_reg);
5158                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5159                         if (mask & (0x1 << j))
5160                                 reta_conf[idx].reta[shift + j] =
5161                                         ((reta >> (CHAR_BIT * j)) &
5162                                                 IXGBE_8_BIT_MASK);
5163                 }
5164         }
5165
5166         return 0;
5167 }
5168
5169 static int
5170 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5171                                 uint32_t index, uint32_t pool)
5172 {
5173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174         uint32_t enable_addr = 1;
5175
5176         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5177                              pool, enable_addr);
5178 }
5179
5180 static void
5181 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5182 {
5183         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5184
5185         ixgbe_clear_rar(hw, index);
5186 }
5187
5188 static int
5189 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5190 {
5191         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5192
5193         ixgbe_remove_rar(dev, 0);
5194         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5195
5196         return 0;
5197 }
5198
5199 static bool
5200 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5201 {
5202         if (strcmp(dev->device->driver->name, drv->driver.name))
5203                 return false;
5204
5205         return true;
5206 }
5207
5208 bool
5209 is_ixgbe_supported(struct rte_eth_dev *dev)
5210 {
5211         return is_device_supported(dev, &rte_ixgbe_pmd);
5212 }
5213
5214 static int
5215 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5216 {
5217         uint32_t hlreg0;
5218         uint32_t maxfrs;
5219         struct ixgbe_hw *hw;
5220         struct rte_eth_dev_info dev_info;
5221         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5222         int ret;
5223
5224         ret = ixgbe_dev_info_get(dev, &dev_info);
5225         if (ret != 0)
5226                 return ret;
5227
5228         /* check that mtu is within the allowed range */
5229         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5230                 return -EINVAL;
5231
5232         /* If device is started, refuse mtu that requires the support of
5233          * scattered packets when this feature has not been enabled before.
5234          */
5235         if (dev->data->dev_started && !dev->data->scattered_rx &&
5236             frame_size + 2 * RTE_VLAN_HLEN >
5237                         dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
5238                 PMD_INIT_LOG(ERR, "Stop port first.");
5239                 return -EINVAL;
5240         }
5241
5242         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5243         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5244
5245         /* switch to jumbo mode if needed */
5246         if (mtu > RTE_ETHER_MTU)
5247                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5248         else
5249                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5250         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5251
5252         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5253         maxfrs &= 0x0000FFFF;
5254         maxfrs |= (frame_size << 16);
5255         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5256
5257         return 0;
5258 }
5259
5260 /*
5261  * Virtual Function operations
5262  */
5263 static void
5264 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5265 {
5266         struct ixgbe_interrupt *intr =
5267                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5268         struct ixgbe_hw *hw =
5269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5270
5271         PMD_INIT_FUNC_TRACE();
5272
5273         /* Clear interrupt mask to stop from interrupts being generated */
5274         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5275
5276         IXGBE_WRITE_FLUSH(hw);
5277
5278         /* Clear mask value. */
5279         intr->mask = 0;
5280 }
5281
5282 static void
5283 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5284 {
5285         struct ixgbe_interrupt *intr =
5286                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5287         struct ixgbe_hw *hw =
5288                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289
5290         PMD_INIT_FUNC_TRACE();
5291
5292         /* VF enable interrupt autoclean */
5293         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5294         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5295         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5296
5297         IXGBE_WRITE_FLUSH(hw);
5298
5299         /* Save IXGBE_VTEIMS value to mask. */
5300         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5301 }
5302
5303 static int
5304 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5305 {
5306         struct rte_eth_conf *conf = &dev->data->dev_conf;
5307         struct ixgbe_adapter *adapter = dev->data->dev_private;
5308
5309         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5310                      dev->data->port_id);
5311
5312         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
5313                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
5314
5315         /*
5316          * VF has no ability to enable/disable HW CRC
5317          * Keep the persistent behavior the same as Host PF
5318          */
5319 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5320         if (conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) {
5321                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5322                 conf->rxmode.offloads &= ~RTE_ETH_RX_OFFLOAD_KEEP_CRC;
5323         }
5324 #else
5325         if (!(conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)) {
5326                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5327                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_KEEP_CRC;
5328         }
5329 #endif
5330
5331         /*
5332          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5333          * allocation or vector Rx preconditions we will reset it.
5334          */
5335         adapter->rx_bulk_alloc_allowed = true;
5336         adapter->rx_vec_allowed = true;
5337
5338         return 0;
5339 }
5340
5341 static int
5342 ixgbevf_dev_start(struct rte_eth_dev *dev)
5343 {
5344         struct ixgbe_hw *hw =
5345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5346         uint32_t intr_vector = 0;
5347         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5348         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5349
5350         int err, mask = 0;
5351
5352         PMD_INIT_FUNC_TRACE();
5353
5354         /* Stop the link setup handler before resetting the HW. */
5355         ixgbe_dev_wait_setup_link_complete(dev, 0);
5356
5357         err = hw->mac.ops.reset_hw(hw);
5358
5359         /**
5360          * In this case, reuses the MAC address assigned by VF
5361          * initialization.
5362          */
5363         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5364                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5365                 return err;
5366         }
5367
5368         hw->mac.get_link_status = true;
5369
5370         /* negotiate mailbox API version to use with the PF. */
5371         ixgbevf_negotiate_api(hw);
5372
5373         ixgbevf_dev_tx_init(dev);
5374
5375         /* This can fail when allocating mbufs for descriptor rings */
5376         err = ixgbevf_dev_rx_init(dev);
5377         if (err) {
5378                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5379                 ixgbe_dev_clear_queues(dev);
5380                 return err;
5381         }
5382
5383         /* Set vfta */
5384         ixgbevf_set_vfta_all(dev, 1);
5385
5386         /* Set HW strip */
5387         mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
5388                 RTE_ETH_VLAN_EXTEND_MASK;
5389         err = ixgbevf_vlan_offload_config(dev, mask);
5390         if (err) {
5391                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5392                 ixgbe_dev_clear_queues(dev);
5393                 return err;
5394         }
5395
5396         ixgbevf_dev_rxtx_start(dev);
5397
5398         /* check and configure queue intr-vector mapping */
5399         if (rte_intr_cap_multiple(intr_handle) &&
5400             dev->data->dev_conf.intr_conf.rxq) {
5401                 /* According to datasheet, only vector 0/1/2 can be used,
5402                  * now only one vector is used for Rx queue
5403                  */
5404                 intr_vector = 1;
5405                 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
5406                         ixgbe_dev_clear_queues(dev);
5407                         return -1;
5408                 }
5409         }
5410
5411         if (rte_intr_dp_is_en(intr_handle)) {
5412                 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
5413                                                    dev->data->nb_rx_queues)) {
5414                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5415                                      " intr_vec", dev->data->nb_rx_queues);
5416                         ixgbe_dev_clear_queues(dev);
5417                         return -ENOMEM;
5418                 }
5419         }
5420         ixgbevf_configure_msix(dev);
5421
5422         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5423          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5424          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5425          * is not cleared, it will fail when following rte_intr_enable( ) tries
5426          * to map Rx queue interrupt to other VFIO vectors.
5427          * So clear uio/vfio intr/evevnfd first to avoid failure.
5428          */
5429         rte_intr_disable(intr_handle);
5430
5431         rte_intr_enable(intr_handle);
5432
5433         /* Re-enable interrupt for VF */
5434         ixgbevf_intr_enable(dev);
5435
5436         /*
5437          * Update link status right before return, because it may
5438          * start link configuration process in a separate thread.
5439          */
5440         ixgbevf_dev_link_update(dev, 0);
5441
5442         hw->adapter_stopped = false;
5443
5444         return 0;
5445 }
5446
5447 static int
5448 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5449 {
5450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5451         struct ixgbe_adapter *adapter = dev->data->dev_private;
5452         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5453         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5454
5455         if (hw->adapter_stopped)
5456                 return 0;
5457
5458         PMD_INIT_FUNC_TRACE();
5459
5460         ixgbe_dev_wait_setup_link_complete(dev, 0);
5461
5462         ixgbevf_intr_disable(dev);
5463
5464         dev->data->dev_started = 0;
5465         hw->adapter_stopped = 1;
5466         ixgbe_stop_adapter(hw);
5467
5468         /*
5469           * Clear what we set, but we still keep shadow_vfta to
5470           * restore after device starts
5471           */
5472         ixgbevf_set_vfta_all(dev, 0);
5473
5474         /* Clear stored conf */
5475         dev->data->scattered_rx = 0;
5476
5477         ixgbe_dev_clear_queues(dev);
5478
5479         /* Clean datapath event and queue/vec mapping */
5480         rte_intr_efd_disable(intr_handle);
5481         rte_intr_vec_list_free(intr_handle);
5482
5483         adapter->rss_reta_updated = 0;
5484
5485         return 0;
5486 }
5487
5488 static int
5489 ixgbevf_dev_close(struct rte_eth_dev *dev)
5490 {
5491         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5492         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5493         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5494         int ret;
5495
5496         PMD_INIT_FUNC_TRACE();
5497         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5498                 return 0;
5499
5500         ixgbe_reset_hw(hw);
5501
5502         ret = ixgbevf_dev_stop(dev);
5503
5504         ixgbe_dev_free_queues(dev);
5505
5506         /**
5507          * Remove the VF MAC address ro ensure
5508          * that the VF traffic goes to the PF
5509          * after stop, close and detach of the VF
5510          **/
5511         ixgbevf_remove_mac_addr(dev, 0);
5512
5513         rte_intr_disable(intr_handle);
5514         rte_intr_callback_unregister(intr_handle,
5515                                      ixgbevf_dev_interrupt_handler, dev);
5516
5517         return ret;
5518 }
5519
5520 /*
5521  * Reset VF device
5522  */
5523 static int
5524 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5525 {
5526         int ret;
5527
5528         ret = eth_ixgbevf_dev_uninit(dev);
5529         if (ret)
5530                 return ret;
5531
5532         ret = eth_ixgbevf_dev_init(dev);
5533
5534         return ret;
5535 }
5536
5537 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5538 {
5539         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5540         struct ixgbe_vfta *shadow_vfta =
5541                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5542         int i = 0, j = 0, vfta = 0, mask = 1;
5543
5544         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5545                 vfta = shadow_vfta->vfta[i];
5546                 if (vfta) {
5547                         mask = 1;
5548                         for (j = 0; j < 32; j++) {
5549                                 if (vfta & mask)
5550                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5551                                                        on, false);
5552                                 mask <<= 1;
5553                         }
5554                 }
5555         }
5556
5557 }
5558
5559 static int
5560 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5561 {
5562         struct ixgbe_hw *hw =
5563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564         struct ixgbe_vfta *shadow_vfta =
5565                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5566         uint32_t vid_idx = 0;
5567         uint32_t vid_bit = 0;
5568         int ret = 0;
5569
5570         PMD_INIT_FUNC_TRACE();
5571
5572         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5573         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5574         if (ret) {
5575                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5576                 return ret;
5577         }
5578         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5579         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5580
5581         /* Save what we set and retore it after device reset */
5582         if (on)
5583                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5584         else
5585                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5586
5587         return 0;
5588 }
5589
5590 static void
5591 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5592 {
5593         struct ixgbe_hw *hw =
5594                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5595         uint32_t ctrl;
5596
5597         PMD_INIT_FUNC_TRACE();
5598
5599         if (queue >= hw->mac.max_rx_queues)
5600                 return;
5601
5602         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5603         if (on)
5604                 ctrl |= IXGBE_RXDCTL_VME;
5605         else
5606                 ctrl &= ~IXGBE_RXDCTL_VME;
5607         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5608
5609         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5610 }
5611
5612 static int
5613 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5614 {
5615         struct ixgbe_rx_queue *rxq;
5616         uint16_t i;
5617         int on = 0;
5618
5619         /* VF function only support hw strip feature, others are not support */
5620         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
5621                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5622                         rxq = dev->data->rx_queues[i];
5623                         on = !!(rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP);
5624                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5625                 }
5626         }
5627
5628         return 0;
5629 }
5630
5631 static int
5632 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5633 {
5634         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5635
5636         ixgbevf_vlan_offload_config(dev, mask);
5637
5638         return 0;
5639 }
5640
5641 int
5642 ixgbe_vt_check(struct ixgbe_hw *hw)
5643 {
5644         uint32_t reg_val;
5645
5646         /* if Virtualization Technology is enabled */
5647         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5648         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5649                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5650                 return -1;
5651         }
5652
5653         return 0;
5654 }
5655
5656 static uint32_t
5657 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5658 {
5659         uint32_t vector = 0;
5660
5661         switch (hw->mac.mc_filter_type) {
5662         case 0:   /* use bits [47:36] of the address */
5663                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5664                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5665                 break;
5666         case 1:   /* use bits [46:35] of the address */
5667                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5668                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5669                 break;
5670         case 2:   /* use bits [45:34] of the address */
5671                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5672                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5673                 break;
5674         case 3:   /* use bits [43:32] of the address */
5675                 vector = ((uc_addr->addr_bytes[4]) |
5676                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5677                 break;
5678         default:  /* Invalid mc_filter_type */
5679                 break;
5680         }
5681
5682         /* vector can only be 12-bits or boundary will be exceeded */
5683         vector &= 0xFFF;
5684         return vector;
5685 }
5686
5687 static int
5688 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5689                         struct rte_ether_addr *mac_addr, uint8_t on)
5690 {
5691         uint32_t vector;
5692         uint32_t uta_idx;
5693         uint32_t reg_val;
5694         uint32_t uta_shift;
5695         uint32_t rc;
5696         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5697         const uint32_t ixgbe_uta_bit_shift = 5;
5698         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5699         const uint32_t bit1 = 0x1;
5700
5701         struct ixgbe_hw *hw =
5702                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5703         struct ixgbe_uta_info *uta_info =
5704                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5705
5706         /* The UTA table only exists on 82599 hardware and newer */
5707         if (hw->mac.type < ixgbe_mac_82599EB)
5708                 return -ENOTSUP;
5709
5710         vector = ixgbe_uta_vector(hw, mac_addr);
5711         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5712         uta_shift = vector & ixgbe_uta_bit_mask;
5713
5714         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5715         if (rc == on)
5716                 return 0;
5717
5718         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5719         if (on) {
5720                 uta_info->uta_in_use++;
5721                 reg_val |= (bit1 << uta_shift);
5722                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5723         } else {
5724                 uta_info->uta_in_use--;
5725                 reg_val &= ~(bit1 << uta_shift);
5726                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5727         }
5728
5729         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5730
5731         if (uta_info->uta_in_use > 0)
5732                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5733                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5734         else
5735                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5736
5737         return 0;
5738 }
5739
5740 static int
5741 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5742 {
5743         int i;
5744         struct ixgbe_hw *hw =
5745                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         struct ixgbe_uta_info *uta_info =
5747                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5748
5749         /* The UTA table only exists on 82599 hardware and newer */
5750         if (hw->mac.type < ixgbe_mac_82599EB)
5751                 return -ENOTSUP;
5752
5753         if (on) {
5754                 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5755                         uta_info->uta_shadow[i] = ~0;
5756                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5757                 }
5758         } else {
5759                 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5760                         uta_info->uta_shadow[i] = 0;
5761                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5762                 }
5763         }
5764         return 0;
5765
5766 }
5767
5768 uint32_t
5769 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5770 {
5771         uint32_t new_val = orig_val;
5772
5773         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG)
5774                 new_val |= IXGBE_VMOLR_AUPE;
5775         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC)
5776                 new_val |= IXGBE_VMOLR_ROMPE;
5777         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC)
5778                 new_val |= IXGBE_VMOLR_ROPE;
5779         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST)
5780                 new_val |= IXGBE_VMOLR_BAM;
5781         if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST)
5782                 new_val |= IXGBE_VMOLR_MPE;
5783
5784         return new_val;
5785 }
5786
5787 static int
5788 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5789 {
5790         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5791         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5792         struct ixgbe_interrupt *intr =
5793                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5794         struct ixgbe_hw *hw =
5795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5796         uint32_t vec = IXGBE_MISC_VEC_ID;
5797
5798         if (rte_intr_allow_others(intr_handle))
5799                 vec = IXGBE_RX_VEC_START;
5800         intr->mask |= (1 << vec);
5801         RTE_SET_USED(queue_id);
5802         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5803
5804         rte_intr_ack(intr_handle);
5805
5806         return 0;
5807 }
5808
5809 static int
5810 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5811 {
5812         struct ixgbe_interrupt *intr =
5813                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5814         struct ixgbe_hw *hw =
5815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5816         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5817         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5818         uint32_t vec = IXGBE_MISC_VEC_ID;
5819
5820         if (rte_intr_allow_others(intr_handle))
5821                 vec = IXGBE_RX_VEC_START;
5822         intr->mask &= ~(1 << vec);
5823         RTE_SET_USED(queue_id);
5824         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5825
5826         return 0;
5827 }
5828
5829 static int
5830 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5831 {
5832         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5833         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5834         uint32_t mask;
5835         struct ixgbe_hw *hw =
5836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5837         struct ixgbe_interrupt *intr =
5838                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5839
5840         if (queue_id < 16) {
5841                 ixgbe_disable_intr(hw);
5842                 intr->mask |= (1 << queue_id);
5843                 ixgbe_enable_intr(dev);
5844         } else if (queue_id < 32) {
5845                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5846                 mask &= (1 << queue_id);
5847                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5848         } else if (queue_id < 64) {
5849                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5850                 mask &= (1 << (queue_id - 32));
5851                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5852         }
5853         rte_intr_ack(intr_handle);
5854
5855         return 0;
5856 }
5857
5858 static int
5859 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5860 {
5861         uint32_t mask;
5862         struct ixgbe_hw *hw =
5863                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5864         struct ixgbe_interrupt *intr =
5865                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5866
5867         if (queue_id < 16) {
5868                 ixgbe_disable_intr(hw);
5869                 intr->mask &= ~(1 << queue_id);
5870                 ixgbe_enable_intr(dev);
5871         } else if (queue_id < 32) {
5872                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5873                 mask &= ~(1 << queue_id);
5874                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5875         } else if (queue_id < 64) {
5876                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5877                 mask &= ~(1 << (queue_id - 32));
5878                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5879         }
5880
5881         return 0;
5882 }
5883
5884 static void
5885 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5886                      uint8_t queue, uint8_t msix_vector)
5887 {
5888         uint32_t tmp, idx;
5889
5890         if (direction == -1) {
5891                 /* other causes */
5892                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5893                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5894                 tmp &= ~0xFF;
5895                 tmp |= msix_vector;
5896                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5897         } else {
5898                 /* rx or tx cause */
5899                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5900                 idx = ((16 * (queue & 1)) + (8 * direction));
5901                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5902                 tmp &= ~(0xFF << idx);
5903                 tmp |= (msix_vector << idx);
5904                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5905         }
5906 }
5907
5908 /**
5909  * set the IVAR registers, mapping interrupt causes to vectors
5910  * @param hw
5911  *  pointer to ixgbe_hw struct
5912  * @direction
5913  *  0 for Rx, 1 for Tx, -1 for other causes
5914  * @queue
5915  *  queue to map the corresponding interrupt to
5916  * @msix_vector
5917  *  the vector to map to the corresponding queue
5918  */
5919 static void
5920 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5921                    uint8_t queue, uint8_t msix_vector)
5922 {
5923         uint32_t tmp, idx;
5924
5925         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5926         if (hw->mac.type == ixgbe_mac_82598EB) {
5927                 if (direction == -1)
5928                         direction = 0;
5929                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5930                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5931                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5932                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5933                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5934         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5935                         (hw->mac.type == ixgbe_mac_X540) ||
5936                         (hw->mac.type == ixgbe_mac_X550) ||
5937                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5938                 if (direction == -1) {
5939                         /* other causes */
5940                         idx = ((queue & 1) * 8);
5941                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5942                         tmp &= ~(0xFF << idx);
5943                         tmp |= (msix_vector << idx);
5944                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5945                 } else {
5946                         /* rx or tx causes */
5947                         idx = ((16 * (queue & 1)) + (8 * direction));
5948                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5949                         tmp &= ~(0xFF << idx);
5950                         tmp |= (msix_vector << idx);
5951                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5952                 }
5953         }
5954 }
5955
5956 static void
5957 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5958 {
5959         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5960         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
5961         struct ixgbe_hw *hw =
5962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5963         uint32_t q_idx;
5964         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5965         uint32_t base = IXGBE_MISC_VEC_ID;
5966
5967         /* Configure VF other cause ivar */
5968         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5969
5970         /* won't configure msix register if no mapping is done
5971          * between intr vector and event fd.
5972          */
5973         if (!rte_intr_dp_is_en(intr_handle))
5974                 return;
5975
5976         if (rte_intr_allow_others(intr_handle)) {
5977                 base = IXGBE_RX_VEC_START;
5978                 vector_idx = IXGBE_RX_VEC_START;
5979         }
5980
5981         /* Configure all RX queues of VF */
5982         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5983                 /* Force all queue use vector 0,
5984                  * as IXGBE_VF_MAXMSIVECTOR = 1
5985                  */
5986                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5987                 rte_intr_vec_list_index_set(intr_handle, q_idx,
5988                                                    vector_idx);
5989                 if (vector_idx < base + rte_intr_nb_efd_get(intr_handle)
5990                     - 1)
5991                         vector_idx++;
5992         }
5993
5994         /* As RX queue setting above show, all queues use the vector 0.
5995          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5996          */
5997         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5998                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5999                         | IXGBE_EITR_CNT_WDIS);
6000 }
6001
6002 /**
6003  * Sets up the hardware to properly generate MSI-X interrupts
6004  * @hw
6005  *  board private structure
6006  */
6007 static void
6008 ixgbe_configure_msix(struct rte_eth_dev *dev)
6009 {
6010         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6011         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
6012         struct ixgbe_hw *hw =
6013                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6015         uint32_t vec = IXGBE_MISC_VEC_ID;
6016         uint32_t mask;
6017         uint32_t gpie;
6018
6019         /* won't configure msix register if no mapping is done
6020          * between intr vector and event fd
6021          * but if misx has been enabled already, need to configure
6022          * auto clean, auto mask and throttling.
6023          */
6024         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6025         if (!rte_intr_dp_is_en(intr_handle) &&
6026             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6027                 return;
6028
6029         if (rte_intr_allow_others(intr_handle))
6030                 vec = base = IXGBE_RX_VEC_START;
6031
6032         /* setup GPIE for MSI-x mode */
6033         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6034         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6035                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6036         /* auto clearing and auto setting corresponding bits in EIMS
6037          * when MSI-X interrupt is triggered
6038          */
6039         if (hw->mac.type == ixgbe_mac_82598EB) {
6040                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6041         } else {
6042                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6043                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6044         }
6045         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6046
6047         /* Populate the IVAR table and set the ITR values to the
6048          * corresponding register.
6049          */
6050         if (rte_intr_dp_is_en(intr_handle)) {
6051                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6052                         queue_id++) {
6053                         /* by default, 1:1 mapping */
6054                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6055                         rte_intr_vec_list_index_set(intr_handle,
6056                                                            queue_id, vec);
6057                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
6058                             - 1)
6059                                 vec++;
6060                 }
6061
6062                 switch (hw->mac.type) {
6063                 case ixgbe_mac_82598EB:
6064                         ixgbe_set_ivar_map(hw, -1,
6065                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6066                                            IXGBE_MISC_VEC_ID);
6067                         break;
6068                 case ixgbe_mac_82599EB:
6069                 case ixgbe_mac_X540:
6070                 case ixgbe_mac_X550:
6071                 case ixgbe_mac_X550EM_x:
6072                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6073                         break;
6074                 default:
6075                         break;
6076                 }
6077         }
6078         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6079                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6080                         | IXGBE_EITR_CNT_WDIS);
6081
6082         /* set up to autoclear timer, and the vectors */
6083         mask = IXGBE_EIMS_ENABLE_MASK;
6084         mask &= ~(IXGBE_EIMS_OTHER |
6085                   IXGBE_EIMS_MAILBOX |
6086                   IXGBE_EIMS_LSC);
6087
6088         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6089 }
6090
6091 int
6092 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6093                            uint16_t queue_idx, uint16_t tx_rate)
6094 {
6095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6096         uint32_t rf_dec, rf_int;
6097         uint32_t bcnrc_val;
6098         uint16_t link_speed = dev->data->dev_link.link_speed;
6099
6100         if (queue_idx >= hw->mac.max_tx_queues)
6101                 return -EINVAL;
6102
6103         if (tx_rate != 0) {
6104                 /* Calculate the rate factor values to set */
6105                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6106                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6107                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6108
6109                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6110                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6111                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6112                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6113         } else {
6114                 bcnrc_val = 0;
6115         }
6116
6117         /*
6118          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6119          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6120          * set as 0x4.
6121          */
6122         if (dev->data->mtu + IXGBE_ETH_OVERHEAD >= IXGBE_MAX_JUMBO_FRAME_SIZE)
6123                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_JUMBO_FRAME);
6124         else
6125                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, IXGBE_MMW_SIZE_DEFAULT);
6126
6127         /* Set RTTBCNRC of queue X */
6128         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6129         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6130         IXGBE_WRITE_FLUSH(hw);
6131
6132         return 0;
6133 }
6134
6135 static int
6136 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6137                      __rte_unused uint32_t index,
6138                      __rte_unused uint32_t pool)
6139 {
6140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6141         int diag;
6142
6143         /*
6144          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6145          * operation. Trap this case to avoid exhausting the [very limited]
6146          * set of PF resources used to store VF MAC addresses.
6147          */
6148         if (memcmp(hw->mac.perm_addr, mac_addr,
6149                         sizeof(struct rte_ether_addr)) == 0)
6150                 return -1;
6151         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6152         if (diag != 0)
6153                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6154                             RTE_ETHER_ADDR_PRT_FMT " - diag=%d",
6155                             RTE_ETHER_ADDR_BYTES(mac_addr), diag);
6156         return diag;
6157 }
6158
6159 static void
6160 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6161 {
6162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6163         struct rte_ether_addr *perm_addr =
6164                 (struct rte_ether_addr *)hw->mac.perm_addr;
6165         struct rte_ether_addr *mac_addr;
6166         uint32_t i;
6167         int diag;
6168
6169         /*
6170          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6171          * not support the deletion of a given MAC address.
6172          * Instead, it imposes to delete all MAC addresses, then to add again
6173          * all MAC addresses with the exception of the one to be deleted.
6174          */
6175         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6176
6177         /*
6178          * Add again all MAC addresses, with the exception of the deleted one
6179          * and of the permanent MAC address.
6180          */
6181         for (i = 0, mac_addr = dev->data->mac_addrs;
6182              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6183                 /* Skip the deleted MAC address */
6184                 if (i == index)
6185                         continue;
6186                 /* Skip NULL MAC addresses */
6187                 if (rte_is_zero_ether_addr(mac_addr))
6188                         continue;
6189                 /* Skip the permanent MAC address */
6190                 if (memcmp(perm_addr, mac_addr,
6191                                 sizeof(struct rte_ether_addr)) == 0)
6192                         continue;
6193                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6194                 if (diag != 0)
6195                         PMD_DRV_LOG(ERR,
6196                                     "Adding again MAC address "
6197                                      RTE_ETHER_ADDR_PRT_FMT " failed "
6198                                     "diag=%d", RTE_ETHER_ADDR_BYTES(mac_addr),
6199                                     diag);
6200         }
6201 }
6202
6203 static int
6204 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6205                         struct rte_ether_addr *addr)
6206 {
6207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6208
6209         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6210
6211         return 0;
6212 }
6213
6214 int
6215 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6216                         struct rte_eth_syn_filter *filter,
6217                         bool add)
6218 {
6219         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6220         struct ixgbe_filter_info *filter_info =
6221                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6222         uint32_t syn_info;
6223         uint32_t synqf;
6224
6225         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6226                 return -EINVAL;
6227
6228         syn_info = filter_info->syn_info;
6229
6230         if (add) {
6231                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6232                         return -EINVAL;
6233                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6234                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6235
6236                 if (filter->hig_pri)
6237                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6238                 else
6239                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6240         } else {
6241                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6242                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6243                         return -ENOENT;
6244                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6245         }
6246
6247         filter_info->syn_info = synqf;
6248         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6249         IXGBE_WRITE_FLUSH(hw);
6250         return 0;
6251 }
6252
6253
6254 static inline enum ixgbe_5tuple_protocol
6255 convert_protocol_type(uint8_t protocol_value)
6256 {
6257         if (protocol_value == IPPROTO_TCP)
6258                 return IXGBE_FILTER_PROTOCOL_TCP;
6259         else if (protocol_value == IPPROTO_UDP)
6260                 return IXGBE_FILTER_PROTOCOL_UDP;
6261         else if (protocol_value == IPPROTO_SCTP)
6262                 return IXGBE_FILTER_PROTOCOL_SCTP;
6263         else
6264                 return IXGBE_FILTER_PROTOCOL_NONE;
6265 }
6266
6267 /* inject a 5-tuple filter to HW */
6268 static inline void
6269 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6270                            struct ixgbe_5tuple_filter *filter)
6271 {
6272         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6273         int i;
6274         uint32_t ftqf, sdpqf;
6275         uint32_t l34timir = 0;
6276         uint8_t mask = 0xff;
6277
6278         i = filter->index;
6279
6280         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6281                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6282         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6283
6284         ftqf = (uint32_t)(filter->filter_info.proto &
6285                 IXGBE_FTQF_PROTOCOL_MASK);
6286         ftqf |= (uint32_t)((filter->filter_info.priority &
6287                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6288         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6289                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6290         if (filter->filter_info.dst_ip_mask == 0)
6291                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6292         if (filter->filter_info.src_port_mask == 0)
6293                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6294         if (filter->filter_info.dst_port_mask == 0)
6295                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6296         if (filter->filter_info.proto_mask == 0)
6297                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6298         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6299         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6300         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6301
6302         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6303         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6304         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6305         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6306
6307         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6308         l34timir |= (uint32_t)(filter->queue <<
6309                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6310         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6311 }
6312
6313 /*
6314  * add a 5tuple filter
6315  *
6316  * @param
6317  * dev: Pointer to struct rte_eth_dev.
6318  * index: the index the filter allocates.
6319  * filter: pointer to the filter that will be added.
6320  * rx_queue: the queue id the filter assigned to.
6321  *
6322  * @return
6323  *    - On success, zero.
6324  *    - On failure, a negative value.
6325  */
6326 static int
6327 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6328                         struct ixgbe_5tuple_filter *filter)
6329 {
6330         struct ixgbe_filter_info *filter_info =
6331                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6332         int i, idx, shift;
6333
6334         /*
6335          * look for an unused 5tuple filter index,
6336          * and insert the filter to list.
6337          */
6338         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6339                 idx = i / (sizeof(uint32_t) * NBBY);
6340                 shift = i % (sizeof(uint32_t) * NBBY);
6341                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6342                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6343                         filter->index = i;
6344                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6345                                           filter,
6346                                           entries);
6347                         break;
6348                 }
6349         }
6350         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6351                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6352                 return -ENOSYS;
6353         }
6354
6355         ixgbe_inject_5tuple_filter(dev, filter);
6356
6357         return 0;
6358 }
6359
6360 /*
6361  * remove a 5tuple filter
6362  *
6363  * @param
6364  * dev: Pointer to struct rte_eth_dev.
6365  * filter: the pointer of the filter will be removed.
6366  */
6367 static void
6368 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6369                         struct ixgbe_5tuple_filter *filter)
6370 {
6371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6372         struct ixgbe_filter_info *filter_info =
6373                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6374         uint16_t index = filter->index;
6375
6376         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6377                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6378         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6379         rte_free(filter);
6380
6381         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6382         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6383         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6384         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6385         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6386 }
6387
6388 static int
6389 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6390 {
6391         struct ixgbe_hw *hw;
6392         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6393         struct rte_eth_dev_data *dev_data = dev->data;
6394
6395         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6396
6397         if (mtu < RTE_ETHER_MIN_MTU || max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6398                 return -EINVAL;
6399
6400         /* If device is started, refuse mtu that requires the support of
6401          * scattered packets when this feature has not been enabled before.
6402          */
6403         if (dev_data->dev_started && !dev_data->scattered_rx &&
6404             (max_frame + 2 * RTE_VLAN_HLEN >
6405                         dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6406                 PMD_INIT_LOG(ERR, "Stop port first.");
6407                 return -EINVAL;
6408         }
6409
6410         /*
6411          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6412          * request of the version 2.0 of the mailbox API.
6413          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6414          * of the mailbox API.
6415          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6416          * prior to 3.11.33 which contains the following change:
6417          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6418          */
6419         if (ixgbevf_rlpml_set_vf(hw, max_frame))
6420                 return -EINVAL;
6421
6422         return 0;
6423 }
6424
6425 static inline struct ixgbe_5tuple_filter *
6426 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6427                         struct ixgbe_5tuple_filter_info *key)
6428 {
6429         struct ixgbe_5tuple_filter *it;
6430
6431         TAILQ_FOREACH(it, filter_list, entries) {
6432                 if (memcmp(key, &it->filter_info,
6433                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6434                         return it;
6435                 }
6436         }
6437         return NULL;
6438 }
6439
6440 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6441 static inline int
6442 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6443                         struct ixgbe_5tuple_filter_info *filter_info)
6444 {
6445         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6446                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6447                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6448                 return -EINVAL;
6449
6450         switch (filter->dst_ip_mask) {
6451         case UINT32_MAX:
6452                 filter_info->dst_ip_mask = 0;
6453                 filter_info->dst_ip = filter->dst_ip;
6454                 break;
6455         case 0:
6456                 filter_info->dst_ip_mask = 1;
6457                 break;
6458         default:
6459                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6460                 return -EINVAL;
6461         }
6462
6463         switch (filter->src_ip_mask) {
6464         case UINT32_MAX:
6465                 filter_info->src_ip_mask = 0;
6466                 filter_info->src_ip = filter->src_ip;
6467                 break;
6468         case 0:
6469                 filter_info->src_ip_mask = 1;
6470                 break;
6471         default:
6472                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6473                 return -EINVAL;
6474         }
6475
6476         switch (filter->dst_port_mask) {
6477         case UINT16_MAX:
6478                 filter_info->dst_port_mask = 0;
6479                 filter_info->dst_port = filter->dst_port;
6480                 break;
6481         case 0:
6482                 filter_info->dst_port_mask = 1;
6483                 break;
6484         default:
6485                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6486                 return -EINVAL;
6487         }
6488
6489         switch (filter->src_port_mask) {
6490         case UINT16_MAX:
6491                 filter_info->src_port_mask = 0;
6492                 filter_info->src_port = filter->src_port;
6493                 break;
6494         case 0:
6495                 filter_info->src_port_mask = 1;
6496                 break;
6497         default:
6498                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6499                 return -EINVAL;
6500         }
6501
6502         switch (filter->proto_mask) {
6503         case UINT8_MAX:
6504                 filter_info->proto_mask = 0;
6505                 filter_info->proto =
6506                         convert_protocol_type(filter->proto);
6507                 break;
6508         case 0:
6509                 filter_info->proto_mask = 1;
6510                 break;
6511         default:
6512                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6513                 return -EINVAL;
6514         }
6515
6516         filter_info->priority = (uint8_t)filter->priority;
6517         return 0;
6518 }
6519
6520 /*
6521  * add or delete a ntuple filter
6522  *
6523  * @param
6524  * dev: Pointer to struct rte_eth_dev.
6525  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6526  * add: if true, add filter, if false, remove filter
6527  *
6528  * @return
6529  *    - On success, zero.
6530  *    - On failure, a negative value.
6531  */
6532 int
6533 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6534                         struct rte_eth_ntuple_filter *ntuple_filter,
6535                         bool add)
6536 {
6537         struct ixgbe_filter_info *filter_info =
6538                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6539         struct ixgbe_5tuple_filter_info filter_5tuple;
6540         struct ixgbe_5tuple_filter *filter;
6541         int ret;
6542
6543         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6544                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6545                 return -EINVAL;
6546         }
6547
6548         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6549         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6550         if (ret < 0)
6551                 return ret;
6552
6553         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6554                                          &filter_5tuple);
6555         if (filter != NULL && add) {
6556                 PMD_DRV_LOG(ERR, "filter exists.");
6557                 return -EEXIST;
6558         }
6559         if (filter == NULL && !add) {
6560                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6561                 return -ENOENT;
6562         }
6563
6564         if (add) {
6565                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6566                                 sizeof(struct ixgbe_5tuple_filter), 0);
6567                 if (filter == NULL)
6568                         return -ENOMEM;
6569                 rte_memcpy(&filter->filter_info,
6570                                  &filter_5tuple,
6571                                  sizeof(struct ixgbe_5tuple_filter_info));
6572                 filter->queue = ntuple_filter->queue;
6573                 ret = ixgbe_add_5tuple_filter(dev, filter);
6574                 if (ret < 0) {
6575                         rte_free(filter);
6576                         return ret;
6577                 }
6578         } else
6579                 ixgbe_remove_5tuple_filter(dev, filter);
6580
6581         return 0;
6582 }
6583
6584 int
6585 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6586                         struct rte_eth_ethertype_filter *filter,
6587                         bool add)
6588 {
6589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590         struct ixgbe_filter_info *filter_info =
6591                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6592         uint32_t etqf = 0;
6593         uint32_t etqs = 0;
6594         int ret;
6595         struct ixgbe_ethertype_filter ethertype_filter;
6596
6597         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6598                 return -EINVAL;
6599
6600         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6601                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6602                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6603                         " ethertype filter.", filter->ether_type);
6604                 return -EINVAL;
6605         }
6606
6607         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6608                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6609                 return -EINVAL;
6610         }
6611         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6612                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6613                 return -EINVAL;
6614         }
6615
6616         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6617         if (ret >= 0 && add) {
6618                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6619                             filter->ether_type);
6620                 return -EEXIST;
6621         }
6622         if (ret < 0 && !add) {
6623                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6624                             filter->ether_type);
6625                 return -ENOENT;
6626         }
6627
6628         if (add) {
6629                 etqf = IXGBE_ETQF_FILTER_EN;
6630                 etqf |= (uint32_t)filter->ether_type;
6631                 etqs |= (uint32_t)((filter->queue <<
6632                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6633                                     IXGBE_ETQS_RX_QUEUE);
6634                 etqs |= IXGBE_ETQS_QUEUE_EN;
6635
6636                 ethertype_filter.ethertype = filter->ether_type;
6637                 ethertype_filter.etqf = etqf;
6638                 ethertype_filter.etqs = etqs;
6639                 ethertype_filter.conf = FALSE;
6640                 ret = ixgbe_ethertype_filter_insert(filter_info,
6641                                                     &ethertype_filter);
6642                 if (ret < 0) {
6643                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6644                         return -ENOSPC;
6645                 }
6646         } else {
6647                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6648                 if (ret < 0)
6649                         return -ENOSYS;
6650         }
6651         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6652         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6653         IXGBE_WRITE_FLUSH(hw);
6654
6655         return 0;
6656 }
6657
6658 static int
6659 ixgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
6660                        const struct rte_flow_ops **ops)
6661 {
6662         *ops = &ixgbe_flow_ops;
6663         return 0;
6664 }
6665
6666 static u8 *
6667 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6668                         u8 **mc_addr_ptr, u32 *vmdq)
6669 {
6670         u8 *mc_addr;
6671
6672         *vmdq = 0;
6673         mc_addr = *mc_addr_ptr;
6674         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6675         return mc_addr;
6676 }
6677
6678 static int
6679 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6680                           struct rte_ether_addr *mc_addr_set,
6681                           uint32_t nb_mc_addr)
6682 {
6683         struct ixgbe_hw *hw;
6684         u8 *mc_addr_list;
6685
6686         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6687         mc_addr_list = (u8 *)mc_addr_set;
6688         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6689                                          ixgbe_dev_addr_list_itr, TRUE);
6690 }
6691
6692 static uint64_t
6693 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6694 {
6695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6696         uint64_t systime_cycles;
6697
6698         switch (hw->mac.type) {
6699         case ixgbe_mac_X550:
6700         case ixgbe_mac_X550EM_x:
6701         case ixgbe_mac_X550EM_a:
6702                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6703                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6704                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6705                                 * NSEC_PER_SEC;
6706                 break;
6707         default:
6708                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6709                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6710                                 << 32;
6711         }
6712
6713         return systime_cycles;
6714 }
6715
6716 static uint64_t
6717 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6718 {
6719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6720         uint64_t rx_tstamp_cycles;
6721
6722         switch (hw->mac.type) {
6723         case ixgbe_mac_X550:
6724         case ixgbe_mac_X550EM_x:
6725         case ixgbe_mac_X550EM_a:
6726                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6727                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6728                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6729                                 * NSEC_PER_SEC;
6730                 break;
6731         default:
6732                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6733                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6734                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6735                                 << 32;
6736         }
6737
6738         return rx_tstamp_cycles;
6739 }
6740
6741 static uint64_t
6742 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6743 {
6744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6745         uint64_t tx_tstamp_cycles;
6746
6747         switch (hw->mac.type) {
6748         case ixgbe_mac_X550:
6749         case ixgbe_mac_X550EM_x:
6750         case ixgbe_mac_X550EM_a:
6751                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6752                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6753                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6754                                 * NSEC_PER_SEC;
6755                 break;
6756         default:
6757                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6758                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6759                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6760                                 << 32;
6761         }
6762
6763         return tx_tstamp_cycles;
6764 }
6765
6766 static void
6767 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6768 {
6769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6770         struct ixgbe_adapter *adapter = dev->data->dev_private;
6771         struct rte_eth_link link;
6772         uint32_t incval = 0;
6773         uint32_t shift = 0;
6774
6775         /* Get current link speed. */
6776         ixgbe_dev_link_update(dev, 1);
6777         rte_eth_linkstatus_get(dev, &link);
6778
6779         switch (link.link_speed) {
6780         case RTE_ETH_SPEED_NUM_100M:
6781                 incval = IXGBE_INCVAL_100;
6782                 shift = IXGBE_INCVAL_SHIFT_100;
6783                 break;
6784         case RTE_ETH_SPEED_NUM_1G:
6785                 incval = IXGBE_INCVAL_1GB;
6786                 shift = IXGBE_INCVAL_SHIFT_1GB;
6787                 break;
6788         case RTE_ETH_SPEED_NUM_10G:
6789         default:
6790                 incval = IXGBE_INCVAL_10GB;
6791                 shift = IXGBE_INCVAL_SHIFT_10GB;
6792                 break;
6793         }
6794
6795         switch (hw->mac.type) {
6796         case ixgbe_mac_X550:
6797         case ixgbe_mac_X550EM_x:
6798         case ixgbe_mac_X550EM_a:
6799                 /* Independent of link speed. */
6800                 incval = 1;
6801                 /* Cycles read will be interpreted as ns. */
6802                 shift = 0;
6803                 /* Fall-through */
6804         case ixgbe_mac_X540:
6805                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6806                 break;
6807         case ixgbe_mac_82599EB:
6808                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6809                 shift -= IXGBE_INCVAL_SHIFT_82599;
6810                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6811                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6812                 break;
6813         default:
6814                 /* Not supported. */
6815                 return;
6816         }
6817
6818         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6819         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6820         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6821
6822         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6823         adapter->systime_tc.cc_shift = shift;
6824         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6825
6826         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6827         adapter->rx_tstamp_tc.cc_shift = shift;
6828         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6829
6830         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6831         adapter->tx_tstamp_tc.cc_shift = shift;
6832         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6833 }
6834
6835 static int
6836 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6837 {
6838         struct ixgbe_adapter *adapter = dev->data->dev_private;
6839
6840         adapter->systime_tc.nsec += delta;
6841         adapter->rx_tstamp_tc.nsec += delta;
6842         adapter->tx_tstamp_tc.nsec += delta;
6843
6844         return 0;
6845 }
6846
6847 static int
6848 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6849 {
6850         uint64_t ns;
6851         struct ixgbe_adapter *adapter = dev->data->dev_private;
6852
6853         ns = rte_timespec_to_ns(ts);
6854         /* Set the timecounters to a new value. */
6855         adapter->systime_tc.nsec = ns;
6856         adapter->rx_tstamp_tc.nsec = ns;
6857         adapter->tx_tstamp_tc.nsec = ns;
6858
6859         return 0;
6860 }
6861
6862 static int
6863 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6864 {
6865         uint64_t ns, systime_cycles;
6866         struct ixgbe_adapter *adapter = dev->data->dev_private;
6867
6868         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6869         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6870         *ts = rte_ns_to_timespec(ns);
6871
6872         return 0;
6873 }
6874
6875 static int
6876 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6877 {
6878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6879         uint32_t tsync_ctl;
6880         uint32_t tsauxc;
6881
6882         /* Stop the timesync system time. */
6883         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6884         /* Reset the timesync system time value. */
6885         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6886         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6887
6888         /* Enable system time for platforms where it isn't on by default. */
6889         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6890         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6891         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6892
6893         ixgbe_start_timecounters(dev);
6894
6895         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6896         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6897                         (RTE_ETHER_TYPE_1588 |
6898                          IXGBE_ETQF_FILTER_EN |
6899                          IXGBE_ETQF_1588));
6900
6901         /* Enable timestamping of received PTP packets. */
6902         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6903         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6904         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6905
6906         /* Enable timestamping of transmitted PTP packets. */
6907         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6908         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6909         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6910
6911         IXGBE_WRITE_FLUSH(hw);
6912
6913         return 0;
6914 }
6915
6916 static int
6917 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6918 {
6919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6920         uint32_t tsync_ctl;
6921
6922         /* Disable timestamping of transmitted PTP packets. */
6923         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6924         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6925         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6926
6927         /* Disable timestamping of received PTP packets. */
6928         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6929         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6930         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6931
6932         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6933         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6934
6935         /* Stop incrementing the System Time registers. */
6936         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6937
6938         return 0;
6939 }
6940
6941 static int
6942 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6943                                  struct timespec *timestamp,
6944                                  uint32_t flags __rte_unused)
6945 {
6946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947         struct ixgbe_adapter *adapter = dev->data->dev_private;
6948         uint32_t tsync_rxctl;
6949         uint64_t rx_tstamp_cycles;
6950         uint64_t ns;
6951
6952         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6953         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6954                 return -EINVAL;
6955
6956         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6957         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6958         *timestamp = rte_ns_to_timespec(ns);
6959
6960         return  0;
6961 }
6962
6963 static int
6964 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6965                                  struct timespec *timestamp)
6966 {
6967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6968         struct ixgbe_adapter *adapter = dev->data->dev_private;
6969         uint32_t tsync_txctl;
6970         uint64_t tx_tstamp_cycles;
6971         uint64_t ns;
6972
6973         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6974         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6975                 return -EINVAL;
6976
6977         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6978         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6979         *timestamp = rte_ns_to_timespec(ns);
6980
6981         return 0;
6982 }
6983
6984 static int
6985 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6986 {
6987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6988         int count = 0;
6989         int g_ind = 0;
6990         const struct reg_info *reg_group;
6991         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6992                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6993
6994         while ((reg_group = reg_set[g_ind++]))
6995                 count += ixgbe_regs_group_count(reg_group);
6996
6997         return count;
6998 }
6999
7000 static int
7001 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7002 {
7003         int count = 0;
7004         int g_ind = 0;
7005         const struct reg_info *reg_group;
7006
7007         while ((reg_group = ixgbevf_regs[g_ind++]))
7008                 count += ixgbe_regs_group_count(reg_group);
7009
7010         return count;
7011 }
7012
7013 static int
7014 ixgbe_get_regs(struct rte_eth_dev *dev,
7015               struct rte_dev_reg_info *regs)
7016 {
7017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7018         uint32_t *data = regs->data;
7019         int g_ind = 0;
7020         int count = 0;
7021         const struct reg_info *reg_group;
7022         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7023                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7024
7025         if (data == NULL) {
7026                 regs->length = ixgbe_get_reg_length(dev);
7027                 regs->width = sizeof(uint32_t);
7028                 return 0;
7029         }
7030
7031         /* Support only full register dump */
7032         if ((regs->length == 0) ||
7033             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7034                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7035                         hw->device_id;
7036                 while ((reg_group = reg_set[g_ind++]))
7037                         count += ixgbe_read_regs_group(dev, &data[count],
7038                                 reg_group);
7039                 return 0;
7040         }
7041
7042         return -ENOTSUP;
7043 }
7044
7045 static int
7046 ixgbevf_get_regs(struct rte_eth_dev *dev,
7047                 struct rte_dev_reg_info *regs)
7048 {
7049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7050         uint32_t *data = regs->data;
7051         int g_ind = 0;
7052         int count = 0;
7053         const struct reg_info *reg_group;
7054
7055         if (data == NULL) {
7056                 regs->length = ixgbevf_get_reg_length(dev);
7057                 regs->width = sizeof(uint32_t);
7058                 return 0;
7059         }
7060
7061         /* Support only full register dump */
7062         if ((regs->length == 0) ||
7063             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7064                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7065                         hw->device_id;
7066                 while ((reg_group = ixgbevf_regs[g_ind++]))
7067                         count += ixgbe_read_regs_group(dev, &data[count],
7068                                                       reg_group);
7069                 return 0;
7070         }
7071
7072         return -ENOTSUP;
7073 }
7074
7075 static int
7076 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7077 {
7078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7079
7080         /* Return unit is byte count */
7081         return hw->eeprom.word_size * 2;
7082 }
7083
7084 static int
7085 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7086                 struct rte_dev_eeprom_info *in_eeprom)
7087 {
7088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7089         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7090         uint16_t *data = in_eeprom->data;
7091         int first, length;
7092
7093         first = in_eeprom->offset >> 1;
7094         length = in_eeprom->length >> 1;
7095         if ((first > hw->eeprom.word_size) ||
7096             ((first + length) > hw->eeprom.word_size))
7097                 return -EINVAL;
7098
7099         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7100
7101         return eeprom->ops.read_buffer(hw, first, length, data);
7102 }
7103
7104 static int
7105 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7106                 struct rte_dev_eeprom_info *in_eeprom)
7107 {
7108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7109         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7110         uint16_t *data = in_eeprom->data;
7111         int first, length;
7112
7113         first = in_eeprom->offset >> 1;
7114         length = in_eeprom->length >> 1;
7115         if ((first > hw->eeprom.word_size) ||
7116             ((first + length) > hw->eeprom.word_size))
7117                 return -EINVAL;
7118
7119         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7120
7121         return eeprom->ops.write_buffer(hw,  first, length, data);
7122 }
7123
7124 static int
7125 ixgbe_get_module_info(struct rte_eth_dev *dev,
7126                       struct rte_eth_dev_module_info *modinfo)
7127 {
7128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7129         uint32_t status;
7130         uint8_t sff8472_rev, addr_mode;
7131         bool page_swap = false;
7132
7133         /* Check whether we support SFF-8472 or not */
7134         status = hw->phy.ops.read_i2c_eeprom(hw,
7135                                              IXGBE_SFF_SFF_8472_COMP,
7136                                              &sff8472_rev);
7137         if (status != 0)
7138                 return -EIO;
7139
7140         /* addressing mode is not supported */
7141         status = hw->phy.ops.read_i2c_eeprom(hw,
7142                                              IXGBE_SFF_SFF_8472_SWAP,
7143                                              &addr_mode);
7144         if (status != 0)
7145                 return -EIO;
7146
7147         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7148                 PMD_DRV_LOG(ERR,
7149                             "Address change required to access page 0xA2, "
7150                             "but not supported. Please report the module "
7151                             "type to the driver maintainers.");
7152                 page_swap = true;
7153         }
7154
7155         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7156                 /* We have a SFP, but it does not support SFF-8472 */
7157                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7158                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7159         } else {
7160                 /* We have a SFP which supports a revision of SFF-8472. */
7161                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7162                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7163         }
7164
7165         return 0;
7166 }
7167
7168 static int
7169 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7170                         struct rte_dev_eeprom_info *info)
7171 {
7172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7173         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7174         uint8_t databyte = 0xFF;
7175         uint8_t *data = info->data;
7176         uint32_t i = 0;
7177
7178         for (i = info->offset; i < info->offset + info->length; i++) {
7179                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7180                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7181                 else
7182                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7183
7184                 if (status != 0)
7185                         return -EIO;
7186
7187                 data[i - info->offset] = databyte;
7188         }
7189
7190         return 0;
7191 }
7192
7193 uint16_t
7194 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7195         switch (mac_type) {
7196         case ixgbe_mac_X550:
7197         case ixgbe_mac_X550EM_x:
7198         case ixgbe_mac_X550EM_a:
7199                 return RTE_ETH_RSS_RETA_SIZE_512;
7200         case ixgbe_mac_X550_vf:
7201         case ixgbe_mac_X550EM_x_vf:
7202         case ixgbe_mac_X550EM_a_vf:
7203                 return RTE_ETH_RSS_RETA_SIZE_64;
7204         case ixgbe_mac_X540_vf:
7205         case ixgbe_mac_82599_vf:
7206                 return 0;
7207         default:
7208                 return RTE_ETH_RSS_RETA_SIZE_128;
7209         }
7210 }
7211
7212 uint32_t
7213 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7214         switch (mac_type) {
7215         case ixgbe_mac_X550:
7216         case ixgbe_mac_X550EM_x:
7217         case ixgbe_mac_X550EM_a:
7218                 if (reta_idx < RTE_ETH_RSS_RETA_SIZE_128)
7219                         return IXGBE_RETA(reta_idx >> 2);
7220                 else
7221                         return IXGBE_ERETA((reta_idx - RTE_ETH_RSS_RETA_SIZE_128) >> 2);
7222         case ixgbe_mac_X550_vf:
7223         case ixgbe_mac_X550EM_x_vf:
7224         case ixgbe_mac_X550EM_a_vf:
7225                 return IXGBE_VFRETA(reta_idx >> 2);
7226         default:
7227                 return IXGBE_RETA(reta_idx >> 2);
7228         }
7229 }
7230
7231 uint32_t
7232 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7233         switch (mac_type) {
7234         case ixgbe_mac_X550_vf:
7235         case ixgbe_mac_X550EM_x_vf:
7236         case ixgbe_mac_X550EM_a_vf:
7237                 return IXGBE_VFMRQC;
7238         default:
7239                 return IXGBE_MRQC;
7240         }
7241 }
7242
7243 uint32_t
7244 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7245         switch (mac_type) {
7246         case ixgbe_mac_X550_vf:
7247         case ixgbe_mac_X550EM_x_vf:
7248         case ixgbe_mac_X550EM_a_vf:
7249                 return IXGBE_VFRSSRK(i);
7250         default:
7251                 return IXGBE_RSSRK(i);
7252         }
7253 }
7254
7255 bool
7256 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7257         switch (mac_type) {
7258         case ixgbe_mac_82599_vf:
7259         case ixgbe_mac_X540_vf:
7260                 return 0;
7261         default:
7262                 return 1;
7263         }
7264 }
7265
7266 static int
7267 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7268                         struct rte_eth_dcb_info *dcb_info)
7269 {
7270         struct ixgbe_dcb_config *dcb_config =
7271                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7272         struct ixgbe_dcb_tc_config *tc;
7273         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7274         uint8_t nb_tcs;
7275         uint8_t i, j;
7276
7277         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
7278                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7279         else
7280                 dcb_info->nb_tcs = 1;
7281
7282         tc_queue = &dcb_info->tc_queue;
7283         nb_tcs = dcb_info->nb_tcs;
7284
7285         if (dcb_config->vt_mode) { /* vt is enabled*/
7286                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7287                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7288                 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++)
7289                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7290                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7291                         for (j = 0; j < nb_tcs; j++) {
7292                                 tc_queue->tc_rxq[0][j].base = j;
7293                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7294                                 tc_queue->tc_txq[0][j].base = j;
7295                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7296                         }
7297                 } else {
7298                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7299                                 for (j = 0; j < nb_tcs; j++) {
7300                                         tc_queue->tc_rxq[i][j].base =
7301                                                 i * nb_tcs + j;
7302                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7303                                         tc_queue->tc_txq[i][j].base =
7304                                                 i * nb_tcs + j;
7305                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7306                                 }
7307                         }
7308                 }
7309         } else { /* vt is disabled*/
7310                 struct rte_eth_dcb_rx_conf *rx_conf =
7311                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7312                 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++)
7313                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7314                 if (dcb_info->nb_tcs == RTE_ETH_4_TCS) {
7315                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7316                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7317                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7318                         }
7319                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7320                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7321                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7322                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7323                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7324                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7325                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7326                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7327                 } else if (dcb_info->nb_tcs == RTE_ETH_8_TCS) {
7328                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7329                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7330                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7331                         }
7332                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7333                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7334                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7335                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7336                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7337                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7338                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7339                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7340                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7341                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7342                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7343                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7344                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7345                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7346                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7347                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7348                 }
7349         }
7350         for (i = 0; i < dcb_info->nb_tcs; i++) {
7351                 tc = &dcb_config->tc_config[i];
7352                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7353         }
7354         return 0;
7355 }
7356
7357 /* Update e-tag ether type */
7358 static int
7359 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7360                             uint16_t ether_type)
7361 {
7362         uint32_t etag_etype;
7363
7364         if (hw->mac.type != ixgbe_mac_X550 &&
7365             hw->mac.type != ixgbe_mac_X550EM_x &&
7366             hw->mac.type != ixgbe_mac_X550EM_a) {
7367                 return -ENOTSUP;
7368         }
7369
7370         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7371         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7372         etag_etype |= ether_type;
7373         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7374         IXGBE_WRITE_FLUSH(hw);
7375
7376         return 0;
7377 }
7378
7379 /* Enable e-tag tunnel */
7380 static int
7381 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7382 {
7383         uint32_t etag_etype;
7384
7385         if (hw->mac.type != ixgbe_mac_X550 &&
7386             hw->mac.type != ixgbe_mac_X550EM_x &&
7387             hw->mac.type != ixgbe_mac_X550EM_a) {
7388                 return -ENOTSUP;
7389         }
7390
7391         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7392         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7393         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7394         IXGBE_WRITE_FLUSH(hw);
7395
7396         return 0;
7397 }
7398
7399 static int
7400 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7401                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7402 {
7403         int ret = 0;
7404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7405         uint32_t i, rar_entries;
7406         uint32_t rar_low, rar_high;
7407
7408         if (hw->mac.type != ixgbe_mac_X550 &&
7409             hw->mac.type != ixgbe_mac_X550EM_x &&
7410             hw->mac.type != ixgbe_mac_X550EM_a) {
7411                 return -ENOTSUP;
7412         }
7413
7414         rar_entries = ixgbe_get_num_rx_addrs(hw);
7415
7416         for (i = 1; i < rar_entries; i++) {
7417                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7418                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7419                 if ((rar_high & IXGBE_RAH_AV) &&
7420                     (rar_high & IXGBE_RAH_ADTYPE) &&
7421                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7422                      l2_tunnel->tunnel_id)) {
7423                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7424                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7425
7426                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7427
7428                         return ret;
7429                 }
7430         }
7431
7432         return ret;
7433 }
7434
7435 static int
7436 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7437                        struct ixgbe_l2_tunnel_conf *l2_tunnel)
7438 {
7439         int ret = 0;
7440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7441         uint32_t i, rar_entries;
7442         uint32_t rar_low, rar_high;
7443
7444         if (hw->mac.type != ixgbe_mac_X550 &&
7445             hw->mac.type != ixgbe_mac_X550EM_x &&
7446             hw->mac.type != ixgbe_mac_X550EM_a) {
7447                 return -ENOTSUP;
7448         }
7449
7450         /* One entry for one tunnel. Try to remove potential existing entry. */
7451         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7452
7453         rar_entries = ixgbe_get_num_rx_addrs(hw);
7454
7455         for (i = 1; i < rar_entries; i++) {
7456                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7457                 if (rar_high & IXGBE_RAH_AV) {
7458                         continue;
7459                 } else {
7460                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7461                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7462                         rar_low = l2_tunnel->tunnel_id;
7463
7464                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7465                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7466
7467                         return ret;
7468                 }
7469         }
7470
7471         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7472                      " Please remove a rule before adding a new one.");
7473         return -EINVAL;
7474 }
7475
7476 static inline struct ixgbe_l2_tn_filter *
7477 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7478                           struct ixgbe_l2_tn_key *key)
7479 {
7480         int ret;
7481
7482         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7483         if (ret < 0)
7484                 return NULL;
7485
7486         return l2_tn_info->hash_map[ret];
7487 }
7488
7489 static inline int
7490 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7491                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7492 {
7493         int ret;
7494
7495         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7496                                &l2_tn_filter->key);
7497
7498         if (ret < 0) {
7499                 PMD_DRV_LOG(ERR,
7500                             "Failed to insert L2 tunnel filter"
7501                             " to hash table %d!",
7502                             ret);
7503                 return ret;
7504         }
7505
7506         l2_tn_info->hash_map[ret] = l2_tn_filter;
7507
7508         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7509
7510         return 0;
7511 }
7512
7513 static inline int
7514 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7515                           struct ixgbe_l2_tn_key *key)
7516 {
7517         int ret;
7518         struct ixgbe_l2_tn_filter *l2_tn_filter;
7519
7520         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7521
7522         if (ret < 0) {
7523                 PMD_DRV_LOG(ERR,
7524                             "No such L2 tunnel filter to delete %d!",
7525                             ret);
7526                 return ret;
7527         }
7528
7529         l2_tn_filter = l2_tn_info->hash_map[ret];
7530         l2_tn_info->hash_map[ret] = NULL;
7531
7532         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7533         rte_free(l2_tn_filter);
7534
7535         return 0;
7536 }
7537
7538 /* Add l2 tunnel filter */
7539 int
7540 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7541                                struct ixgbe_l2_tunnel_conf *l2_tunnel,
7542                                bool restore)
7543 {
7544         int ret;
7545         struct ixgbe_l2_tn_info *l2_tn_info =
7546                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7547         struct ixgbe_l2_tn_key key;
7548         struct ixgbe_l2_tn_filter *node;
7549
7550         if (!restore) {
7551                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7552                 key.tn_id = l2_tunnel->tunnel_id;
7553
7554                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7555
7556                 if (node) {
7557                         PMD_DRV_LOG(ERR,
7558                                     "The L2 tunnel filter already exists!");
7559                         return -EINVAL;
7560                 }
7561
7562                 node = rte_zmalloc("ixgbe_l2_tn",
7563                                    sizeof(struct ixgbe_l2_tn_filter),
7564                                    0);
7565                 if (!node)
7566                         return -ENOMEM;
7567
7568                 rte_memcpy(&node->key,
7569                                  &key,
7570                                  sizeof(struct ixgbe_l2_tn_key));
7571                 node->pool = l2_tunnel->pool;
7572                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7573                 if (ret < 0) {
7574                         rte_free(node);
7575                         return ret;
7576                 }
7577         }
7578
7579         switch (l2_tunnel->l2_tunnel_type) {
7580         case RTE_ETH_L2_TUNNEL_TYPE_E_TAG:
7581                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7582                 break;
7583         default:
7584                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7585                 ret = -EINVAL;
7586                 break;
7587         }
7588
7589         if ((!restore) && (ret < 0))
7590                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7591
7592         return ret;
7593 }
7594
7595 /* Delete l2 tunnel filter */
7596 int
7597 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7598                                struct ixgbe_l2_tunnel_conf *l2_tunnel)
7599 {
7600         int ret;
7601         struct ixgbe_l2_tn_info *l2_tn_info =
7602                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7603         struct ixgbe_l2_tn_key key;
7604
7605         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7606         key.tn_id = l2_tunnel->tunnel_id;
7607         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7608         if (ret < 0)
7609                 return ret;
7610
7611         switch (l2_tunnel->l2_tunnel_type) {
7612         case RTE_ETH_L2_TUNNEL_TYPE_E_TAG:
7613                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7614                 break;
7615         default:
7616                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7617                 ret = -EINVAL;
7618                 break;
7619         }
7620
7621         return ret;
7622 }
7623
7624 static int
7625 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7626 {
7627         int ret = 0;
7628         uint32_t ctrl;
7629         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7630
7631         if (hw->mac.type != ixgbe_mac_X550 &&
7632             hw->mac.type != ixgbe_mac_X550EM_x &&
7633             hw->mac.type != ixgbe_mac_X550EM_a) {
7634                 return -ENOTSUP;
7635         }
7636
7637         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7638         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7639         if (en)
7640                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7641         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7642
7643         return ret;
7644 }
7645
7646 static int
7647 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7648                         uint16_t port)
7649 {
7650         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7651         IXGBE_WRITE_FLUSH(hw);
7652
7653         return 0;
7654 }
7655
7656 /* There's only one register for VxLAN UDP port.
7657  * So, we cannot add several ports. Will update it.
7658  */
7659 static int
7660 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7661                      uint16_t port)
7662 {
7663         if (port == 0) {
7664                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7665                 return -EINVAL;
7666         }
7667
7668         return ixgbe_update_vxlan_port(hw, port);
7669 }
7670
7671 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7672  * UDP port, it must have a value.
7673  * So, will reset it to the original value 0.
7674  */
7675 static int
7676 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7677                      uint16_t port)
7678 {
7679         uint16_t cur_port;
7680
7681         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7682
7683         if (cur_port != port) {
7684                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7685                 return -EINVAL;
7686         }
7687
7688         return ixgbe_update_vxlan_port(hw, 0);
7689 }
7690
7691 /* Add UDP tunneling port */
7692 static int
7693 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7694                               struct rte_eth_udp_tunnel *udp_tunnel)
7695 {
7696         int ret = 0;
7697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7698
7699         if (hw->mac.type != ixgbe_mac_X550 &&
7700             hw->mac.type != ixgbe_mac_X550EM_x &&
7701             hw->mac.type != ixgbe_mac_X550EM_a) {
7702                 return -ENOTSUP;
7703         }
7704
7705         if (udp_tunnel == NULL)
7706                 return -EINVAL;
7707
7708         switch (udp_tunnel->prot_type) {
7709         case RTE_ETH_TUNNEL_TYPE_VXLAN:
7710                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7711                 break;
7712
7713         case RTE_ETH_TUNNEL_TYPE_GENEVE:
7714         case RTE_ETH_TUNNEL_TYPE_TEREDO:
7715                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7716                 ret = -EINVAL;
7717                 break;
7718
7719         default:
7720                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7721                 ret = -EINVAL;
7722                 break;
7723         }
7724
7725         return ret;
7726 }
7727
7728 /* Remove UDP tunneling port */
7729 static int
7730 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7731                               struct rte_eth_udp_tunnel *udp_tunnel)
7732 {
7733         int ret = 0;
7734         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7735
7736         if (hw->mac.type != ixgbe_mac_X550 &&
7737             hw->mac.type != ixgbe_mac_X550EM_x &&
7738             hw->mac.type != ixgbe_mac_X550EM_a) {
7739                 return -ENOTSUP;
7740         }
7741
7742         if (udp_tunnel == NULL)
7743                 return -EINVAL;
7744
7745         switch (udp_tunnel->prot_type) {
7746         case RTE_ETH_TUNNEL_TYPE_VXLAN:
7747                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7748                 break;
7749         case RTE_ETH_TUNNEL_TYPE_GENEVE:
7750         case RTE_ETH_TUNNEL_TYPE_TEREDO:
7751                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7752                 ret = -EINVAL;
7753                 break;
7754         default:
7755                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7756                 ret = -EINVAL;
7757                 break;
7758         }
7759
7760         return ret;
7761 }
7762
7763 static int
7764 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
7765 {
7766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7767         int ret;
7768
7769         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
7770         case IXGBE_SUCCESS:
7771                 ret = 0;
7772                 break;
7773         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7774                 ret = -ENOTSUP;
7775                 break;
7776         default:
7777                 ret = -EAGAIN;
7778                 break;
7779         }
7780
7781         return ret;
7782 }
7783
7784 static int
7785 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
7786 {
7787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7788         int ret;
7789
7790         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
7791         case IXGBE_SUCCESS:
7792                 ret = 0;
7793                 break;
7794         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7795                 ret = -ENOTSUP;
7796                 break;
7797         default:
7798                 ret = -EAGAIN;
7799                 break;
7800         }
7801
7802         return ret;
7803 }
7804
7805 static int
7806 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7807 {
7808         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7809         int ret;
7810         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
7811
7812         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
7813         case IXGBE_SUCCESS:
7814                 ret = 0;
7815                 break;
7816         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7817                 ret = -ENOTSUP;
7818                 break;
7819         default:
7820                 ret = -EAGAIN;
7821                 break;
7822         }
7823
7824         return ret;
7825 }
7826
7827 static int
7828 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7829 {
7830         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7831         int ret;
7832
7833         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
7834         case IXGBE_SUCCESS:
7835                 ret = 0;
7836                 break;
7837         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
7838                 ret = -ENOTSUP;
7839                 break;
7840         default:
7841                 ret = -EAGAIN;
7842                 break;
7843         }
7844
7845         return ret;
7846 }
7847
7848 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7849 {
7850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7851         u32 in_msg = 0;
7852
7853         /* peek the message first */
7854         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
7855
7856         /* PF reset VF event */
7857         if (in_msg == IXGBE_PF_CONTROL_MSG) {
7858                 /* dummy mbx read to ack pf */
7859                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7860                         return;
7861                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7862                                              NULL);
7863         }
7864 }
7865
7866 static int
7867 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7868 {
7869         uint32_t eicr;
7870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7871         struct ixgbe_interrupt *intr =
7872                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7873         ixgbevf_intr_disable(dev);
7874
7875         /* read-on-clear nic registers here */
7876         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7877         intr->flags = 0;
7878
7879         /* only one misc vector supported - mailbox */
7880         eicr &= IXGBE_VTEICR_MASK;
7881         if (eicr == IXGBE_MISC_VEC_ID)
7882                 intr->flags |= IXGBE_FLAG_MAILBOX;
7883
7884         return 0;
7885 }
7886
7887 static int
7888 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7889 {
7890         struct ixgbe_interrupt *intr =
7891                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7892
7893         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7894                 ixgbevf_mbx_process(dev);
7895                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7896         }
7897
7898         ixgbevf_intr_enable(dev);
7899
7900         return 0;
7901 }
7902
7903 static void
7904 ixgbevf_dev_interrupt_handler(void *param)
7905 {
7906         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7907
7908         ixgbevf_dev_interrupt_get_status(dev);
7909         ixgbevf_dev_interrupt_action(dev);
7910 }
7911
7912 /**
7913  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7914  *  @hw: pointer to hardware structure
7915  *
7916  *  Stops the transmit data path and waits for the HW to internally empty
7917  *  the Tx security block
7918  **/
7919 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7920 {
7921 #define IXGBE_MAX_SECTX_POLL 40
7922
7923         int i;
7924         int sectxreg;
7925
7926         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7927         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7928         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7929         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7930                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7931                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7932                         break;
7933                 /* Use interrupt-safe sleep just in case */
7934                 usec_delay(1000);
7935         }
7936
7937         /* For informational purposes only */
7938         if (i >= IXGBE_MAX_SECTX_POLL)
7939                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7940                          "path fully disabled.  Continuing with init.");
7941
7942         return IXGBE_SUCCESS;
7943 }
7944
7945 /**
7946  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7947  *  @hw: pointer to hardware structure
7948  *
7949  *  Enables the transmit data path.
7950  **/
7951 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7952 {
7953         uint32_t sectxreg;
7954
7955         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7956         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7957         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7958         IXGBE_WRITE_FLUSH(hw);
7959
7960         return IXGBE_SUCCESS;
7961 }
7962
7963 /* restore n-tuple filter */
7964 static inline void
7965 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7966 {
7967         struct ixgbe_filter_info *filter_info =
7968                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7969         struct ixgbe_5tuple_filter *node;
7970
7971         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7972                 ixgbe_inject_5tuple_filter(dev, node);
7973         }
7974 }
7975
7976 /* restore ethernet type filter */
7977 static inline void
7978 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7979 {
7980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7981         struct ixgbe_filter_info *filter_info =
7982                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7983         int i;
7984
7985         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
7986                 if (filter_info->ethertype_mask & (1 << i)) {
7987                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
7988                                         filter_info->ethertype_filters[i].etqf);
7989                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
7990                                         filter_info->ethertype_filters[i].etqs);
7991                         IXGBE_WRITE_FLUSH(hw);
7992                 }
7993         }
7994 }
7995
7996 /* restore SYN filter */
7997 static inline void
7998 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
7999 {
8000         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8001         struct ixgbe_filter_info *filter_info =
8002                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8003         uint32_t synqf;
8004
8005         synqf = filter_info->syn_info;
8006
8007         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8008                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8009                 IXGBE_WRITE_FLUSH(hw);
8010         }
8011 }
8012
8013 /* restore L2 tunnel filter */
8014 static inline void
8015 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8016 {
8017         struct ixgbe_l2_tn_info *l2_tn_info =
8018                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8019         struct ixgbe_l2_tn_filter *node;
8020         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8021
8022         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8023                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8024                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8025                 l2_tn_conf.pool           = node->pool;
8026                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8027         }
8028 }
8029
8030 /* restore rss filter */
8031 static inline void
8032 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8033 {
8034         struct ixgbe_filter_info *filter_info =
8035                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8036
8037         if (filter_info->rss_info.conf.queue_num)
8038                 ixgbe_config_rss_filter(dev,
8039                         &filter_info->rss_info, TRUE);
8040 }
8041
8042 static int
8043 ixgbe_filter_restore(struct rte_eth_dev *dev)
8044 {
8045         ixgbe_ntuple_filter_restore(dev);
8046         ixgbe_ethertype_filter_restore(dev);
8047         ixgbe_syn_filter_restore(dev);
8048         ixgbe_fdir_filter_restore(dev);
8049         ixgbe_l2_tn_filter_restore(dev);
8050         ixgbe_rss_filter_restore(dev);
8051
8052         return 0;
8053 }
8054
8055 static void
8056 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8057 {
8058         struct ixgbe_l2_tn_info *l2_tn_info =
8059                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8060         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8061
8062         if (l2_tn_info->e_tag_en)
8063                 (void)ixgbe_e_tag_enable(hw);
8064
8065         if (l2_tn_info->e_tag_fwd_en)
8066                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8067
8068         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8069 }
8070
8071 /* remove all the n-tuple filters */
8072 void
8073 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8074 {
8075         struct ixgbe_filter_info *filter_info =
8076                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8077         struct ixgbe_5tuple_filter *p_5tuple;
8078
8079         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8080                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8081 }
8082
8083 /* remove all the ether type filters */
8084 void
8085 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8086 {
8087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8088         struct ixgbe_filter_info *filter_info =
8089                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8090         int i;
8091
8092         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8093                 if (filter_info->ethertype_mask & (1 << i) &&
8094                     !filter_info->ethertype_filters[i].conf) {
8095                         (void)ixgbe_ethertype_filter_remove(filter_info,
8096                                                             (uint8_t)i);
8097                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8098                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8099                         IXGBE_WRITE_FLUSH(hw);
8100                 }
8101         }
8102 }
8103
8104 /* remove the SYN filter */
8105 void
8106 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8107 {
8108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8109         struct ixgbe_filter_info *filter_info =
8110                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8111
8112         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8113                 filter_info->syn_info = 0;
8114
8115                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8116                 IXGBE_WRITE_FLUSH(hw);
8117         }
8118 }
8119
8120 /* remove all the L2 tunnel filters */
8121 int
8122 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8123 {
8124         struct ixgbe_l2_tn_info *l2_tn_info =
8125                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8126         struct ixgbe_l2_tn_filter *l2_tn_filter;
8127         struct ixgbe_l2_tunnel_conf l2_tn_conf;
8128         int ret = 0;
8129
8130         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8131                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8132                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8133                 l2_tn_conf.pool           = l2_tn_filter->pool;
8134                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8135                 if (ret < 0)
8136                         return ret;
8137         }
8138
8139         return 0;
8140 }
8141
8142 void
8143 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8144                                 struct ixgbe_macsec_setting *macsec_setting)
8145 {
8146         struct ixgbe_macsec_setting *macsec =
8147                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8148
8149         macsec->offload_en = macsec_setting->offload_en;
8150         macsec->encrypt_en = macsec_setting->encrypt_en;
8151         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8152 }
8153
8154 void
8155 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8156 {
8157         struct ixgbe_macsec_setting *macsec =
8158                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8159
8160         macsec->offload_en = 0;
8161         macsec->encrypt_en = 0;
8162         macsec->replayprotect_en = 0;
8163 }
8164
8165 void
8166 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8167                                 struct ixgbe_macsec_setting *macsec_setting)
8168 {
8169         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8170         uint32_t ctrl;
8171         uint8_t en = macsec_setting->encrypt_en;
8172         uint8_t rp = macsec_setting->replayprotect_en;
8173
8174         /**
8175          * Workaround:
8176          * As no ixgbe_disable_sec_rx_path equivalent is
8177          * implemented for tx in the base code, and we are
8178          * not allowed to modify the base code in DPDK, so
8179          * just call the hand-written one directly for now.
8180          * The hardware support has been checked by
8181          * ixgbe_disable_sec_rx_path().
8182          */
8183         ixgbe_disable_sec_tx_path_generic(hw);
8184
8185         /* Enable Ethernet CRC (required by MACsec offload) */
8186         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8187         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8188         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8189
8190         /* Enable the TX and RX crypto engines */
8191         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8192         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8193         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8194
8195         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8196         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8197         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8198
8199         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8200         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8201         ctrl |= 0x3;
8202         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8203
8204         /* Enable SA lookup */
8205         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8206         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8207         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8208                      IXGBE_LSECTXCTRL_AUTH;
8209         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8210         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8211         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8212         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8213
8214         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8215         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8216         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8217         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8218         if (rp)
8219                 ctrl |= IXGBE_LSECRXCTRL_RP;
8220         else
8221                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8222         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8223
8224         /* Start the data paths */
8225         ixgbe_enable_sec_rx_path(hw);
8226         /**
8227          * Workaround:
8228          * As no ixgbe_enable_sec_rx_path equivalent is
8229          * implemented for tx in the base code, and we are
8230          * not allowed to modify the base code in DPDK, so
8231          * just call the hand-written one directly for now.
8232          */
8233         ixgbe_enable_sec_tx_path_generic(hw);
8234 }
8235
8236 void
8237 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8238 {
8239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8240         uint32_t ctrl;
8241
8242         /**
8243          * Workaround:
8244          * As no ixgbe_disable_sec_rx_path equivalent is
8245          * implemented for tx in the base code, and we are
8246          * not allowed to modify the base code in DPDK, so
8247          * just call the hand-written one directly for now.
8248          * The hardware support has been checked by
8249          * ixgbe_disable_sec_rx_path().
8250          */
8251         ixgbe_disable_sec_tx_path_generic(hw);
8252
8253         /* Disable the TX and RX crypto engines */
8254         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8255         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8256         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8257
8258         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8259         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8260         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8261
8262         /* Disable SA lookup */
8263         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8264         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8265         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8266         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8267
8268         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8269         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8270         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8271         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8272
8273         /* Start the data paths */
8274         ixgbe_enable_sec_rx_path(hw);
8275         /**
8276          * Workaround:
8277          * As no ixgbe_enable_sec_rx_path equivalent is
8278          * implemented for tx in the base code, and we are
8279          * not allowed to modify the base code in DPDK, so
8280          * just call the hand-written one directly for now.
8281          */
8282         ixgbe_enable_sec_tx_path_generic(hw);
8283 }
8284
8285 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8286 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8287 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8288 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe,
8289                               IXGBE_DEVARG_FIBER_SDP3_NOT_TX_DISABLE "=<0|1>");
8290 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8291 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8292 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8293 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8294                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8295
8296 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_init, init, NOTICE);
8297 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_driver, driver, NOTICE);
8298
8299 #ifdef RTE_ETHDEV_DEBUG_RX
8300 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_rx, rx, DEBUG);
8301 #endif
8302 #ifdef RTE_ETHDEV_DEBUG_TX
8303 RTE_LOG_REGISTER_SUFFIX(ixgbe_logtype_tx, tx, DEBUG);
8304 #endif