4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
76 #include "rte_pmd_ixgbe.h"
79 * High threshold controlling when to start sending XOFF frames. Must be at
80 * least 8 bytes less than receive packet buffer size. This value is in units
83 #define IXGBE_FC_HI 0x80
86 * Low threshold controlling when to start sending XON frames. This value is
87 * in units of 1024 bytes.
89 #define IXGBE_FC_LO 0x40
91 /* Default minimum inter-interrupt interval for EITR configuration */
92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
94 /* Timer value included in XOFF frames. */
95 #define IXGBE_FC_PAUSE 0x680
97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
98 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
99 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
101 #define IXGBE_MMW_SIZE_DEFAULT 0x4
102 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
103 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
106 * Default values for RX/TX configuration
108 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
109 #define IXGBE_DEFAULT_RX_PTHRESH 8
110 #define IXGBE_DEFAULT_RX_HTHRESH 8
111 #define IXGBE_DEFAULT_RX_WTHRESH 0
113 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
114 #define IXGBE_DEFAULT_TX_PTHRESH 32
115 #define IXGBE_DEFAULT_TX_HTHRESH 0
116 #define IXGBE_DEFAULT_TX_WTHRESH 0
117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
119 /* Bit shift and mask */
120 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
121 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
122 #define IXGBE_8_BIT_WIDTH CHAR_BIT
123 #define IXGBE_8_BIT_MASK UINT8_MAX
125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
129 #define IXGBE_HKEY_MAX_INDEX 10
131 /* Additional timesync values. */
132 #define NSEC_PER_SEC 1000000000L
133 #define IXGBE_INCVAL_10GB 0x66666666
134 #define IXGBE_INCVAL_1GB 0x40000000
135 #define IXGBE_INCVAL_100 0x50000000
136 #define IXGBE_INCVAL_SHIFT_10GB 28
137 #define IXGBE_INCVAL_SHIFT_1GB 24
138 #define IXGBE_INCVAL_SHIFT_100 21
139 #define IXGBE_INCVAL_SHIFT_82599 7
140 #define IXGBE_INCPER_SHIFT_82599 24
142 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
144 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
146 #define DEFAULT_ETAG_ETYPE 0x893f
147 #define IXGBE_ETAG_ETYPE 0x00005084
148 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
149 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
150 #define IXGBE_RAH_ADTYPE 0x40000000
151 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
152 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
155 #define IXGBE_QDE_STRIP_TAG 0x00000004
156 #define IXGBE_VTEICR_MASK 0x07
158 enum ixgbevf_xcast_modes {
159 IXGBEVF_XCAST_MODE_NONE = 0,
160 IXGBEVF_XCAST_MODE_MULTI,
161 IXGBEVF_XCAST_MODE_ALLMULTI,
164 #define IXGBE_EXVET_VET_EXT_SHIFT 16
165 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
174 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
175 static int ixgbe_dev_start(struct rte_eth_dev *dev);
176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
177 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
178 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
185 int wait_to_complete);
186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
187 struct rte_eth_stats *stats);
188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
189 struct rte_eth_xstat *xstats, unsigned n);
190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
191 struct rte_eth_xstat *xstats, unsigned n);
192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
195 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
205 struct rte_eth_dev_info *dev_info);
206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
208 struct rte_eth_dev_info *dev_info);
209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
212 uint16_t vlan_id, int on);
213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
214 enum rte_vlan_type vlan_type,
216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
217 uint16_t queue, bool on);
218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
229 struct rte_eth_fc_conf *fc_conf);
230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_pfc_conf *pfc_conf);
234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
235 struct rte_eth_rss_reta_entry64 *reta_conf,
237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
246 struct rte_intr_handle *handle);
247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
251 uint32_t index, uint32_t pool);
252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
254 struct ether_addr *mac_addr);
255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
256 static int is_ixgbe_pmd(const char *driver_name);
258 /* For Virtual Function support */
259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
261 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
262 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
268 struct rte_eth_stats *stats);
269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
271 uint16_t vlan_id, int on);
272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
273 uint16_t queue, int on);
274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
281 uint8_t queue, uint8_t msix_vector);
282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
286 /* For Eth VMDQ APIs support */
287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
288 ether_addr * mac_addr, uint8_t on);
289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
291 struct rte_eth_mirror_conf *mirror_conf,
292 uint8_t rule_id, uint8_t on);
293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
300 uint8_t queue, uint8_t msix_vector);
301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
304 uint16_t queue_idx, uint16_t tx_rate);
306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
307 struct ether_addr *mac_addr,
308 uint32_t index, uint32_t pool);
309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
311 struct ether_addr *mac_addr);
312 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
313 struct rte_eth_syn_filter *filter,
315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
316 struct rte_eth_syn_filter *filter);
317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
318 enum rte_filter_op filter_op,
320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
321 struct ixgbe_5tuple_filter *filter);
322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
323 struct ixgbe_5tuple_filter *filter);
324 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
325 struct rte_eth_ntuple_filter *filter,
327 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
328 enum rte_filter_op filter_op,
330 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
331 struct rte_eth_ntuple_filter *filter);
332 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
333 struct rte_eth_ethertype_filter *filter,
335 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
336 enum rte_filter_op filter_op,
338 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
339 struct rte_eth_ethertype_filter *filter);
340 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
341 enum rte_filter_type filter_type,
342 enum rte_filter_op filter_op,
344 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
346 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
347 struct ether_addr *mc_addr_set,
348 uint32_t nb_mc_addr);
349 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
350 struct rte_eth_dcb_info *dcb_info);
352 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
353 static int ixgbe_get_regs(struct rte_eth_dev *dev,
354 struct rte_dev_reg_info *regs);
355 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
356 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
357 struct rte_dev_eeprom_info *eeprom);
358 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
359 struct rte_dev_eeprom_info *eeprom);
361 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
362 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
363 struct rte_dev_reg_info *regs);
365 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
366 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
367 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
368 struct timespec *timestamp,
370 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
371 struct timespec *timestamp);
372 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
373 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
374 struct timespec *timestamp);
375 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
376 const struct timespec *timestamp);
377 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
380 static int ixgbe_dev_l2_tunnel_eth_type_conf
381 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
382 static int ixgbe_dev_l2_tunnel_offload_set
383 (struct rte_eth_dev *dev,
384 struct rte_eth_l2_tunnel_conf *l2_tunnel,
387 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
388 enum rte_filter_op filter_op,
391 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
392 struct rte_eth_udp_tunnel *udp_tunnel);
393 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
394 struct rte_eth_udp_tunnel *udp_tunnel);
395 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
396 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
399 * Define VF Stats MACRO for Non "cleared on read" register
401 #define UPDATE_VF_STAT(reg, last, cur) \
403 uint32_t latest = IXGBE_READ_REG(hw, reg); \
404 cur += (latest - last) & UINT_MAX; \
408 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
410 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
411 u64 new_msb = IXGBE_READ_REG(hw, msb); \
412 u64 latest = ((new_msb << 32) | new_lsb); \
413 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
417 #define IXGBE_SET_HWSTRIP(h, q) do {\
418 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
419 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
420 (h)->bitmap[idx] |= 1 << bit;\
423 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
424 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
425 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
426 (h)->bitmap[idx] &= ~(1 << bit);\
429 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
430 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
431 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
432 (r) = (h)->bitmap[idx] >> bit & 1;\
436 * The set of PCI devices this driver supports
438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
486 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
487 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
488 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
489 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
492 #ifdef RTE_NIC_BYPASS
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
495 { .vendor_id = 0, /* sentinel */ },
499 * The set of PCI devices this driver supports (for 82599 VF)
501 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
504 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
505 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
506 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
507 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
508 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
509 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
510 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
511 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
512 { .vendor_id = 0, /* sentinel */ },
515 static const struct rte_eth_desc_lim rx_desc_lim = {
516 .nb_max = IXGBE_MAX_RING_DESC,
517 .nb_min = IXGBE_MIN_RING_DESC,
518 .nb_align = IXGBE_RXD_ALIGN,
521 static const struct rte_eth_desc_lim tx_desc_lim = {
522 .nb_max = IXGBE_MAX_RING_DESC,
523 .nb_min = IXGBE_MIN_RING_DESC,
524 .nb_align = IXGBE_TXD_ALIGN,
525 .nb_seg_max = IXGBE_TX_MAX_SEG,
526 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
529 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
530 .dev_configure = ixgbe_dev_configure,
531 .dev_start = ixgbe_dev_start,
532 .dev_stop = ixgbe_dev_stop,
533 .dev_set_link_up = ixgbe_dev_set_link_up,
534 .dev_set_link_down = ixgbe_dev_set_link_down,
535 .dev_close = ixgbe_dev_close,
536 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
537 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
538 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
539 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
540 .link_update = ixgbe_dev_link_update,
541 .stats_get = ixgbe_dev_stats_get,
542 .xstats_get = ixgbe_dev_xstats_get,
543 .stats_reset = ixgbe_dev_stats_reset,
544 .xstats_reset = ixgbe_dev_xstats_reset,
545 .xstats_get_names = ixgbe_dev_xstats_get_names,
546 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
547 .fw_version_get = ixgbe_fw_version_get,
548 .dev_infos_get = ixgbe_dev_info_get,
549 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
550 .mtu_set = ixgbe_dev_mtu_set,
551 .vlan_filter_set = ixgbe_vlan_filter_set,
552 .vlan_tpid_set = ixgbe_vlan_tpid_set,
553 .vlan_offload_set = ixgbe_vlan_offload_set,
554 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
555 .rx_queue_start = ixgbe_dev_rx_queue_start,
556 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
557 .tx_queue_start = ixgbe_dev_tx_queue_start,
558 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
559 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
560 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
561 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
562 .rx_queue_release = ixgbe_dev_rx_queue_release,
563 .rx_queue_count = ixgbe_dev_rx_queue_count,
564 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
565 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
566 .tx_queue_release = ixgbe_dev_tx_queue_release,
567 .dev_led_on = ixgbe_dev_led_on,
568 .dev_led_off = ixgbe_dev_led_off,
569 .flow_ctrl_get = ixgbe_flow_ctrl_get,
570 .flow_ctrl_set = ixgbe_flow_ctrl_set,
571 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
572 .mac_addr_add = ixgbe_add_rar,
573 .mac_addr_remove = ixgbe_remove_rar,
574 .mac_addr_set = ixgbe_set_default_mac_addr,
575 .uc_hash_table_set = ixgbe_uc_hash_table_set,
576 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
577 .mirror_rule_set = ixgbe_mirror_rule_set,
578 .mirror_rule_reset = ixgbe_mirror_rule_reset,
579 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
580 .reta_update = ixgbe_dev_rss_reta_update,
581 .reta_query = ixgbe_dev_rss_reta_query,
582 #ifdef RTE_NIC_BYPASS
583 .bypass_init = ixgbe_bypass_init,
584 .bypass_state_set = ixgbe_bypass_state_store,
585 .bypass_state_show = ixgbe_bypass_state_show,
586 .bypass_event_set = ixgbe_bypass_event_store,
587 .bypass_event_show = ixgbe_bypass_event_show,
588 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
589 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
590 .bypass_ver_show = ixgbe_bypass_ver_show,
591 .bypass_wd_reset = ixgbe_bypass_wd_reset,
592 #endif /* RTE_NIC_BYPASS */
593 .rss_hash_update = ixgbe_dev_rss_hash_update,
594 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
595 .filter_ctrl = ixgbe_dev_filter_ctrl,
596 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
597 .rxq_info_get = ixgbe_rxq_info_get,
598 .txq_info_get = ixgbe_txq_info_get,
599 .timesync_enable = ixgbe_timesync_enable,
600 .timesync_disable = ixgbe_timesync_disable,
601 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
602 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
603 .get_reg = ixgbe_get_regs,
604 .get_eeprom_length = ixgbe_get_eeprom_length,
605 .get_eeprom = ixgbe_get_eeprom,
606 .set_eeprom = ixgbe_set_eeprom,
607 .get_dcb_info = ixgbe_dev_get_dcb_info,
608 .timesync_adjust_time = ixgbe_timesync_adjust_time,
609 .timesync_read_time = ixgbe_timesync_read_time,
610 .timesync_write_time = ixgbe_timesync_write_time,
611 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
612 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
613 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
614 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
618 * dev_ops for virtual function, bare necessities for basic vf
619 * operation have been implemented
621 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
622 .dev_configure = ixgbevf_dev_configure,
623 .dev_start = ixgbevf_dev_start,
624 .dev_stop = ixgbevf_dev_stop,
625 .link_update = ixgbe_dev_link_update,
626 .stats_get = ixgbevf_dev_stats_get,
627 .xstats_get = ixgbevf_dev_xstats_get,
628 .stats_reset = ixgbevf_dev_stats_reset,
629 .xstats_reset = ixgbevf_dev_stats_reset,
630 .xstats_get_names = ixgbevf_dev_xstats_get_names,
631 .dev_close = ixgbevf_dev_close,
632 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
633 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
634 .dev_infos_get = ixgbevf_dev_info_get,
635 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
636 .mtu_set = ixgbevf_dev_set_mtu,
637 .vlan_filter_set = ixgbevf_vlan_filter_set,
638 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
639 .vlan_offload_set = ixgbevf_vlan_offload_set,
640 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
641 .rx_queue_release = ixgbe_dev_rx_queue_release,
642 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
643 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
644 .tx_queue_release = ixgbe_dev_tx_queue_release,
645 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
646 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
647 .mac_addr_add = ixgbevf_add_mac_addr,
648 .mac_addr_remove = ixgbevf_remove_mac_addr,
649 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
650 .rxq_info_get = ixgbe_rxq_info_get,
651 .txq_info_get = ixgbe_txq_info_get,
652 .mac_addr_set = ixgbevf_set_default_mac_addr,
653 .get_reg = ixgbevf_get_regs,
654 .reta_update = ixgbe_dev_rss_reta_update,
655 .reta_query = ixgbe_dev_rss_reta_query,
656 .rss_hash_update = ixgbe_dev_rss_hash_update,
657 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
660 /* store statistics names and its offset in stats structure */
661 struct rte_ixgbe_xstats_name_off {
662 char name[RTE_ETH_XSTATS_NAME_SIZE];
666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
667 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
668 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
669 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
670 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
671 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
672 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
673 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
674 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
675 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
676 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
677 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
678 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
679 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
680 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
681 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
683 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
685 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
686 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
687 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
688 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
689 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
690 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
691 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
692 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
693 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
694 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
695 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
696 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
697 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
698 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
699 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
700 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
701 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
703 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
705 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
706 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
707 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
708 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
710 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
712 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
714 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
716 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
718 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
720 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
723 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
724 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
725 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
727 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
728 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
729 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
730 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
731 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
733 {"rx_fcoe_no_direct_data_placement_ext_buff",
734 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
736 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
738 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
740 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
742 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
744 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
747 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
748 sizeof(rte_ixgbe_stats_strings[0]))
750 /* MACsec statistics */
751 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
752 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
754 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
755 out_pkts_encrypted)},
756 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
757 out_pkts_protected)},
758 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
759 out_octets_encrypted)},
760 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
761 out_octets_protected)},
762 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
769 in_pkts_unknownsci)},
770 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
771 in_octets_decrypted)},
772 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
773 in_octets_validated)},
774 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
778 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
780 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
782 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
784 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
786 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
788 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
789 in_pkts_notusingsa)},
792 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
793 sizeof(rte_ixgbe_macsec_strings[0]))
795 /* Per-queue statistics */
796 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
797 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
798 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
799 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
800 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
803 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
804 sizeof(rte_ixgbe_rxq_strings[0]))
805 #define IXGBE_NB_RXQ_PRIO_VALUES 8
807 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
808 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
809 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
810 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
814 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
815 sizeof(rte_ixgbe_txq_strings[0]))
816 #define IXGBE_NB_TXQ_PRIO_VALUES 8
818 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
819 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
822 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
823 sizeof(rte_ixgbevf_stats_strings[0]))
826 * Atomically reads the link status information from global
827 * structure rte_eth_dev.
830 * - Pointer to the structure rte_eth_dev to read from.
831 * - Pointer to the buffer to be saved with the link status.
834 * - On success, zero.
835 * - On failure, negative value.
838 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
839 struct rte_eth_link *link)
841 struct rte_eth_link *dst = link;
842 struct rte_eth_link *src = &(dev->data->dev_link);
844 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
845 *(uint64_t *)src) == 0)
852 * Atomically writes the link status information into global
853 * structure rte_eth_dev.
856 * - Pointer to the structure rte_eth_dev to read from.
857 * - Pointer to the buffer to be saved with the link status.
860 * - On success, zero.
861 * - On failure, negative value.
864 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
865 struct rte_eth_link *link)
867 struct rte_eth_link *dst = &(dev->data->dev_link);
868 struct rte_eth_link *src = link;
870 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
871 *(uint64_t *)src) == 0)
878 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
881 ixgbe_is_sfp(struct ixgbe_hw *hw)
883 switch (hw->phy.type) {
884 case ixgbe_phy_sfp_avago:
885 case ixgbe_phy_sfp_ftl:
886 case ixgbe_phy_sfp_intel:
887 case ixgbe_phy_sfp_unknown:
888 case ixgbe_phy_sfp_passive_tyco:
889 case ixgbe_phy_sfp_passive_unknown:
896 static inline int32_t
897 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
902 status = ixgbe_reset_hw(hw);
904 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
905 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
906 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
907 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
908 IXGBE_WRITE_FLUSH(hw);
914 ixgbe_enable_intr(struct rte_eth_dev *dev)
916 struct ixgbe_interrupt *intr =
917 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
918 struct ixgbe_hw *hw =
919 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
921 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
922 IXGBE_WRITE_FLUSH(hw);
926 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
929 ixgbe_disable_intr(struct ixgbe_hw *hw)
931 PMD_INIT_FUNC_TRACE();
933 if (hw->mac.type == ixgbe_mac_82598EB) {
934 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
936 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
937 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
938 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
940 IXGBE_WRITE_FLUSH(hw);
944 * This function resets queue statistics mapping registers.
945 * From Niantic datasheet, Initialization of Statistics section:
946 * "...if software requires the queue counters, the RQSMR and TQSM registers
947 * must be re-programmed following a device reset.
950 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
954 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
955 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
956 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
962 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
967 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
968 #define NB_QMAP_FIELDS_PER_QSM_REG 4
969 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
972 struct ixgbe_stat_mapping_registers *stat_mappings =
973 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
974 uint32_t qsmr_mask = 0;
975 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
979 if ((hw->mac.type != ixgbe_mac_82599EB) &&
980 (hw->mac.type != ixgbe_mac_X540) &&
981 (hw->mac.type != ixgbe_mac_X550) &&
982 (hw->mac.type != ixgbe_mac_X550EM_x) &&
983 (hw->mac.type != ixgbe_mac_X550EM_a))
986 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
987 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
990 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
991 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
992 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
995 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
997 /* Now clear any previous stat_idx set */
998 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1000 stat_mappings->tqsm[n] &= ~clearing_mask;
1002 stat_mappings->rqsmr[n] &= ~clearing_mask;
1004 q_map = (uint32_t)stat_idx;
1005 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1006 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1008 stat_mappings->tqsm[n] |= qsmr_mask;
1010 stat_mappings->rqsmr[n] |= qsmr_mask;
1012 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1013 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1014 queue_id, stat_idx);
1015 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1016 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1018 /* Now write the mapping in the appropriate register */
1020 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1021 stat_mappings->rqsmr[n], n);
1022 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1024 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1025 stat_mappings->tqsm[n], n);
1026 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1032 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1034 struct ixgbe_stat_mapping_registers *stat_mappings =
1035 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1036 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 /* write whatever was in stat mapping table to the NIC */
1040 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1042 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1045 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1050 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1053 struct ixgbe_dcb_tc_config *tc;
1054 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1056 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1057 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1058 for (i = 0; i < dcb_max_tc; i++) {
1059 tc = &dcb_config->tc_config[i];
1060 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1061 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1062 (uint8_t)(100/dcb_max_tc + (i & 1));
1063 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1064 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1065 (uint8_t)(100/dcb_max_tc + (i & 1));
1066 tc->pfc = ixgbe_dcb_pfc_disabled;
1069 /* Initialize default user to priority mapping, UPx->TC0 */
1070 tc = &dcb_config->tc_config[0];
1071 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1072 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1073 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1074 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1075 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1077 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1078 dcb_config->pfc_mode_enable = false;
1079 dcb_config->vt_mode = true;
1080 dcb_config->round_robin_enable = false;
1081 /* support all DCB capabilities in 82599 */
1082 dcb_config->support.capabilities = 0xFF;
1084 /*we only support 4 Tcs for X540, X550 */
1085 if (hw->mac.type == ixgbe_mac_X540 ||
1086 hw->mac.type == ixgbe_mac_X550 ||
1087 hw->mac.type == ixgbe_mac_X550EM_x ||
1088 hw->mac.type == ixgbe_mac_X550EM_a) {
1089 dcb_config->num_tcs.pg_tcs = 4;
1090 dcb_config->num_tcs.pfc_tcs = 4;
1095 * Ensure that all locks are released before first NVM or PHY access
1098 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1103 * Phy lock should not fail in this early stage. If this is the case,
1104 * it is due to an improper exit of the application.
1105 * So force the release of the faulty lock. Release of common lock
1106 * is done automatically by swfw_sync function.
1108 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1109 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1112 ixgbe_release_swfw_semaphore(hw, mask);
1115 * These ones are more tricky since they are common to all ports; but
1116 * swfw_sync retries last long enough (1s) to be almost sure that if
1117 * lock can not be taken it is due to an improper lock of the
1120 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1121 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1122 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1124 ixgbe_release_swfw_semaphore(hw, mask);
1128 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1129 * It returns 0 on success.
1132 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1134 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1135 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1136 struct ixgbe_hw *hw =
1137 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1138 struct ixgbe_vfta *shadow_vfta =
1139 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1140 struct ixgbe_hwstrip *hwstrip =
1141 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1142 struct ixgbe_dcb_config *dcb_config =
1143 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1144 struct ixgbe_filter_info *filter_info =
1145 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1150 PMD_INIT_FUNC_TRACE();
1152 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1153 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1154 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1155 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1158 * For secondary processes, we don't initialise any further as primary
1159 * has already done this work. Only check we don't need a different
1160 * RX and TX function.
1162 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1163 struct ixgbe_tx_queue *txq;
1164 /* TX queue function in primary, set by last queue initialized
1165 * Tx queue may not initialized by primary process
1167 if (eth_dev->data->tx_queues) {
1168 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1169 ixgbe_set_tx_function(eth_dev, txq);
1171 /* Use default TX function if we get here */
1172 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1173 "Using default TX function.");
1176 ixgbe_set_rx_function(eth_dev);
1181 rte_eth_copy_pci_info(eth_dev, pci_dev);
1182 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1184 /* Vendor and Device ID need to be set before init of shared code */
1185 hw->device_id = pci_dev->id.device_id;
1186 hw->vendor_id = pci_dev->id.vendor_id;
1187 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1188 hw->allow_unsupported_sfp = 1;
1190 /* Initialize the shared code (base driver) */
1191 #ifdef RTE_NIC_BYPASS
1192 diag = ixgbe_bypass_init_shared_code(hw);
1194 diag = ixgbe_init_shared_code(hw);
1195 #endif /* RTE_NIC_BYPASS */
1197 if (diag != IXGBE_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1202 /* pick up the PCI bus settings for reporting later */
1203 ixgbe_get_bus_info(hw);
1205 /* Unlock any pending hardware semaphore */
1206 ixgbe_swfw_lock_reset(hw);
1208 /* Initialize DCB configuration*/
1209 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1210 ixgbe_dcb_init(hw, dcb_config);
1211 /* Get Hardware Flow Control setting */
1212 hw->fc.requested_mode = ixgbe_fc_full;
1213 hw->fc.current_mode = ixgbe_fc_full;
1214 hw->fc.pause_time = IXGBE_FC_PAUSE;
1215 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1216 hw->fc.low_water[i] = IXGBE_FC_LO;
1217 hw->fc.high_water[i] = IXGBE_FC_HI;
1219 hw->fc.send_xon = 1;
1221 /* Make sure we have a good EEPROM before we read from it */
1222 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1223 if (diag != IXGBE_SUCCESS) {
1224 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1228 #ifdef RTE_NIC_BYPASS
1229 diag = ixgbe_bypass_init_hw(hw);
1231 diag = ixgbe_init_hw(hw);
1232 #endif /* RTE_NIC_BYPASS */
1235 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1236 * is called too soon after the kernel driver unbinding/binding occurs.
1237 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1238 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1239 * also called. See ixgbe_identify_phy_82599(). The reason for the
1240 * failure is not known, and only occuts when virtualisation features
1241 * are disabled in the bios. A delay of 100ms was found to be enough by
1242 * trial-and-error, and is doubled to be safe.
1244 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1246 diag = ixgbe_init_hw(hw);
1249 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1250 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1251 "LOM. Please be aware there may be issues associated "
1252 "with your hardware.");
1253 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1254 "please contact your Intel or hardware representative "
1255 "who provided you with this hardware.");
1256 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1257 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1259 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1263 /* Reset the hw statistics */
1264 ixgbe_dev_stats_reset(eth_dev);
1266 /* disable interrupt */
1267 ixgbe_disable_intr(hw);
1269 /* reset mappings for queue statistics hw counters*/
1270 ixgbe_reset_qstat_mappings(hw);
1272 /* Allocate memory for storing MAC addresses */
1273 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1274 hw->mac.num_rar_entries, 0);
1275 if (eth_dev->data->mac_addrs == NULL) {
1277 "Failed to allocate %u bytes needed to store "
1279 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1282 /* Copy the permanent MAC address */
1283 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1284 ð_dev->data->mac_addrs[0]);
1286 /* Allocate memory for storing hash filter MAC addresses */
1287 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1288 IXGBE_VMDQ_NUM_UC_MAC, 0);
1289 if (eth_dev->data->hash_mac_addrs == NULL) {
1291 "Failed to allocate %d bytes needed to store MAC addresses",
1292 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1296 /* initialize the vfta */
1297 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1299 /* initialize the hw strip bitmap*/
1300 memset(hwstrip, 0, sizeof(*hwstrip));
1302 /* initialize PF if max_vfs not zero */
1303 ixgbe_pf_host_init(eth_dev);
1305 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1306 /* let hardware know driver is loaded */
1307 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1308 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1309 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1310 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1311 IXGBE_WRITE_FLUSH(hw);
1313 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1314 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1315 (int) hw->mac.type, (int) hw->phy.type,
1316 (int) hw->phy.sfp_type);
1318 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1319 (int) hw->mac.type, (int) hw->phy.type);
1321 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1322 eth_dev->data->port_id, pci_dev->id.vendor_id,
1323 pci_dev->id.device_id);
1325 rte_intr_callback_register(intr_handle,
1326 ixgbe_dev_interrupt_handler, eth_dev);
1328 /* enable uio/vfio intr/eventfd mapping */
1329 rte_intr_enable(intr_handle);
1331 /* enable support intr */
1332 ixgbe_enable_intr(eth_dev);
1334 /* initialize filter info */
1335 memset(filter_info, 0,
1336 sizeof(struct ixgbe_filter_info));
1338 /* initialize 5tuple filter list */
1339 TAILQ_INIT(&filter_info->fivetuple_list);
1341 /* initialize flow director filter list & hash */
1342 ixgbe_fdir_filter_init(eth_dev);
1344 /* initialize l2 tunnel filter list & hash */
1345 ixgbe_l2_tn_filter_init(eth_dev);
1350 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1352 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1353 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1354 struct ixgbe_hw *hw;
1356 PMD_INIT_FUNC_TRACE();
1358 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1361 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1363 if (hw->adapter_stopped == 0)
1364 ixgbe_dev_close(eth_dev);
1366 eth_dev->dev_ops = NULL;
1367 eth_dev->rx_pkt_burst = NULL;
1368 eth_dev->tx_pkt_burst = NULL;
1370 /* Unlock any pending hardware semaphore */
1371 ixgbe_swfw_lock_reset(hw);
1373 /* disable uio intr before callback unregister */
1374 rte_intr_disable(intr_handle);
1375 rte_intr_callback_unregister(intr_handle,
1376 ixgbe_dev_interrupt_handler, eth_dev);
1378 /* uninitialize PF if max_vfs not zero */
1379 ixgbe_pf_host_uninit(eth_dev);
1381 rte_free(eth_dev->data->mac_addrs);
1382 eth_dev->data->mac_addrs = NULL;
1384 rte_free(eth_dev->data->hash_mac_addrs);
1385 eth_dev->data->hash_mac_addrs = NULL;
1387 /* remove all the fdir filters & hash */
1388 ixgbe_fdir_filter_uninit(eth_dev);
1390 /* remove all the L2 tunnel filters & hash */
1391 ixgbe_l2_tn_filter_uninit(eth_dev);
1393 /* Remove all ntuple filters of the device */
1394 ixgbe_ntuple_filter_uninit(eth_dev);
1399 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1401 struct ixgbe_filter_info *filter_info =
1402 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1403 struct ixgbe_5tuple_filter *p_5tuple;
1405 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1406 TAILQ_REMOVE(&filter_info->fivetuple_list,
1411 memset(filter_info->fivetuple_mask, 0,
1412 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1417 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1419 struct ixgbe_hw_fdir_info *fdir_info =
1420 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421 struct ixgbe_fdir_filter *fdir_filter;
1423 if (fdir_info->hash_map)
1424 rte_free(fdir_info->hash_map);
1425 if (fdir_info->hash_handle)
1426 rte_hash_free(fdir_info->hash_handle);
1428 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1429 TAILQ_REMOVE(&fdir_info->fdir_list,
1432 rte_free(fdir_filter);
1438 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1440 struct ixgbe_l2_tn_info *l2_tn_info =
1441 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1442 struct ixgbe_l2_tn_filter *l2_tn_filter;
1444 if (l2_tn_info->hash_map)
1445 rte_free(l2_tn_info->hash_map);
1446 if (l2_tn_info->hash_handle)
1447 rte_hash_free(l2_tn_info->hash_handle);
1449 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1450 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1453 rte_free(l2_tn_filter);
1459 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1461 struct ixgbe_hw_fdir_info *fdir_info =
1462 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1463 char fdir_hash_name[RTE_HASH_NAMESIZE];
1464 struct rte_hash_parameters fdir_hash_params = {
1465 .name = fdir_hash_name,
1466 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1467 .key_len = sizeof(union ixgbe_atr_input),
1468 .hash_func = rte_hash_crc,
1469 .hash_func_init_val = 0,
1470 .socket_id = rte_socket_id(),
1473 TAILQ_INIT(&fdir_info->fdir_list);
1474 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1475 "fdir_%s", eth_dev->data->name);
1476 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1477 if (!fdir_info->hash_handle) {
1478 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1481 fdir_info->hash_map = rte_zmalloc("ixgbe",
1482 sizeof(struct ixgbe_fdir_filter *) *
1483 IXGBE_MAX_FDIR_FILTER_NUM,
1485 if (!fdir_info->hash_map) {
1487 "Failed to allocate memory for fdir hash map!");
1493 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1495 struct ixgbe_l2_tn_info *l2_tn_info =
1496 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1497 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1498 struct rte_hash_parameters l2_tn_hash_params = {
1499 .name = l2_tn_hash_name,
1500 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1501 .key_len = sizeof(struct ixgbe_l2_tn_key),
1502 .hash_func = rte_hash_crc,
1503 .hash_func_init_val = 0,
1504 .socket_id = rte_socket_id(),
1507 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1508 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1509 "l2_tn_%s", eth_dev->data->name);
1510 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1511 if (!l2_tn_info->hash_handle) {
1512 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1515 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1516 sizeof(struct ixgbe_l2_tn_filter *) *
1517 IXGBE_MAX_L2_TN_FILTER_NUM,
1519 if (!l2_tn_info->hash_map) {
1521 "Failed to allocate memory for L2 TN hash map!");
1524 l2_tn_info->e_tag_en = FALSE;
1525 l2_tn_info->e_tag_fwd_en = FALSE;
1526 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1531 * Negotiate mailbox API version with the PF.
1532 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1533 * Then we try to negotiate starting with the most recent one.
1534 * If all negotiation attempts fail, then we will proceed with
1535 * the default one (ixgbe_mbox_api_10).
1538 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1542 /* start with highest supported, proceed down */
1543 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1550 i != RTE_DIM(sup_ver) &&
1551 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1557 generate_random_mac_addr(struct ether_addr *mac_addr)
1561 /* Set Organizationally Unique Identifier (OUI) prefix. */
1562 mac_addr->addr_bytes[0] = 0x00;
1563 mac_addr->addr_bytes[1] = 0x09;
1564 mac_addr->addr_bytes[2] = 0xC0;
1565 /* Force indication of locally assigned MAC address. */
1566 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1567 /* Generate the last 3 bytes of the MAC address with a random number. */
1568 random = rte_rand();
1569 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1573 * Virtual Function device init
1576 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1580 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1581 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1582 struct ixgbe_hw *hw =
1583 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1584 struct ixgbe_vfta *shadow_vfta =
1585 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1586 struct ixgbe_hwstrip *hwstrip =
1587 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1588 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1590 PMD_INIT_FUNC_TRACE();
1592 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1593 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1594 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1596 /* for secondary processes, we don't initialise any further as primary
1597 * has already done this work. Only check we don't need a different
1600 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1601 struct ixgbe_tx_queue *txq;
1602 /* TX queue function in primary, set by last queue initialized
1603 * Tx queue may not initialized by primary process
1605 if (eth_dev->data->tx_queues) {
1606 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1607 ixgbe_set_tx_function(eth_dev, txq);
1609 /* Use default TX function if we get here */
1610 PMD_INIT_LOG(NOTICE,
1611 "No TX queues configured yet. Using default TX function.");
1614 ixgbe_set_rx_function(eth_dev);
1619 rte_eth_copy_pci_info(eth_dev, pci_dev);
1620 eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1622 hw->device_id = pci_dev->id.device_id;
1623 hw->vendor_id = pci_dev->id.vendor_id;
1624 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1626 /* initialize the vfta */
1627 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1629 /* initialize the hw strip bitmap*/
1630 memset(hwstrip, 0, sizeof(*hwstrip));
1632 /* Initialize the shared code (base driver) */
1633 diag = ixgbe_init_shared_code(hw);
1634 if (diag != IXGBE_SUCCESS) {
1635 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1639 /* init_mailbox_params */
1640 hw->mbx.ops.init_params(hw);
1642 /* Reset the hw statistics */
1643 ixgbevf_dev_stats_reset(eth_dev);
1645 /* Disable the interrupts for VF */
1646 ixgbevf_intr_disable(hw);
1648 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1649 diag = hw->mac.ops.reset_hw(hw);
1652 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1653 * the underlying PF driver has not assigned a MAC address to the VF.
1654 * In this case, assign a random MAC address.
1656 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1657 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1661 /* negotiate mailbox API version to use with the PF. */
1662 ixgbevf_negotiate_api(hw);
1664 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1665 ixgbevf_get_queues(hw, &tcs, &tc);
1667 /* Allocate memory for storing MAC addresses */
1668 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1669 hw->mac.num_rar_entries, 0);
1670 if (eth_dev->data->mac_addrs == NULL) {
1672 "Failed to allocate %u bytes needed to store "
1674 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1678 /* Generate a random MAC address, if none was assigned by PF. */
1679 if (is_zero_ether_addr(perm_addr)) {
1680 generate_random_mac_addr(perm_addr);
1681 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1683 rte_free(eth_dev->data->mac_addrs);
1684 eth_dev->data->mac_addrs = NULL;
1687 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1688 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1689 "%02x:%02x:%02x:%02x:%02x:%02x",
1690 perm_addr->addr_bytes[0],
1691 perm_addr->addr_bytes[1],
1692 perm_addr->addr_bytes[2],
1693 perm_addr->addr_bytes[3],
1694 perm_addr->addr_bytes[4],
1695 perm_addr->addr_bytes[5]);
1698 /* Copy the permanent MAC address */
1699 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1701 /* reset the hardware with the new settings */
1702 diag = hw->mac.ops.start_hw(hw);
1708 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1712 rte_intr_callback_register(intr_handle,
1713 ixgbevf_dev_interrupt_handler, eth_dev);
1714 rte_intr_enable(intr_handle);
1715 ixgbevf_intr_enable(hw);
1717 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1718 eth_dev->data->port_id, pci_dev->id.vendor_id,
1719 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1724 /* Virtual Function device uninit */
1727 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1729 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1730 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1731 struct ixgbe_hw *hw;
1733 PMD_INIT_FUNC_TRACE();
1735 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1738 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1740 if (hw->adapter_stopped == 0)
1741 ixgbevf_dev_close(eth_dev);
1743 eth_dev->dev_ops = NULL;
1744 eth_dev->rx_pkt_burst = NULL;
1745 eth_dev->tx_pkt_burst = NULL;
1747 /* Disable the interrupts for VF */
1748 ixgbevf_intr_disable(hw);
1750 rte_free(eth_dev->data->mac_addrs);
1751 eth_dev->data->mac_addrs = NULL;
1753 rte_intr_disable(intr_handle);
1754 rte_intr_callback_unregister(intr_handle,
1755 ixgbevf_dev_interrupt_handler, eth_dev);
1760 static struct eth_driver rte_ixgbe_pmd = {
1762 .id_table = pci_id_ixgbe_map,
1763 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1764 .probe = rte_eth_dev_pci_probe,
1765 .remove = rte_eth_dev_pci_remove,
1767 .eth_dev_init = eth_ixgbe_dev_init,
1768 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1769 .dev_private_size = sizeof(struct ixgbe_adapter),
1773 * virtual function driver struct
1775 static struct eth_driver rte_ixgbevf_pmd = {
1777 .id_table = pci_id_ixgbevf_map,
1778 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1779 .probe = rte_eth_dev_pci_probe,
1780 .remove = rte_eth_dev_pci_remove,
1782 .eth_dev_init = eth_ixgbevf_dev_init,
1783 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1784 .dev_private_size = sizeof(struct ixgbe_adapter),
1788 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1790 struct ixgbe_hw *hw =
1791 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1792 struct ixgbe_vfta *shadow_vfta =
1793 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1798 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1799 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1800 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1805 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1807 /* update local VFTA copy */
1808 shadow_vfta->vfta[vid_idx] = vfta;
1814 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1817 ixgbe_vlan_hw_strip_enable(dev, queue);
1819 ixgbe_vlan_hw_strip_disable(dev, queue);
1823 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1824 enum rte_vlan_type vlan_type,
1827 struct ixgbe_hw *hw =
1828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1834 qinq &= IXGBE_DMATXCTL_GDV;
1836 switch (vlan_type) {
1837 case ETH_VLAN_TYPE_INNER:
1839 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1840 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1841 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1842 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1843 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1844 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1845 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1848 PMD_DRV_LOG(ERR, "Inner type is not supported"
1852 case ETH_VLAN_TYPE_OUTER:
1854 /* Only the high 16-bits is valid */
1855 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1856 IXGBE_EXVET_VET_EXT_SHIFT);
1858 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1859 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1860 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1861 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1862 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1863 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1864 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1870 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1878 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1880 struct ixgbe_hw *hw =
1881 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884 PMD_INIT_FUNC_TRACE();
1886 /* Filter Table Disable */
1887 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1888 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1890 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1894 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1896 struct ixgbe_hw *hw =
1897 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1898 struct ixgbe_vfta *shadow_vfta =
1899 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1903 PMD_INIT_FUNC_TRACE();
1905 /* Filter Table Enable */
1906 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1907 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1908 vlnctrl |= IXGBE_VLNCTRL_VFE;
1910 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1912 /* write whatever is in local vfta copy */
1913 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1914 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1918 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1920 struct ixgbe_hwstrip *hwstrip =
1921 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1922 struct ixgbe_rx_queue *rxq;
1924 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1928 IXGBE_SET_HWSTRIP(hwstrip, queue);
1930 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1932 if (queue >= dev->data->nb_rx_queues)
1935 rxq = dev->data->rx_queues[queue];
1938 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1940 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1944 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1946 struct ixgbe_hw *hw =
1947 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1950 PMD_INIT_FUNC_TRACE();
1952 if (hw->mac.type == ixgbe_mac_82598EB) {
1953 /* No queue level support */
1954 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1958 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1959 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1960 ctrl &= ~IXGBE_RXDCTL_VME;
1961 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1963 /* record those setting for HW strip per queue */
1964 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1968 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1970 struct ixgbe_hw *hw =
1971 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974 PMD_INIT_FUNC_TRACE();
1976 if (hw->mac.type == ixgbe_mac_82598EB) {
1977 /* No queue level supported */
1978 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1982 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984 ctrl |= IXGBE_RXDCTL_VME;
1985 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1987 /* record those setting for HW strip per queue */
1988 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1992 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1994 struct ixgbe_hw *hw =
1995 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998 struct ixgbe_rx_queue *rxq;
2000 PMD_INIT_FUNC_TRACE();
2002 if (hw->mac.type == ixgbe_mac_82598EB) {
2003 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2004 ctrl &= ~IXGBE_VLNCTRL_VME;
2005 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2007 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2008 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2009 rxq = dev->data->rx_queues[i];
2010 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2011 ctrl &= ~IXGBE_RXDCTL_VME;
2012 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2014 /* record those setting for HW strip per queue */
2015 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2021 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2023 struct ixgbe_hw *hw =
2024 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027 struct ixgbe_rx_queue *rxq;
2029 PMD_INIT_FUNC_TRACE();
2031 if (hw->mac.type == ixgbe_mac_82598EB) {
2032 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2033 ctrl |= IXGBE_VLNCTRL_VME;
2034 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2036 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2037 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2038 rxq = dev->data->rx_queues[i];
2039 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2040 ctrl |= IXGBE_RXDCTL_VME;
2041 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2043 /* record those setting for HW strip per queue */
2044 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2050 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2052 struct ixgbe_hw *hw =
2053 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056 PMD_INIT_FUNC_TRACE();
2058 /* DMATXCTRL: Geric Double VLAN Disable */
2059 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2060 ctrl &= ~IXGBE_DMATXCTL_GDV;
2061 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2063 /* CTRL_EXT: Global Double VLAN Disable */
2064 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2065 ctrl &= ~IXGBE_EXTENDED_VLAN;
2066 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2071 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2073 struct ixgbe_hw *hw =
2074 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 PMD_INIT_FUNC_TRACE();
2079 /* DMATXCTRL: Geric Double VLAN Enable */
2080 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2081 ctrl |= IXGBE_DMATXCTL_GDV;
2082 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2084 /* CTRL_EXT: Global Double VLAN Enable */
2085 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2086 ctrl |= IXGBE_EXTENDED_VLAN;
2087 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2089 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2090 if (hw->mac.type == ixgbe_mac_X550 ||
2091 hw->mac.type == ixgbe_mac_X550EM_x ||
2092 hw->mac.type == ixgbe_mac_X550EM_a) {
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2094 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2095 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2099 * VET EXT field in the EXVET register = 0x8100 by default
2100 * So no need to change. Same to VT field of DMATXCTL register
2105 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2107 if (mask & ETH_VLAN_STRIP_MASK) {
2108 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2109 ixgbe_vlan_hw_strip_enable_all(dev);
2111 ixgbe_vlan_hw_strip_disable_all(dev);
2114 if (mask & ETH_VLAN_FILTER_MASK) {
2115 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2116 ixgbe_vlan_hw_filter_enable(dev);
2118 ixgbe_vlan_hw_filter_disable(dev);
2121 if (mask & ETH_VLAN_EXTEND_MASK) {
2122 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2123 ixgbe_vlan_hw_extend_enable(dev);
2125 ixgbe_vlan_hw_extend_disable(dev);
2130 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2132 struct ixgbe_hw *hw =
2133 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2135 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2137 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2138 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2142 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2144 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2149 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2152 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2158 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2159 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2165 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2167 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2168 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2169 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2170 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2172 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2173 /* check multi-queue mode */
2174 switch (dev_conf->rxmode.mq_mode) {
2175 case ETH_MQ_RX_VMDQ_DCB:
2176 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2178 case ETH_MQ_RX_VMDQ_DCB_RSS:
2179 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2180 PMD_INIT_LOG(ERR, "SRIOV active,"
2181 " unsupported mq_mode rx %d.",
2182 dev_conf->rxmode.mq_mode);
2185 case ETH_MQ_RX_VMDQ_RSS:
2186 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2187 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2188 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2189 PMD_INIT_LOG(ERR, "SRIOV is active,"
2190 " invalid queue number"
2191 " for VMDQ RSS, allowed"
2192 " value are 1, 2 or 4.");
2196 case ETH_MQ_RX_VMDQ_ONLY:
2197 case ETH_MQ_RX_NONE:
2198 /* if nothing mq mode configure, use default scheme */
2199 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2200 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2201 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2203 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2204 /* SRIOV only works in VMDq enable mode */
2205 PMD_INIT_LOG(ERR, "SRIOV is active,"
2206 " wrong mq_mode rx %d.",
2207 dev_conf->rxmode.mq_mode);
2211 switch (dev_conf->txmode.mq_mode) {
2212 case ETH_MQ_TX_VMDQ_DCB:
2213 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2214 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2216 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2217 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2221 /* check valid queue number */
2222 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2223 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2224 PMD_INIT_LOG(ERR, "SRIOV is active,"
2225 " nb_rx_q=%d nb_tx_q=%d queue number"
2226 " must be less than or equal to %d.",
2228 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2232 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2233 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2237 /* check configuration for vmdb+dcb mode */
2238 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2239 const struct rte_eth_vmdq_dcb_conf *conf;
2241 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2242 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2243 IXGBE_VMDQ_DCB_NB_QUEUES);
2246 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2247 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2248 conf->nb_queue_pools == ETH_32_POOLS)) {
2249 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2250 " nb_queue_pools must be %d or %d.",
2251 ETH_16_POOLS, ETH_32_POOLS);
2255 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2256 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2258 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2259 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2260 IXGBE_VMDQ_DCB_NB_QUEUES);
2263 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2264 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2265 conf->nb_queue_pools == ETH_32_POOLS)) {
2266 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2267 " nb_queue_pools != %d and"
2268 " nb_queue_pools != %d.",
2269 ETH_16_POOLS, ETH_32_POOLS);
2274 /* For DCB mode check our configuration before we go further */
2275 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2276 const struct rte_eth_dcb_rx_conf *conf;
2278 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2279 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2280 IXGBE_DCB_NB_QUEUES);
2283 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2284 if (!(conf->nb_tcs == ETH_4_TCS ||
2285 conf->nb_tcs == ETH_8_TCS)) {
2286 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2287 " and nb_tcs != %d.",
2288 ETH_4_TCS, ETH_8_TCS);
2293 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2294 const struct rte_eth_dcb_tx_conf *conf;
2296 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2297 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2298 IXGBE_DCB_NB_QUEUES);
2301 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2302 if (!(conf->nb_tcs == ETH_4_TCS ||
2303 conf->nb_tcs == ETH_8_TCS)) {
2304 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2305 " and nb_tcs != %d.",
2306 ETH_4_TCS, ETH_8_TCS);
2312 * When DCB/VT is off, maximum number of queues changes,
2313 * except for 82598EB, which remains constant.
2315 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2316 hw->mac.type != ixgbe_mac_82598EB) {
2317 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2319 "Neither VT nor DCB are enabled, "
2321 IXGBE_NONE_MODE_TX_NB_QUEUES);
2330 ixgbe_dev_configure(struct rte_eth_dev *dev)
2332 struct ixgbe_interrupt *intr =
2333 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2334 struct ixgbe_adapter *adapter =
2335 (struct ixgbe_adapter *)dev->data->dev_private;
2338 PMD_INIT_FUNC_TRACE();
2339 /* multipe queue mode checking */
2340 ret = ixgbe_check_mq_mode(dev);
2342 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2347 /* set flag to update link status after init */
2348 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2351 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2352 * allocation or vector Rx preconditions we will reset it.
2354 adapter->rx_bulk_alloc_allowed = true;
2355 adapter->rx_vec_allowed = true;
2361 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2363 struct ixgbe_hw *hw =
2364 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2365 struct ixgbe_interrupt *intr =
2366 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2369 /* only set up it on X550EM_X */
2370 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2371 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2372 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2373 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2374 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2375 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2380 * Configure device link speed and setup link.
2381 * It returns 0 on success.
2384 ixgbe_dev_start(struct rte_eth_dev *dev)
2386 struct ixgbe_hw *hw =
2387 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388 struct ixgbe_vf_info *vfinfo =
2389 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2390 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2391 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2392 uint32_t intr_vector = 0;
2393 int err, link_up = 0, negotiate = 0;
2398 uint32_t *link_speeds;
2400 PMD_INIT_FUNC_TRACE();
2402 /* IXGBE devices don't support:
2403 * - half duplex (checked afterwards for valid speeds)
2404 * - fixed speed: TODO implement
2406 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2407 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2408 dev->data->port_id);
2412 /* disable uio/vfio intr/eventfd mapping */
2413 rte_intr_disable(intr_handle);
2416 hw->adapter_stopped = 0;
2417 ixgbe_stop_adapter(hw);
2419 /* reinitialize adapter
2420 * this calls reset and start
2422 status = ixgbe_pf_reset_hw(hw);
2425 hw->mac.ops.start_hw(hw);
2426 hw->mac.get_link_status = true;
2428 /* configure PF module if SRIOV enabled */
2429 ixgbe_pf_host_configure(dev);
2431 ixgbe_dev_phy_intr_setup(dev);
2433 /* check and configure queue intr-vector mapping */
2434 if ((rte_intr_cap_multiple(intr_handle) ||
2435 !RTE_ETH_DEV_SRIOV(dev).active) &&
2436 dev->data->dev_conf.intr_conf.rxq != 0) {
2437 intr_vector = dev->data->nb_rx_queues;
2438 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2439 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2440 IXGBE_MAX_INTR_QUEUE_NUM);
2443 if (rte_intr_efd_enable(intr_handle, intr_vector))
2447 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2448 intr_handle->intr_vec =
2449 rte_zmalloc("intr_vec",
2450 dev->data->nb_rx_queues * sizeof(int), 0);
2451 if (intr_handle->intr_vec == NULL) {
2452 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2453 " intr_vec\n", dev->data->nb_rx_queues);
2458 /* confiugre msix for sleep until rx interrupt */
2459 ixgbe_configure_msix(dev);
2461 /* initialize transmission unit */
2462 ixgbe_dev_tx_init(dev);
2464 /* This can fail when allocating mbufs for descriptor rings */
2465 err = ixgbe_dev_rx_init(dev);
2467 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2471 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2472 ETH_VLAN_EXTEND_MASK;
2473 ixgbe_vlan_offload_set(dev, mask);
2475 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2476 /* Enable vlan filtering for VMDq */
2477 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2480 /* Configure DCB hw */
2481 ixgbe_configure_dcb(dev);
2483 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2484 err = ixgbe_fdir_configure(dev);
2489 /* Restore vf rate limit */
2490 if (vfinfo != NULL) {
2491 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2492 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2493 if (vfinfo[vf].tx_rate[idx] != 0)
2494 rte_pmd_ixgbe_set_vf_rate_limit(
2495 dev->data->port_id, vf,
2496 vfinfo[vf].tx_rate[idx],
2500 ixgbe_restore_statistics_mapping(dev);
2502 err = ixgbe_dev_rxtx_start(dev);
2504 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2508 /* Skip link setup if loopback mode is enabled for 82599. */
2509 if (hw->mac.type == ixgbe_mac_82599EB &&
2510 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2511 goto skip_link_setup;
2513 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2514 err = hw->mac.ops.setup_sfp(hw);
2519 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2520 /* Turn on the copper */
2521 ixgbe_set_phy_power(hw, true);
2523 /* Turn on the laser */
2524 ixgbe_enable_tx_laser(hw);
2527 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2530 dev->data->dev_link.link_status = link_up;
2532 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2536 link_speeds = &dev->data->dev_conf.link_speeds;
2537 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2538 ETH_LINK_SPEED_10G)) {
2539 PMD_INIT_LOG(ERR, "Invalid link setting");
2544 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2545 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2546 IXGBE_LINK_SPEED_82599_AUTONEG :
2547 IXGBE_LINK_SPEED_82598_AUTONEG;
2549 if (*link_speeds & ETH_LINK_SPEED_10G)
2550 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2551 if (*link_speeds & ETH_LINK_SPEED_1G)
2552 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2553 if (*link_speeds & ETH_LINK_SPEED_100M)
2554 speed |= IXGBE_LINK_SPEED_100_FULL;
2557 err = ixgbe_setup_link(hw, speed, link_up);
2563 if (rte_intr_allow_others(intr_handle)) {
2564 /* check if lsc interrupt is enabled */
2565 if (dev->data->dev_conf.intr_conf.lsc != 0)
2566 ixgbe_dev_lsc_interrupt_setup(dev);
2567 ixgbe_dev_macsec_interrupt_setup(dev);
2569 rte_intr_callback_unregister(intr_handle,
2570 ixgbe_dev_interrupt_handler, dev);
2571 if (dev->data->dev_conf.intr_conf.lsc != 0)
2572 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2573 " no intr multiplex\n");
2576 /* check if rxq interrupt is enabled */
2577 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2578 rte_intr_dp_is_en(intr_handle))
2579 ixgbe_dev_rxq_interrupt_setup(dev);
2581 /* enable uio/vfio intr/eventfd mapping */
2582 rte_intr_enable(intr_handle);
2584 /* resume enabled intr since hw reset */
2585 ixgbe_enable_intr(dev);
2586 ixgbe_l2_tunnel_conf(dev);
2587 ixgbe_filter_restore(dev);
2592 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2593 ixgbe_dev_clear_queues(dev);
2598 * Stop device: disable rx and tx functions to allow for reconfiguring.
2601 ixgbe_dev_stop(struct rte_eth_dev *dev)
2603 struct rte_eth_link link;
2604 struct ixgbe_hw *hw =
2605 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606 struct ixgbe_vf_info *vfinfo =
2607 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2608 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2609 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2612 PMD_INIT_FUNC_TRACE();
2614 /* disable interrupts */
2615 ixgbe_disable_intr(hw);
2618 ixgbe_pf_reset_hw(hw);
2619 hw->adapter_stopped = 0;
2622 ixgbe_stop_adapter(hw);
2624 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2625 vfinfo[vf].clear_to_send = false;
2627 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2628 /* Turn off the copper */
2629 ixgbe_set_phy_power(hw, false);
2631 /* Turn off the laser */
2632 ixgbe_disable_tx_laser(hw);
2635 ixgbe_dev_clear_queues(dev);
2637 /* Clear stored conf */
2638 dev->data->scattered_rx = 0;
2641 /* Clear recorded link status */
2642 memset(&link, 0, sizeof(link));
2643 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2645 if (!rte_intr_allow_others(intr_handle))
2646 /* resume to the default handler */
2647 rte_intr_callback_register(intr_handle,
2648 ixgbe_dev_interrupt_handler,
2651 /* Clean datapath event and queue/vec mapping */
2652 rte_intr_efd_disable(intr_handle);
2653 if (intr_handle->intr_vec != NULL) {
2654 rte_free(intr_handle->intr_vec);
2655 intr_handle->intr_vec = NULL;
2660 * Set device link up: enable tx.
2663 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2665 struct ixgbe_hw *hw =
2666 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2667 if (hw->mac.type == ixgbe_mac_82599EB) {
2668 #ifdef RTE_NIC_BYPASS
2669 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2670 /* Not suported in bypass mode */
2671 PMD_INIT_LOG(ERR, "Set link up is not supported "
2672 "by device id 0x%x", hw->device_id);
2678 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2679 /* Turn on the copper */
2680 ixgbe_set_phy_power(hw, true);
2682 /* Turn on the laser */
2683 ixgbe_enable_tx_laser(hw);
2690 * Set device link down: disable tx.
2693 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2695 struct ixgbe_hw *hw =
2696 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697 if (hw->mac.type == ixgbe_mac_82599EB) {
2698 #ifdef RTE_NIC_BYPASS
2699 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2700 /* Not suported in bypass mode */
2701 PMD_INIT_LOG(ERR, "Set link down is not supported "
2702 "by device id 0x%x", hw->device_id);
2708 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2709 /* Turn off the copper */
2710 ixgbe_set_phy_power(hw, false);
2712 /* Turn off the laser */
2713 ixgbe_disable_tx_laser(hw);
2720 * Reest and stop device.
2723 ixgbe_dev_close(struct rte_eth_dev *dev)
2725 struct ixgbe_hw *hw =
2726 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2728 PMD_INIT_FUNC_TRACE();
2730 ixgbe_pf_reset_hw(hw);
2732 ixgbe_dev_stop(dev);
2733 hw->adapter_stopped = 1;
2735 ixgbe_dev_free_queues(dev);
2737 ixgbe_disable_pcie_master(hw);
2739 /* reprogram the RAR[0] in case user changed it. */
2740 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2744 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2745 struct ixgbe_hw_stats *hw_stats,
2746 struct ixgbe_macsec_stats *macsec_stats,
2747 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2748 uint64_t *total_qprc, uint64_t *total_qprdc)
2750 uint32_t bprc, lxon, lxoff, total;
2751 uint32_t delta_gprc = 0;
2753 /* Workaround for RX byte count not including CRC bytes when CRC
2754 * strip is enabled. CRC bytes are removed from counters when crc_strip
2757 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2758 IXGBE_HLREG0_RXCRCSTRP);
2760 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2761 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2762 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2763 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2765 for (i = 0; i < 8; i++) {
2766 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2768 /* global total per queue */
2769 hw_stats->mpc[i] += mp;
2770 /* Running comprehensive total for stats display */
2771 *total_missed_rx += hw_stats->mpc[i];
2772 if (hw->mac.type == ixgbe_mac_82598EB) {
2773 hw_stats->rnbc[i] +=
2774 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2775 hw_stats->pxonrxc[i] +=
2776 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2777 hw_stats->pxoffrxc[i] +=
2778 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2780 hw_stats->pxonrxc[i] +=
2781 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2782 hw_stats->pxoffrxc[i] +=
2783 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2784 hw_stats->pxon2offc[i] +=
2785 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2787 hw_stats->pxontxc[i] +=
2788 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2789 hw_stats->pxofftxc[i] +=
2790 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2792 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2793 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2794 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2795 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2797 delta_gprc += delta_qprc;
2799 hw_stats->qprc[i] += delta_qprc;
2800 hw_stats->qptc[i] += delta_qptc;
2802 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2803 hw_stats->qbrc[i] +=
2804 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2806 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2808 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2809 hw_stats->qbtc[i] +=
2810 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2812 hw_stats->qprdc[i] += delta_qprdc;
2813 *total_qprdc += hw_stats->qprdc[i];
2815 *total_qprc += hw_stats->qprc[i];
2816 *total_qbrc += hw_stats->qbrc[i];
2818 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2819 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2820 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2823 * An errata states that gprc actually counts good + missed packets:
2824 * Workaround to set gprc to summated queue packet receives
2826 hw_stats->gprc = *total_qprc;
2828 if (hw->mac.type != ixgbe_mac_82598EB) {
2829 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2830 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2831 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2832 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2833 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2834 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2835 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2836 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2838 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2839 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2840 /* 82598 only has a counter in the high register */
2841 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2842 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2843 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2845 uint64_t old_tpr = hw_stats->tpr;
2847 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2848 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2851 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2853 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2854 hw_stats->gptc += delta_gptc;
2855 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2856 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2859 * Workaround: mprc hardware is incorrectly counting
2860 * broadcasts, so for now we subtract those.
2862 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2863 hw_stats->bprc += bprc;
2864 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2865 if (hw->mac.type == ixgbe_mac_82598EB)
2866 hw_stats->mprc -= bprc;
2868 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2869 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2870 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2871 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2872 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2873 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2875 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2876 hw_stats->lxontxc += lxon;
2877 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2878 hw_stats->lxofftxc += lxoff;
2879 total = lxon + lxoff;
2881 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2882 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2883 hw_stats->gptc -= total;
2884 hw_stats->mptc -= total;
2885 hw_stats->ptc64 -= total;
2886 hw_stats->gotc -= total * ETHER_MIN_LEN;
2888 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2889 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2890 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2891 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2892 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2893 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2894 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2895 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2896 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2897 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2898 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2899 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2900 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2901 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2902 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2903 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2904 /* Only read FCOE on 82599 */
2905 if (hw->mac.type != ixgbe_mac_82598EB) {
2906 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2907 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2908 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2909 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2910 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2913 /* Flow Director Stats registers */
2914 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2915 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2917 /* MACsec Stats registers */
2918 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2919 macsec_stats->out_pkts_encrypted +=
2920 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2921 macsec_stats->out_pkts_protected +=
2922 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2923 macsec_stats->out_octets_encrypted +=
2924 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2925 macsec_stats->out_octets_protected +=
2926 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2927 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2928 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2929 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2930 macsec_stats->in_pkts_unknownsci +=
2931 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2932 macsec_stats->in_octets_decrypted +=
2933 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2934 macsec_stats->in_octets_validated +=
2935 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2936 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2937 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2938 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2939 for (i = 0; i < 2; i++) {
2940 macsec_stats->in_pkts_ok +=
2941 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2942 macsec_stats->in_pkts_invalid +=
2943 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2944 macsec_stats->in_pkts_notvalid +=
2945 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2947 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2948 macsec_stats->in_pkts_notusingsa +=
2949 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2953 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2956 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2958 struct ixgbe_hw *hw =
2959 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960 struct ixgbe_hw_stats *hw_stats =
2961 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2962 struct ixgbe_macsec_stats *macsec_stats =
2963 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2964 dev->data->dev_private);
2965 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2968 total_missed_rx = 0;
2973 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2974 &total_qbrc, &total_qprc, &total_qprdc);
2979 /* Fill out the rte_eth_stats statistics structure */
2980 stats->ipackets = total_qprc;
2981 stats->ibytes = total_qbrc;
2982 stats->opackets = hw_stats->gptc;
2983 stats->obytes = hw_stats->gotc;
2985 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2986 stats->q_ipackets[i] = hw_stats->qprc[i];
2987 stats->q_opackets[i] = hw_stats->qptc[i];
2988 stats->q_ibytes[i] = hw_stats->qbrc[i];
2989 stats->q_obytes[i] = hw_stats->qbtc[i];
2990 stats->q_errors[i] = hw_stats->qprdc[i];
2994 stats->imissed = total_missed_rx;
2995 stats->ierrors = hw_stats->crcerrs +
3011 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3013 struct ixgbe_hw_stats *stats =
3014 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3016 /* HW registers are cleared on read */
3017 ixgbe_dev_stats_get(dev, NULL);
3019 /* Reset software totals */
3020 memset(stats, 0, sizeof(*stats));
3023 /* This function calculates the number of xstats based on the current config */
3025 ixgbe_xstats_calc_num(void) {
3026 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3027 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3028 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3031 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3032 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3034 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3035 unsigned stat, i, count;
3037 if (xstats_names != NULL) {
3040 /* Note: limit >= cnt_stats checked upstream
3041 * in rte_eth_xstats_names()
3044 /* Extended stats from ixgbe_hw_stats */
3045 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3046 snprintf(xstats_names[count].name,
3047 sizeof(xstats_names[count].name),
3049 rte_ixgbe_stats_strings[i].name);
3054 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3055 snprintf(xstats_names[count].name,
3056 sizeof(xstats_names[count].name),
3058 rte_ixgbe_macsec_strings[i].name);
3062 /* RX Priority Stats */
3063 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3064 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3065 snprintf(xstats_names[count].name,
3066 sizeof(xstats_names[count].name),
3067 "rx_priority%u_%s", i,
3068 rte_ixgbe_rxq_strings[stat].name);
3073 /* TX Priority Stats */
3074 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3075 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3076 snprintf(xstats_names[count].name,
3077 sizeof(xstats_names[count].name),
3078 "tx_priority%u_%s", i,
3079 rte_ixgbe_txq_strings[stat].name);
3087 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3088 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3092 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3095 if (xstats_names != NULL)
3096 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3097 snprintf(xstats_names[i].name,
3098 sizeof(xstats_names[i].name),
3099 "%s", rte_ixgbevf_stats_strings[i].name);
3100 return IXGBEVF_NB_XSTATS;
3104 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3107 struct ixgbe_hw *hw =
3108 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3109 struct ixgbe_hw_stats *hw_stats =
3110 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3111 struct ixgbe_macsec_stats *macsec_stats =
3112 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3113 dev->data->dev_private);
3114 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3115 unsigned i, stat, count = 0;
3117 count = ixgbe_xstats_calc_num();
3122 total_missed_rx = 0;
3127 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3128 &total_qbrc, &total_qprc, &total_qprdc);
3130 /* If this is a reset xstats is NULL, and we have cleared the
3131 * registers by reading them.
3136 /* Extended stats from ixgbe_hw_stats */
3138 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3139 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3140 rte_ixgbe_stats_strings[i].offset);
3141 xstats[count].id = count;
3146 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3147 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3148 rte_ixgbe_macsec_strings[i].offset);
3149 xstats[count].id = count;
3153 /* RX Priority Stats */
3154 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3155 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3156 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3157 rte_ixgbe_rxq_strings[stat].offset +
3158 (sizeof(uint64_t) * i));
3159 xstats[count].id = count;
3164 /* TX Priority Stats */
3165 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3166 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3167 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3168 rte_ixgbe_txq_strings[stat].offset +
3169 (sizeof(uint64_t) * i));
3170 xstats[count].id = count;
3178 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3180 struct ixgbe_hw_stats *stats =
3181 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3182 struct ixgbe_macsec_stats *macsec_stats =
3183 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3184 dev->data->dev_private);
3186 unsigned count = ixgbe_xstats_calc_num();
3188 /* HW registers are cleared on read */
3189 ixgbe_dev_xstats_get(dev, NULL, count);
3191 /* Reset software totals */
3192 memset(stats, 0, sizeof(*stats));
3193 memset(macsec_stats, 0, sizeof(*macsec_stats));
3197 ixgbevf_update_stats(struct rte_eth_dev *dev)
3199 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3200 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3201 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3203 /* Good Rx packet, include VF loopback */
3204 UPDATE_VF_STAT(IXGBE_VFGPRC,
3205 hw_stats->last_vfgprc, hw_stats->vfgprc);
3207 /* Good Rx octets, include VF loopback */
3208 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3209 hw_stats->last_vfgorc, hw_stats->vfgorc);
3211 /* Good Tx packet, include VF loopback */
3212 UPDATE_VF_STAT(IXGBE_VFGPTC,
3213 hw_stats->last_vfgptc, hw_stats->vfgptc);
3215 /* Good Tx octets, include VF loopback */
3216 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3217 hw_stats->last_vfgotc, hw_stats->vfgotc);
3219 /* Rx Multicst Packet */
3220 UPDATE_VF_STAT(IXGBE_VFMPRC,
3221 hw_stats->last_vfmprc, hw_stats->vfmprc);
3225 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3228 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3229 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3232 if (n < IXGBEVF_NB_XSTATS)
3233 return IXGBEVF_NB_XSTATS;
3235 ixgbevf_update_stats(dev);
3240 /* Extended stats */
3241 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3242 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3243 rte_ixgbevf_stats_strings[i].offset);
3246 return IXGBEVF_NB_XSTATS;
3250 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3252 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3253 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3255 ixgbevf_update_stats(dev);
3260 stats->ipackets = hw_stats->vfgprc;
3261 stats->ibytes = hw_stats->vfgorc;
3262 stats->opackets = hw_stats->vfgptc;
3263 stats->obytes = hw_stats->vfgotc;
3267 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3269 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3270 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3272 /* Sync HW register to the last stats */
3273 ixgbevf_dev_stats_get(dev, NULL);
3275 /* reset HW current stats*/
3276 hw_stats->vfgprc = 0;
3277 hw_stats->vfgorc = 0;
3278 hw_stats->vfgptc = 0;
3279 hw_stats->vfgotc = 0;
3283 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3285 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3286 u16 eeprom_verh, eeprom_verl;
3290 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3291 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3293 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3294 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3296 ret += 1; /* add the size of '\0' */
3297 if (fw_size < (u32)ret)
3304 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3306 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3307 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3310 dev_info->pci_dev = pci_dev;
3311 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3312 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3313 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3315 * When DCB/VT is off, maximum number of queues changes,
3316 * except for 82598EB, which remains constant.
3318 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3319 hw->mac.type != ixgbe_mac_82598EB)
3320 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3322 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3323 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3324 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3325 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3326 dev_info->max_vfs = pci_dev->max_vfs;
3327 if (hw->mac.type == ixgbe_mac_82598EB)
3328 dev_info->max_vmdq_pools = ETH_16_POOLS;
3330 dev_info->max_vmdq_pools = ETH_64_POOLS;
3331 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3332 dev_info->rx_offload_capa =
3333 DEV_RX_OFFLOAD_VLAN_STRIP |
3334 DEV_RX_OFFLOAD_IPV4_CKSUM |
3335 DEV_RX_OFFLOAD_UDP_CKSUM |
3336 DEV_RX_OFFLOAD_TCP_CKSUM;
3339 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3342 if ((hw->mac.type == ixgbe_mac_82599EB ||
3343 hw->mac.type == ixgbe_mac_X540) &&
3344 !RTE_ETH_DEV_SRIOV(dev).active)
3345 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3347 if (hw->mac.type == ixgbe_mac_82599EB ||
3348 hw->mac.type == ixgbe_mac_X540)
3349 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3351 if (hw->mac.type == ixgbe_mac_X550 ||
3352 hw->mac.type == ixgbe_mac_X550EM_x ||
3353 hw->mac.type == ixgbe_mac_X550EM_a)
3354 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3356 dev_info->tx_offload_capa =
3357 DEV_TX_OFFLOAD_VLAN_INSERT |
3358 DEV_TX_OFFLOAD_IPV4_CKSUM |
3359 DEV_TX_OFFLOAD_UDP_CKSUM |
3360 DEV_TX_OFFLOAD_TCP_CKSUM |
3361 DEV_TX_OFFLOAD_SCTP_CKSUM |
3362 DEV_TX_OFFLOAD_TCP_TSO;
3364 if (hw->mac.type == ixgbe_mac_82599EB ||
3365 hw->mac.type == ixgbe_mac_X540)
3366 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3368 if (hw->mac.type == ixgbe_mac_X550 ||
3369 hw->mac.type == ixgbe_mac_X550EM_x ||
3370 hw->mac.type == ixgbe_mac_X550EM_a)
3371 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3373 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3375 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3376 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3377 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3379 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3383 dev_info->default_txconf = (struct rte_eth_txconf) {
3385 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3386 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3387 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3389 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3390 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3391 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3392 ETH_TXQ_FLAGS_NOOFFLOADS,
3395 dev_info->rx_desc_lim = rx_desc_lim;
3396 dev_info->tx_desc_lim = tx_desc_lim;
3398 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3399 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3400 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3402 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3403 if (hw->mac.type == ixgbe_mac_X540 ||
3404 hw->mac.type == ixgbe_mac_X540_vf ||
3405 hw->mac.type == ixgbe_mac_X550 ||
3406 hw->mac.type == ixgbe_mac_X550_vf) {
3407 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3411 static const uint32_t *
3412 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3414 static const uint32_t ptypes[] = {
3415 /* For non-vec functions,
3416 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3417 * for vec functions,
3418 * refers to _recv_raw_pkts_vec().
3422 RTE_PTYPE_L3_IPV4_EXT,
3424 RTE_PTYPE_L3_IPV6_EXT,
3428 RTE_PTYPE_TUNNEL_IP,
3429 RTE_PTYPE_INNER_L3_IPV6,
3430 RTE_PTYPE_INNER_L3_IPV6_EXT,
3431 RTE_PTYPE_INNER_L4_TCP,
3432 RTE_PTYPE_INNER_L4_UDP,
3436 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3437 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3438 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3439 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3445 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3446 struct rte_eth_dev_info *dev_info)
3448 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3449 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3451 dev_info->pci_dev = pci_dev;
3452 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3453 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3454 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3455 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3456 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3457 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3458 dev_info->max_vfs = pci_dev->max_vfs;
3459 if (hw->mac.type == ixgbe_mac_82598EB)
3460 dev_info->max_vmdq_pools = ETH_16_POOLS;
3462 dev_info->max_vmdq_pools = ETH_64_POOLS;
3463 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3464 DEV_RX_OFFLOAD_IPV4_CKSUM |
3465 DEV_RX_OFFLOAD_UDP_CKSUM |
3466 DEV_RX_OFFLOAD_TCP_CKSUM;
3467 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3468 DEV_TX_OFFLOAD_IPV4_CKSUM |
3469 DEV_TX_OFFLOAD_UDP_CKSUM |
3470 DEV_TX_OFFLOAD_TCP_CKSUM |
3471 DEV_TX_OFFLOAD_SCTP_CKSUM |
3472 DEV_TX_OFFLOAD_TCP_TSO;
3474 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3476 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3477 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3478 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3480 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3484 dev_info->default_txconf = (struct rte_eth_txconf) {
3486 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3487 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3488 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3490 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3491 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3492 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3493 ETH_TXQ_FLAGS_NOOFFLOADS,
3496 dev_info->rx_desc_lim = rx_desc_lim;
3497 dev_info->tx_desc_lim = tx_desc_lim;
3500 /* return 0 means link status changed, -1 means not changed */
3502 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3504 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3505 struct rte_eth_link link, old;
3506 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3510 link.link_status = ETH_LINK_DOWN;
3511 link.link_speed = 0;
3512 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3513 memset(&old, 0, sizeof(old));
3514 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3516 hw->mac.get_link_status = true;
3518 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3519 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3520 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3522 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3525 link.link_speed = ETH_SPEED_NUM_100M;
3526 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3527 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3528 if (link.link_status == old.link_status)
3534 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3535 if (link.link_status == old.link_status)
3539 link.link_status = ETH_LINK_UP;
3540 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3542 switch (link_speed) {
3544 case IXGBE_LINK_SPEED_UNKNOWN:
3545 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3546 link.link_speed = ETH_SPEED_NUM_100M;
3549 case IXGBE_LINK_SPEED_100_FULL:
3550 link.link_speed = ETH_SPEED_NUM_100M;
3553 case IXGBE_LINK_SPEED_1GB_FULL:
3554 link.link_speed = ETH_SPEED_NUM_1G;
3557 case IXGBE_LINK_SPEED_10GB_FULL:
3558 link.link_speed = ETH_SPEED_NUM_10G;
3561 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3563 if (link.link_status == old.link_status)
3570 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3572 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3575 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3576 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3577 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3581 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3583 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3587 fctrl &= (~IXGBE_FCTRL_UPE);
3588 if (dev->data->all_multicast == 1)
3589 fctrl |= IXGBE_FCTRL_MPE;
3591 fctrl &= (~IXGBE_FCTRL_MPE);
3592 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3596 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3598 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3602 fctrl |= IXGBE_FCTRL_MPE;
3603 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3607 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3609 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3612 if (dev->data->promiscuous == 1)
3613 return; /* must remain in all_multicast mode */
3615 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3616 fctrl &= (~IXGBE_FCTRL_MPE);
3617 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3621 * It clears the interrupt causes and enables the interrupt.
3622 * It will be called once only during nic initialized.
3625 * Pointer to struct rte_eth_dev.
3628 * - On success, zero.
3629 * - On failure, a negative value.
3632 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3634 struct ixgbe_interrupt *intr =
3635 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3637 ixgbe_dev_link_status_print(dev);
3638 intr->mask |= IXGBE_EICR_LSC;
3644 * It clears the interrupt causes and enables the interrupt.
3645 * It will be called once only during nic initialized.
3648 * Pointer to struct rte_eth_dev.
3651 * - On success, zero.
3652 * - On failure, a negative value.
3655 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3657 struct ixgbe_interrupt *intr =
3658 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3660 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3666 * It clears the interrupt causes and enables the interrupt.
3667 * It will be called once only during nic initialized.
3670 * Pointer to struct rte_eth_dev.
3673 * - On success, zero.
3674 * - On failure, a negative value.
3677 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3679 struct ixgbe_interrupt *intr =
3680 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3682 intr->mask |= IXGBE_EICR_LINKSEC;
3688 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3691 * Pointer to struct rte_eth_dev.
3694 * - On success, zero.
3695 * - On failure, a negative value.
3698 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702 struct ixgbe_interrupt *intr =
3703 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3705 /* clear all cause mask */
3706 ixgbe_disable_intr(hw);
3708 /* read-on-clear nic registers here */
3709 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3710 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3714 /* set flag for async link update */
3715 if (eicr & IXGBE_EICR_LSC)
3716 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3718 if (eicr & IXGBE_EICR_MAILBOX)
3719 intr->flags |= IXGBE_FLAG_MAILBOX;
3721 if (eicr & IXGBE_EICR_LINKSEC)
3722 intr->flags |= IXGBE_FLAG_MACSEC;
3724 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3725 hw->phy.type == ixgbe_phy_x550em_ext_t &&
3726 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3727 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3733 * It gets and then prints the link status.
3736 * Pointer to struct rte_eth_dev.
3739 * - On success, zero.
3740 * - On failure, a negative value.
3743 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3745 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3746 struct rte_eth_link link;
3748 memset(&link, 0, sizeof(link));
3749 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3750 if (link.link_status) {
3751 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3752 (int)(dev->data->port_id),
3753 (unsigned)link.link_speed,
3754 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3755 "full-duplex" : "half-duplex");
3757 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3758 (int)(dev->data->port_id));
3760 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3761 pci_dev->addr.domain,
3763 pci_dev->addr.devid,
3764 pci_dev->addr.function);
3768 * It executes link_update after knowing an interrupt occurred.
3771 * Pointer to struct rte_eth_dev.
3774 * - On success, zero.
3775 * - On failure, a negative value.
3778 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3779 struct rte_intr_handle *intr_handle)
3781 struct ixgbe_interrupt *intr =
3782 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3784 struct rte_eth_link link;
3785 int intr_enable_delay = false;
3786 struct ixgbe_hw *hw =
3787 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3789 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3791 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3792 ixgbe_pf_mbx_process(dev);
3793 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3796 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3797 ixgbe_handle_lasi(hw);
3798 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3801 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3802 /* get the link status before link update, for predicting later */
3803 memset(&link, 0, sizeof(link));
3804 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3806 ixgbe_dev_link_update(dev, 0);
3809 if (!link.link_status)
3810 /* handle it 1 sec later, wait it being stable */
3811 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3812 /* likely to down */
3814 /* handle it 4 sec later, wait it being stable */
3815 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3817 ixgbe_dev_link_status_print(dev);
3819 intr_enable_delay = true;
3822 if (intr_enable_delay) {
3823 if (rte_eal_alarm_set(timeout * 1000,
3824 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3825 PMD_DRV_LOG(ERR, "Error setting alarm");
3827 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3828 ixgbe_enable_intr(dev);
3829 rte_intr_enable(intr_handle);
3837 * Interrupt handler which shall be registered for alarm callback for delayed
3838 * handling specific interrupt to wait for the stable nic state. As the
3839 * NIC interrupt state is not stable for ixgbe after link is just down,
3840 * it needs to wait 4 seconds to get the stable status.
3843 * Pointer to interrupt handle.
3845 * The address of parameter (struct rte_eth_dev *) regsitered before.
3851 ixgbe_dev_interrupt_delayed_handler(void *param)
3853 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3854 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3855 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3856 struct ixgbe_interrupt *intr =
3857 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3858 struct ixgbe_hw *hw =
3859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3862 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3863 if (eicr & IXGBE_EICR_MAILBOX)
3864 ixgbe_pf_mbx_process(dev);
3866 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3867 ixgbe_handle_lasi(hw);
3868 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3871 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3872 ixgbe_dev_link_update(dev, 0);
3873 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3874 ixgbe_dev_link_status_print(dev);
3875 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3878 if (intr->flags & IXGBE_FLAG_MACSEC) {
3879 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3881 intr->flags &= ~IXGBE_FLAG_MACSEC;
3884 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3885 ixgbe_enable_intr(dev);
3886 rte_intr_enable(intr_handle);
3890 * Interrupt handler triggered by NIC for handling
3891 * specific interrupt.
3894 * Pointer to interrupt handle.
3896 * The address of parameter (struct rte_eth_dev *) regsitered before.
3902 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3905 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3907 ixgbe_dev_interrupt_get_status(dev);
3908 ixgbe_dev_interrupt_action(dev, handle);
3912 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3914 struct ixgbe_hw *hw;
3916 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3921 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3923 struct ixgbe_hw *hw;
3925 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3926 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3930 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3932 struct ixgbe_hw *hw;
3938 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940 fc_conf->pause_time = hw->fc.pause_time;
3941 fc_conf->high_water = hw->fc.high_water[0];
3942 fc_conf->low_water = hw->fc.low_water[0];
3943 fc_conf->send_xon = hw->fc.send_xon;
3944 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3947 * Return rx_pause status according to actual setting of
3950 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3951 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3957 * Return tx_pause status according to actual setting of
3960 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3961 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3966 if (rx_pause && tx_pause)
3967 fc_conf->mode = RTE_FC_FULL;
3969 fc_conf->mode = RTE_FC_RX_PAUSE;
3971 fc_conf->mode = RTE_FC_TX_PAUSE;
3973 fc_conf->mode = RTE_FC_NONE;
3979 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3981 struct ixgbe_hw *hw;
3983 uint32_t rx_buf_size;
3984 uint32_t max_high_water;
3986 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3993 PMD_INIT_FUNC_TRACE();
3995 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3996 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3997 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4000 * At least reserve one Ethernet frame for watermark
4001 * high_water/low_water in kilo bytes for ixgbe
4003 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4004 if ((fc_conf->high_water > max_high_water) ||
4005 (fc_conf->high_water < fc_conf->low_water)) {
4006 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4007 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4011 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4012 hw->fc.pause_time = fc_conf->pause_time;
4013 hw->fc.high_water[0] = fc_conf->high_water;
4014 hw->fc.low_water[0] = fc_conf->low_water;
4015 hw->fc.send_xon = fc_conf->send_xon;
4016 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4018 err = ixgbe_fc_enable(hw);
4020 /* Not negotiated is not an error case */
4021 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4023 /* check if we want to forward MAC frames - driver doesn't have native
4024 * capability to do that, so we'll write the registers ourselves */
4026 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4028 /* set or clear MFLCN.PMCF bit depending on configuration */
4029 if (fc_conf->mac_ctrl_frame_fwd != 0)
4030 mflcn |= IXGBE_MFLCN_PMCF;
4032 mflcn &= ~IXGBE_MFLCN_PMCF;
4034 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4035 IXGBE_WRITE_FLUSH(hw);
4040 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4045 * ixgbe_pfc_enable_generic - Enable flow control
4046 * @hw: pointer to hardware structure
4047 * @tc_num: traffic class number
4048 * Enable flow control according to the current settings.
4051 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4054 uint32_t mflcn_reg, fccfg_reg;
4056 uint32_t fcrtl, fcrth;
4060 /* Validate the water mark configuration */
4061 if (!hw->fc.pause_time) {
4062 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4066 /* Low water mark of zero causes XOFF floods */
4067 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4068 /* High/Low water can not be 0 */
4069 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4070 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4071 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4075 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4076 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4077 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4081 /* Negotiate the fc mode to use */
4082 ixgbe_fc_autoneg(hw);
4084 /* Disable any previous flow control settings */
4085 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4086 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4088 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4089 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4091 switch (hw->fc.current_mode) {
4094 * If the count of enabled RX Priority Flow control >1,
4095 * and the TX pause can not be disabled
4098 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4099 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4100 if (reg & IXGBE_FCRTH_FCEN)
4104 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4106 case ixgbe_fc_rx_pause:
4108 * Rx Flow control is enabled and Tx Flow control is
4109 * disabled by software override. Since there really
4110 * isn't a way to advertise that we are capable of RX
4111 * Pause ONLY, we will advertise that we support both
4112 * symmetric and asymmetric Rx PAUSE. Later, we will
4113 * disable the adapter's ability to send PAUSE frames.
4115 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4117 * If the count of enabled RX Priority Flow control >1,
4118 * and the TX pause can not be disabled
4121 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4122 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4123 if (reg & IXGBE_FCRTH_FCEN)
4127 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4129 case ixgbe_fc_tx_pause:
4131 * Tx Flow control is enabled, and Rx Flow control is
4132 * disabled by software override.
4134 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4137 /* Flow control (both Rx and Tx) is enabled by SW override. */
4138 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4139 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4142 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4143 ret_val = IXGBE_ERR_CONFIG;
4147 /* Set 802.3x based flow control settings. */
4148 mflcn_reg |= IXGBE_MFLCN_DPF;
4149 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4150 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4152 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4153 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4154 hw->fc.high_water[tc_num]) {
4155 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4156 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4157 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4159 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4161 * In order to prevent Tx hangs when the internal Tx
4162 * switch is enabled we must set the high water mark
4163 * to the maximum FCRTH value. This allows the Tx
4164 * switch to function even under heavy Rx workloads.
4166 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4168 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4170 /* Configure pause time (2 TCs per register) */
4171 reg = hw->fc.pause_time * 0x00010001;
4172 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4173 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4175 /* Configure flow control refresh threshold value */
4176 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4183 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4185 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4186 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4188 if (hw->mac.type != ixgbe_mac_82598EB) {
4189 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4195 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4198 uint32_t rx_buf_size;
4199 uint32_t max_high_water;
4201 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4202 struct ixgbe_hw *hw =
4203 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204 struct ixgbe_dcb_config *dcb_config =
4205 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4207 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4214 PMD_INIT_FUNC_TRACE();
4216 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4217 tc_num = map[pfc_conf->priority];
4218 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4219 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4221 * At least reserve one Ethernet frame for watermark
4222 * high_water/low_water in kilo bytes for ixgbe
4224 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4225 if ((pfc_conf->fc.high_water > max_high_water) ||
4226 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4227 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4228 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4232 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4233 hw->fc.pause_time = pfc_conf->fc.pause_time;
4234 hw->fc.send_xon = pfc_conf->fc.send_xon;
4235 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4236 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4238 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4240 /* Not negotiated is not an error case */
4241 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4244 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4249 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4250 struct rte_eth_rss_reta_entry64 *reta_conf,
4253 uint16_t i, sp_reta_size;
4256 uint16_t idx, shift;
4257 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4260 PMD_INIT_FUNC_TRACE();
4262 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4263 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4268 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4269 if (reta_size != sp_reta_size) {
4270 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4271 "(%d) doesn't match the number hardware can supported "
4272 "(%d)\n", reta_size, sp_reta_size);
4276 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4277 idx = i / RTE_RETA_GROUP_SIZE;
4278 shift = i % RTE_RETA_GROUP_SIZE;
4279 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4283 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4284 if (mask == IXGBE_4_BIT_MASK)
4287 r = IXGBE_READ_REG(hw, reta_reg);
4288 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4289 if (mask & (0x1 << j))
4290 reta |= reta_conf[idx].reta[shift + j] <<
4293 reta |= r & (IXGBE_8_BIT_MASK <<
4296 IXGBE_WRITE_REG(hw, reta_reg, reta);
4303 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4304 struct rte_eth_rss_reta_entry64 *reta_conf,
4307 uint16_t i, sp_reta_size;
4310 uint16_t idx, shift;
4311 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314 PMD_INIT_FUNC_TRACE();
4315 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4316 if (reta_size != sp_reta_size) {
4317 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4318 "(%d) doesn't match the number hardware can supported "
4319 "(%d)\n", reta_size, sp_reta_size);
4323 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4324 idx = i / RTE_RETA_GROUP_SIZE;
4325 shift = i % RTE_RETA_GROUP_SIZE;
4326 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4331 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4332 reta = IXGBE_READ_REG(hw, reta_reg);
4333 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4334 if (mask & (0x1 << j))
4335 reta_conf[idx].reta[shift + j] =
4336 ((reta >> (CHAR_BIT * j)) &
4345 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4346 uint32_t index, uint32_t pool)
4348 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4349 uint32_t enable_addr = 1;
4351 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4355 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4357 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4359 ixgbe_clear_rar(hw, index);
4363 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4365 ixgbe_remove_rar(dev, 0);
4367 ixgbe_add_rar(dev, addr, 0, 0);
4371 is_ixgbe_pmd(const char *driver_name)
4373 if (!strstr(driver_name, "ixgbe"))
4376 if (strstr(driver_name, "ixgbe_vf"))
4383 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4384 struct ether_addr *mac_addr)
4386 struct ixgbe_hw *hw;
4387 struct ixgbe_vf_info *vfinfo;
4389 uint8_t *new_mac = (uint8_t *)(mac_addr);
4390 struct rte_eth_dev *dev;
4391 struct rte_eth_dev_info dev_info;
4393 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4395 dev = &rte_eth_devices[port];
4396 rte_eth_dev_info_get(port, &dev_info);
4398 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4401 if (vf >= dev_info.max_vfs)
4404 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4405 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4406 rar_entry = hw->mac.num_rar_entries - (vf + 1);
4408 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4409 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4411 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4418 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4422 struct ixgbe_hw *hw;
4423 struct rte_eth_dev_info dev_info;
4424 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4426 ixgbe_dev_info_get(dev, &dev_info);
4428 /* check that mtu is within the allowed range */
4429 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4432 /* refuse mtu that requires the support of scattered packets when this
4433 * feature has not been enabled before.
4435 if (!dev->data->scattered_rx &&
4436 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4437 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4440 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4441 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4443 /* switch to jumbo mode if needed */
4444 if (frame_size > ETHER_MAX_LEN) {
4445 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4446 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4448 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4449 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4451 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4453 /* update max frame size */
4454 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4456 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4457 maxfrs &= 0x0000FFFF;
4458 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4459 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4465 * Virtual Function operations
4468 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4470 PMD_INIT_FUNC_TRACE();
4472 /* Clear interrupt mask to stop from interrupts being generated */
4473 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4475 IXGBE_WRITE_FLUSH(hw);
4479 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4481 PMD_INIT_FUNC_TRACE();
4483 /* VF enable interrupt autoclean */
4484 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4485 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4486 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4488 IXGBE_WRITE_FLUSH(hw);
4492 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4494 struct rte_eth_conf *conf = &dev->data->dev_conf;
4495 struct ixgbe_adapter *adapter =
4496 (struct ixgbe_adapter *)dev->data->dev_private;
4498 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4499 dev->data->port_id);
4502 * VF has no ability to enable/disable HW CRC
4503 * Keep the persistent behavior the same as Host PF
4505 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4506 if (!conf->rxmode.hw_strip_crc) {
4507 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4508 conf->rxmode.hw_strip_crc = 1;
4511 if (conf->rxmode.hw_strip_crc) {
4512 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4513 conf->rxmode.hw_strip_crc = 0;
4518 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4519 * allocation or vector Rx preconditions we will reset it.
4521 adapter->rx_bulk_alloc_allowed = true;
4522 adapter->rx_vec_allowed = true;
4528 ixgbevf_dev_start(struct rte_eth_dev *dev)
4530 struct ixgbe_hw *hw =
4531 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4532 uint32_t intr_vector = 0;
4533 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4534 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4538 PMD_INIT_FUNC_TRACE();
4540 hw->mac.ops.reset_hw(hw);
4541 hw->mac.get_link_status = true;
4543 /* negotiate mailbox API version to use with the PF. */
4544 ixgbevf_negotiate_api(hw);
4546 ixgbevf_dev_tx_init(dev);
4548 /* This can fail when allocating mbufs for descriptor rings */
4549 err = ixgbevf_dev_rx_init(dev);
4551 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4552 ixgbe_dev_clear_queues(dev);
4557 ixgbevf_set_vfta_all(dev, 1);
4560 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4561 ETH_VLAN_EXTEND_MASK;
4562 ixgbevf_vlan_offload_set(dev, mask);
4564 ixgbevf_dev_rxtx_start(dev);
4566 /* check and configure queue intr-vector mapping */
4567 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4568 intr_vector = dev->data->nb_rx_queues;
4569 if (rte_intr_efd_enable(intr_handle, intr_vector))
4573 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4574 intr_handle->intr_vec =
4575 rte_zmalloc("intr_vec",
4576 dev->data->nb_rx_queues * sizeof(int), 0);
4577 if (intr_handle->intr_vec == NULL) {
4578 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4579 " intr_vec\n", dev->data->nb_rx_queues);
4583 ixgbevf_configure_msix(dev);
4585 rte_intr_enable(intr_handle);
4587 /* Re-enable interrupt for VF */
4588 ixgbevf_intr_enable(hw);
4594 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4596 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4597 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4598 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4600 PMD_INIT_FUNC_TRACE();
4602 ixgbevf_intr_disable(hw);
4604 hw->adapter_stopped = 1;
4605 ixgbe_stop_adapter(hw);
4608 * Clear what we set, but we still keep shadow_vfta to
4609 * restore after device starts
4611 ixgbevf_set_vfta_all(dev, 0);
4613 /* Clear stored conf */
4614 dev->data->scattered_rx = 0;
4616 ixgbe_dev_clear_queues(dev);
4618 /* Clean datapath event and queue/vec mapping */
4619 rte_intr_efd_disable(intr_handle);
4620 if (intr_handle->intr_vec != NULL) {
4621 rte_free(intr_handle->intr_vec);
4622 intr_handle->intr_vec = NULL;
4627 ixgbevf_dev_close(struct rte_eth_dev *dev)
4629 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4631 PMD_INIT_FUNC_TRACE();
4635 ixgbevf_dev_stop(dev);
4637 ixgbe_dev_free_queues(dev);
4640 * Remove the VF MAC address ro ensure
4641 * that the VF traffic goes to the PF
4642 * after stop, close and detach of the VF
4644 ixgbevf_remove_mac_addr(dev, 0);
4647 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4649 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4650 struct ixgbe_vfta *shadow_vfta =
4651 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4652 int i = 0, j = 0, vfta = 0, mask = 1;
4654 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4655 vfta = shadow_vfta->vfta[i];
4658 for (j = 0; j < 32; j++) {
4660 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4670 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4672 struct ixgbe_hw *hw =
4673 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4674 struct ixgbe_vfta *shadow_vfta =
4675 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4676 uint32_t vid_idx = 0;
4677 uint32_t vid_bit = 0;
4680 PMD_INIT_FUNC_TRACE();
4682 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4683 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4685 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4688 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4689 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4691 /* Save what we set and retore it after device reset */
4693 shadow_vfta->vfta[vid_idx] |= vid_bit;
4695 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4701 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4703 struct ixgbe_hw *hw =
4704 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707 PMD_INIT_FUNC_TRACE();
4709 if (queue >= hw->mac.max_rx_queues)
4712 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4714 ctrl |= IXGBE_RXDCTL_VME;
4716 ctrl &= ~IXGBE_RXDCTL_VME;
4717 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4719 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4723 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4725 struct ixgbe_hw *hw =
4726 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4730 /* VF function only support hw strip feature, others are not support */
4731 if (mask & ETH_VLAN_STRIP_MASK) {
4732 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4734 for (i = 0; i < hw->mac.max_rx_queues; i++)
4735 ixgbevf_vlan_strip_queue_set(dev, i, on);
4740 ixgbe_vt_check(struct ixgbe_hw *hw)
4744 /* if Virtualization Technology is enabled */
4745 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4746 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4747 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4755 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4757 uint32_t vector = 0;
4759 switch (hw->mac.mc_filter_type) {
4760 case 0: /* use bits [47:36] of the address */
4761 vector = ((uc_addr->addr_bytes[4] >> 4) |
4762 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4764 case 1: /* use bits [46:35] of the address */
4765 vector = ((uc_addr->addr_bytes[4] >> 3) |
4766 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4768 case 2: /* use bits [45:34] of the address */
4769 vector = ((uc_addr->addr_bytes[4] >> 2) |
4770 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4772 case 3: /* use bits [43:32] of the address */
4773 vector = ((uc_addr->addr_bytes[4]) |
4774 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4776 default: /* Invalid mc_filter_type */
4780 /* vector can only be 12-bits or boundary will be exceeded */
4786 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4794 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4795 const uint32_t ixgbe_uta_bit_shift = 5;
4796 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4797 const uint32_t bit1 = 0x1;
4799 struct ixgbe_hw *hw =
4800 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4801 struct ixgbe_uta_info *uta_info =
4802 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4804 /* The UTA table only exists on 82599 hardware and newer */
4805 if (hw->mac.type < ixgbe_mac_82599EB)
4808 vector = ixgbe_uta_vector(hw, mac_addr);
4809 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4810 uta_shift = vector & ixgbe_uta_bit_mask;
4812 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4816 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4818 uta_info->uta_in_use++;
4819 reg_val |= (bit1 << uta_shift);
4820 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4822 uta_info->uta_in_use--;
4823 reg_val &= ~(bit1 << uta_shift);
4824 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4827 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4829 if (uta_info->uta_in_use > 0)
4830 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4831 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4833 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4839 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4842 struct ixgbe_hw *hw =
4843 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4844 struct ixgbe_uta_info *uta_info =
4845 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4847 /* The UTA table only exists on 82599 hardware and newer */
4848 if (hw->mac.type < ixgbe_mac_82599EB)
4852 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4853 uta_info->uta_shadow[i] = ~0;
4854 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4857 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4858 uta_info->uta_shadow[i] = 0;
4859 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4867 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4869 uint32_t new_val = orig_val;
4871 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4872 new_val |= IXGBE_VMOLR_AUPE;
4873 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4874 new_val |= IXGBE_VMOLR_ROMPE;
4875 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4876 new_val |= IXGBE_VMOLR_ROPE;
4877 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4878 new_val |= IXGBE_VMOLR_BAM;
4879 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4880 new_val |= IXGBE_VMOLR_MPE;
4887 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4889 struct ixgbe_hw *hw;
4890 struct ixgbe_mac_info *mac;
4891 struct rte_eth_dev *dev;
4892 struct rte_eth_dev_info dev_info;
4894 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4896 dev = &rte_eth_devices[port];
4897 rte_eth_dev_info_get(port, &dev_info);
4899 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4902 if (vf >= dev_info.max_vfs)
4908 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4911 mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4917 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4919 struct ixgbe_hw *hw;
4920 struct ixgbe_mac_info *mac;
4921 struct rte_eth_dev *dev;
4922 struct rte_eth_dev_info dev_info;
4924 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4926 dev = &rte_eth_devices[port];
4927 rte_eth_dev_info_get(port, &dev_info);
4929 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4932 if (vf >= dev_info.max_vfs)
4938 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4940 mac->ops.set_mac_anti_spoofing(hw, on, vf);
4946 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4948 struct ixgbe_hw *hw;
4950 struct rte_eth_dev *dev;
4951 struct rte_eth_dev_info dev_info;
4953 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4955 dev = &rte_eth_devices[port];
4956 rte_eth_dev_info_get(port, &dev_info);
4958 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4961 if (vf >= dev_info.max_vfs)
4964 if (vlan_id > ETHER_MAX_VLAN_ID)
4967 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4968 ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4971 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4976 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4982 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4984 struct ixgbe_hw *hw;
4986 struct rte_eth_dev *dev;
4987 struct rte_eth_dev_info dev_info;
4989 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4991 dev = &rte_eth_devices[port];
4992 rte_eth_dev_info_get(port, &dev_info);
4994 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5000 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5001 ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5002 /* enable or disable VMDQ loopback */
5004 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5006 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5008 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5014 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5016 struct ixgbe_hw *hw;
5019 int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5020 struct rte_eth_dev *dev;
5021 struct rte_eth_dev_info dev_info;
5023 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5025 dev = &rte_eth_devices[port];
5026 rte_eth_dev_info_get(port, &dev_info);
5028 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5034 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035 for (i = 0; i <= num_queues; i++) {
5036 reg_value = IXGBE_QDE_WRITE |
5037 (i << IXGBE_QDE_IDX_SHIFT) |
5038 (on & IXGBE_QDE_ENABLE);
5039 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5046 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5048 struct ixgbe_hw *hw;
5050 struct rte_eth_dev *dev;
5051 struct rte_eth_dev_info dev_info;
5053 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5055 dev = &rte_eth_devices[port];
5056 rte_eth_dev_info_get(port, &dev_info);
5058 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5061 /* only support VF's 0 to 63 */
5062 if ((vf >= dev_info.max_vfs) || (vf > 63))
5068 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5069 reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5071 reg_value |= IXGBE_SRRCTL_DROP_EN;
5073 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5075 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5081 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5083 struct rte_eth_dev *dev;
5084 struct rte_eth_dev_info dev_info;
5085 uint16_t queues_per_pool;
5088 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5090 dev = &rte_eth_devices[port];
5091 rte_eth_dev_info_get(port, &dev_info);
5093 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5096 if (vf >= dev_info.max_vfs)
5102 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5104 /* The PF has 128 queue pairs and in SRIOV configuration
5105 * those queues will be assigned to VF's, so RXDCTL
5106 * registers will be dealing with queues which will be
5108 * Let's say we have SRIOV configured with 31 VF's then the
5109 * first 124 queues 0-123 will be allocated to VF's and only
5110 * the last 4 queues 123-127 will be assigned to the PF.
5113 queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5115 for (q = 0; q < queues_per_pool; q++)
5116 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5117 q + vf * queues_per_pool, on);
5122 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5125 struct rte_eth_dev *dev;
5126 struct rte_eth_dev_info dev_info;
5127 struct ixgbe_hw *hw;
5130 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5132 dev = &rte_eth_devices[port];
5133 rte_eth_dev_info_get(port, &dev_info);
5135 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5138 if (vf >= dev_info.max_vfs)
5144 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5147 if (hw->mac.type == ixgbe_mac_82598EB) {
5148 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5149 " on 82599 hardware and newer");
5152 if (ixgbe_vt_check(hw) < 0)
5155 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5162 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5168 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5170 struct rte_eth_dev *dev;
5171 struct rte_eth_dev_info dev_info;
5174 const uint8_t bit1 = 0x1;
5175 struct ixgbe_hw *hw;
5177 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5179 dev = &rte_eth_devices[port];
5180 rte_eth_dev_info_get(port, &dev_info);
5182 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5185 if (vf >= dev_info.max_vfs)
5191 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5193 if (ixgbe_vt_check(hw) < 0)
5196 /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5198 addr = IXGBE_VFRE(1);
5199 val = bit1 << (vf - 32);
5201 addr = IXGBE_VFRE(0);
5205 reg = IXGBE_READ_REG(hw, addr);
5212 IXGBE_WRITE_REG(hw, addr, reg);
5218 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5220 struct rte_eth_dev *dev;
5221 struct rte_eth_dev_info dev_info;
5224 const uint8_t bit1 = 0x1;
5226 struct ixgbe_hw *hw;
5228 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5230 dev = &rte_eth_devices[port];
5231 rte_eth_dev_info_get(port, &dev_info);
5233 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5236 if (vf >= dev_info.max_vfs)
5242 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5243 if (ixgbe_vt_check(hw) < 0)
5246 /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5248 addr = IXGBE_VFTE(1);
5249 val = bit1 << (vf - 32);
5251 addr = IXGBE_VFTE(0);
5255 reg = IXGBE_READ_REG(hw, addr);
5262 IXGBE_WRITE_REG(hw, addr, reg);
5268 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5269 uint64_t vf_mask, uint8_t vlan_on)
5271 struct rte_eth_dev *dev;
5272 struct rte_eth_dev_info dev_info;
5275 struct ixgbe_hw *hw;
5277 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5279 dev = &rte_eth_devices[port];
5280 rte_eth_dev_info_get(port, &dev_info);
5282 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5285 if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5288 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5289 if (ixgbe_vt_check(hw) < 0)
5292 for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5293 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5294 ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5304 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5305 uint16_t tx_rate, uint64_t q_msk)
5307 struct rte_eth_dev *dev;
5308 struct rte_eth_dev_info dev_info;
5309 struct ixgbe_hw *hw;
5310 struct ixgbe_vf_info *vfinfo;
5311 struct rte_eth_link link;
5312 uint8_t nb_q_per_pool;
5313 uint32_t queue_stride;
5314 uint32_t queue_idx, idx = 0, vf_idx;
5316 uint16_t total_rate = 0;
5317 struct rte_pci_device *pci_dev;
5319 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5321 dev = &rte_eth_devices[port];
5322 rte_eth_dev_info_get(port, &dev_info);
5323 rte_eth_link_get_nowait(port, &link);
5325 if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5328 if (vf >= dev_info.max_vfs)
5331 if (tx_rate > link.link_speed)
5337 pci_dev = IXGBE_DEV_TO_PCI(dev);
5338 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5339 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5340 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5341 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5342 queue_idx = vf * queue_stride;
5343 queue_end = queue_idx + nb_q_per_pool - 1;
5344 if (queue_end >= hw->mac.max_tx_queues)
5348 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5351 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5353 total_rate += vfinfo[vf_idx].tx_rate[idx];
5359 /* Store tx_rate for this vf. */
5360 for (idx = 0; idx < nb_q_per_pool; idx++) {
5361 if (((uint64_t)0x1 << idx) & q_msk) {
5362 if (vfinfo[vf].tx_rate[idx] != tx_rate)
5363 vfinfo[vf].tx_rate[idx] = tx_rate;
5364 total_rate += tx_rate;
5368 if (total_rate > dev->data->dev_link.link_speed) {
5369 /* Reset stored TX rate of the VF if it causes exceed
5372 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5376 /* Set RTTBCNRC of each queue/pool for vf X */
5377 for (; queue_idx <= queue_end; queue_idx++) {
5379 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5386 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5387 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5388 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5389 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5390 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5391 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5392 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5395 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5396 struct rte_eth_mirror_conf *mirror_conf,
5397 uint8_t rule_id, uint8_t on)
5399 uint32_t mr_ctl, vlvf;
5400 uint32_t mp_lsb = 0;
5401 uint32_t mv_msb = 0;
5402 uint32_t mv_lsb = 0;
5403 uint32_t mp_msb = 0;
5406 uint64_t vlan_mask = 0;
5408 const uint8_t pool_mask_offset = 32;
5409 const uint8_t vlan_mask_offset = 32;
5410 const uint8_t dst_pool_offset = 8;
5411 const uint8_t rule_mr_offset = 4;
5412 const uint8_t mirror_rule_mask = 0x0F;
5414 struct ixgbe_mirror_info *mr_info =
5415 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5416 struct ixgbe_hw *hw =
5417 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5418 uint8_t mirror_type = 0;
5420 if (ixgbe_vt_check(hw) < 0)
5423 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5426 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5427 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5428 mirror_conf->rule_type);
5432 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5433 mirror_type |= IXGBE_MRCTL_VLME;
5434 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5435 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5436 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5437 /* search vlan id related pool vlan filter index */
5438 reg_index = ixgbe_find_vlvf_slot(hw,
5439 mirror_conf->vlan.vlan_id[i],
5443 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5444 if ((vlvf & IXGBE_VLVF_VIEN) &&
5445 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5446 mirror_conf->vlan.vlan_id[i]))
5447 vlan_mask |= (1ULL << reg_index);
5454 mv_lsb = vlan_mask & 0xFFFFFFFF;
5455 mv_msb = vlan_mask >> vlan_mask_offset;
5457 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5458 mirror_conf->vlan.vlan_mask;
5459 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5460 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5461 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5462 mirror_conf->vlan.vlan_id[i];
5467 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5468 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5469 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5474 * if enable pool mirror, write related pool mask register,if disable
5475 * pool mirror, clear PFMRVM register
5477 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5478 mirror_type |= IXGBE_MRCTL_VPME;
5480 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5481 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5482 mr_info->mr_conf[rule_id].pool_mask =
5483 mirror_conf->pool_mask;
5488 mr_info->mr_conf[rule_id].pool_mask = 0;
5491 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5492 mirror_type |= IXGBE_MRCTL_UPME;
5493 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5494 mirror_type |= IXGBE_MRCTL_DPME;
5496 /* read mirror control register and recalculate it */
5497 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5500 mr_ctl |= mirror_type;
5501 mr_ctl &= mirror_rule_mask;
5502 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5504 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5506 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5507 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5509 /* write mirrror control register */
5510 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5512 /* write pool mirrror control register */
5513 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5514 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5515 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5518 /* write VLAN mirrror control register */
5519 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5520 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5521 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5529 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5532 uint32_t lsb_val = 0;
5533 uint32_t msb_val = 0;
5534 const uint8_t rule_mr_offset = 4;
5536 struct ixgbe_hw *hw =
5537 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5538 struct ixgbe_mirror_info *mr_info =
5539 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5541 if (ixgbe_vt_check(hw) < 0)
5544 memset(&mr_info->mr_conf[rule_id], 0,
5545 sizeof(struct rte_eth_mirror_conf));
5547 /* clear PFVMCTL register */
5548 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5550 /* clear pool mask register */
5551 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5552 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5554 /* clear vlan mask register */
5555 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5556 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5562 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5564 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5565 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5567 struct ixgbe_hw *hw =
5568 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5571 mask |= (1 << IXGBE_MISC_VEC_ID);
5572 RTE_SET_USED(queue_id);
5573 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5575 rte_intr_enable(intr_handle);
5581 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5584 struct ixgbe_hw *hw =
5585 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5587 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5588 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5589 RTE_SET_USED(queue_id);
5590 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5596 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5598 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5599 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5601 struct ixgbe_hw *hw =
5602 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603 struct ixgbe_interrupt *intr =
5604 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5606 if (queue_id < 16) {
5607 ixgbe_disable_intr(hw);
5608 intr->mask |= (1 << queue_id);
5609 ixgbe_enable_intr(dev);
5610 } else if (queue_id < 32) {
5611 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5612 mask &= (1 << queue_id);
5613 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5614 } else if (queue_id < 64) {
5615 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5616 mask &= (1 << (queue_id - 32));
5617 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5619 rte_intr_enable(intr_handle);
5625 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5628 struct ixgbe_hw *hw =
5629 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5630 struct ixgbe_interrupt *intr =
5631 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5633 if (queue_id < 16) {
5634 ixgbe_disable_intr(hw);
5635 intr->mask &= ~(1 << queue_id);
5636 ixgbe_enable_intr(dev);
5637 } else if (queue_id < 32) {
5638 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5639 mask &= ~(1 << queue_id);
5640 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5641 } else if (queue_id < 64) {
5642 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5643 mask &= ~(1 << (queue_id - 32));
5644 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5651 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5652 uint8_t queue, uint8_t msix_vector)
5656 if (direction == -1) {
5658 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5659 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5662 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5664 /* rx or tx cause */
5665 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5666 idx = ((16 * (queue & 1)) + (8 * direction));
5667 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5668 tmp &= ~(0xFF << idx);
5669 tmp |= (msix_vector << idx);
5670 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5675 * set the IVAR registers, mapping interrupt causes to vectors
5677 * pointer to ixgbe_hw struct
5679 * 0 for Rx, 1 for Tx, -1 for other causes
5681 * queue to map the corresponding interrupt to
5683 * the vector to map to the corresponding queue
5686 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5687 uint8_t queue, uint8_t msix_vector)
5691 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5692 if (hw->mac.type == ixgbe_mac_82598EB) {
5693 if (direction == -1)
5695 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5696 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5697 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5698 tmp |= (msix_vector << (8 * (queue & 0x3)));
5699 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5700 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5701 (hw->mac.type == ixgbe_mac_X540)) {
5702 if (direction == -1) {
5704 idx = ((queue & 1) * 8);
5705 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5706 tmp &= ~(0xFF << idx);
5707 tmp |= (msix_vector << idx);
5708 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5710 /* rx or tx causes */
5711 idx = ((16 * (queue & 1)) + (8 * direction));
5712 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5713 tmp &= ~(0xFF << idx);
5714 tmp |= (msix_vector << idx);
5715 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5721 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5723 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5724 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5725 struct ixgbe_hw *hw =
5726 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5728 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5730 /* Configure VF other cause ivar */
5731 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5733 /* won't configure msix register if no mapping is done
5734 * between intr vector and event fd.
5736 if (!rte_intr_dp_is_en(intr_handle))
5739 /* Configure all RX queues of VF */
5740 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5741 /* Force all queue use vector 0,
5742 * as IXGBE_VF_MAXMSIVECOTR = 1
5744 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5745 intr_handle->intr_vec[q_idx] = vector_idx;
5750 * Sets up the hardware to properly generate MSI-X interrupts
5752 * board private structure
5755 ixgbe_configure_msix(struct rte_eth_dev *dev)
5757 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5758 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5759 struct ixgbe_hw *hw =
5760 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5761 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5762 uint32_t vec = IXGBE_MISC_VEC_ID;
5766 /* won't configure msix register if no mapping is done
5767 * between intr vector and event fd
5769 if (!rte_intr_dp_is_en(intr_handle))
5772 if (rte_intr_allow_others(intr_handle))
5773 vec = base = IXGBE_RX_VEC_START;
5775 /* setup GPIE for MSI-x mode */
5776 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5777 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5778 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5779 /* auto clearing and auto setting corresponding bits in EIMS
5780 * when MSI-X interrupt is triggered
5782 if (hw->mac.type == ixgbe_mac_82598EB) {
5783 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5785 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5786 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5788 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5790 /* Populate the IVAR table and set the ITR values to the
5791 * corresponding register.
5793 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5795 /* by default, 1:1 mapping */
5796 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5797 intr_handle->intr_vec[queue_id] = vec;
5798 if (vec < base + intr_handle->nb_efd - 1)
5802 switch (hw->mac.type) {
5803 case ixgbe_mac_82598EB:
5804 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5807 case ixgbe_mac_82599EB:
5808 case ixgbe_mac_X540:
5809 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5814 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5815 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5817 /* set up to autoclear timer, and the vectors */
5818 mask = IXGBE_EIMS_ENABLE_MASK;
5819 mask &= ~(IXGBE_EIMS_OTHER |
5820 IXGBE_EIMS_MAILBOX |
5823 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5826 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5827 uint16_t queue_idx, uint16_t tx_rate)
5829 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5830 uint32_t rf_dec, rf_int;
5832 uint16_t link_speed = dev->data->dev_link.link_speed;
5834 if (queue_idx >= hw->mac.max_tx_queues)
5838 /* Calculate the rate factor values to set */
5839 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5840 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5841 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5843 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5844 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5845 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5846 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5852 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5853 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5856 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5857 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5858 IXGBE_MAX_JUMBO_FRAME_SIZE))
5859 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5860 IXGBE_MMW_SIZE_JUMBO_FRAME);
5862 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5863 IXGBE_MMW_SIZE_DEFAULT);
5865 /* Set RTTBCNRC of queue X */
5866 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5867 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5868 IXGBE_WRITE_FLUSH(hw);
5874 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5875 __attribute__((unused)) uint32_t index,
5876 __attribute__((unused)) uint32_t pool)
5878 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5882 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5883 * operation. Trap this case to avoid exhausting the [very limited]
5884 * set of PF resources used to store VF MAC addresses.
5886 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5888 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5891 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5895 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5898 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5899 struct ether_addr *mac_addr;
5904 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5905 * not support the deletion of a given MAC address.
5906 * Instead, it imposes to delete all MAC addresses, then to add again
5907 * all MAC addresses with the exception of the one to be deleted.
5909 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5912 * Add again all MAC addresses, with the exception of the deleted one
5913 * and of the permanent MAC address.
5915 for (i = 0, mac_addr = dev->data->mac_addrs;
5916 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5917 /* Skip the deleted MAC address */
5920 /* Skip NULL MAC addresses */
5921 if (is_zero_ether_addr(mac_addr))
5923 /* Skip the permanent MAC address */
5924 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5926 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5929 "Adding again MAC address "
5930 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5932 mac_addr->addr_bytes[0],
5933 mac_addr->addr_bytes[1],
5934 mac_addr->addr_bytes[2],
5935 mac_addr->addr_bytes[3],
5936 mac_addr->addr_bytes[4],
5937 mac_addr->addr_bytes[5],
5943 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5945 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5947 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5950 #define MAC_TYPE_FILTER_SUP(type) do {\
5951 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5952 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5953 (type) != ixgbe_mac_X550EM_a)\
5958 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5959 struct rte_eth_syn_filter *filter,
5962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5963 struct ixgbe_filter_info *filter_info =
5964 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5968 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5971 syn_info = filter_info->syn_info;
5974 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5976 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5977 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5979 if (filter->hig_pri)
5980 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5982 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5984 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5985 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5987 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5990 filter_info->syn_info = synqf;
5991 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5992 IXGBE_WRITE_FLUSH(hw);
5997 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5998 struct rte_eth_syn_filter *filter)
6000 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6001 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6003 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6004 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6005 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6012 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6013 enum rte_filter_op filter_op,
6016 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6019 MAC_TYPE_FILTER_SUP(hw->mac.type);
6021 if (filter_op == RTE_ETH_FILTER_NOP)
6025 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6030 switch (filter_op) {
6031 case RTE_ETH_FILTER_ADD:
6032 ret = ixgbe_syn_filter_set(dev,
6033 (struct rte_eth_syn_filter *)arg,
6036 case RTE_ETH_FILTER_DELETE:
6037 ret = ixgbe_syn_filter_set(dev,
6038 (struct rte_eth_syn_filter *)arg,
6041 case RTE_ETH_FILTER_GET:
6042 ret = ixgbe_syn_filter_get(dev,
6043 (struct rte_eth_syn_filter *)arg);
6046 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6055 static inline enum ixgbe_5tuple_protocol
6056 convert_protocol_type(uint8_t protocol_value)
6058 if (protocol_value == IPPROTO_TCP)
6059 return IXGBE_FILTER_PROTOCOL_TCP;
6060 else if (protocol_value == IPPROTO_UDP)
6061 return IXGBE_FILTER_PROTOCOL_UDP;
6062 else if (protocol_value == IPPROTO_SCTP)
6063 return IXGBE_FILTER_PROTOCOL_SCTP;
6065 return IXGBE_FILTER_PROTOCOL_NONE;
6068 /* inject a 5-tuple filter to HW */
6070 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6071 struct ixgbe_5tuple_filter *filter)
6073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6075 uint32_t ftqf, sdpqf;
6076 uint32_t l34timir = 0;
6077 uint8_t mask = 0xff;
6081 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6082 IXGBE_SDPQF_DSTPORT_SHIFT);
6083 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6085 ftqf = (uint32_t)(filter->filter_info.proto &
6086 IXGBE_FTQF_PROTOCOL_MASK);
6087 ftqf |= (uint32_t)((filter->filter_info.priority &
6088 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6089 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6090 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6091 if (filter->filter_info.dst_ip_mask == 0)
6092 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6093 if (filter->filter_info.src_port_mask == 0)
6094 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6095 if (filter->filter_info.dst_port_mask == 0)
6096 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6097 if (filter->filter_info.proto_mask == 0)
6098 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6099 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6100 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6101 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6103 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6104 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6105 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6106 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6108 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6109 l34timir |= (uint32_t)(filter->queue <<
6110 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6111 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6115 * add a 5tuple filter
6118 * dev: Pointer to struct rte_eth_dev.
6119 * index: the index the filter allocates.
6120 * filter: ponter to the filter that will be added.
6121 * rx_queue: the queue id the filter assigned to.
6124 * - On success, zero.
6125 * - On failure, a negative value.
6128 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6129 struct ixgbe_5tuple_filter *filter)
6131 struct ixgbe_filter_info *filter_info =
6132 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6136 * look for an unused 5tuple filter index,
6137 * and insert the filter to list.
6139 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6140 idx = i / (sizeof(uint32_t) * NBBY);
6141 shift = i % (sizeof(uint32_t) * NBBY);
6142 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6143 filter_info->fivetuple_mask[idx] |= 1 << shift;
6145 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6151 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6152 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6156 ixgbe_inject_5tuple_filter(dev, filter);
6162 * remove a 5tuple filter
6165 * dev: Pointer to struct rte_eth_dev.
6166 * filter: the pointer of the filter will be removed.
6169 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6170 struct ixgbe_5tuple_filter *filter)
6172 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6173 struct ixgbe_filter_info *filter_info =
6174 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6175 uint16_t index = filter->index;
6177 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6178 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6179 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6182 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6183 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6184 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6185 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6186 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6190 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6192 struct ixgbe_hw *hw;
6193 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6195 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6197 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6200 /* refuse mtu that requires the support of scattered packets when this
6201 * feature has not been enabled before.
6203 if (!dev->data->scattered_rx &&
6204 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6205 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6209 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6210 * request of the version 2.0 of the mailbox API.
6211 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6212 * of the mailbox API.
6213 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6214 * prior to 3.11.33 which contains the following change:
6215 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6217 ixgbevf_rlpml_set_vf(hw, max_frame);
6219 /* update max frame size */
6220 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6224 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
6225 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6229 static inline struct ixgbe_5tuple_filter *
6230 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6231 struct ixgbe_5tuple_filter_info *key)
6233 struct ixgbe_5tuple_filter *it;
6235 TAILQ_FOREACH(it, filter_list, entries) {
6236 if (memcmp(key, &it->filter_info,
6237 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6244 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6246 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6247 struct ixgbe_5tuple_filter_info *filter_info)
6249 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6250 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6251 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6254 switch (filter->dst_ip_mask) {
6256 filter_info->dst_ip_mask = 0;
6257 filter_info->dst_ip = filter->dst_ip;
6260 filter_info->dst_ip_mask = 1;
6263 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6267 switch (filter->src_ip_mask) {
6269 filter_info->src_ip_mask = 0;
6270 filter_info->src_ip = filter->src_ip;
6273 filter_info->src_ip_mask = 1;
6276 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6280 switch (filter->dst_port_mask) {
6282 filter_info->dst_port_mask = 0;
6283 filter_info->dst_port = filter->dst_port;
6286 filter_info->dst_port_mask = 1;
6289 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6293 switch (filter->src_port_mask) {
6295 filter_info->src_port_mask = 0;
6296 filter_info->src_port = filter->src_port;
6299 filter_info->src_port_mask = 1;
6302 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6306 switch (filter->proto_mask) {
6308 filter_info->proto_mask = 0;
6309 filter_info->proto =
6310 convert_protocol_type(filter->proto);
6313 filter_info->proto_mask = 1;
6316 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6320 filter_info->priority = (uint8_t)filter->priority;
6325 * add or delete a ntuple filter
6328 * dev: Pointer to struct rte_eth_dev.
6329 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6330 * add: if true, add filter, if false, remove filter
6333 * - On success, zero.
6334 * - On failure, a negative value.
6337 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6338 struct rte_eth_ntuple_filter *ntuple_filter,
6341 struct ixgbe_filter_info *filter_info =
6342 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6343 struct ixgbe_5tuple_filter_info filter_5tuple;
6344 struct ixgbe_5tuple_filter *filter;
6347 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6348 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6352 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6353 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6357 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6359 if (filter != NULL && add) {
6360 PMD_DRV_LOG(ERR, "filter exists.");
6363 if (filter == NULL && !add) {
6364 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6369 filter = rte_zmalloc("ixgbe_5tuple_filter",
6370 sizeof(struct ixgbe_5tuple_filter), 0);
6373 (void)rte_memcpy(&filter->filter_info,
6375 sizeof(struct ixgbe_5tuple_filter_info));
6376 filter->queue = ntuple_filter->queue;
6377 ret = ixgbe_add_5tuple_filter(dev, filter);
6383 ixgbe_remove_5tuple_filter(dev, filter);
6389 * get a ntuple filter
6392 * dev: Pointer to struct rte_eth_dev.
6393 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6396 * - On success, zero.
6397 * - On failure, a negative value.
6400 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6401 struct rte_eth_ntuple_filter *ntuple_filter)
6403 struct ixgbe_filter_info *filter_info =
6404 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6405 struct ixgbe_5tuple_filter_info filter_5tuple;
6406 struct ixgbe_5tuple_filter *filter;
6409 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6410 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6414 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6415 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6419 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6421 if (filter == NULL) {
6422 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6425 ntuple_filter->queue = filter->queue;
6430 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6431 * @dev: pointer to rte_eth_dev structure
6432 * @filter_op:operation will be taken.
6433 * @arg: a pointer to specific structure corresponding to the filter_op
6436 * - On success, zero.
6437 * - On failure, a negative value.
6440 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6441 enum rte_filter_op filter_op,
6444 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6447 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6449 if (filter_op == RTE_ETH_FILTER_NOP)
6453 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6458 switch (filter_op) {
6459 case RTE_ETH_FILTER_ADD:
6460 ret = ixgbe_add_del_ntuple_filter(dev,
6461 (struct rte_eth_ntuple_filter *)arg,
6464 case RTE_ETH_FILTER_DELETE:
6465 ret = ixgbe_add_del_ntuple_filter(dev,
6466 (struct rte_eth_ntuple_filter *)arg,
6469 case RTE_ETH_FILTER_GET:
6470 ret = ixgbe_get_ntuple_filter(dev,
6471 (struct rte_eth_ntuple_filter *)arg);
6474 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6482 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6483 struct rte_eth_ethertype_filter *filter,
6486 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6487 struct ixgbe_filter_info *filter_info =
6488 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6492 struct ixgbe_ethertype_filter ethertype_filter;
6494 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6497 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6498 filter->ether_type == ETHER_TYPE_IPv6) {
6499 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6500 " ethertype filter.", filter->ether_type);
6504 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6505 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6508 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6509 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6513 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6514 if (ret >= 0 && add) {
6515 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6516 filter->ether_type);
6519 if (ret < 0 && !add) {
6520 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6521 filter->ether_type);
6526 etqf = IXGBE_ETQF_FILTER_EN;
6527 etqf |= (uint32_t)filter->ether_type;
6528 etqs |= (uint32_t)((filter->queue <<
6529 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6530 IXGBE_ETQS_RX_QUEUE);
6531 etqs |= IXGBE_ETQS_QUEUE_EN;
6533 ethertype_filter.ethertype = filter->ether_type;
6534 ethertype_filter.etqf = etqf;
6535 ethertype_filter.etqs = etqs;
6536 ethertype_filter.conf = FALSE;
6537 ret = ixgbe_ethertype_filter_insert(filter_info,
6540 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6544 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6548 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6549 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6550 IXGBE_WRITE_FLUSH(hw);
6556 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6557 struct rte_eth_ethertype_filter *filter)
6559 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6560 struct ixgbe_filter_info *filter_info =
6561 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6562 uint32_t etqf, etqs;
6565 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6567 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6568 filter->ether_type);
6572 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6573 if (etqf & IXGBE_ETQF_FILTER_EN) {
6574 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6575 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6577 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6578 IXGBE_ETQS_RX_QUEUE_SHIFT;
6585 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6586 * @dev: pointer to rte_eth_dev structure
6587 * @filter_op:operation will be taken.
6588 * @arg: a pointer to specific structure corresponding to the filter_op
6591 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6592 enum rte_filter_op filter_op,
6595 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6598 MAC_TYPE_FILTER_SUP(hw->mac.type);
6600 if (filter_op == RTE_ETH_FILTER_NOP)
6604 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6609 switch (filter_op) {
6610 case RTE_ETH_FILTER_ADD:
6611 ret = ixgbe_add_del_ethertype_filter(dev,
6612 (struct rte_eth_ethertype_filter *)arg,
6615 case RTE_ETH_FILTER_DELETE:
6616 ret = ixgbe_add_del_ethertype_filter(dev,
6617 (struct rte_eth_ethertype_filter *)arg,
6620 case RTE_ETH_FILTER_GET:
6621 ret = ixgbe_get_ethertype_filter(dev,
6622 (struct rte_eth_ethertype_filter *)arg);
6625 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6633 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6634 enum rte_filter_type filter_type,
6635 enum rte_filter_op filter_op,
6640 switch (filter_type) {
6641 case RTE_ETH_FILTER_NTUPLE:
6642 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6644 case RTE_ETH_FILTER_ETHERTYPE:
6645 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6647 case RTE_ETH_FILTER_SYN:
6648 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6650 case RTE_ETH_FILTER_FDIR:
6651 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6653 case RTE_ETH_FILTER_L2_TUNNEL:
6654 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6656 case RTE_ETH_FILTER_GENERIC:
6657 if (filter_op != RTE_ETH_FILTER_GET)
6659 *(const void **)arg = &ixgbe_flow_ops;
6662 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6672 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6673 u8 **mc_addr_ptr, u32 *vmdq)
6678 mc_addr = *mc_addr_ptr;
6679 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6684 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6685 struct ether_addr *mc_addr_set,
6686 uint32_t nb_mc_addr)
6688 struct ixgbe_hw *hw;
6691 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6692 mc_addr_list = (u8 *)mc_addr_set;
6693 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6694 ixgbe_dev_addr_list_itr, TRUE);
6698 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6700 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6701 uint64_t systime_cycles;
6703 switch (hw->mac.type) {
6704 case ixgbe_mac_X550:
6705 case ixgbe_mac_X550EM_x:
6706 case ixgbe_mac_X550EM_a:
6707 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6708 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6709 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6713 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6714 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6718 return systime_cycles;
6722 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6724 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6725 uint64_t rx_tstamp_cycles;
6727 switch (hw->mac.type) {
6728 case ixgbe_mac_X550:
6729 case ixgbe_mac_X550EM_x:
6730 case ixgbe_mac_X550EM_a:
6731 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6732 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6733 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6737 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6738 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6739 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6743 return rx_tstamp_cycles;
6747 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6749 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6750 uint64_t tx_tstamp_cycles;
6752 switch (hw->mac.type) {
6753 case ixgbe_mac_X550:
6754 case ixgbe_mac_X550EM_x:
6755 case ixgbe_mac_X550EM_a:
6756 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6757 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6758 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6762 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6763 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6764 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6768 return tx_tstamp_cycles;
6772 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6774 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6775 struct ixgbe_adapter *adapter =
6776 (struct ixgbe_adapter *)dev->data->dev_private;
6777 struct rte_eth_link link;
6778 uint32_t incval = 0;
6781 /* Get current link speed. */
6782 memset(&link, 0, sizeof(link));
6783 ixgbe_dev_link_update(dev, 1);
6784 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6786 switch (link.link_speed) {
6787 case ETH_SPEED_NUM_100M:
6788 incval = IXGBE_INCVAL_100;
6789 shift = IXGBE_INCVAL_SHIFT_100;
6791 case ETH_SPEED_NUM_1G:
6792 incval = IXGBE_INCVAL_1GB;
6793 shift = IXGBE_INCVAL_SHIFT_1GB;
6795 case ETH_SPEED_NUM_10G:
6797 incval = IXGBE_INCVAL_10GB;
6798 shift = IXGBE_INCVAL_SHIFT_10GB;
6802 switch (hw->mac.type) {
6803 case ixgbe_mac_X550:
6804 case ixgbe_mac_X550EM_x:
6805 case ixgbe_mac_X550EM_a:
6806 /* Independent of link speed. */
6808 /* Cycles read will be interpreted as ns. */
6811 case ixgbe_mac_X540:
6812 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6814 case ixgbe_mac_82599EB:
6815 incval >>= IXGBE_INCVAL_SHIFT_82599;
6816 shift -= IXGBE_INCVAL_SHIFT_82599;
6817 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6818 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6821 /* Not supported. */
6825 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6826 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6827 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6829 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6830 adapter->systime_tc.cc_shift = shift;
6831 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6833 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6834 adapter->rx_tstamp_tc.cc_shift = shift;
6835 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6837 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6838 adapter->tx_tstamp_tc.cc_shift = shift;
6839 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6843 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6845 struct ixgbe_adapter *adapter =
6846 (struct ixgbe_adapter *)dev->data->dev_private;
6848 adapter->systime_tc.nsec += delta;
6849 adapter->rx_tstamp_tc.nsec += delta;
6850 adapter->tx_tstamp_tc.nsec += delta;
6856 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6859 struct ixgbe_adapter *adapter =
6860 (struct ixgbe_adapter *)dev->data->dev_private;
6862 ns = rte_timespec_to_ns(ts);
6863 /* Set the timecounters to a new value. */
6864 adapter->systime_tc.nsec = ns;
6865 adapter->rx_tstamp_tc.nsec = ns;
6866 adapter->tx_tstamp_tc.nsec = ns;
6872 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6874 uint64_t ns, systime_cycles;
6875 struct ixgbe_adapter *adapter =
6876 (struct ixgbe_adapter *)dev->data->dev_private;
6878 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6879 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6880 *ts = rte_ns_to_timespec(ns);
6886 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6888 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6892 /* Stop the timesync system time. */
6893 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6894 /* Reset the timesync system time value. */
6895 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6896 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6898 /* Enable system time for platforms where it isn't on by default. */
6899 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6900 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6901 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6903 ixgbe_start_timecounters(dev);
6905 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6906 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6908 IXGBE_ETQF_FILTER_EN |
6911 /* Enable timestamping of received PTP packets. */
6912 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6913 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6914 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6916 /* Enable timestamping of transmitted PTP packets. */
6917 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6918 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6919 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6921 IXGBE_WRITE_FLUSH(hw);
6927 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6929 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6932 /* Disable timestamping of transmitted PTP packets. */
6933 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6934 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6935 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6937 /* Disable timestamping of received PTP packets. */
6938 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6939 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6940 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6942 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6943 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6945 /* Stop incrementating the System Time registers. */
6946 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6952 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6953 struct timespec *timestamp,
6954 uint32_t flags __rte_unused)
6956 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6957 struct ixgbe_adapter *adapter =
6958 (struct ixgbe_adapter *)dev->data->dev_private;
6959 uint32_t tsync_rxctl;
6960 uint64_t rx_tstamp_cycles;
6963 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6964 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6967 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6968 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6969 *timestamp = rte_ns_to_timespec(ns);
6975 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6976 struct timespec *timestamp)
6978 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6979 struct ixgbe_adapter *adapter =
6980 (struct ixgbe_adapter *)dev->data->dev_private;
6981 uint32_t tsync_txctl;
6982 uint64_t tx_tstamp_cycles;
6985 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6986 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6989 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6990 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6991 *timestamp = rte_ns_to_timespec(ns);
6997 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6999 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7002 const struct reg_info *reg_group;
7003 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7004 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7006 while ((reg_group = reg_set[g_ind++]))
7007 count += ixgbe_regs_group_count(reg_group);
7013 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7017 const struct reg_info *reg_group;
7019 while ((reg_group = ixgbevf_regs[g_ind++]))
7020 count += ixgbe_regs_group_count(reg_group);
7026 ixgbe_get_regs(struct rte_eth_dev *dev,
7027 struct rte_dev_reg_info *regs)
7029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7030 uint32_t *data = regs->data;
7033 const struct reg_info *reg_group;
7034 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7035 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7038 regs->length = ixgbe_get_reg_length(dev);
7039 regs->width = sizeof(uint32_t);
7043 /* Support only full register dump */
7044 if ((regs->length == 0) ||
7045 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7046 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7048 while ((reg_group = reg_set[g_ind++]))
7049 count += ixgbe_read_regs_group(dev, &data[count],
7058 ixgbevf_get_regs(struct rte_eth_dev *dev,
7059 struct rte_dev_reg_info *regs)
7061 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7062 uint32_t *data = regs->data;
7065 const struct reg_info *reg_group;
7068 regs->length = ixgbevf_get_reg_length(dev);
7069 regs->width = sizeof(uint32_t);
7073 /* Support only full register dump */
7074 if ((regs->length == 0) ||
7075 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7076 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7078 while ((reg_group = ixgbevf_regs[g_ind++]))
7079 count += ixgbe_read_regs_group(dev, &data[count],
7088 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7090 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092 /* Return unit is byte count */
7093 return hw->eeprom.word_size * 2;
7097 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7098 struct rte_dev_eeprom_info *in_eeprom)
7100 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7101 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7102 uint16_t *data = in_eeprom->data;
7105 first = in_eeprom->offset >> 1;
7106 length = in_eeprom->length >> 1;
7107 if ((first > hw->eeprom.word_size) ||
7108 ((first + length) > hw->eeprom.word_size))
7111 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7113 return eeprom->ops.read_buffer(hw, first, length, data);
7117 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7118 struct rte_dev_eeprom_info *in_eeprom)
7120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7122 uint16_t *data = in_eeprom->data;
7125 first = in_eeprom->offset >> 1;
7126 length = in_eeprom->length >> 1;
7127 if ((first > hw->eeprom.word_size) ||
7128 ((first + length) > hw->eeprom.word_size))
7131 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7133 return eeprom->ops.write_buffer(hw, first, length, data);
7137 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7139 case ixgbe_mac_X550:
7140 case ixgbe_mac_X550EM_x:
7141 case ixgbe_mac_X550EM_a:
7142 return ETH_RSS_RETA_SIZE_512;
7143 case ixgbe_mac_X550_vf:
7144 case ixgbe_mac_X550EM_x_vf:
7145 case ixgbe_mac_X550EM_a_vf:
7146 return ETH_RSS_RETA_SIZE_64;
7148 return ETH_RSS_RETA_SIZE_128;
7153 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7155 case ixgbe_mac_X550:
7156 case ixgbe_mac_X550EM_x:
7157 case ixgbe_mac_X550EM_a:
7158 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7159 return IXGBE_RETA(reta_idx >> 2);
7161 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7162 case ixgbe_mac_X550_vf:
7163 case ixgbe_mac_X550EM_x_vf:
7164 case ixgbe_mac_X550EM_a_vf:
7165 return IXGBE_VFRETA(reta_idx >> 2);
7167 return IXGBE_RETA(reta_idx >> 2);
7172 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7174 case ixgbe_mac_X550_vf:
7175 case ixgbe_mac_X550EM_x_vf:
7176 case ixgbe_mac_X550EM_a_vf:
7177 return IXGBE_VFMRQC;
7184 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7186 case ixgbe_mac_X550_vf:
7187 case ixgbe_mac_X550EM_x_vf:
7188 case ixgbe_mac_X550EM_a_vf:
7189 return IXGBE_VFRSSRK(i);
7191 return IXGBE_RSSRK(i);
7196 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7198 case ixgbe_mac_82599_vf:
7199 case ixgbe_mac_X540_vf:
7207 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7208 struct rte_eth_dcb_info *dcb_info)
7210 struct ixgbe_dcb_config *dcb_config =
7211 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7212 struct ixgbe_dcb_tc_config *tc;
7215 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7216 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7218 dcb_info->nb_tcs = 1;
7220 if (dcb_config->vt_mode) { /* vt is enabled*/
7221 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7222 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7223 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7224 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7225 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7226 for (j = 0; j < dcb_info->nb_tcs; j++) {
7227 dcb_info->tc_queue.tc_rxq[i][j].base =
7228 i * dcb_info->nb_tcs + j;
7229 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7230 dcb_info->tc_queue.tc_txq[i][j].base =
7231 i * dcb_info->nb_tcs + j;
7232 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7235 } else { /* vt is disabled*/
7236 struct rte_eth_dcb_rx_conf *rx_conf =
7237 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7238 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7239 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7240 if (dcb_info->nb_tcs == ETH_4_TCS) {
7241 for (i = 0; i < dcb_info->nb_tcs; i++) {
7242 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7243 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7245 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7246 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7247 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7248 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7249 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7250 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7251 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7252 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7253 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7254 for (i = 0; i < dcb_info->nb_tcs; i++) {
7255 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7256 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7258 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7259 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7260 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7261 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7262 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7263 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7264 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7265 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7266 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7267 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7268 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7269 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7270 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7271 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7272 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7273 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7276 for (i = 0; i < dcb_info->nb_tcs; i++) {
7277 tc = &dcb_config->tc_config[i];
7278 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7283 /* Update e-tag ether type */
7285 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7286 uint16_t ether_type)
7288 uint32_t etag_etype;
7290 if (hw->mac.type != ixgbe_mac_X550 &&
7291 hw->mac.type != ixgbe_mac_X550EM_x &&
7292 hw->mac.type != ixgbe_mac_X550EM_a) {
7296 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7297 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7298 etag_etype |= ether_type;
7299 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7300 IXGBE_WRITE_FLUSH(hw);
7305 /* Config l2 tunnel ether type */
7307 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7308 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7311 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7312 struct ixgbe_l2_tn_info *l2_tn_info =
7313 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7315 if (l2_tunnel == NULL)
7318 switch (l2_tunnel->l2_tunnel_type) {
7319 case RTE_L2_TUNNEL_TYPE_E_TAG:
7320 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7321 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7324 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7332 /* Enable e-tag tunnel */
7334 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7336 uint32_t etag_etype;
7338 if (hw->mac.type != ixgbe_mac_X550 &&
7339 hw->mac.type != ixgbe_mac_X550EM_x &&
7340 hw->mac.type != ixgbe_mac_X550EM_a) {
7344 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7345 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7346 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7347 IXGBE_WRITE_FLUSH(hw);
7352 /* Enable l2 tunnel */
7354 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7355 enum rte_eth_tunnel_type l2_tunnel_type)
7358 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7359 struct ixgbe_l2_tn_info *l2_tn_info =
7360 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7362 switch (l2_tunnel_type) {
7363 case RTE_L2_TUNNEL_TYPE_E_TAG:
7364 l2_tn_info->e_tag_en = TRUE;
7365 ret = ixgbe_e_tag_enable(hw);
7368 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7376 /* Disable e-tag tunnel */
7378 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7380 uint32_t etag_etype;
7382 if (hw->mac.type != ixgbe_mac_X550 &&
7383 hw->mac.type != ixgbe_mac_X550EM_x &&
7384 hw->mac.type != ixgbe_mac_X550EM_a) {
7388 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7389 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7390 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7391 IXGBE_WRITE_FLUSH(hw);
7396 /* Disable l2 tunnel */
7398 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7399 enum rte_eth_tunnel_type l2_tunnel_type)
7402 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7403 struct ixgbe_l2_tn_info *l2_tn_info =
7404 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7406 switch (l2_tunnel_type) {
7407 case RTE_L2_TUNNEL_TYPE_E_TAG:
7408 l2_tn_info->e_tag_en = FALSE;
7409 ret = ixgbe_e_tag_disable(hw);
7412 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7421 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7422 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7425 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7426 uint32_t i, rar_entries;
7427 uint32_t rar_low, rar_high;
7429 if (hw->mac.type != ixgbe_mac_X550 &&
7430 hw->mac.type != ixgbe_mac_X550EM_x &&
7431 hw->mac.type != ixgbe_mac_X550EM_a) {
7435 rar_entries = ixgbe_get_num_rx_addrs(hw);
7437 for (i = 1; i < rar_entries; i++) {
7438 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7439 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7440 if ((rar_high & IXGBE_RAH_AV) &&
7441 (rar_high & IXGBE_RAH_ADTYPE) &&
7442 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7443 l2_tunnel->tunnel_id)) {
7444 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7445 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7447 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7457 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7458 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7461 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7462 uint32_t i, rar_entries;
7463 uint32_t rar_low, rar_high;
7465 if (hw->mac.type != ixgbe_mac_X550 &&
7466 hw->mac.type != ixgbe_mac_X550EM_x &&
7467 hw->mac.type != ixgbe_mac_X550EM_a) {
7471 /* One entry for one tunnel. Try to remove potential existing entry. */
7472 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7474 rar_entries = ixgbe_get_num_rx_addrs(hw);
7476 for (i = 1; i < rar_entries; i++) {
7477 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7478 if (rar_high & IXGBE_RAH_AV) {
7481 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7482 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7483 rar_low = l2_tunnel->tunnel_id;
7485 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7486 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7492 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7493 " Please remove a rule before adding a new one.");
7497 static inline struct ixgbe_l2_tn_filter *
7498 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7499 struct ixgbe_l2_tn_key *key)
7503 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7507 return l2_tn_info->hash_map[ret];
7511 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7512 struct ixgbe_l2_tn_filter *l2_tn_filter)
7516 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7517 &l2_tn_filter->key);
7521 "Failed to insert L2 tunnel filter"
7522 " to hash table %d!",
7527 l2_tn_info->hash_map[ret] = l2_tn_filter;
7529 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7535 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7536 struct ixgbe_l2_tn_key *key)
7539 struct ixgbe_l2_tn_filter *l2_tn_filter;
7541 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7545 "No such L2 tunnel filter to delete %d!",
7550 l2_tn_filter = l2_tn_info->hash_map[ret];
7551 l2_tn_info->hash_map[ret] = NULL;
7553 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7554 rte_free(l2_tn_filter);
7559 /* Add l2 tunnel filter */
7561 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7562 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7566 struct ixgbe_l2_tn_info *l2_tn_info =
7567 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7568 struct ixgbe_l2_tn_key key;
7569 struct ixgbe_l2_tn_filter *node;
7572 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7573 key.tn_id = l2_tunnel->tunnel_id;
7575 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7579 "The L2 tunnel filter already exists!");
7583 node = rte_zmalloc("ixgbe_l2_tn",
7584 sizeof(struct ixgbe_l2_tn_filter),
7589 (void)rte_memcpy(&node->key,
7591 sizeof(struct ixgbe_l2_tn_key));
7592 node->pool = l2_tunnel->pool;
7593 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7600 switch (l2_tunnel->l2_tunnel_type) {
7601 case RTE_L2_TUNNEL_TYPE_E_TAG:
7602 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7605 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7610 if ((!restore) && (ret < 0))
7611 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7616 /* Delete l2 tunnel filter */
7618 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7619 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7622 struct ixgbe_l2_tn_info *l2_tn_info =
7623 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7624 struct ixgbe_l2_tn_key key;
7626 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7627 key.tn_id = l2_tunnel->tunnel_id;
7628 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7632 switch (l2_tunnel->l2_tunnel_type) {
7633 case RTE_L2_TUNNEL_TYPE_E_TAG:
7634 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7637 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7646 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7647 * @dev: pointer to rte_eth_dev structure
7648 * @filter_op:operation will be taken.
7649 * @arg: a pointer to specific structure corresponding to the filter_op
7652 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7653 enum rte_filter_op filter_op,
7658 if (filter_op == RTE_ETH_FILTER_NOP)
7662 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7667 switch (filter_op) {
7668 case RTE_ETH_FILTER_ADD:
7669 ret = ixgbe_dev_l2_tunnel_filter_add
7671 (struct rte_eth_l2_tunnel_conf *)arg,
7674 case RTE_ETH_FILTER_DELETE:
7675 ret = ixgbe_dev_l2_tunnel_filter_del
7677 (struct rte_eth_l2_tunnel_conf *)arg);
7680 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7688 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7692 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7694 if (hw->mac.type != ixgbe_mac_X550 &&
7695 hw->mac.type != ixgbe_mac_X550EM_x &&
7696 hw->mac.type != ixgbe_mac_X550EM_a) {
7700 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7701 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7703 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7704 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7709 /* Enable l2 tunnel forwarding */
7711 ixgbe_dev_l2_tunnel_forwarding_enable
7712 (struct rte_eth_dev *dev,
7713 enum rte_eth_tunnel_type l2_tunnel_type)
7715 struct ixgbe_l2_tn_info *l2_tn_info =
7716 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7719 switch (l2_tunnel_type) {
7720 case RTE_L2_TUNNEL_TYPE_E_TAG:
7721 l2_tn_info->e_tag_fwd_en = TRUE;
7722 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7725 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7733 /* Disable l2 tunnel forwarding */
7735 ixgbe_dev_l2_tunnel_forwarding_disable
7736 (struct rte_eth_dev *dev,
7737 enum rte_eth_tunnel_type l2_tunnel_type)
7739 struct ixgbe_l2_tn_info *l2_tn_info =
7740 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7743 switch (l2_tunnel_type) {
7744 case RTE_L2_TUNNEL_TYPE_E_TAG:
7745 l2_tn_info->e_tag_fwd_en = FALSE;
7746 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7749 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7758 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7759 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7762 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7764 uint32_t vmtir, vmvir;
7765 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7767 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7769 "VF id %u should be less than %u",
7775 if (hw->mac.type != ixgbe_mac_X550 &&
7776 hw->mac.type != ixgbe_mac_X550EM_x &&
7777 hw->mac.type != ixgbe_mac_X550EM_a) {
7782 vmtir = l2_tunnel->tunnel_id;
7786 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7788 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7789 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7791 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7792 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7797 /* Enable l2 tunnel tag insertion */
7799 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7800 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7804 switch (l2_tunnel->l2_tunnel_type) {
7805 case RTE_L2_TUNNEL_TYPE_E_TAG:
7806 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7809 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7817 /* Disable l2 tunnel tag insertion */
7819 ixgbe_dev_l2_tunnel_insertion_disable
7820 (struct rte_eth_dev *dev,
7821 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7825 switch (l2_tunnel->l2_tunnel_type) {
7826 case RTE_L2_TUNNEL_TYPE_E_TAG:
7827 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7830 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7839 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7844 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7846 if (hw->mac.type != ixgbe_mac_X550 &&
7847 hw->mac.type != ixgbe_mac_X550EM_x &&
7848 hw->mac.type != ixgbe_mac_X550EM_a) {
7852 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7854 qde |= IXGBE_QDE_STRIP_TAG;
7856 qde &= ~IXGBE_QDE_STRIP_TAG;
7857 qde &= ~IXGBE_QDE_READ;
7858 qde |= IXGBE_QDE_WRITE;
7859 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7864 /* Enable l2 tunnel tag stripping */
7866 ixgbe_dev_l2_tunnel_stripping_enable
7867 (struct rte_eth_dev *dev,
7868 enum rte_eth_tunnel_type l2_tunnel_type)
7872 switch (l2_tunnel_type) {
7873 case RTE_L2_TUNNEL_TYPE_E_TAG:
7874 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7877 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7885 /* Disable l2 tunnel tag stripping */
7887 ixgbe_dev_l2_tunnel_stripping_disable
7888 (struct rte_eth_dev *dev,
7889 enum rte_eth_tunnel_type l2_tunnel_type)
7893 switch (l2_tunnel_type) {
7894 case RTE_L2_TUNNEL_TYPE_E_TAG:
7895 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7898 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7906 /* Enable/disable l2 tunnel offload functions */
7908 ixgbe_dev_l2_tunnel_offload_set
7909 (struct rte_eth_dev *dev,
7910 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7916 if (l2_tunnel == NULL)
7920 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7922 ret = ixgbe_dev_l2_tunnel_enable(
7924 l2_tunnel->l2_tunnel_type);
7926 ret = ixgbe_dev_l2_tunnel_disable(
7928 l2_tunnel->l2_tunnel_type);
7931 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7933 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7937 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7942 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7944 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7946 l2_tunnel->l2_tunnel_type);
7948 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7950 l2_tunnel->l2_tunnel_type);
7953 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7955 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7957 l2_tunnel->l2_tunnel_type);
7959 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7961 l2_tunnel->l2_tunnel_type);
7968 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7971 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7972 IXGBE_WRITE_FLUSH(hw);
7977 /* There's only one register for VxLAN UDP port.
7978 * So, we cannot add several ports. Will update it.
7981 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7985 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7989 return ixgbe_update_vxlan_port(hw, port);
7992 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7993 * UDP port, it must have a value.
7994 * So, will reset it to the original value 0.
7997 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8002 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8004 if (cur_port != port) {
8005 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8009 return ixgbe_update_vxlan_port(hw, 0);
8012 /* Add UDP tunneling port */
8014 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8015 struct rte_eth_udp_tunnel *udp_tunnel)
8018 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8020 if (hw->mac.type != ixgbe_mac_X550 &&
8021 hw->mac.type != ixgbe_mac_X550EM_x &&
8022 hw->mac.type != ixgbe_mac_X550EM_a) {
8026 if (udp_tunnel == NULL)
8029 switch (udp_tunnel->prot_type) {
8030 case RTE_TUNNEL_TYPE_VXLAN:
8031 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8034 case RTE_TUNNEL_TYPE_GENEVE:
8035 case RTE_TUNNEL_TYPE_TEREDO:
8036 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8041 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8049 /* Remove UDP tunneling port */
8051 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8052 struct rte_eth_udp_tunnel *udp_tunnel)
8055 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8057 if (hw->mac.type != ixgbe_mac_X550 &&
8058 hw->mac.type != ixgbe_mac_X550EM_x &&
8059 hw->mac.type != ixgbe_mac_X550EM_a) {
8063 if (udp_tunnel == NULL)
8066 switch (udp_tunnel->prot_type) {
8067 case RTE_TUNNEL_TYPE_VXLAN:
8068 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8070 case RTE_TUNNEL_TYPE_GENEVE:
8071 case RTE_TUNNEL_TYPE_TEREDO:
8072 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8076 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8085 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8087 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8089 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8093 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8095 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8097 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8100 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8105 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8108 /* PF reset VF event */
8109 if (in_msg == IXGBE_PF_CONTROL_MSG)
8110 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8114 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8118 struct ixgbe_interrupt *intr =
8119 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8120 ixgbevf_intr_disable(hw);
8122 /* read-on-clear nic registers here */
8123 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8126 /* only one misc vector supported - mailbox */
8127 eicr &= IXGBE_VTEICR_MASK;
8128 if (eicr == IXGBE_MISC_VEC_ID)
8129 intr->flags |= IXGBE_FLAG_MAILBOX;
8135 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8138 struct ixgbe_interrupt *intr =
8139 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8141 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8142 ixgbevf_mbx_process(dev);
8143 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8146 ixgbevf_intr_enable(hw);
8152 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8155 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8157 ixgbevf_dev_interrupt_get_status(dev);
8158 ixgbevf_dev_interrupt_action(dev);
8162 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8163 * @hw: pointer to hardware structure
8165 * Stops the transmit data path and waits for the HW to internally empty
8166 * the Tx security block
8168 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8170 #define IXGBE_MAX_SECTX_POLL 40
8175 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8176 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8177 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8178 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8179 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8180 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8182 /* Use interrupt-safe sleep just in case */
8186 /* For informational purposes only */
8187 if (i >= IXGBE_MAX_SECTX_POLL)
8188 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8189 "path fully disabled. Continuing with init.\n");
8191 return IXGBE_SUCCESS;
8195 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8196 * @hw: pointer to hardware structure
8198 * Enables the transmit data path.
8200 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8204 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8205 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8206 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8207 IXGBE_WRITE_FLUSH(hw);
8209 return IXGBE_SUCCESS;
8213 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8215 struct ixgbe_hw *hw;
8216 struct rte_eth_dev *dev;
8219 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8221 dev = &rte_eth_devices[port];
8222 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8224 /* Stop the data paths */
8225 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8229 * As no ixgbe_disable_sec_rx_path equivalent is
8230 * implemented for tx in the base code, and we are
8231 * not allowed to modify the base code in DPDK, so
8232 * just call the hand-written one directly for now.
8233 * The hardware support has been checked by
8234 * ixgbe_disable_sec_rx_path().
8236 ixgbe_disable_sec_tx_path_generic(hw);
8238 /* Enable Ethernet CRC (required by MACsec offload) */
8239 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8240 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8241 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8243 /* Enable the TX and RX crypto engines */
8244 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8245 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8246 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8248 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8249 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8250 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8252 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8253 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8255 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8257 /* Enable SA lookup */
8258 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8259 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8260 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8261 IXGBE_LSECTXCTRL_AUTH;
8262 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8263 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8264 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8265 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8267 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8268 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8269 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8270 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8272 ctrl |= IXGBE_LSECRXCTRL_RP;
8274 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8275 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8277 /* Start the data paths */
8278 ixgbe_enable_sec_rx_path(hw);
8281 * As no ixgbe_enable_sec_rx_path equivalent is
8282 * implemented for tx in the base code, and we are
8283 * not allowed to modify the base code in DPDK, so
8284 * just call the hand-written one directly for now.
8286 ixgbe_enable_sec_tx_path_generic(hw);
8292 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8294 struct ixgbe_hw *hw;
8295 struct rte_eth_dev *dev;
8298 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8300 dev = &rte_eth_devices[port];
8301 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8303 /* Stop the data paths */
8304 if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8308 * As no ixgbe_disable_sec_rx_path equivalent is
8309 * implemented for tx in the base code, and we are
8310 * not allowed to modify the base code in DPDK, so
8311 * just call the hand-written one directly for now.
8312 * The hardware support has been checked by
8313 * ixgbe_disable_sec_rx_path().
8315 ixgbe_disable_sec_tx_path_generic(hw);
8317 /* Disable the TX and RX crypto engines */
8318 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8319 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8320 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8322 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8323 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8324 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8326 /* Disable SA lookup */
8327 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8328 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8329 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8330 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8332 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8333 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8334 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8335 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8337 /* Start the data paths */
8338 ixgbe_enable_sec_rx_path(hw);
8341 * As no ixgbe_enable_sec_rx_path equivalent is
8342 * implemented for tx in the base code, and we are
8343 * not allowed to modify the base code in DPDK, so
8344 * just call the hand-written one directly for now.
8346 ixgbe_enable_sec_tx_path_generic(hw);
8352 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8354 struct ixgbe_hw *hw;
8355 struct rte_eth_dev *dev;
8358 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8360 dev = &rte_eth_devices[port];
8361 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8363 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8364 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8366 ctrl = mac[4] | (mac[5] << 8);
8367 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8373 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8375 struct ixgbe_hw *hw;
8376 struct rte_eth_dev *dev;
8379 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8381 dev = &rte_eth_devices[port];
8382 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8384 ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8385 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8387 pi = rte_cpu_to_be_16(pi);
8388 ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8389 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8395 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8396 uint32_t pn, uint8_t *key)
8398 struct ixgbe_hw *hw;
8399 struct rte_eth_dev *dev;
8402 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8404 dev = &rte_eth_devices[port];
8405 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8407 if (idx != 0 && idx != 1)
8413 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8415 /* Set the PN and key */
8416 pn = rte_cpu_to_be_32(pn);
8418 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8420 for (i = 0; i < 4; i++) {
8421 ctrl = (key[i * 4 + 0] << 0) |
8422 (key[i * 4 + 1] << 8) |
8423 (key[i * 4 + 2] << 16) |
8424 (key[i * 4 + 3] << 24);
8425 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8428 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8430 for (i = 0; i < 4; i++) {
8431 ctrl = (key[i * 4 + 0] << 0) |
8432 (key[i * 4 + 1] << 8) |
8433 (key[i * 4 + 2] << 16) |
8434 (key[i * 4 + 3] << 24);
8435 IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8439 /* Set AN and select the SA */
8440 ctrl = (an << idx * 2) | (idx << 4);
8441 IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8447 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8448 uint32_t pn, uint8_t *key)
8450 struct ixgbe_hw *hw;
8451 struct rte_eth_dev *dev;
8454 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8456 dev = &rte_eth_devices[port];
8457 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8459 if (idx != 0 && idx != 1)
8466 pn = rte_cpu_to_be_32(pn);
8467 IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8470 for (i = 0; i < 4; i++) {
8471 ctrl = (key[i * 4 + 0] << 0) |
8472 (key[i * 4 + 1] << 8) |
8473 (key[i * 4 + 2] << 16) |
8474 (key[i * 4 + 3] << 24);
8475 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8478 /* Set the AN and validate the SA */
8479 ctrl = an | (1 << 2);
8480 IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8485 /* restore n-tuple filter */
8487 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8489 struct ixgbe_filter_info *filter_info =
8490 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8491 struct ixgbe_5tuple_filter *node;
8493 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8494 ixgbe_inject_5tuple_filter(dev, node);
8498 /* restore ethernet type filter */
8500 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8502 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8503 struct ixgbe_filter_info *filter_info =
8504 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8507 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8508 if (filter_info->ethertype_mask & (1 << i)) {
8509 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8510 filter_info->ethertype_filters[i].etqf);
8511 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8512 filter_info->ethertype_filters[i].etqs);
8513 IXGBE_WRITE_FLUSH(hw);
8518 /* restore SYN filter */
8520 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8522 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8523 struct ixgbe_filter_info *filter_info =
8524 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8527 synqf = filter_info->syn_info;
8529 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8530 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8531 IXGBE_WRITE_FLUSH(hw);
8535 /* restore L2 tunnel filter */
8537 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8539 struct ixgbe_l2_tn_info *l2_tn_info =
8540 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8541 struct ixgbe_l2_tn_filter *node;
8542 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8544 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8545 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8546 l2_tn_conf.tunnel_id = node->key.tn_id;
8547 l2_tn_conf.pool = node->pool;
8548 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8553 ixgbe_filter_restore(struct rte_eth_dev *dev)
8555 ixgbe_ntuple_filter_restore(dev);
8556 ixgbe_ethertype_filter_restore(dev);
8557 ixgbe_syn_filter_restore(dev);
8558 ixgbe_fdir_filter_restore(dev);
8559 ixgbe_l2_tn_filter_restore(dev);
8565 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8567 struct ixgbe_l2_tn_info *l2_tn_info =
8568 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8569 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8571 if (l2_tn_info->e_tag_en)
8572 (void)ixgbe_e_tag_enable(hw);
8574 if (l2_tn_info->e_tag_fwd_en)
8575 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8577 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8580 /* remove all the n-tuple filters */
8582 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8584 struct ixgbe_filter_info *filter_info =
8585 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8586 struct ixgbe_5tuple_filter *p_5tuple;
8588 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8589 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8592 /* remove all the ether type filters */
8594 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8596 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8597 struct ixgbe_filter_info *filter_info =
8598 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8601 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8602 if (filter_info->ethertype_mask & (1 << i) &&
8603 !filter_info->ethertype_filters[i].conf) {
8604 (void)ixgbe_ethertype_filter_remove(filter_info,
8606 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8607 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8608 IXGBE_WRITE_FLUSH(hw);
8613 /* remove the SYN filter */
8615 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8617 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8618 struct ixgbe_filter_info *filter_info =
8619 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8621 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8622 filter_info->syn_info = 0;
8624 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8625 IXGBE_WRITE_FLUSH(hw);
8629 /* remove all the L2 tunnel filters */
8630 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8632 struct ixgbe_l2_tn_info *l2_tn_info =
8633 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8634 struct ixgbe_l2_tn_filter *l2_tn_filter;
8635 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8638 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8639 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8640 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8641 l2_tn_conf.pool = l2_tn_filter->pool;
8642 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8650 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8651 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8652 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8653 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8654 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8655 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");