drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 int ixgbe_logtype_init;
 423 int ixgbe_logtype_driver;
 424
 425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
 426 int ixgbe_logtype_rx;
 427 #endif
 428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
 429 int ixgbe_logtype_tx;
 430 #endif
 431 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 432 int ixgbe_logtype_tx_free;
 433 #endif
 434
 435 /*
 436  * The set of PCI devices this driver supports
 437  */
 438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 487 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 489 #endif
 490         { .vendor_id = 0, /* sentinel */ },
 491 };
 492
 493 /*
 494  * The set of PCI devices this driver supports (for 82599 VF)
 495  */
 496 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 507         { .vendor_id = 0, /* sentinel */ },
 508 };
 509
 510 static const struct rte_eth_desc_lim rx_desc_lim = {
 511         .nb_max = IXGBE_MAX_RING_DESC,
 512         .nb_min = IXGBE_MIN_RING_DESC,
 513         .nb_align = IXGBE_RXD_ALIGN,
 514 };
 515
 516 static const struct rte_eth_desc_lim tx_desc_lim = {
 517         .nb_max = IXGBE_MAX_RING_DESC,
 518         .nb_min = IXGBE_MIN_RING_DESC,
 519         .nb_align = IXGBE_TXD_ALIGN,
 520         .nb_seg_max = IXGBE_TX_MAX_SEG,
 521         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 522 };
 523
 524 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 525         .dev_configure        = ixgbe_dev_configure,
 526         .dev_start            = ixgbe_dev_start,
 527         .dev_stop             = ixgbe_dev_stop,
 528         .dev_set_link_up    = ixgbe_dev_set_link_up,
 529         .dev_set_link_down  = ixgbe_dev_set_link_down,
 530         .dev_close            = ixgbe_dev_close,
 531         .dev_reset            = ixgbe_dev_reset,
 532         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 533         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 534         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 535         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 536         .link_update          = ixgbe_dev_link_update,
 537         .stats_get            = ixgbe_dev_stats_get,
 538         .xstats_get           = ixgbe_dev_xstats_get,
 539         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 540         .stats_reset          = ixgbe_dev_stats_reset,
 541         .xstats_reset         = ixgbe_dev_xstats_reset,
 542         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 543         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 544         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 545         .fw_version_get       = ixgbe_fw_version_get,
 546         .dev_infos_get        = ixgbe_dev_info_get,
 547         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 548         .mtu_set              = ixgbe_dev_mtu_set,
 549         .vlan_filter_set      = ixgbe_vlan_filter_set,
 550         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 551         .vlan_offload_set     = ixgbe_vlan_offload_set,
 552         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 553         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 554         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 555         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 556         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 557         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 558         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 559         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 560         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 561         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 562         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 563         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 564         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 565         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 566         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 567         .dev_led_on           = ixgbe_dev_led_on,
 568         .dev_led_off          = ixgbe_dev_led_off,
 569         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 570         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 571         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 572         .mac_addr_add         = ixgbe_add_rar,
 573         .mac_addr_remove      = ixgbe_remove_rar,
 574         .mac_addr_set         = ixgbe_set_default_mac_addr,
 575         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 576         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 577         .mirror_rule_set      = ixgbe_mirror_rule_set,
 578         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 579         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 580         .reta_update          = ixgbe_dev_rss_reta_update,
 581         .reta_query           = ixgbe_dev_rss_reta_query,
 582         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 583         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 584         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 585         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 586         .rxq_info_get         = ixgbe_rxq_info_get,
 587         .txq_info_get         = ixgbe_txq_info_get,
 588         .timesync_enable      = ixgbe_timesync_enable,
 589         .timesync_disable     = ixgbe_timesync_disable,
 590         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 591         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 592         .get_reg              = ixgbe_get_regs,
 593         .get_eeprom_length    = ixgbe_get_eeprom_length,
 594         .get_eeprom           = ixgbe_get_eeprom,
 595         .set_eeprom           = ixgbe_set_eeprom,
 596         .get_module_info      = ixgbe_get_module_info,
 597         .get_module_eeprom    = ixgbe_get_module_eeprom,
 598         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 599         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 600         .timesync_read_time   = ixgbe_timesync_read_time,
 601         .timesync_write_time  = ixgbe_timesync_write_time,
 602         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 603         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 604         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 605         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 606         .tm_ops_get           = ixgbe_tm_ops_get,
 607         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 608 };
 609
 610 /*
 611  * dev_ops for virtual function, bare necessities for basic vf
 612  * operation have been implemented
 613  */
 614 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 615         .dev_configure        = ixgbevf_dev_configure,
 616         .dev_start            = ixgbevf_dev_start,
 617         .dev_stop             = ixgbevf_dev_stop,
 618         .link_update          = ixgbevf_dev_link_update,
 619         .stats_get            = ixgbevf_dev_stats_get,
 620         .xstats_get           = ixgbevf_dev_xstats_get,
 621         .stats_reset          = ixgbevf_dev_stats_reset,
 622         .xstats_reset         = ixgbevf_dev_stats_reset,
 623         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 624         .dev_close            = ixgbevf_dev_close,
 625         .dev_reset            = ixgbevf_dev_reset,
 626         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 627         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 628         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 629         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 630         .dev_infos_get        = ixgbevf_dev_info_get,
 631         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 632         .mtu_set              = ixgbevf_dev_set_mtu,
 633         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 634         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 635         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 636         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 637         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 638         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 639         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 640         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 641         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 642         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 643         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 644         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 645         .mac_addr_add         = ixgbevf_add_mac_addr,
 646         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 647         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 648         .rxq_info_get         = ixgbe_rxq_info_get,
 649         .txq_info_get         = ixgbe_txq_info_get,
 650         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 651         .get_reg              = ixgbevf_get_regs,
 652         .reta_update          = ixgbe_dev_rss_reta_update,
 653         .reta_query           = ixgbe_dev_rss_reta_query,
 654         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 655         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 656         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 657 };
 658
 659 /* store statistics names and its offset in stats structure */
 660 struct rte_ixgbe_xstats_name_off {
 661         char name[RTE_ETH_XSTATS_NAME_SIZE];
 662         unsigned offset;
 663 };
 664
 665 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 666         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 667         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 668         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 669         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 670         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 671         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 672         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 673         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 674         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 675         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 676         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 677         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 678         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 679         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 680         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 prc1023)},
 682         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 prc1522)},
 684         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 685         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 686         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 687         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 688         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 689         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 690         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 691         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 692         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 693         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 694         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 695         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 696         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 697         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 698         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 699         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 700         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 701                 ptc1023)},
 702         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 703                 ptc1522)},
 704         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 705         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 706         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 707         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 708
 709         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirustat_add)},
 711         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 712                 fdirustat_remove)},
 713         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 714                 fdirfstat_fadd)},
 715         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 716                 fdirfstat_fremove)},
 717         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 718                 fdirmatch)},
 719         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 720                 fdirmiss)},
 721
 722         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 723         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 724         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 725                 fclast)},
 726         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 727         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 728         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 729         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 730         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 731                 fcoe_noddp)},
 732         {"rx_fcoe_no_direct_data_placement_ext_buff",
 733                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 734
 735         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxontxc)},
 737         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxonrxc)},
 739         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 740                 lxofftxc)},
 741         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 742                 lxoffrxc)},
 743         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 744 };
 745
 746 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 747                            sizeof(rte_ixgbe_stats_strings[0]))
 748
 749 /* MACsec statistics */
 750 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 751         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 752                 out_pkts_untagged)},
 753         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 754                 out_pkts_encrypted)},
 755         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 756                 out_pkts_protected)},
 757         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 758                 out_octets_encrypted)},
 759         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 760                 out_octets_protected)},
 761         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_untagged)},
 763         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_badtag)},
 765         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_nosci)},
 767         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_unknownsci)},
 769         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 770                 in_octets_decrypted)},
 771         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 772                 in_octets_validated)},
 773         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_unchecked)},
 775         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_delayed)},
 777         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_late)},
 779         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_ok)},
 781         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_invalid)},
 783         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 784                 in_pkts_notvalid)},
 785         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 786                 in_pkts_unusedsa)},
 787         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 788                 in_pkts_notusingsa)},
 789 };
 790
 791 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 792                            sizeof(rte_ixgbe_macsec_strings[0]))
 793
 794 /* Per-queue statistics */
 795 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 796         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 797         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 798         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 799         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 800 };
 801
 802 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 803                            sizeof(rte_ixgbe_rxq_strings[0]))
 804 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 805
 806 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 807         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 808         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 809         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 810                 pxon2offc)},
 811 };
 812
 813 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 814                            sizeof(rte_ixgbe_txq_strings[0]))
 815 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 816
 817 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 818         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 819 };
 820
 821 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 822                 sizeof(rte_ixgbevf_stats_strings[0]))
 823
 824 /*
 825  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 826  */
 827 static inline int
 828 ixgbe_is_sfp(struct ixgbe_hw *hw)
 829 {
 830         switch (hw->phy.type) {
 831         case ixgbe_phy_sfp_avago:
 832         case ixgbe_phy_sfp_ftl:
 833         case ixgbe_phy_sfp_intel:
 834         case ixgbe_phy_sfp_unknown:
 835         case ixgbe_phy_sfp_passive_tyco:
 836         case ixgbe_phy_sfp_passive_unknown:
 837                 return 1;
 838         default:
 839                 return 0;
 840         }
 841 }
 842
 843 static inline int32_t
 844 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 845 {
 846         uint32_t ctrl_ext;
 847         int32_t status;
 848
 849         status = ixgbe_reset_hw(hw);
 850
 851         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 852         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 853         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 854         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 855         IXGBE_WRITE_FLUSH(hw);
 856
 857         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 858                 status = IXGBE_SUCCESS;
 859         return status;
 860 }
 861
 862 static inline void
 863 ixgbe_enable_intr(struct rte_eth_dev *dev)
 864 {
 865         struct ixgbe_interrupt *intr =
 866                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 867         struct ixgbe_hw *hw =
 868                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 869
 870         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 871         IXGBE_WRITE_FLUSH(hw);
 872 }
 873
 874 /*
 875  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 876  */
 877 static void
 878 ixgbe_disable_intr(struct ixgbe_hw *hw)
 879 {
 880         PMD_INIT_FUNC_TRACE();
 881
 882         if (hw->mac.type == ixgbe_mac_82598EB) {
 883                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 884         } else {
 885                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 886                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 887                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 888         }
 889         IXGBE_WRITE_FLUSH(hw);
 890 }
 891
 892 /*
 893  * This function resets queue statistics mapping registers.
 894  * From Niantic datasheet, Initialization of Statistics section:
 895  * "...if software requires the queue counters, the RQSMR and TQSM registers
 896  * must be re-programmed following a device reset.
 897  */
 898 static void
 899 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 900 {
 901         uint32_t i;
 902
 903         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 904                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 905                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 906         }
 907 }
 908
 909
 910 static int
 911 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 912                                   uint16_t queue_id,
 913                                   uint8_t stat_idx,
 914                                   uint8_t is_rx)
 915 {
 916 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 917 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 918 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 919
 920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 921         struct ixgbe_stat_mapping_registers *stat_mappings =
 922                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 923         uint32_t qsmr_mask = 0;
 924         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 925         uint32_t q_map;
 926         uint8_t n, offset;
 927
 928         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 929                 (hw->mac.type != ixgbe_mac_X540) &&
 930                 (hw->mac.type != ixgbe_mac_X550) &&
 931                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 932                 (hw->mac.type != ixgbe_mac_X550EM_a))
 933                 return -ENOSYS;
 934
 935         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 936                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 937                      queue_id, stat_idx);
 938
 939         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 940         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 941                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 942                 return -EIO;
 943         }
 944         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 945
 946         /* Now clear any previous stat_idx set */
 947         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 948         if (!is_rx)
 949                 stat_mappings->tqsm[n] &= ~clearing_mask;
 950         else
 951                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 952
 953         q_map = (uint32_t)stat_idx;
 954         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 955         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 956         if (!is_rx)
 957                 stat_mappings->tqsm[n] |= qsmr_mask;
 958         else
 959                 stat_mappings->rqsmr[n] |= qsmr_mask;
 960
 961         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 962                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 963                      queue_id, stat_idx);
 964         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 965                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 966
 967         /* Now write the mapping in the appropriate register */
 968         if (is_rx) {
 969                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 970                              stat_mappings->rqsmr[n], n);
 971                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 972         } else {
 973                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 974                              stat_mappings->tqsm[n], n);
 975                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 976         }
 977         return 0;
 978 }
 979
 980 static void
 981 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 982 {
 983         struct ixgbe_stat_mapping_registers *stat_mappings =
 984                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 986         int i;
 987
 988         /* write whatever was in stat mapping table to the NIC */
 989         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 990                 /* rx */
 991                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 992
 993                 /* tx */
 994                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 995         }
 996 }
 997
 998 static void
 999 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1000 {
1001         uint8_t i;
1002         struct ixgbe_dcb_tc_config *tc;
1003         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1004
1005         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1006         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1007         for (i = 0; i < dcb_max_tc; i++) {
1008                 tc = &dcb_config->tc_config[i];
1009                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1010                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1011                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1012                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1013                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1014                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1015                 tc->pfc = ixgbe_dcb_pfc_disabled;
1016         }
1017
1018         /* Initialize default user to priority mapping, UPx->TC0 */
1019         tc = &dcb_config->tc_config[0];
1020         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1021         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1022         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1023                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1024                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1025         }
1026         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1027         dcb_config->pfc_mode_enable = false;
1028         dcb_config->vt_mode = true;
1029         dcb_config->round_robin_enable = false;
1030         /* support all DCB capabilities in 82599 */
1031         dcb_config->support.capabilities = 0xFF;
1032
1033         /*we only support 4 Tcs for X540, X550 */
1034         if (hw->mac.type == ixgbe_mac_X540 ||
1035                 hw->mac.type == ixgbe_mac_X550 ||
1036                 hw->mac.type == ixgbe_mac_X550EM_x ||
1037                 hw->mac.type == ixgbe_mac_X550EM_a) {
1038                 dcb_config->num_tcs.pg_tcs = 4;
1039                 dcb_config->num_tcs.pfc_tcs = 4;
1040         }
1041 }
1042
1043 /*
1044  * Ensure that all locks are released before first NVM or PHY access
1045  */
1046 static void
1047 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1048 {
1049         uint16_t mask;
1050
1051         /*
1052          * Phy lock should not fail in this early stage. If this is the case,
1053          * it is due to an improper exit of the application.
1054          * So force the release of the faulty lock. Release of common lock
1055          * is done automatically by swfw_sync function.
1056          */
1057         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1058         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1059                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1060         }
1061         ixgbe_release_swfw_semaphore(hw, mask);
1062
1063         /*
1064          * These ones are more tricky since they are common to all ports; but
1065          * swfw_sync retries last long enough (1s) to be almost sure that if
1066          * lock can not be taken it is due to an improper lock of the
1067          * semaphore.
1068          */
1069         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1070         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1071                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1072         }
1073         ixgbe_release_swfw_semaphore(hw, mask);
1074 }
1075
1076 /*
1077  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1078  * It returns 0 on success.
1079  */
1080 static int
1081 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1082 {
1083         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1084         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1085         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1086         struct ixgbe_hw *hw =
1087                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1088         struct ixgbe_vfta *shadow_vfta =
1089                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1090         struct ixgbe_hwstrip *hwstrip =
1091                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1092         struct ixgbe_dcb_config *dcb_config =
1093                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1094         struct ixgbe_filter_info *filter_info =
1095                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1096         struct ixgbe_bw_conf *bw_conf =
1097                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1098         uint32_t ctrl_ext;
1099         uint16_t csum;
1100         int diag, i;
1101
1102         PMD_INIT_FUNC_TRACE();
1103
1104         ixgbe_dev_macsec_setting_reset(eth_dev);
1105
1106         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1107         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1108         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1109         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1110
1111         /*
1112          * For secondary processes, we don't initialise any further as primary
1113          * has already done this work. Only check we don't need a different
1114          * RX and TX function.
1115          */
1116         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1117                 struct ixgbe_tx_queue *txq;
1118                 /* TX queue function in primary, set by last queue initialized
1119                  * Tx queue may not initialized by primary process
1120                  */
1121                 if (eth_dev->data->tx_queues) {
1122                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1123                         ixgbe_set_tx_function(eth_dev, txq);
1124                 } else {
1125                         /* Use default TX function if we get here */
1126                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1127                                      "Using default TX function.");
1128                 }
1129
1130                 ixgbe_set_rx_function(eth_dev);
1131
1132                 return 0;
1133         }
1134
1135         rte_atomic32_clear(&ad->link_thread_running);
1136         rte_eth_copy_pci_info(eth_dev, pci_dev);
1137
1138         /* Vendor and Device ID need to be set before init of shared code */
1139         hw->device_id = pci_dev->id.device_id;
1140         hw->vendor_id = pci_dev->id.vendor_id;
1141         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1142         hw->allow_unsupported_sfp = 1;
1143
1144         /* Initialize the shared code (base driver) */
1145 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1146         diag = ixgbe_bypass_init_shared_code(hw);
1147 #else
1148         diag = ixgbe_init_shared_code(hw);
1149 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1150
1151         if (diag != IXGBE_SUCCESS) {
1152                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1153                 return -EIO;
1154         }
1155
1156         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1157                 PMD_INIT_LOG(ERR, "\nERROR: "
1158                         "Firmware recovery mode detected. Limiting functionality.\n"
1159                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1160                         "User Guide for details on firmware recovery mode.");
1161                 return -EIO;
1162         }
1163
1164         /* pick up the PCI bus settings for reporting later */
1165         ixgbe_get_bus_info(hw);
1166
1167         /* Unlock any pending hardware semaphore */
1168         ixgbe_swfw_lock_reset(hw);
1169
1170 #ifdef RTE_LIBRTE_SECURITY
1171         /* Initialize security_ctx only for primary process*/
1172         if (ixgbe_ipsec_ctx_create(eth_dev))
1173                 return -ENOMEM;
1174 #endif
1175
1176         /* Initialize DCB configuration*/
1177         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1178         ixgbe_dcb_init(hw, dcb_config);
1179         /* Get Hardware Flow Control setting */
1180         hw->fc.requested_mode = ixgbe_fc_none;
1181         hw->fc.current_mode = ixgbe_fc_none;
1182         hw->fc.pause_time = IXGBE_FC_PAUSE;
1183         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1184                 hw->fc.low_water[i] = IXGBE_FC_LO;
1185                 hw->fc.high_water[i] = IXGBE_FC_HI;
1186         }
1187         hw->fc.send_xon = 1;
1188
1189         /* Make sure we have a good EEPROM before we read from it */
1190         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1191         if (diag != IXGBE_SUCCESS) {
1192                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1193                 return -EIO;
1194         }
1195
1196 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1197         diag = ixgbe_bypass_init_hw(hw);
1198 #else
1199         diag = ixgbe_init_hw(hw);
1200 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1201
1202         /*
1203          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1204          * is called too soon after the kernel driver unbinding/binding occurs.
1205          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1206          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1207          * also called. See ixgbe_identify_phy_82599(). The reason for the
1208          * failure is not known, and only occuts when virtualisation features
1209          * are disabled in the bios. A delay of 100ms  was found to be enough by
1210          * trial-and-error, and is doubled to be safe.
1211          */
1212         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1213                 rte_delay_ms(200);
1214                 diag = ixgbe_init_hw(hw);
1215         }
1216
1217         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1218                 diag = IXGBE_SUCCESS;
1219
1220         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1221                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1222                              "LOM.  Please be aware there may be issues associated "
1223                              "with your hardware.");
1224                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1225                              "please contact your Intel or hardware representative "
1226                              "who provided you with this hardware.");
1227         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1228                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1229         if (diag) {
1230                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1231                 return -EIO;
1232         }
1233
1234         /* Reset the hw statistics */
1235         ixgbe_dev_stats_reset(eth_dev);
1236
1237         /* disable interrupt */
1238         ixgbe_disable_intr(hw);
1239
1240         /* reset mappings for queue statistics hw counters*/
1241         ixgbe_reset_qstat_mappings(hw);
1242
1243         /* Allocate memory for storing MAC addresses */
1244         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1245                                                hw->mac.num_rar_entries, 0);
1246         if (eth_dev->data->mac_addrs == NULL) {
1247                 PMD_INIT_LOG(ERR,
1248                              "Failed to allocate %u bytes needed to store "
1249                              "MAC addresses",
1250                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1251                 return -ENOMEM;
1252         }
1253         /* Copy the permanent MAC address */
1254         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1255                         &eth_dev->data->mac_addrs[0]);
1256
1257         /* Allocate memory for storing hash filter MAC addresses */
1258         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1259                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1260         if (eth_dev->data->hash_mac_addrs == NULL) {
1261                 PMD_INIT_LOG(ERR,
1262                              "Failed to allocate %d bytes needed to store MAC addresses",
1263                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1264                 return -ENOMEM;
1265         }
1266
1267         /* Pass the information to the rte_eth_dev_close() that it should also
1268          * release the private port resources.
1269          */
1270         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1271
1272         /* initialize the vfta */
1273         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1274
1275         /* initialize the hw strip bitmap*/
1276         memset(hwstrip, 0, sizeof(*hwstrip));
1277
1278         /* initialize PF if max_vfs not zero */
1279         ixgbe_pf_host_init(eth_dev);
1280
1281         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1282         /* let hardware know driver is loaded */
1283         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1284         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1285         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1286         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1287         IXGBE_WRITE_FLUSH(hw);
1288
1289         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1290                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1291                              (int) hw->mac.type, (int) hw->phy.type,
1292                              (int) hw->phy.sfp_type);
1293         else
1294                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1295                              (int) hw->mac.type, (int) hw->phy.type);
1296
1297         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1298                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1299                      pci_dev->id.device_id);
1300
1301         rte_intr_callback_register(intr_handle,
1302                                    ixgbe_dev_interrupt_handler, eth_dev);
1303
1304         /* enable uio/vfio intr/eventfd mapping */
1305         rte_intr_enable(intr_handle);
1306
1307         /* enable support intr */
1308         ixgbe_enable_intr(eth_dev);
1309
1310         /* initialize filter info */
1311         memset(filter_info, 0,
1312                sizeof(struct ixgbe_filter_info));
1313
1314         /* initialize 5tuple filter list */
1315         TAILQ_INIT(&filter_info->fivetuple_list);
1316
1317         /* initialize flow director filter list & hash */
1318         ixgbe_fdir_filter_init(eth_dev);
1319
1320         /* initialize l2 tunnel filter list & hash */
1321         ixgbe_l2_tn_filter_init(eth_dev);
1322
1323         /* initialize flow filter lists */
1324         ixgbe_filterlist_init();
1325
1326         /* initialize bandwidth configuration info */
1327         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1328
1329         /* initialize Traffic Manager configuration */
1330         ixgbe_tm_conf_init(eth_dev);
1331
1332         return 0;
1333 }
1334
1335 static int
1336 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1337 {
1338         PMD_INIT_FUNC_TRACE();
1339
1340         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1341                 return 0;
1342
1343         ixgbe_dev_close(eth_dev);
1344
1345         return 0;
1346 }
1347
1348 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1349 {
1350         struct ixgbe_filter_info *filter_info =
1351                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1352         struct ixgbe_5tuple_filter *p_5tuple;
1353
1354         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1355                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1356                              p_5tuple,
1357                              entries);
1358                 rte_free(p_5tuple);
1359         }
1360         memset(filter_info->fivetuple_mask, 0,
1361                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1362
1363         return 0;
1364 }
1365
1366 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct ixgbe_hw_fdir_info *fdir_info =
1369                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1370         struct ixgbe_fdir_filter *fdir_filter;
1371
1372                 if (fdir_info->hash_map)
1373                 rte_free(fdir_info->hash_map);
1374         if (fdir_info->hash_handle)
1375                 rte_hash_free(fdir_info->hash_handle);
1376
1377         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1378                 TAILQ_REMOVE(&fdir_info->fdir_list,
1379                              fdir_filter,
1380                              entries);
1381                 rte_free(fdir_filter);
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1388 {
1389         struct ixgbe_l2_tn_info *l2_tn_info =
1390                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1391         struct ixgbe_l2_tn_filter *l2_tn_filter;
1392
1393         if (l2_tn_info->hash_map)
1394                 rte_free(l2_tn_info->hash_map);
1395         if (l2_tn_info->hash_handle)
1396                 rte_hash_free(l2_tn_info->hash_handle);
1397
1398         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1399                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1400                              l2_tn_filter,
1401                              entries);
1402                 rte_free(l2_tn_filter);
1403         }
1404
1405         return 0;
1406 }
1407
1408 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1409 {
1410         struct ixgbe_hw_fdir_info *fdir_info =
1411                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1412         char fdir_hash_name[RTE_HASH_NAMESIZE];
1413         struct rte_hash_parameters fdir_hash_params = {
1414                 .name = fdir_hash_name,
1415                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1416                 .key_len = sizeof(union ixgbe_atr_input),
1417                 .hash_func = rte_hash_crc,
1418                 .hash_func_init_val = 0,
1419                 .socket_id = rte_socket_id(),
1420         };
1421
1422         TAILQ_INIT(&fdir_info->fdir_list);
1423         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1424                  "fdir_%s", eth_dev->device->name);
1425         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1426         if (!fdir_info->hash_handle) {
1427                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1428                 return -EINVAL;
1429         }
1430         fdir_info->hash_map = rte_zmalloc("ixgbe",
1431                                           sizeof(struct ixgbe_fdir_filter *) *
1432                                           IXGBE_MAX_FDIR_FILTER_NUM,
1433                                           0);
1434         if (!fdir_info->hash_map) {
1435                 PMD_INIT_LOG(ERR,
1436                              "Failed to allocate memory for fdir hash map!");
1437                 return -ENOMEM;
1438         }
1439         fdir_info->mask_added = FALSE;
1440
1441         return 0;
1442 }
1443
1444 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1445 {
1446         struct ixgbe_l2_tn_info *l2_tn_info =
1447                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1448         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1449         struct rte_hash_parameters l2_tn_hash_params = {
1450                 .name = l2_tn_hash_name,
1451                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1452                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1453                 .hash_func = rte_hash_crc,
1454                 .hash_func_init_val = 0,
1455                 .socket_id = rte_socket_id(),
1456         };
1457
1458         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1459         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1460                  "l2_tn_%s", eth_dev->device->name);
1461         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1462         if (!l2_tn_info->hash_handle) {
1463                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1464                 return -EINVAL;
1465         }
1466         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1467                                    sizeof(struct ixgbe_l2_tn_filter *) *
1468                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1469                                    0);
1470         if (!l2_tn_info->hash_map) {
1471                 PMD_INIT_LOG(ERR,
1472                         "Failed to allocate memory for L2 TN hash map!");
1473                 return -ENOMEM;
1474         }
1475         l2_tn_info->e_tag_en = FALSE;
1476         l2_tn_info->e_tag_fwd_en = FALSE;
1477         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1478
1479         return 0;
1480 }
1481 /*
1482  * Negotiate mailbox API version with the PF.
1483  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1484  * Then we try to negotiate starting with the most recent one.
1485  * If all negotiation attempts fail, then we will proceed with
1486  * the default one (ixgbe_mbox_api_10).
1487  */
1488 static void
1489 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1490 {
1491         int32_t i;
1492
1493         /* start with highest supported, proceed down */
1494         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1495                 ixgbe_mbox_api_13,
1496                 ixgbe_mbox_api_12,
1497                 ixgbe_mbox_api_11,
1498                 ixgbe_mbox_api_10,
1499         };
1500
1501         for (i = 0;
1502                         i != RTE_DIM(sup_ver) &&
1503                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1504                         i++)
1505                 ;
1506 }
1507
1508 static void
1509 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1510 {
1511         uint64_t random;
1512
1513         /* Set Organizationally Unique Identifier (OUI) prefix. */
1514         mac_addr->addr_bytes[0] = 0x00;
1515         mac_addr->addr_bytes[1] = 0x09;
1516         mac_addr->addr_bytes[2] = 0xC0;
1517         /* Force indication of locally assigned MAC address. */
1518         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1519         /* Generate the last 3 bytes of the MAC address with a random number. */
1520         random = rte_rand();
1521         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1522 }
1523
1524 static int
1525 devarg_handle_int(__rte_unused const char *key, const char *value,
1526                   void *extra_args)
1527 {
1528         uint16_t *n = extra_args;
1529
1530         if (value == NULL || extra_args == NULL)
1531                 return -EINVAL;
1532
1533         *n = (uint16_t)strtoul(value, NULL, 0);
1534         if (*n == USHRT_MAX && errno == ERANGE)
1535                 return -1;
1536
1537         return 0;
1538 }
1539
1540 static void
1541 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1542                       struct rte_devargs *devargs)
1543 {
1544         struct rte_kvargs *kvlist;
1545         uint16_t pflink_fullchk;
1546
1547         if (devargs == NULL)
1548                 return;
1549
1550         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1551         if (kvlist == NULL)
1552                 return;
1553
1554         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1555             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1556                                devarg_handle_int, &pflink_fullchk) == 0 &&
1557             pflink_fullchk == 1)
1558                 adapter->pflink_fullchk = 1;
1559
1560         rte_kvargs_free(kvlist);
1561 }
1562
1563 /*
1564  * Virtual Function device init
1565  */
1566 static int
1567 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1568 {
1569         int diag;
1570         uint32_t tc, tcs;
1571         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1572         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1574         struct ixgbe_hw *hw =
1575                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1576         struct ixgbe_vfta *shadow_vfta =
1577                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1578         struct ixgbe_hwstrip *hwstrip =
1579                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1580         struct rte_ether_addr *perm_addr =
1581                 (struct rte_ether_addr *)hw->mac.perm_addr;
1582
1583         PMD_INIT_FUNC_TRACE();
1584
1585         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1586         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1587         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1588
1589         /* for secondary processes, we don't initialise any further as primary
1590          * has already done this work. Only check we don't need a different
1591          * RX function
1592          */
1593         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1594                 struct ixgbe_tx_queue *txq;
1595                 /* TX queue function in primary, set by last queue initialized
1596                  * Tx queue may not initialized by primary process
1597                  */
1598                 if (eth_dev->data->tx_queues) {
1599                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1600                         ixgbe_set_tx_function(eth_dev, txq);
1601                 } else {
1602                         /* Use default TX function if we get here */
1603                         PMD_INIT_LOG(NOTICE,
1604                                      "No TX queues configured yet. Using default TX function.");
1605                 }
1606
1607                 ixgbe_set_rx_function(eth_dev);
1608
1609                 return 0;
1610         }
1611
1612         rte_atomic32_clear(&ad->link_thread_running);
1613         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1614                               pci_dev->device.devargs);
1615
1616         rte_eth_copy_pci_info(eth_dev, pci_dev);
1617
1618         hw->device_id = pci_dev->id.device_id;
1619         hw->vendor_id = pci_dev->id.vendor_id;
1620         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1621
1622         /* initialize the vfta */
1623         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1624
1625         /* initialize the hw strip bitmap*/
1626         memset(hwstrip, 0, sizeof(*hwstrip));
1627
1628         /* Initialize the shared code (base driver) */
1629         diag = ixgbe_init_shared_code(hw);
1630         if (diag != IXGBE_SUCCESS) {
1631                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1632                 return -EIO;
1633         }
1634
1635         /* init_mailbox_params */
1636         hw->mbx.ops.init_params(hw);
1637
1638         /* Reset the hw statistics */
1639         ixgbevf_dev_stats_reset(eth_dev);
1640
1641         /* Disable the interrupts for VF */
1642         ixgbevf_intr_disable(eth_dev);
1643
1644         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1645         diag = hw->mac.ops.reset_hw(hw);
1646
1647         /*
1648          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1649          * the underlying PF driver has not assigned a MAC address to the VF.
1650          * In this case, assign a random MAC address.
1651          */
1652         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1653                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1654                 /*
1655                  * This error code will be propagated to the app by
1656                  * rte_eth_dev_reset, so use a public error code rather than
1657                  * the internal-only IXGBE_ERR_RESET_FAILED
1658                  */
1659                 return -EAGAIN;
1660         }
1661
1662         /* negotiate mailbox API version to use with the PF. */
1663         ixgbevf_negotiate_api(hw);
1664
1665         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1666         ixgbevf_get_queues(hw, &tcs, &tc);
1667
1668         /* Allocate memory for storing MAC addresses */
1669         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1670                                                hw->mac.num_rar_entries, 0);
1671         if (eth_dev->data->mac_addrs == NULL) {
1672                 PMD_INIT_LOG(ERR,
1673                              "Failed to allocate %u bytes needed to store "
1674                              "MAC addresses",
1675                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1676                 return -ENOMEM;
1677         }
1678
1679         /* Pass the information to the rte_eth_dev_close() that it should also
1680          * release the private port resources.
1681          */
1682         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1683
1684         /* Generate a random MAC address, if none was assigned by PF. */
1685         if (rte_is_zero_ether_addr(perm_addr)) {
1686                 generate_random_mac_addr(perm_addr);
1687                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1688                 if (diag) {
1689                         rte_free(eth_dev->data->mac_addrs);
1690                         eth_dev->data->mac_addrs = NULL;
1691                         return diag;
1692                 }
1693                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1694                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1695                              "%02x:%02x:%02x:%02x:%02x:%02x",
1696                              perm_addr->addr_bytes[0],
1697                              perm_addr->addr_bytes[1],
1698                              perm_addr->addr_bytes[2],
1699                              perm_addr->addr_bytes[3],
1700                              perm_addr->addr_bytes[4],
1701                              perm_addr->addr_bytes[5]);
1702         }
1703
1704         /* Copy the permanent MAC address */
1705         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1706
1707         /* reset the hardware with the new settings */
1708         diag = hw->mac.ops.start_hw(hw);
1709         switch (diag) {
1710         case  0:
1711                 break;
1712
1713         default:
1714                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1715                 return -EIO;
1716         }
1717
1718         rte_intr_callback_register(intr_handle,
1719                                    ixgbevf_dev_interrupt_handler, eth_dev);
1720         rte_intr_enable(intr_handle);
1721         ixgbevf_intr_enable(eth_dev);
1722
1723         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1724                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1725                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1726
1727         return 0;
1728 }
1729
1730 /* Virtual Function device uninit */
1731
1732 static int
1733 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1734 {
1735         PMD_INIT_FUNC_TRACE();
1736
1737         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1738                 return 0;
1739
1740         ixgbevf_dev_close(eth_dev);
1741
1742         return 0;
1743 }
1744
1745 static int
1746 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1747                 struct rte_pci_device *pci_dev)
1748 {
1749         char name[RTE_ETH_NAME_MAX_LEN];
1750         struct rte_eth_dev *pf_ethdev;
1751         struct rte_eth_devargs eth_da;
1752         int i, retval;
1753
1754         if (pci_dev->device.devargs) {
1755                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1756                                 &eth_da);
1757                 if (retval)
1758                         return retval;
1759         } else
1760                 memset(&eth_da, 0, sizeof(eth_da));
1761
1762         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1763                 sizeof(struct ixgbe_adapter),
1764                 eth_dev_pci_specific_init, pci_dev,
1765                 eth_ixgbe_dev_init, NULL);
1766
1767         if (retval || eth_da.nb_representor_ports < 1)
1768                 return retval;
1769
1770         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1771         if (pf_ethdev == NULL)
1772                 return -ENODEV;
1773
1774         /* probe VF representor ports */
1775         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1776                 struct ixgbe_vf_info *vfinfo;
1777                 struct ixgbe_vf_representor representor;
1778
1779                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1780                         pf_ethdev->data->dev_private);
1781                 if (vfinfo == NULL) {
1782                         PMD_DRV_LOG(ERR,
1783                                 "no virtual functions supported by PF");
1784                         break;
1785                 }
1786
1787                 representor.vf_id = eth_da.representor_ports[i];
1788                 representor.switch_domain_id = vfinfo->switch_domain_id;
1789                 representor.pf_ethdev = pf_ethdev;
1790
1791                 /* representor port net_bdf_port */
1792                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1793                         pci_dev->device.name,
1794                         eth_da.representor_ports[i]);
1795
1796                 retval = rte_eth_dev_create(&pci_dev->device, name,
1797                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1798                         ixgbe_vf_representor_init, &representor);
1799
1800                 if (retval)
1801                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1802                                 "representor %s.", name);
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1809 {
1810         struct rte_eth_dev *ethdev;
1811
1812         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1813         if (!ethdev)
1814                 return 0;
1815
1816         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1817                 return rte_eth_dev_pci_generic_remove(pci_dev,
1818                                         ixgbe_vf_representor_uninit);
1819         else
1820                 return rte_eth_dev_pci_generic_remove(pci_dev,
1821                                                 eth_ixgbe_dev_uninit);
1822 }
1823
1824 static struct rte_pci_driver rte_ixgbe_pmd = {
1825         .id_table = pci_id_ixgbe_map,
1826         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1827         .probe = eth_ixgbe_pci_probe,
1828         .remove = eth_ixgbe_pci_remove,
1829 };
1830
1831 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1832         struct rte_pci_device *pci_dev)
1833 {
1834         return rte_eth_dev_pci_generic_probe(pci_dev,
1835                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1836 }
1837
1838 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1839 {
1840         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1841 }
1842
1843 /*
1844  * virtual function driver struct
1845  */
1846 static struct rte_pci_driver rte_ixgbevf_pmd = {
1847         .id_table = pci_id_ixgbevf_map,
1848         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1849         .probe = eth_ixgbevf_pci_probe,
1850         .remove = eth_ixgbevf_pci_remove,
1851 };
1852
1853 static int
1854 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1855 {
1856         struct ixgbe_hw *hw =
1857                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         struct ixgbe_vfta *shadow_vfta =
1859                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1860         uint32_t vfta;
1861         uint32_t vid_idx;
1862         uint32_t vid_bit;
1863
1864         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1865         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1866         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1867         if (on)
1868                 vfta |= vid_bit;
1869         else
1870                 vfta &= ~vid_bit;
1871         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1872
1873         /* update local VFTA copy */
1874         shadow_vfta->vfta[vid_idx] = vfta;
1875
1876         return 0;
1877 }
1878
1879 static void
1880 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1881 {
1882         if (on)
1883                 ixgbe_vlan_hw_strip_enable(dev, queue);
1884         else
1885                 ixgbe_vlan_hw_strip_disable(dev, queue);
1886 }
1887
1888 static int
1889 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1890                     enum rte_vlan_type vlan_type,
1891                     uint16_t tpid)
1892 {
1893         struct ixgbe_hw *hw =
1894                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895         int ret = 0;
1896         uint32_t reg;
1897         uint32_t qinq;
1898
1899         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1900         qinq &= IXGBE_DMATXCTL_GDV;
1901
1902         switch (vlan_type) {
1903         case ETH_VLAN_TYPE_INNER:
1904                 if (qinq) {
1905                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1906                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1907                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1908                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1909                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1910                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1911                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1912                 } else {
1913                         ret = -ENOTSUP;
1914                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1915                                     " by single VLAN");
1916                 }
1917                 break;
1918         case ETH_VLAN_TYPE_OUTER:
1919                 if (qinq) {
1920                         /* Only the high 16-bits is valid */
1921                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1922                                         IXGBE_EXVET_VET_EXT_SHIFT);
1923                 } else {
1924                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1925                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1926                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1927                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1928                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1929                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1930                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1931                 }
1932
1933                 break;
1934         default:
1935                 ret = -EINVAL;
1936                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1937                 break;
1938         }
1939
1940         return ret;
1941 }
1942
1943 void
1944 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1945 {
1946         struct ixgbe_hw *hw =
1947                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         uint32_t vlnctrl;
1949
1950         PMD_INIT_FUNC_TRACE();
1951
1952         /* Filter Table Disable */
1953         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1954         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1955
1956         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1957 }
1958
1959 void
1960 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1961 {
1962         struct ixgbe_hw *hw =
1963                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964         struct ixgbe_vfta *shadow_vfta =
1965                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1966         uint32_t vlnctrl;
1967         uint16_t i;
1968
1969         PMD_INIT_FUNC_TRACE();
1970
1971         /* Filter Table Enable */
1972         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1973         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1974         vlnctrl |= IXGBE_VLNCTRL_VFE;
1975
1976         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1977
1978         /* write whatever is in local vfta copy */
1979         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1980                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1981 }
1982
1983 static void
1984 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1985 {
1986         struct ixgbe_hwstrip *hwstrip =
1987                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1988         struct ixgbe_rx_queue *rxq;
1989
1990         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1991                 return;
1992
1993         if (on)
1994                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1995         else
1996                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1997
1998         if (queue >= dev->data->nb_rx_queues)
1999                 return;
2000
2001         rxq = dev->data->rx_queues[queue];
2002
2003         if (on) {
2004                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2005                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2006         } else {
2007                 rxq->vlan_flags = PKT_RX_VLAN;
2008                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2009         }
2010 }
2011
2012 static void
2013 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2014 {
2015         struct ixgbe_hw *hw =
2016                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         uint32_t ctrl;
2018
2019         PMD_INIT_FUNC_TRACE();
2020
2021         if (hw->mac.type == ixgbe_mac_82598EB) {
2022                 /* No queue level support */
2023                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2024                 return;
2025         }
2026
2027         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2028         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2029         ctrl &= ~IXGBE_RXDCTL_VME;
2030         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2031
2032         /* record those setting for HW strip per queue */
2033         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2034 }
2035
2036 static void
2037 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2038 {
2039         struct ixgbe_hw *hw =
2040                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041         uint32_t ctrl;
2042
2043         PMD_INIT_FUNC_TRACE();
2044
2045         if (hw->mac.type == ixgbe_mac_82598EB) {
2046                 /* No queue level supported */
2047                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2048                 return;
2049         }
2050
2051         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2053         ctrl |= IXGBE_RXDCTL_VME;
2054         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2055
2056         /* record those setting for HW strip per queue */
2057         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2058 }
2059
2060 static void
2061 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         uint32_t ctrl;
2066
2067         PMD_INIT_FUNC_TRACE();
2068
2069         /* DMATXCTRL: Geric Double VLAN Disable */
2070         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2071         ctrl &= ~IXGBE_DMATXCTL_GDV;
2072         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2073
2074         /* CTRL_EXT: Global Double VLAN Disable */
2075         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2076         ctrl &= ~IXGBE_EXTENDED_VLAN;
2077         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2078
2079 }
2080
2081 static void
2082 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2083 {
2084         struct ixgbe_hw *hw =
2085                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2086         uint32_t ctrl;
2087
2088         PMD_INIT_FUNC_TRACE();
2089
2090         /* DMATXCTRL: Geric Double VLAN Enable */
2091         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2092         ctrl |= IXGBE_DMATXCTL_GDV;
2093         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2094
2095         /* CTRL_EXT: Global Double VLAN Enable */
2096         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2097         ctrl |= IXGBE_EXTENDED_VLAN;
2098         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2099
2100         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2101         if (hw->mac.type == ixgbe_mac_X550 ||
2102             hw->mac.type == ixgbe_mac_X550EM_x ||
2103             hw->mac.type == ixgbe_mac_X550EM_a) {
2104                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2105                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2106                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2107         }
2108
2109         /*
2110          * VET EXT field in the EXVET register = 0x8100 by default
2111          * So no need to change. Same to VT field of DMATXCTL register
2112          */
2113 }
2114
2115 void
2116 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2117 {
2118         struct ixgbe_hw *hw =
2119                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2121         uint32_t ctrl;
2122         uint16_t i;
2123         struct ixgbe_rx_queue *rxq;
2124         bool on;
2125
2126         PMD_INIT_FUNC_TRACE();
2127
2128         if (hw->mac.type == ixgbe_mac_82598EB) {
2129                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2130                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2131                         ctrl |= IXGBE_VLNCTRL_VME;
2132                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2133                 } else {
2134                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2135                         ctrl &= ~IXGBE_VLNCTRL_VME;
2136                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2137                 }
2138         } else {
2139                 /*
2140                  * Other 10G NIC, the VLAN strip can be setup
2141                  * per queue in RXDCTL
2142                  */
2143                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2144                         rxq = dev->data->rx_queues[i];
2145                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2146                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2147                                 ctrl |= IXGBE_RXDCTL_VME;
2148                                 on = TRUE;
2149                         } else {
2150                                 ctrl &= ~IXGBE_RXDCTL_VME;
2151                                 on = FALSE;
2152                         }
2153                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2154
2155                         /* record those setting for HW strip per queue */
2156                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2157                 }
2158         }
2159 }
2160
2161 static void
2162 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2163 {
2164         uint16_t i;
2165         struct rte_eth_rxmode *rxmode;
2166         struct ixgbe_rx_queue *rxq;
2167
2168         if (mask & ETH_VLAN_STRIP_MASK) {
2169                 rxmode = &dev->data->dev_conf.rxmode;
2170                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2171                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2172                                 rxq = dev->data->rx_queues[i];
2173                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2174                         }
2175                 else
2176                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2177                                 rxq = dev->data->rx_queues[i];
2178                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2179                         }
2180         }
2181 }
2182
2183 static int
2184 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2185 {
2186         struct rte_eth_rxmode *rxmode;
2187         rxmode = &dev->data->dev_conf.rxmode;
2188
2189         if (mask & ETH_VLAN_STRIP_MASK) {
2190                 ixgbe_vlan_hw_strip_config(dev);
2191         }
2192
2193         if (mask & ETH_VLAN_FILTER_MASK) {
2194                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2195                         ixgbe_vlan_hw_filter_enable(dev);
2196                 else
2197                         ixgbe_vlan_hw_filter_disable(dev);
2198         }
2199
2200         if (mask & ETH_VLAN_EXTEND_MASK) {
2201                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2202                         ixgbe_vlan_hw_extend_enable(dev);
2203                 else
2204                         ixgbe_vlan_hw_extend_disable(dev);
2205         }
2206
2207         return 0;
2208 }
2209
2210 static int
2211 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2212 {
2213         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2214
2215         ixgbe_vlan_offload_config(dev, mask);
2216
2217         return 0;
2218 }
2219
2220 static void
2221 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2222 {
2223         struct ixgbe_hw *hw =
2224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2226         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2227
2228         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2229         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2230 }
2231
2232 static int
2233 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2234 {
2235         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2236
2237         switch (nb_rx_q) {
2238         case 1:
2239         case 2:
2240                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2241                 break;
2242         case 4:
2243                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2244                 break;
2245         default:
2246                 return -EINVAL;
2247         }
2248
2249         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2250                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2251         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2252                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2253         return 0;
2254 }
2255
2256 static int
2257 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2258 {
2259         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2260         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2262         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2263
2264         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2265                 /* check multi-queue mode */
2266                 switch (dev_conf->rxmode.mq_mode) {
2267                 case ETH_MQ_RX_VMDQ_DCB:
2268                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2269                         break;
2270                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2271                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2272                         PMD_INIT_LOG(ERR, "SRIOV active,"
2273                                         " unsupported mq_mode rx %d.",
2274                                         dev_conf->rxmode.mq_mode);
2275                         return -EINVAL;
2276                 case ETH_MQ_RX_RSS:
2277                 case ETH_MQ_RX_VMDQ_RSS:
2278                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2279                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2280                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2281                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2282                                                 " invalid queue number"
2283                                                 " for VMDQ RSS, allowed"
2284                                                 " value are 1, 2 or 4.");
2285                                         return -EINVAL;
2286                                 }
2287                         break;
2288                 case ETH_MQ_RX_VMDQ_ONLY:
2289                 case ETH_MQ_RX_NONE:
2290                         /* if nothing mq mode configure, use default scheme */
2291                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2292                         break;
2293                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2294                         /* SRIOV only works in VMDq enable mode */
2295                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2296                                         " wrong mq_mode rx %d.",
2297                                         dev_conf->rxmode.mq_mode);
2298                         return -EINVAL;
2299                 }
2300
2301                 switch (dev_conf->txmode.mq_mode) {
2302                 case ETH_MQ_TX_VMDQ_DCB:
2303                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2304                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2305                         break;
2306                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2307                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2308                         break;
2309                 }
2310
2311                 /* check valid queue number */
2312                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2313                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2314                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2315                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2316                                         " must be less than or equal to %d.",
2317                                         nb_rx_q, nb_tx_q,
2318                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2319                         return -EINVAL;
2320                 }
2321         } else {
2322                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2323                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2324                                           " not supported.");
2325                         return -EINVAL;
2326                 }
2327                 /* check configuration for vmdb+dcb mode */
2328                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2329                         const struct rte_eth_vmdq_dcb_conf *conf;
2330
2331                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2332                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2333                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2334                                 return -EINVAL;
2335                         }
2336                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2337                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2338                                conf->nb_queue_pools == ETH_32_POOLS)) {
2339                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2340                                                 " nb_queue_pools must be %d or %d.",
2341                                                 ETH_16_POOLS, ETH_32_POOLS);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2346                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2347
2348                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2349                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2350                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2351                                 return -EINVAL;
2352                         }
2353                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2354                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2355                                conf->nb_queue_pools == ETH_32_POOLS)) {
2356                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2357                                                 " nb_queue_pools != %d and"
2358                                                 " nb_queue_pools != %d.",
2359                                                 ETH_16_POOLS, ETH_32_POOLS);
2360                                 return -EINVAL;
2361                         }
2362                 }
2363
2364                 /* For DCB mode check our configuration before we go further */
2365                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2366                         const struct rte_eth_dcb_rx_conf *conf;
2367
2368                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2369                         if (!(conf->nb_tcs == ETH_4_TCS ||
2370                                conf->nb_tcs == ETH_8_TCS)) {
2371                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372                                                 " and nb_tcs != %d.",
2373                                                 ETH_4_TCS, ETH_8_TCS);
2374                                 return -EINVAL;
2375                         }
2376                 }
2377
2378                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2379                         const struct rte_eth_dcb_tx_conf *conf;
2380
2381                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2382                         if (!(conf->nb_tcs == ETH_4_TCS ||
2383                                conf->nb_tcs == ETH_8_TCS)) {
2384                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2385                                                 " and nb_tcs != %d.",
2386                                                 ETH_4_TCS, ETH_8_TCS);
2387                                 return -EINVAL;
2388                         }
2389                 }
2390
2391                 /*
2392                  * When DCB/VT is off, maximum number of queues changes,
2393                  * except for 82598EB, which remains constant.
2394                  */
2395                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2396                                 hw->mac.type != ixgbe_mac_82598EB) {
2397                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2398                                 PMD_INIT_LOG(ERR,
2399                                              "Neither VT nor DCB are enabled, "
2400                                              "nb_tx_q > %d.",
2401                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2402                                 return -EINVAL;
2403                         }
2404                 }
2405         }
2406         return 0;
2407 }
2408
2409 static int
2410 ixgbe_dev_configure(struct rte_eth_dev *dev)
2411 {
2412         struct ixgbe_interrupt *intr =
2413                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2414         struct ixgbe_adapter *adapter = dev->data->dev_private;
2415         int ret;
2416
2417         PMD_INIT_FUNC_TRACE();
2418
2419         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2420                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2421
2422         /* multipe queue mode checking */
2423         ret  = ixgbe_check_mq_mode(dev);
2424         if (ret != 0) {
2425                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2426                             ret);
2427                 return ret;
2428         }
2429
2430         /* set flag to update link status after init */
2431         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2432
2433         /*
2434          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2435          * allocation or vector Rx preconditions we will reset it.
2436          */
2437         adapter->rx_bulk_alloc_allowed = true;
2438         adapter->rx_vec_allowed = true;
2439
2440         return 0;
2441 }
2442
2443 static void
2444 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2445 {
2446         struct ixgbe_hw *hw =
2447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448         struct ixgbe_interrupt *intr =
2449                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2450         uint32_t gpie;
2451
2452         /* only set up it on X550EM_X */
2453         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2454                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2455                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2456                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2457                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2458                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2459         }
2460 }
2461
2462 int
2463 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2464                         uint16_t tx_rate, uint64_t q_msk)
2465 {
2466         struct ixgbe_hw *hw;
2467         struct ixgbe_vf_info *vfinfo;
2468         struct rte_eth_link link;
2469         uint8_t  nb_q_per_pool;
2470         uint32_t queue_stride;
2471         uint32_t queue_idx, idx = 0, vf_idx;
2472         uint32_t queue_end;
2473         uint16_t total_rate = 0;
2474         struct rte_pci_device *pci_dev;
2475         int ret;
2476
2477         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2478         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2479         if (ret < 0)
2480                 return ret;
2481
2482         if (vf >= pci_dev->max_vfs)
2483                 return -EINVAL;
2484
2485         if (tx_rate > link.link_speed)
2486                 return -EINVAL;
2487
2488         if (q_msk == 0)
2489                 return 0;
2490
2491         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2493         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2494         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2495         queue_idx = vf * queue_stride;
2496         queue_end = queue_idx + nb_q_per_pool - 1;
2497         if (queue_end >= hw->mac.max_tx_queues)
2498                 return -EINVAL;
2499
2500         if (vfinfo) {
2501                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2502                         if (vf_idx == vf)
2503                                 continue;
2504                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2505                                 idx++)
2506                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2507                 }
2508         } else {
2509                 return -EINVAL;
2510         }
2511
2512         /* Store tx_rate for this vf. */
2513         for (idx = 0; idx < nb_q_per_pool; idx++) {
2514                 if (((uint64_t)0x1 << idx) & q_msk) {
2515                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2516                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2517                         total_rate += tx_rate;
2518                 }
2519         }
2520
2521         if (total_rate > dev->data->dev_link.link_speed) {
2522                 /* Reset stored TX rate of the VF if it causes exceed
2523                  * link speed.
2524                  */
2525                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2526                 return -EINVAL;
2527         }
2528
2529         /* Set RTTBCNRC of each queue/pool for vf X  */
2530         for (; queue_idx <= queue_end; queue_idx++) {
2531                 if (0x1 & q_msk)
2532                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2533                 q_msk = q_msk >> 1;
2534         }
2535
2536         return 0;
2537 }
2538
2539 static int
2540 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2541 {
2542         struct ixgbe_adapter *adapter = dev->data->dev_private;
2543         int err;
2544         uint32_t mflcn;
2545
2546         ixgbe_setup_fc(hw);
2547
2548         err = ixgbe_fc_enable(hw);
2549
2550         /* Not negotiated is not an error case */
2551         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2552                 /*
2553                  *check if we want to forward MAC frames - driver doesn't
2554                  *have native capability to do that,
2555                  *so we'll write the registers ourselves
2556                  */
2557
2558                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2559
2560                 /* set or clear MFLCN.PMCF bit depending on configuration */
2561                 if (adapter->mac_ctrl_frame_fwd != 0)
2562                         mflcn |= IXGBE_MFLCN_PMCF;
2563                 else
2564                         mflcn &= ~IXGBE_MFLCN_PMCF;
2565
2566                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2567                 IXGBE_WRITE_FLUSH(hw);
2568
2569                 return 0;
2570         }
2571         return err;
2572 }
2573
2574 /*
2575  * Configure device link speed and setup link.
2576  * It returns 0 on success.
2577  */
2578 static int
2579 ixgbe_dev_start(struct rte_eth_dev *dev)
2580 {
2581         struct ixgbe_hw *hw =
2582                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2583         struct ixgbe_vf_info *vfinfo =
2584                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2585         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2586         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2587         uint32_t intr_vector = 0;
2588         int err;
2589         bool link_up = false, negotiate = 0;
2590         uint32_t speed = 0;
2591         uint32_t allowed_speeds = 0;
2592         int mask = 0;
2593         int status;
2594         uint16_t vf, idx;
2595         uint32_t *link_speeds;
2596         struct ixgbe_tm_conf *tm_conf =
2597                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2598         struct ixgbe_macsec_setting *macsec_setting =
2599                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2600
2601         PMD_INIT_FUNC_TRACE();
2602
2603         /* Stop the link setup handler before resetting the HW. */
2604         ixgbe_dev_wait_setup_link_complete(dev, 0);
2605
2606         /* disable uio/vfio intr/eventfd mapping */
2607         rte_intr_disable(intr_handle);
2608
2609         /* stop adapter */
2610         hw->adapter_stopped = 0;
2611         ixgbe_stop_adapter(hw);
2612
2613         /* reinitialize adapter
2614          * this calls reset and start
2615          */
2616         status = ixgbe_pf_reset_hw(hw);
2617         if (status != 0)
2618                 return -1;
2619         hw->mac.ops.start_hw(hw);
2620         hw->mac.get_link_status = true;
2621
2622         /* configure PF module if SRIOV enabled */
2623         ixgbe_pf_host_configure(dev);
2624
2625         ixgbe_dev_phy_intr_setup(dev);
2626
2627         /* check and configure queue intr-vector mapping */
2628         if ((rte_intr_cap_multiple(intr_handle) ||
2629              !RTE_ETH_DEV_SRIOV(dev).active) &&
2630             dev->data->dev_conf.intr_conf.rxq != 0) {
2631                 intr_vector = dev->data->nb_rx_queues;
2632                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2633                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2634                                         IXGBE_MAX_INTR_QUEUE_NUM);
2635                         return -ENOTSUP;
2636                 }
2637                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2638                         return -1;
2639         }
2640
2641         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2642                 intr_handle->intr_vec =
2643                         rte_zmalloc("intr_vec",
2644                                     dev->data->nb_rx_queues * sizeof(int), 0);
2645                 if (intr_handle->intr_vec == NULL) {
2646                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2647                                      " intr_vec", dev->data->nb_rx_queues);
2648                         return -ENOMEM;
2649                 }
2650         }
2651
2652         /* confiugre msix for sleep until rx interrupt */
2653         ixgbe_configure_msix(dev);
2654
2655         /* initialize transmission unit */
2656         ixgbe_dev_tx_init(dev);
2657
2658         /* This can fail when allocating mbufs for descriptor rings */
2659         err = ixgbe_dev_rx_init(dev);
2660         if (err) {
2661                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2662                 goto error;
2663         }
2664
2665         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2666                 ETH_VLAN_EXTEND_MASK;
2667         err = ixgbe_vlan_offload_config(dev, mask);
2668         if (err) {
2669                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2670                 goto error;
2671         }
2672
2673         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2674                 /* Enable vlan filtering for VMDq */
2675                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2676         }
2677
2678         /* Configure DCB hw */
2679         ixgbe_configure_dcb(dev);
2680
2681         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2682                 err = ixgbe_fdir_configure(dev);
2683                 if (err)
2684                         goto error;
2685         }
2686
2687         /* Restore vf rate limit */
2688         if (vfinfo != NULL) {
2689                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2690                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2691                                 if (vfinfo[vf].tx_rate[idx] != 0)
2692                                         ixgbe_set_vf_rate_limit(
2693                                                 dev, vf,
2694                                                 vfinfo[vf].tx_rate[idx],
2695                                                 1 << idx);
2696         }
2697
2698         ixgbe_restore_statistics_mapping(dev);
2699
2700         err = ixgbe_flow_ctrl_enable(dev, hw);
2701         if (err < 0) {
2702                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2703                 goto error;
2704         }
2705
2706         err = ixgbe_dev_rxtx_start(dev);
2707         if (err < 0) {
2708                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2709                 goto error;
2710         }
2711
2712         /* Skip link setup if loopback mode is enabled. */
2713         if (dev->data->dev_conf.lpbk_mode != 0) {
2714                 err = ixgbe_check_supported_loopback_mode(dev);
2715                 if (err < 0) {
2716                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2717                         goto error;
2718                 } else {
2719                         goto skip_link_setup;
2720                 }
2721         }
2722
2723         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2724                 err = hw->mac.ops.setup_sfp(hw);
2725                 if (err)
2726                         goto error;
2727         }
2728
2729         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2730                 /* Turn on the copper */
2731                 ixgbe_set_phy_power(hw, true);
2732         } else {
2733                 /* Turn on the laser */
2734                 ixgbe_enable_tx_laser(hw);
2735         }
2736
2737         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2738         if (err)
2739                 goto error;
2740         dev->data->dev_link.link_status = link_up;
2741
2742         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2743         if (err)
2744                 goto error;
2745
2746         switch (hw->mac.type) {
2747         case ixgbe_mac_X550:
2748         case ixgbe_mac_X550EM_x:
2749         case ixgbe_mac_X550EM_a:
2750                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2751                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2752                         ETH_LINK_SPEED_10G;
2753                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2754                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2755                         allowed_speeds = ETH_LINK_SPEED_10M |
2756                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2757                 break;
2758         default:
2759                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2760                         ETH_LINK_SPEED_10G;
2761         }
2762
2763         link_speeds = &dev->data->dev_conf.link_speeds;
2764
2765         /* Ignore autoneg flag bit and check the validity of
2766          * link_speed
2767          */
2768         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2769                 PMD_INIT_LOG(ERR, "Invalid link setting");
2770                 goto error;
2771         }
2772
2773         speed = 0x0;
2774         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2775                 switch (hw->mac.type) {
2776                 case ixgbe_mac_82598EB:
2777                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2778                         break;
2779                 case ixgbe_mac_82599EB:
2780                 case ixgbe_mac_X540:
2781                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2782                         break;
2783                 case ixgbe_mac_X550:
2784                 case ixgbe_mac_X550EM_x:
2785                 case ixgbe_mac_X550EM_a:
2786                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2787                         break;
2788                 default:
2789                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2790                 }
2791         } else {
2792                 if (*link_speeds & ETH_LINK_SPEED_10G)
2793                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2794                 if (*link_speeds & ETH_LINK_SPEED_5G)
2795                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2796                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2797                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2798                 if (*link_speeds & ETH_LINK_SPEED_1G)
2799                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2800                 if (*link_speeds & ETH_LINK_SPEED_100M)
2801                         speed |= IXGBE_LINK_SPEED_100_FULL;
2802                 if (*link_speeds & ETH_LINK_SPEED_10M)
2803                         speed |= IXGBE_LINK_SPEED_10_FULL;
2804         }
2805
2806         err = ixgbe_setup_link(hw, speed, link_up);
2807         if (err)
2808                 goto error;
2809
2810 skip_link_setup:
2811
2812         if (rte_intr_allow_others(intr_handle)) {
2813                 /* check if lsc interrupt is enabled */
2814                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2815                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2816                 else
2817                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2818                 ixgbe_dev_macsec_interrupt_setup(dev);
2819         } else {
2820                 rte_intr_callback_unregister(intr_handle,
2821                                              ixgbe_dev_interrupt_handler, dev);
2822                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2823                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2824                                      " no intr multiplex");
2825         }
2826
2827         /* check if rxq interrupt is enabled */
2828         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2829             rte_intr_dp_is_en(intr_handle))
2830                 ixgbe_dev_rxq_interrupt_setup(dev);
2831
2832         /* enable uio/vfio intr/eventfd mapping */
2833         rte_intr_enable(intr_handle);
2834
2835         /* resume enabled intr since hw reset */
2836         ixgbe_enable_intr(dev);
2837         ixgbe_l2_tunnel_conf(dev);
2838         ixgbe_filter_restore(dev);
2839
2840         if (tm_conf->root && !tm_conf->committed)
2841                 PMD_DRV_LOG(WARNING,
2842                             "please call hierarchy_commit() "
2843                             "before starting the port");
2844
2845         /* wait for the controller to acquire link */
2846         err = ixgbe_wait_for_link_up(hw);
2847         if (err)
2848                 goto error;
2849
2850         /*
2851          * Update link status right before return, because it may
2852          * start link configuration process in a separate thread.
2853          */
2854         ixgbe_dev_link_update(dev, 0);
2855
2856         /* setup the macsec setting register */
2857         if (macsec_setting->offload_en)
2858                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2859
2860         return 0;
2861
2862 error:
2863         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2864         ixgbe_dev_clear_queues(dev);
2865         return -EIO;
2866 }
2867
2868 /*
2869  * Stop device: disable rx and tx functions to allow for reconfiguring.
2870  */
2871 static void
2872 ixgbe_dev_stop(struct rte_eth_dev *dev)
2873 {
2874         struct rte_eth_link link;
2875         struct ixgbe_adapter *adapter = dev->data->dev_private;
2876         struct ixgbe_hw *hw =
2877                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2878         struct ixgbe_vf_info *vfinfo =
2879                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2880         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2881         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2882         int vf;
2883         struct ixgbe_tm_conf *tm_conf =
2884                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2885
2886         if (hw->adapter_stopped)
2887                 return;
2888
2889         PMD_INIT_FUNC_TRACE();
2890
2891         ixgbe_dev_wait_setup_link_complete(dev, 0);
2892
2893         /* disable interrupts */
2894         ixgbe_disable_intr(hw);
2895
2896         /* reset the NIC */
2897         ixgbe_pf_reset_hw(hw);
2898         hw->adapter_stopped = 0;
2899
2900         /* stop adapter */
2901         ixgbe_stop_adapter(hw);
2902
2903         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2904                 vfinfo[vf].clear_to_send = false;
2905
2906         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2907                 /* Turn off the copper */
2908                 ixgbe_set_phy_power(hw, false);
2909         } else {
2910                 /* Turn off the laser */
2911                 ixgbe_disable_tx_laser(hw);
2912         }
2913
2914         ixgbe_dev_clear_queues(dev);
2915
2916         /* Clear stored conf */
2917         dev->data->scattered_rx = 0;
2918         dev->data->lro = 0;
2919
2920         /* Clear recorded link status */
2921         memset(&link, 0, sizeof(link));
2922         rte_eth_linkstatus_set(dev, &link);
2923
2924         if (!rte_intr_allow_others(intr_handle))
2925                 /* resume to the default handler */
2926                 rte_intr_callback_register(intr_handle,
2927                                            ixgbe_dev_interrupt_handler,
2928                                            (void *)dev);
2929
2930         /* Clean datapath event and queue/vec mapping */
2931         rte_intr_efd_disable(intr_handle);
2932         if (intr_handle->intr_vec != NULL) {
2933                 rte_free(intr_handle->intr_vec);
2934                 intr_handle->intr_vec = NULL;
2935         }
2936
2937         /* reset hierarchy commit */
2938         tm_conf->committed = false;
2939
2940         adapter->rss_reta_updated = 0;
2941
2942         adapter->mac_ctrl_frame_fwd = 0;
2943
2944         hw->adapter_stopped = true;
2945 }
2946
2947 /*
2948  * Set device link up: enable tx.
2949  */
2950 static int
2951 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2952 {
2953         struct ixgbe_hw *hw =
2954                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955         if (hw->mac.type == ixgbe_mac_82599EB) {
2956 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2957                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2958                         /* Not suported in bypass mode */
2959                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2960                                      "by device id 0x%x", hw->device_id);
2961                         return -ENOTSUP;
2962                 }
2963 #endif
2964         }
2965
2966         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2967                 /* Turn on the copper */
2968                 ixgbe_set_phy_power(hw, true);
2969         } else {
2970                 /* Turn on the laser */
2971                 ixgbe_enable_tx_laser(hw);
2972                 ixgbe_dev_link_update(dev, 0);
2973         }
2974
2975         return 0;
2976 }
2977
2978 /*
2979  * Set device link down: disable tx.
2980  */
2981 static int
2982 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2983 {
2984         struct ixgbe_hw *hw =
2985                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986         if (hw->mac.type == ixgbe_mac_82599EB) {
2987 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2988                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2989                         /* Not suported in bypass mode */
2990                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2991                                      "by device id 0x%x", hw->device_id);
2992                         return -ENOTSUP;
2993                 }
2994 #endif
2995         }
2996
2997         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2998                 /* Turn off the copper */
2999                 ixgbe_set_phy_power(hw, false);
3000         } else {
3001                 /* Turn off the laser */
3002                 ixgbe_disable_tx_laser(hw);
3003                 ixgbe_dev_link_update(dev, 0);
3004         }
3005
3006         return 0;
3007 }
3008
3009 /*
3010  * Reset and stop device.
3011  */
3012 static void
3013 ixgbe_dev_close(struct rte_eth_dev *dev)
3014 {
3015         struct ixgbe_hw *hw =
3016                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3018         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3019         int retries = 0;
3020         int ret;
3021
3022         PMD_INIT_FUNC_TRACE();
3023
3024         ixgbe_pf_reset_hw(hw);
3025
3026         ixgbe_dev_stop(dev);
3027
3028         ixgbe_dev_free_queues(dev);
3029
3030         ixgbe_disable_pcie_master(hw);
3031
3032         /* reprogram the RAR[0] in case user changed it. */
3033         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3034
3035         dev->dev_ops = NULL;
3036         dev->rx_pkt_burst = NULL;
3037         dev->tx_pkt_burst = NULL;
3038
3039         /* Unlock any pending hardware semaphore */
3040         ixgbe_swfw_lock_reset(hw);
3041
3042         /* disable uio intr before callback unregister */
3043         rte_intr_disable(intr_handle);
3044
3045         do {
3046                 ret = rte_intr_callback_unregister(intr_handle,
3047                                 ixgbe_dev_interrupt_handler, dev);
3048                 if (ret >= 0 || ret == -ENOENT) {
3049                         break;
3050                 } else if (ret != -EAGAIN) {
3051                         PMD_INIT_LOG(ERR,
3052                                 "intr callback unregister failed: %d",
3053                                 ret);
3054                 }
3055                 rte_delay_ms(100);
3056         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3057
3058         /* cancel the delay handler before remove dev */
3059         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3060
3061         /* uninitialize PF if max_vfs not zero */
3062         ixgbe_pf_host_uninit(dev);
3063
3064         /* remove all the fdir filters & hash */
3065         ixgbe_fdir_filter_uninit(dev);
3066
3067         /* remove all the L2 tunnel filters & hash */
3068         ixgbe_l2_tn_filter_uninit(dev);
3069
3070         /* Remove all ntuple filters of the device */
3071         ixgbe_ntuple_filter_uninit(dev);
3072
3073         /* clear all the filters list */
3074         ixgbe_filterlist_flush();
3075
3076         /* Remove all Traffic Manager configuration */
3077         ixgbe_tm_conf_uninit(dev);
3078
3079 #ifdef RTE_LIBRTE_SECURITY
3080         rte_free(dev->security_ctx);
3081 #endif
3082
3083 }
3084
3085 /*
3086  * Reset PF device.
3087  */
3088 static int
3089 ixgbe_dev_reset(struct rte_eth_dev *dev)
3090 {
3091         int ret;
3092
3093         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3094          * its VF to make them align with it. The detailed notification
3095          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3096          * To avoid unexpected behavior in VF, currently reset of PF with
3097          * SR-IOV activation is not supported. It might be supported later.
3098          */
3099         if (dev->data->sriov.active)
3100                 return -ENOTSUP;
3101
3102         ret = eth_ixgbe_dev_uninit(dev);
3103         if (ret)
3104                 return ret;
3105
3106         ret = eth_ixgbe_dev_init(dev, NULL);
3107
3108         return ret;
3109 }
3110
3111 static void
3112 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3113                            struct ixgbe_hw_stats *hw_stats,
3114                            struct ixgbe_macsec_stats *macsec_stats,
3115                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3116                            uint64_t *total_qprc, uint64_t *total_qprdc)
3117 {
3118         uint32_t bprc, lxon, lxoff, total;
3119         uint32_t delta_gprc = 0;
3120         unsigned i;
3121         /* Workaround for RX byte count not including CRC bytes when CRC
3122          * strip is enabled. CRC bytes are removed from counters when crc_strip
3123          * is disabled.
3124          */
3125         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3126                         IXGBE_HLREG0_RXCRCSTRP);
3127
3128         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3129         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3130         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3131         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3132
3133         for (i = 0; i < 8; i++) {
3134                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3135
3136                 /* global total per queue */
3137                 hw_stats->mpc[i] += mp;
3138                 /* Running comprehensive total for stats display */
3139                 *total_missed_rx += hw_stats->mpc[i];
3140                 if (hw->mac.type == ixgbe_mac_82598EB) {
3141                         hw_stats->rnbc[i] +=
3142                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3143                         hw_stats->pxonrxc[i] +=
3144                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3145                         hw_stats->pxoffrxc[i] +=
3146                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3147                 } else {
3148                         hw_stats->pxonrxc[i] +=
3149                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3150                         hw_stats->pxoffrxc[i] +=
3151                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3152                         hw_stats->pxon2offc[i] +=
3153                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3154                 }
3155                 hw_stats->pxontxc[i] +=
3156                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3157                 hw_stats->pxofftxc[i] +=
3158                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3159         }
3160         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3161                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3162                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3163                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3164
3165                 delta_gprc += delta_qprc;
3166
3167                 hw_stats->qprc[i] += delta_qprc;
3168                 hw_stats->qptc[i] += delta_qptc;
3169
3170                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3171                 hw_stats->qbrc[i] +=
3172                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3173                 if (crc_strip == 0)
3174                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3175
3176                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3177                 hw_stats->qbtc[i] +=
3178                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3179
3180                 hw_stats->qprdc[i] += delta_qprdc;
3181                 *total_qprdc += hw_stats->qprdc[i];
3182
3183                 *total_qprc += hw_stats->qprc[i];
3184                 *total_qbrc += hw_stats->qbrc[i];
3185         }
3186         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3187         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3188         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3189
3190         /*
3191          * An errata states that gprc actually counts good + missed packets:
3192          * Workaround to set gprc to summated queue packet receives
3193          */
3194         hw_stats->gprc = *total_qprc;
3195
3196         if (hw->mac.type != ixgbe_mac_82598EB) {
3197                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3198                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3199                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3200                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3201                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3202                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3203                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3204                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3205         } else {
3206                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3207                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3208                 /* 82598 only has a counter in the high register */
3209                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3210                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3211                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3212         }
3213         uint64_t old_tpr = hw_stats->tpr;
3214
3215         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3216         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3217
3218         if (crc_strip == 0)
3219                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3220
3221         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3222         hw_stats->gptc += delta_gptc;
3223         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3224         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3225
3226         /*
3227          * Workaround: mprc hardware is incorrectly counting
3228          * broadcasts, so for now we subtract those.
3229          */
3230         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3231         hw_stats->bprc += bprc;
3232         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3233         if (hw->mac.type == ixgbe_mac_82598EB)
3234                 hw_stats->mprc -= bprc;
3235
3236         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3237         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3238         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3239         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3240         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3241         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3242
3243         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3244         hw_stats->lxontxc += lxon;
3245         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3246         hw_stats->lxofftxc += lxoff;
3247         total = lxon + lxoff;
3248
3249         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3250         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3251         hw_stats->gptc -= total;
3252         hw_stats->mptc -= total;
3253         hw_stats->ptc64 -= total;
3254         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3255
3256         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3257         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3258         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3259         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3260         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3261         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3262         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3263         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3264         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3265         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3266         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3267         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3268         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3269         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3270         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3271         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3272         /* Only read FCOE on 82599 */
3273         if (hw->mac.type != ixgbe_mac_82598EB) {
3274                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3275                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3276                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3277                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3278                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3279         }
3280
3281         /* Flow Director Stats registers */
3282         if (hw->mac.type != ixgbe_mac_82598EB) {
3283                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3284                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3285                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3286                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3287                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3288                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3289                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3290                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3291                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3292                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3293         }
3294         /* MACsec Stats registers */
3295         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3296         macsec_stats->out_pkts_encrypted +=
3297                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3298         macsec_stats->out_pkts_protected +=
3299                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3300         macsec_stats->out_octets_encrypted +=
3301                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3302         macsec_stats->out_octets_protected +=
3303                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3304         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3305         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3306         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3307         macsec_stats->in_pkts_unknownsci +=
3308                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3309         macsec_stats->in_octets_decrypted +=
3310                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3311         macsec_stats->in_octets_validated +=
3312                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3313         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3314         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3315         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3316         for (i = 0; i < 2; i++) {
3317                 macsec_stats->in_pkts_ok +=
3318                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3319                 macsec_stats->in_pkts_invalid +=
3320                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3321                 macsec_stats->in_pkts_notvalid +=
3322                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3323         }
3324         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3325         macsec_stats->in_pkts_notusingsa +=
3326                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3327 }
3328
3329 /*
3330  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3331  */
3332 static int
3333 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3334 {
3335         struct ixgbe_hw *hw =
3336                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         struct ixgbe_hw_stats *hw_stats =
3338                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3339         struct ixgbe_macsec_stats *macsec_stats =
3340                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3341                                 dev->data->dev_private);
3342         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3343         unsigned i;
3344
3345         total_missed_rx = 0;
3346         total_qbrc = 0;
3347         total_qprc = 0;
3348         total_qprdc = 0;
3349
3350         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3351                         &total_qbrc, &total_qprc, &total_qprdc);
3352
3353         if (stats == NULL)
3354                 return -EINVAL;
3355
3356         /* Fill out the rte_eth_stats statistics structure */
3357         stats->ipackets = total_qprc;
3358         stats->ibytes = total_qbrc;
3359         stats->opackets = hw_stats->gptc;
3360         stats->obytes = hw_stats->gotc;
3361
3362         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3363                 stats->q_ipackets[i] = hw_stats->qprc[i];
3364                 stats->q_opackets[i] = hw_stats->qptc[i];
3365                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3366                 stats->q_obytes[i] = hw_stats->qbtc[i];
3367                 stats->q_errors[i] = hw_stats->qprdc[i];
3368         }
3369
3370         /* Rx Errors */
3371         stats->imissed  = total_missed_rx;
3372         stats->ierrors  = hw_stats->crcerrs +
3373                           hw_stats->mspdc +
3374                           hw_stats->rlec +
3375                           hw_stats->ruc +
3376                           hw_stats->roc +
3377                           hw_stats->illerrc +
3378                           hw_stats->errbc +
3379                           hw_stats->rfc +
3380                           hw_stats->fccrc +
3381                           hw_stats->fclast;
3382
3383         /* Tx Errors */
3384         stats->oerrors  = 0;
3385         return 0;
3386 }
3387
3388 static int
3389 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3390 {
3391         struct ixgbe_hw_stats *stats =
3392                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3393
3394         /* HW registers are cleared on read */
3395         ixgbe_dev_stats_get(dev, NULL);
3396
3397         /* Reset software totals */
3398         memset(stats, 0, sizeof(*stats));
3399
3400         return 0;
3401 }
3402
3403 /* This function calculates the number of xstats based on the current config */
3404 static unsigned
3405 ixgbe_xstats_calc_num(void) {
3406         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3407                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3408                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3409 }
3410
3411 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3412         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3413 {
3414         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3415         unsigned stat, i, count;
3416
3417         if (xstats_names != NULL) {
3418                 count = 0;
3419
3420                 /* Note: limit >= cnt_stats checked upstream
3421                  * in rte_eth_xstats_names()
3422                  */
3423
3424                 /* Extended stats from ixgbe_hw_stats */
3425                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3426                         strlcpy(xstats_names[count].name,
3427                                 rte_ixgbe_stats_strings[i].name,
3428                                 sizeof(xstats_names[count].name));
3429                         count++;
3430                 }
3431
3432                 /* MACsec Stats */
3433                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3434                         strlcpy(xstats_names[count].name,
3435                                 rte_ixgbe_macsec_strings[i].name,
3436                                 sizeof(xstats_names[count].name));
3437                         count++;
3438                 }
3439
3440                 /* RX Priority Stats */
3441                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3442                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3443                                 snprintf(xstats_names[count].name,
3444                                         sizeof(xstats_names[count].name),
3445                                         "rx_priority%u_%s", i,
3446                                         rte_ixgbe_rxq_strings[stat].name);
3447                                 count++;
3448                         }
3449                 }
3450
3451                 /* TX Priority Stats */
3452                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3453                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3454                                 snprintf(xstats_names[count].name,
3455                                         sizeof(xstats_names[count].name),
3456                                         "tx_priority%u_%s", i,
3457                                         rte_ixgbe_txq_strings[stat].name);
3458                                 count++;
3459                         }
3460                 }
3461         }
3462         return cnt_stats;
3463 }
3464
3465 static int ixgbe_dev_xstats_get_names_by_id(
3466         struct rte_eth_dev *dev,
3467         struct rte_eth_xstat_name *xstats_names,
3468         const uint64_t *ids,
3469         unsigned int limit)
3470 {
3471         if (!ids) {
3472                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3473                 unsigned int stat, i, count;
3474
3475                 if (xstats_names != NULL) {
3476                         count = 0;
3477
3478                         /* Note: limit >= cnt_stats checked upstream
3479                          * in rte_eth_xstats_names()
3480                          */
3481
3482                         /* Extended stats from ixgbe_hw_stats */
3483                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3484                                 strlcpy(xstats_names[count].name,
3485                                         rte_ixgbe_stats_strings[i].name,
3486                                         sizeof(xstats_names[count].name));
3487                                 count++;
3488                         }
3489
3490                         /* MACsec Stats */
3491                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3492                                 strlcpy(xstats_names[count].name,
3493                                         rte_ixgbe_macsec_strings[i].name,
3494                                         sizeof(xstats_names[count].name));
3495                                 count++;
3496                         }
3497
3498                         /* RX Priority Stats */
3499                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3500                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3501                                         snprintf(xstats_names[count].name,
3502                                             sizeof(xstats_names[count].name),
3503                                             "rx_priority%u_%s", i,
3504                                             rte_ixgbe_rxq_strings[stat].name);
3505                                         count++;
3506                                 }
3507                         }
3508
3509                         /* TX Priority Stats */
3510                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3511                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3512                                         snprintf(xstats_names[count].name,
3513                                             sizeof(xstats_names[count].name),
3514                                             "tx_priority%u_%s", i,
3515                                             rte_ixgbe_txq_strings[stat].name);
3516                                         count++;
3517                                 }
3518                         }
3519                 }
3520                 return cnt_stats;
3521         }
3522
3523         uint16_t i;
3524         uint16_t size = ixgbe_xstats_calc_num();
3525         struct rte_eth_xstat_name xstats_names_copy[size];
3526
3527         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3528                         size);
3529
3530         for (i = 0; i < limit; i++) {
3531                 if (ids[i] >= size) {
3532                         PMD_INIT_LOG(ERR, "id value isn't valid");
3533                         return -1;
3534                 }
3535                 strcpy(xstats_names[i].name,
3536                                 xstats_names_copy[ids[i]].name);
3537         }
3538         return limit;
3539 }
3540
3541 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3542         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3543 {
3544         unsigned i;
3545
3546         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3547                 return -ENOMEM;
3548
3549         if (xstats_names != NULL)
3550                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3551                         strlcpy(xstats_names[i].name,
3552                                 rte_ixgbevf_stats_strings[i].name,
3553                                 sizeof(xstats_names[i].name));
3554         return IXGBEVF_NB_XSTATS;
3555 }
3556
3557 static int
3558 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3559                                          unsigned n)
3560 {
3561         struct ixgbe_hw *hw =
3562                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3563         struct ixgbe_hw_stats *hw_stats =
3564                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3565         struct ixgbe_macsec_stats *macsec_stats =
3566                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3567                                 dev->data->dev_private);
3568         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3569         unsigned i, stat, count = 0;
3570
3571         count = ixgbe_xstats_calc_num();
3572
3573         if (n < count)
3574                 return count;
3575
3576         total_missed_rx = 0;
3577         total_qbrc = 0;
3578         total_qprc = 0;
3579         total_qprdc = 0;
3580
3581         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3582                         &total_qbrc, &total_qprc, &total_qprdc);
3583
3584         /* If this is a reset xstats is NULL, and we have cleared the
3585          * registers by reading them.
3586          */
3587         if (!xstats)
3588                 return 0;
3589
3590         /* Extended stats from ixgbe_hw_stats */
3591         count = 0;
3592         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3593                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3594                                 rte_ixgbe_stats_strings[i].offset);
3595                 xstats[count].id = count;
3596                 count++;
3597         }
3598
3599         /* MACsec Stats */
3600         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3601                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3602                                 rte_ixgbe_macsec_strings[i].offset);
3603                 xstats[count].id = count;
3604                 count++;
3605         }
3606
3607         /* RX Priority Stats */
3608         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3609                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3610                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3611                                         rte_ixgbe_rxq_strings[stat].offset +
3612                                         (sizeof(uint64_t) * i));
3613                         xstats[count].id = count;
3614                         count++;
3615                 }
3616         }
3617
3618         /* TX Priority Stats */
3619         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3620                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3621                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3622                                         rte_ixgbe_txq_strings[stat].offset +
3623                                         (sizeof(uint64_t) * i));
3624                         xstats[count].id = count;
3625                         count++;
3626                 }
3627         }
3628         return count;
3629 }
3630
3631 static int
3632 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3633                 uint64_t *values, unsigned int n)
3634 {
3635         if (!ids) {
3636                 struct ixgbe_hw *hw =
3637                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3638                 struct ixgbe_hw_stats *hw_stats =
3639                                 IXGBE_DEV_PRIVATE_TO_STATS(
3640                                                 dev->data->dev_private);
3641                 struct ixgbe_macsec_stats *macsec_stats =
3642                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3643                                         dev->data->dev_private);
3644                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3645                 unsigned int i, stat, count = 0;
3646
3647                 count = ixgbe_xstats_calc_num();
3648
3649                 if (!ids && n < count)
3650                         return count;
3651
3652                 total_missed_rx = 0;
3653                 total_qbrc = 0;
3654                 total_qprc = 0;
3655                 total_qprdc = 0;
3656
3657                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3658                                 &total_missed_rx, &total_qbrc, &total_qprc,
3659                                 &total_qprdc);
3660
3661                 /* If this is a reset xstats is NULL, and we have cleared the
3662                  * registers by reading them.
3663                  */
3664                 if (!ids && !values)
3665                         return 0;
3666
3667                 /* Extended stats from ixgbe_hw_stats */
3668                 count = 0;
3669                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3670                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3671                                         rte_ixgbe_stats_strings[i].offset);
3672                         count++;
3673                 }
3674
3675                 /* MACsec Stats */
3676                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3677                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3678                                         rte_ixgbe_macsec_strings[i].offset);
3679                         count++;
3680                 }
3681
3682                 /* RX Priority Stats */
3683                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3684                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3685                                 values[count] =
3686                                         *(uint64_t *)(((char *)hw_stats) +
3687                                         rte_ixgbe_rxq_strings[stat].offset +
3688                                         (sizeof(uint64_t) * i));
3689                                 count++;
3690                         }
3691                 }
3692
3693                 /* TX Priority Stats */
3694                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3695                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3696                                 values[count] =
3697                                         *(uint64_t *)(((char *)hw_stats) +
3698                                         rte_ixgbe_txq_strings[stat].offset +
3699                                         (sizeof(uint64_t) * i));
3700                                 count++;
3701                         }
3702                 }
3703                 return count;
3704         }
3705
3706         uint16_t i;
3707         uint16_t size = ixgbe_xstats_calc_num();
3708         uint64_t values_copy[size];
3709
3710         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3711
3712         for (i = 0; i < n; i++) {
3713                 if (ids[i] >= size) {
3714                         PMD_INIT_LOG(ERR, "id value isn't valid");
3715                         return -1;
3716                 }
3717                 values[i] = values_copy[ids[i]];
3718         }
3719         return n;
3720 }
3721
3722 static int
3723 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3724 {
3725         struct ixgbe_hw_stats *stats =
3726                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3727         struct ixgbe_macsec_stats *macsec_stats =
3728                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3729                                 dev->data->dev_private);
3730
3731         unsigned count = ixgbe_xstats_calc_num();
3732
3733         /* HW registers are cleared on read */
3734         ixgbe_dev_xstats_get(dev, NULL, count);
3735
3736         /* Reset software totals */
3737         memset(stats, 0, sizeof(*stats));
3738         memset(macsec_stats, 0, sizeof(*macsec_stats));
3739
3740         return 0;
3741 }
3742
3743 static void
3744 ixgbevf_update_stats(struct rte_eth_dev *dev)
3745 {
3746         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3747         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3748                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3749
3750         /* Good Rx packet, include VF loopback */
3751         UPDATE_VF_STAT(IXGBE_VFGPRC,
3752             hw_stats->last_vfgprc, hw_stats->vfgprc);
3753
3754         /* Good Rx octets, include VF loopback */
3755         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3756             hw_stats->last_vfgorc, hw_stats->vfgorc);
3757
3758         /* Good Tx packet, include VF loopback */
3759         UPDATE_VF_STAT(IXGBE_VFGPTC,
3760             hw_stats->last_vfgptc, hw_stats->vfgptc);
3761
3762         /* Good Tx octets, include VF loopback */
3763         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3764             hw_stats->last_vfgotc, hw_stats->vfgotc);
3765
3766         /* Rx Multicst Packet */
3767         UPDATE_VF_STAT(IXGBE_VFMPRC,
3768             hw_stats->last_vfmprc, hw_stats->vfmprc);
3769 }
3770
3771 static int
3772 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3773                        unsigned n)
3774 {
3775         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3776                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3777         unsigned i;
3778
3779         if (n < IXGBEVF_NB_XSTATS)
3780                 return IXGBEVF_NB_XSTATS;
3781
3782         ixgbevf_update_stats(dev);
3783
3784         if (!xstats)
3785                 return 0;
3786
3787         /* Extended stats */
3788         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3789                 xstats[i].id = i;
3790                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3791                         rte_ixgbevf_stats_strings[i].offset);
3792         }
3793
3794         return IXGBEVF_NB_XSTATS;
3795 }
3796
3797 static int
3798 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3799 {
3800         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3801                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3802
3803         ixgbevf_update_stats(dev);
3804
3805         if (stats == NULL)
3806                 return -EINVAL;
3807
3808         stats->ipackets = hw_stats->vfgprc;
3809         stats->ibytes = hw_stats->vfgorc;
3810         stats->opackets = hw_stats->vfgptc;
3811         stats->obytes = hw_stats->vfgotc;
3812         return 0;
3813 }
3814
3815 static int
3816 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3817 {
3818         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3819                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3820
3821         /* Sync HW register to the last stats */
3822         ixgbevf_dev_stats_get(dev, NULL);
3823
3824         /* reset HW current stats*/
3825         hw_stats->vfgprc = 0;
3826         hw_stats->vfgorc = 0;
3827         hw_stats->vfgptc = 0;
3828         hw_stats->vfgotc = 0;
3829
3830         return 0;
3831 }
3832
3833 static int
3834 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3835 {
3836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3837         u16 eeprom_verh, eeprom_verl;
3838         u32 etrack_id;
3839         int ret;
3840
3841         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3842         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3843
3844         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3845         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3846
3847         ret += 1; /* add the size of '\0' */
3848         if (fw_size < (u32)ret)
3849                 return ret;
3850         else
3851                 return 0;
3852 }
3853
3854 static int
3855 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3856 {
3857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3859         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3860
3861         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3862         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3863         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3864                 /*
3865                  * When DCB/VT is off, maximum number of queues changes,
3866                  * except for 82598EB, which remains constant.
3867                  */
3868                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3869                                 hw->mac.type != ixgbe_mac_82598EB)
3870                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3871         }
3872         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3873         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3874         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3875         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3876         dev_info->max_vfs = pci_dev->max_vfs;
3877         if (hw->mac.type == ixgbe_mac_82598EB)
3878                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3879         else
3880                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3881         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3882         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3883         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3884         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3885         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3886                                      dev_info->rx_queue_offload_capa);
3887         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3888         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3889
3890         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3891                 .rx_thresh = {
3892                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3893                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3894                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3895                 },
3896                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3897                 .rx_drop_en = 0,
3898                 .offloads = 0,
3899         };
3900
3901         dev_info->default_txconf = (struct rte_eth_txconf) {
3902                 .tx_thresh = {
3903                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3904                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3905                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3906                 },
3907                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3908                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3909                 .offloads = 0,
3910         };
3911
3912         dev_info->rx_desc_lim = rx_desc_lim;
3913         dev_info->tx_desc_lim = tx_desc_lim;
3914
3915         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3916         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3917         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3918
3919         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3920         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3921                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3922                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3923                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3924
3925         if (hw->mac.type == ixgbe_mac_X540 ||
3926             hw->mac.type == ixgbe_mac_X540_vf ||
3927             hw->mac.type == ixgbe_mac_X550 ||
3928             hw->mac.type == ixgbe_mac_X550_vf) {
3929                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3930         }
3931         if (hw->mac.type == ixgbe_mac_X550) {
3932                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3933                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3934         }
3935
3936         /* Driver-preferred Rx/Tx parameters */
3937         dev_info->default_rxportconf.burst_size = 32;
3938         dev_info->default_txportconf.burst_size = 32;
3939         dev_info->default_rxportconf.nb_queues = 1;
3940         dev_info->default_txportconf.nb_queues = 1;
3941         dev_info->default_rxportconf.ring_size = 256;
3942         dev_info->default_txportconf.ring_size = 256;
3943
3944         return 0;
3945 }
3946
3947 static const uint32_t *
3948 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3949 {
3950         static const uint32_t ptypes[] = {
3951                 /* For non-vec functions,
3952                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3953                  * for vec functions,
3954                  * refers to _recv_raw_pkts_vec().
3955                  */
3956                 RTE_PTYPE_L2_ETHER,
3957                 RTE_PTYPE_L3_IPV4,
3958                 RTE_PTYPE_L3_IPV4_EXT,
3959                 RTE_PTYPE_L3_IPV6,
3960                 RTE_PTYPE_L3_IPV6_EXT,
3961                 RTE_PTYPE_L4_SCTP,
3962                 RTE_PTYPE_L4_TCP,
3963                 RTE_PTYPE_L4_UDP,
3964                 RTE_PTYPE_TUNNEL_IP,
3965                 RTE_PTYPE_INNER_L3_IPV6,
3966                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3967                 RTE_PTYPE_INNER_L4_TCP,
3968                 RTE_PTYPE_INNER_L4_UDP,
3969                 RTE_PTYPE_UNKNOWN
3970         };
3971
3972         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3973             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3974             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3975             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3976                 return ptypes;
3977
3978 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3979         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3980             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3981                 return ptypes;
3982 #endif
3983         return NULL;
3984 }
3985
3986 static int
3987 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3988                      struct rte_eth_dev_info *dev_info)
3989 {
3990         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3992
3993         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3994         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3995         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3996         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3997         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3998         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3999         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
4000         dev_info->max_vfs = pci_dev->max_vfs;
4001         if (hw->mac.type == ixgbe_mac_82598EB)
4002                 dev_info->max_vmdq_pools = ETH_16_POOLS;
4003         else
4004                 dev_info->max_vmdq_pools = ETH_64_POOLS;
4005         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
4006         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
4007                                      dev_info->rx_queue_offload_capa);
4008         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
4009         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
4010         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
4011         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
4012         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
4013
4014         dev_info->default_rxconf = (struct rte_eth_rxconf) {
4015                 .rx_thresh = {
4016                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4017                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4018                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4019                 },
4020                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4021                 .rx_drop_en = 0,
4022                 .offloads = 0,
4023         };
4024
4025         dev_info->default_txconf = (struct rte_eth_txconf) {
4026                 .tx_thresh = {
4027                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4028                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4029                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4030                 },
4031                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4032                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4033                 .offloads = 0,
4034         };
4035
4036         dev_info->rx_desc_lim = rx_desc_lim;
4037         dev_info->tx_desc_lim = tx_desc_lim;
4038
4039         return 0;
4040 }
4041
4042 static int
4043 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4044                    bool *link_up, int wait_to_complete)
4045 {
4046         struct ixgbe_adapter *adapter = container_of(hw,
4047                                                      struct ixgbe_adapter, hw);
4048         struct ixgbe_mbx_info *mbx = &hw->mbx;
4049         struct ixgbe_mac_info *mac = &hw->mac;
4050         uint32_t links_reg, in_msg;
4051         int ret_val = 0;
4052
4053         /* If we were hit with a reset drop the link */
4054         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4055                 mac->get_link_status = true;
4056
4057         if (!mac->get_link_status)
4058                 goto out;
4059
4060         /* if link status is down no point in checking to see if pf is up */
4061         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4062         if (!(links_reg & IXGBE_LINKS_UP))
4063                 goto out;
4064
4065         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4066          * before the link status is correct
4067          */
4068         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4069                 int i;
4070
4071                 for (i = 0; i < 5; i++) {
4072                         rte_delay_us(100);
4073                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4074
4075                         if (!(links_reg & IXGBE_LINKS_UP))
4076                                 goto out;
4077                 }
4078         }
4079
4080         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4081         case IXGBE_LINKS_SPEED_10G_82599:
4082                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4083                 if (hw->mac.type >= ixgbe_mac_X550) {
4084                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4085                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4086                 }
4087                 break;
4088         case IXGBE_LINKS_SPEED_1G_82599:
4089                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4090                 break;
4091         case IXGBE_LINKS_SPEED_100_82599:
4092                 *speed = IXGBE_LINK_SPEED_100_FULL;
4093                 if (hw->mac.type == ixgbe_mac_X550) {
4094                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4095                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4096                 }
4097                 break;
4098         case IXGBE_LINKS_SPEED_10_X550EM_A:
4099                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4100                 /* Since Reserved in older MAC's */
4101                 if (hw->mac.type >= ixgbe_mac_X550)
4102                         *speed = IXGBE_LINK_SPEED_10_FULL;
4103                 break;
4104         default:
4105                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4106         }
4107
4108         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4109                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4110                         mac->get_link_status = true;
4111                 else
4112                         mac->get_link_status = false;
4113
4114                 goto out;
4115         }
4116
4117         /* if the read failed it could just be a mailbox collision, best wait
4118          * until we are called again and don't report an error
4119          */
4120         if (mbx->ops.read(hw, &in_msg, 1, 0))
4121                 goto out;
4122
4123         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4124                 /* msg is not CTS and is NACK we must have lost CTS status */
4125                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4126                         mac->get_link_status = false;
4127                 goto out;
4128         }
4129
4130         /* the pf is talking, if we timed out in the past we reinit */
4131         if (!mbx->timeout) {
4132                 ret_val = -1;
4133                 goto out;
4134         }
4135
4136         /* if we passed all the tests above then the link is up and we no
4137          * longer need to check for link
4138          */
4139         mac->get_link_status = false;
4140
4141 out:
4142         *link_up = !mac->get_link_status;
4143         return ret_val;
4144 }
4145
4146 /*
4147  * If @timeout_ms was 0, it means that it will not return until link complete.
4148  * It returns 1 on complete, return 0 on timeout.
4149  */
4150 static int
4151 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4152 {
4153 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4154         struct ixgbe_adapter *ad = dev->data->dev_private;
4155         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4156
4157         while (rte_atomic32_read(&ad->link_thread_running)) {
4158                 msec_delay(1);
4159                 timeout--;
4160
4161                 if (timeout_ms) {
4162                         if (!timeout)
4163                                 return 0;
4164                 } else if (!timeout) {
4165                         /* It will not return until link complete */
4166                         timeout = WARNING_TIMEOUT;
4167                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4168                 }
4169         }
4170
4171         return 1;
4172 }
4173
4174 static void *
4175 ixgbe_dev_setup_link_thread_handler(void *param)
4176 {
4177         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4178         struct ixgbe_adapter *ad = dev->data->dev_private;
4179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4180         struct ixgbe_interrupt *intr =
4181                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4182         u32 speed;
4183         bool autoneg = false;
4184
4185         pthread_detach(pthread_self());
4186         speed = hw->phy.autoneg_advertised;
4187         if (!speed)
4188                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4189
4190         ixgbe_setup_link(hw, speed, true);
4191
4192         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4193         rte_atomic32_clear(&ad->link_thread_running);
4194         return NULL;
4195 }
4196
4197 /*
4198  * In freebsd environment, nic_uio drivers do not support interrupts,
4199  * rte_intr_callback_register() will fail to register interrupts.
4200  * We can not make link status to change from down to up by interrupt
4201  * callback. So we need to wait for the controller to acquire link
4202  * when ports start.
4203  * It returns 0 on link up.
4204  */
4205 static int
4206 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4207 {
4208 #ifdef RTE_EXEC_ENV_FREEBSD
4209         int err, i;
4210         bool link_up = false;
4211         uint32_t speed = 0;
4212         const int nb_iter = 25;
4213
4214         for (i = 0; i < nb_iter; i++) {
4215                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4216                 if (err)
4217                         return err;
4218                 if (link_up)
4219                         return 0;
4220                 msec_delay(200);
4221         }
4222
4223         return 0;
4224 #else
4225         RTE_SET_USED(hw);
4226         return 0;
4227 #endif
4228 }
4229
4230 /* return 0 means link status changed, -1 means not changed */
4231 int
4232 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4233                             int wait_to_complete, int vf)
4234 {
4235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236         struct ixgbe_adapter *ad = dev->data->dev_private;
4237         struct rte_eth_link link;
4238         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4239         struct ixgbe_interrupt *intr =
4240                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4241         bool link_up;
4242         int diag;
4243         int wait = 1;
4244         u32 esdp_reg;
4245
4246         memset(&link, 0, sizeof(link));
4247         link.link_status = ETH_LINK_DOWN;
4248         link.link_speed = ETH_SPEED_NUM_NONE;
4249         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4250         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4251                         ETH_LINK_SPEED_FIXED);
4252
4253         hw->mac.get_link_status = true;
4254
4255         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4256                 return rte_eth_linkstatus_set(dev, &link);
4257
4258         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4259         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4260                 wait = 0;
4261
4262 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4263 #ifdef RTE_EXEC_ENV_FREEBSD
4264         wait = 1;
4265 #endif
4266
4267         if (vf)
4268                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4269         else
4270                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4271
4272         if (diag != 0) {
4273                 link.link_speed = ETH_SPEED_NUM_100M;
4274                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4275                 return rte_eth_linkstatus_set(dev, &link);
4276         }
4277
4278         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4279                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4280                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4281                         link_up = 0;
4282         }
4283
4284         if (link_up == 0) {
4285                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4286                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4287                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4288                                 /* To avoid race condition between threads, set
4289                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4290                                  * when there is no link thread running.
4291                                  */
4292                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4293                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4294                                         "ixgbe-link-handler",
4295                                         NULL,
4296                                         ixgbe_dev_setup_link_thread_handler,
4297                                         dev) < 0) {
4298                                         PMD_DRV_LOG(ERR,
4299                                                 "Create link thread failed!");
4300                                         rte_atomic32_clear(&ad->link_thread_running);
4301                                 }
4302                         } else {
4303                                 PMD_DRV_LOG(ERR,
4304                                         "Other link thread is running now!");
4305                         }
4306                 }
4307                 return rte_eth_linkstatus_set(dev, &link);
4308         }
4309
4310         link.link_status = ETH_LINK_UP;
4311         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4312
4313         switch (link_speed) {
4314         default:
4315         case IXGBE_LINK_SPEED_UNKNOWN:
4316                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4317                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4318                         link.link_speed = ETH_SPEED_NUM_10M;
4319                 else
4320                         link.link_speed = ETH_SPEED_NUM_100M;
4321                 break;
4322
4323         case IXGBE_LINK_SPEED_100_FULL:
4324                 link.link_speed = ETH_SPEED_NUM_100M;
4325                 break;
4326
4327         case IXGBE_LINK_SPEED_1GB_FULL:
4328                 link.link_speed = ETH_SPEED_NUM_1G;
4329                 break;
4330
4331         case IXGBE_LINK_SPEED_2_5GB_FULL:
4332                 link.link_speed = ETH_SPEED_NUM_2_5G;
4333                 break;
4334
4335         case IXGBE_LINK_SPEED_5GB_FULL:
4336                 link.link_speed = ETH_SPEED_NUM_5G;
4337                 break;
4338
4339         case IXGBE_LINK_SPEED_10GB_FULL:
4340                 link.link_speed = ETH_SPEED_NUM_10G;
4341                 break;
4342         }
4343
4344         return rte_eth_linkstatus_set(dev, &link);
4345 }
4346
4347 static int
4348 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4349 {
4350         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4351 }
4352
4353 static int
4354 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4355 {
4356         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4357 }
4358
4359 static int
4360 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4361 {
4362         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4363         uint32_t fctrl;
4364
4365         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4366         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4367         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4368
4369         return 0;
4370 }
4371
4372 static int
4373 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4374 {
4375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4376         uint32_t fctrl;
4377
4378         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4379         fctrl &= (~IXGBE_FCTRL_UPE);
4380         if (dev->data->all_multicast == 1)
4381                 fctrl |= IXGBE_FCTRL_MPE;
4382         else
4383                 fctrl &= (~IXGBE_FCTRL_MPE);
4384         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4385
4386         return 0;
4387 }
4388
4389 static int
4390 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4391 {
4392         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4393         uint32_t fctrl;
4394
4395         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4396         fctrl |= IXGBE_FCTRL_MPE;
4397         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4398
4399         return 0;
4400 }
4401
4402 static int
4403 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4404 {
4405         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4406         uint32_t fctrl;
4407
4408         if (dev->data->promiscuous == 1)
4409                 return 0; /* must remain in all_multicast mode */
4410
4411         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4412         fctrl &= (~IXGBE_FCTRL_MPE);
4413         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4414
4415         return 0;
4416 }
4417
4418 /**
4419  * It clears the interrupt causes and enables the interrupt.
4420  * It will be called once only during nic initialized.
4421  *
4422  * @param dev
4423  *  Pointer to struct rte_eth_dev.
4424  * @param on
4425  *  Enable or Disable.
4426  *
4427  * @return
4428  *  - On success, zero.
4429  *  - On failure, a negative value.
4430  */
4431 static int
4432 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4433 {
4434         struct ixgbe_interrupt *intr =
4435                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4436
4437         ixgbe_dev_link_status_print(dev);
4438         if (on)
4439                 intr->mask |= IXGBE_EICR_LSC;
4440         else
4441                 intr->mask &= ~IXGBE_EICR_LSC;
4442
4443         return 0;
4444 }
4445
4446 /**
4447  * It clears the interrupt causes and enables the interrupt.
4448  * It will be called once only during nic initialized.
4449  *
4450  * @param dev
4451  *  Pointer to struct rte_eth_dev.
4452  *
4453  * @return
4454  *  - On success, zero.
4455  *  - On failure, a negative value.
4456  */
4457 static int
4458 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4459 {
4460         struct ixgbe_interrupt *intr =
4461                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4462
4463         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4464
4465         return 0;
4466 }
4467
4468 /**
4469  * It clears the interrupt causes and enables the interrupt.
4470  * It will be called once only during nic initialized.
4471  *
4472  * @param dev
4473  *  Pointer to struct rte_eth_dev.
4474  *
4475  * @return
4476  *  - On success, zero.
4477  *  - On failure, a negative value.
4478  */
4479 static int
4480 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4481 {
4482         struct ixgbe_interrupt *intr =
4483                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4484
4485         intr->mask |= IXGBE_EICR_LINKSEC;
4486
4487         return 0;
4488 }
4489
4490 /*
4491  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4492  *
4493  * @param dev
4494  *  Pointer to struct rte_eth_dev.
4495  *
4496  * @return
4497  *  - On success, zero.
4498  *  - On failure, a negative value.
4499  */
4500 static int
4501 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4502 {
4503         uint32_t eicr;
4504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         struct ixgbe_interrupt *intr =
4506                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4507
4508         /* clear all cause mask */
4509         ixgbe_disable_intr(hw);
4510
4511         /* read-on-clear nic registers here */
4512         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4513         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4514
4515         intr->flags = 0;
4516
4517         /* set flag for async link update */
4518         if (eicr & IXGBE_EICR_LSC)
4519                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4520
4521         if (eicr & IXGBE_EICR_MAILBOX)
4522                 intr->flags |= IXGBE_FLAG_MAILBOX;
4523
4524         if (eicr & IXGBE_EICR_LINKSEC)
4525                 intr->flags |= IXGBE_FLAG_MACSEC;
4526
4527         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4528             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4529             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4530                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4531
4532         return 0;
4533 }
4534
4535 /**
4536  * It gets and then prints the link status.
4537  *
4538  * @param dev
4539  *  Pointer to struct rte_eth_dev.
4540  *
4541  * @return
4542  *  - On success, zero.
4543  *  - On failure, a negative value.
4544  */
4545 static void
4546 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4547 {
4548         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4549         struct rte_eth_link link;
4550
4551         rte_eth_linkstatus_get(dev, &link);
4552
4553         if (link.link_status) {
4554                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4555                                         (int)(dev->data->port_id),
4556                                         (unsigned)link.link_speed,
4557                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4558                                         "full-duplex" : "half-duplex");
4559         } else {
4560                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4561                                 (int)(dev->data->port_id));
4562         }
4563         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4564                                 pci_dev->addr.domain,
4565                                 pci_dev->addr.bus,
4566                                 pci_dev->addr.devid,
4567                                 pci_dev->addr.function);
4568 }
4569
4570 /*
4571  * It executes link_update after knowing an interrupt occurred.
4572  *
4573  * @param dev
4574  *  Pointer to struct rte_eth_dev.
4575  *
4576  * @return
4577  *  - On success, zero.
4578  *  - On failure, a negative value.
4579  */
4580 static int
4581 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4582 {
4583         struct ixgbe_interrupt *intr =
4584                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4585         int64_t timeout;
4586         struct ixgbe_hw *hw =
4587                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4588
4589         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4590
4591         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4592                 ixgbe_pf_mbx_process(dev);
4593                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4594         }
4595
4596         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4597                 ixgbe_handle_lasi(hw);
4598                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4599         }
4600
4601         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4602                 struct rte_eth_link link;
4603
4604                 /* get the link status before link update, for predicting later */
4605                 rte_eth_linkstatus_get(dev, &link);
4606
4607                 ixgbe_dev_link_update(dev, 0);
4608
4609                 /* likely to up */
4610                 if (!link.link_status)
4611                         /* handle it 1 sec later, wait it being stable */
4612                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4613                 /* likely to down */
4614                 else
4615                         /* handle it 4 sec later, wait it being stable */
4616                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4617
4618                 ixgbe_dev_link_status_print(dev);
4619                 if (rte_eal_alarm_set(timeout * 1000,
4620                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4621                         PMD_DRV_LOG(ERR, "Error setting alarm");
4622                 else {
4623                         /* remember original mask */
4624                         intr->mask_original = intr->mask;
4625                         /* only disable lsc interrupt */
4626                         intr->mask &= ~IXGBE_EIMS_LSC;
4627                 }
4628         }
4629
4630         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4631         ixgbe_enable_intr(dev);
4632
4633         return 0;
4634 }
4635
4636 /**
4637  * Interrupt handler which shall be registered for alarm callback for delayed
4638  * handling specific interrupt to wait for the stable nic state. As the
4639  * NIC interrupt state is not stable for ixgbe after link is just down,
4640  * it needs to wait 4 seconds to get the stable status.
4641  *
4642  * @param handle
4643  *  Pointer to interrupt handle.
4644  * @param param
4645  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4646  *
4647  * @return
4648  *  void
4649  */
4650 static void
4651 ixgbe_dev_interrupt_delayed_handler(void *param)
4652 {
4653         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4654         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4655         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4656         struct ixgbe_interrupt *intr =
4657                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4658         struct ixgbe_hw *hw =
4659                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4660         uint32_t eicr;
4661
4662         ixgbe_disable_intr(hw);
4663
4664         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4665         if (eicr & IXGBE_EICR_MAILBOX)
4666                 ixgbe_pf_mbx_process(dev);
4667
4668         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4669                 ixgbe_handle_lasi(hw);
4670                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4671         }
4672
4673         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4674                 ixgbe_dev_link_update(dev, 0);
4675                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4676                 ixgbe_dev_link_status_print(dev);
4677                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4678                                               NULL);
4679         }
4680
4681         if (intr->flags & IXGBE_FLAG_MACSEC) {
4682                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4683                                               NULL);
4684                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4685         }
4686
4687         /* restore original mask */
4688         intr->mask = intr->mask_original;
4689         intr->mask_original = 0;
4690
4691         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4692         ixgbe_enable_intr(dev);
4693         rte_intr_ack(intr_handle);
4694 }
4695
4696 /**
4697  * Interrupt handler triggered by NIC  for handling
4698  * specific interrupt.
4699  *
4700  * @param handle
4701  *  Pointer to interrupt handle.
4702  * @param param
4703  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4704  *
4705  * @return
4706  *  void
4707  */
4708 static void
4709 ixgbe_dev_interrupt_handler(void *param)
4710 {
4711         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4712
4713         ixgbe_dev_interrupt_get_status(dev);
4714         ixgbe_dev_interrupt_action(dev);
4715 }
4716
4717 static int
4718 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4719 {
4720         struct ixgbe_hw *hw;
4721
4722         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4723         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4724 }
4725
4726 static int
4727 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4728 {
4729         struct ixgbe_hw *hw;
4730
4731         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4732         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4733 }
4734
4735 static int
4736 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4737 {
4738         struct ixgbe_hw *hw;
4739         uint32_t mflcn_reg;
4740         uint32_t fccfg_reg;
4741         int rx_pause;
4742         int tx_pause;
4743
4744         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4745
4746         fc_conf->pause_time = hw->fc.pause_time;
4747         fc_conf->high_water = hw->fc.high_water[0];
4748         fc_conf->low_water = hw->fc.low_water[0];
4749         fc_conf->send_xon = hw->fc.send_xon;
4750         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4751
4752         /*
4753          * Return rx_pause status according to actual setting of
4754          * MFLCN register.
4755          */
4756         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4757         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4758                 rx_pause = 1;
4759         else
4760                 rx_pause = 0;
4761
4762         /*
4763          * Return tx_pause status according to actual setting of
4764          * FCCFG register.
4765          */
4766         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4767         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4768                 tx_pause = 1;
4769         else
4770                 tx_pause = 0;
4771
4772         if (rx_pause && tx_pause)
4773                 fc_conf->mode = RTE_FC_FULL;
4774         else if (rx_pause)
4775                 fc_conf->mode = RTE_FC_RX_PAUSE;
4776         else if (tx_pause)
4777                 fc_conf->mode = RTE_FC_TX_PAUSE;
4778         else
4779                 fc_conf->mode = RTE_FC_NONE;
4780
4781         return 0;
4782 }
4783
4784 static int
4785 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4786 {
4787         struct ixgbe_hw *hw;
4788         struct ixgbe_adapter *adapter = dev->data->dev_private;
4789         int err;
4790         uint32_t rx_buf_size;
4791         uint32_t max_high_water;
4792         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4793                 ixgbe_fc_none,
4794                 ixgbe_fc_rx_pause,
4795                 ixgbe_fc_tx_pause,
4796                 ixgbe_fc_full
4797         };
4798
4799         PMD_INIT_FUNC_TRACE();
4800
4801         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4802         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4803         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4804
4805         /*
4806          * At least reserve one Ethernet frame for watermark
4807          * high_water/low_water in kilo bytes for ixgbe
4808          */
4809         max_high_water = (rx_buf_size -
4810                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4811         if ((fc_conf->high_water > max_high_water) ||
4812                 (fc_conf->high_water < fc_conf->low_water)) {
4813                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4814                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4815                 return -EINVAL;
4816         }
4817
4818         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4819         hw->fc.pause_time     = fc_conf->pause_time;
4820         hw->fc.high_water[0]  = fc_conf->high_water;
4821         hw->fc.low_water[0]   = fc_conf->low_water;
4822         hw->fc.send_xon       = fc_conf->send_xon;
4823         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4824         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4825
4826         err = ixgbe_flow_ctrl_enable(dev, hw);
4827         if (err < 0) {
4828                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4829                 return -EIO;
4830         }
4831         return err;
4832 }
4833
4834 /**
4835  *  ixgbe_pfc_enable_generic - Enable flow control
4836  *  @hw: pointer to hardware structure
4837  *  @tc_num: traffic class number
4838  *  Enable flow control according to the current settings.
4839  */
4840 static int
4841 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4842 {
4843         int ret_val = 0;
4844         uint32_t mflcn_reg, fccfg_reg;
4845         uint32_t reg;
4846         uint32_t fcrtl, fcrth;
4847         uint8_t i;
4848         uint8_t nb_rx_en;
4849
4850         /* Validate the water mark configuration */
4851         if (!hw->fc.pause_time) {
4852                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4853                 goto out;
4854         }
4855
4856         /* Low water mark of zero causes XOFF floods */
4857         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4858                  /* High/Low water can not be 0 */
4859                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4860                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4861                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4862                         goto out;
4863                 }
4864
4865                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4866                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4867                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4868                         goto out;
4869                 }
4870         }
4871         /* Negotiate the fc mode to use */
4872         ixgbe_fc_autoneg(hw);
4873
4874         /* Disable any previous flow control settings */
4875         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4876         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4877
4878         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4879         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4880
4881         switch (hw->fc.current_mode) {
4882         case ixgbe_fc_none:
4883                 /*
4884                  * If the count of enabled RX Priority Flow control >1,
4885                  * and the TX pause can not be disabled
4886                  */
4887                 nb_rx_en = 0;
4888                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4889                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4890                         if (reg & IXGBE_FCRTH_FCEN)
4891                                 nb_rx_en++;
4892                 }
4893                 if (nb_rx_en > 1)
4894                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4895                 break;
4896         case ixgbe_fc_rx_pause:
4897                 /*
4898                  * Rx Flow control is enabled and Tx Flow control is
4899                  * disabled by software override. Since there really
4900                  * isn't a way to advertise that we are capable of RX
4901                  * Pause ONLY, we will advertise that we support both
4902                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4903                  * disable the adapter's ability to send PAUSE frames.
4904                  */
4905                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4906                 /*
4907                  * If the count of enabled RX Priority Flow control >1,
4908                  * and the TX pause can not be disabled
4909                  */
4910                 nb_rx_en = 0;
4911                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4912                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4913                         if (reg & IXGBE_FCRTH_FCEN)
4914                                 nb_rx_en++;
4915                 }
4916                 if (nb_rx_en > 1)
4917                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4918                 break;
4919         case ixgbe_fc_tx_pause:
4920                 /*
4921                  * Tx Flow control is enabled, and Rx Flow control is
4922                  * disabled by software override.
4923                  */
4924                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4925                 break;
4926         case ixgbe_fc_full:
4927                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4928                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4929                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4930                 break;
4931         default:
4932                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4933                 ret_val = IXGBE_ERR_CONFIG;
4934                 goto out;
4935         }
4936
4937         /* Set 802.3x based flow control settings. */
4938         mflcn_reg |= IXGBE_MFLCN_DPF;
4939         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4940         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4941
4942         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4943         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4944                 hw->fc.high_water[tc_num]) {
4945                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4946                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4947                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4948         } else {
4949                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4950                 /*
4951                  * In order to prevent Tx hangs when the internal Tx
4952                  * switch is enabled we must set the high water mark
4953                  * to the maximum FCRTH value.  This allows the Tx
4954                  * switch to function even under heavy Rx workloads.
4955                  */
4956                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4957         }
4958         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4959
4960         /* Configure pause time (2 TCs per register) */
4961         reg = hw->fc.pause_time * 0x00010001;
4962         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4963                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4964
4965         /* Configure flow control refresh threshold value */
4966         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4967
4968 out:
4969         return ret_val;
4970 }
4971
4972 static int
4973 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4974 {
4975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4977
4978         if (hw->mac.type != ixgbe_mac_82598EB) {
4979                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4980         }
4981         return ret_val;
4982 }
4983
4984 static int
4985 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4986 {
4987         int err;
4988         uint32_t rx_buf_size;
4989         uint32_t max_high_water;
4990         uint8_t tc_num;
4991         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4992         struct ixgbe_hw *hw =
4993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4994         struct ixgbe_dcb_config *dcb_config =
4995                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4996
4997         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4998                 ixgbe_fc_none,
4999                 ixgbe_fc_rx_pause,
5000                 ixgbe_fc_tx_pause,
5001                 ixgbe_fc_full
5002         };
5003
5004         PMD_INIT_FUNC_TRACE();
5005
5006         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
5007         tc_num = map[pfc_conf->priority];
5008         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
5009         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
5010         /*
5011          * At least reserve one Ethernet frame for watermark
5012          * high_water/low_water in kilo bytes for ixgbe
5013          */
5014         max_high_water = (rx_buf_size -
5015                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5016         if ((pfc_conf->fc.high_water > max_high_water) ||
5017             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5018                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5019                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5020                 return -EINVAL;
5021         }
5022
5023         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5024         hw->fc.pause_time = pfc_conf->fc.pause_time;
5025         hw->fc.send_xon = pfc_conf->fc.send_xon;
5026         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5027         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5028
5029         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5030
5031         /* Not negotiated is not an error case */
5032         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5033                 return 0;
5034
5035         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5036         return -EIO;
5037 }
5038
5039 static int
5040 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5041                           struct rte_eth_rss_reta_entry64 *reta_conf,
5042                           uint16_t reta_size)
5043 {
5044         uint16_t i, sp_reta_size;
5045         uint8_t j, mask;
5046         uint32_t reta, r;
5047         uint16_t idx, shift;
5048         struct ixgbe_adapter *adapter = dev->data->dev_private;
5049         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5050         uint32_t reta_reg;
5051
5052         PMD_INIT_FUNC_TRACE();
5053
5054         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5055                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5056                         "NIC.");
5057                 return -ENOTSUP;
5058         }
5059
5060         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5061         if (reta_size != sp_reta_size) {
5062                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5063                         "(%d) doesn't match the number hardware can supported "
5064                         "(%d)", reta_size, sp_reta_size);
5065                 return -EINVAL;
5066         }
5067
5068         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5069                 idx = i / RTE_RETA_GROUP_SIZE;
5070                 shift = i % RTE_RETA_GROUP_SIZE;
5071                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5072                                                 IXGBE_4_BIT_MASK);
5073                 if (!mask)
5074                         continue;
5075                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5076                 if (mask == IXGBE_4_BIT_MASK)
5077                         r = 0;
5078                 else
5079                         r = IXGBE_READ_REG(hw, reta_reg);
5080                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5081                         if (mask & (0x1 << j))
5082                                 reta |= reta_conf[idx].reta[shift + j] <<
5083                                                         (CHAR_BIT * j);
5084                         else
5085                                 reta |= r & (IXGBE_8_BIT_MASK <<
5086                                                 (CHAR_BIT * j));
5087                 }
5088                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5089         }
5090         adapter->rss_reta_updated = 1;
5091
5092         return 0;
5093 }
5094
5095 static int
5096 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5097                          struct rte_eth_rss_reta_entry64 *reta_conf,
5098                          uint16_t reta_size)
5099 {
5100         uint16_t i, sp_reta_size;
5101         uint8_t j, mask;
5102         uint32_t reta;
5103         uint16_t idx, shift;
5104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105         uint32_t reta_reg;
5106
5107         PMD_INIT_FUNC_TRACE();
5108         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5109         if (reta_size != sp_reta_size) {
5110                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5111                         "(%d) doesn't match the number hardware can supported "
5112                         "(%d)", reta_size, sp_reta_size);
5113                 return -EINVAL;
5114         }
5115
5116         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5117                 idx = i / RTE_RETA_GROUP_SIZE;
5118                 shift = i % RTE_RETA_GROUP_SIZE;
5119                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5120                                                 IXGBE_4_BIT_MASK);
5121                 if (!mask)
5122                         continue;
5123
5124                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5125                 reta = IXGBE_READ_REG(hw, reta_reg);
5126                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5127                         if (mask & (0x1 << j))
5128                                 reta_conf[idx].reta[shift + j] =
5129                                         ((reta >> (CHAR_BIT * j)) &
5130                                                 IXGBE_8_BIT_MASK);
5131                 }
5132         }
5133
5134         return 0;
5135 }
5136
5137 static int
5138 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5139                                 uint32_t index, uint32_t pool)
5140 {
5141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142         uint32_t enable_addr = 1;
5143
5144         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5145                              pool, enable_addr);
5146 }
5147
5148 static void
5149 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5150 {
5151         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5152
5153         ixgbe_clear_rar(hw, index);
5154 }
5155
5156 static int
5157 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5158 {
5159         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5160
5161         ixgbe_remove_rar(dev, 0);
5162         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5163
5164         return 0;
5165 }
5166
5167 static bool
5168 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5169 {
5170         if (strcmp(dev->device->driver->name, drv->driver.name))
5171                 return false;
5172
5173         return true;
5174 }
5175
5176 bool
5177 is_ixgbe_supported(struct rte_eth_dev *dev)
5178 {
5179         return is_device_supported(dev, &rte_ixgbe_pmd);
5180 }
5181
5182 static int
5183 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5184 {
5185         uint32_t hlreg0;
5186         uint32_t maxfrs;
5187         struct ixgbe_hw *hw;
5188         struct rte_eth_dev_info dev_info;
5189         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5190         struct rte_eth_dev_data *dev_data = dev->data;
5191         int ret;
5192
5193         ret = ixgbe_dev_info_get(dev, &dev_info);
5194         if (ret != 0)
5195                 return ret;
5196
5197         /* check that mtu is within the allowed range */
5198         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5199                 return -EINVAL;
5200
5201         /* If device is started, refuse mtu that requires the support of
5202          * scattered packets when this feature has not been enabled before.
5203          */
5204         if (dev_data->dev_started && !dev_data->scattered_rx &&
5205             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5206              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5207                 PMD_INIT_LOG(ERR, "Stop port first.");
5208                 return -EINVAL;
5209         }
5210
5211         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5212         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5213
5214         /* switch to jumbo mode if needed */
5215         if (frame_size > RTE_ETHER_MAX_LEN) {
5216                 dev->data->dev_conf.rxmode.offloads |=
5217                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5218                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5219         } else {
5220                 dev->data->dev_conf.rxmode.offloads &=
5221                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5222                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5223         }
5224         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5225
5226         /* update max frame size */
5227         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5228
5229         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5230         maxfrs &= 0x0000FFFF;
5231         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5232         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5233
5234         return 0;
5235 }
5236
5237 /*
5238  * Virtual Function operations
5239  */
5240 static void
5241 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5242 {
5243         struct ixgbe_interrupt *intr =
5244                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5245         struct ixgbe_hw *hw =
5246                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5247
5248         PMD_INIT_FUNC_TRACE();
5249
5250         /* Clear interrupt mask to stop from interrupts being generated */
5251         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5252
5253         IXGBE_WRITE_FLUSH(hw);
5254
5255         /* Clear mask value. */
5256         intr->mask = 0;
5257 }
5258
5259 static void
5260 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5261 {
5262         struct ixgbe_interrupt *intr =
5263                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5264         struct ixgbe_hw *hw =
5265                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5266
5267         PMD_INIT_FUNC_TRACE();
5268
5269         /* VF enable interrupt autoclean */
5270         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5271         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5272         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5273
5274         IXGBE_WRITE_FLUSH(hw);
5275
5276         /* Save IXGBE_VTEIMS value to mask. */
5277         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5278 }
5279
5280 static int
5281 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5282 {
5283         struct rte_eth_conf *conf = &dev->data->dev_conf;
5284         struct ixgbe_adapter *adapter = dev->data->dev_private;
5285
5286         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5287                      dev->data->port_id);
5288
5289         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5290                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5291
5292         /*
5293          * VF has no ability to enable/disable HW CRC
5294          * Keep the persistent behavior the same as Host PF
5295          */
5296 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5297         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5298                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5299                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5300         }
5301 #else
5302         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5303                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5304                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5305         }
5306 #endif
5307
5308         /*
5309          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5310          * allocation or vector Rx preconditions we will reset it.
5311          */
5312         adapter->rx_bulk_alloc_allowed = true;
5313         adapter->rx_vec_allowed = true;
5314
5315         return 0;
5316 }
5317
5318 static int
5319 ixgbevf_dev_start(struct rte_eth_dev *dev)
5320 {
5321         struct ixgbe_hw *hw =
5322                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5323         uint32_t intr_vector = 0;
5324         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5325         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5326
5327         int err, mask = 0;
5328
5329         PMD_INIT_FUNC_TRACE();
5330
5331         /* Stop the link setup handler before resetting the HW. */
5332         ixgbe_dev_wait_setup_link_complete(dev, 0);
5333
5334         err = hw->mac.ops.reset_hw(hw);
5335         if (err) {
5336                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5337                 return err;
5338         }
5339         hw->mac.get_link_status = true;
5340
5341         /* negotiate mailbox API version to use with the PF. */
5342         ixgbevf_negotiate_api(hw);
5343
5344         ixgbevf_dev_tx_init(dev);
5345
5346         /* This can fail when allocating mbufs for descriptor rings */
5347         err = ixgbevf_dev_rx_init(dev);
5348         if (err) {
5349                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5350                 ixgbe_dev_clear_queues(dev);
5351                 return err;
5352         }
5353
5354         /* Set vfta */
5355         ixgbevf_set_vfta_all(dev, 1);
5356
5357         /* Set HW strip */
5358         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5359                 ETH_VLAN_EXTEND_MASK;
5360         err = ixgbevf_vlan_offload_config(dev, mask);
5361         if (err) {
5362                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5363                 ixgbe_dev_clear_queues(dev);
5364                 return err;
5365         }
5366
5367         ixgbevf_dev_rxtx_start(dev);
5368
5369         /* check and configure queue intr-vector mapping */
5370         if (rte_intr_cap_multiple(intr_handle) &&
5371             dev->data->dev_conf.intr_conf.rxq) {
5372                 /* According to datasheet, only vector 0/1/2 can be used,
5373                  * now only one vector is used for Rx queue
5374                  */
5375                 intr_vector = 1;
5376                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5377                         return -1;
5378         }
5379
5380         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5381                 intr_handle->intr_vec =
5382                         rte_zmalloc("intr_vec",
5383                                     dev->data->nb_rx_queues * sizeof(int), 0);
5384                 if (intr_handle->intr_vec == NULL) {
5385                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5386                                      " intr_vec", dev->data->nb_rx_queues);
5387                         return -ENOMEM;
5388                 }
5389         }
5390         ixgbevf_configure_msix(dev);
5391
5392         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5393          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5394          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5395          * is not cleared, it will fail when following rte_intr_enable( ) tries
5396          * to map Rx queue interrupt to other VFIO vectors.
5397          * So clear uio/vfio intr/evevnfd first to avoid failure.
5398          */
5399         rte_intr_disable(intr_handle);
5400
5401         rte_intr_enable(intr_handle);
5402
5403         /* Re-enable interrupt for VF */
5404         ixgbevf_intr_enable(dev);
5405
5406         /*
5407          * Update link status right before return, because it may
5408          * start link configuration process in a separate thread.
5409          */
5410         ixgbevf_dev_link_update(dev, 0);
5411
5412         hw->adapter_stopped = false;
5413
5414         return 0;
5415 }
5416
5417 static void
5418 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5419 {
5420         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5421         struct ixgbe_adapter *adapter = dev->data->dev_private;
5422         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5423         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5424
5425         if (hw->adapter_stopped)
5426                 return;
5427
5428         PMD_INIT_FUNC_TRACE();
5429
5430         ixgbe_dev_wait_setup_link_complete(dev, 0);
5431
5432         ixgbevf_intr_disable(dev);
5433
5434         hw->adapter_stopped = 1;
5435         ixgbe_stop_adapter(hw);
5436
5437         /*
5438           * Clear what we set, but we still keep shadow_vfta to
5439           * restore after device starts
5440           */
5441         ixgbevf_set_vfta_all(dev, 0);
5442
5443         /* Clear stored conf */
5444         dev->data->scattered_rx = 0;
5445
5446         ixgbe_dev_clear_queues(dev);
5447
5448         /* Clean datapath event and queue/vec mapping */
5449         rte_intr_efd_disable(intr_handle);
5450         if (intr_handle->intr_vec != NULL) {
5451                 rte_free(intr_handle->intr_vec);
5452                 intr_handle->intr_vec = NULL;
5453         }
5454
5455         adapter->rss_reta_updated = 0;
5456 }
5457
5458 static void
5459 ixgbevf_dev_close(struct rte_eth_dev *dev)
5460 {
5461         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5462         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5463         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5464
5465         PMD_INIT_FUNC_TRACE();
5466
5467         ixgbe_reset_hw(hw);
5468
5469         ixgbevf_dev_stop(dev);
5470
5471         ixgbe_dev_free_queues(dev);
5472
5473         /**
5474          * Remove the VF MAC address ro ensure
5475          * that the VF traffic goes to the PF
5476          * after stop, close and detach of the VF
5477          **/
5478         ixgbevf_remove_mac_addr(dev, 0);
5479
5480         dev->dev_ops = NULL;
5481         dev->rx_pkt_burst = NULL;
5482         dev->tx_pkt_burst = NULL;
5483
5484         rte_intr_disable(intr_handle);
5485         rte_intr_callback_unregister(intr_handle,
5486                                      ixgbevf_dev_interrupt_handler, dev);
5487 }
5488
5489 /*
5490  * Reset VF device
5491  */
5492 static int
5493 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5494 {
5495         int ret;
5496
5497         ret = eth_ixgbevf_dev_uninit(dev);
5498         if (ret)
5499                 return ret;
5500
5501         ret = eth_ixgbevf_dev_init(dev);
5502
5503         return ret;
5504 }
5505
5506 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5507 {
5508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5509         struct ixgbe_vfta *shadow_vfta =
5510                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5511         int i = 0, j = 0, vfta = 0, mask = 1;
5512
5513         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5514                 vfta = shadow_vfta->vfta[i];
5515                 if (vfta) {
5516                         mask = 1;
5517                         for (j = 0; j < 32; j++) {
5518                                 if (vfta & mask)
5519                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5520                                                        on, false);
5521                                 mask <<= 1;
5522                         }
5523                 }
5524         }
5525
5526 }
5527
5528 static int
5529 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5530 {
5531         struct ixgbe_hw *hw =
5532                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5533         struct ixgbe_vfta *shadow_vfta =
5534                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5535         uint32_t vid_idx = 0;
5536         uint32_t vid_bit = 0;
5537         int ret = 0;
5538
5539         PMD_INIT_FUNC_TRACE();
5540
5541         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5542         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5543         if (ret) {
5544                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5545                 return ret;
5546         }
5547         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5548         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5549
5550         /* Save what we set and retore it after device reset */
5551         if (on)
5552                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5553         else
5554                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5555
5556         return 0;
5557 }
5558
5559 static void
5560 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5561 {
5562         struct ixgbe_hw *hw =
5563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5564         uint32_t ctrl;
5565
5566         PMD_INIT_FUNC_TRACE();
5567
5568         if (queue >= hw->mac.max_rx_queues)
5569                 return;
5570
5571         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5572         if (on)
5573                 ctrl |= IXGBE_RXDCTL_VME;
5574         else
5575                 ctrl &= ~IXGBE_RXDCTL_VME;
5576         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5577
5578         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5579 }
5580
5581 static int
5582 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5583 {
5584         struct ixgbe_rx_queue *rxq;
5585         uint16_t i;
5586         int on = 0;
5587
5588         /* VF function only support hw strip feature, others are not support */
5589         if (mask & ETH_VLAN_STRIP_MASK) {
5590                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5591                         rxq = dev->data->rx_queues[i];
5592                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5593                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5594                 }
5595         }
5596
5597         return 0;
5598 }
5599
5600 static int
5601 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5602 {
5603         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5604
5605         ixgbevf_vlan_offload_config(dev, mask);
5606
5607         return 0;
5608 }
5609
5610 int
5611 ixgbe_vt_check(struct ixgbe_hw *hw)
5612 {
5613         uint32_t reg_val;
5614
5615         /* if Virtualization Technology is enabled */
5616         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5617         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5618                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5619                 return -1;
5620         }
5621
5622         return 0;
5623 }
5624
5625 static uint32_t
5626 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5627 {
5628         uint32_t vector = 0;
5629
5630         switch (hw->mac.mc_filter_type) {
5631         case 0:   /* use bits [47:36] of the address */
5632                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5633                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5634                 break;
5635         case 1:   /* use bits [46:35] of the address */
5636                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5637                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5638                 break;
5639         case 2:   /* use bits [45:34] of the address */
5640                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5641                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5642                 break;
5643         case 3:   /* use bits [43:32] of the address */
5644                 vector = ((uc_addr->addr_bytes[4]) |
5645                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5646                 break;
5647         default:  /* Invalid mc_filter_type */
5648                 break;
5649         }
5650
5651         /* vector can only be 12-bits or boundary will be exceeded */
5652         vector &= 0xFFF;
5653         return vector;
5654 }
5655
5656 static int
5657 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5658                         struct rte_ether_addr *mac_addr, uint8_t on)
5659 {
5660         uint32_t vector;
5661         uint32_t uta_idx;
5662         uint32_t reg_val;
5663         uint32_t uta_shift;
5664         uint32_t rc;
5665         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5666         const uint32_t ixgbe_uta_bit_shift = 5;
5667         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5668         const uint32_t bit1 = 0x1;
5669
5670         struct ixgbe_hw *hw =
5671                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5672         struct ixgbe_uta_info *uta_info =
5673                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5674
5675         /* The UTA table only exists on 82599 hardware and newer */
5676         if (hw->mac.type < ixgbe_mac_82599EB)
5677                 return -ENOTSUP;
5678
5679         vector = ixgbe_uta_vector(hw, mac_addr);
5680         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5681         uta_shift = vector & ixgbe_uta_bit_mask;
5682
5683         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5684         if (rc == on)
5685                 return 0;
5686
5687         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5688         if (on) {
5689                 uta_info->uta_in_use++;
5690                 reg_val |= (bit1 << uta_shift);
5691                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5692         } else {
5693                 uta_info->uta_in_use--;
5694                 reg_val &= ~(bit1 << uta_shift);
5695                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5696         }
5697
5698         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5699
5700         if (uta_info->uta_in_use > 0)
5701                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5702                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5703         else
5704                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5705
5706         return 0;
5707 }
5708
5709 static int
5710 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5711 {
5712         int i;
5713         struct ixgbe_hw *hw =
5714                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5715         struct ixgbe_uta_info *uta_info =
5716                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5717
5718         /* The UTA table only exists on 82599 hardware and newer */
5719         if (hw->mac.type < ixgbe_mac_82599EB)
5720                 return -ENOTSUP;
5721
5722         if (on) {
5723                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5724                         uta_info->uta_shadow[i] = ~0;
5725                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5726                 }
5727         } else {
5728                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5729                         uta_info->uta_shadow[i] = 0;
5730                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5731                 }
5732         }
5733         return 0;
5734
5735 }
5736
5737 uint32_t
5738 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5739 {
5740         uint32_t new_val = orig_val;
5741
5742         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5743                 new_val |= IXGBE_VMOLR_AUPE;
5744         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5745                 new_val |= IXGBE_VMOLR_ROMPE;
5746         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5747                 new_val |= IXGBE_VMOLR_ROPE;
5748         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5749                 new_val |= IXGBE_VMOLR_BAM;
5750         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5751                 new_val |= IXGBE_VMOLR_MPE;
5752
5753         return new_val;
5754 }
5755
5756 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5757 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5758 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5759 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5760 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5761         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5762         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5763
5764 static int
5765 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5766                       struct rte_eth_mirror_conf *mirror_conf,
5767                       uint8_t rule_id, uint8_t on)
5768 {
5769         uint32_t mr_ctl, vlvf;
5770         uint32_t mp_lsb = 0;
5771         uint32_t mv_msb = 0;
5772         uint32_t mv_lsb = 0;
5773         uint32_t mp_msb = 0;
5774         uint8_t i = 0;
5775         int reg_index = 0;
5776         uint64_t vlan_mask = 0;
5777
5778         const uint8_t pool_mask_offset = 32;
5779         const uint8_t vlan_mask_offset = 32;
5780         const uint8_t dst_pool_offset = 8;
5781         const uint8_t rule_mr_offset  = 4;
5782         const uint8_t mirror_rule_mask = 0x0F;
5783
5784         struct ixgbe_mirror_info *mr_info =
5785                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5786         struct ixgbe_hw *hw =
5787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5788         uint8_t mirror_type = 0;
5789
5790         if (ixgbe_vt_check(hw) < 0)
5791                 return -ENOTSUP;
5792
5793         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5794                 return -EINVAL;
5795
5796         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5797                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5798                             mirror_conf->rule_type);
5799                 return -EINVAL;
5800         }
5801
5802         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5803                 mirror_type |= IXGBE_MRCTL_VLME;
5804                 /* Check if vlan id is valid and find conresponding VLAN ID
5805                  * index in VLVF
5806                  */
5807                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5808                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5809                                 /* search vlan id related pool vlan filter
5810                                  * index
5811                                  */
5812                                 reg_index = ixgbe_find_vlvf_slot(
5813                                                 hw,
5814                                                 mirror_conf->vlan.vlan_id[i],
5815                                                 false);
5816                                 if (reg_index < 0)
5817                                         return -EINVAL;
5818                                 vlvf = IXGBE_READ_REG(hw,
5819                                                       IXGBE_VLVF(reg_index));
5820                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5821                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5822                                       mirror_conf->vlan.vlan_id[i]))
5823                                         vlan_mask |= (1ULL << reg_index);
5824                                 else
5825                                         return -EINVAL;
5826                         }
5827                 }
5828
5829                 if (on) {
5830                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5831                         mv_msb = vlan_mask >> vlan_mask_offset;
5832
5833                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5834                                                 mirror_conf->vlan.vlan_mask;
5835                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5836                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5837                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5838                                                 mirror_conf->vlan.vlan_id[i];
5839                         }
5840                 } else {
5841                         mv_lsb = 0;
5842                         mv_msb = 0;
5843                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5844                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5845                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5846                 }
5847         }
5848
5849         /**
5850          * if enable pool mirror, write related pool mask register,if disable
5851          * pool mirror, clear PFMRVM register
5852          */
5853         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5854                 mirror_type |= IXGBE_MRCTL_VPME;
5855                 if (on) {
5856                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5857                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5858                         mr_info->mr_conf[rule_id].pool_mask =
5859                                         mirror_conf->pool_mask;
5860
5861                 } else {
5862                         mp_lsb = 0;
5863                         mp_msb = 0;
5864                         mr_info->mr_conf[rule_id].pool_mask = 0;
5865                 }
5866         }
5867         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5868                 mirror_type |= IXGBE_MRCTL_UPME;
5869         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5870                 mirror_type |= IXGBE_MRCTL_DPME;
5871
5872         /* read  mirror control register and recalculate it */
5873         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5874
5875         if (on) {
5876                 mr_ctl |= mirror_type;
5877                 mr_ctl &= mirror_rule_mask;
5878                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5879         } else {
5880                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5881         }
5882
5883         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5884         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5885
5886         /* write mirrror control  register */
5887         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5888
5889         /* write pool mirrror control  register */
5890         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5891                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5892                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5893                                 mp_msb);
5894         }
5895         /* write VLAN mirrror control  register */
5896         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5897                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5898                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5899                                 mv_msb);
5900         }
5901
5902         return 0;
5903 }
5904
5905 static int
5906 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5907 {
5908         int mr_ctl = 0;
5909         uint32_t lsb_val = 0;
5910         uint32_t msb_val = 0;
5911         const uint8_t rule_mr_offset = 4;
5912
5913         struct ixgbe_hw *hw =
5914                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5915         struct ixgbe_mirror_info *mr_info =
5916                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5917
5918         if (ixgbe_vt_check(hw) < 0)
5919                 return -ENOTSUP;
5920
5921         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5922                 return -EINVAL;
5923
5924         memset(&mr_info->mr_conf[rule_id], 0,
5925                sizeof(struct rte_eth_mirror_conf));
5926
5927         /* clear PFVMCTL register */
5928         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5929
5930         /* clear pool mask register */
5931         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5932         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5933
5934         /* clear vlan mask register */
5935         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5936         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5937
5938         return 0;
5939 }
5940
5941 static int
5942 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5943 {
5944         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5945         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5946         struct ixgbe_interrupt *intr =
5947                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5948         struct ixgbe_hw *hw =
5949                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5950         uint32_t vec = IXGBE_MISC_VEC_ID;
5951
5952         if (rte_intr_allow_others(intr_handle))
5953                 vec = IXGBE_RX_VEC_START;
5954         intr->mask |= (1 << vec);
5955         RTE_SET_USED(queue_id);
5956         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5957
5958         rte_intr_ack(intr_handle);
5959
5960         return 0;
5961 }
5962
5963 static int
5964 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5965 {
5966         struct ixgbe_interrupt *intr =
5967                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5968         struct ixgbe_hw *hw =
5969                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5970         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5971         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5972         uint32_t vec = IXGBE_MISC_VEC_ID;
5973
5974         if (rte_intr_allow_others(intr_handle))
5975                 vec = IXGBE_RX_VEC_START;
5976         intr->mask &= ~(1 << vec);
5977         RTE_SET_USED(queue_id);
5978         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5979
5980         return 0;
5981 }
5982
5983 static int
5984 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5985 {
5986         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5987         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5988         uint32_t mask;
5989         struct ixgbe_hw *hw =
5990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5991         struct ixgbe_interrupt *intr =
5992                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5993
5994         if (queue_id < 16) {
5995                 ixgbe_disable_intr(hw);
5996                 intr->mask |= (1 << queue_id);
5997                 ixgbe_enable_intr(dev);
5998         } else if (queue_id < 32) {
5999                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6000                 mask &= (1 << queue_id);
6001                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6002         } else if (queue_id < 64) {
6003                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6004                 mask &= (1 << (queue_id - 32));
6005                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6006         }
6007         rte_intr_ack(intr_handle);
6008
6009         return 0;
6010 }
6011
6012 static int
6013 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6014 {
6015         uint32_t mask;
6016         struct ixgbe_hw *hw =
6017                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6018         struct ixgbe_interrupt *intr =
6019                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6020
6021         if (queue_id < 16) {
6022                 ixgbe_disable_intr(hw);
6023                 intr->mask &= ~(1 << queue_id);
6024                 ixgbe_enable_intr(dev);
6025         } else if (queue_id < 32) {
6026                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6027                 mask &= ~(1 << queue_id);
6028                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6029         } else if (queue_id < 64) {
6030                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6031                 mask &= ~(1 << (queue_id - 32));
6032                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6033         }
6034
6035         return 0;
6036 }
6037
6038 static void
6039 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6040                      uint8_t queue, uint8_t msix_vector)
6041 {
6042         uint32_t tmp, idx;
6043
6044         if (direction == -1) {
6045                 /* other causes */
6046                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6047                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6048                 tmp &= ~0xFF;
6049                 tmp |= msix_vector;
6050                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6051         } else {
6052                 /* rx or tx cause */
6053                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6054                 idx = ((16 * (queue & 1)) + (8 * direction));
6055                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6056                 tmp &= ~(0xFF << idx);
6057                 tmp |= (msix_vector << idx);
6058                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6059         }
6060 }
6061
6062 /**
6063  * set the IVAR registers, mapping interrupt causes to vectors
6064  * @param hw
6065  *  pointer to ixgbe_hw struct
6066  * @direction
6067  *  0 for Rx, 1 for Tx, -1 for other causes
6068  * @queue
6069  *  queue to map the corresponding interrupt to
6070  * @msix_vector
6071  *  the vector to map to the corresponding queue
6072  */
6073 static void
6074 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6075                    uint8_t queue, uint8_t msix_vector)
6076 {
6077         uint32_t tmp, idx;
6078
6079         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6080         if (hw->mac.type == ixgbe_mac_82598EB) {
6081                 if (direction == -1)
6082                         direction = 0;
6083                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6084                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6085                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6086                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6087                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6088         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6089                         (hw->mac.type == ixgbe_mac_X540) ||
6090                         (hw->mac.type == ixgbe_mac_X550) ||
6091                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6092                 if (direction == -1) {
6093                         /* other causes */
6094                         idx = ((queue & 1) * 8);
6095                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6096                         tmp &= ~(0xFF << idx);
6097                         tmp |= (msix_vector << idx);
6098                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6099                 } else {
6100                         /* rx or tx causes */
6101                         idx = ((16 * (queue & 1)) + (8 * direction));
6102                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6103                         tmp &= ~(0xFF << idx);
6104                         tmp |= (msix_vector << idx);
6105                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6106                 }
6107         }
6108 }
6109
6110 static void
6111 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6112 {
6113         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6114         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6115         struct ixgbe_hw *hw =
6116                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6117         uint32_t q_idx;
6118         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6119         uint32_t base = IXGBE_MISC_VEC_ID;
6120
6121         /* Configure VF other cause ivar */
6122         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6123
6124         /* won't configure msix register if no mapping is done
6125          * between intr vector and event fd.
6126          */
6127         if (!rte_intr_dp_is_en(intr_handle))
6128                 return;
6129
6130         if (rte_intr_allow_others(intr_handle)) {
6131                 base = IXGBE_RX_VEC_START;
6132                 vector_idx = IXGBE_RX_VEC_START;
6133         }
6134
6135         /* Configure all RX queues of VF */
6136         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6137                 /* Force all queue use vector 0,
6138                  * as IXGBE_VF_MAXMSIVECOTR = 1
6139                  */
6140                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6141                 intr_handle->intr_vec[q_idx] = vector_idx;
6142                 if (vector_idx < base + intr_handle->nb_efd - 1)
6143                         vector_idx++;
6144         }
6145
6146         /* As RX queue setting above show, all queues use the vector 0.
6147          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6148          */
6149         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6150                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6151                         | IXGBE_EITR_CNT_WDIS);
6152 }
6153
6154 /**
6155  * Sets up the hardware to properly generate MSI-X interrupts
6156  * @hw
6157  *  board private structure
6158  */
6159 static void
6160 ixgbe_configure_msix(struct rte_eth_dev *dev)
6161 {
6162         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6163         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6164         struct ixgbe_hw *hw =
6165                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6166         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6167         uint32_t vec = IXGBE_MISC_VEC_ID;
6168         uint32_t mask;
6169         uint32_t gpie;
6170
6171         /* won't configure msix register if no mapping is done
6172          * between intr vector and event fd
6173          * but if misx has been enabled already, need to configure
6174          * auto clean, auto mask and throttling.
6175          */
6176         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6177         if (!rte_intr_dp_is_en(intr_handle) &&
6178             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6179                 return;
6180
6181         if (rte_intr_allow_others(intr_handle))
6182                 vec = base = IXGBE_RX_VEC_START;
6183
6184         /* setup GPIE for MSI-x mode */
6185         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6186         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6187                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6188         /* auto clearing and auto setting corresponding bits in EIMS
6189          * when MSI-X interrupt is triggered
6190          */
6191         if (hw->mac.type == ixgbe_mac_82598EB) {
6192                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6193         } else {
6194                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6195                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6196         }
6197         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6198
6199         /* Populate the IVAR table and set the ITR values to the
6200          * corresponding register.
6201          */
6202         if (rte_intr_dp_is_en(intr_handle)) {
6203                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6204                         queue_id++) {
6205                         /* by default, 1:1 mapping */
6206                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6207                         intr_handle->intr_vec[queue_id] = vec;
6208                         if (vec < base + intr_handle->nb_efd - 1)
6209                                 vec++;
6210                 }
6211
6212                 switch (hw->mac.type) {
6213                 case ixgbe_mac_82598EB:
6214                         ixgbe_set_ivar_map(hw, -1,
6215                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6216                                            IXGBE_MISC_VEC_ID);
6217                         break;
6218                 case ixgbe_mac_82599EB:
6219                 case ixgbe_mac_X540:
6220                 case ixgbe_mac_X550:
6221                 case ixgbe_mac_X550EM_x:
6222                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6223                         break;
6224                 default:
6225                         break;
6226                 }
6227         }
6228         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6229                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6230                         | IXGBE_EITR_CNT_WDIS);
6231
6232         /* set up to autoclear timer, and the vectors */
6233         mask = IXGBE_EIMS_ENABLE_MASK;
6234         mask &= ~(IXGBE_EIMS_OTHER |
6235                   IXGBE_EIMS_MAILBOX |
6236                   IXGBE_EIMS_LSC);
6237
6238         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6239 }
6240
6241 int
6242 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6243                            uint16_t queue_idx, uint16_t tx_rate)
6244 {
6245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6246         struct rte_eth_rxmode *rxmode;
6247         uint32_t rf_dec, rf_int;
6248         uint32_t bcnrc_val;
6249         uint16_t link_speed = dev->data->dev_link.link_speed;
6250
6251         if (queue_idx >= hw->mac.max_tx_queues)
6252                 return -EINVAL;
6253
6254         if (tx_rate != 0) {
6255                 /* Calculate the rate factor values to set */
6256                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6257                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6258                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6259
6260                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6261                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6262                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6263                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6264         } else {
6265                 bcnrc_val = 0;
6266         }
6267
6268         rxmode = &dev->data->dev_conf.rxmode;
6269         /*
6270          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6271          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6272          * set as 0x4.
6273          */
6274         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6275             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6276                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6277                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6278         else
6279                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6280                         IXGBE_MMW_SIZE_DEFAULT);
6281
6282         /* Set RTTBCNRC of queue X */
6283         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6284         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6285         IXGBE_WRITE_FLUSH(hw);
6286
6287         return 0;
6288 }
6289
6290 static int
6291 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6292                      __rte_unused uint32_t index,
6293                      __rte_unused uint32_t pool)
6294 {
6295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6296         int diag;
6297
6298         /*
6299          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6300          * operation. Trap this case to avoid exhausting the [very limited]
6301          * set of PF resources used to store VF MAC addresses.
6302          */
6303         if (memcmp(hw->mac.perm_addr, mac_addr,
6304                         sizeof(struct rte_ether_addr)) == 0)
6305                 return -1;
6306         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6307         if (diag != 0)
6308                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6309                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6310                             mac_addr->addr_bytes[0],
6311                             mac_addr->addr_bytes[1],
6312                             mac_addr->addr_bytes[2],
6313                             mac_addr->addr_bytes[3],
6314                             mac_addr->addr_bytes[4],
6315                             mac_addr->addr_bytes[5],
6316                             diag);
6317         return diag;
6318 }
6319
6320 static void
6321 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6322 {
6323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6324         struct rte_ether_addr *perm_addr =
6325                 (struct rte_ether_addr *)hw->mac.perm_addr;
6326         struct rte_ether_addr *mac_addr;
6327         uint32_t i;
6328         int diag;
6329
6330         /*
6331          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6332          * not support the deletion of a given MAC address.
6333          * Instead, it imposes to delete all MAC addresses, then to add again
6334          * all MAC addresses with the exception of the one to be deleted.
6335          */
6336         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6337
6338         /*
6339          * Add again all MAC addresses, with the exception of the deleted one
6340          * and of the permanent MAC address.
6341          */
6342         for (i = 0, mac_addr = dev->data->mac_addrs;
6343              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6344                 /* Skip the deleted MAC address */
6345                 if (i == index)
6346                         continue;
6347                 /* Skip NULL MAC addresses */
6348                 if (rte_is_zero_ether_addr(mac_addr))
6349                         continue;
6350                 /* Skip the permanent MAC address */
6351                 if (memcmp(perm_addr, mac_addr,
6352                                 sizeof(struct rte_ether_addr)) == 0)
6353                         continue;
6354                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6355                 if (diag != 0)
6356                         PMD_DRV_LOG(ERR,
6357                                     "Adding again MAC address "
6358                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6359                                     "diag=%d",
6360                                     mac_addr->addr_bytes[0],
6361                                     mac_addr->addr_bytes[1],
6362                                     mac_addr->addr_bytes[2],
6363                                     mac_addr->addr_bytes[3],
6364                                     mac_addr->addr_bytes[4],
6365                                     mac_addr->addr_bytes[5],
6366                                     diag);
6367         }
6368 }
6369
6370 static int
6371 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6372                         struct rte_ether_addr *addr)
6373 {
6374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6375
6376         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6377
6378         return 0;
6379 }
6380
6381 int
6382 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6383                         struct rte_eth_syn_filter *filter,
6384                         bool add)
6385 {
6386         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6387         struct ixgbe_filter_info *filter_info =
6388                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6389         uint32_t syn_info;
6390         uint32_t synqf;
6391
6392         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6393                 return -EINVAL;
6394
6395         syn_info = filter_info->syn_info;
6396
6397         if (add) {
6398                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6399                         return -EINVAL;
6400                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6401                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6402
6403                 if (filter->hig_pri)
6404                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6405                 else
6406                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6407         } else {
6408                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6409                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6410                         return -ENOENT;
6411                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6412         }
6413
6414         filter_info->syn_info = synqf;
6415         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6416         IXGBE_WRITE_FLUSH(hw);
6417         return 0;
6418 }
6419
6420 static int
6421 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6422                         struct rte_eth_syn_filter *filter)
6423 {
6424         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6425         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6426
6427         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6428                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6429                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6430                 return 0;
6431         }
6432         return -ENOENT;
6433 }
6434
6435 static int
6436 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6437                         enum rte_filter_op filter_op,
6438                         void *arg)
6439 {
6440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6441         int ret;
6442
6443         MAC_TYPE_FILTER_SUP(hw->mac.type);
6444
6445         if (filter_op == RTE_ETH_FILTER_NOP)
6446                 return 0;
6447
6448         if (arg == NULL) {
6449                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6450                             filter_op);
6451                 return -EINVAL;
6452         }
6453
6454         switch (filter_op) {
6455         case RTE_ETH_FILTER_ADD:
6456                 ret = ixgbe_syn_filter_set(dev,
6457                                 (struct rte_eth_syn_filter *)arg,
6458                                 TRUE);
6459                 break;
6460         case RTE_ETH_FILTER_DELETE:
6461                 ret = ixgbe_syn_filter_set(dev,
6462                                 (struct rte_eth_syn_filter *)arg,
6463                                 FALSE);
6464                 break;
6465         case RTE_ETH_FILTER_GET:
6466                 ret = ixgbe_syn_filter_get(dev,
6467                                 (struct rte_eth_syn_filter *)arg);
6468                 break;
6469         default:
6470                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6471                 ret = -EINVAL;
6472                 break;
6473         }
6474
6475         return ret;
6476 }
6477
6478
6479 static inline enum ixgbe_5tuple_protocol
6480 convert_protocol_type(uint8_t protocol_value)
6481 {
6482         if (protocol_value == IPPROTO_TCP)
6483                 return IXGBE_FILTER_PROTOCOL_TCP;
6484         else if (protocol_value == IPPROTO_UDP)
6485                 return IXGBE_FILTER_PROTOCOL_UDP;
6486         else if (protocol_value == IPPROTO_SCTP)
6487                 return IXGBE_FILTER_PROTOCOL_SCTP;
6488         else
6489                 return IXGBE_FILTER_PROTOCOL_NONE;
6490 }
6491
6492 /* inject a 5-tuple filter to HW */
6493 static inline void
6494 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6495                            struct ixgbe_5tuple_filter *filter)
6496 {
6497         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6498         int i;
6499         uint32_t ftqf, sdpqf;
6500         uint32_t l34timir = 0;
6501         uint8_t mask = 0xff;
6502
6503         i = filter->index;
6504
6505         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6506                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6507         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6508
6509         ftqf = (uint32_t)(filter->filter_info.proto &
6510                 IXGBE_FTQF_PROTOCOL_MASK);
6511         ftqf |= (uint32_t)((filter->filter_info.priority &
6512                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6513         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6514                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6515         if (filter->filter_info.dst_ip_mask == 0)
6516                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6517         if (filter->filter_info.src_port_mask == 0)
6518                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6519         if (filter->filter_info.dst_port_mask == 0)
6520                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6521         if (filter->filter_info.proto_mask == 0)
6522                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6523         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6524         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6525         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6526
6527         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6528         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6529         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6530         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6531
6532         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6533         l34timir |= (uint32_t)(filter->queue <<
6534                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6535         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6536 }
6537
6538 /*
6539  * add a 5tuple filter
6540  *
6541  * @param
6542  * dev: Pointer to struct rte_eth_dev.
6543  * index: the index the filter allocates.
6544  * filter: ponter to the filter that will be added.
6545  * rx_queue: the queue id the filter assigned to.
6546  *
6547  * @return
6548  *    - On success, zero.
6549  *    - On failure, a negative value.
6550  */
6551 static int
6552 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6553                         struct ixgbe_5tuple_filter *filter)
6554 {
6555         struct ixgbe_filter_info *filter_info =
6556                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6557         int i, idx, shift;
6558
6559         /*
6560          * look for an unused 5tuple filter index,
6561          * and insert the filter to list.
6562          */
6563         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6564                 idx = i / (sizeof(uint32_t) * NBBY);
6565                 shift = i % (sizeof(uint32_t) * NBBY);
6566                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6567                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6568                         filter->index = i;
6569                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6570                                           filter,
6571                                           entries);
6572                         break;
6573                 }
6574         }
6575         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6576                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6577                 return -ENOSYS;
6578         }
6579
6580         ixgbe_inject_5tuple_filter(dev, filter);
6581
6582         return 0;
6583 }
6584
6585 /*
6586  * remove a 5tuple filter
6587  *
6588  * @param
6589  * dev: Pointer to struct rte_eth_dev.
6590  * filter: the pointer of the filter will be removed.
6591  */
6592 static void
6593 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6594                         struct ixgbe_5tuple_filter *filter)
6595 {
6596         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6597         struct ixgbe_filter_info *filter_info =
6598                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6599         uint16_t index = filter->index;
6600
6601         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6602                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6603         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6604         rte_free(filter);
6605
6606         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6607         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6608         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6609         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6610         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6611 }
6612
6613 static int
6614 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6615 {
6616         struct ixgbe_hw *hw;
6617         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6618         struct rte_eth_dev_data *dev_data = dev->data;
6619
6620         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6621
6622         if (mtu < RTE_ETHER_MIN_MTU ||
6623                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6624                 return -EINVAL;
6625
6626         /* If device is started, refuse mtu that requires the support of
6627          * scattered packets when this feature has not been enabled before.
6628          */
6629         if (dev_data->dev_started && !dev_data->scattered_rx &&
6630             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6631              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6632                 PMD_INIT_LOG(ERR, "Stop port first.");
6633                 return -EINVAL;
6634         }
6635
6636         /*
6637          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6638          * request of the version 2.0 of the mailbox API.
6639          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6640          * of the mailbox API.
6641          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6642          * prior to 3.11.33 which contains the following change:
6643          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6644          */
6645         ixgbevf_rlpml_set_vf(hw, max_frame);
6646
6647         /* update max frame size */
6648         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6649         return 0;
6650 }
6651
6652 static inline struct ixgbe_5tuple_filter *
6653 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6654                         struct ixgbe_5tuple_filter_info *key)
6655 {
6656         struct ixgbe_5tuple_filter *it;
6657
6658         TAILQ_FOREACH(it, filter_list, entries) {
6659                 if (memcmp(key, &it->filter_info,
6660                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6661                         return it;
6662                 }
6663         }
6664         return NULL;
6665 }
6666
6667 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6668 static inline int
6669 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6670                         struct ixgbe_5tuple_filter_info *filter_info)
6671 {
6672         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6673                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6674                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6675                 return -EINVAL;
6676
6677         switch (filter->dst_ip_mask) {
6678         case UINT32_MAX:
6679                 filter_info->dst_ip_mask = 0;
6680                 filter_info->dst_ip = filter->dst_ip;
6681                 break;
6682         case 0:
6683                 filter_info->dst_ip_mask = 1;
6684                 break;
6685         default:
6686                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6687                 return -EINVAL;
6688         }
6689
6690         switch (filter->src_ip_mask) {
6691         case UINT32_MAX:
6692                 filter_info->src_ip_mask = 0;
6693                 filter_info->src_ip = filter->src_ip;
6694                 break;
6695         case 0:
6696                 filter_info->src_ip_mask = 1;
6697                 break;
6698         default:
6699                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6700                 return -EINVAL;
6701         }
6702
6703         switch (filter->dst_port_mask) {
6704         case UINT16_MAX:
6705                 filter_info->dst_port_mask = 0;
6706                 filter_info->dst_port = filter->dst_port;
6707                 break;
6708         case 0:
6709                 filter_info->dst_port_mask = 1;
6710                 break;
6711         default:
6712                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6713                 return -EINVAL;
6714         }
6715
6716         switch (filter->src_port_mask) {
6717         case UINT16_MAX:
6718                 filter_info->src_port_mask = 0;
6719                 filter_info->src_port = filter->src_port;
6720                 break;
6721         case 0:
6722                 filter_info->src_port_mask = 1;
6723                 break;
6724         default:
6725                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6726                 return -EINVAL;
6727         }
6728
6729         switch (filter->proto_mask) {
6730         case UINT8_MAX:
6731                 filter_info->proto_mask = 0;
6732                 filter_info->proto =
6733                         convert_protocol_type(filter->proto);
6734                 break;
6735         case 0:
6736                 filter_info->proto_mask = 1;
6737                 break;
6738         default:
6739                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6740                 return -EINVAL;
6741         }
6742
6743         filter_info->priority = (uint8_t)filter->priority;
6744         return 0;
6745 }
6746
6747 /*
6748  * add or delete a ntuple filter
6749  *
6750  * @param
6751  * dev: Pointer to struct rte_eth_dev.
6752  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6753  * add: if true, add filter, if false, remove filter
6754  *
6755  * @return
6756  *    - On success, zero.
6757  *    - On failure, a negative value.
6758  */
6759 int
6760 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6761                         struct rte_eth_ntuple_filter *ntuple_filter,
6762                         bool add)
6763 {
6764         struct ixgbe_filter_info *filter_info =
6765                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6766         struct ixgbe_5tuple_filter_info filter_5tuple;
6767         struct ixgbe_5tuple_filter *filter;
6768         int ret;
6769
6770         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6771                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6772                 return -EINVAL;
6773         }
6774
6775         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6776         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6777         if (ret < 0)
6778                 return ret;
6779
6780         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6781                                          &filter_5tuple);
6782         if (filter != NULL && add) {
6783                 PMD_DRV_LOG(ERR, "filter exists.");
6784                 return -EEXIST;
6785         }
6786         if (filter == NULL && !add) {
6787                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6788                 return -ENOENT;
6789         }
6790
6791         if (add) {
6792                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6793                                 sizeof(struct ixgbe_5tuple_filter), 0);
6794                 if (filter == NULL)
6795                         return -ENOMEM;
6796                 rte_memcpy(&filter->filter_info,
6797                                  &filter_5tuple,
6798                                  sizeof(struct ixgbe_5tuple_filter_info));
6799                 filter->queue = ntuple_filter->queue;
6800                 ret = ixgbe_add_5tuple_filter(dev, filter);
6801                 if (ret < 0) {
6802                         rte_free(filter);
6803                         return ret;
6804                 }
6805         } else
6806                 ixgbe_remove_5tuple_filter(dev, filter);
6807
6808         return 0;
6809 }
6810
6811 /*
6812  * get a ntuple filter
6813  *
6814  * @param
6815  * dev: Pointer to struct rte_eth_dev.
6816  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6817  *
6818  * @return
6819  *    - On success, zero.
6820  *    - On failure, a negative value.
6821  */
6822 static int
6823 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6824                         struct rte_eth_ntuple_filter *ntuple_filter)
6825 {
6826         struct ixgbe_filter_info *filter_info =
6827                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6828         struct ixgbe_5tuple_filter_info filter_5tuple;
6829         struct ixgbe_5tuple_filter *filter;
6830         int ret;
6831
6832         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6833                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6834                 return -EINVAL;
6835         }
6836
6837         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6838         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6839         if (ret < 0)
6840                 return ret;
6841
6842         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6843                                          &filter_5tuple);
6844         if (filter == NULL) {
6845                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6846                 return -ENOENT;
6847         }
6848         ntuple_filter->queue = filter->queue;
6849         return 0;
6850 }
6851
6852 /*
6853  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6854  * @dev: pointer to rte_eth_dev structure
6855  * @filter_op:operation will be taken.
6856  * @arg: a pointer to specific structure corresponding to the filter_op
6857  *
6858  * @return
6859  *    - On success, zero.
6860  *    - On failure, a negative value.
6861  */
6862 static int
6863 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6864                                 enum rte_filter_op filter_op,
6865                                 void *arg)
6866 {
6867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6868         int ret;
6869
6870         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6871
6872         if (filter_op == RTE_ETH_FILTER_NOP)
6873                 return 0;
6874
6875         if (arg == NULL) {
6876                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6877                             filter_op);
6878                 return -EINVAL;
6879         }
6880
6881         switch (filter_op) {
6882         case RTE_ETH_FILTER_ADD:
6883                 ret = ixgbe_add_del_ntuple_filter(dev,
6884                         (struct rte_eth_ntuple_filter *)arg,
6885                         TRUE);
6886                 break;
6887         case RTE_ETH_FILTER_DELETE:
6888                 ret = ixgbe_add_del_ntuple_filter(dev,
6889                         (struct rte_eth_ntuple_filter *)arg,
6890                         FALSE);
6891                 break;
6892         case RTE_ETH_FILTER_GET:
6893                 ret = ixgbe_get_ntuple_filter(dev,
6894                         (struct rte_eth_ntuple_filter *)arg);
6895                 break;
6896         default:
6897                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6898                 ret = -EINVAL;
6899                 break;
6900         }
6901         return ret;
6902 }
6903
6904 int
6905 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6906                         struct rte_eth_ethertype_filter *filter,
6907                         bool add)
6908 {
6909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6910         struct ixgbe_filter_info *filter_info =
6911                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6912         uint32_t etqf = 0;
6913         uint32_t etqs = 0;
6914         int ret;
6915         struct ixgbe_ethertype_filter ethertype_filter;
6916
6917         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6918                 return -EINVAL;
6919
6920         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6921                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6922                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6923                         " ethertype filter.", filter->ether_type);
6924                 return -EINVAL;
6925         }
6926
6927         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6928                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6929                 return -EINVAL;
6930         }
6931         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6932                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6933                 return -EINVAL;
6934         }
6935
6936         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6937         if (ret >= 0 && add) {
6938                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6939                             filter->ether_type);
6940                 return -EEXIST;
6941         }
6942         if (ret < 0 && !add) {
6943                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6944                             filter->ether_type);
6945                 return -ENOENT;
6946         }
6947
6948         if (add) {
6949                 etqf = IXGBE_ETQF_FILTER_EN;
6950                 etqf |= (uint32_t)filter->ether_type;
6951                 etqs |= (uint32_t)((filter->queue <<
6952                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6953                                     IXGBE_ETQS_RX_QUEUE);
6954                 etqs |= IXGBE_ETQS_QUEUE_EN;
6955
6956                 ethertype_filter.ethertype = filter->ether_type;
6957                 ethertype_filter.etqf = etqf;
6958                 ethertype_filter.etqs = etqs;
6959                 ethertype_filter.conf = FALSE;
6960                 ret = ixgbe_ethertype_filter_insert(filter_info,
6961                                                     &ethertype_filter);
6962                 if (ret < 0) {
6963                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6964                         return -ENOSPC;
6965                 }
6966         } else {
6967                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6968                 if (ret < 0)
6969                         return -ENOSYS;
6970         }
6971         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6972         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6973         IXGBE_WRITE_FLUSH(hw);
6974
6975         return 0;
6976 }
6977
6978 static int
6979 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6980                         struct rte_eth_ethertype_filter *filter)
6981 {
6982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6983         struct ixgbe_filter_info *filter_info =
6984                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6985         uint32_t etqf, etqs;
6986         int ret;
6987
6988         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6989         if (ret < 0) {
6990                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6991                             filter->ether_type);
6992                 return -ENOENT;
6993         }
6994
6995         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6996         if (etqf & IXGBE_ETQF_FILTER_EN) {
6997                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6998                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6999                 filter->flags = 0;
7000                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
7001                                IXGBE_ETQS_RX_QUEUE_SHIFT;
7002                 return 0;
7003         }
7004         return -ENOENT;
7005 }
7006
7007 /*
7008  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7009  * @dev: pointer to rte_eth_dev structure
7010  * @filter_op:operation will be taken.
7011  * @arg: a pointer to specific structure corresponding to the filter_op
7012  */
7013 static int
7014 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7015                                 enum rte_filter_op filter_op,
7016                                 void *arg)
7017 {
7018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7019         int ret;
7020
7021         MAC_TYPE_FILTER_SUP(hw->mac.type);
7022
7023         if (filter_op == RTE_ETH_FILTER_NOP)
7024                 return 0;
7025
7026         if (arg == NULL) {
7027                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7028                             filter_op);
7029                 return -EINVAL;
7030         }
7031
7032         switch (filter_op) {
7033         case RTE_ETH_FILTER_ADD:
7034                 ret = ixgbe_add_del_ethertype_filter(dev,
7035                         (struct rte_eth_ethertype_filter *)arg,
7036                         TRUE);
7037                 break;
7038         case RTE_ETH_FILTER_DELETE:
7039                 ret = ixgbe_add_del_ethertype_filter(dev,
7040                         (struct rte_eth_ethertype_filter *)arg,
7041                         FALSE);
7042                 break;
7043         case RTE_ETH_FILTER_GET:
7044                 ret = ixgbe_get_ethertype_filter(dev,
7045                         (struct rte_eth_ethertype_filter *)arg);
7046                 break;
7047         default:
7048                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7049                 ret = -EINVAL;
7050                 break;
7051         }
7052         return ret;
7053 }
7054
7055 static int
7056 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7057                      enum rte_filter_type filter_type,
7058                      enum rte_filter_op filter_op,
7059                      void *arg)
7060 {
7061         int ret = 0;
7062
7063         switch (filter_type) {
7064         case RTE_ETH_FILTER_NTUPLE:
7065                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7066                 break;
7067         case RTE_ETH_FILTER_ETHERTYPE:
7068                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7069                 break;
7070         case RTE_ETH_FILTER_SYN:
7071                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7072                 break;
7073         case RTE_ETH_FILTER_FDIR:
7074                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7075                 break;
7076         case RTE_ETH_FILTER_L2_TUNNEL:
7077                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7078                 break;
7079         case RTE_ETH_FILTER_GENERIC:
7080                 if (filter_op != RTE_ETH_FILTER_GET)
7081                         return -EINVAL;
7082                 *(const void **)arg = &ixgbe_flow_ops;
7083                 break;
7084         default:
7085                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7086                                                         filter_type);
7087                 ret = -EINVAL;
7088                 break;
7089         }
7090
7091         return ret;
7092 }
7093
7094 static u8 *
7095 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7096                         u8 **mc_addr_ptr, u32 *vmdq)
7097 {
7098         u8 *mc_addr;
7099
7100         *vmdq = 0;
7101         mc_addr = *mc_addr_ptr;
7102         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7103         return mc_addr;
7104 }
7105
7106 static int
7107 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7108                           struct rte_ether_addr *mc_addr_set,
7109                           uint32_t nb_mc_addr)
7110 {
7111         struct ixgbe_hw *hw;
7112         u8 *mc_addr_list;
7113
7114         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7115         mc_addr_list = (u8 *)mc_addr_set;
7116         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7117                                          ixgbe_dev_addr_list_itr, TRUE);
7118 }
7119
7120 static uint64_t
7121 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7122 {
7123         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7124         uint64_t systime_cycles;
7125
7126         switch (hw->mac.type) {
7127         case ixgbe_mac_X550:
7128         case ixgbe_mac_X550EM_x:
7129         case ixgbe_mac_X550EM_a:
7130                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7131                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7132                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7133                                 * NSEC_PER_SEC;
7134                 break;
7135         default:
7136                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7137                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7138                                 << 32;
7139         }
7140
7141         return systime_cycles;
7142 }
7143
7144 static uint64_t
7145 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7146 {
7147         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7148         uint64_t rx_tstamp_cycles;
7149
7150         switch (hw->mac.type) {
7151         case ixgbe_mac_X550:
7152         case ixgbe_mac_X550EM_x:
7153         case ixgbe_mac_X550EM_a:
7154                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7155                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7156                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7157                                 * NSEC_PER_SEC;
7158                 break;
7159         default:
7160                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7161                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7162                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7163                                 << 32;
7164         }
7165
7166         return rx_tstamp_cycles;
7167 }
7168
7169 static uint64_t
7170 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7171 {
7172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7173         uint64_t tx_tstamp_cycles;
7174
7175         switch (hw->mac.type) {
7176         case ixgbe_mac_X550:
7177         case ixgbe_mac_X550EM_x:
7178         case ixgbe_mac_X550EM_a:
7179                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7180                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7181                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7182                                 * NSEC_PER_SEC;
7183                 break;
7184         default:
7185                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7186                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7187                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7188                                 << 32;
7189         }
7190
7191         return tx_tstamp_cycles;
7192 }
7193
7194 static void
7195 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7196 {
7197         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7198         struct ixgbe_adapter *adapter = dev->data->dev_private;
7199         struct rte_eth_link link;
7200         uint32_t incval = 0;
7201         uint32_t shift = 0;
7202
7203         /* Get current link speed. */
7204         ixgbe_dev_link_update(dev, 1);
7205         rte_eth_linkstatus_get(dev, &link);
7206
7207         switch (link.link_speed) {
7208         case ETH_SPEED_NUM_100M:
7209                 incval = IXGBE_INCVAL_100;
7210                 shift = IXGBE_INCVAL_SHIFT_100;
7211                 break;
7212         case ETH_SPEED_NUM_1G:
7213                 incval = IXGBE_INCVAL_1GB;
7214                 shift = IXGBE_INCVAL_SHIFT_1GB;
7215                 break;
7216         case ETH_SPEED_NUM_10G:
7217         default:
7218                 incval = IXGBE_INCVAL_10GB;
7219                 shift = IXGBE_INCVAL_SHIFT_10GB;
7220                 break;
7221         }
7222
7223         switch (hw->mac.type) {
7224         case ixgbe_mac_X550:
7225         case ixgbe_mac_X550EM_x:
7226         case ixgbe_mac_X550EM_a:
7227                 /* Independent of link speed. */
7228                 incval = 1;
7229                 /* Cycles read will be interpreted as ns. */
7230                 shift = 0;
7231                 /* Fall-through */
7232         case ixgbe_mac_X540:
7233                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7234                 break;
7235         case ixgbe_mac_82599EB:
7236                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7237                 shift -= IXGBE_INCVAL_SHIFT_82599;
7238                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7239                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7240                 break;
7241         default:
7242                 /* Not supported. */
7243                 return;
7244         }
7245
7246         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7247         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7248         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7249
7250         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7251         adapter->systime_tc.cc_shift = shift;
7252         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7253
7254         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7255         adapter->rx_tstamp_tc.cc_shift = shift;
7256         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7257
7258         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7259         adapter->tx_tstamp_tc.cc_shift = shift;
7260         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7261 }
7262
7263 static int
7264 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7265 {
7266         struct ixgbe_adapter *adapter = dev->data->dev_private;
7267
7268         adapter->systime_tc.nsec += delta;
7269         adapter->rx_tstamp_tc.nsec += delta;
7270         adapter->tx_tstamp_tc.nsec += delta;
7271
7272         return 0;
7273 }
7274
7275 static int
7276 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7277 {
7278         uint64_t ns;
7279         struct ixgbe_adapter *adapter = dev->data->dev_private;
7280
7281         ns = rte_timespec_to_ns(ts);
7282         /* Set the timecounters to a new value. */
7283         adapter->systime_tc.nsec = ns;
7284         adapter->rx_tstamp_tc.nsec = ns;
7285         adapter->tx_tstamp_tc.nsec = ns;
7286
7287         return 0;
7288 }
7289
7290 static int
7291 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7292 {
7293         uint64_t ns, systime_cycles;
7294         struct ixgbe_adapter *adapter = dev->data->dev_private;
7295
7296         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7297         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7298         *ts = rte_ns_to_timespec(ns);
7299
7300         return 0;
7301 }
7302
7303 static int
7304 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7305 {
7306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7307         uint32_t tsync_ctl;
7308         uint32_t tsauxc;
7309
7310         /* Stop the timesync system time. */
7311         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7312         /* Reset the timesync system time value. */
7313         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7314         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7315
7316         /* Enable system time for platforms where it isn't on by default. */
7317         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7318         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7319         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7320
7321         ixgbe_start_timecounters(dev);
7322
7323         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7324         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7325                         (RTE_ETHER_TYPE_1588 |
7326                          IXGBE_ETQF_FILTER_EN |
7327                          IXGBE_ETQF_1588));
7328
7329         /* Enable timestamping of received PTP packets. */
7330         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7331         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7332         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7333
7334         /* Enable timestamping of transmitted PTP packets. */
7335         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7336         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7337         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7338
7339         IXGBE_WRITE_FLUSH(hw);
7340
7341         return 0;
7342 }
7343
7344 static int
7345 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7346 {
7347         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7348         uint32_t tsync_ctl;
7349
7350         /* Disable timestamping of transmitted PTP packets. */
7351         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7352         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7353         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7354
7355         /* Disable timestamping of received PTP packets. */
7356         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7357         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7358         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7359
7360         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7361         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7362
7363         /* Stop incrementating the System Time registers. */
7364         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7365
7366         return 0;
7367 }
7368
7369 static int
7370 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7371                                  struct timespec *timestamp,
7372                                  uint32_t flags __rte_unused)
7373 {
7374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7375         struct ixgbe_adapter *adapter = dev->data->dev_private;
7376         uint32_t tsync_rxctl;
7377         uint64_t rx_tstamp_cycles;
7378         uint64_t ns;
7379
7380         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7381         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7382                 return -EINVAL;
7383
7384         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7385         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7386         *timestamp = rte_ns_to_timespec(ns);
7387
7388         return  0;
7389 }
7390
7391 static int
7392 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7393                                  struct timespec *timestamp)
7394 {
7395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7396         struct ixgbe_adapter *adapter = dev->data->dev_private;
7397         uint32_t tsync_txctl;
7398         uint64_t tx_tstamp_cycles;
7399         uint64_t ns;
7400
7401         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7402         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7403                 return -EINVAL;
7404
7405         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7406         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7407         *timestamp = rte_ns_to_timespec(ns);
7408
7409         return 0;
7410 }
7411
7412 static int
7413 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7414 {
7415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7416         int count = 0;
7417         int g_ind = 0;
7418         const struct reg_info *reg_group;
7419         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7420                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7421
7422         while ((reg_group = reg_set[g_ind++]))
7423                 count += ixgbe_regs_group_count(reg_group);
7424
7425         return count;
7426 }
7427
7428 static int
7429 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7430 {
7431         int count = 0;
7432         int g_ind = 0;
7433         const struct reg_info *reg_group;
7434
7435         while ((reg_group = ixgbevf_regs[g_ind++]))
7436                 count += ixgbe_regs_group_count(reg_group);
7437
7438         return count;
7439 }
7440
7441 static int
7442 ixgbe_get_regs(struct rte_eth_dev *dev,
7443               struct rte_dev_reg_info *regs)
7444 {
7445         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7446         uint32_t *data = regs->data;
7447         int g_ind = 0;
7448         int count = 0;
7449         const struct reg_info *reg_group;
7450         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7451                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7452
7453         if (data == NULL) {
7454                 regs->length = ixgbe_get_reg_length(dev);
7455                 regs->width = sizeof(uint32_t);
7456                 return 0;
7457         }
7458
7459         /* Support only full register dump */
7460         if ((regs->length == 0) ||
7461             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7462                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7463                         hw->device_id;
7464                 while ((reg_group = reg_set[g_ind++]))
7465                         count += ixgbe_read_regs_group(dev, &data[count],
7466                                 reg_group);
7467                 return 0;
7468         }
7469
7470         return -ENOTSUP;
7471 }
7472
7473 static int
7474 ixgbevf_get_regs(struct rte_eth_dev *dev,
7475                 struct rte_dev_reg_info *regs)
7476 {
7477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7478         uint32_t *data = regs->data;
7479         int g_ind = 0;
7480         int count = 0;
7481         const struct reg_info *reg_group;
7482
7483         if (data == NULL) {
7484                 regs->length = ixgbevf_get_reg_length(dev);
7485                 regs->width = sizeof(uint32_t);
7486                 return 0;
7487         }
7488
7489         /* Support only full register dump */
7490         if ((regs->length == 0) ||
7491             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7492                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7493                         hw->device_id;
7494                 while ((reg_group = ixgbevf_regs[g_ind++]))
7495                         count += ixgbe_read_regs_group(dev, &data[count],
7496                                                       reg_group);
7497                 return 0;
7498         }
7499
7500         return -ENOTSUP;
7501 }
7502
7503 static int
7504 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7505 {
7506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507
7508         /* Return unit is byte count */
7509         return hw->eeprom.word_size * 2;
7510 }
7511
7512 static int
7513 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7514                 struct rte_dev_eeprom_info *in_eeprom)
7515 {
7516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7517         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7518         uint16_t *data = in_eeprom->data;
7519         int first, length;
7520
7521         first = in_eeprom->offset >> 1;
7522         length = in_eeprom->length >> 1;
7523         if ((first > hw->eeprom.word_size) ||
7524             ((first + length) > hw->eeprom.word_size))
7525                 return -EINVAL;
7526
7527         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7528
7529         return eeprom->ops.read_buffer(hw, first, length, data);
7530 }
7531
7532 static int
7533 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7534                 struct rte_dev_eeprom_info *in_eeprom)
7535 {
7536         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7537         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7538         uint16_t *data = in_eeprom->data;
7539         int first, length;
7540
7541         first = in_eeprom->offset >> 1;
7542         length = in_eeprom->length >> 1;
7543         if ((first > hw->eeprom.word_size) ||
7544             ((first + length) > hw->eeprom.word_size))
7545                 return -EINVAL;
7546
7547         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7548
7549         return eeprom->ops.write_buffer(hw,  first, length, data);
7550 }
7551
7552 static int
7553 ixgbe_get_module_info(struct rte_eth_dev *dev,
7554                       struct rte_eth_dev_module_info *modinfo)
7555 {
7556         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7557         uint32_t status;
7558         uint8_t sff8472_rev, addr_mode;
7559         bool page_swap = false;
7560
7561         /* Check whether we support SFF-8472 or not */
7562         status = hw->phy.ops.read_i2c_eeprom(hw,
7563                                              IXGBE_SFF_SFF_8472_COMP,
7564                                              &sff8472_rev);
7565         if (status != 0)
7566                 return -EIO;
7567
7568         /* addressing mode is not supported */
7569         status = hw->phy.ops.read_i2c_eeprom(hw,
7570                                              IXGBE_SFF_SFF_8472_SWAP,
7571                                              &addr_mode);
7572         if (status != 0)
7573                 return -EIO;
7574
7575         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7576                 PMD_DRV_LOG(ERR,
7577                             "Address change required to access page 0xA2, "
7578                             "but not supported. Please report the module "
7579                             "type to the driver maintainers.");
7580                 page_swap = true;
7581         }
7582
7583         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7584                 /* We have a SFP, but it does not support SFF-8472 */
7585                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7586                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7587         } else {
7588                 /* We have a SFP which supports a revision of SFF-8472. */
7589                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7590                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7591         }
7592
7593         return 0;
7594 }
7595
7596 static int
7597 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7598                         struct rte_dev_eeprom_info *info)
7599 {
7600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7601         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7602         uint8_t databyte = 0xFF;
7603         uint8_t *data = info->data;
7604         uint32_t i = 0;
7605
7606         if (info->length == 0)
7607                 return -EINVAL;
7608
7609         for (i = info->offset; i < info->offset + info->length; i++) {
7610                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7611                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7612                 else
7613                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7614
7615                 if (status != 0)
7616                         return -EIO;
7617
7618                 data[i - info->offset] = databyte;
7619         }
7620
7621         return 0;
7622 }
7623
7624 uint16_t
7625 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7626         switch (mac_type) {
7627         case ixgbe_mac_X550:
7628         case ixgbe_mac_X550EM_x:
7629         case ixgbe_mac_X550EM_a:
7630                 return ETH_RSS_RETA_SIZE_512;
7631         case ixgbe_mac_X550_vf:
7632         case ixgbe_mac_X550EM_x_vf:
7633         case ixgbe_mac_X550EM_a_vf:
7634                 return ETH_RSS_RETA_SIZE_64;
7635         case ixgbe_mac_X540_vf:
7636         case ixgbe_mac_82599_vf:
7637                 return 0;
7638         default:
7639                 return ETH_RSS_RETA_SIZE_128;
7640         }
7641 }
7642
7643 uint32_t
7644 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7645         switch (mac_type) {
7646         case ixgbe_mac_X550:
7647         case ixgbe_mac_X550EM_x:
7648         case ixgbe_mac_X550EM_a:
7649                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7650                         return IXGBE_RETA(reta_idx >> 2);
7651                 else
7652                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7653         case ixgbe_mac_X550_vf:
7654         case ixgbe_mac_X550EM_x_vf:
7655         case ixgbe_mac_X550EM_a_vf:
7656                 return IXGBE_VFRETA(reta_idx >> 2);
7657         default:
7658                 return IXGBE_RETA(reta_idx >> 2);
7659         }
7660 }
7661
7662 uint32_t
7663 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7664         switch (mac_type) {
7665         case ixgbe_mac_X550_vf:
7666         case ixgbe_mac_X550EM_x_vf:
7667         case ixgbe_mac_X550EM_a_vf:
7668                 return IXGBE_VFMRQC;
7669         default:
7670                 return IXGBE_MRQC;
7671         }
7672 }
7673
7674 uint32_t
7675 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7676         switch (mac_type) {
7677         case ixgbe_mac_X550_vf:
7678         case ixgbe_mac_X550EM_x_vf:
7679         case ixgbe_mac_X550EM_a_vf:
7680                 return IXGBE_VFRSSRK(i);
7681         default:
7682                 return IXGBE_RSSRK(i);
7683         }
7684 }
7685
7686 bool
7687 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7688         switch (mac_type) {
7689         case ixgbe_mac_82599_vf:
7690         case ixgbe_mac_X540_vf:
7691                 return 0;
7692         default:
7693                 return 1;
7694         }
7695 }
7696
7697 static int
7698 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7699                         struct rte_eth_dcb_info *dcb_info)
7700 {
7701         struct ixgbe_dcb_config *dcb_config =
7702                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7703         struct ixgbe_dcb_tc_config *tc;
7704         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7705         uint8_t nb_tcs;
7706         uint8_t i, j;
7707
7708         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7709                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7710         else
7711                 dcb_info->nb_tcs = 1;
7712
7713         tc_queue = &dcb_info->tc_queue;
7714         nb_tcs = dcb_info->nb_tcs;
7715
7716         if (dcb_config->vt_mode) { /* vt is enabled*/
7717                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7718                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7719                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7720                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7721                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7722                         for (j = 0; j < nb_tcs; j++) {
7723                                 tc_queue->tc_rxq[0][j].base = j;
7724                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7725                                 tc_queue->tc_txq[0][j].base = j;
7726                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7727                         }
7728                 } else {
7729                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7730                                 for (j = 0; j < nb_tcs; j++) {
7731                                         tc_queue->tc_rxq[i][j].base =
7732                                                 i * nb_tcs + j;
7733                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7734                                         tc_queue->tc_txq[i][j].base =
7735                                                 i * nb_tcs + j;
7736                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7737                                 }
7738                         }
7739                 }
7740         } else { /* vt is disabled*/
7741                 struct rte_eth_dcb_rx_conf *rx_conf =
7742                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7743                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7744                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7745                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7746                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7747                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7748                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7749                         }
7750                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7751                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7752                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7753                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7754                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7755                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7756                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7757                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7758                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7759                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7760                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7761                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7762                         }
7763                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7764                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7765                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7766                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7767                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7768                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7769                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7770                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7771                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7772                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7773                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7774                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7775                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7776                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7777                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7778                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7779                 }
7780         }
7781         for (i = 0; i < dcb_info->nb_tcs; i++) {
7782                 tc = &dcb_config->tc_config[i];
7783                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7784         }
7785         return 0;
7786 }
7787
7788 /* Update e-tag ether type */
7789 static int
7790 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7791                             uint16_t ether_type)
7792 {
7793         uint32_t etag_etype;
7794
7795         if (hw->mac.type != ixgbe_mac_X550 &&
7796             hw->mac.type != ixgbe_mac_X550EM_x &&
7797             hw->mac.type != ixgbe_mac_X550EM_a) {
7798                 return -ENOTSUP;
7799         }
7800
7801         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7802         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7803         etag_etype |= ether_type;
7804         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7805         IXGBE_WRITE_FLUSH(hw);
7806
7807         return 0;
7808 }
7809
7810 /* Config l2 tunnel ether type */
7811 static int
7812 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7813                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7814 {
7815         int ret = 0;
7816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7817         struct ixgbe_l2_tn_info *l2_tn_info =
7818                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7819
7820         if (l2_tunnel == NULL)
7821                 return -EINVAL;
7822
7823         switch (l2_tunnel->l2_tunnel_type) {
7824         case RTE_L2_TUNNEL_TYPE_E_TAG:
7825                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7826                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7827                 break;
7828         default:
7829                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7830                 ret = -EINVAL;
7831                 break;
7832         }
7833
7834         return ret;
7835 }
7836
7837 /* Enable e-tag tunnel */
7838 static int
7839 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7840 {
7841         uint32_t etag_etype;
7842
7843         if (hw->mac.type != ixgbe_mac_X550 &&
7844             hw->mac.type != ixgbe_mac_X550EM_x &&
7845             hw->mac.type != ixgbe_mac_X550EM_a) {
7846                 return -ENOTSUP;
7847         }
7848
7849         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7850         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7851         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7852         IXGBE_WRITE_FLUSH(hw);
7853
7854         return 0;
7855 }
7856
7857 /* Enable l2 tunnel */
7858 static int
7859 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7860                            enum rte_eth_tunnel_type l2_tunnel_type)
7861 {
7862         int ret = 0;
7863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7864         struct ixgbe_l2_tn_info *l2_tn_info =
7865                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7866
7867         switch (l2_tunnel_type) {
7868         case RTE_L2_TUNNEL_TYPE_E_TAG:
7869                 l2_tn_info->e_tag_en = TRUE;
7870                 ret = ixgbe_e_tag_enable(hw);
7871                 break;
7872         default:
7873                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7874                 ret = -EINVAL;
7875                 break;
7876         }
7877
7878         return ret;
7879 }
7880
7881 /* Disable e-tag tunnel */
7882 static int
7883 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7884 {
7885         uint32_t etag_etype;
7886
7887         if (hw->mac.type != ixgbe_mac_X550 &&
7888             hw->mac.type != ixgbe_mac_X550EM_x &&
7889             hw->mac.type != ixgbe_mac_X550EM_a) {
7890                 return -ENOTSUP;
7891         }
7892
7893         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7894         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7895         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7896         IXGBE_WRITE_FLUSH(hw);
7897
7898         return 0;
7899 }
7900
7901 /* Disable l2 tunnel */
7902 static int
7903 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7904                             enum rte_eth_tunnel_type l2_tunnel_type)
7905 {
7906         int ret = 0;
7907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7908         struct ixgbe_l2_tn_info *l2_tn_info =
7909                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7910
7911         switch (l2_tunnel_type) {
7912         case RTE_L2_TUNNEL_TYPE_E_TAG:
7913                 l2_tn_info->e_tag_en = FALSE;
7914                 ret = ixgbe_e_tag_disable(hw);
7915                 break;
7916         default:
7917                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7918                 ret = -EINVAL;
7919                 break;
7920         }
7921
7922         return ret;
7923 }
7924
7925 static int
7926 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7927                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7928 {
7929         int ret = 0;
7930         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7931         uint32_t i, rar_entries;
7932         uint32_t rar_low, rar_high;
7933
7934         if (hw->mac.type != ixgbe_mac_X550 &&
7935             hw->mac.type != ixgbe_mac_X550EM_x &&
7936             hw->mac.type != ixgbe_mac_X550EM_a) {
7937                 return -ENOTSUP;
7938         }
7939
7940         rar_entries = ixgbe_get_num_rx_addrs(hw);
7941
7942         for (i = 1; i < rar_entries; i++) {
7943                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7944                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7945                 if ((rar_high & IXGBE_RAH_AV) &&
7946                     (rar_high & IXGBE_RAH_ADTYPE) &&
7947                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7948                      l2_tunnel->tunnel_id)) {
7949                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7950                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7951
7952                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7953
7954                         return ret;
7955                 }
7956         }
7957
7958         return ret;
7959 }
7960
7961 static int
7962 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7963                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7964 {
7965         int ret = 0;
7966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7967         uint32_t i, rar_entries;
7968         uint32_t rar_low, rar_high;
7969
7970         if (hw->mac.type != ixgbe_mac_X550 &&
7971             hw->mac.type != ixgbe_mac_X550EM_x &&
7972             hw->mac.type != ixgbe_mac_X550EM_a) {
7973                 return -ENOTSUP;
7974         }
7975
7976         /* One entry for one tunnel. Try to remove potential existing entry. */
7977         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7978
7979         rar_entries = ixgbe_get_num_rx_addrs(hw);
7980
7981         for (i = 1; i < rar_entries; i++) {
7982                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7983                 if (rar_high & IXGBE_RAH_AV) {
7984                         continue;
7985                 } else {
7986                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7987                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7988                         rar_low = l2_tunnel->tunnel_id;
7989
7990                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7991                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7992
7993                         return ret;
7994                 }
7995         }
7996
7997         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7998                      " Please remove a rule before adding a new one.");
7999         return -EINVAL;
8000 }
8001
8002 static inline struct ixgbe_l2_tn_filter *
8003 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
8004                           struct ixgbe_l2_tn_key *key)
8005 {
8006         int ret;
8007
8008         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8009         if (ret < 0)
8010                 return NULL;
8011
8012         return l2_tn_info->hash_map[ret];
8013 }
8014
8015 static inline int
8016 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8017                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8018 {
8019         int ret;
8020
8021         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8022                                &l2_tn_filter->key);
8023
8024         if (ret < 0) {
8025                 PMD_DRV_LOG(ERR,
8026                             "Failed to insert L2 tunnel filter"
8027                             " to hash table %d!",
8028                             ret);
8029                 return ret;
8030         }
8031
8032         l2_tn_info->hash_map[ret] = l2_tn_filter;
8033
8034         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8035
8036         return 0;
8037 }
8038
8039 static inline int
8040 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8041                           struct ixgbe_l2_tn_key *key)
8042 {
8043         int ret;
8044         struct ixgbe_l2_tn_filter *l2_tn_filter;
8045
8046         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8047
8048         if (ret < 0) {
8049                 PMD_DRV_LOG(ERR,
8050                             "No such L2 tunnel filter to delete %d!",
8051                             ret);
8052                 return ret;
8053         }
8054
8055         l2_tn_filter = l2_tn_info->hash_map[ret];
8056         l2_tn_info->hash_map[ret] = NULL;
8057
8058         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8059         rte_free(l2_tn_filter);
8060
8061         return 0;
8062 }
8063
8064 /* Add l2 tunnel filter */
8065 int
8066 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8067                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8068                                bool restore)
8069 {
8070         int ret;
8071         struct ixgbe_l2_tn_info *l2_tn_info =
8072                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8073         struct ixgbe_l2_tn_key key;
8074         struct ixgbe_l2_tn_filter *node;
8075
8076         if (!restore) {
8077                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8078                 key.tn_id = l2_tunnel->tunnel_id;
8079
8080                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8081
8082                 if (node) {
8083                         PMD_DRV_LOG(ERR,
8084                                     "The L2 tunnel filter already exists!");
8085                         return -EINVAL;
8086                 }
8087
8088                 node = rte_zmalloc("ixgbe_l2_tn",
8089                                    sizeof(struct ixgbe_l2_tn_filter),
8090                                    0);
8091                 if (!node)
8092                         return -ENOMEM;
8093
8094                 rte_memcpy(&node->key,
8095                                  &key,
8096                                  sizeof(struct ixgbe_l2_tn_key));
8097                 node->pool = l2_tunnel->pool;
8098                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8099                 if (ret < 0) {
8100                         rte_free(node);
8101                         return ret;
8102                 }
8103         }
8104
8105         switch (l2_tunnel->l2_tunnel_type) {
8106         case RTE_L2_TUNNEL_TYPE_E_TAG:
8107                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8108                 break;
8109         default:
8110                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8111                 ret = -EINVAL;
8112                 break;
8113         }
8114
8115         if ((!restore) && (ret < 0))
8116                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8117
8118         return ret;
8119 }
8120
8121 /* Delete l2 tunnel filter */
8122 int
8123 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8124                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8125 {
8126         int ret;
8127         struct ixgbe_l2_tn_info *l2_tn_info =
8128                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8129         struct ixgbe_l2_tn_key key;
8130
8131         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8132         key.tn_id = l2_tunnel->tunnel_id;
8133         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8134         if (ret < 0)
8135                 return ret;
8136
8137         switch (l2_tunnel->l2_tunnel_type) {
8138         case RTE_L2_TUNNEL_TYPE_E_TAG:
8139                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8140                 break;
8141         default:
8142                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8143                 ret = -EINVAL;
8144                 break;
8145         }
8146
8147         return ret;
8148 }
8149
8150 /**
8151  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8152  * @dev: pointer to rte_eth_dev structure
8153  * @filter_op:operation will be taken.
8154  * @arg: a pointer to specific structure corresponding to the filter_op
8155  */
8156 static int
8157 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8158                                   enum rte_filter_op filter_op,
8159                                   void *arg)
8160 {
8161         int ret;
8162
8163         if (filter_op == RTE_ETH_FILTER_NOP)
8164                 return 0;
8165
8166         if (arg == NULL) {
8167                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8168                             filter_op);
8169                 return -EINVAL;
8170         }
8171
8172         switch (filter_op) {
8173         case RTE_ETH_FILTER_ADD:
8174                 ret = ixgbe_dev_l2_tunnel_filter_add
8175                         (dev,
8176                          (struct rte_eth_l2_tunnel_conf *)arg,
8177                          FALSE);
8178                 break;
8179         case RTE_ETH_FILTER_DELETE:
8180                 ret = ixgbe_dev_l2_tunnel_filter_del
8181                         (dev,
8182                          (struct rte_eth_l2_tunnel_conf *)arg);
8183                 break;
8184         default:
8185                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8186                 ret = -EINVAL;
8187                 break;
8188         }
8189         return ret;
8190 }
8191
8192 static int
8193 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8194 {
8195         int ret = 0;
8196         uint32_t ctrl;
8197         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8198
8199         if (hw->mac.type != ixgbe_mac_X550 &&
8200             hw->mac.type != ixgbe_mac_X550EM_x &&
8201             hw->mac.type != ixgbe_mac_X550EM_a) {
8202                 return -ENOTSUP;
8203         }
8204
8205         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8206         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8207         if (en)
8208                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8209         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8210
8211         return ret;
8212 }
8213
8214 /* Enable l2 tunnel forwarding */
8215 static int
8216 ixgbe_dev_l2_tunnel_forwarding_enable
8217         (struct rte_eth_dev *dev,
8218          enum rte_eth_tunnel_type l2_tunnel_type)
8219 {
8220         struct ixgbe_l2_tn_info *l2_tn_info =
8221                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8222         int ret = 0;
8223
8224         switch (l2_tunnel_type) {
8225         case RTE_L2_TUNNEL_TYPE_E_TAG:
8226                 l2_tn_info->e_tag_fwd_en = TRUE;
8227                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8228                 break;
8229         default:
8230                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8231                 ret = -EINVAL;
8232                 break;
8233         }
8234
8235         return ret;
8236 }
8237
8238 /* Disable l2 tunnel forwarding */
8239 static int
8240 ixgbe_dev_l2_tunnel_forwarding_disable
8241         (struct rte_eth_dev *dev,
8242          enum rte_eth_tunnel_type l2_tunnel_type)
8243 {
8244         struct ixgbe_l2_tn_info *l2_tn_info =
8245                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8246         int ret = 0;
8247
8248         switch (l2_tunnel_type) {
8249         case RTE_L2_TUNNEL_TYPE_E_TAG:
8250                 l2_tn_info->e_tag_fwd_en = FALSE;
8251                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8252                 break;
8253         default:
8254                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8255                 ret = -EINVAL;
8256                 break;
8257         }
8258
8259         return ret;
8260 }
8261
8262 static int
8263 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8264                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8265                              bool en)
8266 {
8267         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8268         int ret = 0;
8269         uint32_t vmtir, vmvir;
8270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8271
8272         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8273                 PMD_DRV_LOG(ERR,
8274                             "VF id %u should be less than %u",
8275                             l2_tunnel->vf_id,
8276                             pci_dev->max_vfs);
8277                 return -EINVAL;
8278         }
8279
8280         if (hw->mac.type != ixgbe_mac_X550 &&
8281             hw->mac.type != ixgbe_mac_X550EM_x &&
8282             hw->mac.type != ixgbe_mac_X550EM_a) {
8283                 return -ENOTSUP;
8284         }
8285
8286         if (en)
8287                 vmtir = l2_tunnel->tunnel_id;
8288         else
8289                 vmtir = 0;
8290
8291         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8292
8293         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8294         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8295         if (en)
8296                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8297         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8298
8299         return ret;
8300 }
8301
8302 /* Enable l2 tunnel tag insertion */
8303 static int
8304 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8305                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8306 {
8307         int ret = 0;
8308
8309         switch (l2_tunnel->l2_tunnel_type) {
8310         case RTE_L2_TUNNEL_TYPE_E_TAG:
8311                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8312                 break;
8313         default:
8314                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8315                 ret = -EINVAL;
8316                 break;
8317         }
8318
8319         return ret;
8320 }
8321
8322 /* Disable l2 tunnel tag insertion */
8323 static int
8324 ixgbe_dev_l2_tunnel_insertion_disable
8325         (struct rte_eth_dev *dev,
8326          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8327 {
8328         int ret = 0;
8329
8330         switch (l2_tunnel->l2_tunnel_type) {
8331         case RTE_L2_TUNNEL_TYPE_E_TAG:
8332                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8333                 break;
8334         default:
8335                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8336                 ret = -EINVAL;
8337                 break;
8338         }
8339
8340         return ret;
8341 }
8342
8343 static int
8344 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8345                              bool en)
8346 {
8347         int ret = 0;
8348         uint32_t qde;
8349         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8350
8351         if (hw->mac.type != ixgbe_mac_X550 &&
8352             hw->mac.type != ixgbe_mac_X550EM_x &&
8353             hw->mac.type != ixgbe_mac_X550EM_a) {
8354                 return -ENOTSUP;
8355         }
8356
8357         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8358         if (en)
8359                 qde |= IXGBE_QDE_STRIP_TAG;
8360         else
8361                 qde &= ~IXGBE_QDE_STRIP_TAG;
8362         qde &= ~IXGBE_QDE_READ;
8363         qde |= IXGBE_QDE_WRITE;
8364         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8365
8366         return ret;
8367 }
8368
8369 /* Enable l2 tunnel tag stripping */
8370 static int
8371 ixgbe_dev_l2_tunnel_stripping_enable
8372         (struct rte_eth_dev *dev,
8373          enum rte_eth_tunnel_type l2_tunnel_type)
8374 {
8375         int ret = 0;
8376
8377         switch (l2_tunnel_type) {
8378         case RTE_L2_TUNNEL_TYPE_E_TAG:
8379                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8380                 break;
8381         default:
8382                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8383                 ret = -EINVAL;
8384                 break;
8385         }
8386
8387         return ret;
8388 }
8389
8390 /* Disable l2 tunnel tag stripping */
8391 static int
8392 ixgbe_dev_l2_tunnel_stripping_disable
8393         (struct rte_eth_dev *dev,
8394          enum rte_eth_tunnel_type l2_tunnel_type)
8395 {
8396         int ret = 0;
8397
8398         switch (l2_tunnel_type) {
8399         case RTE_L2_TUNNEL_TYPE_E_TAG:
8400                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8401                 break;
8402         default:
8403                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8404                 ret = -EINVAL;
8405                 break;
8406         }
8407
8408         return ret;
8409 }
8410
8411 /* Enable/disable l2 tunnel offload functions */
8412 static int
8413 ixgbe_dev_l2_tunnel_offload_set
8414         (struct rte_eth_dev *dev,
8415          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8416          uint32_t mask,
8417          uint8_t en)
8418 {
8419         int ret = 0;
8420
8421         if (l2_tunnel == NULL)
8422                 return -EINVAL;
8423
8424         ret = -EINVAL;
8425         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8426                 if (en)
8427                         ret = ixgbe_dev_l2_tunnel_enable(
8428                                 dev,
8429                                 l2_tunnel->l2_tunnel_type);
8430                 else
8431                         ret = ixgbe_dev_l2_tunnel_disable(
8432                                 dev,
8433                                 l2_tunnel->l2_tunnel_type);
8434         }
8435
8436         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8437                 if (en)
8438                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8439                                 dev,
8440                                 l2_tunnel);
8441                 else
8442                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8443                                 dev,
8444                                 l2_tunnel);
8445         }
8446
8447         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8448                 if (en)
8449                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8450                                 dev,
8451                                 l2_tunnel->l2_tunnel_type);
8452                 else
8453                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8454                                 dev,
8455                                 l2_tunnel->l2_tunnel_type);
8456         }
8457
8458         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8459                 if (en)
8460                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8461                                 dev,
8462                                 l2_tunnel->l2_tunnel_type);
8463                 else
8464                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8465                                 dev,
8466                                 l2_tunnel->l2_tunnel_type);
8467         }
8468
8469         return ret;
8470 }
8471
8472 static int
8473 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8474                         uint16_t port)
8475 {
8476         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8477         IXGBE_WRITE_FLUSH(hw);
8478
8479         return 0;
8480 }
8481
8482 /* There's only one register for VxLAN UDP port.
8483  * So, we cannot add several ports. Will update it.
8484  */
8485 static int
8486 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8487                      uint16_t port)
8488 {
8489         if (port == 0) {
8490                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8491                 return -EINVAL;
8492         }
8493
8494         return ixgbe_update_vxlan_port(hw, port);
8495 }
8496
8497 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8498  * UDP port, it must have a value.
8499  * So, will reset it to the original value 0.
8500  */
8501 static int
8502 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8503                      uint16_t port)
8504 {
8505         uint16_t cur_port;
8506
8507         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8508
8509         if (cur_port != port) {
8510                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8511                 return -EINVAL;
8512         }
8513
8514         return ixgbe_update_vxlan_port(hw, 0);
8515 }
8516
8517 /* Add UDP tunneling port */
8518 static int
8519 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8520                               struct rte_eth_udp_tunnel *udp_tunnel)
8521 {
8522         int ret = 0;
8523         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8524
8525         if (hw->mac.type != ixgbe_mac_X550 &&
8526             hw->mac.type != ixgbe_mac_X550EM_x &&
8527             hw->mac.type != ixgbe_mac_X550EM_a) {
8528                 return -ENOTSUP;
8529         }
8530
8531         if (udp_tunnel == NULL)
8532                 return -EINVAL;
8533
8534         switch (udp_tunnel->prot_type) {
8535         case RTE_TUNNEL_TYPE_VXLAN:
8536                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8537                 break;
8538
8539         case RTE_TUNNEL_TYPE_GENEVE:
8540         case RTE_TUNNEL_TYPE_TEREDO:
8541                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8542                 ret = -EINVAL;
8543                 break;
8544
8545         default:
8546                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8547                 ret = -EINVAL;
8548                 break;
8549         }
8550
8551         return ret;
8552 }
8553
8554 /* Remove UDP tunneling port */
8555 static int
8556 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8557                               struct rte_eth_udp_tunnel *udp_tunnel)
8558 {
8559         int ret = 0;
8560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8561
8562         if (hw->mac.type != ixgbe_mac_X550 &&
8563             hw->mac.type != ixgbe_mac_X550EM_x &&
8564             hw->mac.type != ixgbe_mac_X550EM_a) {
8565                 return -ENOTSUP;
8566         }
8567
8568         if (udp_tunnel == NULL)
8569                 return -EINVAL;
8570
8571         switch (udp_tunnel->prot_type) {
8572         case RTE_TUNNEL_TYPE_VXLAN:
8573                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8574                 break;
8575         case RTE_TUNNEL_TYPE_GENEVE:
8576         case RTE_TUNNEL_TYPE_TEREDO:
8577                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8578                 ret = -EINVAL;
8579                 break;
8580         default:
8581                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8582                 ret = -EINVAL;
8583                 break;
8584         }
8585
8586         return ret;
8587 }
8588
8589 static int
8590 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8591 {
8592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8593         int ret;
8594
8595         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8596         case IXGBE_SUCCESS:
8597                 ret = 0;
8598                 break;
8599         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8600                 ret = -ENOTSUP;
8601                 break;
8602         default:
8603                 ret = -EAGAIN;
8604                 break;
8605         }
8606
8607         return ret;
8608 }
8609
8610 static int
8611 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8612 {
8613         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8614         int ret;
8615
8616         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8617         case IXGBE_SUCCESS:
8618                 ret = 0;
8619                 break;
8620         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8621                 ret = -ENOTSUP;
8622                 break;
8623         default:
8624                 ret = -EAGAIN;
8625                 break;
8626         }
8627
8628         return ret;
8629 }
8630
8631 static int
8632 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8633 {
8634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8635         int ret;
8636         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8637
8638         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8639         case IXGBE_SUCCESS:
8640                 ret = 0;
8641                 break;
8642         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8643                 ret = -ENOTSUP;
8644                 break;
8645         default:
8646                 ret = -EAGAIN;
8647                 break;
8648         }
8649
8650         return ret;
8651 }
8652
8653 static int
8654 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8655 {
8656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8657         int ret;
8658
8659         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8660         case IXGBE_SUCCESS:
8661                 ret = 0;
8662                 break;
8663         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8664                 ret = -ENOTSUP;
8665                 break;
8666         default:
8667                 ret = -EAGAIN;
8668                 break;
8669         }
8670
8671         return ret;
8672 }
8673
8674 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8675 {
8676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8677         u32 in_msg = 0;
8678
8679         /* peek the message first */
8680         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8681
8682         /* PF reset VF event */
8683         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8684                 /* dummy mbx read to ack pf */
8685                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8686                         return;
8687                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8688                                               NULL);
8689         }
8690 }
8691
8692 static int
8693 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8694 {
8695         uint32_t eicr;
8696         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8697         struct ixgbe_interrupt *intr =
8698                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8699         ixgbevf_intr_disable(dev);
8700
8701         /* read-on-clear nic registers here */
8702         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8703         intr->flags = 0;
8704
8705         /* only one misc vector supported - mailbox */
8706         eicr &= IXGBE_VTEICR_MASK;
8707         if (eicr == IXGBE_MISC_VEC_ID)
8708                 intr->flags |= IXGBE_FLAG_MAILBOX;
8709
8710         return 0;
8711 }
8712
8713 static int
8714 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8715 {
8716         struct ixgbe_interrupt *intr =
8717                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8718
8719         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8720                 ixgbevf_mbx_process(dev);
8721                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8722         }
8723
8724         ixgbevf_intr_enable(dev);
8725
8726         return 0;
8727 }
8728
8729 static void
8730 ixgbevf_dev_interrupt_handler(void *param)
8731 {
8732         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8733
8734         ixgbevf_dev_interrupt_get_status(dev);
8735         ixgbevf_dev_interrupt_action(dev);
8736 }
8737
8738 /**
8739  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8740  *  @hw: pointer to hardware structure
8741  *
8742  *  Stops the transmit data path and waits for the HW to internally empty
8743  *  the Tx security block
8744  **/
8745 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8746 {
8747 #define IXGBE_MAX_SECTX_POLL 40
8748
8749         int i;
8750         int sectxreg;
8751
8752         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8753         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8754         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8755         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8756                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8757                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8758                         break;
8759                 /* Use interrupt-safe sleep just in case */
8760                 usec_delay(1000);
8761         }
8762
8763         /* For informational purposes only */
8764         if (i >= IXGBE_MAX_SECTX_POLL)
8765                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8766                          "path fully disabled.  Continuing with init.");
8767
8768         return IXGBE_SUCCESS;
8769 }
8770
8771 /**
8772  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8773  *  @hw: pointer to hardware structure
8774  *
8775  *  Enables the transmit data path.
8776  **/
8777 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8778 {
8779         uint32_t sectxreg;
8780
8781         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8782         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8783         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8784         IXGBE_WRITE_FLUSH(hw);
8785
8786         return IXGBE_SUCCESS;
8787 }
8788
8789 /* restore n-tuple filter */
8790 static inline void
8791 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8792 {
8793         struct ixgbe_filter_info *filter_info =
8794                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8795         struct ixgbe_5tuple_filter *node;
8796
8797         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8798                 ixgbe_inject_5tuple_filter(dev, node);
8799         }
8800 }
8801
8802 /* restore ethernet type filter */
8803 static inline void
8804 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8805 {
8806         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8807         struct ixgbe_filter_info *filter_info =
8808                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8809         int i;
8810
8811         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8812                 if (filter_info->ethertype_mask & (1 << i)) {
8813                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8814                                         filter_info->ethertype_filters[i].etqf);
8815                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8816                                         filter_info->ethertype_filters[i].etqs);
8817                         IXGBE_WRITE_FLUSH(hw);
8818                 }
8819         }
8820 }
8821
8822 /* restore SYN filter */
8823 static inline void
8824 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8825 {
8826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8827         struct ixgbe_filter_info *filter_info =
8828                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8829         uint32_t synqf;
8830
8831         synqf = filter_info->syn_info;
8832
8833         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8834                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8835                 IXGBE_WRITE_FLUSH(hw);
8836         }
8837 }
8838
8839 /* restore L2 tunnel filter */
8840 static inline void
8841 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8842 {
8843         struct ixgbe_l2_tn_info *l2_tn_info =
8844                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8845         struct ixgbe_l2_tn_filter *node;
8846         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8847
8848         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8849                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8850                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8851                 l2_tn_conf.pool           = node->pool;
8852                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8853         }
8854 }
8855
8856 /* restore rss filter */
8857 static inline void
8858 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8859 {
8860         struct ixgbe_filter_info *filter_info =
8861                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8862
8863         if (filter_info->rss_info.conf.queue_num)
8864                 ixgbe_config_rss_filter(dev,
8865                         &filter_info->rss_info, TRUE);
8866 }
8867
8868 static int
8869 ixgbe_filter_restore(struct rte_eth_dev *dev)
8870 {
8871         ixgbe_ntuple_filter_restore(dev);
8872         ixgbe_ethertype_filter_restore(dev);
8873         ixgbe_syn_filter_restore(dev);
8874         ixgbe_fdir_filter_restore(dev);
8875         ixgbe_l2_tn_filter_restore(dev);
8876         ixgbe_rss_filter_restore(dev);
8877
8878         return 0;
8879 }
8880
8881 static void
8882 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8883 {
8884         struct ixgbe_l2_tn_info *l2_tn_info =
8885                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8887
8888         if (l2_tn_info->e_tag_en)
8889                 (void)ixgbe_e_tag_enable(hw);
8890
8891         if (l2_tn_info->e_tag_fwd_en)
8892                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8893
8894         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8895 }
8896
8897 /* remove all the n-tuple filters */
8898 void
8899 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8900 {
8901         struct ixgbe_filter_info *filter_info =
8902                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8903         struct ixgbe_5tuple_filter *p_5tuple;
8904
8905         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8906                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8907 }
8908
8909 /* remove all the ether type filters */
8910 void
8911 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8912 {
8913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8914         struct ixgbe_filter_info *filter_info =
8915                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8916         int i;
8917
8918         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8919                 if (filter_info->ethertype_mask & (1 << i) &&
8920                     !filter_info->ethertype_filters[i].conf) {
8921                         (void)ixgbe_ethertype_filter_remove(filter_info,
8922                                                             (uint8_t)i);
8923                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8924                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8925                         IXGBE_WRITE_FLUSH(hw);
8926                 }
8927         }
8928 }
8929
8930 /* remove the SYN filter */
8931 void
8932 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8933 {
8934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8935         struct ixgbe_filter_info *filter_info =
8936                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8937
8938         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8939                 filter_info->syn_info = 0;
8940
8941                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8942                 IXGBE_WRITE_FLUSH(hw);
8943         }
8944 }
8945
8946 /* remove all the L2 tunnel filters */
8947 int
8948 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8949 {
8950         struct ixgbe_l2_tn_info *l2_tn_info =
8951                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8952         struct ixgbe_l2_tn_filter *l2_tn_filter;
8953         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8954         int ret = 0;
8955
8956         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8957                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8958                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8959                 l2_tn_conf.pool           = l2_tn_filter->pool;
8960                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8961                 if (ret < 0)
8962                         return ret;
8963         }
8964
8965         return 0;
8966 }
8967
8968 void
8969 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8970                                 struct ixgbe_macsec_setting *macsec_setting)
8971 {
8972         struct ixgbe_macsec_setting *macsec =
8973                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8974
8975         macsec->offload_en = macsec_setting->offload_en;
8976         macsec->encrypt_en = macsec_setting->encrypt_en;
8977         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8978 }
8979
8980 void
8981 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8982 {
8983         struct ixgbe_macsec_setting *macsec =
8984                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8985
8986         macsec->offload_en = 0;
8987         macsec->encrypt_en = 0;
8988         macsec->replayprotect_en = 0;
8989 }
8990
8991 void
8992 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8993                                 struct ixgbe_macsec_setting *macsec_setting)
8994 {
8995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8996         uint32_t ctrl;
8997         uint8_t en = macsec_setting->encrypt_en;
8998         uint8_t rp = macsec_setting->replayprotect_en;
8999
9000         /**
9001          * Workaround:
9002          * As no ixgbe_disable_sec_rx_path equivalent is
9003          * implemented for tx in the base code, and we are
9004          * not allowed to modify the base code in DPDK, so
9005          * just call the hand-written one directly for now.
9006          * The hardware support has been checked by
9007          * ixgbe_disable_sec_rx_path().
9008          */
9009         ixgbe_disable_sec_tx_path_generic(hw);
9010
9011         /* Enable Ethernet CRC (required by MACsec offload) */
9012         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9013         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9014         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9015
9016         /* Enable the TX and RX crypto engines */
9017         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9018         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9019         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9020
9021         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9022         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9023         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9024
9025         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9026         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9027         ctrl |= 0x3;
9028         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9029
9030         /* Enable SA lookup */
9031         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9032         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9033         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9034                      IXGBE_LSECTXCTRL_AUTH;
9035         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9036         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9037         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9038         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9039
9040         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9041         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9042         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9043         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9044         if (rp)
9045                 ctrl |= IXGBE_LSECRXCTRL_RP;
9046         else
9047                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9048         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9049
9050         /* Start the data paths */
9051         ixgbe_enable_sec_rx_path(hw);
9052         /**
9053          * Workaround:
9054          * As no ixgbe_enable_sec_rx_path equivalent is
9055          * implemented for tx in the base code, and we are
9056          * not allowed to modify the base code in DPDK, so
9057          * just call the hand-written one directly for now.
9058          */
9059         ixgbe_enable_sec_tx_path_generic(hw);
9060 }
9061
9062 void
9063 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9064 {
9065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9066         uint32_t ctrl;
9067
9068         /**
9069          * Workaround:
9070          * As no ixgbe_disable_sec_rx_path equivalent is
9071          * implemented for tx in the base code, and we are
9072          * not allowed to modify the base code in DPDK, so
9073          * just call the hand-written one directly for now.
9074          * The hardware support has been checked by
9075          * ixgbe_disable_sec_rx_path().
9076          */
9077         ixgbe_disable_sec_tx_path_generic(hw);
9078
9079         /* Disable the TX and RX crypto engines */
9080         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9081         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9082         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9083
9084         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9085         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9086         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9087
9088         /* Disable SA lookup */
9089         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9090         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9091         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9092         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9093
9094         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9095         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9096         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9097         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9098
9099         /* Start the data paths */
9100         ixgbe_enable_sec_rx_path(hw);
9101         /**
9102          * Workaround:
9103          * As no ixgbe_enable_sec_rx_path equivalent is
9104          * implemented for tx in the base code, and we are
9105          * not allowed to modify the base code in DPDK, so
9106          * just call the hand-written one directly for now.
9107          */
9108         ixgbe_enable_sec_tx_path_generic(hw);
9109 }
9110
9111 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9112 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9113 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9114 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9115 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9116 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9117 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9118                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9119
9120 RTE_INIT(ixgbe_init_log)
9121 {
9122         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9123         if (ixgbe_logtype_init >= 0)
9124                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9125         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9126         if (ixgbe_logtype_driver >= 0)
9127                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9128 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9129         ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9130         if (ixgbe_logtype_rx >= 0)
9131                 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9132 #endif
9133
9134 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9135         ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9136         if (ixgbe_logtype_tx >= 0)
9137                 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9138 #endif
9139
9140 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9141         ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9142         if (ixgbe_logtype_tx_free >= 0)
9143                 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);
9144 #endif
9145 }