drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 318                      enum rte_filter_type filter_type,
 319                      enum rte_filter_op filter_op,
 320                      void *arg);
 321 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 322
 323 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 324                                       struct rte_ether_addr *mc_addr_set,
 325                                       uint32_t nb_mc_addr);
 326 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                    struct rte_eth_dcb_info *dcb_info);
 328
 329 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 330 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 331                             struct rte_dev_reg_info *regs);
 332 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 334                                 struct rte_dev_eeprom_info *eeprom);
 335 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 336                                 struct rte_dev_eeprom_info *eeprom);
 337
 338 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 339                                  struct rte_eth_dev_module_info *modinfo);
 340 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 341                                    struct rte_dev_eeprom_info *info);
 342
 343 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 344 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 345                                 struct rte_dev_reg_info *regs);
 346
 347 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 348 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 349 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 350                                             struct timespec *timestamp,
 351                                             uint32_t flags);
 352 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp);
 354 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 355 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 358                                    const struct timespec *timestamp);
 359 static void ixgbevf_dev_interrupt_handler(void *param);
 360
 361 static int ixgbe_dev_l2_tunnel_eth_type_conf
 362         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 363 static int ixgbe_dev_l2_tunnel_offload_set
 364         (struct rte_eth_dev *dev,
 365          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 366          uint32_t mask,
 367          uint8_t en);
 368 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 369                                              enum rte_filter_op filter_op,
 370                                              void *arg);
 371
 372 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 373                                          struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 375                                          struct rte_eth_udp_tunnel *udp_tunnel);
 376 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 377 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 378 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 379
 380 /*
 381  * Define VF Stats MACRO for Non "cleared on read" register
 382  */
 383 #define UPDATE_VF_STAT(reg, last, cur)                          \
 384 {                                                               \
 385         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 386         cur += (latest - last) & UINT_MAX;                      \
 387         last = latest;                                          \
 388 }
 389
 390 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 391 {                                                                \
 392         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 393         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 394         u64 latest = ((new_msb << 32) | new_lsb);                \
 395         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 396         last = latest;                                           \
 397 }
 398
 399 #define IXGBE_SET_HWSTRIP(h, q) do {\
 400                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 402                 (h)->bitmap[idx] |= 1 << bit;\
 403         } while (0)
 404
 405 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 406                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 407                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 408                 (h)->bitmap[idx] &= ~(1 << bit);\
 409         } while (0)
 410
 411 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 412                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 413                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 414                 (r) = (h)->bitmap[idx] >> bit & 1;\
 415         } while (0)
 416
 417 /*
 418  * The set of PCI devices this driver supports
 419  */
 420 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 469 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 471 #endif
 472         { .vendor_id = 0, /* sentinel */ },
 473 };
 474
 475 /*
 476  * The set of PCI devices this driver supports (for 82599 VF)
 477  */
 478 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 489         { .vendor_id = 0, /* sentinel */ },
 490 };
 491
 492 static const struct rte_eth_desc_lim rx_desc_lim = {
 493         .nb_max = IXGBE_MAX_RING_DESC,
 494         .nb_min = IXGBE_MIN_RING_DESC,
 495         .nb_align = IXGBE_RXD_ALIGN,
 496 };
 497
 498 static const struct rte_eth_desc_lim tx_desc_lim = {
 499         .nb_max = IXGBE_MAX_RING_DESC,
 500         .nb_min = IXGBE_MIN_RING_DESC,
 501         .nb_align = IXGBE_TXD_ALIGN,
 502         .nb_seg_max = IXGBE_TX_MAX_SEG,
 503         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 504 };
 505
 506 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 507         .dev_configure        = ixgbe_dev_configure,
 508         .dev_start            = ixgbe_dev_start,
 509         .dev_stop             = ixgbe_dev_stop,
 510         .dev_set_link_up    = ixgbe_dev_set_link_up,
 511         .dev_set_link_down  = ixgbe_dev_set_link_down,
 512         .dev_close            = ixgbe_dev_close,
 513         .dev_reset            = ixgbe_dev_reset,
 514         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 515         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 516         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 517         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 518         .link_update          = ixgbe_dev_link_update,
 519         .stats_get            = ixgbe_dev_stats_get,
 520         .xstats_get           = ixgbe_dev_xstats_get,
 521         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 522         .stats_reset          = ixgbe_dev_stats_reset,
 523         .xstats_reset         = ixgbe_dev_xstats_reset,
 524         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 525         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 526         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 527         .fw_version_get       = ixgbe_fw_version_get,
 528         .dev_infos_get        = ixgbe_dev_info_get,
 529         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 530         .mtu_set              = ixgbe_dev_mtu_set,
 531         .vlan_filter_set      = ixgbe_vlan_filter_set,
 532         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 533         .vlan_offload_set     = ixgbe_vlan_offload_set,
 534         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 535         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 536         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 537         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 538         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 539         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 540         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 541         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 542         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 543         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 544         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 545         .dev_led_on           = ixgbe_dev_led_on,
 546         .dev_led_off          = ixgbe_dev_led_off,
 547         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 548         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 549         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 550         .mac_addr_add         = ixgbe_add_rar,
 551         .mac_addr_remove      = ixgbe_remove_rar,
 552         .mac_addr_set         = ixgbe_set_default_mac_addr,
 553         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 554         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 555         .mirror_rule_set      = ixgbe_mirror_rule_set,
 556         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 557         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 558         .reta_update          = ixgbe_dev_rss_reta_update,
 559         .reta_query           = ixgbe_dev_rss_reta_query,
 560         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 561         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 562         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 563         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 564         .rxq_info_get         = ixgbe_rxq_info_get,
 565         .txq_info_get         = ixgbe_txq_info_get,
 566         .timesync_enable      = ixgbe_timesync_enable,
 567         .timesync_disable     = ixgbe_timesync_disable,
 568         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 569         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 570         .get_reg              = ixgbe_get_regs,
 571         .get_eeprom_length    = ixgbe_get_eeprom_length,
 572         .get_eeprom           = ixgbe_get_eeprom,
 573         .set_eeprom           = ixgbe_set_eeprom,
 574         .get_module_info      = ixgbe_get_module_info,
 575         .get_module_eeprom    = ixgbe_get_module_eeprom,
 576         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 577         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 578         .timesync_read_time   = ixgbe_timesync_read_time,
 579         .timesync_write_time  = ixgbe_timesync_write_time,
 580         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 581         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 582         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 583         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 584         .tm_ops_get           = ixgbe_tm_ops_get,
 585         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 586 };
 587
 588 /*
 589  * dev_ops for virtual function, bare necessities for basic vf
 590  * operation have been implemented
 591  */
 592 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 593         .dev_configure        = ixgbevf_dev_configure,
 594         .dev_start            = ixgbevf_dev_start,
 595         .dev_stop             = ixgbevf_dev_stop,
 596         .link_update          = ixgbevf_dev_link_update,
 597         .stats_get            = ixgbevf_dev_stats_get,
 598         .xstats_get           = ixgbevf_dev_xstats_get,
 599         .stats_reset          = ixgbevf_dev_stats_reset,
 600         .xstats_reset         = ixgbevf_dev_stats_reset,
 601         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 602         .dev_close            = ixgbevf_dev_close,
 603         .dev_reset            = ixgbevf_dev_reset,
 604         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 605         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 606         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 607         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 608         .dev_infos_get        = ixgbevf_dev_info_get,
 609         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 610         .mtu_set              = ixgbevf_dev_set_mtu,
 611         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 612         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 613         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 614         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 615         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 616         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 617         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 618         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 619         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 620         .mac_addr_add         = ixgbevf_add_mac_addr,
 621         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 622         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 623         .rxq_info_get         = ixgbe_rxq_info_get,
 624         .txq_info_get         = ixgbe_txq_info_get,
 625         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 626         .get_reg              = ixgbevf_get_regs,
 627         .reta_update          = ixgbe_dev_rss_reta_update,
 628         .reta_query           = ixgbe_dev_rss_reta_query,
 629         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 630         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 631         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 632 };
 633
 634 /* store statistics names and its offset in stats structure */
 635 struct rte_ixgbe_xstats_name_off {
 636         char name[RTE_ETH_XSTATS_NAME_SIZE];
 637         unsigned offset;
 638 };
 639
 640 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 641         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 642         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 643         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 644         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 645         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 646         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 647         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 648         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 649         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 650         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 651         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 652         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 653         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 654         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 655         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 656                 prc1023)},
 657         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 658                 prc1522)},
 659         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 660         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 661         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 662         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 663         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 664         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 665         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 666         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 667         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 668         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 669         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 670         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 671         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 672         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 673         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 674         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 675         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 676                 ptc1023)},
 677         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 678                 ptc1522)},
 679         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 680         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 681         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 682         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 683
 684         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 685                 fdirustat_add)},
 686         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirustat_remove)},
 688         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 689                 fdirfstat_fadd)},
 690         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 691                 fdirfstat_fremove)},
 692         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 693                 fdirmatch)},
 694         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 695                 fdirmiss)},
 696
 697         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 698         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 699         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 700                 fclast)},
 701         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 702         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 703         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 704         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 705         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 706                 fcoe_noddp)},
 707         {"rx_fcoe_no_direct_data_placement_ext_buff",
 708                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 709
 710         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 711                 lxontxc)},
 712         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 713                 lxonrxc)},
 714         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 715                 lxofftxc)},
 716         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 717                 lxoffrxc)},
 718         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 719 };
 720
 721 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 722                            sizeof(rte_ixgbe_stats_strings[0]))
 723
 724 /* MACsec statistics */
 725 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 726         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 727                 out_pkts_untagged)},
 728         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 729                 out_pkts_encrypted)},
 730         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 731                 out_pkts_protected)},
 732         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 733                 out_octets_encrypted)},
 734         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 735                 out_octets_protected)},
 736         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_untagged)},
 738         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_badtag)},
 740         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_nosci)},
 742         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_unknownsci)},
 744         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 745                 in_octets_decrypted)},
 746         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 747                 in_octets_validated)},
 748         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_unchecked)},
 750         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_delayed)},
 752         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_late)},
 754         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_ok)},
 756         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_invalid)},
 758         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_notvalid)},
 760         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unusedsa)},
 762         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_notusingsa)},
 764 };
 765
 766 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 767                            sizeof(rte_ixgbe_macsec_strings[0]))
 768
 769 /* Per-queue statistics */
 770 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 771         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 772         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 773         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 774         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 775 };
 776
 777 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 778                            sizeof(rte_ixgbe_rxq_strings[0]))
 779 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 780
 781 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 782         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 783         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 784         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 785                 pxon2offc)},
 786 };
 787
 788 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 789                            sizeof(rte_ixgbe_txq_strings[0]))
 790 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 791
 792 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 793         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 794 };
 795
 796 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 797                 sizeof(rte_ixgbevf_stats_strings[0]))
 798
 799 /*
 800  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 801  */
 802 static inline int
 803 ixgbe_is_sfp(struct ixgbe_hw *hw)
 804 {
 805         switch (hw->phy.type) {
 806         case ixgbe_phy_sfp_avago:
 807         case ixgbe_phy_sfp_ftl:
 808         case ixgbe_phy_sfp_intel:
 809         case ixgbe_phy_sfp_unknown:
 810         case ixgbe_phy_sfp_passive_tyco:
 811         case ixgbe_phy_sfp_passive_unknown:
 812                 return 1;
 813         default:
 814                 return 0;
 815         }
 816 }
 817
 818 static inline int32_t
 819 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 820 {
 821         uint32_t ctrl_ext;
 822         int32_t status;
 823
 824         status = ixgbe_reset_hw(hw);
 825
 826         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 827         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 828         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 829         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 830         IXGBE_WRITE_FLUSH(hw);
 831
 832         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 833                 status = IXGBE_SUCCESS;
 834         return status;
 835 }
 836
 837 static inline void
 838 ixgbe_enable_intr(struct rte_eth_dev *dev)
 839 {
 840         struct ixgbe_interrupt *intr =
 841                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 842         struct ixgbe_hw *hw =
 843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 844
 845         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 846         IXGBE_WRITE_FLUSH(hw);
 847 }
 848
 849 /*
 850  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 851  */
 852 static void
 853 ixgbe_disable_intr(struct ixgbe_hw *hw)
 854 {
 855         PMD_INIT_FUNC_TRACE();
 856
 857         if (hw->mac.type == ixgbe_mac_82598EB) {
 858                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 859         } else {
 860                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 862                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 863         }
 864         IXGBE_WRITE_FLUSH(hw);
 865 }
 866
 867 /*
 868  * This function resets queue statistics mapping registers.
 869  * From Niantic datasheet, Initialization of Statistics section:
 870  * "...if software requires the queue counters, the RQSMR and TQSM registers
 871  * must be re-programmed following a device reset.
 872  */
 873 static void
 874 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 875 {
 876         uint32_t i;
 877
 878         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 879                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 880                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 881         }
 882 }
 883
 884
 885 static int
 886 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 887                                   uint16_t queue_id,
 888                                   uint8_t stat_idx,
 889                                   uint8_t is_rx)
 890 {
 891 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 892 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 893 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 894
 895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 896         struct ixgbe_stat_mapping_registers *stat_mappings =
 897                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 898         uint32_t qsmr_mask = 0;
 899         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 900         uint32_t q_map;
 901         uint8_t n, offset;
 902
 903         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 904                 (hw->mac.type != ixgbe_mac_X540) &&
 905                 (hw->mac.type != ixgbe_mac_X550) &&
 906                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 907                 (hw->mac.type != ixgbe_mac_X550EM_a))
 908                 return -ENOSYS;
 909
 910         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 911                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 912                      queue_id, stat_idx);
 913
 914         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 915         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 916                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 917                 return -EIO;
 918         }
 919         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 920
 921         /* Now clear any previous stat_idx set */
 922         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 923         if (!is_rx)
 924                 stat_mappings->tqsm[n] &= ~clearing_mask;
 925         else
 926                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 927
 928         q_map = (uint32_t)stat_idx;
 929         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 930         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 931         if (!is_rx)
 932                 stat_mappings->tqsm[n] |= qsmr_mask;
 933         else
 934                 stat_mappings->rqsmr[n] |= qsmr_mask;
 935
 936         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 937                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 938                      queue_id, stat_idx);
 939         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 940                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 941
 942         /* Now write the mapping in the appropriate register */
 943         if (is_rx) {
 944                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 945                              stat_mappings->rqsmr[n], n);
 946                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 947         } else {
 948                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 949                              stat_mappings->tqsm[n], n);
 950                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 951         }
 952         return 0;
 953 }
 954
 955 static void
 956 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 957 {
 958         struct ixgbe_stat_mapping_registers *stat_mappings =
 959                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 960         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961         int i;
 962
 963         /* write whatever was in stat mapping table to the NIC */
 964         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 965                 /* rx */
 966                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 967
 968                 /* tx */
 969                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 970         }
 971 }
 972
 973 static void
 974 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 975 {
 976         uint8_t i;
 977         struct ixgbe_dcb_tc_config *tc;
 978         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 979
 980         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 981         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 982         for (i = 0; i < dcb_max_tc; i++) {
 983                 tc = &dcb_config->tc_config[i];
 984                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 985                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 986                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 987                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 988                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 989                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 990                 tc->pfc = ixgbe_dcb_pfc_disabled;
 991         }
 992
 993         /* Initialize default user to priority mapping, UPx->TC0 */
 994         tc = &dcb_config->tc_config[0];
 995         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 996         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 997         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 998                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 999                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1000         }
1001         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1002         dcb_config->pfc_mode_enable = false;
1003         dcb_config->vt_mode = true;
1004         dcb_config->round_robin_enable = false;
1005         /* support all DCB capabilities in 82599 */
1006         dcb_config->support.capabilities = 0xFF;
1007
1008         /*we only support 4 Tcs for X540, X550 */
1009         if (hw->mac.type == ixgbe_mac_X540 ||
1010                 hw->mac.type == ixgbe_mac_X550 ||
1011                 hw->mac.type == ixgbe_mac_X550EM_x ||
1012                 hw->mac.type == ixgbe_mac_X550EM_a) {
1013                 dcb_config->num_tcs.pg_tcs = 4;
1014                 dcb_config->num_tcs.pfc_tcs = 4;
1015         }
1016 }
1017
1018 /*
1019  * Ensure that all locks are released before first NVM or PHY access
1020  */
1021 static void
1022 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1023 {
1024         uint16_t mask;
1025
1026         /*
1027          * Phy lock should not fail in this early stage. If this is the case,
1028          * it is due to an improper exit of the application.
1029          * So force the release of the faulty lock. Release of common lock
1030          * is done automatically by swfw_sync function.
1031          */
1032         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1033         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1034                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1035         }
1036         ixgbe_release_swfw_semaphore(hw, mask);
1037
1038         /*
1039          * These ones are more tricky since they are common to all ports; but
1040          * swfw_sync retries last long enough (1s) to be almost sure that if
1041          * lock can not be taken it is due to an improper lock of the
1042          * semaphore.
1043          */
1044         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1045         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1046                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1047         }
1048         ixgbe_release_swfw_semaphore(hw, mask);
1049 }
1050
1051 /*
1052  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1053  * It returns 0 on success.
1054  */
1055 static int
1056 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1057 {
1058         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1059         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1060         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1061         struct ixgbe_hw *hw =
1062                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1063         struct ixgbe_vfta *shadow_vfta =
1064                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1065         struct ixgbe_hwstrip *hwstrip =
1066                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1067         struct ixgbe_dcb_config *dcb_config =
1068                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1069         struct ixgbe_filter_info *filter_info =
1070                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1071         struct ixgbe_bw_conf *bw_conf =
1072                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1073         uint32_t ctrl_ext;
1074         uint16_t csum;
1075         int diag, i, ret;
1076
1077         PMD_INIT_FUNC_TRACE();
1078
1079         ixgbe_dev_macsec_setting_reset(eth_dev);
1080
1081         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1082         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1083         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1084         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1085         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1086         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1087         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1088         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1089
1090         /*
1091          * For secondary processes, we don't initialise any further as primary
1092          * has already done this work. Only check we don't need a different
1093          * RX and TX function.
1094          */
1095         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1096                 struct ixgbe_tx_queue *txq;
1097                 /* TX queue function in primary, set by last queue initialized
1098                  * Tx queue may not initialized by primary process
1099                  */
1100                 if (eth_dev->data->tx_queues) {
1101                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1102                         ixgbe_set_tx_function(eth_dev, txq);
1103                 } else {
1104                         /* Use default TX function if we get here */
1105                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1106                                      "Using default TX function.");
1107                 }
1108
1109                 ixgbe_set_rx_function(eth_dev);
1110
1111                 return 0;
1112         }
1113
1114         rte_atomic32_clear(&ad->link_thread_running);
1115         rte_eth_copy_pci_info(eth_dev, pci_dev);
1116         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1117
1118         /* Vendor and Device ID need to be set before init of shared code */
1119         hw->device_id = pci_dev->id.device_id;
1120         hw->vendor_id = pci_dev->id.vendor_id;
1121         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1122         hw->allow_unsupported_sfp = 1;
1123
1124         /* Initialize the shared code (base driver) */
1125 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1126         diag = ixgbe_bypass_init_shared_code(hw);
1127 #else
1128         diag = ixgbe_init_shared_code(hw);
1129 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1130
1131         if (diag != IXGBE_SUCCESS) {
1132                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1133                 return -EIO;
1134         }
1135
1136         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1137                 PMD_INIT_LOG(ERR, "\nERROR: "
1138                         "Firmware recovery mode detected. Limiting functionality.\n"
1139                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1140                         "User Guide for details on firmware recovery mode.");
1141                 return -EIO;
1142         }
1143
1144         /* pick up the PCI bus settings for reporting later */
1145         ixgbe_get_bus_info(hw);
1146
1147         /* Unlock any pending hardware semaphore */
1148         ixgbe_swfw_lock_reset(hw);
1149
1150 #ifdef RTE_LIB_SECURITY
1151         /* Initialize security_ctx only for primary process*/
1152         if (ixgbe_ipsec_ctx_create(eth_dev))
1153                 return -ENOMEM;
1154 #endif
1155
1156         /* Initialize DCB configuration*/
1157         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1158         ixgbe_dcb_init(hw, dcb_config);
1159         /* Get Hardware Flow Control setting */
1160         hw->fc.requested_mode = ixgbe_fc_none;
1161         hw->fc.current_mode = ixgbe_fc_none;
1162         hw->fc.pause_time = IXGBE_FC_PAUSE;
1163         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1164                 hw->fc.low_water[i] = IXGBE_FC_LO;
1165                 hw->fc.high_water[i] = IXGBE_FC_HI;
1166         }
1167         hw->fc.send_xon = 1;
1168
1169         /* Make sure we have a good EEPROM before we read from it */
1170         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1171         if (diag != IXGBE_SUCCESS) {
1172                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1173                 return -EIO;
1174         }
1175
1176 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1177         diag = ixgbe_bypass_init_hw(hw);
1178 #else
1179         diag = ixgbe_init_hw(hw);
1180 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1181
1182         /*
1183          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1184          * is called too soon after the kernel driver unbinding/binding occurs.
1185          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1186          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1187          * also called. See ixgbe_identify_phy_82599(). The reason for the
1188          * failure is not known, and only occuts when virtualisation features
1189          * are disabled in the bios. A delay of 100ms  was found to be enough by
1190          * trial-and-error, and is doubled to be safe.
1191          */
1192         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1193                 rte_delay_ms(200);
1194                 diag = ixgbe_init_hw(hw);
1195         }
1196
1197         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1198                 diag = IXGBE_SUCCESS;
1199
1200         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1201                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1202                              "LOM.  Please be aware there may be issues associated "
1203                              "with your hardware.");
1204                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1205                              "please contact your Intel or hardware representative "
1206                              "who provided you with this hardware.");
1207         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1208                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1209         if (diag) {
1210                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1211                 return -EIO;
1212         }
1213
1214         /* Reset the hw statistics */
1215         ixgbe_dev_stats_reset(eth_dev);
1216
1217         /* disable interrupt */
1218         ixgbe_disable_intr(hw);
1219
1220         /* reset mappings for queue statistics hw counters*/
1221         ixgbe_reset_qstat_mappings(hw);
1222
1223         /* Allocate memory for storing MAC addresses */
1224         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1225                                                hw->mac.num_rar_entries, 0);
1226         if (eth_dev->data->mac_addrs == NULL) {
1227                 PMD_INIT_LOG(ERR,
1228                              "Failed to allocate %u bytes needed to store "
1229                              "MAC addresses",
1230                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1231                 return -ENOMEM;
1232         }
1233         /* Copy the permanent MAC address */
1234         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1235                         &eth_dev->data->mac_addrs[0]);
1236
1237         /* Allocate memory for storing hash filter MAC addresses */
1238         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1239                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1240         if (eth_dev->data->hash_mac_addrs == NULL) {
1241                 PMD_INIT_LOG(ERR,
1242                              "Failed to allocate %d bytes needed to store MAC addresses",
1243                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1244                 return -ENOMEM;
1245         }
1246
1247         /* initialize the vfta */
1248         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1249
1250         /* initialize the hw strip bitmap*/
1251         memset(hwstrip, 0, sizeof(*hwstrip));
1252
1253         /* initialize PF if max_vfs not zero */
1254         ret = ixgbe_pf_host_init(eth_dev);
1255         if (ret) {
1256                 rte_free(eth_dev->data->mac_addrs);
1257                 eth_dev->data->mac_addrs = NULL;
1258                 rte_free(eth_dev->data->hash_mac_addrs);
1259                 eth_dev->data->hash_mac_addrs = NULL;
1260                 return ret;
1261         }
1262
1263         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1264         /* let hardware know driver is loaded */
1265         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1266         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1267         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1268         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1269         IXGBE_WRITE_FLUSH(hw);
1270
1271         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1272                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1273                              (int) hw->mac.type, (int) hw->phy.type,
1274                              (int) hw->phy.sfp_type);
1275         else
1276                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1277                              (int) hw->mac.type, (int) hw->phy.type);
1278
1279         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1280                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1281                      pci_dev->id.device_id);
1282
1283         rte_intr_callback_register(intr_handle,
1284                                    ixgbe_dev_interrupt_handler, eth_dev);
1285
1286         /* enable uio/vfio intr/eventfd mapping */
1287         rte_intr_enable(intr_handle);
1288
1289         /* enable support intr */
1290         ixgbe_enable_intr(eth_dev);
1291
1292         /* initialize filter info */
1293         memset(filter_info, 0,
1294                sizeof(struct ixgbe_filter_info));
1295
1296         /* initialize 5tuple filter list */
1297         TAILQ_INIT(&filter_info->fivetuple_list);
1298
1299         /* initialize flow director filter list & hash */
1300         ixgbe_fdir_filter_init(eth_dev);
1301
1302         /* initialize l2 tunnel filter list & hash */
1303         ixgbe_l2_tn_filter_init(eth_dev);
1304
1305         /* initialize flow filter lists */
1306         ixgbe_filterlist_init();
1307
1308         /* initialize bandwidth configuration info */
1309         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1310
1311         /* initialize Traffic Manager configuration */
1312         ixgbe_tm_conf_init(eth_dev);
1313
1314         return 0;
1315 }
1316
1317 static int
1318 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1319 {
1320         PMD_INIT_FUNC_TRACE();
1321
1322         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1323                 return 0;
1324
1325         ixgbe_dev_close(eth_dev);
1326
1327         return 0;
1328 }
1329
1330 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1331 {
1332         struct ixgbe_filter_info *filter_info =
1333                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1334         struct ixgbe_5tuple_filter *p_5tuple;
1335
1336         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1337                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1338                              p_5tuple,
1339                              entries);
1340                 rte_free(p_5tuple);
1341         }
1342         memset(filter_info->fivetuple_mask, 0,
1343                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1344
1345         return 0;
1346 }
1347
1348 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1349 {
1350         struct ixgbe_hw_fdir_info *fdir_info =
1351                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1352         struct ixgbe_fdir_filter *fdir_filter;
1353
1354                 if (fdir_info->hash_map)
1355                 rte_free(fdir_info->hash_map);
1356         if (fdir_info->hash_handle)
1357                 rte_hash_free(fdir_info->hash_handle);
1358
1359         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1360                 TAILQ_REMOVE(&fdir_info->fdir_list,
1361                              fdir_filter,
1362                              entries);
1363                 rte_free(fdir_filter);
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1370 {
1371         struct ixgbe_l2_tn_info *l2_tn_info =
1372                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1373         struct ixgbe_l2_tn_filter *l2_tn_filter;
1374
1375         if (l2_tn_info->hash_map)
1376                 rte_free(l2_tn_info->hash_map);
1377         if (l2_tn_info->hash_handle)
1378                 rte_hash_free(l2_tn_info->hash_handle);
1379
1380         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1381                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1382                              l2_tn_filter,
1383                              entries);
1384                 rte_free(l2_tn_filter);
1385         }
1386
1387         return 0;
1388 }
1389
1390 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1391 {
1392         struct ixgbe_hw_fdir_info *fdir_info =
1393                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1394         char fdir_hash_name[RTE_HASH_NAMESIZE];
1395         struct rte_hash_parameters fdir_hash_params = {
1396                 .name = fdir_hash_name,
1397                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1398                 .key_len = sizeof(union ixgbe_atr_input),
1399                 .hash_func = rte_hash_crc,
1400                 .hash_func_init_val = 0,
1401                 .socket_id = rte_socket_id(),
1402         };
1403
1404         TAILQ_INIT(&fdir_info->fdir_list);
1405         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1406                  "fdir_%s", eth_dev->device->name);
1407         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1408         if (!fdir_info->hash_handle) {
1409                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1410                 return -EINVAL;
1411         }
1412         fdir_info->hash_map = rte_zmalloc("ixgbe",
1413                                           sizeof(struct ixgbe_fdir_filter *) *
1414                                           IXGBE_MAX_FDIR_FILTER_NUM,
1415                                           0);
1416         if (!fdir_info->hash_map) {
1417                 PMD_INIT_LOG(ERR,
1418                              "Failed to allocate memory for fdir hash map!");
1419                 return -ENOMEM;
1420         }
1421         fdir_info->mask_added = FALSE;
1422
1423         return 0;
1424 }
1425
1426 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1427 {
1428         struct ixgbe_l2_tn_info *l2_tn_info =
1429                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1430         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1431         struct rte_hash_parameters l2_tn_hash_params = {
1432                 .name = l2_tn_hash_name,
1433                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1434                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1435                 .hash_func = rte_hash_crc,
1436                 .hash_func_init_val = 0,
1437                 .socket_id = rte_socket_id(),
1438         };
1439
1440         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1441         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1442                  "l2_tn_%s", eth_dev->device->name);
1443         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1444         if (!l2_tn_info->hash_handle) {
1445                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1446                 return -EINVAL;
1447         }
1448         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1449                                    sizeof(struct ixgbe_l2_tn_filter *) *
1450                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1451                                    0);
1452         if (!l2_tn_info->hash_map) {
1453                 PMD_INIT_LOG(ERR,
1454                         "Failed to allocate memory for L2 TN hash map!");
1455                 return -ENOMEM;
1456         }
1457         l2_tn_info->e_tag_en = FALSE;
1458         l2_tn_info->e_tag_fwd_en = FALSE;
1459         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1460
1461         return 0;
1462 }
1463 /*
1464  * Negotiate mailbox API version with the PF.
1465  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1466  * Then we try to negotiate starting with the most recent one.
1467  * If all negotiation attempts fail, then we will proceed with
1468  * the default one (ixgbe_mbox_api_10).
1469  */
1470 static void
1471 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1472 {
1473         int32_t i;
1474
1475         /* start with highest supported, proceed down */
1476         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1477                 ixgbe_mbox_api_13,
1478                 ixgbe_mbox_api_12,
1479                 ixgbe_mbox_api_11,
1480                 ixgbe_mbox_api_10,
1481         };
1482
1483         for (i = 0;
1484                         i != RTE_DIM(sup_ver) &&
1485                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1486                         i++)
1487                 ;
1488 }
1489
1490 static void
1491 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1492 {
1493         uint64_t random;
1494
1495         /* Set Organizationally Unique Identifier (OUI) prefix. */
1496         mac_addr->addr_bytes[0] = 0x00;
1497         mac_addr->addr_bytes[1] = 0x09;
1498         mac_addr->addr_bytes[2] = 0xC0;
1499         /* Force indication of locally assigned MAC address. */
1500         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1501         /* Generate the last 3 bytes of the MAC address with a random number. */
1502         random = rte_rand();
1503         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1504 }
1505
1506 static int
1507 devarg_handle_int(__rte_unused const char *key, const char *value,
1508                   void *extra_args)
1509 {
1510         uint16_t *n = extra_args;
1511
1512         if (value == NULL || extra_args == NULL)
1513                 return -EINVAL;
1514
1515         *n = (uint16_t)strtoul(value, NULL, 0);
1516         if (*n == USHRT_MAX && errno == ERANGE)
1517                 return -1;
1518
1519         return 0;
1520 }
1521
1522 static void
1523 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1524                       struct rte_devargs *devargs)
1525 {
1526         struct rte_kvargs *kvlist;
1527         uint16_t pflink_fullchk;
1528
1529         if (devargs == NULL)
1530                 return;
1531
1532         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1533         if (kvlist == NULL)
1534                 return;
1535
1536         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1537             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1538                                devarg_handle_int, &pflink_fullchk) == 0 &&
1539             pflink_fullchk == 1)
1540                 adapter->pflink_fullchk = 1;
1541
1542         rte_kvargs_free(kvlist);
1543 }
1544
1545 /*
1546  * Virtual Function device init
1547  */
1548 static int
1549 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1550 {
1551         int diag;
1552         uint32_t tc, tcs;
1553         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1554         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1555         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1556         struct ixgbe_hw *hw =
1557                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1558         struct ixgbe_vfta *shadow_vfta =
1559                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1560         struct ixgbe_hwstrip *hwstrip =
1561                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1562         struct rte_ether_addr *perm_addr =
1563                 (struct rte_ether_addr *)hw->mac.perm_addr;
1564
1565         PMD_INIT_FUNC_TRACE();
1566
1567         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1568         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1569         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1570         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1571         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1572         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1573
1574         /* for secondary processes, we don't initialise any further as primary
1575          * has already done this work. Only check we don't need a different
1576          * RX function
1577          */
1578         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1579                 struct ixgbe_tx_queue *txq;
1580                 /* TX queue function in primary, set by last queue initialized
1581                  * Tx queue may not initialized by primary process
1582                  */
1583                 if (eth_dev->data->tx_queues) {
1584                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1585                         ixgbe_set_tx_function(eth_dev, txq);
1586                 } else {
1587                         /* Use default TX function if we get here */
1588                         PMD_INIT_LOG(NOTICE,
1589                                      "No TX queues configured yet. Using default TX function.");
1590                 }
1591
1592                 ixgbe_set_rx_function(eth_dev);
1593
1594                 return 0;
1595         }
1596
1597         rte_atomic32_clear(&ad->link_thread_running);
1598         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1599                               pci_dev->device.devargs);
1600
1601         rte_eth_copy_pci_info(eth_dev, pci_dev);
1602         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1603
1604         hw->device_id = pci_dev->id.device_id;
1605         hw->vendor_id = pci_dev->id.vendor_id;
1606         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1607
1608         /* initialize the vfta */
1609         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1610
1611         /* initialize the hw strip bitmap*/
1612         memset(hwstrip, 0, sizeof(*hwstrip));
1613
1614         /* Initialize the shared code (base driver) */
1615         diag = ixgbe_init_shared_code(hw);
1616         if (diag != IXGBE_SUCCESS) {
1617                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1618                 return -EIO;
1619         }
1620
1621         /* init_mailbox_params */
1622         hw->mbx.ops.init_params(hw);
1623
1624         /* Reset the hw statistics */
1625         ixgbevf_dev_stats_reset(eth_dev);
1626
1627         /* Disable the interrupts for VF */
1628         ixgbevf_intr_disable(eth_dev);
1629
1630         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1631         diag = hw->mac.ops.reset_hw(hw);
1632
1633         /*
1634          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1635          * the underlying PF driver has not assigned a MAC address to the VF.
1636          * In this case, assign a random MAC address.
1637          */
1638         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1639                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1640                 /*
1641                  * This error code will be propagated to the app by
1642                  * rte_eth_dev_reset, so use a public error code rather than
1643                  * the internal-only IXGBE_ERR_RESET_FAILED
1644                  */
1645                 return -EAGAIN;
1646         }
1647
1648         /* negotiate mailbox API version to use with the PF. */
1649         ixgbevf_negotiate_api(hw);
1650
1651         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1652         ixgbevf_get_queues(hw, &tcs, &tc);
1653
1654         /* Allocate memory for storing MAC addresses */
1655         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1656                                                hw->mac.num_rar_entries, 0);
1657         if (eth_dev->data->mac_addrs == NULL) {
1658                 PMD_INIT_LOG(ERR,
1659                              "Failed to allocate %u bytes needed to store "
1660                              "MAC addresses",
1661                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1662                 return -ENOMEM;
1663         }
1664
1665         /* Generate a random MAC address, if none was assigned by PF. */
1666         if (rte_is_zero_ether_addr(perm_addr)) {
1667                 generate_random_mac_addr(perm_addr);
1668                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1669                 if (diag) {
1670                         rte_free(eth_dev->data->mac_addrs);
1671                         eth_dev->data->mac_addrs = NULL;
1672                         return diag;
1673                 }
1674                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1675                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1676                              "%02x:%02x:%02x:%02x:%02x:%02x",
1677                              perm_addr->addr_bytes[0],
1678                              perm_addr->addr_bytes[1],
1679                              perm_addr->addr_bytes[2],
1680                              perm_addr->addr_bytes[3],
1681                              perm_addr->addr_bytes[4],
1682                              perm_addr->addr_bytes[5]);
1683         }
1684
1685         /* Copy the permanent MAC address */
1686         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1687
1688         /* reset the hardware with the new settings */
1689         diag = hw->mac.ops.start_hw(hw);
1690         switch (diag) {
1691         case  0:
1692                 break;
1693
1694         default:
1695                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1696                 return -EIO;
1697         }
1698
1699         rte_intr_callback_register(intr_handle,
1700                                    ixgbevf_dev_interrupt_handler, eth_dev);
1701         rte_intr_enable(intr_handle);
1702         ixgbevf_intr_enable(eth_dev);
1703
1704         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1705                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1706                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1707
1708         return 0;
1709 }
1710
1711 /* Virtual Function device uninit */
1712
1713 static int
1714 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1715 {
1716         PMD_INIT_FUNC_TRACE();
1717
1718         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1719                 return 0;
1720
1721         ixgbevf_dev_close(eth_dev);
1722
1723         return 0;
1724 }
1725
1726 static int
1727 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1728                 struct rte_pci_device *pci_dev)
1729 {
1730         char name[RTE_ETH_NAME_MAX_LEN];
1731         struct rte_eth_dev *pf_ethdev;
1732         struct rte_eth_devargs eth_da;
1733         int i, retval;
1734
1735         if (pci_dev->device.devargs) {
1736                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1737                                 &eth_da);
1738                 if (retval)
1739                         return retval;
1740         } else
1741                 memset(&eth_da, 0, sizeof(eth_da));
1742
1743         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1744                 sizeof(struct ixgbe_adapter),
1745                 eth_dev_pci_specific_init, pci_dev,
1746                 eth_ixgbe_dev_init, NULL);
1747
1748         if (retval || eth_da.nb_representor_ports < 1)
1749                 return retval;
1750
1751         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1752         if (pf_ethdev == NULL)
1753                 return -ENODEV;
1754
1755         /* probe VF representor ports */
1756         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1757                 struct ixgbe_vf_info *vfinfo;
1758                 struct ixgbe_vf_representor representor;
1759
1760                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1761                         pf_ethdev->data->dev_private);
1762                 if (vfinfo == NULL) {
1763                         PMD_DRV_LOG(ERR,
1764                                 "no virtual functions supported by PF");
1765                         break;
1766                 }
1767
1768                 representor.vf_id = eth_da.representor_ports[i];
1769                 representor.switch_domain_id = vfinfo->switch_domain_id;
1770                 representor.pf_ethdev = pf_ethdev;
1771
1772                 /* representor port net_bdf_port */
1773                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1774                         pci_dev->device.name,
1775                         eth_da.representor_ports[i]);
1776
1777                 retval = rte_eth_dev_create(&pci_dev->device, name,
1778                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1779                         ixgbe_vf_representor_init, &representor);
1780
1781                 if (retval)
1782                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1783                                 "representor %s.", name);
1784         }
1785
1786         return 0;
1787 }
1788
1789 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1790 {
1791         struct rte_eth_dev *ethdev;
1792
1793         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1794         if (!ethdev)
1795                 return 0;
1796
1797         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1798                 return rte_eth_dev_pci_generic_remove(pci_dev,
1799                                         ixgbe_vf_representor_uninit);
1800         else
1801                 return rte_eth_dev_pci_generic_remove(pci_dev,
1802                                                 eth_ixgbe_dev_uninit);
1803 }
1804
1805 static struct rte_pci_driver rte_ixgbe_pmd = {
1806         .id_table = pci_id_ixgbe_map,
1807         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1808         .probe = eth_ixgbe_pci_probe,
1809         .remove = eth_ixgbe_pci_remove,
1810 };
1811
1812 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1813         struct rte_pci_device *pci_dev)
1814 {
1815         return rte_eth_dev_pci_generic_probe(pci_dev,
1816                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1817 }
1818
1819 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1820 {
1821         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1822 }
1823
1824 /*
1825  * virtual function driver struct
1826  */
1827 static struct rte_pci_driver rte_ixgbevf_pmd = {
1828         .id_table = pci_id_ixgbevf_map,
1829         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1830         .probe = eth_ixgbevf_pci_probe,
1831         .remove = eth_ixgbevf_pci_remove,
1832 };
1833
1834 static int
1835 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1836 {
1837         struct ixgbe_hw *hw =
1838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839         struct ixgbe_vfta *shadow_vfta =
1840                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1841         uint32_t vfta;
1842         uint32_t vid_idx;
1843         uint32_t vid_bit;
1844
1845         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1846         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1847         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1848         if (on)
1849                 vfta |= vid_bit;
1850         else
1851                 vfta &= ~vid_bit;
1852         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1853
1854         /* update local VFTA copy */
1855         shadow_vfta->vfta[vid_idx] = vfta;
1856
1857         return 0;
1858 }
1859
1860 static void
1861 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1862 {
1863         if (on)
1864                 ixgbe_vlan_hw_strip_enable(dev, queue);
1865         else
1866                 ixgbe_vlan_hw_strip_disable(dev, queue);
1867 }
1868
1869 static int
1870 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1871                     enum rte_vlan_type vlan_type,
1872                     uint16_t tpid)
1873 {
1874         struct ixgbe_hw *hw =
1875                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876         int ret = 0;
1877         uint32_t reg;
1878         uint32_t qinq;
1879
1880         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1881         qinq &= IXGBE_DMATXCTL_GDV;
1882
1883         switch (vlan_type) {
1884         case ETH_VLAN_TYPE_INNER:
1885                 if (qinq) {
1886                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1887                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1888                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1889                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1890                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1891                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1892                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1893                 } else {
1894                         ret = -ENOTSUP;
1895                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1896                                     " by single VLAN");
1897                 }
1898                 break;
1899         case ETH_VLAN_TYPE_OUTER:
1900                 if (qinq) {
1901                         /* Only the high 16-bits is valid */
1902                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1903                                         IXGBE_EXVET_VET_EXT_SHIFT);
1904                 } else {
1905                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1906                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1907                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1908                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1909                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1910                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1911                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1912                 }
1913
1914                 break;
1915         default:
1916                 ret = -EINVAL;
1917                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1918                 break;
1919         }
1920
1921         return ret;
1922 }
1923
1924 void
1925 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1926 {
1927         struct ixgbe_hw *hw =
1928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         uint32_t vlnctrl;
1930
1931         PMD_INIT_FUNC_TRACE();
1932
1933         /* Filter Table Disable */
1934         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1935         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1936
1937         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1938 }
1939
1940 void
1941 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1942 {
1943         struct ixgbe_hw *hw =
1944                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1945         struct ixgbe_vfta *shadow_vfta =
1946                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1947         uint32_t vlnctrl;
1948         uint16_t i;
1949
1950         PMD_INIT_FUNC_TRACE();
1951
1952         /* Filter Table Enable */
1953         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1954         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1955         vlnctrl |= IXGBE_VLNCTRL_VFE;
1956
1957         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1958
1959         /* write whatever is in local vfta copy */
1960         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1961                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1962 }
1963
1964 static void
1965 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1966 {
1967         struct ixgbe_hwstrip *hwstrip =
1968                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1969         struct ixgbe_rx_queue *rxq;
1970
1971         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1972                 return;
1973
1974         if (on)
1975                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1976         else
1977                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1978
1979         if (queue >= dev->data->nb_rx_queues)
1980                 return;
1981
1982         rxq = dev->data->rx_queues[queue];
1983
1984         if (on) {
1985                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1986                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1987         } else {
1988                 rxq->vlan_flags = PKT_RX_VLAN;
1989                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1990         }
1991 }
1992
1993 static void
1994 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1995 {
1996         struct ixgbe_hw *hw =
1997                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998         uint32_t ctrl;
1999
2000         PMD_INIT_FUNC_TRACE();
2001
2002         if (hw->mac.type == ixgbe_mac_82598EB) {
2003                 /* No queue level support */
2004                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2005                 return;
2006         }
2007
2008         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2009         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2010         ctrl &= ~IXGBE_RXDCTL_VME;
2011         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2012
2013         /* record those setting for HW strip per queue */
2014         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2015 }
2016
2017 static void
2018 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2019 {
2020         struct ixgbe_hw *hw =
2021                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022         uint32_t ctrl;
2023
2024         PMD_INIT_FUNC_TRACE();
2025
2026         if (hw->mac.type == ixgbe_mac_82598EB) {
2027                 /* No queue level supported */
2028                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2029                 return;
2030         }
2031
2032         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2033         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2034         ctrl |= IXGBE_RXDCTL_VME;
2035         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2036
2037         /* record those setting for HW strip per queue */
2038         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2039 }
2040
2041 static void
2042 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2043 {
2044         struct ixgbe_hw *hw =
2045                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2046         uint32_t ctrl;
2047
2048         PMD_INIT_FUNC_TRACE();
2049
2050         /* DMATXCTRL: Geric Double VLAN Disable */
2051         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2052         ctrl &= ~IXGBE_DMATXCTL_GDV;
2053         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2054
2055         /* CTRL_EXT: Global Double VLAN Disable */
2056         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2057         ctrl &= ~IXGBE_EXTENDED_VLAN;
2058         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2059
2060 }
2061
2062 static void
2063 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2064 {
2065         struct ixgbe_hw *hw =
2066                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         uint32_t ctrl;
2068
2069         PMD_INIT_FUNC_TRACE();
2070
2071         /* DMATXCTRL: Geric Double VLAN Enable */
2072         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2073         ctrl |= IXGBE_DMATXCTL_GDV;
2074         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2075
2076         /* CTRL_EXT: Global Double VLAN Enable */
2077         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2078         ctrl |= IXGBE_EXTENDED_VLAN;
2079         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2080
2081         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2082         if (hw->mac.type == ixgbe_mac_X550 ||
2083             hw->mac.type == ixgbe_mac_X550EM_x ||
2084             hw->mac.type == ixgbe_mac_X550EM_a) {
2085                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2086                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2087                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2088         }
2089
2090         /*
2091          * VET EXT field in the EXVET register = 0x8100 by default
2092          * So no need to change. Same to VT field of DMATXCTL register
2093          */
2094 }
2095
2096 void
2097 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2098 {
2099         struct ixgbe_hw *hw =
2100                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2102         uint32_t ctrl;
2103         uint16_t i;
2104         struct ixgbe_rx_queue *rxq;
2105         bool on;
2106
2107         PMD_INIT_FUNC_TRACE();
2108
2109         if (hw->mac.type == ixgbe_mac_82598EB) {
2110                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2111                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2112                         ctrl |= IXGBE_VLNCTRL_VME;
2113                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2114                 } else {
2115                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2116                         ctrl &= ~IXGBE_VLNCTRL_VME;
2117                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2118                 }
2119         } else {
2120                 /*
2121                  * Other 10G NIC, the VLAN strip can be setup
2122                  * per queue in RXDCTL
2123                  */
2124                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2125                         rxq = dev->data->rx_queues[i];
2126                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2127                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2128                                 ctrl |= IXGBE_RXDCTL_VME;
2129                                 on = TRUE;
2130                         } else {
2131                                 ctrl &= ~IXGBE_RXDCTL_VME;
2132                                 on = FALSE;
2133                         }
2134                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2135
2136                         /* record those setting for HW strip per queue */
2137                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2138                 }
2139         }
2140 }
2141
2142 static void
2143 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2144 {
2145         uint16_t i;
2146         struct rte_eth_rxmode *rxmode;
2147         struct ixgbe_rx_queue *rxq;
2148
2149         if (mask & ETH_VLAN_STRIP_MASK) {
2150                 rxmode = &dev->data->dev_conf.rxmode;
2151                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2152                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2153                                 rxq = dev->data->rx_queues[i];
2154                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2155                         }
2156                 else
2157                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2158                                 rxq = dev->data->rx_queues[i];
2159                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2160                         }
2161         }
2162 }
2163
2164 static int
2165 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2166 {
2167         struct rte_eth_rxmode *rxmode;
2168         rxmode = &dev->data->dev_conf.rxmode;
2169
2170         if (mask & ETH_VLAN_STRIP_MASK) {
2171                 ixgbe_vlan_hw_strip_config(dev);
2172         }
2173
2174         if (mask & ETH_VLAN_FILTER_MASK) {
2175                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2176                         ixgbe_vlan_hw_filter_enable(dev);
2177                 else
2178                         ixgbe_vlan_hw_filter_disable(dev);
2179         }
2180
2181         if (mask & ETH_VLAN_EXTEND_MASK) {
2182                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2183                         ixgbe_vlan_hw_extend_enable(dev);
2184                 else
2185                         ixgbe_vlan_hw_extend_disable(dev);
2186         }
2187
2188         return 0;
2189 }
2190
2191 static int
2192 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2193 {
2194         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2195
2196         ixgbe_vlan_offload_config(dev, mask);
2197
2198         return 0;
2199 }
2200
2201 static void
2202 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2203 {
2204         struct ixgbe_hw *hw =
2205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2206         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2207         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2208
2209         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2210         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2211 }
2212
2213 static int
2214 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2215 {
2216         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2217
2218         switch (nb_rx_q) {
2219         case 1:
2220         case 2:
2221                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2222                 break;
2223         case 4:
2224                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2225                 break;
2226         default:
2227                 return -EINVAL;
2228         }
2229
2230         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2231                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2232         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2233                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2234         return 0;
2235 }
2236
2237 static int
2238 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2239 {
2240         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2243         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2244
2245         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2246                 /* check multi-queue mode */
2247                 switch (dev_conf->rxmode.mq_mode) {
2248                 case ETH_MQ_RX_VMDQ_DCB:
2249                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2250                         break;
2251                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2252                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2253                         PMD_INIT_LOG(ERR, "SRIOV active,"
2254                                         " unsupported mq_mode rx %d.",
2255                                         dev_conf->rxmode.mq_mode);
2256                         return -EINVAL;
2257                 case ETH_MQ_RX_RSS:
2258                 case ETH_MQ_RX_VMDQ_RSS:
2259                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2260                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2261                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2262                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2263                                                 " invalid queue number"
2264                                                 " for VMDQ RSS, allowed"
2265                                                 " value are 1, 2 or 4.");
2266                                         return -EINVAL;
2267                                 }
2268                         break;
2269                 case ETH_MQ_RX_VMDQ_ONLY:
2270                 case ETH_MQ_RX_NONE:
2271                         /* if nothing mq mode configure, use default scheme */
2272                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2273                         break;
2274                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2275                         /* SRIOV only works in VMDq enable mode */
2276                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2277                                         " wrong mq_mode rx %d.",
2278                                         dev_conf->rxmode.mq_mode);
2279                         return -EINVAL;
2280                 }
2281
2282                 switch (dev_conf->txmode.mq_mode) {
2283                 case ETH_MQ_TX_VMDQ_DCB:
2284                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2285                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2286                         break;
2287                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2288                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2289                         break;
2290                 }
2291
2292                 /* check valid queue number */
2293                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2294                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2295                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2296                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2297                                         " must be less than or equal to %d.",
2298                                         nb_rx_q, nb_tx_q,
2299                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2300                         return -EINVAL;
2301                 }
2302         } else {
2303                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2304                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2305                                           " not supported.");
2306                         return -EINVAL;
2307                 }
2308                 /* check configuration for vmdb+dcb mode */
2309                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2310                         const struct rte_eth_vmdq_dcb_conf *conf;
2311
2312                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2313                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2314                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2315                                 return -EINVAL;
2316                         }
2317                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2318                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2319                                conf->nb_queue_pools == ETH_32_POOLS)) {
2320                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2321                                                 " nb_queue_pools must be %d or %d.",
2322                                                 ETH_16_POOLS, ETH_32_POOLS);
2323                                 return -EINVAL;
2324                         }
2325                 }
2326                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2327                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2328
2329                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2330                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2331                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2332                                 return -EINVAL;
2333                         }
2334                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2335                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2336                                conf->nb_queue_pools == ETH_32_POOLS)) {
2337                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2338                                                 " nb_queue_pools != %d and"
2339                                                 " nb_queue_pools != %d.",
2340                                                 ETH_16_POOLS, ETH_32_POOLS);
2341                                 return -EINVAL;
2342                         }
2343                 }
2344
2345                 /* For DCB mode check our configuration before we go further */
2346                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2347                         const struct rte_eth_dcb_rx_conf *conf;
2348
2349                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2350                         if (!(conf->nb_tcs == ETH_4_TCS ||
2351                                conf->nb_tcs == ETH_8_TCS)) {
2352                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2353                                                 " and nb_tcs != %d.",
2354                                                 ETH_4_TCS, ETH_8_TCS);
2355                                 return -EINVAL;
2356                         }
2357                 }
2358
2359                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2360                         const struct rte_eth_dcb_tx_conf *conf;
2361
2362                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2363                         if (!(conf->nb_tcs == ETH_4_TCS ||
2364                                conf->nb_tcs == ETH_8_TCS)) {
2365                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2366                                                 " and nb_tcs != %d.",
2367                                                 ETH_4_TCS, ETH_8_TCS);
2368                                 return -EINVAL;
2369                         }
2370                 }
2371
2372                 /*
2373                  * When DCB/VT is off, maximum number of queues changes,
2374                  * except for 82598EB, which remains constant.
2375                  */
2376                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2377                                 hw->mac.type != ixgbe_mac_82598EB) {
2378                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2379                                 PMD_INIT_LOG(ERR,
2380                                              "Neither VT nor DCB are enabled, "
2381                                              "nb_tx_q > %d.",
2382                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2383                                 return -EINVAL;
2384                         }
2385                 }
2386         }
2387         return 0;
2388 }
2389
2390 static int
2391 ixgbe_dev_configure(struct rte_eth_dev *dev)
2392 {
2393         struct ixgbe_interrupt *intr =
2394                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2395         struct ixgbe_adapter *adapter = dev->data->dev_private;
2396         int ret;
2397
2398         PMD_INIT_FUNC_TRACE();
2399
2400         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2401                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2402
2403         /* multipe queue mode checking */
2404         ret  = ixgbe_check_mq_mode(dev);
2405         if (ret != 0) {
2406                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2407                             ret);
2408                 return ret;
2409         }
2410
2411         /* set flag to update link status after init */
2412         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2413
2414         /*
2415          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2416          * allocation or vector Rx preconditions we will reset it.
2417          */
2418         adapter->rx_bulk_alloc_allowed = true;
2419         adapter->rx_vec_allowed = true;
2420
2421         return 0;
2422 }
2423
2424 static void
2425 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2426 {
2427         struct ixgbe_hw *hw =
2428                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429         struct ixgbe_interrupt *intr =
2430                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2431         uint32_t gpie;
2432
2433         /* only set up it on X550EM_X */
2434         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2435                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2436                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2437                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2438                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2439                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2440         }
2441 }
2442
2443 int
2444 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2445                         uint16_t tx_rate, uint64_t q_msk)
2446 {
2447         struct ixgbe_hw *hw;
2448         struct ixgbe_vf_info *vfinfo;
2449         struct rte_eth_link link;
2450         uint8_t  nb_q_per_pool;
2451         uint32_t queue_stride;
2452         uint32_t queue_idx, idx = 0, vf_idx;
2453         uint32_t queue_end;
2454         uint16_t total_rate = 0;
2455         struct rte_pci_device *pci_dev;
2456         int ret;
2457
2458         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2459         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2460         if (ret < 0)
2461                 return ret;
2462
2463         if (vf >= pci_dev->max_vfs)
2464                 return -EINVAL;
2465
2466         if (tx_rate > link.link_speed)
2467                 return -EINVAL;
2468
2469         if (q_msk == 0)
2470                 return 0;
2471
2472         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2474         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2475         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2476         queue_idx = vf * queue_stride;
2477         queue_end = queue_idx + nb_q_per_pool - 1;
2478         if (queue_end >= hw->mac.max_tx_queues)
2479                 return -EINVAL;
2480
2481         if (vfinfo) {
2482                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2483                         if (vf_idx == vf)
2484                                 continue;
2485                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2486                                 idx++)
2487                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2488                 }
2489         } else {
2490                 return -EINVAL;
2491         }
2492
2493         /* Store tx_rate for this vf. */
2494         for (idx = 0; idx < nb_q_per_pool; idx++) {
2495                 if (((uint64_t)0x1 << idx) & q_msk) {
2496                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2497                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2498                         total_rate += tx_rate;
2499                 }
2500         }
2501
2502         if (total_rate > dev->data->dev_link.link_speed) {
2503                 /* Reset stored TX rate of the VF if it causes exceed
2504                  * link speed.
2505                  */
2506                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2507                 return -EINVAL;
2508         }
2509
2510         /* Set RTTBCNRC of each queue/pool for vf X  */
2511         for (; queue_idx <= queue_end; queue_idx++) {
2512                 if (0x1 & q_msk)
2513                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2514                 q_msk = q_msk >> 1;
2515         }
2516
2517         return 0;
2518 }
2519
2520 static int
2521 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2522 {
2523         struct ixgbe_adapter *adapter = dev->data->dev_private;
2524         int err;
2525         uint32_t mflcn;
2526
2527         ixgbe_setup_fc(hw);
2528
2529         err = ixgbe_fc_enable(hw);
2530
2531         /* Not negotiated is not an error case */
2532         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2533                 /*
2534                  *check if we want to forward MAC frames - driver doesn't
2535                  *have native capability to do that,
2536                  *so we'll write the registers ourselves
2537                  */
2538
2539                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2540
2541                 /* set or clear MFLCN.PMCF bit depending on configuration */
2542                 if (adapter->mac_ctrl_frame_fwd != 0)
2543                         mflcn |= IXGBE_MFLCN_PMCF;
2544                 else
2545                         mflcn &= ~IXGBE_MFLCN_PMCF;
2546
2547                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2548                 IXGBE_WRITE_FLUSH(hw);
2549
2550                 return 0;
2551         }
2552         return err;
2553 }
2554
2555 /*
2556  * Configure device link speed and setup link.
2557  * It returns 0 on success.
2558  */
2559 static int
2560 ixgbe_dev_start(struct rte_eth_dev *dev)
2561 {
2562         struct ixgbe_hw *hw =
2563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2564         struct ixgbe_vf_info *vfinfo =
2565                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2566         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2567         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2568         uint32_t intr_vector = 0;
2569         int err;
2570         bool link_up = false, negotiate = 0;
2571         uint32_t speed = 0;
2572         uint32_t allowed_speeds = 0;
2573         int mask = 0;
2574         int status;
2575         uint16_t vf, idx;
2576         uint32_t *link_speeds;
2577         struct ixgbe_tm_conf *tm_conf =
2578                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2579         struct ixgbe_macsec_setting *macsec_setting =
2580                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2581
2582         PMD_INIT_FUNC_TRACE();
2583
2584         /* Stop the link setup handler before resetting the HW. */
2585         ixgbe_dev_wait_setup_link_complete(dev, 0);
2586
2587         /* disable uio/vfio intr/eventfd mapping */
2588         rte_intr_disable(intr_handle);
2589
2590         /* stop adapter */
2591         hw->adapter_stopped = 0;
2592         ixgbe_stop_adapter(hw);
2593
2594         /* reinitialize adapter
2595          * this calls reset and start
2596          */
2597         status = ixgbe_pf_reset_hw(hw);
2598         if (status != 0)
2599                 return -1;
2600         hw->mac.ops.start_hw(hw);
2601         hw->mac.get_link_status = true;
2602
2603         /* configure PF module if SRIOV enabled */
2604         ixgbe_pf_host_configure(dev);
2605
2606         ixgbe_dev_phy_intr_setup(dev);
2607
2608         /* check and configure queue intr-vector mapping */
2609         if ((rte_intr_cap_multiple(intr_handle) ||
2610              !RTE_ETH_DEV_SRIOV(dev).active) &&
2611             dev->data->dev_conf.intr_conf.rxq != 0) {
2612                 intr_vector = dev->data->nb_rx_queues;
2613                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2614                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2615                                         IXGBE_MAX_INTR_QUEUE_NUM);
2616                         return -ENOTSUP;
2617                 }
2618                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2619                         return -1;
2620         }
2621
2622         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2623                 intr_handle->intr_vec =
2624                         rte_zmalloc("intr_vec",
2625                                     dev->data->nb_rx_queues * sizeof(int), 0);
2626                 if (intr_handle->intr_vec == NULL) {
2627                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2628                                      " intr_vec", dev->data->nb_rx_queues);
2629                         return -ENOMEM;
2630                 }
2631         }
2632
2633         /* confiugre msix for sleep until rx interrupt */
2634         ixgbe_configure_msix(dev);
2635
2636         /* initialize transmission unit */
2637         ixgbe_dev_tx_init(dev);
2638
2639         /* This can fail when allocating mbufs for descriptor rings */
2640         err = ixgbe_dev_rx_init(dev);
2641         if (err) {
2642                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2643                 goto error;
2644         }
2645
2646         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2647                 ETH_VLAN_EXTEND_MASK;
2648         err = ixgbe_vlan_offload_config(dev, mask);
2649         if (err) {
2650                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2651                 goto error;
2652         }
2653
2654         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2655                 /* Enable vlan filtering for VMDq */
2656                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2657         }
2658
2659         /* Configure DCB hw */
2660         ixgbe_configure_dcb(dev);
2661
2662         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2663                 err = ixgbe_fdir_configure(dev);
2664                 if (err)
2665                         goto error;
2666         }
2667
2668         /* Restore vf rate limit */
2669         if (vfinfo != NULL) {
2670                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2671                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2672                                 if (vfinfo[vf].tx_rate[idx] != 0)
2673                                         ixgbe_set_vf_rate_limit(
2674                                                 dev, vf,
2675                                                 vfinfo[vf].tx_rate[idx],
2676                                                 1 << idx);
2677         }
2678
2679         ixgbe_restore_statistics_mapping(dev);
2680
2681         err = ixgbe_flow_ctrl_enable(dev, hw);
2682         if (err < 0) {
2683                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2684                 goto error;
2685         }
2686
2687         err = ixgbe_dev_rxtx_start(dev);
2688         if (err < 0) {
2689                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2690                 goto error;
2691         }
2692
2693         /* Skip link setup if loopback mode is enabled. */
2694         if (dev->data->dev_conf.lpbk_mode != 0) {
2695                 err = ixgbe_check_supported_loopback_mode(dev);
2696                 if (err < 0) {
2697                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2698                         goto error;
2699                 } else {
2700                         goto skip_link_setup;
2701                 }
2702         }
2703
2704         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2705                 err = hw->mac.ops.setup_sfp(hw);
2706                 if (err)
2707                         goto error;
2708         }
2709
2710         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2711                 /* Turn on the copper */
2712                 ixgbe_set_phy_power(hw, true);
2713         } else {
2714                 /* Turn on the laser */
2715                 ixgbe_enable_tx_laser(hw);
2716         }
2717
2718         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2719         if (err)
2720                 goto error;
2721         dev->data->dev_link.link_status = link_up;
2722
2723         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2724         if (err)
2725                 goto error;
2726
2727         switch (hw->mac.type) {
2728         case ixgbe_mac_X550:
2729         case ixgbe_mac_X550EM_x:
2730         case ixgbe_mac_X550EM_a:
2731                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2732                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2733                         ETH_LINK_SPEED_10G;
2734                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2735                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2736                         allowed_speeds = ETH_LINK_SPEED_10M |
2737                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2738                 break;
2739         default:
2740                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2741                         ETH_LINK_SPEED_10G;
2742         }
2743
2744         link_speeds = &dev->data->dev_conf.link_speeds;
2745
2746         /* Ignore autoneg flag bit and check the validity of
2747          * link_speed
2748          */
2749         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2750                 PMD_INIT_LOG(ERR, "Invalid link setting");
2751                 goto error;
2752         }
2753
2754         speed = 0x0;
2755         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2756                 switch (hw->mac.type) {
2757                 case ixgbe_mac_82598EB:
2758                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2759                         break;
2760                 case ixgbe_mac_82599EB:
2761                 case ixgbe_mac_X540:
2762                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2763                         break;
2764                 case ixgbe_mac_X550:
2765                 case ixgbe_mac_X550EM_x:
2766                 case ixgbe_mac_X550EM_a:
2767                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2768                         break;
2769                 default:
2770                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2771                 }
2772         } else {
2773                 if (*link_speeds & ETH_LINK_SPEED_10G)
2774                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2775                 if (*link_speeds & ETH_LINK_SPEED_5G)
2776                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2777                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2778                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2779                 if (*link_speeds & ETH_LINK_SPEED_1G)
2780                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2781                 if (*link_speeds & ETH_LINK_SPEED_100M)
2782                         speed |= IXGBE_LINK_SPEED_100_FULL;
2783                 if (*link_speeds & ETH_LINK_SPEED_10M)
2784                         speed |= IXGBE_LINK_SPEED_10_FULL;
2785         }
2786
2787         err = ixgbe_setup_link(hw, speed, link_up);
2788         if (err)
2789                 goto error;
2790
2791 skip_link_setup:
2792
2793         if (rte_intr_allow_others(intr_handle)) {
2794                 /* check if lsc interrupt is enabled */
2795                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2796                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2797                 else
2798                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2799                 ixgbe_dev_macsec_interrupt_setup(dev);
2800         } else {
2801                 rte_intr_callback_unregister(intr_handle,
2802                                              ixgbe_dev_interrupt_handler, dev);
2803                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2804                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2805                                      " no intr multiplex");
2806         }
2807
2808         /* check if rxq interrupt is enabled */
2809         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2810             rte_intr_dp_is_en(intr_handle))
2811                 ixgbe_dev_rxq_interrupt_setup(dev);
2812
2813         /* enable uio/vfio intr/eventfd mapping */
2814         rte_intr_enable(intr_handle);
2815
2816         /* resume enabled intr since hw reset */
2817         ixgbe_enable_intr(dev);
2818         ixgbe_l2_tunnel_conf(dev);
2819         ixgbe_filter_restore(dev);
2820
2821         if (tm_conf->root && !tm_conf->committed)
2822                 PMD_DRV_LOG(WARNING,
2823                             "please call hierarchy_commit() "
2824                             "before starting the port");
2825
2826         /* wait for the controller to acquire link */
2827         err = ixgbe_wait_for_link_up(hw);
2828         if (err)
2829                 goto error;
2830
2831         /*
2832          * Update link status right before return, because it may
2833          * start link configuration process in a separate thread.
2834          */
2835         ixgbe_dev_link_update(dev, 0);
2836
2837         /* setup the macsec setting register */
2838         if (macsec_setting->offload_en)
2839                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2840
2841         return 0;
2842
2843 error:
2844         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2845         ixgbe_dev_clear_queues(dev);
2846         return -EIO;
2847 }
2848
2849 /*
2850  * Stop device: disable rx and tx functions to allow for reconfiguring.
2851  */
2852 static int
2853 ixgbe_dev_stop(struct rte_eth_dev *dev)
2854 {
2855         struct rte_eth_link link;
2856         struct ixgbe_adapter *adapter = dev->data->dev_private;
2857         struct ixgbe_hw *hw =
2858                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859         struct ixgbe_vf_info *vfinfo =
2860                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2861         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2862         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2863         int vf;
2864         struct ixgbe_tm_conf *tm_conf =
2865                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2866
2867         if (hw->adapter_stopped)
2868                 return 0;
2869
2870         PMD_INIT_FUNC_TRACE();
2871
2872         ixgbe_dev_wait_setup_link_complete(dev, 0);
2873
2874         /* disable interrupts */
2875         ixgbe_disable_intr(hw);
2876
2877         /* reset the NIC */
2878         ixgbe_pf_reset_hw(hw);
2879         hw->adapter_stopped = 0;
2880
2881         /* stop adapter */
2882         ixgbe_stop_adapter(hw);
2883
2884         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2885                 vfinfo[vf].clear_to_send = false;
2886
2887         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2888                 /* Turn off the copper */
2889                 ixgbe_set_phy_power(hw, false);
2890         } else {
2891                 /* Turn off the laser */
2892                 ixgbe_disable_tx_laser(hw);
2893         }
2894
2895         ixgbe_dev_clear_queues(dev);
2896
2897         /* Clear stored conf */
2898         dev->data->scattered_rx = 0;
2899         dev->data->lro = 0;
2900
2901         /* Clear recorded link status */
2902         memset(&link, 0, sizeof(link));
2903         rte_eth_linkstatus_set(dev, &link);
2904
2905         if (!rte_intr_allow_others(intr_handle))
2906                 /* resume to the default handler */
2907                 rte_intr_callback_register(intr_handle,
2908                                            ixgbe_dev_interrupt_handler,
2909                                            (void *)dev);
2910
2911         /* Clean datapath event and queue/vec mapping */
2912         rte_intr_efd_disable(intr_handle);
2913         if (intr_handle->intr_vec != NULL) {
2914                 rte_free(intr_handle->intr_vec);
2915                 intr_handle->intr_vec = NULL;
2916         }
2917
2918         /* reset hierarchy commit */
2919         tm_conf->committed = false;
2920
2921         adapter->rss_reta_updated = 0;
2922
2923         hw->adapter_stopped = true;
2924         dev->data->dev_started = 0;
2925
2926         return 0;
2927 }
2928
2929 /*
2930  * Set device link up: enable tx.
2931  */
2932 static int
2933 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2934 {
2935         struct ixgbe_hw *hw =
2936                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2937         if (hw->mac.type == ixgbe_mac_82599EB) {
2938 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2939                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2940                         /* Not suported in bypass mode */
2941                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2942                                      "by device id 0x%x", hw->device_id);
2943                         return -ENOTSUP;
2944                 }
2945 #endif
2946         }
2947
2948         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2949                 /* Turn on the copper */
2950                 ixgbe_set_phy_power(hw, true);
2951         } else {
2952                 /* Turn on the laser */
2953                 ixgbe_enable_tx_laser(hw);
2954                 ixgbe_dev_link_update(dev, 0);
2955         }
2956
2957         return 0;
2958 }
2959
2960 /*
2961  * Set device link down: disable tx.
2962  */
2963 static int
2964 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2965 {
2966         struct ixgbe_hw *hw =
2967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968         if (hw->mac.type == ixgbe_mac_82599EB) {
2969 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2970                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2971                         /* Not suported in bypass mode */
2972                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2973                                      "by device id 0x%x", hw->device_id);
2974                         return -ENOTSUP;
2975                 }
2976 #endif
2977         }
2978
2979         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2980                 /* Turn off the copper */
2981                 ixgbe_set_phy_power(hw, false);
2982         } else {
2983                 /* Turn off the laser */
2984                 ixgbe_disable_tx_laser(hw);
2985                 ixgbe_dev_link_update(dev, 0);
2986         }
2987
2988         return 0;
2989 }
2990
2991 /*
2992  * Reset and stop device.
2993  */
2994 static int
2995 ixgbe_dev_close(struct rte_eth_dev *dev)
2996 {
2997         struct ixgbe_hw *hw =
2998                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2999         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3000         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3001         int retries = 0;
3002         int ret;
3003
3004         PMD_INIT_FUNC_TRACE();
3005         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3006                 return 0;
3007
3008         ixgbe_pf_reset_hw(hw);
3009
3010         ret = ixgbe_dev_stop(dev);
3011
3012         ixgbe_dev_free_queues(dev);
3013
3014         ixgbe_disable_pcie_master(hw);
3015
3016         /* reprogram the RAR[0] in case user changed it. */
3017         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3018
3019         /* Unlock any pending hardware semaphore */
3020         ixgbe_swfw_lock_reset(hw);
3021
3022         /* disable uio intr before callback unregister */
3023         rte_intr_disable(intr_handle);
3024
3025         do {
3026                 ret = rte_intr_callback_unregister(intr_handle,
3027                                 ixgbe_dev_interrupt_handler, dev);
3028                 if (ret >= 0 || ret == -ENOENT) {
3029                         break;
3030                 } else if (ret != -EAGAIN) {
3031                         PMD_INIT_LOG(ERR,
3032                                 "intr callback unregister failed: %d",
3033                                 ret);
3034                 }
3035                 rte_delay_ms(100);
3036         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3037
3038         /* cancel the delay handler before remove dev */
3039         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3040
3041         /* uninitialize PF if max_vfs not zero */
3042         ixgbe_pf_host_uninit(dev);
3043
3044         /* remove all the fdir filters & hash */
3045         ixgbe_fdir_filter_uninit(dev);
3046
3047         /* remove all the L2 tunnel filters & hash */
3048         ixgbe_l2_tn_filter_uninit(dev);
3049
3050         /* Remove all ntuple filters of the device */
3051         ixgbe_ntuple_filter_uninit(dev);
3052
3053         /* clear all the filters list */
3054         ixgbe_filterlist_flush();
3055
3056         /* Remove all Traffic Manager configuration */
3057         ixgbe_tm_conf_uninit(dev);
3058
3059 #ifdef RTE_LIB_SECURITY
3060         rte_free(dev->security_ctx);
3061 #endif
3062
3063         return ret;
3064 }
3065
3066 /*
3067  * Reset PF device.
3068  */
3069 static int
3070 ixgbe_dev_reset(struct rte_eth_dev *dev)
3071 {
3072         int ret;
3073
3074         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3075          * its VF to make them align with it. The detailed notification
3076          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3077          * To avoid unexpected behavior in VF, currently reset of PF with
3078          * SR-IOV activation is not supported. It might be supported later.
3079          */
3080         if (dev->data->sriov.active)
3081                 return -ENOTSUP;
3082
3083         ret = eth_ixgbe_dev_uninit(dev);
3084         if (ret)
3085                 return ret;
3086
3087         ret = eth_ixgbe_dev_init(dev, NULL);
3088
3089         return ret;
3090 }
3091
3092 static void
3093 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3094                            struct ixgbe_hw_stats *hw_stats,
3095                            struct ixgbe_macsec_stats *macsec_stats,
3096                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3097                            uint64_t *total_qprc, uint64_t *total_qprdc)
3098 {
3099         uint32_t bprc, lxon, lxoff, total;
3100         uint32_t delta_gprc = 0;
3101         unsigned i;
3102         /* Workaround for RX byte count not including CRC bytes when CRC
3103          * strip is enabled. CRC bytes are removed from counters when crc_strip
3104          * is disabled.
3105          */
3106         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3107                         IXGBE_HLREG0_RXCRCSTRP);
3108
3109         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3110         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3111         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3112         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3113
3114         for (i = 0; i < 8; i++) {
3115                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3116
3117                 /* global total per queue */
3118                 hw_stats->mpc[i] += mp;
3119                 /* Running comprehensive total for stats display */
3120                 *total_missed_rx += hw_stats->mpc[i];
3121                 if (hw->mac.type == ixgbe_mac_82598EB) {
3122                         hw_stats->rnbc[i] +=
3123                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3124                         hw_stats->pxonrxc[i] +=
3125                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3126                         hw_stats->pxoffrxc[i] +=
3127                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3128                 } else {
3129                         hw_stats->pxonrxc[i] +=
3130                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3131                         hw_stats->pxoffrxc[i] +=
3132                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3133                         hw_stats->pxon2offc[i] +=
3134                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3135                 }
3136                 hw_stats->pxontxc[i] +=
3137                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3138                 hw_stats->pxofftxc[i] +=
3139                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3140         }
3141         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3142                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3143                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3144                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3145
3146                 delta_gprc += delta_qprc;
3147
3148                 hw_stats->qprc[i] += delta_qprc;
3149                 hw_stats->qptc[i] += delta_qptc;
3150
3151                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3152                 hw_stats->qbrc[i] +=
3153                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3154                 if (crc_strip == 0)
3155                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3156
3157                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3158                 hw_stats->qbtc[i] +=
3159                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3160
3161                 hw_stats->qprdc[i] += delta_qprdc;
3162                 *total_qprdc += hw_stats->qprdc[i];
3163
3164                 *total_qprc += hw_stats->qprc[i];
3165                 *total_qbrc += hw_stats->qbrc[i];
3166         }
3167         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3168         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3169         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3170
3171         /*
3172          * An errata states that gprc actually counts good + missed packets:
3173          * Workaround to set gprc to summated queue packet receives
3174          */
3175         hw_stats->gprc = *total_qprc;
3176
3177         if (hw->mac.type != ixgbe_mac_82598EB) {
3178                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3179                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3180                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3181                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3182                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3183                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3184                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3185                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3186         } else {
3187                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3188                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3189                 /* 82598 only has a counter in the high register */
3190                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3191                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3192                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3193         }
3194         uint64_t old_tpr = hw_stats->tpr;
3195
3196         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3197         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3198
3199         if (crc_strip == 0)
3200                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3201
3202         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3203         hw_stats->gptc += delta_gptc;
3204         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3205         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3206
3207         /*
3208          * Workaround: mprc hardware is incorrectly counting
3209          * broadcasts, so for now we subtract those.
3210          */
3211         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3212         hw_stats->bprc += bprc;
3213         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3214         if (hw->mac.type == ixgbe_mac_82598EB)
3215                 hw_stats->mprc -= bprc;
3216
3217         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3218         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3219         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3220         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3221         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3222         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3223
3224         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3225         hw_stats->lxontxc += lxon;
3226         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3227         hw_stats->lxofftxc += lxoff;
3228         total = lxon + lxoff;
3229
3230         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3231         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3232         hw_stats->gptc -= total;
3233         hw_stats->mptc -= total;
3234         hw_stats->ptc64 -= total;
3235         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3236
3237         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3238         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3239         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3240         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3241         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3242         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3243         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3244         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3245         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3246         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3247         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3248         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3249         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3250         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3251         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3252         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3253         /* Only read FCOE on 82599 */
3254         if (hw->mac.type != ixgbe_mac_82598EB) {
3255                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3256                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3257                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3258                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3259                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3260         }
3261
3262         /* Flow Director Stats registers */
3263         if (hw->mac.type != ixgbe_mac_82598EB) {
3264                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3265                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3266                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3267                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3268                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3269                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3270                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3271                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3272                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3273                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3274         }
3275         /* MACsec Stats registers */
3276         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3277         macsec_stats->out_pkts_encrypted +=
3278                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3279         macsec_stats->out_pkts_protected +=
3280                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3281         macsec_stats->out_octets_encrypted +=
3282                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3283         macsec_stats->out_octets_protected +=
3284                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3285         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3286         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3287         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3288         macsec_stats->in_pkts_unknownsci +=
3289                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3290         macsec_stats->in_octets_decrypted +=
3291                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3292         macsec_stats->in_octets_validated +=
3293                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3294         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3295         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3296         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3297         for (i = 0; i < 2; i++) {
3298                 macsec_stats->in_pkts_ok +=
3299                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3300                 macsec_stats->in_pkts_invalid +=
3301                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3302                 macsec_stats->in_pkts_notvalid +=
3303                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3304         }
3305         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3306         macsec_stats->in_pkts_notusingsa +=
3307                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3308 }
3309
3310 /*
3311  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3312  */
3313 static int
3314 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3315 {
3316         struct ixgbe_hw *hw =
3317                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318         struct ixgbe_hw_stats *hw_stats =
3319                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3320         struct ixgbe_macsec_stats *macsec_stats =
3321                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3322                                 dev->data->dev_private);
3323         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3324         unsigned i;
3325
3326         total_missed_rx = 0;
3327         total_qbrc = 0;
3328         total_qprc = 0;
3329         total_qprdc = 0;
3330
3331         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3332                         &total_qbrc, &total_qprc, &total_qprdc);
3333
3334         if (stats == NULL)
3335                 return -EINVAL;
3336
3337         /* Fill out the rte_eth_stats statistics structure */
3338         stats->ipackets = total_qprc;
3339         stats->ibytes = total_qbrc;
3340         stats->opackets = hw_stats->gptc;
3341         stats->obytes = hw_stats->gotc;
3342
3343         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3344                 stats->q_ipackets[i] = hw_stats->qprc[i];
3345                 stats->q_opackets[i] = hw_stats->qptc[i];
3346                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3347                 stats->q_obytes[i] = hw_stats->qbtc[i];
3348                 stats->q_errors[i] = hw_stats->qprdc[i];
3349         }
3350
3351         /* Rx Errors */
3352         stats->imissed  = total_missed_rx;
3353         stats->ierrors  = hw_stats->crcerrs +
3354                           hw_stats->mspdc +
3355                           hw_stats->rlec +
3356                           hw_stats->ruc +
3357                           hw_stats->roc +
3358                           hw_stats->illerrc +
3359                           hw_stats->errbc +
3360                           hw_stats->rfc +
3361                           hw_stats->fccrc +
3362                           hw_stats->fclast;
3363
3364         /* Tx Errors */
3365         stats->oerrors  = 0;
3366         return 0;
3367 }
3368
3369 static int
3370 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3371 {
3372         struct ixgbe_hw_stats *stats =
3373                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3374
3375         /* HW registers are cleared on read */
3376         ixgbe_dev_stats_get(dev, NULL);
3377
3378         /* Reset software totals */
3379         memset(stats, 0, sizeof(*stats));
3380
3381         return 0;
3382 }
3383
3384 /* This function calculates the number of xstats based on the current config */
3385 static unsigned
3386 ixgbe_xstats_calc_num(void) {
3387         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3388                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3389                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3390 }
3391
3392 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3393         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3394 {
3395         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3396         unsigned stat, i, count;
3397
3398         if (xstats_names != NULL) {
3399                 count = 0;
3400
3401                 /* Note: limit >= cnt_stats checked upstream
3402                  * in rte_eth_xstats_names()
3403                  */
3404
3405                 /* Extended stats from ixgbe_hw_stats */
3406                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3407                         strlcpy(xstats_names[count].name,
3408                                 rte_ixgbe_stats_strings[i].name,
3409                                 sizeof(xstats_names[count].name));
3410                         count++;
3411                 }
3412
3413                 /* MACsec Stats */
3414                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3415                         strlcpy(xstats_names[count].name,
3416                                 rte_ixgbe_macsec_strings[i].name,
3417                                 sizeof(xstats_names[count].name));
3418                         count++;
3419                 }
3420
3421                 /* RX Priority Stats */
3422                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3423                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3424                                 snprintf(xstats_names[count].name,
3425                                         sizeof(xstats_names[count].name),
3426                                         "rx_priority%u_%s", i,
3427                                         rte_ixgbe_rxq_strings[stat].name);
3428                                 count++;
3429                         }
3430                 }
3431
3432                 /* TX Priority Stats */
3433                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3434                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3435                                 snprintf(xstats_names[count].name,
3436                                         sizeof(xstats_names[count].name),
3437                                         "tx_priority%u_%s", i,
3438                                         rte_ixgbe_txq_strings[stat].name);
3439                                 count++;
3440                         }
3441                 }
3442         }
3443         return cnt_stats;
3444 }
3445
3446 static int ixgbe_dev_xstats_get_names_by_id(
3447         struct rte_eth_dev *dev,
3448         struct rte_eth_xstat_name *xstats_names,
3449         const uint64_t *ids,
3450         unsigned int limit)
3451 {
3452         if (!ids) {
3453                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3454                 unsigned int stat, i, count;
3455
3456                 if (xstats_names != NULL) {
3457                         count = 0;
3458
3459                         /* Note: limit >= cnt_stats checked upstream
3460                          * in rte_eth_xstats_names()
3461                          */
3462
3463                         /* Extended stats from ixgbe_hw_stats */
3464                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3465                                 strlcpy(xstats_names[count].name,
3466                                         rte_ixgbe_stats_strings[i].name,
3467                                         sizeof(xstats_names[count].name));
3468                                 count++;
3469                         }
3470
3471                         /* MACsec Stats */
3472                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3473                                 strlcpy(xstats_names[count].name,
3474                                         rte_ixgbe_macsec_strings[i].name,
3475                                         sizeof(xstats_names[count].name));
3476                                 count++;
3477                         }
3478
3479                         /* RX Priority Stats */
3480                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3481                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3482                                         snprintf(xstats_names[count].name,
3483                                             sizeof(xstats_names[count].name),
3484                                             "rx_priority%u_%s", i,
3485                                             rte_ixgbe_rxq_strings[stat].name);
3486                                         count++;
3487                                 }
3488                         }
3489
3490                         /* TX Priority Stats */
3491                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3492                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3493                                         snprintf(xstats_names[count].name,
3494                                             sizeof(xstats_names[count].name),
3495                                             "tx_priority%u_%s", i,
3496                                             rte_ixgbe_txq_strings[stat].name);
3497                                         count++;
3498                                 }
3499                         }
3500                 }
3501                 return cnt_stats;
3502         }
3503
3504         uint16_t i;
3505         uint16_t size = ixgbe_xstats_calc_num();
3506         struct rte_eth_xstat_name xstats_names_copy[size];
3507
3508         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3509                         size);
3510
3511         for (i = 0; i < limit; i++) {
3512                 if (ids[i] >= size) {
3513                         PMD_INIT_LOG(ERR, "id value isn't valid");
3514                         return -1;
3515                 }
3516                 strcpy(xstats_names[i].name,
3517                                 xstats_names_copy[ids[i]].name);
3518         }
3519         return limit;
3520 }
3521
3522 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3523         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3524 {
3525         unsigned i;
3526
3527         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3528                 return -ENOMEM;
3529
3530         if (xstats_names != NULL)
3531                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3532                         strlcpy(xstats_names[i].name,
3533                                 rte_ixgbevf_stats_strings[i].name,
3534                                 sizeof(xstats_names[i].name));
3535         return IXGBEVF_NB_XSTATS;
3536 }
3537
3538 static int
3539 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3540                                          unsigned n)
3541 {
3542         struct ixgbe_hw *hw =
3543                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3544         struct ixgbe_hw_stats *hw_stats =
3545                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3546         struct ixgbe_macsec_stats *macsec_stats =
3547                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3548                                 dev->data->dev_private);
3549         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3550         unsigned i, stat, count = 0;
3551
3552         count = ixgbe_xstats_calc_num();
3553
3554         if (n < count)
3555                 return count;
3556
3557         total_missed_rx = 0;
3558         total_qbrc = 0;
3559         total_qprc = 0;
3560         total_qprdc = 0;
3561
3562         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3563                         &total_qbrc, &total_qprc, &total_qprdc);
3564
3565         /* If this is a reset xstats is NULL, and we have cleared the
3566          * registers by reading them.
3567          */
3568         if (!xstats)
3569                 return 0;
3570
3571         /* Extended stats from ixgbe_hw_stats */
3572         count = 0;
3573         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3574                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3575                                 rte_ixgbe_stats_strings[i].offset);
3576                 xstats[count].id = count;
3577                 count++;
3578         }
3579
3580         /* MACsec Stats */
3581         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3582                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3583                                 rte_ixgbe_macsec_strings[i].offset);
3584                 xstats[count].id = count;
3585                 count++;
3586         }
3587
3588         /* RX Priority Stats */
3589         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3590                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3591                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3592                                         rte_ixgbe_rxq_strings[stat].offset +
3593                                         (sizeof(uint64_t) * i));
3594                         xstats[count].id = count;
3595                         count++;
3596                 }
3597         }
3598
3599         /* TX Priority Stats */
3600         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3601                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3602                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3603                                         rte_ixgbe_txq_strings[stat].offset +
3604                                         (sizeof(uint64_t) * i));
3605                         xstats[count].id = count;
3606                         count++;
3607                 }
3608         }
3609         return count;
3610 }
3611
3612 static int
3613 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3614                 uint64_t *values, unsigned int n)
3615 {
3616         if (!ids) {
3617                 struct ixgbe_hw *hw =
3618                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619                 struct ixgbe_hw_stats *hw_stats =
3620                                 IXGBE_DEV_PRIVATE_TO_STATS(
3621                                                 dev->data->dev_private);
3622                 struct ixgbe_macsec_stats *macsec_stats =
3623                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3624                                         dev->data->dev_private);
3625                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3626                 unsigned int i, stat, count = 0;
3627
3628                 count = ixgbe_xstats_calc_num();
3629
3630                 if (!ids && n < count)
3631                         return count;
3632
3633                 total_missed_rx = 0;
3634                 total_qbrc = 0;
3635                 total_qprc = 0;
3636                 total_qprdc = 0;
3637
3638                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3639                                 &total_missed_rx, &total_qbrc, &total_qprc,
3640                                 &total_qprdc);
3641
3642                 /* If this is a reset xstats is NULL, and we have cleared the
3643                  * registers by reading them.
3644                  */
3645                 if (!ids && !values)
3646                         return 0;
3647
3648                 /* Extended stats from ixgbe_hw_stats */
3649                 count = 0;
3650                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3651                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3652                                         rte_ixgbe_stats_strings[i].offset);
3653                         count++;
3654                 }
3655
3656                 /* MACsec Stats */
3657                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3658                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3659                                         rte_ixgbe_macsec_strings[i].offset);
3660                         count++;
3661                 }
3662
3663                 /* RX Priority Stats */
3664                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3665                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3666                                 values[count] =
3667                                         *(uint64_t *)(((char *)hw_stats) +
3668                                         rte_ixgbe_rxq_strings[stat].offset +
3669                                         (sizeof(uint64_t) * i));
3670                                 count++;
3671                         }
3672                 }
3673
3674                 /* TX Priority Stats */
3675                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3676                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3677                                 values[count] =
3678                                         *(uint64_t *)(((char *)hw_stats) +
3679                                         rte_ixgbe_txq_strings[stat].offset +
3680                                         (sizeof(uint64_t) * i));
3681                                 count++;
3682                         }
3683                 }
3684                 return count;
3685         }
3686
3687         uint16_t i;
3688         uint16_t size = ixgbe_xstats_calc_num();
3689         uint64_t values_copy[size];
3690
3691         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3692
3693         for (i = 0; i < n; i++) {
3694                 if (ids[i] >= size) {
3695                         PMD_INIT_LOG(ERR, "id value isn't valid");
3696                         return -1;
3697                 }
3698                 values[i] = values_copy[ids[i]];
3699         }
3700         return n;
3701 }
3702
3703 static int
3704 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3705 {
3706         struct ixgbe_hw_stats *stats =
3707                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3708         struct ixgbe_macsec_stats *macsec_stats =
3709                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3710                                 dev->data->dev_private);
3711
3712         unsigned count = ixgbe_xstats_calc_num();
3713
3714         /* HW registers are cleared on read */
3715         ixgbe_dev_xstats_get(dev, NULL, count);
3716
3717         /* Reset software totals */
3718         memset(stats, 0, sizeof(*stats));
3719         memset(macsec_stats, 0, sizeof(*macsec_stats));
3720
3721         return 0;
3722 }
3723
3724 static void
3725 ixgbevf_update_stats(struct rte_eth_dev *dev)
3726 {
3727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3729                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3730
3731         /* Good Rx packet, include VF loopback */
3732         UPDATE_VF_STAT(IXGBE_VFGPRC,
3733             hw_stats->last_vfgprc, hw_stats->vfgprc);
3734
3735         /* Good Rx octets, include VF loopback */
3736         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3737             hw_stats->last_vfgorc, hw_stats->vfgorc);
3738
3739         /* Good Tx packet, include VF loopback */
3740         UPDATE_VF_STAT(IXGBE_VFGPTC,
3741             hw_stats->last_vfgptc, hw_stats->vfgptc);
3742
3743         /* Good Tx octets, include VF loopback */
3744         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3745             hw_stats->last_vfgotc, hw_stats->vfgotc);
3746
3747         /* Rx Multicst Packet */
3748         UPDATE_VF_STAT(IXGBE_VFMPRC,
3749             hw_stats->last_vfmprc, hw_stats->vfmprc);
3750 }
3751
3752 static int
3753 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3754                        unsigned n)
3755 {
3756         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3757                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3758         unsigned i;
3759
3760         if (n < IXGBEVF_NB_XSTATS)
3761                 return IXGBEVF_NB_XSTATS;
3762
3763         ixgbevf_update_stats(dev);
3764
3765         if (!xstats)
3766                 return 0;
3767
3768         /* Extended stats */
3769         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3770                 xstats[i].id = i;
3771                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3772                         rte_ixgbevf_stats_strings[i].offset);
3773         }
3774
3775         return IXGBEVF_NB_XSTATS;
3776 }
3777
3778 static int
3779 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3780 {
3781         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3782                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3783
3784         ixgbevf_update_stats(dev);
3785
3786         if (stats == NULL)
3787                 return -EINVAL;
3788
3789         stats->ipackets = hw_stats->vfgprc;
3790         stats->ibytes = hw_stats->vfgorc;
3791         stats->opackets = hw_stats->vfgptc;
3792         stats->obytes = hw_stats->vfgotc;
3793         return 0;
3794 }
3795
3796 static int
3797 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3798 {
3799         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3800                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3801
3802         /* Sync HW register to the last stats */
3803         ixgbevf_dev_stats_get(dev, NULL);
3804
3805         /* reset HW current stats*/
3806         hw_stats->vfgprc = 0;
3807         hw_stats->vfgorc = 0;
3808         hw_stats->vfgptc = 0;
3809         hw_stats->vfgotc = 0;
3810
3811         return 0;
3812 }
3813
3814 static int
3815 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3816 {
3817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3818         u16 eeprom_verh, eeprom_verl;
3819         u32 etrack_id;
3820         int ret;
3821
3822         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3823         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3824
3825         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3826         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3827
3828         ret += 1; /* add the size of '\0' */
3829         if (fw_size < (u32)ret)
3830                 return ret;
3831         else
3832                 return 0;
3833 }
3834
3835 static int
3836 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3837 {
3838         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3841
3842         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3843         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3844         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3845                 /*
3846                  * When DCB/VT is off, maximum number of queues changes,
3847                  * except for 82598EB, which remains constant.
3848                  */
3849                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3850                                 hw->mac.type != ixgbe_mac_82598EB)
3851                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3852         }
3853         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3854         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3855         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3856         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3857         dev_info->max_vfs = pci_dev->max_vfs;
3858         if (hw->mac.type == ixgbe_mac_82598EB)
3859                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3860         else
3861                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3862         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3863         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3864         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3865         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3866         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3867                                      dev_info->rx_queue_offload_capa);
3868         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3869         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3870
3871         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3872                 .rx_thresh = {
3873                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3874                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3875                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3876                 },
3877                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3878                 .rx_drop_en = 0,
3879                 .offloads = 0,
3880         };
3881
3882         dev_info->default_txconf = (struct rte_eth_txconf) {
3883                 .tx_thresh = {
3884                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3885                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3886                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3887                 },
3888                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3889                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3890                 .offloads = 0,
3891         };
3892
3893         dev_info->rx_desc_lim = rx_desc_lim;
3894         dev_info->tx_desc_lim = tx_desc_lim;
3895
3896         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3897         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3898         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3899
3900         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3901         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3902                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3903                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3904                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3905
3906         if (hw->mac.type == ixgbe_mac_X540 ||
3907             hw->mac.type == ixgbe_mac_X540_vf ||
3908             hw->mac.type == ixgbe_mac_X550 ||
3909             hw->mac.type == ixgbe_mac_X550_vf) {
3910                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3911         }
3912         if (hw->mac.type == ixgbe_mac_X550) {
3913                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3914                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3915         }
3916
3917         /* Driver-preferred Rx/Tx parameters */
3918         dev_info->default_rxportconf.burst_size = 32;
3919         dev_info->default_txportconf.burst_size = 32;
3920         dev_info->default_rxportconf.nb_queues = 1;
3921         dev_info->default_txportconf.nb_queues = 1;
3922         dev_info->default_rxportconf.ring_size = 256;
3923         dev_info->default_txportconf.ring_size = 256;
3924
3925         return 0;
3926 }
3927
3928 static const uint32_t *
3929 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3930 {
3931         static const uint32_t ptypes[] = {
3932                 /* For non-vec functions,
3933                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3934                  * for vec functions,
3935                  * refers to _recv_raw_pkts_vec().
3936                  */
3937                 RTE_PTYPE_L2_ETHER,
3938                 RTE_PTYPE_L3_IPV4,
3939                 RTE_PTYPE_L3_IPV4_EXT,
3940                 RTE_PTYPE_L3_IPV6,
3941                 RTE_PTYPE_L3_IPV6_EXT,
3942                 RTE_PTYPE_L4_SCTP,
3943                 RTE_PTYPE_L4_TCP,
3944                 RTE_PTYPE_L4_UDP,
3945                 RTE_PTYPE_TUNNEL_IP,
3946                 RTE_PTYPE_INNER_L3_IPV6,
3947                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3948                 RTE_PTYPE_INNER_L4_TCP,
3949                 RTE_PTYPE_INNER_L4_UDP,
3950                 RTE_PTYPE_UNKNOWN
3951         };
3952
3953         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3954             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3955             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3956             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3957                 return ptypes;
3958
3959 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3960         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3961             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3962                 return ptypes;
3963 #endif
3964         return NULL;
3965 }
3966
3967 static int
3968 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3969                      struct rte_eth_dev_info *dev_info)
3970 {
3971         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973
3974         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3975         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3976         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3977         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3978         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3979         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3980         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3981         dev_info->max_vfs = pci_dev->max_vfs;
3982         if (hw->mac.type == ixgbe_mac_82598EB)
3983                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3984         else
3985                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3986         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3987         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3988                                      dev_info->rx_queue_offload_capa);
3989         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3990         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3991         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3992         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3993         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3994
3995         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3996                 .rx_thresh = {
3997                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3998                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3999                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4000                 },
4001                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4002                 .rx_drop_en = 0,
4003                 .offloads = 0,
4004         };
4005
4006         dev_info->default_txconf = (struct rte_eth_txconf) {
4007                 .tx_thresh = {
4008                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4009                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4010                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4011                 },
4012                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4013                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4014                 .offloads = 0,
4015         };
4016
4017         dev_info->rx_desc_lim = rx_desc_lim;
4018         dev_info->tx_desc_lim = tx_desc_lim;
4019
4020         return 0;
4021 }
4022
4023 static int
4024 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4025                    bool *link_up, int wait_to_complete)
4026 {
4027         struct ixgbe_adapter *adapter = container_of(hw,
4028                                                      struct ixgbe_adapter, hw);
4029         struct ixgbe_mbx_info *mbx = &hw->mbx;
4030         struct ixgbe_mac_info *mac = &hw->mac;
4031         uint32_t links_reg, in_msg;
4032         int ret_val = 0;
4033
4034         /* If we were hit with a reset drop the link */
4035         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4036                 mac->get_link_status = true;
4037
4038         if (!mac->get_link_status)
4039                 goto out;
4040
4041         /* if link status is down no point in checking to see if pf is up */
4042         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4043         if (!(links_reg & IXGBE_LINKS_UP))
4044                 goto out;
4045
4046         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4047          * before the link status is correct
4048          */
4049         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4050                 int i;
4051
4052                 for (i = 0; i < 5; i++) {
4053                         rte_delay_us(100);
4054                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4055
4056                         if (!(links_reg & IXGBE_LINKS_UP))
4057                                 goto out;
4058                 }
4059         }
4060
4061         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4062         case IXGBE_LINKS_SPEED_10G_82599:
4063                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4064                 if (hw->mac.type >= ixgbe_mac_X550) {
4065                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4066                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4067                 }
4068                 break;
4069         case IXGBE_LINKS_SPEED_1G_82599:
4070                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4071                 break;
4072         case IXGBE_LINKS_SPEED_100_82599:
4073                 *speed = IXGBE_LINK_SPEED_100_FULL;
4074                 if (hw->mac.type == ixgbe_mac_X550) {
4075                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4076                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4077                 }
4078                 break;
4079         case IXGBE_LINKS_SPEED_10_X550EM_A:
4080                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4081                 /* Since Reserved in older MAC's */
4082                 if (hw->mac.type >= ixgbe_mac_X550)
4083                         *speed = IXGBE_LINK_SPEED_10_FULL;
4084                 break;
4085         default:
4086                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4087         }
4088
4089         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4090                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4091                         mac->get_link_status = true;
4092                 else
4093                         mac->get_link_status = false;
4094
4095                 goto out;
4096         }
4097
4098         /* if the read failed it could just be a mailbox collision, best wait
4099          * until we are called again and don't report an error
4100          */
4101         if (mbx->ops.read(hw, &in_msg, 1, 0))
4102                 goto out;
4103
4104         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4105                 /* msg is not CTS and is NACK we must have lost CTS status */
4106                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4107                         mac->get_link_status = false;
4108                 goto out;
4109         }
4110
4111         /* the pf is talking, if we timed out in the past we reinit */
4112         if (!mbx->timeout) {
4113                 ret_val = -1;
4114                 goto out;
4115         }
4116
4117         /* if we passed all the tests above then the link is up and we no
4118          * longer need to check for link
4119          */
4120         mac->get_link_status = false;
4121
4122 out:
4123         *link_up = !mac->get_link_status;
4124         return ret_val;
4125 }
4126
4127 /*
4128  * If @timeout_ms was 0, it means that it will not return until link complete.
4129  * It returns 1 on complete, return 0 on timeout.
4130  */
4131 static int
4132 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4133 {
4134 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4135         struct ixgbe_adapter *ad = dev->data->dev_private;
4136         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4137
4138         while (rte_atomic32_read(&ad->link_thread_running)) {
4139                 msec_delay(1);
4140                 timeout--;
4141
4142                 if (timeout_ms) {
4143                         if (!timeout)
4144                                 return 0;
4145                 } else if (!timeout) {
4146                         /* It will not return until link complete */
4147                         timeout = WARNING_TIMEOUT;
4148                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4149                 }
4150         }
4151
4152         return 1;
4153 }
4154
4155 static void *
4156 ixgbe_dev_setup_link_thread_handler(void *param)
4157 {
4158         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4159         struct ixgbe_adapter *ad = dev->data->dev_private;
4160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4161         struct ixgbe_interrupt *intr =
4162                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4163         u32 speed;
4164         bool autoneg = false;
4165
4166         pthread_detach(pthread_self());
4167         speed = hw->phy.autoneg_advertised;
4168         if (!speed)
4169                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4170
4171         ixgbe_setup_link(hw, speed, true);
4172
4173         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4174         rte_atomic32_clear(&ad->link_thread_running);
4175         return NULL;
4176 }
4177
4178 /*
4179  * In freebsd environment, nic_uio drivers do not support interrupts,
4180  * rte_intr_callback_register() will fail to register interrupts.
4181  * We can not make link status to change from down to up by interrupt
4182  * callback. So we need to wait for the controller to acquire link
4183  * when ports start.
4184  * It returns 0 on link up.
4185  */
4186 static int
4187 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4188 {
4189 #ifdef RTE_EXEC_ENV_FREEBSD
4190         int err, i;
4191         bool link_up = false;
4192         uint32_t speed = 0;
4193         const int nb_iter = 25;
4194
4195         for (i = 0; i < nb_iter; i++) {
4196                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4197                 if (err)
4198                         return err;
4199                 if (link_up)
4200                         return 0;
4201                 msec_delay(200);
4202         }
4203
4204         return 0;
4205 #else
4206         RTE_SET_USED(hw);
4207         return 0;
4208 #endif
4209 }
4210
4211 /* return 0 means link status changed, -1 means not changed */
4212 int
4213 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4214                             int wait_to_complete, int vf)
4215 {
4216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4217         struct ixgbe_adapter *ad = dev->data->dev_private;
4218         struct rte_eth_link link;
4219         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4220         struct ixgbe_interrupt *intr =
4221                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4222         bool link_up;
4223         int diag;
4224         int wait = 1;
4225         u32 esdp_reg;
4226
4227         memset(&link, 0, sizeof(link));
4228         link.link_status = ETH_LINK_DOWN;
4229         link.link_speed = ETH_SPEED_NUM_NONE;
4230         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4231         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4232                         ETH_LINK_SPEED_FIXED);
4233
4234         hw->mac.get_link_status = true;
4235
4236         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4237                 return rte_eth_linkstatus_set(dev, &link);
4238
4239         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4240         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4241                 wait = 0;
4242
4243 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4244 #ifdef RTE_EXEC_ENV_FREEBSD
4245         wait = 1;
4246 #endif
4247
4248         if (vf)
4249                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4250         else
4251                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4252
4253         if (diag != 0) {
4254                 link.link_speed = ETH_SPEED_NUM_100M;
4255                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4256                 return rte_eth_linkstatus_set(dev, &link);
4257         }
4258
4259         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4260                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4261                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4262                         link_up = 0;
4263         }
4264
4265         if (link_up == 0) {
4266                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4267                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4268                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4269                                 /* To avoid race condition between threads, set
4270                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4271                                  * when there is no link thread running.
4272                                  */
4273                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4274                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4275                                         "ixgbe-link-handler",
4276                                         NULL,
4277                                         ixgbe_dev_setup_link_thread_handler,
4278                                         dev) < 0) {
4279                                         PMD_DRV_LOG(ERR,
4280                                                 "Create link thread failed!");
4281                                         rte_atomic32_clear(&ad->link_thread_running);
4282                                 }
4283                         } else {
4284                                 PMD_DRV_LOG(ERR,
4285                                         "Other link thread is running now!");
4286                         }
4287                 }
4288                 return rte_eth_linkstatus_set(dev, &link);
4289         }
4290
4291         link.link_status = ETH_LINK_UP;
4292         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4293
4294         switch (link_speed) {
4295         default:
4296         case IXGBE_LINK_SPEED_UNKNOWN:
4297                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4298                 break;
4299
4300         case IXGBE_LINK_SPEED_10_FULL:
4301                 link.link_speed = ETH_SPEED_NUM_10M;
4302                 break;
4303
4304         case IXGBE_LINK_SPEED_100_FULL:
4305                 link.link_speed = ETH_SPEED_NUM_100M;
4306                 break;
4307
4308         case IXGBE_LINK_SPEED_1GB_FULL:
4309                 link.link_speed = ETH_SPEED_NUM_1G;
4310                 break;
4311
4312         case IXGBE_LINK_SPEED_2_5GB_FULL:
4313                 link.link_speed = ETH_SPEED_NUM_2_5G;
4314                 break;
4315
4316         case IXGBE_LINK_SPEED_5GB_FULL:
4317                 link.link_speed = ETH_SPEED_NUM_5G;
4318                 break;
4319
4320         case IXGBE_LINK_SPEED_10GB_FULL:
4321                 link.link_speed = ETH_SPEED_NUM_10G;
4322                 break;
4323         }
4324
4325         return rte_eth_linkstatus_set(dev, &link);
4326 }
4327
4328 static int
4329 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4330 {
4331         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4332 }
4333
4334 static int
4335 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4336 {
4337         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4338 }
4339
4340 static int
4341 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4342 {
4343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4344         uint32_t fctrl;
4345
4346         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4347         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4348         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4349
4350         return 0;
4351 }
4352
4353 static int
4354 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4355 {
4356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357         uint32_t fctrl;
4358
4359         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4360         fctrl &= (~IXGBE_FCTRL_UPE);
4361         if (dev->data->all_multicast == 1)
4362                 fctrl |= IXGBE_FCTRL_MPE;
4363         else
4364                 fctrl &= (~IXGBE_FCTRL_MPE);
4365         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4366
4367         return 0;
4368 }
4369
4370 static int
4371 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4372 {
4373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4374         uint32_t fctrl;
4375
4376         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4377         fctrl |= IXGBE_FCTRL_MPE;
4378         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4379
4380         return 0;
4381 }
4382
4383 static int
4384 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4385 {
4386         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4387         uint32_t fctrl;
4388
4389         if (dev->data->promiscuous == 1)
4390                 return 0; /* must remain in all_multicast mode */
4391
4392         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4393         fctrl &= (~IXGBE_FCTRL_MPE);
4394         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4395
4396         return 0;
4397 }
4398
4399 /**
4400  * It clears the interrupt causes and enables the interrupt.
4401  * It will be called once only during nic initialized.
4402  *
4403  * @param dev
4404  *  Pointer to struct rte_eth_dev.
4405  * @param on
4406  *  Enable or Disable.
4407  *
4408  * @return
4409  *  - On success, zero.
4410  *  - On failure, a negative value.
4411  */
4412 static int
4413 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4414 {
4415         struct ixgbe_interrupt *intr =
4416                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4417
4418         ixgbe_dev_link_status_print(dev);
4419         if (on)
4420                 intr->mask |= IXGBE_EICR_LSC;
4421         else
4422                 intr->mask &= ~IXGBE_EICR_LSC;
4423
4424         return 0;
4425 }
4426
4427 /**
4428  * It clears the interrupt causes and enables the interrupt.
4429  * It will be called once only during nic initialized.
4430  *
4431  * @param dev
4432  *  Pointer to struct rte_eth_dev.
4433  *
4434  * @return
4435  *  - On success, zero.
4436  *  - On failure, a negative value.
4437  */
4438 static int
4439 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4440 {
4441         struct ixgbe_interrupt *intr =
4442                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4443
4444         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4445
4446         return 0;
4447 }
4448
4449 /**
4450  * It clears the interrupt causes and enables the interrupt.
4451  * It will be called once only during nic initialized.
4452  *
4453  * @param dev
4454  *  Pointer to struct rte_eth_dev.
4455  *
4456  * @return
4457  *  - On success, zero.
4458  *  - On failure, a negative value.
4459  */
4460 static int
4461 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4462 {
4463         struct ixgbe_interrupt *intr =
4464                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4465
4466         intr->mask |= IXGBE_EICR_LINKSEC;
4467
4468         return 0;
4469 }
4470
4471 /*
4472  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4473  *
4474  * @param dev
4475  *  Pointer to struct rte_eth_dev.
4476  *
4477  * @return
4478  *  - On success, zero.
4479  *  - On failure, a negative value.
4480  */
4481 static int
4482 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4483 {
4484         uint32_t eicr;
4485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4486         struct ixgbe_interrupt *intr =
4487                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4488
4489         /* clear all cause mask */
4490         ixgbe_disable_intr(hw);
4491
4492         /* read-on-clear nic registers here */
4493         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4494         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4495
4496         intr->flags = 0;
4497
4498         /* set flag for async link update */
4499         if (eicr & IXGBE_EICR_LSC)
4500                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4501
4502         if (eicr & IXGBE_EICR_MAILBOX)
4503                 intr->flags |= IXGBE_FLAG_MAILBOX;
4504
4505         if (eicr & IXGBE_EICR_LINKSEC)
4506                 intr->flags |= IXGBE_FLAG_MACSEC;
4507
4508         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4509             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4510             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4511                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4512
4513         return 0;
4514 }
4515
4516 /**
4517  * It gets and then prints the link status.
4518  *
4519  * @param dev
4520  *  Pointer to struct rte_eth_dev.
4521  *
4522  * @return
4523  *  - On success, zero.
4524  *  - On failure, a negative value.
4525  */
4526 static void
4527 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4528 {
4529         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4530         struct rte_eth_link link;
4531
4532         rte_eth_linkstatus_get(dev, &link);
4533
4534         if (link.link_status) {
4535                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4536                                         (int)(dev->data->port_id),
4537                                         (unsigned)link.link_speed,
4538                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4539                                         "full-duplex" : "half-duplex");
4540         } else {
4541                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4542                                 (int)(dev->data->port_id));
4543         }
4544         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4545                                 pci_dev->addr.domain,
4546                                 pci_dev->addr.bus,
4547                                 pci_dev->addr.devid,
4548                                 pci_dev->addr.function);
4549 }
4550
4551 /*
4552  * It executes link_update after knowing an interrupt occurred.
4553  *
4554  * @param dev
4555  *  Pointer to struct rte_eth_dev.
4556  *
4557  * @return
4558  *  - On success, zero.
4559  *  - On failure, a negative value.
4560  */
4561 static int
4562 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4563 {
4564         struct ixgbe_interrupt *intr =
4565                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4566         int64_t timeout;
4567         struct ixgbe_hw *hw =
4568                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4569
4570         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4571
4572         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4573                 ixgbe_pf_mbx_process(dev);
4574                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4575         }
4576
4577         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4578                 ixgbe_handle_lasi(hw);
4579                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4580         }
4581
4582         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4583                 struct rte_eth_link link;
4584
4585                 /* get the link status before link update, for predicting later */
4586                 rte_eth_linkstatus_get(dev, &link);
4587
4588                 ixgbe_dev_link_update(dev, 0);
4589
4590                 /* likely to up */
4591                 if (!link.link_status)
4592                         /* handle it 1 sec later, wait it being stable */
4593                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4594                 /* likely to down */
4595                 else
4596                         /* handle it 4 sec later, wait it being stable */
4597                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4598
4599                 ixgbe_dev_link_status_print(dev);
4600                 if (rte_eal_alarm_set(timeout * 1000,
4601                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4602                         PMD_DRV_LOG(ERR, "Error setting alarm");
4603                 else {
4604                         /* remember original mask */
4605                         intr->mask_original = intr->mask;
4606                         /* only disable lsc interrupt */
4607                         intr->mask &= ~IXGBE_EIMS_LSC;
4608                 }
4609         }
4610
4611         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4612         ixgbe_enable_intr(dev);
4613
4614         return 0;
4615 }
4616
4617 /**
4618  * Interrupt handler which shall be registered for alarm callback for delayed
4619  * handling specific interrupt to wait for the stable nic state. As the
4620  * NIC interrupt state is not stable for ixgbe after link is just down,
4621  * it needs to wait 4 seconds to get the stable status.
4622  *
4623  * @param handle
4624  *  Pointer to interrupt handle.
4625  * @param param
4626  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4627  *
4628  * @return
4629  *  void
4630  */
4631 static void
4632 ixgbe_dev_interrupt_delayed_handler(void *param)
4633 {
4634         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4635         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4636         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4637         struct ixgbe_interrupt *intr =
4638                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4639         struct ixgbe_hw *hw =
4640                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4641         uint32_t eicr;
4642
4643         ixgbe_disable_intr(hw);
4644
4645         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4646         if (eicr & IXGBE_EICR_MAILBOX)
4647                 ixgbe_pf_mbx_process(dev);
4648
4649         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4650                 ixgbe_handle_lasi(hw);
4651                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4652         }
4653
4654         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4655                 ixgbe_dev_link_update(dev, 0);
4656                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4657                 ixgbe_dev_link_status_print(dev);
4658                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4659         }
4660
4661         if (intr->flags & IXGBE_FLAG_MACSEC) {
4662                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4663                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4664         }
4665
4666         /* restore original mask */
4667         intr->mask = intr->mask_original;
4668         intr->mask_original = 0;
4669
4670         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4671         ixgbe_enable_intr(dev);
4672         rte_intr_ack(intr_handle);
4673 }
4674
4675 /**
4676  * Interrupt handler triggered by NIC  for handling
4677  * specific interrupt.
4678  *
4679  * @param handle
4680  *  Pointer to interrupt handle.
4681  * @param param
4682  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4683  *
4684  * @return
4685  *  void
4686  */
4687 static void
4688 ixgbe_dev_interrupt_handler(void *param)
4689 {
4690         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4691
4692         ixgbe_dev_interrupt_get_status(dev);
4693         ixgbe_dev_interrupt_action(dev);
4694 }
4695
4696 static int
4697 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4698 {
4699         struct ixgbe_hw *hw;
4700
4701         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4703 }
4704
4705 static int
4706 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4707 {
4708         struct ixgbe_hw *hw;
4709
4710         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4711         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4712 }
4713
4714 static int
4715 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4716 {
4717         struct ixgbe_hw *hw;
4718         uint32_t mflcn_reg;
4719         uint32_t fccfg_reg;
4720         int rx_pause;
4721         int tx_pause;
4722
4723         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724
4725         fc_conf->pause_time = hw->fc.pause_time;
4726         fc_conf->high_water = hw->fc.high_water[0];
4727         fc_conf->low_water = hw->fc.low_water[0];
4728         fc_conf->send_xon = hw->fc.send_xon;
4729         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4730
4731         /*
4732          * Return rx_pause status according to actual setting of
4733          * MFLCN register.
4734          */
4735         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4736         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4737                 fc_conf->mac_ctrl_frame_fwd = 1;
4738         else
4739                 fc_conf->mac_ctrl_frame_fwd = 0;
4740
4741         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4742                 rx_pause = 1;
4743         else
4744                 rx_pause = 0;
4745
4746         /*
4747          * Return tx_pause status according to actual setting of
4748          * FCCFG register.
4749          */
4750         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4751         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4752                 tx_pause = 1;
4753         else
4754                 tx_pause = 0;
4755
4756         if (rx_pause && tx_pause)
4757                 fc_conf->mode = RTE_FC_FULL;
4758         else if (rx_pause)
4759                 fc_conf->mode = RTE_FC_RX_PAUSE;
4760         else if (tx_pause)
4761                 fc_conf->mode = RTE_FC_TX_PAUSE;
4762         else
4763                 fc_conf->mode = RTE_FC_NONE;
4764
4765         return 0;
4766 }
4767
4768 static int
4769 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4770 {
4771         struct ixgbe_hw *hw;
4772         struct ixgbe_adapter *adapter = dev->data->dev_private;
4773         int err;
4774         uint32_t rx_buf_size;
4775         uint32_t max_high_water;
4776         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4777                 ixgbe_fc_none,
4778                 ixgbe_fc_rx_pause,
4779                 ixgbe_fc_tx_pause,
4780                 ixgbe_fc_full
4781         };
4782
4783         PMD_INIT_FUNC_TRACE();
4784
4785         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4786         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4787         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4788
4789         /*
4790          * At least reserve one Ethernet frame for watermark
4791          * high_water/low_water in kilo bytes for ixgbe
4792          */
4793         max_high_water = (rx_buf_size -
4794                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4795         if ((fc_conf->high_water > max_high_water) ||
4796                 (fc_conf->high_water < fc_conf->low_water)) {
4797                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4798                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4799                 return -EINVAL;
4800         }
4801
4802         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4803         hw->fc.pause_time     = fc_conf->pause_time;
4804         hw->fc.high_water[0]  = fc_conf->high_water;
4805         hw->fc.low_water[0]   = fc_conf->low_water;
4806         hw->fc.send_xon       = fc_conf->send_xon;
4807         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4808         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4809
4810         err = ixgbe_flow_ctrl_enable(dev, hw);
4811         if (err < 0) {
4812                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4813                 return -EIO;
4814         }
4815         return err;
4816 }
4817
4818 /**
4819  *  ixgbe_pfc_enable_generic - Enable flow control
4820  *  @hw: pointer to hardware structure
4821  *  @tc_num: traffic class number
4822  *  Enable flow control according to the current settings.
4823  */
4824 static int
4825 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4826 {
4827         int ret_val = 0;
4828         uint32_t mflcn_reg, fccfg_reg;
4829         uint32_t reg;
4830         uint32_t fcrtl, fcrth;
4831         uint8_t i;
4832         uint8_t nb_rx_en;
4833
4834         /* Validate the water mark configuration */
4835         if (!hw->fc.pause_time) {
4836                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4837                 goto out;
4838         }
4839
4840         /* Low water mark of zero causes XOFF floods */
4841         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4842                  /* High/Low water can not be 0 */
4843                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4844                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4845                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4846                         goto out;
4847                 }
4848
4849                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4850                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4851                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4852                         goto out;
4853                 }
4854         }
4855         /* Negotiate the fc mode to use */
4856         ixgbe_fc_autoneg(hw);
4857
4858         /* Disable any previous flow control settings */
4859         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4860         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4861
4862         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4863         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4864
4865         switch (hw->fc.current_mode) {
4866         case ixgbe_fc_none:
4867                 /*
4868                  * If the count of enabled RX Priority Flow control >1,
4869                  * and the TX pause can not be disabled
4870                  */
4871                 nb_rx_en = 0;
4872                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4873                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4874                         if (reg & IXGBE_FCRTH_FCEN)
4875                                 nb_rx_en++;
4876                 }
4877                 if (nb_rx_en > 1)
4878                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4879                 break;
4880         case ixgbe_fc_rx_pause:
4881                 /*
4882                  * Rx Flow control is enabled and Tx Flow control is
4883                  * disabled by software override. Since there really
4884                  * isn't a way to advertise that we are capable of RX
4885                  * Pause ONLY, we will advertise that we support both
4886                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4887                  * disable the adapter's ability to send PAUSE frames.
4888                  */
4889                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4890                 /*
4891                  * If the count of enabled RX Priority Flow control >1,
4892                  * and the TX pause can not be disabled
4893                  */
4894                 nb_rx_en = 0;
4895                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4896                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4897                         if (reg & IXGBE_FCRTH_FCEN)
4898                                 nb_rx_en++;
4899                 }
4900                 if (nb_rx_en > 1)
4901                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4902                 break;
4903         case ixgbe_fc_tx_pause:
4904                 /*
4905                  * Tx Flow control is enabled, and Rx Flow control is
4906                  * disabled by software override.
4907                  */
4908                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4909                 break;
4910         case ixgbe_fc_full:
4911                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4912                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4913                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4914                 break;
4915         default:
4916                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4917                 ret_val = IXGBE_ERR_CONFIG;
4918                 goto out;
4919         }
4920
4921         /* Set 802.3x based flow control settings. */
4922         mflcn_reg |= IXGBE_MFLCN_DPF;
4923         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4924         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4925
4926         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4927         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4928                 hw->fc.high_water[tc_num]) {
4929                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4930                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4931                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4932         } else {
4933                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4934                 /*
4935                  * In order to prevent Tx hangs when the internal Tx
4936                  * switch is enabled we must set the high water mark
4937                  * to the maximum FCRTH value.  This allows the Tx
4938                  * switch to function even under heavy Rx workloads.
4939                  */
4940                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4941         }
4942         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4943
4944         /* Configure pause time (2 TCs per register) */
4945         reg = hw->fc.pause_time * 0x00010001;
4946         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4947                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4948
4949         /* Configure flow control refresh threshold value */
4950         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4951
4952 out:
4953         return ret_val;
4954 }
4955
4956 static int
4957 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4958 {
4959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4960         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4961
4962         if (hw->mac.type != ixgbe_mac_82598EB) {
4963                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4964         }
4965         return ret_val;
4966 }
4967
4968 static int
4969 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4970 {
4971         int err;
4972         uint32_t rx_buf_size;
4973         uint32_t max_high_water;
4974         uint8_t tc_num;
4975         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4976         struct ixgbe_hw *hw =
4977                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4978         struct ixgbe_dcb_config *dcb_config =
4979                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4980
4981         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4982                 ixgbe_fc_none,
4983                 ixgbe_fc_rx_pause,
4984                 ixgbe_fc_tx_pause,
4985                 ixgbe_fc_full
4986         };
4987
4988         PMD_INIT_FUNC_TRACE();
4989
4990         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4991         tc_num = map[pfc_conf->priority];
4992         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4993         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4994         /*
4995          * At least reserve one Ethernet frame for watermark
4996          * high_water/low_water in kilo bytes for ixgbe
4997          */
4998         max_high_water = (rx_buf_size -
4999                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5000         if ((pfc_conf->fc.high_water > max_high_water) ||
5001             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5002                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5003                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5004                 return -EINVAL;
5005         }
5006
5007         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5008         hw->fc.pause_time = pfc_conf->fc.pause_time;
5009         hw->fc.send_xon = pfc_conf->fc.send_xon;
5010         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5011         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5012
5013         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5014
5015         /* Not negotiated is not an error case */
5016         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5017                 return 0;
5018
5019         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5020         return -EIO;
5021 }
5022
5023 static int
5024 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5025                           struct rte_eth_rss_reta_entry64 *reta_conf,
5026                           uint16_t reta_size)
5027 {
5028         uint16_t i, sp_reta_size;
5029         uint8_t j, mask;
5030         uint32_t reta, r;
5031         uint16_t idx, shift;
5032         struct ixgbe_adapter *adapter = dev->data->dev_private;
5033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5034         uint32_t reta_reg;
5035
5036         PMD_INIT_FUNC_TRACE();
5037
5038         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5039                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5040                         "NIC.");
5041                 return -ENOTSUP;
5042         }
5043
5044         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5045         if (reta_size != sp_reta_size) {
5046                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5047                         "(%d) doesn't match the number hardware can supported "
5048                         "(%d)", reta_size, sp_reta_size);
5049                 return -EINVAL;
5050         }
5051
5052         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5053                 idx = i / RTE_RETA_GROUP_SIZE;
5054                 shift = i % RTE_RETA_GROUP_SIZE;
5055                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5056                                                 IXGBE_4_BIT_MASK);
5057                 if (!mask)
5058                         continue;
5059                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5060                 if (mask == IXGBE_4_BIT_MASK)
5061                         r = 0;
5062                 else
5063                         r = IXGBE_READ_REG(hw, reta_reg);
5064                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5065                         if (mask & (0x1 << j))
5066                                 reta |= reta_conf[idx].reta[shift + j] <<
5067                                                         (CHAR_BIT * j);
5068                         else
5069                                 reta |= r & (IXGBE_8_BIT_MASK <<
5070                                                 (CHAR_BIT * j));
5071                 }
5072                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5073         }
5074         adapter->rss_reta_updated = 1;
5075
5076         return 0;
5077 }
5078
5079 static int
5080 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5081                          struct rte_eth_rss_reta_entry64 *reta_conf,
5082                          uint16_t reta_size)
5083 {
5084         uint16_t i, sp_reta_size;
5085         uint8_t j, mask;
5086         uint32_t reta;
5087         uint16_t idx, shift;
5088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5089         uint32_t reta_reg;
5090
5091         PMD_INIT_FUNC_TRACE();
5092         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5093         if (reta_size != sp_reta_size) {
5094                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5095                         "(%d) doesn't match the number hardware can supported "
5096                         "(%d)", reta_size, sp_reta_size);
5097                 return -EINVAL;
5098         }
5099
5100         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5101                 idx = i / RTE_RETA_GROUP_SIZE;
5102                 shift = i % RTE_RETA_GROUP_SIZE;
5103                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5104                                                 IXGBE_4_BIT_MASK);
5105                 if (!mask)
5106                         continue;
5107
5108                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5109                 reta = IXGBE_READ_REG(hw, reta_reg);
5110                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5111                         if (mask & (0x1 << j))
5112                                 reta_conf[idx].reta[shift + j] =
5113                                         ((reta >> (CHAR_BIT * j)) &
5114                                                 IXGBE_8_BIT_MASK);
5115                 }
5116         }
5117
5118         return 0;
5119 }
5120
5121 static int
5122 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5123                                 uint32_t index, uint32_t pool)
5124 {
5125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5126         uint32_t enable_addr = 1;
5127
5128         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5129                              pool, enable_addr);
5130 }
5131
5132 static void
5133 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5134 {
5135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5136
5137         ixgbe_clear_rar(hw, index);
5138 }
5139
5140 static int
5141 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5142 {
5143         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5144
5145         ixgbe_remove_rar(dev, 0);
5146         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5147
5148         return 0;
5149 }
5150
5151 static bool
5152 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5153 {
5154         if (strcmp(dev->device->driver->name, drv->driver.name))
5155                 return false;
5156
5157         return true;
5158 }
5159
5160 bool
5161 is_ixgbe_supported(struct rte_eth_dev *dev)
5162 {
5163         return is_device_supported(dev, &rte_ixgbe_pmd);
5164 }
5165
5166 static int
5167 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5168 {
5169         uint32_t hlreg0;
5170         uint32_t maxfrs;
5171         struct ixgbe_hw *hw;
5172         struct rte_eth_dev_info dev_info;
5173         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5174         struct rte_eth_dev_data *dev_data = dev->data;
5175         int ret;
5176
5177         ret = ixgbe_dev_info_get(dev, &dev_info);
5178         if (ret != 0)
5179                 return ret;
5180
5181         /* check that mtu is within the allowed range */
5182         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5183                 return -EINVAL;
5184
5185         /* If device is started, refuse mtu that requires the support of
5186          * scattered packets when this feature has not been enabled before.
5187          */
5188         if (dev_data->dev_started && !dev_data->scattered_rx &&
5189             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5190              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5191                 PMD_INIT_LOG(ERR, "Stop port first.");
5192                 return -EINVAL;
5193         }
5194
5195         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5196         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5197
5198         /* switch to jumbo mode if needed */
5199         if (frame_size > RTE_ETHER_MAX_LEN) {
5200                 dev->data->dev_conf.rxmode.offloads |=
5201                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5202                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5203         } else {
5204                 dev->data->dev_conf.rxmode.offloads &=
5205                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5206                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5207         }
5208         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5209
5210         /* update max frame size */
5211         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5212
5213         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5214         maxfrs &= 0x0000FFFF;
5215         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5216         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5217
5218         return 0;
5219 }
5220
5221 /*
5222  * Virtual Function operations
5223  */
5224 static void
5225 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5226 {
5227         struct ixgbe_interrupt *intr =
5228                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5229         struct ixgbe_hw *hw =
5230                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5231
5232         PMD_INIT_FUNC_TRACE();
5233
5234         /* Clear interrupt mask to stop from interrupts being generated */
5235         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5236
5237         IXGBE_WRITE_FLUSH(hw);
5238
5239         /* Clear mask value. */
5240         intr->mask = 0;
5241 }
5242
5243 static void
5244 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5245 {
5246         struct ixgbe_interrupt *intr =
5247                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5248         struct ixgbe_hw *hw =
5249                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5250
5251         PMD_INIT_FUNC_TRACE();
5252
5253         /* VF enable interrupt autoclean */
5254         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5255         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5256         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5257
5258         IXGBE_WRITE_FLUSH(hw);
5259
5260         /* Save IXGBE_VTEIMS value to mask. */
5261         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5262 }
5263
5264 static int
5265 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5266 {
5267         struct rte_eth_conf *conf = &dev->data->dev_conf;
5268         struct ixgbe_adapter *adapter = dev->data->dev_private;
5269
5270         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5271                      dev->data->port_id);
5272
5273         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5274                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5275
5276         /*
5277          * VF has no ability to enable/disable HW CRC
5278          * Keep the persistent behavior the same as Host PF
5279          */
5280 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5281         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5282                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5283                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5284         }
5285 #else
5286         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5287                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5288                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5289         }
5290 #endif
5291
5292         /*
5293          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5294          * allocation or vector Rx preconditions we will reset it.
5295          */
5296         adapter->rx_bulk_alloc_allowed = true;
5297         adapter->rx_vec_allowed = true;
5298
5299         return 0;
5300 }
5301
5302 static int
5303 ixgbevf_dev_start(struct rte_eth_dev *dev)
5304 {
5305         struct ixgbe_hw *hw =
5306                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5307         uint32_t intr_vector = 0;
5308         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5309         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5310
5311         int err, mask = 0;
5312
5313         PMD_INIT_FUNC_TRACE();
5314
5315         /* Stop the link setup handler before resetting the HW. */
5316         ixgbe_dev_wait_setup_link_complete(dev, 0);
5317
5318         err = hw->mac.ops.reset_hw(hw);
5319
5320         /**
5321          * In this case, reuses the MAC address assigned by VF
5322          * initialization.
5323          */
5324         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5325                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5326                 return err;
5327         }
5328
5329         hw->mac.get_link_status = true;
5330
5331         /* negotiate mailbox API version to use with the PF. */
5332         ixgbevf_negotiate_api(hw);
5333
5334         ixgbevf_dev_tx_init(dev);
5335
5336         /* This can fail when allocating mbufs for descriptor rings */
5337         err = ixgbevf_dev_rx_init(dev);
5338         if (err) {
5339                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5340                 ixgbe_dev_clear_queues(dev);
5341                 return err;
5342         }
5343
5344         /* Set vfta */
5345         ixgbevf_set_vfta_all(dev, 1);
5346
5347         /* Set HW strip */
5348         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5349                 ETH_VLAN_EXTEND_MASK;
5350         err = ixgbevf_vlan_offload_config(dev, mask);
5351         if (err) {
5352                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5353                 ixgbe_dev_clear_queues(dev);
5354                 return err;
5355         }
5356
5357         ixgbevf_dev_rxtx_start(dev);
5358
5359         /* check and configure queue intr-vector mapping */
5360         if (rte_intr_cap_multiple(intr_handle) &&
5361             dev->data->dev_conf.intr_conf.rxq) {
5362                 /* According to datasheet, only vector 0/1/2 can be used,
5363                  * now only one vector is used for Rx queue
5364                  */
5365                 intr_vector = 1;
5366                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5367                         return -1;
5368         }
5369
5370         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5371                 intr_handle->intr_vec =
5372                         rte_zmalloc("intr_vec",
5373                                     dev->data->nb_rx_queues * sizeof(int), 0);
5374                 if (intr_handle->intr_vec == NULL) {
5375                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5376                                      " intr_vec", dev->data->nb_rx_queues);
5377                         return -ENOMEM;
5378                 }
5379         }
5380         ixgbevf_configure_msix(dev);
5381
5382         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5383          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5384          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5385          * is not cleared, it will fail when following rte_intr_enable( ) tries
5386          * to map Rx queue interrupt to other VFIO vectors.
5387          * So clear uio/vfio intr/evevnfd first to avoid failure.
5388          */
5389         rte_intr_disable(intr_handle);
5390
5391         rte_intr_enable(intr_handle);
5392
5393         /* Re-enable interrupt for VF */
5394         ixgbevf_intr_enable(dev);
5395
5396         /*
5397          * Update link status right before return, because it may
5398          * start link configuration process in a separate thread.
5399          */
5400         ixgbevf_dev_link_update(dev, 0);
5401
5402         hw->adapter_stopped = false;
5403
5404         return 0;
5405 }
5406
5407 static int
5408 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5409 {
5410         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411         struct ixgbe_adapter *adapter = dev->data->dev_private;
5412         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5413         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5414
5415         if (hw->adapter_stopped)
5416                 return 0;
5417
5418         PMD_INIT_FUNC_TRACE();
5419
5420         ixgbe_dev_wait_setup_link_complete(dev, 0);
5421
5422         ixgbevf_intr_disable(dev);
5423
5424         dev->data->dev_started = 0;
5425         hw->adapter_stopped = 1;
5426         ixgbe_stop_adapter(hw);
5427
5428         /*
5429           * Clear what we set, but we still keep shadow_vfta to
5430           * restore after device starts
5431           */
5432         ixgbevf_set_vfta_all(dev, 0);
5433
5434         /* Clear stored conf */
5435         dev->data->scattered_rx = 0;
5436
5437         ixgbe_dev_clear_queues(dev);
5438
5439         /* Clean datapath event and queue/vec mapping */
5440         rte_intr_efd_disable(intr_handle);
5441         if (intr_handle->intr_vec != NULL) {
5442                 rte_free(intr_handle->intr_vec);
5443                 intr_handle->intr_vec = NULL;
5444         }
5445
5446         adapter->rss_reta_updated = 0;
5447
5448         return 0;
5449 }
5450
5451 static int
5452 ixgbevf_dev_close(struct rte_eth_dev *dev)
5453 {
5454         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5455         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5456         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5457         int ret;
5458
5459         PMD_INIT_FUNC_TRACE();
5460         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5461                 return 0;
5462
5463         ixgbe_reset_hw(hw);
5464
5465         ret = ixgbevf_dev_stop(dev);
5466
5467         ixgbe_dev_free_queues(dev);
5468
5469         /**
5470          * Remove the VF MAC address ro ensure
5471          * that the VF traffic goes to the PF
5472          * after stop, close and detach of the VF
5473          **/
5474         ixgbevf_remove_mac_addr(dev, 0);
5475
5476         rte_intr_disable(intr_handle);
5477         rte_intr_callback_unregister(intr_handle,
5478                                      ixgbevf_dev_interrupt_handler, dev);
5479
5480         return ret;
5481 }
5482
5483 /*
5484  * Reset VF device
5485  */
5486 static int
5487 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5488 {
5489         int ret;
5490
5491         ret = eth_ixgbevf_dev_uninit(dev);
5492         if (ret)
5493                 return ret;
5494
5495         ret = eth_ixgbevf_dev_init(dev);
5496
5497         return ret;
5498 }
5499
5500 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5501 {
5502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5503         struct ixgbe_vfta *shadow_vfta =
5504                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5505         int i = 0, j = 0, vfta = 0, mask = 1;
5506
5507         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5508                 vfta = shadow_vfta->vfta[i];
5509                 if (vfta) {
5510                         mask = 1;
5511                         for (j = 0; j < 32; j++) {
5512                                 if (vfta & mask)
5513                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5514                                                        on, false);
5515                                 mask <<= 1;
5516                         }
5517                 }
5518         }
5519
5520 }
5521
5522 static int
5523 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5524 {
5525         struct ixgbe_hw *hw =
5526                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5527         struct ixgbe_vfta *shadow_vfta =
5528                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5529         uint32_t vid_idx = 0;
5530         uint32_t vid_bit = 0;
5531         int ret = 0;
5532
5533         PMD_INIT_FUNC_TRACE();
5534
5535         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5536         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5537         if (ret) {
5538                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5539                 return ret;
5540         }
5541         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5542         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5543
5544         /* Save what we set and retore it after device reset */
5545         if (on)
5546                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5547         else
5548                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5549
5550         return 0;
5551 }
5552
5553 static void
5554 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5555 {
5556         struct ixgbe_hw *hw =
5557                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5558         uint32_t ctrl;
5559
5560         PMD_INIT_FUNC_TRACE();
5561
5562         if (queue >= hw->mac.max_rx_queues)
5563                 return;
5564
5565         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5566         if (on)
5567                 ctrl |= IXGBE_RXDCTL_VME;
5568         else
5569                 ctrl &= ~IXGBE_RXDCTL_VME;
5570         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5571
5572         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5573 }
5574
5575 static int
5576 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5577 {
5578         struct ixgbe_rx_queue *rxq;
5579         uint16_t i;
5580         int on = 0;
5581
5582         /* VF function only support hw strip feature, others are not support */
5583         if (mask & ETH_VLAN_STRIP_MASK) {
5584                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5585                         rxq = dev->data->rx_queues[i];
5586                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5587                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5588                 }
5589         }
5590
5591         return 0;
5592 }
5593
5594 static int
5595 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5596 {
5597         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5598
5599         ixgbevf_vlan_offload_config(dev, mask);
5600
5601         return 0;
5602 }
5603
5604 int
5605 ixgbe_vt_check(struct ixgbe_hw *hw)
5606 {
5607         uint32_t reg_val;
5608
5609         /* if Virtualization Technology is enabled */
5610         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5611         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5612                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5613                 return -1;
5614         }
5615
5616         return 0;
5617 }
5618
5619 static uint32_t
5620 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5621 {
5622         uint32_t vector = 0;
5623
5624         switch (hw->mac.mc_filter_type) {
5625         case 0:   /* use bits [47:36] of the address */
5626                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5627                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5628                 break;
5629         case 1:   /* use bits [46:35] of the address */
5630                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5631                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5632                 break;
5633         case 2:   /* use bits [45:34] of the address */
5634                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5635                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5636                 break;
5637         case 3:   /* use bits [43:32] of the address */
5638                 vector = ((uc_addr->addr_bytes[4]) |
5639                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5640                 break;
5641         default:  /* Invalid mc_filter_type */
5642                 break;
5643         }
5644
5645         /* vector can only be 12-bits or boundary will be exceeded */
5646         vector &= 0xFFF;
5647         return vector;
5648 }
5649
5650 static int
5651 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5652                         struct rte_ether_addr *mac_addr, uint8_t on)
5653 {
5654         uint32_t vector;
5655         uint32_t uta_idx;
5656         uint32_t reg_val;
5657         uint32_t uta_shift;
5658         uint32_t rc;
5659         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5660         const uint32_t ixgbe_uta_bit_shift = 5;
5661         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5662         const uint32_t bit1 = 0x1;
5663
5664         struct ixgbe_hw *hw =
5665                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5666         struct ixgbe_uta_info *uta_info =
5667                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5668
5669         /* The UTA table only exists on 82599 hardware and newer */
5670         if (hw->mac.type < ixgbe_mac_82599EB)
5671                 return -ENOTSUP;
5672
5673         vector = ixgbe_uta_vector(hw, mac_addr);
5674         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5675         uta_shift = vector & ixgbe_uta_bit_mask;
5676
5677         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5678         if (rc == on)
5679                 return 0;
5680
5681         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5682         if (on) {
5683                 uta_info->uta_in_use++;
5684                 reg_val |= (bit1 << uta_shift);
5685                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5686         } else {
5687                 uta_info->uta_in_use--;
5688                 reg_val &= ~(bit1 << uta_shift);
5689                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5690         }
5691
5692         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5693
5694         if (uta_info->uta_in_use > 0)
5695                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5696                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5697         else
5698                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5699
5700         return 0;
5701 }
5702
5703 static int
5704 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5705 {
5706         int i;
5707         struct ixgbe_hw *hw =
5708                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5709         struct ixgbe_uta_info *uta_info =
5710                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5711
5712         /* The UTA table only exists on 82599 hardware and newer */
5713         if (hw->mac.type < ixgbe_mac_82599EB)
5714                 return -ENOTSUP;
5715
5716         if (on) {
5717                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5718                         uta_info->uta_shadow[i] = ~0;
5719                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5720                 }
5721         } else {
5722                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5723                         uta_info->uta_shadow[i] = 0;
5724                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5725                 }
5726         }
5727         return 0;
5728
5729 }
5730
5731 uint32_t
5732 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5733 {
5734         uint32_t new_val = orig_val;
5735
5736         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5737                 new_val |= IXGBE_VMOLR_AUPE;
5738         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5739                 new_val |= IXGBE_VMOLR_ROMPE;
5740         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5741                 new_val |= IXGBE_VMOLR_ROPE;
5742         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5743                 new_val |= IXGBE_VMOLR_BAM;
5744         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5745                 new_val |= IXGBE_VMOLR_MPE;
5746
5747         return new_val;
5748 }
5749
5750 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5751 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5752 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5753 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5754 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5755         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5756         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5757
5758 static int
5759 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5760                       struct rte_eth_mirror_conf *mirror_conf,
5761                       uint8_t rule_id, uint8_t on)
5762 {
5763         uint32_t mr_ctl, vlvf;
5764         uint32_t mp_lsb = 0;
5765         uint32_t mv_msb = 0;
5766         uint32_t mv_lsb = 0;
5767         uint32_t mp_msb = 0;
5768         uint8_t i = 0;
5769         int reg_index = 0;
5770         uint64_t vlan_mask = 0;
5771
5772         const uint8_t pool_mask_offset = 32;
5773         const uint8_t vlan_mask_offset = 32;
5774         const uint8_t dst_pool_offset = 8;
5775         const uint8_t rule_mr_offset  = 4;
5776         const uint8_t mirror_rule_mask = 0x0F;
5777
5778         struct ixgbe_mirror_info *mr_info =
5779                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5780         struct ixgbe_hw *hw =
5781                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5782         uint8_t mirror_type = 0;
5783
5784         if (ixgbe_vt_check(hw) < 0)
5785                 return -ENOTSUP;
5786
5787         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5788                 return -EINVAL;
5789
5790         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5791                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5792                             mirror_conf->rule_type);
5793                 return -EINVAL;
5794         }
5795
5796         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5797                 mirror_type |= IXGBE_MRCTL_VLME;
5798                 /* Check if vlan id is valid and find conresponding VLAN ID
5799                  * index in VLVF
5800                  */
5801                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5802                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5803                                 /* search vlan id related pool vlan filter
5804                                  * index
5805                                  */
5806                                 reg_index = ixgbe_find_vlvf_slot(
5807                                                 hw,
5808                                                 mirror_conf->vlan.vlan_id[i],
5809                                                 false);
5810                                 if (reg_index < 0)
5811                                         return -EINVAL;
5812                                 vlvf = IXGBE_READ_REG(hw,
5813                                                       IXGBE_VLVF(reg_index));
5814                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5815                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5816                                       mirror_conf->vlan.vlan_id[i]))
5817                                         vlan_mask |= (1ULL << reg_index);
5818                                 else
5819                                         return -EINVAL;
5820                         }
5821                 }
5822
5823                 if (on) {
5824                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5825                         mv_msb = vlan_mask >> vlan_mask_offset;
5826
5827                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5828                                                 mirror_conf->vlan.vlan_mask;
5829                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5830                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5831                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5832                                                 mirror_conf->vlan.vlan_id[i];
5833                         }
5834                 } else {
5835                         mv_lsb = 0;
5836                         mv_msb = 0;
5837                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5838                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5839                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5840                 }
5841         }
5842
5843         /**
5844          * if enable pool mirror, write related pool mask register,if disable
5845          * pool mirror, clear PFMRVM register
5846          */
5847         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5848                 mirror_type |= IXGBE_MRCTL_VPME;
5849                 if (on) {
5850                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5851                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5852                         mr_info->mr_conf[rule_id].pool_mask =
5853                                         mirror_conf->pool_mask;
5854
5855                 } else {
5856                         mp_lsb = 0;
5857                         mp_msb = 0;
5858                         mr_info->mr_conf[rule_id].pool_mask = 0;
5859                 }
5860         }
5861         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5862                 mirror_type |= IXGBE_MRCTL_UPME;
5863         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5864                 mirror_type |= IXGBE_MRCTL_DPME;
5865
5866         /* read  mirror control register and recalculate it */
5867         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5868
5869         if (on) {
5870                 mr_ctl |= mirror_type;
5871                 mr_ctl &= mirror_rule_mask;
5872                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5873         } else {
5874                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5875         }
5876
5877         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5878         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5879
5880         /* write mirrror control  register */
5881         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5882
5883         /* write pool mirrror control  register */
5884         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5885                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5886                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5887                                 mp_msb);
5888         }
5889         /* write VLAN mirrror control  register */
5890         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5891                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5892                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5893                                 mv_msb);
5894         }
5895
5896         return 0;
5897 }
5898
5899 static int
5900 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5901 {
5902         int mr_ctl = 0;
5903         uint32_t lsb_val = 0;
5904         uint32_t msb_val = 0;
5905         const uint8_t rule_mr_offset = 4;
5906
5907         struct ixgbe_hw *hw =
5908                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5909         struct ixgbe_mirror_info *mr_info =
5910                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5911
5912         if (ixgbe_vt_check(hw) < 0)
5913                 return -ENOTSUP;
5914
5915         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5916                 return -EINVAL;
5917
5918         memset(&mr_info->mr_conf[rule_id], 0,
5919                sizeof(struct rte_eth_mirror_conf));
5920
5921         /* clear PFVMCTL register */
5922         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5923
5924         /* clear pool mask register */
5925         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5926         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5927
5928         /* clear vlan mask register */
5929         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5930         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5931
5932         return 0;
5933 }
5934
5935 static int
5936 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5937 {
5938         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5939         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5940         struct ixgbe_interrupt *intr =
5941                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5942         struct ixgbe_hw *hw =
5943                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5944         uint32_t vec = IXGBE_MISC_VEC_ID;
5945
5946         if (rte_intr_allow_others(intr_handle))
5947                 vec = IXGBE_RX_VEC_START;
5948         intr->mask |= (1 << vec);
5949         RTE_SET_USED(queue_id);
5950         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5951
5952         rte_intr_ack(intr_handle);
5953
5954         return 0;
5955 }
5956
5957 static int
5958 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5959 {
5960         struct ixgbe_interrupt *intr =
5961                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5962         struct ixgbe_hw *hw =
5963                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5964         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5965         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5966         uint32_t vec = IXGBE_MISC_VEC_ID;
5967
5968         if (rte_intr_allow_others(intr_handle))
5969                 vec = IXGBE_RX_VEC_START;
5970         intr->mask &= ~(1 << vec);
5971         RTE_SET_USED(queue_id);
5972         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5973
5974         return 0;
5975 }
5976
5977 static int
5978 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5979 {
5980         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5981         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5982         uint32_t mask;
5983         struct ixgbe_hw *hw =
5984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5985         struct ixgbe_interrupt *intr =
5986                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5987
5988         if (queue_id < 16) {
5989                 ixgbe_disable_intr(hw);
5990                 intr->mask |= (1 << queue_id);
5991                 ixgbe_enable_intr(dev);
5992         } else if (queue_id < 32) {
5993                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5994                 mask &= (1 << queue_id);
5995                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5996         } else if (queue_id < 64) {
5997                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5998                 mask &= (1 << (queue_id - 32));
5999                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6000         }
6001         rte_intr_ack(intr_handle);
6002
6003         return 0;
6004 }
6005
6006 static int
6007 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6008 {
6009         uint32_t mask;
6010         struct ixgbe_hw *hw =
6011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6012         struct ixgbe_interrupt *intr =
6013                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6014
6015         if (queue_id < 16) {
6016                 ixgbe_disable_intr(hw);
6017                 intr->mask &= ~(1 << queue_id);
6018                 ixgbe_enable_intr(dev);
6019         } else if (queue_id < 32) {
6020                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6021                 mask &= ~(1 << queue_id);
6022                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6023         } else if (queue_id < 64) {
6024                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6025                 mask &= ~(1 << (queue_id - 32));
6026                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6027         }
6028
6029         return 0;
6030 }
6031
6032 static void
6033 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6034                      uint8_t queue, uint8_t msix_vector)
6035 {
6036         uint32_t tmp, idx;
6037
6038         if (direction == -1) {
6039                 /* other causes */
6040                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6041                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6042                 tmp &= ~0xFF;
6043                 tmp |= msix_vector;
6044                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6045         } else {
6046                 /* rx or tx cause */
6047                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6048                 idx = ((16 * (queue & 1)) + (8 * direction));
6049                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6050                 tmp &= ~(0xFF << idx);
6051                 tmp |= (msix_vector << idx);
6052                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6053         }
6054 }
6055
6056 /**
6057  * set the IVAR registers, mapping interrupt causes to vectors
6058  * @param hw
6059  *  pointer to ixgbe_hw struct
6060  * @direction
6061  *  0 for Rx, 1 for Tx, -1 for other causes
6062  * @queue
6063  *  queue to map the corresponding interrupt to
6064  * @msix_vector
6065  *  the vector to map to the corresponding queue
6066  */
6067 static void
6068 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6069                    uint8_t queue, uint8_t msix_vector)
6070 {
6071         uint32_t tmp, idx;
6072
6073         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6074         if (hw->mac.type == ixgbe_mac_82598EB) {
6075                 if (direction == -1)
6076                         direction = 0;
6077                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6078                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6079                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6080                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6081                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6082         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6083                         (hw->mac.type == ixgbe_mac_X540) ||
6084                         (hw->mac.type == ixgbe_mac_X550) ||
6085                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6086                 if (direction == -1) {
6087                         /* other causes */
6088                         idx = ((queue & 1) * 8);
6089                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6090                         tmp &= ~(0xFF << idx);
6091                         tmp |= (msix_vector << idx);
6092                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6093                 } else {
6094                         /* rx or tx causes */
6095                         idx = ((16 * (queue & 1)) + (8 * direction));
6096                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6097                         tmp &= ~(0xFF << idx);
6098                         tmp |= (msix_vector << idx);
6099                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6100                 }
6101         }
6102 }
6103
6104 static void
6105 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6106 {
6107         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6108         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6109         struct ixgbe_hw *hw =
6110                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6111         uint32_t q_idx;
6112         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6113         uint32_t base = IXGBE_MISC_VEC_ID;
6114
6115         /* Configure VF other cause ivar */
6116         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6117
6118         /* won't configure msix register if no mapping is done
6119          * between intr vector and event fd.
6120          */
6121         if (!rte_intr_dp_is_en(intr_handle))
6122                 return;
6123
6124         if (rte_intr_allow_others(intr_handle)) {
6125                 base = IXGBE_RX_VEC_START;
6126                 vector_idx = IXGBE_RX_VEC_START;
6127         }
6128
6129         /* Configure all RX queues of VF */
6130         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6131                 /* Force all queue use vector 0,
6132                  * as IXGBE_VF_MAXMSIVECOTR = 1
6133                  */
6134                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6135                 intr_handle->intr_vec[q_idx] = vector_idx;
6136                 if (vector_idx < base + intr_handle->nb_efd - 1)
6137                         vector_idx++;
6138         }
6139
6140         /* As RX queue setting above show, all queues use the vector 0.
6141          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6142          */
6143         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6144                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6145                         | IXGBE_EITR_CNT_WDIS);
6146 }
6147
6148 /**
6149  * Sets up the hardware to properly generate MSI-X interrupts
6150  * @hw
6151  *  board private structure
6152  */
6153 static void
6154 ixgbe_configure_msix(struct rte_eth_dev *dev)
6155 {
6156         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6157         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6158         struct ixgbe_hw *hw =
6159                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6160         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6161         uint32_t vec = IXGBE_MISC_VEC_ID;
6162         uint32_t mask;
6163         uint32_t gpie;
6164
6165         /* won't configure msix register if no mapping is done
6166          * between intr vector and event fd
6167          * but if misx has been enabled already, need to configure
6168          * auto clean, auto mask and throttling.
6169          */
6170         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6171         if (!rte_intr_dp_is_en(intr_handle) &&
6172             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6173                 return;
6174
6175         if (rte_intr_allow_others(intr_handle))
6176                 vec = base = IXGBE_RX_VEC_START;
6177
6178         /* setup GPIE for MSI-x mode */
6179         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6180         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6181                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6182         /* auto clearing and auto setting corresponding bits in EIMS
6183          * when MSI-X interrupt is triggered
6184          */
6185         if (hw->mac.type == ixgbe_mac_82598EB) {
6186                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6187         } else {
6188                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6189                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6190         }
6191         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6192
6193         /* Populate the IVAR table and set the ITR values to the
6194          * corresponding register.
6195          */
6196         if (rte_intr_dp_is_en(intr_handle)) {
6197                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6198                         queue_id++) {
6199                         /* by default, 1:1 mapping */
6200                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6201                         intr_handle->intr_vec[queue_id] = vec;
6202                         if (vec < base + intr_handle->nb_efd - 1)
6203                                 vec++;
6204                 }
6205
6206                 switch (hw->mac.type) {
6207                 case ixgbe_mac_82598EB:
6208                         ixgbe_set_ivar_map(hw, -1,
6209                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6210                                            IXGBE_MISC_VEC_ID);
6211                         break;
6212                 case ixgbe_mac_82599EB:
6213                 case ixgbe_mac_X540:
6214                 case ixgbe_mac_X550:
6215                 case ixgbe_mac_X550EM_x:
6216                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6217                         break;
6218                 default:
6219                         break;
6220                 }
6221         }
6222         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6223                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6224                         | IXGBE_EITR_CNT_WDIS);
6225
6226         /* set up to autoclear timer, and the vectors */
6227         mask = IXGBE_EIMS_ENABLE_MASK;
6228         mask &= ~(IXGBE_EIMS_OTHER |
6229                   IXGBE_EIMS_MAILBOX |
6230                   IXGBE_EIMS_LSC);
6231
6232         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6233 }
6234
6235 int
6236 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6237                            uint16_t queue_idx, uint16_t tx_rate)
6238 {
6239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6240         struct rte_eth_rxmode *rxmode;
6241         uint32_t rf_dec, rf_int;
6242         uint32_t bcnrc_val;
6243         uint16_t link_speed = dev->data->dev_link.link_speed;
6244
6245         if (queue_idx >= hw->mac.max_tx_queues)
6246                 return -EINVAL;
6247
6248         if (tx_rate != 0) {
6249                 /* Calculate the rate factor values to set */
6250                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6251                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6252                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6253
6254                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6255                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6256                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6257                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6258         } else {
6259                 bcnrc_val = 0;
6260         }
6261
6262         rxmode = &dev->data->dev_conf.rxmode;
6263         /*
6264          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6265          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6266          * set as 0x4.
6267          */
6268         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6269             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6270                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6271                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6272         else
6273                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6274                         IXGBE_MMW_SIZE_DEFAULT);
6275
6276         /* Set RTTBCNRC of queue X */
6277         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6278         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6279         IXGBE_WRITE_FLUSH(hw);
6280
6281         return 0;
6282 }
6283
6284 static int
6285 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6286                      __rte_unused uint32_t index,
6287                      __rte_unused uint32_t pool)
6288 {
6289         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6290         int diag;
6291
6292         /*
6293          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6294          * operation. Trap this case to avoid exhausting the [very limited]
6295          * set of PF resources used to store VF MAC addresses.
6296          */
6297         if (memcmp(hw->mac.perm_addr, mac_addr,
6298                         sizeof(struct rte_ether_addr)) == 0)
6299                 return -1;
6300         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6301         if (diag != 0)
6302                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6303                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6304                             mac_addr->addr_bytes[0],
6305                             mac_addr->addr_bytes[1],
6306                             mac_addr->addr_bytes[2],
6307                             mac_addr->addr_bytes[3],
6308                             mac_addr->addr_bytes[4],
6309                             mac_addr->addr_bytes[5],
6310                             diag);
6311         return diag;
6312 }
6313
6314 static void
6315 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6316 {
6317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6318         struct rte_ether_addr *perm_addr =
6319                 (struct rte_ether_addr *)hw->mac.perm_addr;
6320         struct rte_ether_addr *mac_addr;
6321         uint32_t i;
6322         int diag;
6323
6324         /*
6325          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6326          * not support the deletion of a given MAC address.
6327          * Instead, it imposes to delete all MAC addresses, then to add again
6328          * all MAC addresses with the exception of the one to be deleted.
6329          */
6330         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6331
6332         /*
6333          * Add again all MAC addresses, with the exception of the deleted one
6334          * and of the permanent MAC address.
6335          */
6336         for (i = 0, mac_addr = dev->data->mac_addrs;
6337              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6338                 /* Skip the deleted MAC address */
6339                 if (i == index)
6340                         continue;
6341                 /* Skip NULL MAC addresses */
6342                 if (rte_is_zero_ether_addr(mac_addr))
6343                         continue;
6344                 /* Skip the permanent MAC address */
6345                 if (memcmp(perm_addr, mac_addr,
6346                                 sizeof(struct rte_ether_addr)) == 0)
6347                         continue;
6348                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6349                 if (diag != 0)
6350                         PMD_DRV_LOG(ERR,
6351                                     "Adding again MAC address "
6352                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6353                                     "diag=%d",
6354                                     mac_addr->addr_bytes[0],
6355                                     mac_addr->addr_bytes[1],
6356                                     mac_addr->addr_bytes[2],
6357                                     mac_addr->addr_bytes[3],
6358                                     mac_addr->addr_bytes[4],
6359                                     mac_addr->addr_bytes[5],
6360                                     diag);
6361         }
6362 }
6363
6364 static int
6365 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6366                         struct rte_ether_addr *addr)
6367 {
6368         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6369
6370         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6371
6372         return 0;
6373 }
6374
6375 int
6376 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6377                         struct rte_eth_syn_filter *filter,
6378                         bool add)
6379 {
6380         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6381         struct ixgbe_filter_info *filter_info =
6382                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6383         uint32_t syn_info;
6384         uint32_t synqf;
6385
6386         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6387                 return -EINVAL;
6388
6389         syn_info = filter_info->syn_info;
6390
6391         if (add) {
6392                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6393                         return -EINVAL;
6394                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6395                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6396
6397                 if (filter->hig_pri)
6398                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6399                 else
6400                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6401         } else {
6402                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6403                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6404                         return -ENOENT;
6405                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6406         }
6407
6408         filter_info->syn_info = synqf;
6409         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6410         IXGBE_WRITE_FLUSH(hw);
6411         return 0;
6412 }
6413
6414 static int
6415 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6416                         struct rte_eth_syn_filter *filter)
6417 {
6418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6419         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6420
6421         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6422                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6423                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6424                 return 0;
6425         }
6426         return -ENOENT;
6427 }
6428
6429 static int
6430 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6431                         enum rte_filter_op filter_op,
6432                         void *arg)
6433 {
6434         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6435         int ret;
6436
6437         MAC_TYPE_FILTER_SUP(hw->mac.type);
6438
6439         if (filter_op == RTE_ETH_FILTER_NOP)
6440                 return 0;
6441
6442         if (arg == NULL) {
6443                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6444                             filter_op);
6445                 return -EINVAL;
6446         }
6447
6448         switch (filter_op) {
6449         case RTE_ETH_FILTER_ADD:
6450                 ret = ixgbe_syn_filter_set(dev,
6451                                 (struct rte_eth_syn_filter *)arg,
6452                                 TRUE);
6453                 break;
6454         case RTE_ETH_FILTER_DELETE:
6455                 ret = ixgbe_syn_filter_set(dev,
6456                                 (struct rte_eth_syn_filter *)arg,
6457                                 FALSE);
6458                 break;
6459         case RTE_ETH_FILTER_GET:
6460                 ret = ixgbe_syn_filter_get(dev,
6461                                 (struct rte_eth_syn_filter *)arg);
6462                 break;
6463         default:
6464                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6465                 ret = -EINVAL;
6466                 break;
6467         }
6468
6469         return ret;
6470 }
6471
6472
6473 static inline enum ixgbe_5tuple_protocol
6474 convert_protocol_type(uint8_t protocol_value)
6475 {
6476         if (protocol_value == IPPROTO_TCP)
6477                 return IXGBE_FILTER_PROTOCOL_TCP;
6478         else if (protocol_value == IPPROTO_UDP)
6479                 return IXGBE_FILTER_PROTOCOL_UDP;
6480         else if (protocol_value == IPPROTO_SCTP)
6481                 return IXGBE_FILTER_PROTOCOL_SCTP;
6482         else
6483                 return IXGBE_FILTER_PROTOCOL_NONE;
6484 }
6485
6486 /* inject a 5-tuple filter to HW */
6487 static inline void
6488 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6489                            struct ixgbe_5tuple_filter *filter)
6490 {
6491         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6492         int i;
6493         uint32_t ftqf, sdpqf;
6494         uint32_t l34timir = 0;
6495         uint8_t mask = 0xff;
6496
6497         i = filter->index;
6498
6499         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6500                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6501         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6502
6503         ftqf = (uint32_t)(filter->filter_info.proto &
6504                 IXGBE_FTQF_PROTOCOL_MASK);
6505         ftqf |= (uint32_t)((filter->filter_info.priority &
6506                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6507         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6508                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6509         if (filter->filter_info.dst_ip_mask == 0)
6510                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6511         if (filter->filter_info.src_port_mask == 0)
6512                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6513         if (filter->filter_info.dst_port_mask == 0)
6514                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6515         if (filter->filter_info.proto_mask == 0)
6516                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6517         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6518         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6519         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6520
6521         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6522         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6523         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6524         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6525
6526         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6527         l34timir |= (uint32_t)(filter->queue <<
6528                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6529         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6530 }
6531
6532 /*
6533  * add a 5tuple filter
6534  *
6535  * @param
6536  * dev: Pointer to struct rte_eth_dev.
6537  * index: the index the filter allocates.
6538  * filter: ponter to the filter that will be added.
6539  * rx_queue: the queue id the filter assigned to.
6540  *
6541  * @return
6542  *    - On success, zero.
6543  *    - On failure, a negative value.
6544  */
6545 static int
6546 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6547                         struct ixgbe_5tuple_filter *filter)
6548 {
6549         struct ixgbe_filter_info *filter_info =
6550                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6551         int i, idx, shift;
6552
6553         /*
6554          * look for an unused 5tuple filter index,
6555          * and insert the filter to list.
6556          */
6557         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6558                 idx = i / (sizeof(uint32_t) * NBBY);
6559                 shift = i % (sizeof(uint32_t) * NBBY);
6560                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6561                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6562                         filter->index = i;
6563                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6564                                           filter,
6565                                           entries);
6566                         break;
6567                 }
6568         }
6569         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6570                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6571                 return -ENOSYS;
6572         }
6573
6574         ixgbe_inject_5tuple_filter(dev, filter);
6575
6576         return 0;
6577 }
6578
6579 /*
6580  * remove a 5tuple filter
6581  *
6582  * @param
6583  * dev: Pointer to struct rte_eth_dev.
6584  * filter: the pointer of the filter will be removed.
6585  */
6586 static void
6587 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6588                         struct ixgbe_5tuple_filter *filter)
6589 {
6590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6591         struct ixgbe_filter_info *filter_info =
6592                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6593         uint16_t index = filter->index;
6594
6595         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6596                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6597         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6598         rte_free(filter);
6599
6600         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6601         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6602         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6603         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6604         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6605 }
6606
6607 static int
6608 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6609 {
6610         struct ixgbe_hw *hw;
6611         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6612         struct rte_eth_dev_data *dev_data = dev->data;
6613
6614         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6615
6616         if (mtu < RTE_ETHER_MIN_MTU ||
6617                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6618                 return -EINVAL;
6619
6620         /* If device is started, refuse mtu that requires the support of
6621          * scattered packets when this feature has not been enabled before.
6622          */
6623         if (dev_data->dev_started && !dev_data->scattered_rx &&
6624             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6625              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6626                 PMD_INIT_LOG(ERR, "Stop port first.");
6627                 return -EINVAL;
6628         }
6629
6630         /*
6631          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6632          * request of the version 2.0 of the mailbox API.
6633          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6634          * of the mailbox API.
6635          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6636          * prior to 3.11.33 which contains the following change:
6637          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6638          */
6639         ixgbevf_rlpml_set_vf(hw, max_frame);
6640
6641         /* update max frame size */
6642         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6643         return 0;
6644 }
6645
6646 static inline struct ixgbe_5tuple_filter *
6647 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6648                         struct ixgbe_5tuple_filter_info *key)
6649 {
6650         struct ixgbe_5tuple_filter *it;
6651
6652         TAILQ_FOREACH(it, filter_list, entries) {
6653                 if (memcmp(key, &it->filter_info,
6654                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6655                         return it;
6656                 }
6657         }
6658         return NULL;
6659 }
6660
6661 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6662 static inline int
6663 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6664                         struct ixgbe_5tuple_filter_info *filter_info)
6665 {
6666         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6667                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6668                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6669                 return -EINVAL;
6670
6671         switch (filter->dst_ip_mask) {
6672         case UINT32_MAX:
6673                 filter_info->dst_ip_mask = 0;
6674                 filter_info->dst_ip = filter->dst_ip;
6675                 break;
6676         case 0:
6677                 filter_info->dst_ip_mask = 1;
6678                 break;
6679         default:
6680                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6681                 return -EINVAL;
6682         }
6683
6684         switch (filter->src_ip_mask) {
6685         case UINT32_MAX:
6686                 filter_info->src_ip_mask = 0;
6687                 filter_info->src_ip = filter->src_ip;
6688                 break;
6689         case 0:
6690                 filter_info->src_ip_mask = 1;
6691                 break;
6692         default:
6693                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6694                 return -EINVAL;
6695         }
6696
6697         switch (filter->dst_port_mask) {
6698         case UINT16_MAX:
6699                 filter_info->dst_port_mask = 0;
6700                 filter_info->dst_port = filter->dst_port;
6701                 break;
6702         case 0:
6703                 filter_info->dst_port_mask = 1;
6704                 break;
6705         default:
6706                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6707                 return -EINVAL;
6708         }
6709
6710         switch (filter->src_port_mask) {
6711         case UINT16_MAX:
6712                 filter_info->src_port_mask = 0;
6713                 filter_info->src_port = filter->src_port;
6714                 break;
6715         case 0:
6716                 filter_info->src_port_mask = 1;
6717                 break;
6718         default:
6719                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6720                 return -EINVAL;
6721         }
6722
6723         switch (filter->proto_mask) {
6724         case UINT8_MAX:
6725                 filter_info->proto_mask = 0;
6726                 filter_info->proto =
6727                         convert_protocol_type(filter->proto);
6728                 break;
6729         case 0:
6730                 filter_info->proto_mask = 1;
6731                 break;
6732         default:
6733                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6734                 return -EINVAL;
6735         }
6736
6737         filter_info->priority = (uint8_t)filter->priority;
6738         return 0;
6739 }
6740
6741 /*
6742  * add or delete a ntuple filter
6743  *
6744  * @param
6745  * dev: Pointer to struct rte_eth_dev.
6746  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6747  * add: if true, add filter, if false, remove filter
6748  *
6749  * @return
6750  *    - On success, zero.
6751  *    - On failure, a negative value.
6752  */
6753 int
6754 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6755                         struct rte_eth_ntuple_filter *ntuple_filter,
6756                         bool add)
6757 {
6758         struct ixgbe_filter_info *filter_info =
6759                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6760         struct ixgbe_5tuple_filter_info filter_5tuple;
6761         struct ixgbe_5tuple_filter *filter;
6762         int ret;
6763
6764         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6765                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6766                 return -EINVAL;
6767         }
6768
6769         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6770         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6771         if (ret < 0)
6772                 return ret;
6773
6774         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6775                                          &filter_5tuple);
6776         if (filter != NULL && add) {
6777                 PMD_DRV_LOG(ERR, "filter exists.");
6778                 return -EEXIST;
6779         }
6780         if (filter == NULL && !add) {
6781                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6782                 return -ENOENT;
6783         }
6784
6785         if (add) {
6786                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6787                                 sizeof(struct ixgbe_5tuple_filter), 0);
6788                 if (filter == NULL)
6789                         return -ENOMEM;
6790                 rte_memcpy(&filter->filter_info,
6791                                  &filter_5tuple,
6792                                  sizeof(struct ixgbe_5tuple_filter_info));
6793                 filter->queue = ntuple_filter->queue;
6794                 ret = ixgbe_add_5tuple_filter(dev, filter);
6795                 if (ret < 0) {
6796                         rte_free(filter);
6797                         return ret;
6798                 }
6799         } else
6800                 ixgbe_remove_5tuple_filter(dev, filter);
6801
6802         return 0;
6803 }
6804
6805 /*
6806  * get a ntuple filter
6807  *
6808  * @param
6809  * dev: Pointer to struct rte_eth_dev.
6810  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6811  *
6812  * @return
6813  *    - On success, zero.
6814  *    - On failure, a negative value.
6815  */
6816 static int
6817 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6818                         struct rte_eth_ntuple_filter *ntuple_filter)
6819 {
6820         struct ixgbe_filter_info *filter_info =
6821                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6822         struct ixgbe_5tuple_filter_info filter_5tuple;
6823         struct ixgbe_5tuple_filter *filter;
6824         int ret;
6825
6826         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6827                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6828                 return -EINVAL;
6829         }
6830
6831         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6832         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6833         if (ret < 0)
6834                 return ret;
6835
6836         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6837                                          &filter_5tuple);
6838         if (filter == NULL) {
6839                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6840                 return -ENOENT;
6841         }
6842         ntuple_filter->queue = filter->queue;
6843         return 0;
6844 }
6845
6846 /*
6847  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6848  * @dev: pointer to rte_eth_dev structure
6849  * @filter_op:operation will be taken.
6850  * @arg: a pointer to specific structure corresponding to the filter_op
6851  *
6852  * @return
6853  *    - On success, zero.
6854  *    - On failure, a negative value.
6855  */
6856 static int
6857 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6858                                 enum rte_filter_op filter_op,
6859                                 void *arg)
6860 {
6861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6862         int ret;
6863
6864         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6865
6866         if (filter_op == RTE_ETH_FILTER_NOP)
6867                 return 0;
6868
6869         if (arg == NULL) {
6870                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6871                             filter_op);
6872                 return -EINVAL;
6873         }
6874
6875         switch (filter_op) {
6876         case RTE_ETH_FILTER_ADD:
6877                 ret = ixgbe_add_del_ntuple_filter(dev,
6878                         (struct rte_eth_ntuple_filter *)arg,
6879                         TRUE);
6880                 break;
6881         case RTE_ETH_FILTER_DELETE:
6882                 ret = ixgbe_add_del_ntuple_filter(dev,
6883                         (struct rte_eth_ntuple_filter *)arg,
6884                         FALSE);
6885                 break;
6886         case RTE_ETH_FILTER_GET:
6887                 ret = ixgbe_get_ntuple_filter(dev,
6888                         (struct rte_eth_ntuple_filter *)arg);
6889                 break;
6890         default:
6891                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6892                 ret = -EINVAL;
6893                 break;
6894         }
6895         return ret;
6896 }
6897
6898 int
6899 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6900                         struct rte_eth_ethertype_filter *filter,
6901                         bool add)
6902 {
6903         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6904         struct ixgbe_filter_info *filter_info =
6905                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6906         uint32_t etqf = 0;
6907         uint32_t etqs = 0;
6908         int ret;
6909         struct ixgbe_ethertype_filter ethertype_filter;
6910
6911         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6912                 return -EINVAL;
6913
6914         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6915                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6916                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6917                         " ethertype filter.", filter->ether_type);
6918                 return -EINVAL;
6919         }
6920
6921         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6922                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6923                 return -EINVAL;
6924         }
6925         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6926                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6927                 return -EINVAL;
6928         }
6929
6930         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6931         if (ret >= 0 && add) {
6932                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6933                             filter->ether_type);
6934                 return -EEXIST;
6935         }
6936         if (ret < 0 && !add) {
6937                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6938                             filter->ether_type);
6939                 return -ENOENT;
6940         }
6941
6942         if (add) {
6943                 etqf = IXGBE_ETQF_FILTER_EN;
6944                 etqf |= (uint32_t)filter->ether_type;
6945                 etqs |= (uint32_t)((filter->queue <<
6946                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6947                                     IXGBE_ETQS_RX_QUEUE);
6948                 etqs |= IXGBE_ETQS_QUEUE_EN;
6949
6950                 ethertype_filter.ethertype = filter->ether_type;
6951                 ethertype_filter.etqf = etqf;
6952                 ethertype_filter.etqs = etqs;
6953                 ethertype_filter.conf = FALSE;
6954                 ret = ixgbe_ethertype_filter_insert(filter_info,
6955                                                     &ethertype_filter);
6956                 if (ret < 0) {
6957                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6958                         return -ENOSPC;
6959                 }
6960         } else {
6961                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6962                 if (ret < 0)
6963                         return -ENOSYS;
6964         }
6965         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6966         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6967         IXGBE_WRITE_FLUSH(hw);
6968
6969         return 0;
6970 }
6971
6972 static int
6973 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6974                      enum rte_filter_type filter_type,
6975                      enum rte_filter_op filter_op,
6976                      void *arg)
6977 {
6978         int ret = 0;
6979
6980         switch (filter_type) {
6981         case RTE_ETH_FILTER_NTUPLE:
6982                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6983                 break;
6984         case RTE_ETH_FILTER_SYN:
6985                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6986                 break;
6987         case RTE_ETH_FILTER_FDIR:
6988                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6989                 break;
6990         case RTE_ETH_FILTER_L2_TUNNEL:
6991                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6992                 break;
6993         case RTE_ETH_FILTER_GENERIC:
6994                 if (filter_op != RTE_ETH_FILTER_GET)
6995                         return -EINVAL;
6996                 *(const void **)arg = &ixgbe_flow_ops;
6997                 break;
6998         default:
6999                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7000                                                         filter_type);
7001                 ret = -EINVAL;
7002                 break;
7003         }
7004
7005         return ret;
7006 }
7007
7008 static u8 *
7009 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7010                         u8 **mc_addr_ptr, u32 *vmdq)
7011 {
7012         u8 *mc_addr;
7013
7014         *vmdq = 0;
7015         mc_addr = *mc_addr_ptr;
7016         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7017         return mc_addr;
7018 }
7019
7020 static int
7021 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7022                           struct rte_ether_addr *mc_addr_set,
7023                           uint32_t nb_mc_addr)
7024 {
7025         struct ixgbe_hw *hw;
7026         u8 *mc_addr_list;
7027
7028         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7029         mc_addr_list = (u8 *)mc_addr_set;
7030         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7031                                          ixgbe_dev_addr_list_itr, TRUE);
7032 }
7033
7034 static uint64_t
7035 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7036 {
7037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7038         uint64_t systime_cycles;
7039
7040         switch (hw->mac.type) {
7041         case ixgbe_mac_X550:
7042         case ixgbe_mac_X550EM_x:
7043         case ixgbe_mac_X550EM_a:
7044                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7045                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7046                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7047                                 * NSEC_PER_SEC;
7048                 break;
7049         default:
7050                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7051                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7052                                 << 32;
7053         }
7054
7055         return systime_cycles;
7056 }
7057
7058 static uint64_t
7059 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7060 {
7061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7062         uint64_t rx_tstamp_cycles;
7063
7064         switch (hw->mac.type) {
7065         case ixgbe_mac_X550:
7066         case ixgbe_mac_X550EM_x:
7067         case ixgbe_mac_X550EM_a:
7068                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7069                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7070                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7071                                 * NSEC_PER_SEC;
7072                 break;
7073         default:
7074                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7075                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7076                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7077                                 << 32;
7078         }
7079
7080         return rx_tstamp_cycles;
7081 }
7082
7083 static uint64_t
7084 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7085 {
7086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087         uint64_t tx_tstamp_cycles;
7088
7089         switch (hw->mac.type) {
7090         case ixgbe_mac_X550:
7091         case ixgbe_mac_X550EM_x:
7092         case ixgbe_mac_X550EM_a:
7093                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7094                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7095                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7096                                 * NSEC_PER_SEC;
7097                 break;
7098         default:
7099                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7100                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7101                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7102                                 << 32;
7103         }
7104
7105         return tx_tstamp_cycles;
7106 }
7107
7108 static void
7109 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7110 {
7111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7112         struct ixgbe_adapter *adapter = dev->data->dev_private;
7113         struct rte_eth_link link;
7114         uint32_t incval = 0;
7115         uint32_t shift = 0;
7116
7117         /* Get current link speed. */
7118         ixgbe_dev_link_update(dev, 1);
7119         rte_eth_linkstatus_get(dev, &link);
7120
7121         switch (link.link_speed) {
7122         case ETH_SPEED_NUM_100M:
7123                 incval = IXGBE_INCVAL_100;
7124                 shift = IXGBE_INCVAL_SHIFT_100;
7125                 break;
7126         case ETH_SPEED_NUM_1G:
7127                 incval = IXGBE_INCVAL_1GB;
7128                 shift = IXGBE_INCVAL_SHIFT_1GB;
7129                 break;
7130         case ETH_SPEED_NUM_10G:
7131         default:
7132                 incval = IXGBE_INCVAL_10GB;
7133                 shift = IXGBE_INCVAL_SHIFT_10GB;
7134                 break;
7135         }
7136
7137         switch (hw->mac.type) {
7138         case ixgbe_mac_X550:
7139         case ixgbe_mac_X550EM_x:
7140         case ixgbe_mac_X550EM_a:
7141                 /* Independent of link speed. */
7142                 incval = 1;
7143                 /* Cycles read will be interpreted as ns. */
7144                 shift = 0;
7145                 /* Fall-through */
7146         case ixgbe_mac_X540:
7147                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7148                 break;
7149         case ixgbe_mac_82599EB:
7150                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7151                 shift -= IXGBE_INCVAL_SHIFT_82599;
7152                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7153                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7154                 break;
7155         default:
7156                 /* Not supported. */
7157                 return;
7158         }
7159
7160         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7161         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7162         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7163
7164         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7165         adapter->systime_tc.cc_shift = shift;
7166         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7167
7168         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7169         adapter->rx_tstamp_tc.cc_shift = shift;
7170         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7171
7172         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7173         adapter->tx_tstamp_tc.cc_shift = shift;
7174         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7175 }
7176
7177 static int
7178 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7179 {
7180         struct ixgbe_adapter *adapter = dev->data->dev_private;
7181
7182         adapter->systime_tc.nsec += delta;
7183         adapter->rx_tstamp_tc.nsec += delta;
7184         adapter->tx_tstamp_tc.nsec += delta;
7185
7186         return 0;
7187 }
7188
7189 static int
7190 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7191 {
7192         uint64_t ns;
7193         struct ixgbe_adapter *adapter = dev->data->dev_private;
7194
7195         ns = rte_timespec_to_ns(ts);
7196         /* Set the timecounters to a new value. */
7197         adapter->systime_tc.nsec = ns;
7198         adapter->rx_tstamp_tc.nsec = ns;
7199         adapter->tx_tstamp_tc.nsec = ns;
7200
7201         return 0;
7202 }
7203
7204 static int
7205 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7206 {
7207         uint64_t ns, systime_cycles;
7208         struct ixgbe_adapter *adapter = dev->data->dev_private;
7209
7210         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7211         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7212         *ts = rte_ns_to_timespec(ns);
7213
7214         return 0;
7215 }
7216
7217 static int
7218 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7219 {
7220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7221         uint32_t tsync_ctl;
7222         uint32_t tsauxc;
7223
7224         /* Stop the timesync system time. */
7225         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7226         /* Reset the timesync system time value. */
7227         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7228         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7229
7230         /* Enable system time for platforms where it isn't on by default. */
7231         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7232         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7233         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7234
7235         ixgbe_start_timecounters(dev);
7236
7237         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7238         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7239                         (RTE_ETHER_TYPE_1588 |
7240                          IXGBE_ETQF_FILTER_EN |
7241                          IXGBE_ETQF_1588));
7242
7243         /* Enable timestamping of received PTP packets. */
7244         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7245         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7246         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7247
7248         /* Enable timestamping of transmitted PTP packets. */
7249         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7250         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7251         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7252
7253         IXGBE_WRITE_FLUSH(hw);
7254
7255         return 0;
7256 }
7257
7258 static int
7259 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7260 {
7261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7262         uint32_t tsync_ctl;
7263
7264         /* Disable timestamping of transmitted PTP packets. */
7265         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7266         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7267         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7268
7269         /* Disable timestamping of received PTP packets. */
7270         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7271         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7272         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7273
7274         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7275         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7276
7277         /* Stop incrementating the System Time registers. */
7278         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7279
7280         return 0;
7281 }
7282
7283 static int
7284 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7285                                  struct timespec *timestamp,
7286                                  uint32_t flags __rte_unused)
7287 {
7288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7289         struct ixgbe_adapter *adapter = dev->data->dev_private;
7290         uint32_t tsync_rxctl;
7291         uint64_t rx_tstamp_cycles;
7292         uint64_t ns;
7293
7294         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7295         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7296                 return -EINVAL;
7297
7298         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7299         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7300         *timestamp = rte_ns_to_timespec(ns);
7301
7302         return  0;
7303 }
7304
7305 static int
7306 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7307                                  struct timespec *timestamp)
7308 {
7309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7310         struct ixgbe_adapter *adapter = dev->data->dev_private;
7311         uint32_t tsync_txctl;
7312         uint64_t tx_tstamp_cycles;
7313         uint64_t ns;
7314
7315         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7316         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7317                 return -EINVAL;
7318
7319         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7320         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7321         *timestamp = rte_ns_to_timespec(ns);
7322
7323         return 0;
7324 }
7325
7326 static int
7327 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7328 {
7329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7330         int count = 0;
7331         int g_ind = 0;
7332         const struct reg_info *reg_group;
7333         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7334                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7335
7336         while ((reg_group = reg_set[g_ind++]))
7337                 count += ixgbe_regs_group_count(reg_group);
7338
7339         return count;
7340 }
7341
7342 static int
7343 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7344 {
7345         int count = 0;
7346         int g_ind = 0;
7347         const struct reg_info *reg_group;
7348
7349         while ((reg_group = ixgbevf_regs[g_ind++]))
7350                 count += ixgbe_regs_group_count(reg_group);
7351
7352         return count;
7353 }
7354
7355 static int
7356 ixgbe_get_regs(struct rte_eth_dev *dev,
7357               struct rte_dev_reg_info *regs)
7358 {
7359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7360         uint32_t *data = regs->data;
7361         int g_ind = 0;
7362         int count = 0;
7363         const struct reg_info *reg_group;
7364         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7365                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7366
7367         if (data == NULL) {
7368                 regs->length = ixgbe_get_reg_length(dev);
7369                 regs->width = sizeof(uint32_t);
7370                 return 0;
7371         }
7372
7373         /* Support only full register dump */
7374         if ((regs->length == 0) ||
7375             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7376                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7377                         hw->device_id;
7378                 while ((reg_group = reg_set[g_ind++]))
7379                         count += ixgbe_read_regs_group(dev, &data[count],
7380                                 reg_group);
7381                 return 0;
7382         }
7383
7384         return -ENOTSUP;
7385 }
7386
7387 static int
7388 ixgbevf_get_regs(struct rte_eth_dev *dev,
7389                 struct rte_dev_reg_info *regs)
7390 {
7391         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7392         uint32_t *data = regs->data;
7393         int g_ind = 0;
7394         int count = 0;
7395         const struct reg_info *reg_group;
7396
7397         if (data == NULL) {
7398                 regs->length = ixgbevf_get_reg_length(dev);
7399                 regs->width = sizeof(uint32_t);
7400                 return 0;
7401         }
7402
7403         /* Support only full register dump */
7404         if ((regs->length == 0) ||
7405             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7406                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7407                         hw->device_id;
7408                 while ((reg_group = ixgbevf_regs[g_ind++]))
7409                         count += ixgbe_read_regs_group(dev, &data[count],
7410                                                       reg_group);
7411                 return 0;
7412         }
7413
7414         return -ENOTSUP;
7415 }
7416
7417 static int
7418 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7419 {
7420         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7421
7422         /* Return unit is byte count */
7423         return hw->eeprom.word_size * 2;
7424 }
7425
7426 static int
7427 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7428                 struct rte_dev_eeprom_info *in_eeprom)
7429 {
7430         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7431         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7432         uint16_t *data = in_eeprom->data;
7433         int first, length;
7434
7435         first = in_eeprom->offset >> 1;
7436         length = in_eeprom->length >> 1;
7437         if ((first > hw->eeprom.word_size) ||
7438             ((first + length) > hw->eeprom.word_size))
7439                 return -EINVAL;
7440
7441         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7442
7443         return eeprom->ops.read_buffer(hw, first, length, data);
7444 }
7445
7446 static int
7447 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7448                 struct rte_dev_eeprom_info *in_eeprom)
7449 {
7450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7451         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7452         uint16_t *data = in_eeprom->data;
7453         int first, length;
7454
7455         first = in_eeprom->offset >> 1;
7456         length = in_eeprom->length >> 1;
7457         if ((first > hw->eeprom.word_size) ||
7458             ((first + length) > hw->eeprom.word_size))
7459                 return -EINVAL;
7460
7461         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7462
7463         return eeprom->ops.write_buffer(hw,  first, length, data);
7464 }
7465
7466 static int
7467 ixgbe_get_module_info(struct rte_eth_dev *dev,
7468                       struct rte_eth_dev_module_info *modinfo)
7469 {
7470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7471         uint32_t status;
7472         uint8_t sff8472_rev, addr_mode;
7473         bool page_swap = false;
7474
7475         /* Check whether we support SFF-8472 or not */
7476         status = hw->phy.ops.read_i2c_eeprom(hw,
7477                                              IXGBE_SFF_SFF_8472_COMP,
7478                                              &sff8472_rev);
7479         if (status != 0)
7480                 return -EIO;
7481
7482         /* addressing mode is not supported */
7483         status = hw->phy.ops.read_i2c_eeprom(hw,
7484                                              IXGBE_SFF_SFF_8472_SWAP,
7485                                              &addr_mode);
7486         if (status != 0)
7487                 return -EIO;
7488
7489         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7490                 PMD_DRV_LOG(ERR,
7491                             "Address change required to access page 0xA2, "
7492                             "but not supported. Please report the module "
7493                             "type to the driver maintainers.");
7494                 page_swap = true;
7495         }
7496
7497         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7498                 /* We have a SFP, but it does not support SFF-8472 */
7499                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7500                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7501         } else {
7502                 /* We have a SFP which supports a revision of SFF-8472. */
7503                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7504                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7505         }
7506
7507         return 0;
7508 }
7509
7510 static int
7511 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7512                         struct rte_dev_eeprom_info *info)
7513 {
7514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7515         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7516         uint8_t databyte = 0xFF;
7517         uint8_t *data = info->data;
7518         uint32_t i = 0;
7519
7520         if (info->length == 0)
7521                 return -EINVAL;
7522
7523         for (i = info->offset; i < info->offset + info->length; i++) {
7524                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7525                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7526                 else
7527                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7528
7529                 if (status != 0)
7530                         return -EIO;
7531
7532                 data[i - info->offset] = databyte;
7533         }
7534
7535         return 0;
7536 }
7537
7538 uint16_t
7539 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7540         switch (mac_type) {
7541         case ixgbe_mac_X550:
7542         case ixgbe_mac_X550EM_x:
7543         case ixgbe_mac_X550EM_a:
7544                 return ETH_RSS_RETA_SIZE_512;
7545         case ixgbe_mac_X550_vf:
7546         case ixgbe_mac_X550EM_x_vf:
7547         case ixgbe_mac_X550EM_a_vf:
7548                 return ETH_RSS_RETA_SIZE_64;
7549         case ixgbe_mac_X540_vf:
7550         case ixgbe_mac_82599_vf:
7551                 return 0;
7552         default:
7553                 return ETH_RSS_RETA_SIZE_128;
7554         }
7555 }
7556
7557 uint32_t
7558 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7559         switch (mac_type) {
7560         case ixgbe_mac_X550:
7561         case ixgbe_mac_X550EM_x:
7562         case ixgbe_mac_X550EM_a:
7563                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7564                         return IXGBE_RETA(reta_idx >> 2);
7565                 else
7566                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7567         case ixgbe_mac_X550_vf:
7568         case ixgbe_mac_X550EM_x_vf:
7569         case ixgbe_mac_X550EM_a_vf:
7570                 return IXGBE_VFRETA(reta_idx >> 2);
7571         default:
7572                 return IXGBE_RETA(reta_idx >> 2);
7573         }
7574 }
7575
7576 uint32_t
7577 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7578         switch (mac_type) {
7579         case ixgbe_mac_X550_vf:
7580         case ixgbe_mac_X550EM_x_vf:
7581         case ixgbe_mac_X550EM_a_vf:
7582                 return IXGBE_VFMRQC;
7583         default:
7584                 return IXGBE_MRQC;
7585         }
7586 }
7587
7588 uint32_t
7589 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7590         switch (mac_type) {
7591         case ixgbe_mac_X550_vf:
7592         case ixgbe_mac_X550EM_x_vf:
7593         case ixgbe_mac_X550EM_a_vf:
7594                 return IXGBE_VFRSSRK(i);
7595         default:
7596                 return IXGBE_RSSRK(i);
7597         }
7598 }
7599
7600 bool
7601 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7602         switch (mac_type) {
7603         case ixgbe_mac_82599_vf:
7604         case ixgbe_mac_X540_vf:
7605                 return 0;
7606         default:
7607                 return 1;
7608         }
7609 }
7610
7611 static int
7612 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7613                         struct rte_eth_dcb_info *dcb_info)
7614 {
7615         struct ixgbe_dcb_config *dcb_config =
7616                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7617         struct ixgbe_dcb_tc_config *tc;
7618         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7619         uint8_t nb_tcs;
7620         uint8_t i, j;
7621
7622         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7623                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7624         else
7625                 dcb_info->nb_tcs = 1;
7626
7627         tc_queue = &dcb_info->tc_queue;
7628         nb_tcs = dcb_info->nb_tcs;
7629
7630         if (dcb_config->vt_mode) { /* vt is enabled*/
7631                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7632                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7633                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7634                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7635                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7636                         for (j = 0; j < nb_tcs; j++) {
7637                                 tc_queue->tc_rxq[0][j].base = j;
7638                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7639                                 tc_queue->tc_txq[0][j].base = j;
7640                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7641                         }
7642                 } else {
7643                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7644                                 for (j = 0; j < nb_tcs; j++) {
7645                                         tc_queue->tc_rxq[i][j].base =
7646                                                 i * nb_tcs + j;
7647                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7648                                         tc_queue->tc_txq[i][j].base =
7649                                                 i * nb_tcs + j;
7650                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7651                                 }
7652                         }
7653                 }
7654         } else { /* vt is disabled*/
7655                 struct rte_eth_dcb_rx_conf *rx_conf =
7656                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7657                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7658                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7659                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7660                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7661                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7662                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7663                         }
7664                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7665                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7666                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7667                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7668                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7669                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7670                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7671                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7672                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7673                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7674                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7675                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7676                         }
7677                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7678                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7679                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7680                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7681                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7682                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7683                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7684                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7685                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7686                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7687                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7688                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7689                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7690                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7691                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7692                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7693                 }
7694         }
7695         for (i = 0; i < dcb_info->nb_tcs; i++) {
7696                 tc = &dcb_config->tc_config[i];
7697                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7698         }
7699         return 0;
7700 }
7701
7702 /* Update e-tag ether type */
7703 static int
7704 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7705                             uint16_t ether_type)
7706 {
7707         uint32_t etag_etype;
7708
7709         if (hw->mac.type != ixgbe_mac_X550 &&
7710             hw->mac.type != ixgbe_mac_X550EM_x &&
7711             hw->mac.type != ixgbe_mac_X550EM_a) {
7712                 return -ENOTSUP;
7713         }
7714
7715         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7716         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7717         etag_etype |= ether_type;
7718         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7719         IXGBE_WRITE_FLUSH(hw);
7720
7721         return 0;
7722 }
7723
7724 /* Config l2 tunnel ether type */
7725 static int
7726 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7727                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7728 {
7729         int ret = 0;
7730         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7731         struct ixgbe_l2_tn_info *l2_tn_info =
7732                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7733
7734         if (l2_tunnel == NULL)
7735                 return -EINVAL;
7736
7737         switch (l2_tunnel->l2_tunnel_type) {
7738         case RTE_L2_TUNNEL_TYPE_E_TAG:
7739                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7740                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7741                 break;
7742         default:
7743                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7744                 ret = -EINVAL;
7745                 break;
7746         }
7747
7748         return ret;
7749 }
7750
7751 /* Enable e-tag tunnel */
7752 static int
7753 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7754 {
7755         uint32_t etag_etype;
7756
7757         if (hw->mac.type != ixgbe_mac_X550 &&
7758             hw->mac.type != ixgbe_mac_X550EM_x &&
7759             hw->mac.type != ixgbe_mac_X550EM_a) {
7760                 return -ENOTSUP;
7761         }
7762
7763         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7764         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7765         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7766         IXGBE_WRITE_FLUSH(hw);
7767
7768         return 0;
7769 }
7770
7771 /* Enable l2 tunnel */
7772 static int
7773 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7774                            enum rte_eth_tunnel_type l2_tunnel_type)
7775 {
7776         int ret = 0;
7777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7778         struct ixgbe_l2_tn_info *l2_tn_info =
7779                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7780
7781         switch (l2_tunnel_type) {
7782         case RTE_L2_TUNNEL_TYPE_E_TAG:
7783                 l2_tn_info->e_tag_en = TRUE;
7784                 ret = ixgbe_e_tag_enable(hw);
7785                 break;
7786         default:
7787                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7788                 ret = -EINVAL;
7789                 break;
7790         }
7791
7792         return ret;
7793 }
7794
7795 /* Disable e-tag tunnel */
7796 static int
7797 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7798 {
7799         uint32_t etag_etype;
7800
7801         if (hw->mac.type != ixgbe_mac_X550 &&
7802             hw->mac.type != ixgbe_mac_X550EM_x &&
7803             hw->mac.type != ixgbe_mac_X550EM_a) {
7804                 return -ENOTSUP;
7805         }
7806
7807         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7808         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7809         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7810         IXGBE_WRITE_FLUSH(hw);
7811
7812         return 0;
7813 }
7814
7815 /* Disable l2 tunnel */
7816 static int
7817 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7818                             enum rte_eth_tunnel_type l2_tunnel_type)
7819 {
7820         int ret = 0;
7821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7822         struct ixgbe_l2_tn_info *l2_tn_info =
7823                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7824
7825         switch (l2_tunnel_type) {
7826         case RTE_L2_TUNNEL_TYPE_E_TAG:
7827                 l2_tn_info->e_tag_en = FALSE;
7828                 ret = ixgbe_e_tag_disable(hw);
7829                 break;
7830         default:
7831                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7832                 ret = -EINVAL;
7833                 break;
7834         }
7835
7836         return ret;
7837 }
7838
7839 static int
7840 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7841                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7842 {
7843         int ret = 0;
7844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7845         uint32_t i, rar_entries;
7846         uint32_t rar_low, rar_high;
7847
7848         if (hw->mac.type != ixgbe_mac_X550 &&
7849             hw->mac.type != ixgbe_mac_X550EM_x &&
7850             hw->mac.type != ixgbe_mac_X550EM_a) {
7851                 return -ENOTSUP;
7852         }
7853
7854         rar_entries = ixgbe_get_num_rx_addrs(hw);
7855
7856         for (i = 1; i < rar_entries; i++) {
7857                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7858                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7859                 if ((rar_high & IXGBE_RAH_AV) &&
7860                     (rar_high & IXGBE_RAH_ADTYPE) &&
7861                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7862                      l2_tunnel->tunnel_id)) {
7863                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7864                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7865
7866                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7867
7868                         return ret;
7869                 }
7870         }
7871
7872         return ret;
7873 }
7874
7875 static int
7876 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7877                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7878 {
7879         int ret = 0;
7880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7881         uint32_t i, rar_entries;
7882         uint32_t rar_low, rar_high;
7883
7884         if (hw->mac.type != ixgbe_mac_X550 &&
7885             hw->mac.type != ixgbe_mac_X550EM_x &&
7886             hw->mac.type != ixgbe_mac_X550EM_a) {
7887                 return -ENOTSUP;
7888         }
7889
7890         /* One entry for one tunnel. Try to remove potential existing entry. */
7891         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7892
7893         rar_entries = ixgbe_get_num_rx_addrs(hw);
7894
7895         for (i = 1; i < rar_entries; i++) {
7896                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7897                 if (rar_high & IXGBE_RAH_AV) {
7898                         continue;
7899                 } else {
7900                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7901                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7902                         rar_low = l2_tunnel->tunnel_id;
7903
7904                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7905                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7906
7907                         return ret;
7908                 }
7909         }
7910
7911         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7912                      " Please remove a rule before adding a new one.");
7913         return -EINVAL;
7914 }
7915
7916 static inline struct ixgbe_l2_tn_filter *
7917 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7918                           struct ixgbe_l2_tn_key *key)
7919 {
7920         int ret;
7921
7922         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7923         if (ret < 0)
7924                 return NULL;
7925
7926         return l2_tn_info->hash_map[ret];
7927 }
7928
7929 static inline int
7930 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7931                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7932 {
7933         int ret;
7934
7935         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7936                                &l2_tn_filter->key);
7937
7938         if (ret < 0) {
7939                 PMD_DRV_LOG(ERR,
7940                             "Failed to insert L2 tunnel filter"
7941                             " to hash table %d!",
7942                             ret);
7943                 return ret;
7944         }
7945
7946         l2_tn_info->hash_map[ret] = l2_tn_filter;
7947
7948         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7949
7950         return 0;
7951 }
7952
7953 static inline int
7954 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7955                           struct ixgbe_l2_tn_key *key)
7956 {
7957         int ret;
7958         struct ixgbe_l2_tn_filter *l2_tn_filter;
7959
7960         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7961
7962         if (ret < 0) {
7963                 PMD_DRV_LOG(ERR,
7964                             "No such L2 tunnel filter to delete %d!",
7965                             ret);
7966                 return ret;
7967         }
7968
7969         l2_tn_filter = l2_tn_info->hash_map[ret];
7970         l2_tn_info->hash_map[ret] = NULL;
7971
7972         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7973         rte_free(l2_tn_filter);
7974
7975         return 0;
7976 }
7977
7978 /* Add l2 tunnel filter */
7979 int
7980 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7981                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7982                                bool restore)
7983 {
7984         int ret;
7985         struct ixgbe_l2_tn_info *l2_tn_info =
7986                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7987         struct ixgbe_l2_tn_key key;
7988         struct ixgbe_l2_tn_filter *node;
7989
7990         if (!restore) {
7991                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7992                 key.tn_id = l2_tunnel->tunnel_id;
7993
7994                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7995
7996                 if (node) {
7997                         PMD_DRV_LOG(ERR,
7998                                     "The L2 tunnel filter already exists!");
7999                         return -EINVAL;
8000                 }
8001
8002                 node = rte_zmalloc("ixgbe_l2_tn",
8003                                    sizeof(struct ixgbe_l2_tn_filter),
8004                                    0);
8005                 if (!node)
8006                         return -ENOMEM;
8007
8008                 rte_memcpy(&node->key,
8009                                  &key,
8010                                  sizeof(struct ixgbe_l2_tn_key));
8011                 node->pool = l2_tunnel->pool;
8012                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8013                 if (ret < 0) {
8014                         rte_free(node);
8015                         return ret;
8016                 }
8017         }
8018
8019         switch (l2_tunnel->l2_tunnel_type) {
8020         case RTE_L2_TUNNEL_TYPE_E_TAG:
8021                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8022                 break;
8023         default:
8024                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8025                 ret = -EINVAL;
8026                 break;
8027         }
8028
8029         if ((!restore) && (ret < 0))
8030                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8031
8032         return ret;
8033 }
8034
8035 /* Delete l2 tunnel filter */
8036 int
8037 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8038                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8039 {
8040         int ret;
8041         struct ixgbe_l2_tn_info *l2_tn_info =
8042                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8043         struct ixgbe_l2_tn_key key;
8044
8045         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8046         key.tn_id = l2_tunnel->tunnel_id;
8047         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8048         if (ret < 0)
8049                 return ret;
8050
8051         switch (l2_tunnel->l2_tunnel_type) {
8052         case RTE_L2_TUNNEL_TYPE_E_TAG:
8053                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8054                 break;
8055         default:
8056                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8057                 ret = -EINVAL;
8058                 break;
8059         }
8060
8061         return ret;
8062 }
8063
8064 /**
8065  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8066  * @dev: pointer to rte_eth_dev structure
8067  * @filter_op:operation will be taken.
8068  * @arg: a pointer to specific structure corresponding to the filter_op
8069  */
8070 static int
8071 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8072                                   enum rte_filter_op filter_op,
8073                                   void *arg)
8074 {
8075         int ret;
8076
8077         if (filter_op == RTE_ETH_FILTER_NOP)
8078                 return 0;
8079
8080         if (arg == NULL) {
8081                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8082                             filter_op);
8083                 return -EINVAL;
8084         }
8085
8086         switch (filter_op) {
8087         case RTE_ETH_FILTER_ADD:
8088                 ret = ixgbe_dev_l2_tunnel_filter_add
8089                         (dev,
8090                          (struct rte_eth_l2_tunnel_conf *)arg,
8091                          FALSE);
8092                 break;
8093         case RTE_ETH_FILTER_DELETE:
8094                 ret = ixgbe_dev_l2_tunnel_filter_del
8095                         (dev,
8096                          (struct rte_eth_l2_tunnel_conf *)arg);
8097                 break;
8098         default:
8099                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8100                 ret = -EINVAL;
8101                 break;
8102         }
8103         return ret;
8104 }
8105
8106 static int
8107 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8108 {
8109         int ret = 0;
8110         uint32_t ctrl;
8111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8112
8113         if (hw->mac.type != ixgbe_mac_X550 &&
8114             hw->mac.type != ixgbe_mac_X550EM_x &&
8115             hw->mac.type != ixgbe_mac_X550EM_a) {
8116                 return -ENOTSUP;
8117         }
8118
8119         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8120         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8121         if (en)
8122                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8123         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8124
8125         return ret;
8126 }
8127
8128 /* Enable l2 tunnel forwarding */
8129 static int
8130 ixgbe_dev_l2_tunnel_forwarding_enable
8131         (struct rte_eth_dev *dev,
8132          enum rte_eth_tunnel_type l2_tunnel_type)
8133 {
8134         struct ixgbe_l2_tn_info *l2_tn_info =
8135                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8136         int ret = 0;
8137
8138         switch (l2_tunnel_type) {
8139         case RTE_L2_TUNNEL_TYPE_E_TAG:
8140                 l2_tn_info->e_tag_fwd_en = TRUE;
8141                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8142                 break;
8143         default:
8144                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8145                 ret = -EINVAL;
8146                 break;
8147         }
8148
8149         return ret;
8150 }
8151
8152 /* Disable l2 tunnel forwarding */
8153 static int
8154 ixgbe_dev_l2_tunnel_forwarding_disable
8155         (struct rte_eth_dev *dev,
8156          enum rte_eth_tunnel_type l2_tunnel_type)
8157 {
8158         struct ixgbe_l2_tn_info *l2_tn_info =
8159                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8160         int ret = 0;
8161
8162         switch (l2_tunnel_type) {
8163         case RTE_L2_TUNNEL_TYPE_E_TAG:
8164                 l2_tn_info->e_tag_fwd_en = FALSE;
8165                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8166                 break;
8167         default:
8168                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8169                 ret = -EINVAL;
8170                 break;
8171         }
8172
8173         return ret;
8174 }
8175
8176 static int
8177 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8178                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8179                              bool en)
8180 {
8181         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8182         int ret = 0;
8183         uint32_t vmtir, vmvir;
8184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8185
8186         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8187                 PMD_DRV_LOG(ERR,
8188                             "VF id %u should be less than %u",
8189                             l2_tunnel->vf_id,
8190                             pci_dev->max_vfs);
8191                 return -EINVAL;
8192         }
8193
8194         if (hw->mac.type != ixgbe_mac_X550 &&
8195             hw->mac.type != ixgbe_mac_X550EM_x &&
8196             hw->mac.type != ixgbe_mac_X550EM_a) {
8197                 return -ENOTSUP;
8198         }
8199
8200         if (en)
8201                 vmtir = l2_tunnel->tunnel_id;
8202         else
8203                 vmtir = 0;
8204
8205         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8206
8207         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8208         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8209         if (en)
8210                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8211         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8212
8213         return ret;
8214 }
8215
8216 /* Enable l2 tunnel tag insertion */
8217 static int
8218 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8219                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8220 {
8221         int ret = 0;
8222
8223         switch (l2_tunnel->l2_tunnel_type) {
8224         case RTE_L2_TUNNEL_TYPE_E_TAG:
8225                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8226                 break;
8227         default:
8228                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8229                 ret = -EINVAL;
8230                 break;
8231         }
8232
8233         return ret;
8234 }
8235
8236 /* Disable l2 tunnel tag insertion */
8237 static int
8238 ixgbe_dev_l2_tunnel_insertion_disable
8239         (struct rte_eth_dev *dev,
8240          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8241 {
8242         int ret = 0;
8243
8244         switch (l2_tunnel->l2_tunnel_type) {
8245         case RTE_L2_TUNNEL_TYPE_E_TAG:
8246                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8247                 break;
8248         default:
8249                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8250                 ret = -EINVAL;
8251                 break;
8252         }
8253
8254         return ret;
8255 }
8256
8257 static int
8258 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8259                              bool en)
8260 {
8261         int ret = 0;
8262         uint32_t qde;
8263         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8264
8265         if (hw->mac.type != ixgbe_mac_X550 &&
8266             hw->mac.type != ixgbe_mac_X550EM_x &&
8267             hw->mac.type != ixgbe_mac_X550EM_a) {
8268                 return -ENOTSUP;
8269         }
8270
8271         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8272         if (en)
8273                 qde |= IXGBE_QDE_STRIP_TAG;
8274         else
8275                 qde &= ~IXGBE_QDE_STRIP_TAG;
8276         qde &= ~IXGBE_QDE_READ;
8277         qde |= IXGBE_QDE_WRITE;
8278         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8279
8280         return ret;
8281 }
8282
8283 /* Enable l2 tunnel tag stripping */
8284 static int
8285 ixgbe_dev_l2_tunnel_stripping_enable
8286         (struct rte_eth_dev *dev,
8287          enum rte_eth_tunnel_type l2_tunnel_type)
8288 {
8289         int ret = 0;
8290
8291         switch (l2_tunnel_type) {
8292         case RTE_L2_TUNNEL_TYPE_E_TAG:
8293                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8294                 break;
8295         default:
8296                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8297                 ret = -EINVAL;
8298                 break;
8299         }
8300
8301         return ret;
8302 }
8303
8304 /* Disable l2 tunnel tag stripping */
8305 static int
8306 ixgbe_dev_l2_tunnel_stripping_disable
8307         (struct rte_eth_dev *dev,
8308          enum rte_eth_tunnel_type l2_tunnel_type)
8309 {
8310         int ret = 0;
8311
8312         switch (l2_tunnel_type) {
8313         case RTE_L2_TUNNEL_TYPE_E_TAG:
8314                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8315                 break;
8316         default:
8317                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8318                 ret = -EINVAL;
8319                 break;
8320         }
8321
8322         return ret;
8323 }
8324
8325 /* Enable/disable l2 tunnel offload functions */
8326 static int
8327 ixgbe_dev_l2_tunnel_offload_set
8328         (struct rte_eth_dev *dev,
8329          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8330          uint32_t mask,
8331          uint8_t en)
8332 {
8333         int ret = 0;
8334
8335         if (l2_tunnel == NULL)
8336                 return -EINVAL;
8337
8338         ret = -EINVAL;
8339         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8340                 if (en)
8341                         ret = ixgbe_dev_l2_tunnel_enable(
8342                                 dev,
8343                                 l2_tunnel->l2_tunnel_type);
8344                 else
8345                         ret = ixgbe_dev_l2_tunnel_disable(
8346                                 dev,
8347                                 l2_tunnel->l2_tunnel_type);
8348         }
8349
8350         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8351                 if (en)
8352                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8353                                 dev,
8354                                 l2_tunnel);
8355                 else
8356                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8357                                 dev,
8358                                 l2_tunnel);
8359         }
8360
8361         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8362                 if (en)
8363                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8364                                 dev,
8365                                 l2_tunnel->l2_tunnel_type);
8366                 else
8367                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8368                                 dev,
8369                                 l2_tunnel->l2_tunnel_type);
8370         }
8371
8372         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8373                 if (en)
8374                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8375                                 dev,
8376                                 l2_tunnel->l2_tunnel_type);
8377                 else
8378                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8379                                 dev,
8380                                 l2_tunnel->l2_tunnel_type);
8381         }
8382
8383         return ret;
8384 }
8385
8386 static int
8387 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8388                         uint16_t port)
8389 {
8390         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8391         IXGBE_WRITE_FLUSH(hw);
8392
8393         return 0;
8394 }
8395
8396 /* There's only one register for VxLAN UDP port.
8397  * So, we cannot add several ports. Will update it.
8398  */
8399 static int
8400 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8401                      uint16_t port)
8402 {
8403         if (port == 0) {
8404                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8405                 return -EINVAL;
8406         }
8407
8408         return ixgbe_update_vxlan_port(hw, port);
8409 }
8410
8411 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8412  * UDP port, it must have a value.
8413  * So, will reset it to the original value 0.
8414  */
8415 static int
8416 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8417                      uint16_t port)
8418 {
8419         uint16_t cur_port;
8420
8421         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8422
8423         if (cur_port != port) {
8424                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8425                 return -EINVAL;
8426         }
8427
8428         return ixgbe_update_vxlan_port(hw, 0);
8429 }
8430
8431 /* Add UDP tunneling port */
8432 static int
8433 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8434                               struct rte_eth_udp_tunnel *udp_tunnel)
8435 {
8436         int ret = 0;
8437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8438
8439         if (hw->mac.type != ixgbe_mac_X550 &&
8440             hw->mac.type != ixgbe_mac_X550EM_x &&
8441             hw->mac.type != ixgbe_mac_X550EM_a) {
8442                 return -ENOTSUP;
8443         }
8444
8445         if (udp_tunnel == NULL)
8446                 return -EINVAL;
8447
8448         switch (udp_tunnel->prot_type) {
8449         case RTE_TUNNEL_TYPE_VXLAN:
8450                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8451                 break;
8452
8453         case RTE_TUNNEL_TYPE_GENEVE:
8454         case RTE_TUNNEL_TYPE_TEREDO:
8455                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8456                 ret = -EINVAL;
8457                 break;
8458
8459         default:
8460                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8461                 ret = -EINVAL;
8462                 break;
8463         }
8464
8465         return ret;
8466 }
8467
8468 /* Remove UDP tunneling port */
8469 static int
8470 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8471                               struct rte_eth_udp_tunnel *udp_tunnel)
8472 {
8473         int ret = 0;
8474         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8475
8476         if (hw->mac.type != ixgbe_mac_X550 &&
8477             hw->mac.type != ixgbe_mac_X550EM_x &&
8478             hw->mac.type != ixgbe_mac_X550EM_a) {
8479                 return -ENOTSUP;
8480         }
8481
8482         if (udp_tunnel == NULL)
8483                 return -EINVAL;
8484
8485         switch (udp_tunnel->prot_type) {
8486         case RTE_TUNNEL_TYPE_VXLAN:
8487                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8488                 break;
8489         case RTE_TUNNEL_TYPE_GENEVE:
8490         case RTE_TUNNEL_TYPE_TEREDO:
8491                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8492                 ret = -EINVAL;
8493                 break;
8494         default:
8495                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8496                 ret = -EINVAL;
8497                 break;
8498         }
8499
8500         return ret;
8501 }
8502
8503 static int
8504 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8505 {
8506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8507         int ret;
8508
8509         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8510         case IXGBE_SUCCESS:
8511                 ret = 0;
8512                 break;
8513         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8514                 ret = -ENOTSUP;
8515                 break;
8516         default:
8517                 ret = -EAGAIN;
8518                 break;
8519         }
8520
8521         return ret;
8522 }
8523
8524 static int
8525 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8526 {
8527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8528         int ret;
8529
8530         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8531         case IXGBE_SUCCESS:
8532                 ret = 0;
8533                 break;
8534         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8535                 ret = -ENOTSUP;
8536                 break;
8537         default:
8538                 ret = -EAGAIN;
8539                 break;
8540         }
8541
8542         return ret;
8543 }
8544
8545 static int
8546 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8547 {
8548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8549         int ret;
8550         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8551
8552         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8553         case IXGBE_SUCCESS:
8554                 ret = 0;
8555                 break;
8556         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8557                 ret = -ENOTSUP;
8558                 break;
8559         default:
8560                 ret = -EAGAIN;
8561                 break;
8562         }
8563
8564         return ret;
8565 }
8566
8567 static int
8568 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8569 {
8570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8571         int ret;
8572
8573         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8574         case IXGBE_SUCCESS:
8575                 ret = 0;
8576                 break;
8577         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8578                 ret = -ENOTSUP;
8579                 break;
8580         default:
8581                 ret = -EAGAIN;
8582                 break;
8583         }
8584
8585         return ret;
8586 }
8587
8588 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8589 {
8590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8591         u32 in_msg = 0;
8592
8593         /* peek the message first */
8594         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8595
8596         /* PF reset VF event */
8597         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8598                 /* dummy mbx read to ack pf */
8599                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8600                         return;
8601                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8602                                              NULL);
8603         }
8604 }
8605
8606 static int
8607 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8608 {
8609         uint32_t eicr;
8610         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8611         struct ixgbe_interrupt *intr =
8612                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8613         ixgbevf_intr_disable(dev);
8614
8615         /* read-on-clear nic registers here */
8616         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8617         intr->flags = 0;
8618
8619         /* only one misc vector supported - mailbox */
8620         eicr &= IXGBE_VTEICR_MASK;
8621         if (eicr == IXGBE_MISC_VEC_ID)
8622                 intr->flags |= IXGBE_FLAG_MAILBOX;
8623
8624         return 0;
8625 }
8626
8627 static int
8628 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8629 {
8630         struct ixgbe_interrupt *intr =
8631                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8632
8633         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8634                 ixgbevf_mbx_process(dev);
8635                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8636         }
8637
8638         ixgbevf_intr_enable(dev);
8639
8640         return 0;
8641 }
8642
8643 static void
8644 ixgbevf_dev_interrupt_handler(void *param)
8645 {
8646         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8647
8648         ixgbevf_dev_interrupt_get_status(dev);
8649         ixgbevf_dev_interrupt_action(dev);
8650 }
8651
8652 /**
8653  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8654  *  @hw: pointer to hardware structure
8655  *
8656  *  Stops the transmit data path and waits for the HW to internally empty
8657  *  the Tx security block
8658  **/
8659 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8660 {
8661 #define IXGBE_MAX_SECTX_POLL 40
8662
8663         int i;
8664         int sectxreg;
8665
8666         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8667         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8668         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8669         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8670                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8671                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8672                         break;
8673                 /* Use interrupt-safe sleep just in case */
8674                 usec_delay(1000);
8675         }
8676
8677         /* For informational purposes only */
8678         if (i >= IXGBE_MAX_SECTX_POLL)
8679                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8680                          "path fully disabled.  Continuing with init.");
8681
8682         return IXGBE_SUCCESS;
8683 }
8684
8685 /**
8686  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8687  *  @hw: pointer to hardware structure
8688  *
8689  *  Enables the transmit data path.
8690  **/
8691 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8692 {
8693         uint32_t sectxreg;
8694
8695         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8696         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8697         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8698         IXGBE_WRITE_FLUSH(hw);
8699
8700         return IXGBE_SUCCESS;
8701 }
8702
8703 /* restore n-tuple filter */
8704 static inline void
8705 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8706 {
8707         struct ixgbe_filter_info *filter_info =
8708                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8709         struct ixgbe_5tuple_filter *node;
8710
8711         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8712                 ixgbe_inject_5tuple_filter(dev, node);
8713         }
8714 }
8715
8716 /* restore ethernet type filter */
8717 static inline void
8718 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8719 {
8720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8721         struct ixgbe_filter_info *filter_info =
8722                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8723         int i;
8724
8725         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8726                 if (filter_info->ethertype_mask & (1 << i)) {
8727                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8728                                         filter_info->ethertype_filters[i].etqf);
8729                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8730                                         filter_info->ethertype_filters[i].etqs);
8731                         IXGBE_WRITE_FLUSH(hw);
8732                 }
8733         }
8734 }
8735
8736 /* restore SYN filter */
8737 static inline void
8738 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8739 {
8740         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8741         struct ixgbe_filter_info *filter_info =
8742                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8743         uint32_t synqf;
8744
8745         synqf = filter_info->syn_info;
8746
8747         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8748                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8749                 IXGBE_WRITE_FLUSH(hw);
8750         }
8751 }
8752
8753 /* restore L2 tunnel filter */
8754 static inline void
8755 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8756 {
8757         struct ixgbe_l2_tn_info *l2_tn_info =
8758                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8759         struct ixgbe_l2_tn_filter *node;
8760         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8761
8762         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8763                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8764                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8765                 l2_tn_conf.pool           = node->pool;
8766                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8767         }
8768 }
8769
8770 /* restore rss filter */
8771 static inline void
8772 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8773 {
8774         struct ixgbe_filter_info *filter_info =
8775                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8776
8777         if (filter_info->rss_info.conf.queue_num)
8778                 ixgbe_config_rss_filter(dev,
8779                         &filter_info->rss_info, TRUE);
8780 }
8781
8782 static int
8783 ixgbe_filter_restore(struct rte_eth_dev *dev)
8784 {
8785         ixgbe_ntuple_filter_restore(dev);
8786         ixgbe_ethertype_filter_restore(dev);
8787         ixgbe_syn_filter_restore(dev);
8788         ixgbe_fdir_filter_restore(dev);
8789         ixgbe_l2_tn_filter_restore(dev);
8790         ixgbe_rss_filter_restore(dev);
8791
8792         return 0;
8793 }
8794
8795 static void
8796 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8797 {
8798         struct ixgbe_l2_tn_info *l2_tn_info =
8799                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8801
8802         if (l2_tn_info->e_tag_en)
8803                 (void)ixgbe_e_tag_enable(hw);
8804
8805         if (l2_tn_info->e_tag_fwd_en)
8806                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8807
8808         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8809 }
8810
8811 /* remove all the n-tuple filters */
8812 void
8813 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8814 {
8815         struct ixgbe_filter_info *filter_info =
8816                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8817         struct ixgbe_5tuple_filter *p_5tuple;
8818
8819         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8820                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8821 }
8822
8823 /* remove all the ether type filters */
8824 void
8825 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8826 {
8827         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8828         struct ixgbe_filter_info *filter_info =
8829                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8830         int i;
8831
8832         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8833                 if (filter_info->ethertype_mask & (1 << i) &&
8834                     !filter_info->ethertype_filters[i].conf) {
8835                         (void)ixgbe_ethertype_filter_remove(filter_info,
8836                                                             (uint8_t)i);
8837                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8838                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8839                         IXGBE_WRITE_FLUSH(hw);
8840                 }
8841         }
8842 }
8843
8844 /* remove the SYN filter */
8845 void
8846 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8847 {
8848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8849         struct ixgbe_filter_info *filter_info =
8850                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8851
8852         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8853                 filter_info->syn_info = 0;
8854
8855                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8856                 IXGBE_WRITE_FLUSH(hw);
8857         }
8858 }
8859
8860 /* remove all the L2 tunnel filters */
8861 int
8862 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8863 {
8864         struct ixgbe_l2_tn_info *l2_tn_info =
8865                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8866         struct ixgbe_l2_tn_filter *l2_tn_filter;
8867         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8868         int ret = 0;
8869
8870         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8871                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8872                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8873                 l2_tn_conf.pool           = l2_tn_filter->pool;
8874                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8875                 if (ret < 0)
8876                         return ret;
8877         }
8878
8879         return 0;
8880 }
8881
8882 void
8883 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8884                                 struct ixgbe_macsec_setting *macsec_setting)
8885 {
8886         struct ixgbe_macsec_setting *macsec =
8887                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8888
8889         macsec->offload_en = macsec_setting->offload_en;
8890         macsec->encrypt_en = macsec_setting->encrypt_en;
8891         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8892 }
8893
8894 void
8895 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8896 {
8897         struct ixgbe_macsec_setting *macsec =
8898                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8899
8900         macsec->offload_en = 0;
8901         macsec->encrypt_en = 0;
8902         macsec->replayprotect_en = 0;
8903 }
8904
8905 void
8906 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8907                                 struct ixgbe_macsec_setting *macsec_setting)
8908 {
8909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8910         uint32_t ctrl;
8911         uint8_t en = macsec_setting->encrypt_en;
8912         uint8_t rp = macsec_setting->replayprotect_en;
8913
8914         /**
8915          * Workaround:
8916          * As no ixgbe_disable_sec_rx_path equivalent is
8917          * implemented for tx in the base code, and we are
8918          * not allowed to modify the base code in DPDK, so
8919          * just call the hand-written one directly for now.
8920          * The hardware support has been checked by
8921          * ixgbe_disable_sec_rx_path().
8922          */
8923         ixgbe_disable_sec_tx_path_generic(hw);
8924
8925         /* Enable Ethernet CRC (required by MACsec offload) */
8926         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8927         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8928         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8929
8930         /* Enable the TX and RX crypto engines */
8931         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8932         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8933         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8934
8935         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8936         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8937         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8938
8939         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8940         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8941         ctrl |= 0x3;
8942         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8943
8944         /* Enable SA lookup */
8945         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8946         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8947         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8948                      IXGBE_LSECTXCTRL_AUTH;
8949         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8950         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8951         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8952         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8953
8954         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8955         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8956         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8957         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8958         if (rp)
8959                 ctrl |= IXGBE_LSECRXCTRL_RP;
8960         else
8961                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8962         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8963
8964         /* Start the data paths */
8965         ixgbe_enable_sec_rx_path(hw);
8966         /**
8967          * Workaround:
8968          * As no ixgbe_enable_sec_rx_path equivalent is
8969          * implemented for tx in the base code, and we are
8970          * not allowed to modify the base code in DPDK, so
8971          * just call the hand-written one directly for now.
8972          */
8973         ixgbe_enable_sec_tx_path_generic(hw);
8974 }
8975
8976 void
8977 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8978 {
8979         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8980         uint32_t ctrl;
8981
8982         /**
8983          * Workaround:
8984          * As no ixgbe_disable_sec_rx_path equivalent is
8985          * implemented for tx in the base code, and we are
8986          * not allowed to modify the base code in DPDK, so
8987          * just call the hand-written one directly for now.
8988          * The hardware support has been checked by
8989          * ixgbe_disable_sec_rx_path().
8990          */
8991         ixgbe_disable_sec_tx_path_generic(hw);
8992
8993         /* Disable the TX and RX crypto engines */
8994         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8995         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8996         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8997
8998         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8999         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9000         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9001
9002         /* Disable SA lookup */
9003         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9004         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9005         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9006         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9007
9008         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9009         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9010         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9011         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9012
9013         /* Start the data paths */
9014         ixgbe_enable_sec_rx_path(hw);
9015         /**
9016          * Workaround:
9017          * As no ixgbe_enable_sec_rx_path equivalent is
9018          * implemented for tx in the base code, and we are
9019          * not allowed to modify the base code in DPDK, so
9020          * just call the hand-written one directly for now.
9021          */
9022         ixgbe_enable_sec_tx_path_generic(hw);
9023 }
9024
9025 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9026 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9027 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9028 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9029 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9030 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9031 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9032                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9033
9034 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9035 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9036
9037 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9038 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9039 #endif
9040 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9041 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9042 #endif
9043 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9044 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9045 #endif