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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
64 #include "ixgbe_logs.h"
65 #include "base/ixgbe_api.h"
66 #include "base/ixgbe_vf.h"
67 #include "base/ixgbe_common.h"
68 #include "ixgbe_ethdev.h"
69 #include "ixgbe_bypass.h"
70 #include "ixgbe_rxtx.h"
71 #include "base/ixgbe_type.h"
72 #include "base/ixgbe_phy.h"
73 #include "ixgbe_regs.h"
76 * High threshold controlling when to start sending XOFF frames. Must be at
77 * least 8 bytes less than receive packet buffer size. This value is in units
80 #define IXGBE_FC_HI 0x80
83 * Low threshold controlling when to start sending XON frames. This value is
84 * in units of 1024 bytes.
86 #define IXGBE_FC_LO 0x40
88 /* Default minimum inter-interrupt interval for EITR configuration */
89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
91 /* Timer value included in XOFF frames. */
92 #define IXGBE_FC_PAUSE 0x680
94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
95 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
96 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
98 #define IXGBE_MMW_SIZE_DEFAULT 0x4
99 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
100 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
103 * Default values for RX/TX configuration
105 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
106 #define IXGBE_DEFAULT_RX_PTHRESH 8
107 #define IXGBE_DEFAULT_RX_HTHRESH 8
108 #define IXGBE_DEFAULT_RX_WTHRESH 0
110 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
111 #define IXGBE_DEFAULT_TX_PTHRESH 32
112 #define IXGBE_DEFAULT_TX_HTHRESH 0
113 #define IXGBE_DEFAULT_TX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
116 /* Bit shift and mask */
117 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
118 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
119 #define IXGBE_8_BIT_WIDTH CHAR_BIT
120 #define IXGBE_8_BIT_MASK UINT8_MAX
122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
126 #define IXGBE_HKEY_MAX_INDEX 10
128 /* Additional timesync values. */
129 #define NSEC_PER_SEC 1000000000L
130 #define IXGBE_INCVAL_10GB 0x66666666
131 #define IXGBE_INCVAL_1GB 0x40000000
132 #define IXGBE_INCVAL_100 0x50000000
133 #define IXGBE_INCVAL_SHIFT_10GB 28
134 #define IXGBE_INCVAL_SHIFT_1GB 24
135 #define IXGBE_INCVAL_SHIFT_100 21
136 #define IXGBE_INCVAL_SHIFT_82599 7
137 #define IXGBE_INCPER_SHIFT_82599 24
139 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
141 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
143 #define DEFAULT_ETAG_ETYPE 0x893f
144 #define IXGBE_ETAG_ETYPE 0x00005084
145 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
146 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
147 #define IXGBE_RAH_ADTYPE 0x40000000
148 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
149 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
152 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
155 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
156 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
157 static int ixgbe_dev_start(struct rte_eth_dev *dev);
158 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
159 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
160 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
161 static void ixgbe_dev_close(struct rte_eth_dev *dev);
162 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
163 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
164 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
165 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
166 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
167 int wait_to_complete);
168 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
169 struct rte_eth_stats *stats);
170 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
171 struct rte_eth_xstats *xstats, unsigned n);
172 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
173 struct rte_eth_xstats *xstats, unsigned n);
174 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
175 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
180 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
181 struct rte_eth_dev_info *dev_info);
182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
183 struct rte_eth_dev_info *dev_info);
184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
187 uint16_t vlan_id, int on);
188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
189 enum rte_vlan_type vlan_type,
191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
192 uint16_t queue, bool on);
193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
195 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
204 struct rte_eth_fc_conf *fc_conf);
205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
206 struct rte_eth_fc_conf *fc_conf);
207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
208 struct rte_eth_pfc_conf *pfc_conf);
209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
217 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
218 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
219 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
220 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
223 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
224 uint32_t index, uint32_t pool);
225 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
226 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
227 struct ether_addr *mac_addr);
228 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
230 /* For Virtual Function support */
231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
233 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
234 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
235 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
236 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
237 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
238 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
239 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
240 struct rte_eth_stats *stats);
241 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
242 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
243 uint16_t vlan_id, int on);
244 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
245 uint16_t queue, int on);
246 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
247 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
248 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
250 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
252 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
253 uint8_t queue, uint8_t msix_vector);
254 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
256 /* For Eth VMDQ APIs support */
257 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
258 ether_addr* mac_addr,uint8_t on);
259 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
260 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
261 uint16_t rx_mask, uint8_t on);
262 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
263 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
264 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
265 uint64_t pool_mask,uint8_t vlan_on);
266 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
267 struct rte_eth_mirror_conf *mirror_conf,
268 uint8_t rule_id, uint8_t on);
269 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
271 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
273 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
275 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
276 uint8_t queue, uint8_t msix_vector);
277 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
279 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
280 uint16_t queue_idx, uint16_t tx_rate);
281 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
282 uint16_t tx_rate, uint64_t q_msk);
284 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
285 struct ether_addr *mac_addr,
286 uint32_t index, uint32_t pool);
287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
289 struct ether_addr *mac_addr);
290 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
291 struct rte_eth_syn_filter *filter,
293 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
294 struct rte_eth_syn_filter *filter);
295 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
296 enum rte_filter_op filter_op,
298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
299 struct ixgbe_5tuple_filter *filter);
300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
301 struct ixgbe_5tuple_filter *filter);
302 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
303 struct rte_eth_ntuple_filter *filter,
305 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
306 enum rte_filter_op filter_op,
308 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
309 struct rte_eth_ntuple_filter *filter);
310 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
311 struct rte_eth_ethertype_filter *filter,
313 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
314 enum rte_filter_op filter_op,
316 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
317 struct rte_eth_ethertype_filter *filter);
318 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
319 enum rte_filter_type filter_type,
320 enum rte_filter_op filter_op,
322 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
324 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
325 struct ether_addr *mc_addr_set,
326 uint32_t nb_mc_addr);
327 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
330 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
331 static int ixgbe_get_regs(struct rte_eth_dev *dev,
332 struct rte_dev_reg_info *regs);
333 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
334 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
335 struct rte_dev_eeprom_info *eeprom);
336 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
337 struct rte_dev_eeprom_info *eeprom);
339 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
340 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
341 struct rte_dev_reg_info *regs);
343 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
344 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
345 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
346 struct timespec *timestamp,
348 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp);
350 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
351 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
352 struct timespec *timestamp);
353 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
354 const struct timespec *timestamp);
356 static int ixgbe_dev_l2_tunnel_eth_type_conf
357 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
358 static int ixgbe_dev_l2_tunnel_offload_set
359 (struct rte_eth_dev *dev,
360 struct rte_eth_l2_tunnel_conf *l2_tunnel,
363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
364 enum rte_filter_op filter_op,
367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
368 struct rte_eth_udp_tunnel *udp_tunnel);
369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
370 struct rte_eth_udp_tunnel *udp_tunnel);
373 * Define VF Stats MACRO for Non "cleared on read" register
375 #define UPDATE_VF_STAT(reg, last, cur) \
377 uint32_t latest = IXGBE_READ_REG(hw, reg); \
378 cur += (latest - last) & UINT_MAX; \
382 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
384 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
385 u64 new_msb = IXGBE_READ_REG(hw, msb); \
386 u64 latest = ((new_msb << 32) | new_lsb); \
387 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
391 #define IXGBE_SET_HWSTRIP(h, q) do{\
392 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
393 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
394 (h)->bitmap[idx] |= 1 << bit;\
397 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
398 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
399 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
400 (h)->bitmap[idx] &= ~(1 << bit);\
403 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
404 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
405 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
406 (r) = (h)->bitmap[idx] >> bit & 1;\
410 * The set of PCI devices this driver supports
412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
414 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
415 #include "rte_pci_dev_ids.h"
417 { .vendor_id = 0, /* sentinel */ },
422 * The set of PCI devices this driver supports (for 82599 VF)
424 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
426 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
427 #include "rte_pci_dev_ids.h"
428 { .vendor_id = 0, /* sentinel */ },
432 static const struct rte_eth_desc_lim rx_desc_lim = {
433 .nb_max = IXGBE_MAX_RING_DESC,
434 .nb_min = IXGBE_MIN_RING_DESC,
435 .nb_align = IXGBE_RXD_ALIGN,
438 static const struct rte_eth_desc_lim tx_desc_lim = {
439 .nb_max = IXGBE_MAX_RING_DESC,
440 .nb_min = IXGBE_MIN_RING_DESC,
441 .nb_align = IXGBE_TXD_ALIGN,
444 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
445 .dev_configure = ixgbe_dev_configure,
446 .dev_start = ixgbe_dev_start,
447 .dev_stop = ixgbe_dev_stop,
448 .dev_set_link_up = ixgbe_dev_set_link_up,
449 .dev_set_link_down = ixgbe_dev_set_link_down,
450 .dev_close = ixgbe_dev_close,
451 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
452 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
453 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
454 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
455 .link_update = ixgbe_dev_link_update,
456 .stats_get = ixgbe_dev_stats_get,
457 .xstats_get = ixgbe_dev_xstats_get,
458 .stats_reset = ixgbe_dev_stats_reset,
459 .xstats_reset = ixgbe_dev_xstats_reset,
460 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
461 .dev_infos_get = ixgbe_dev_info_get,
462 .mtu_set = ixgbe_dev_mtu_set,
463 .vlan_filter_set = ixgbe_vlan_filter_set,
464 .vlan_tpid_set = ixgbe_vlan_tpid_set,
465 .vlan_offload_set = ixgbe_vlan_offload_set,
466 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
467 .rx_queue_start = ixgbe_dev_rx_queue_start,
468 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
469 .tx_queue_start = ixgbe_dev_tx_queue_start,
470 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
471 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
472 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
474 .rx_queue_release = ixgbe_dev_rx_queue_release,
475 .rx_queue_count = ixgbe_dev_rx_queue_count,
476 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
477 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
478 .tx_queue_release = ixgbe_dev_tx_queue_release,
479 .dev_led_on = ixgbe_dev_led_on,
480 .dev_led_off = ixgbe_dev_led_off,
481 .flow_ctrl_get = ixgbe_flow_ctrl_get,
482 .flow_ctrl_set = ixgbe_flow_ctrl_set,
483 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
484 .mac_addr_add = ixgbe_add_rar,
485 .mac_addr_remove = ixgbe_remove_rar,
486 .mac_addr_set = ixgbe_set_default_mac_addr,
487 .uc_hash_table_set = ixgbe_uc_hash_table_set,
488 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
489 .mirror_rule_set = ixgbe_mirror_rule_set,
490 .mirror_rule_reset = ixgbe_mirror_rule_reset,
491 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
492 .set_vf_rx = ixgbe_set_pool_rx,
493 .set_vf_tx = ixgbe_set_pool_tx,
494 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
495 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
496 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
497 .reta_update = ixgbe_dev_rss_reta_update,
498 .reta_query = ixgbe_dev_rss_reta_query,
499 #ifdef RTE_NIC_BYPASS
500 .bypass_init = ixgbe_bypass_init,
501 .bypass_state_set = ixgbe_bypass_state_store,
502 .bypass_state_show = ixgbe_bypass_state_show,
503 .bypass_event_set = ixgbe_bypass_event_store,
504 .bypass_event_show = ixgbe_bypass_event_show,
505 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
506 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
507 .bypass_ver_show = ixgbe_bypass_ver_show,
508 .bypass_wd_reset = ixgbe_bypass_wd_reset,
509 #endif /* RTE_NIC_BYPASS */
510 .rss_hash_update = ixgbe_dev_rss_hash_update,
511 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
512 .filter_ctrl = ixgbe_dev_filter_ctrl,
513 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
514 .rxq_info_get = ixgbe_rxq_info_get,
515 .txq_info_get = ixgbe_txq_info_get,
516 .timesync_enable = ixgbe_timesync_enable,
517 .timesync_disable = ixgbe_timesync_disable,
518 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
519 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
520 .get_reg_length = ixgbe_get_reg_length,
521 .get_reg = ixgbe_get_regs,
522 .get_eeprom_length = ixgbe_get_eeprom_length,
523 .get_eeprom = ixgbe_get_eeprom,
524 .set_eeprom = ixgbe_set_eeprom,
525 .get_dcb_info = ixgbe_dev_get_dcb_info,
526 .timesync_adjust_time = ixgbe_timesync_adjust_time,
527 .timesync_read_time = ixgbe_timesync_read_time,
528 .timesync_write_time = ixgbe_timesync_write_time,
529 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
530 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
531 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
532 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
536 * dev_ops for virtual function, bare necessities for basic vf
537 * operation have been implemented
539 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
540 .dev_configure = ixgbevf_dev_configure,
541 .dev_start = ixgbevf_dev_start,
542 .dev_stop = ixgbevf_dev_stop,
543 .link_update = ixgbe_dev_link_update,
544 .stats_get = ixgbevf_dev_stats_get,
545 .xstats_get = ixgbevf_dev_xstats_get,
546 .stats_reset = ixgbevf_dev_stats_reset,
547 .xstats_reset = ixgbevf_dev_stats_reset,
548 .dev_close = ixgbevf_dev_close,
549 .dev_infos_get = ixgbevf_dev_info_get,
550 .mtu_set = ixgbevf_dev_set_mtu,
551 .vlan_filter_set = ixgbevf_vlan_filter_set,
552 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
553 .vlan_offload_set = ixgbevf_vlan_offload_set,
554 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
555 .rx_queue_release = ixgbe_dev_rx_queue_release,
556 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
557 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
558 .tx_queue_release = ixgbe_dev_tx_queue_release,
559 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
560 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
561 .mac_addr_add = ixgbevf_add_mac_addr,
562 .mac_addr_remove = ixgbevf_remove_mac_addr,
563 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
564 .rxq_info_get = ixgbe_rxq_info_get,
565 .txq_info_get = ixgbe_txq_info_get,
566 .mac_addr_set = ixgbevf_set_default_mac_addr,
567 .get_reg_length = ixgbevf_get_reg_length,
568 .get_reg = ixgbevf_get_regs,
569 .reta_update = ixgbe_dev_rss_reta_update,
570 .reta_query = ixgbe_dev_rss_reta_query,
571 .rss_hash_update = ixgbe_dev_rss_hash_update,
572 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
575 /* store statistics names and its offset in stats structure */
576 struct rte_ixgbe_xstats_name_off {
577 char name[RTE_ETH_XSTATS_NAME_SIZE];
581 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
582 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
583 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
584 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
585 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
586 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
587 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
588 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
589 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
590 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
591 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
592 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
593 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
594 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
595 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
596 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
598 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
600 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
601 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
602 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
603 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
604 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
605 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
606 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
607 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
608 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
609 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
610 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
611 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
612 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
613 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
614 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
615 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
616 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
618 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
620 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
621 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
622 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
623 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
625 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
627 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
629 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
631 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
633 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
635 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
638 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
639 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
640 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
642 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
643 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
644 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
645 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
646 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
648 {"rx_fcoe_no_direct_data_placement_ext_buff",
649 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
651 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
653 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
655 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
657 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
659 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
662 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
663 sizeof(rte_ixgbe_stats_strings[0]))
665 /* Per-queue statistics */
666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
667 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
668 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
669 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
670 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
673 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
674 sizeof(rte_ixgbe_rxq_strings[0]))
676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
677 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
678 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
679 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
683 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
684 sizeof(rte_ixgbe_txq_strings[0]))
686 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
687 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
690 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
691 sizeof(rte_ixgbevf_stats_strings[0]))
694 * Atomically reads the link status information from global
695 * structure rte_eth_dev.
698 * - Pointer to the structure rte_eth_dev to read from.
699 * - Pointer to the buffer to be saved with the link status.
702 * - On success, zero.
703 * - On failure, negative value.
706 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
707 struct rte_eth_link *link)
709 struct rte_eth_link *dst = link;
710 struct rte_eth_link *src = &(dev->data->dev_link);
712 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
713 *(uint64_t *)src) == 0)
720 * Atomically writes the link status information into global
721 * structure rte_eth_dev.
724 * - Pointer to the structure rte_eth_dev to read from.
725 * - Pointer to the buffer to be saved with the link status.
728 * - On success, zero.
729 * - On failure, negative value.
732 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
733 struct rte_eth_link *link)
735 struct rte_eth_link *dst = &(dev->data->dev_link);
736 struct rte_eth_link *src = link;
738 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
739 *(uint64_t *)src) == 0)
746 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
749 ixgbe_is_sfp(struct ixgbe_hw *hw)
751 switch (hw->phy.type) {
752 case ixgbe_phy_sfp_avago:
753 case ixgbe_phy_sfp_ftl:
754 case ixgbe_phy_sfp_intel:
755 case ixgbe_phy_sfp_unknown:
756 case ixgbe_phy_sfp_passive_tyco:
757 case ixgbe_phy_sfp_passive_unknown:
764 static inline int32_t
765 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
770 status = ixgbe_reset_hw(hw);
772 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
773 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
774 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
775 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
776 IXGBE_WRITE_FLUSH(hw);
782 ixgbe_enable_intr(struct rte_eth_dev *dev)
784 struct ixgbe_interrupt *intr =
785 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
786 struct ixgbe_hw *hw =
787 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
789 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
790 IXGBE_WRITE_FLUSH(hw);
794 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
797 ixgbe_disable_intr(struct ixgbe_hw *hw)
799 PMD_INIT_FUNC_TRACE();
801 if (hw->mac.type == ixgbe_mac_82598EB) {
802 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
804 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
805 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
806 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
808 IXGBE_WRITE_FLUSH(hw);
812 * This function resets queue statistics mapping registers.
813 * From Niantic datasheet, Initialization of Statistics section:
814 * "...if software requires the queue counters, the RQSMR and TQSM registers
815 * must be re-programmed following a device reset.
818 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
822 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
823 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
824 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
830 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
835 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
836 #define NB_QMAP_FIELDS_PER_QSM_REG 4
837 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
839 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
840 struct ixgbe_stat_mapping_registers *stat_mappings =
841 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
842 uint32_t qsmr_mask = 0;
843 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
847 if ((hw->mac.type != ixgbe_mac_82599EB) &&
848 (hw->mac.type != ixgbe_mac_X540) &&
849 (hw->mac.type != ixgbe_mac_X550) &&
850 (hw->mac.type != ixgbe_mac_X550EM_x))
853 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
854 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
857 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
858 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
859 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
862 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
864 /* Now clear any previous stat_idx set */
865 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
867 stat_mappings->tqsm[n] &= ~clearing_mask;
869 stat_mappings->rqsmr[n] &= ~clearing_mask;
871 q_map = (uint32_t)stat_idx;
872 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
873 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
875 stat_mappings->tqsm[n] |= qsmr_mask;
877 stat_mappings->rqsmr[n] |= qsmr_mask;
879 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
880 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
882 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
883 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
885 /* Now write the mapping in the appropriate register */
887 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
888 stat_mappings->rqsmr[n], n);
889 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
892 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
893 stat_mappings->tqsm[n], n);
894 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
900 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
902 struct ixgbe_stat_mapping_registers *stat_mappings =
903 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
904 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
907 /* write whatever was in stat mapping table to the NIC */
908 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
910 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
913 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
918 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
921 struct ixgbe_dcb_tc_config *tc;
922 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
924 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
925 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
926 for (i = 0; i < dcb_max_tc; i++) {
927 tc = &dcb_config->tc_config[i];
928 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
929 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
930 (uint8_t)(100/dcb_max_tc + (i & 1));
931 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
932 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
933 (uint8_t)(100/dcb_max_tc + (i & 1));
934 tc->pfc = ixgbe_dcb_pfc_disabled;
937 /* Initialize default user to priority mapping, UPx->TC0 */
938 tc = &dcb_config->tc_config[0];
939 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
940 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
941 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
942 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
943 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
945 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
946 dcb_config->pfc_mode_enable = false;
947 dcb_config->vt_mode = true;
948 dcb_config->round_robin_enable = false;
949 /* support all DCB capabilities in 82599 */
950 dcb_config->support.capabilities = 0xFF;
952 /*we only support 4 Tcs for X540, X550 */
953 if (hw->mac.type == ixgbe_mac_X540 ||
954 hw->mac.type == ixgbe_mac_X550 ||
955 hw->mac.type == ixgbe_mac_X550EM_x) {
956 dcb_config->num_tcs.pg_tcs = 4;
957 dcb_config->num_tcs.pfc_tcs = 4;
962 * Ensure that all locks are released before first NVM or PHY access
965 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
970 * Phy lock should not fail in this early stage. If this is the case,
971 * it is due to an improper exit of the application.
972 * So force the release of the faulty lock. Release of common lock
973 * is done automatically by swfw_sync function.
975 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
976 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
977 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
979 ixgbe_release_swfw_semaphore(hw, mask);
982 * These ones are more tricky since they are common to all ports; but
983 * swfw_sync retries last long enough (1s) to be almost sure that if
984 * lock can not be taken it is due to an improper lock of the
987 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
988 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
989 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
991 ixgbe_release_swfw_semaphore(hw, mask);
995 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
996 * It returns 0 on success.
999 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1001 struct rte_pci_device *pci_dev;
1002 struct ixgbe_hw *hw =
1003 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1004 struct ixgbe_vfta * shadow_vfta =
1005 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1006 struct ixgbe_hwstrip *hwstrip =
1007 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1008 struct ixgbe_dcb_config *dcb_config =
1009 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1010 struct ixgbe_filter_info *filter_info =
1011 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1016 PMD_INIT_FUNC_TRACE();
1018 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1019 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1020 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1023 * For secondary processes, we don't initialise any further as primary
1024 * has already done this work. Only check we don't need a different
1025 * RX and TX function.
1027 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1028 struct ixgbe_tx_queue *txq;
1029 /* TX queue function in primary, set by last queue initialized
1030 * Tx queue may not initialized by primary process */
1031 if (eth_dev->data->tx_queues) {
1032 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1033 ixgbe_set_tx_function(eth_dev, txq);
1035 /* Use default TX function if we get here */
1036 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1037 "Using default TX function.");
1040 ixgbe_set_rx_function(eth_dev);
1044 pci_dev = eth_dev->pci_dev;
1046 rte_eth_copy_pci_info(eth_dev, pci_dev);
1048 /* Vendor and Device ID need to be set before init of shared code */
1049 hw->device_id = pci_dev->id.device_id;
1050 hw->vendor_id = pci_dev->id.vendor_id;
1051 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1052 hw->allow_unsupported_sfp = 1;
1054 /* Initialize the shared code (base driver) */
1055 #ifdef RTE_NIC_BYPASS
1056 diag = ixgbe_bypass_init_shared_code(hw);
1058 diag = ixgbe_init_shared_code(hw);
1059 #endif /* RTE_NIC_BYPASS */
1061 if (diag != IXGBE_SUCCESS) {
1062 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1066 /* pick up the PCI bus settings for reporting later */
1067 ixgbe_get_bus_info(hw);
1069 /* Unlock any pending hardware semaphore */
1070 ixgbe_swfw_lock_reset(hw);
1072 /* Initialize DCB configuration*/
1073 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1074 ixgbe_dcb_init(hw,dcb_config);
1075 /* Get Hardware Flow Control setting */
1076 hw->fc.requested_mode = ixgbe_fc_full;
1077 hw->fc.current_mode = ixgbe_fc_full;
1078 hw->fc.pause_time = IXGBE_FC_PAUSE;
1079 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1080 hw->fc.low_water[i] = IXGBE_FC_LO;
1081 hw->fc.high_water[i] = IXGBE_FC_HI;
1083 hw->fc.send_xon = 1;
1085 /* Make sure we have a good EEPROM before we read from it */
1086 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1087 if (diag != IXGBE_SUCCESS) {
1088 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1092 #ifdef RTE_NIC_BYPASS
1093 diag = ixgbe_bypass_init_hw(hw);
1095 diag = ixgbe_init_hw(hw);
1096 #endif /* RTE_NIC_BYPASS */
1099 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1100 * is called too soon after the kernel driver unbinding/binding occurs.
1101 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1102 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1103 * also called. See ixgbe_identify_phy_82599(). The reason for the
1104 * failure is not known, and only occuts when virtualisation features
1105 * are disabled in the bios. A delay of 100ms was found to be enough by
1106 * trial-and-error, and is doubled to be safe.
1108 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1110 diag = ixgbe_init_hw(hw);
1113 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1114 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1115 "LOM. Please be aware there may be issues associated "
1116 "with your hardware.");
1117 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1118 "please contact your Intel or hardware representative "
1119 "who provided you with this hardware.");
1120 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1121 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1123 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1127 /* Reset the hw statistics */
1128 ixgbe_dev_stats_reset(eth_dev);
1130 /* disable interrupt */
1131 ixgbe_disable_intr(hw);
1133 /* reset mappings for queue statistics hw counters*/
1134 ixgbe_reset_qstat_mappings(hw);
1136 /* Allocate memory for storing MAC addresses */
1137 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1138 hw->mac.num_rar_entries, 0);
1139 if (eth_dev->data->mac_addrs == NULL) {
1141 "Failed to allocate %u bytes needed to store "
1143 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1146 /* Copy the permanent MAC address */
1147 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1148 ð_dev->data->mac_addrs[0]);
1150 /* Allocate memory for storing hash filter MAC addresses */
1151 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1152 IXGBE_VMDQ_NUM_UC_MAC, 0);
1153 if (eth_dev->data->hash_mac_addrs == NULL) {
1155 "Failed to allocate %d bytes needed to store MAC addresses",
1156 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1160 /* initialize the vfta */
1161 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1163 /* initialize the hw strip bitmap*/
1164 memset(hwstrip, 0, sizeof(*hwstrip));
1166 /* initialize PF if max_vfs not zero */
1167 ixgbe_pf_host_init(eth_dev);
1169 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1170 /* let hardware know driver is loaded */
1171 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1172 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1173 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1174 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1175 IXGBE_WRITE_FLUSH(hw);
1177 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1178 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1179 (int) hw->mac.type, (int) hw->phy.type,
1180 (int) hw->phy.sfp_type);
1182 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1183 (int) hw->mac.type, (int) hw->phy.type);
1185 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1186 eth_dev->data->port_id, pci_dev->id.vendor_id,
1187 pci_dev->id.device_id);
1189 rte_intr_callback_register(&pci_dev->intr_handle,
1190 ixgbe_dev_interrupt_handler,
1193 /* enable uio/vfio intr/eventfd mapping */
1194 rte_intr_enable(&pci_dev->intr_handle);
1196 /* enable support intr */
1197 ixgbe_enable_intr(eth_dev);
1199 /* initialize 5tuple filter list */
1200 TAILQ_INIT(&filter_info->fivetuple_list);
1201 memset(filter_info->fivetuple_mask, 0,
1202 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1208 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1210 struct rte_pci_device *pci_dev;
1211 struct ixgbe_hw *hw;
1213 PMD_INIT_FUNC_TRACE();
1215 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1218 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1219 pci_dev = eth_dev->pci_dev;
1221 if (hw->adapter_stopped == 0)
1222 ixgbe_dev_close(eth_dev);
1224 eth_dev->dev_ops = NULL;
1225 eth_dev->rx_pkt_burst = NULL;
1226 eth_dev->tx_pkt_burst = NULL;
1228 /* Unlock any pending hardware semaphore */
1229 ixgbe_swfw_lock_reset(hw);
1231 /* disable uio intr before callback unregister */
1232 rte_intr_disable(&(pci_dev->intr_handle));
1233 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1234 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1236 /* uninitialize PF if max_vfs not zero */
1237 ixgbe_pf_host_uninit(eth_dev);
1239 rte_free(eth_dev->data->mac_addrs);
1240 eth_dev->data->mac_addrs = NULL;
1242 rte_free(eth_dev->data->hash_mac_addrs);
1243 eth_dev->data->hash_mac_addrs = NULL;
1249 * Negotiate mailbox API version with the PF.
1250 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1251 * Then we try to negotiate starting with the most recent one.
1252 * If all negotiation attempts fail, then we will proceed with
1253 * the default one (ixgbe_mbox_api_10).
1256 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1260 /* start with highest supported, proceed down */
1261 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1267 i != RTE_DIM(sup_ver) &&
1268 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1274 generate_random_mac_addr(struct ether_addr *mac_addr)
1278 /* Set Organizationally Unique Identifier (OUI) prefix. */
1279 mac_addr->addr_bytes[0] = 0x00;
1280 mac_addr->addr_bytes[1] = 0x09;
1281 mac_addr->addr_bytes[2] = 0xC0;
1282 /* Force indication of locally assigned MAC address. */
1283 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1284 /* Generate the last 3 bytes of the MAC address with a random number. */
1285 random = rte_rand();
1286 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1290 * Virtual Function device init
1293 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1297 struct rte_pci_device *pci_dev;
1298 struct ixgbe_hw *hw =
1299 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1300 struct ixgbe_vfta * shadow_vfta =
1301 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1302 struct ixgbe_hwstrip *hwstrip =
1303 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1304 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1306 PMD_INIT_FUNC_TRACE();
1308 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1309 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1310 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1312 /* for secondary processes, we don't initialise any further as primary
1313 * has already done this work. Only check we don't need a different
1315 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1316 if (eth_dev->data->scattered_rx)
1317 eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1321 pci_dev = eth_dev->pci_dev;
1323 rte_eth_copy_pci_info(eth_dev, pci_dev);
1325 hw->device_id = pci_dev->id.device_id;
1326 hw->vendor_id = pci_dev->id.vendor_id;
1327 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1329 /* initialize the vfta */
1330 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1332 /* initialize the hw strip bitmap*/
1333 memset(hwstrip, 0, sizeof(*hwstrip));
1335 /* Initialize the shared code (base driver) */
1336 diag = ixgbe_init_shared_code(hw);
1337 if (diag != IXGBE_SUCCESS) {
1338 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1342 /* init_mailbox_params */
1343 hw->mbx.ops.init_params(hw);
1345 /* Reset the hw statistics */
1346 ixgbevf_dev_stats_reset(eth_dev);
1348 /* Disable the interrupts for VF */
1349 ixgbevf_intr_disable(hw);
1351 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1352 diag = hw->mac.ops.reset_hw(hw);
1355 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1356 * the underlying PF driver has not assigned a MAC address to the VF.
1357 * In this case, assign a random MAC address.
1359 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1360 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1364 /* negotiate mailbox API version to use with the PF. */
1365 ixgbevf_negotiate_api(hw);
1367 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1368 ixgbevf_get_queues(hw, &tcs, &tc);
1370 /* Allocate memory for storing MAC addresses */
1371 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1372 hw->mac.num_rar_entries, 0);
1373 if (eth_dev->data->mac_addrs == NULL) {
1375 "Failed to allocate %u bytes needed to store "
1377 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1381 /* Generate a random MAC address, if none was assigned by PF. */
1382 if (is_zero_ether_addr(perm_addr)) {
1383 generate_random_mac_addr(perm_addr);
1384 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1386 rte_free(eth_dev->data->mac_addrs);
1387 eth_dev->data->mac_addrs = NULL;
1390 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1391 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1392 "%02x:%02x:%02x:%02x:%02x:%02x",
1393 perm_addr->addr_bytes[0],
1394 perm_addr->addr_bytes[1],
1395 perm_addr->addr_bytes[2],
1396 perm_addr->addr_bytes[3],
1397 perm_addr->addr_bytes[4],
1398 perm_addr->addr_bytes[5]);
1401 /* Copy the permanent MAC address */
1402 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1404 /* reset the hardware with the new settings */
1405 diag = hw->mac.ops.start_hw(hw);
1411 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1415 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1416 eth_dev->data->port_id, pci_dev->id.vendor_id,
1417 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1422 /* Virtual Function device uninit */
1425 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1427 struct ixgbe_hw *hw;
1430 PMD_INIT_FUNC_TRACE();
1432 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1435 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1437 if (hw->adapter_stopped == 0)
1438 ixgbevf_dev_close(eth_dev);
1440 eth_dev->dev_ops = NULL;
1441 eth_dev->rx_pkt_burst = NULL;
1442 eth_dev->tx_pkt_burst = NULL;
1444 /* Disable the interrupts for VF */
1445 ixgbevf_intr_disable(hw);
1447 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1448 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1449 eth_dev->data->rx_queues[i] = NULL;
1451 eth_dev->data->nb_rx_queues = 0;
1453 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1454 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1455 eth_dev->data->tx_queues[i] = NULL;
1457 eth_dev->data->nb_tx_queues = 0;
1459 rte_free(eth_dev->data->mac_addrs);
1460 eth_dev->data->mac_addrs = NULL;
1465 static struct eth_driver rte_ixgbe_pmd = {
1467 .name = "rte_ixgbe_pmd",
1468 .id_table = pci_id_ixgbe_map,
1469 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1470 RTE_PCI_DRV_DETACHABLE,
1472 .eth_dev_init = eth_ixgbe_dev_init,
1473 .eth_dev_uninit = eth_ixgbe_dev_uninit,
1474 .dev_private_size = sizeof(struct ixgbe_adapter),
1478 * virtual function driver struct
1480 static struct eth_driver rte_ixgbevf_pmd = {
1482 .name = "rte_ixgbevf_pmd",
1483 .id_table = pci_id_ixgbevf_map,
1484 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1486 .eth_dev_init = eth_ixgbevf_dev_init,
1487 .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1488 .dev_private_size = sizeof(struct ixgbe_adapter),
1492 * Driver initialization routine.
1493 * Invoked once at EAL init time.
1494 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1497 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1499 PMD_INIT_FUNC_TRACE();
1501 rte_eth_driver_register(&rte_ixgbe_pmd);
1506 * VF Driver initialization routine.
1507 * Invoked one at EAL init time.
1508 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1511 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1513 PMD_INIT_FUNC_TRACE();
1515 rte_eth_driver_register(&rte_ixgbevf_pmd);
1520 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1522 struct ixgbe_hw *hw =
1523 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524 struct ixgbe_vfta * shadow_vfta =
1525 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1530 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1531 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1532 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1537 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1539 /* update local VFTA copy */
1540 shadow_vfta->vfta[vid_idx] = vfta;
1546 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1549 ixgbe_vlan_hw_strip_enable(dev, queue);
1551 ixgbe_vlan_hw_strip_disable(dev, queue);
1555 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1556 enum rte_vlan_type vlan_type,
1559 struct ixgbe_hw *hw =
1560 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1563 switch (vlan_type) {
1564 case ETH_VLAN_TYPE_INNER:
1565 /* Only the high 16-bits is valid */
1566 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1570 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1578 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1580 struct ixgbe_hw *hw =
1581 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584 PMD_INIT_FUNC_TRACE();
1586 /* Filter Table Disable */
1587 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1588 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1590 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1594 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1596 struct ixgbe_hw *hw =
1597 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1598 struct ixgbe_vfta * shadow_vfta =
1599 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1603 PMD_INIT_FUNC_TRACE();
1605 /* Filter Table Enable */
1606 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1607 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1608 vlnctrl |= IXGBE_VLNCTRL_VFE;
1610 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1612 /* write whatever is in local vfta copy */
1613 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1614 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1618 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1620 struct ixgbe_hwstrip *hwstrip =
1621 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1623 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1627 IXGBE_SET_HWSTRIP(hwstrip, queue);
1629 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1633 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1635 struct ixgbe_hw *hw =
1636 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639 PMD_INIT_FUNC_TRACE();
1641 if (hw->mac.type == ixgbe_mac_82598EB) {
1642 /* No queue level support */
1643 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1647 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1648 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1649 ctrl &= ~IXGBE_RXDCTL_VME;
1650 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1652 /* record those setting for HW strip per queue */
1653 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1657 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1659 struct ixgbe_hw *hw =
1660 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663 PMD_INIT_FUNC_TRACE();
1665 if (hw->mac.type == ixgbe_mac_82598EB) {
1666 /* No queue level supported */
1667 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1671 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1672 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1673 ctrl |= IXGBE_RXDCTL_VME;
1674 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1676 /* record those setting for HW strip per queue */
1677 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1681 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1683 struct ixgbe_hw *hw =
1684 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1688 PMD_INIT_FUNC_TRACE();
1690 if (hw->mac.type == ixgbe_mac_82598EB) {
1691 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1692 ctrl &= ~IXGBE_VLNCTRL_VME;
1693 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1696 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1697 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1698 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1699 ctrl &= ~IXGBE_RXDCTL_VME;
1700 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1702 /* record those setting for HW strip per queue */
1703 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1709 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1711 struct ixgbe_hw *hw =
1712 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716 PMD_INIT_FUNC_TRACE();
1718 if (hw->mac.type == ixgbe_mac_82598EB) {
1719 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1720 ctrl |= IXGBE_VLNCTRL_VME;
1721 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1724 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1725 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1726 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1727 ctrl |= IXGBE_RXDCTL_VME;
1728 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1730 /* record those setting for HW strip per queue */
1731 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1737 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1739 struct ixgbe_hw *hw =
1740 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743 PMD_INIT_FUNC_TRACE();
1745 /* DMATXCTRL: Geric Double VLAN Disable */
1746 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1747 ctrl &= ~IXGBE_DMATXCTL_GDV;
1748 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1750 /* CTRL_EXT: Global Double VLAN Disable */
1751 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1752 ctrl &= ~IXGBE_EXTENDED_VLAN;
1753 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1758 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1760 struct ixgbe_hw *hw =
1761 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764 PMD_INIT_FUNC_TRACE();
1766 /* DMATXCTRL: Geric Double VLAN Enable */
1767 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1768 ctrl |= IXGBE_DMATXCTL_GDV;
1769 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1771 /* CTRL_EXT: Global Double VLAN Enable */
1772 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1773 ctrl |= IXGBE_EXTENDED_VLAN;
1774 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1776 /* Clear pooling mode of PFVTCTL. It's required by X550. */
1777 if (hw->mac.type == ixgbe_mac_X550 ||
1778 hw->mac.type == ixgbe_mac_X550EM_x) {
1779 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1780 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1781 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1785 * VET EXT field in the EXVET register = 0x8100 by default
1786 * So no need to change. Same to VT field of DMATXCTL register
1791 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1793 if(mask & ETH_VLAN_STRIP_MASK){
1794 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1795 ixgbe_vlan_hw_strip_enable_all(dev);
1797 ixgbe_vlan_hw_strip_disable_all(dev);
1800 if(mask & ETH_VLAN_FILTER_MASK){
1801 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1802 ixgbe_vlan_hw_filter_enable(dev);
1804 ixgbe_vlan_hw_filter_disable(dev);
1807 if(mask & ETH_VLAN_EXTEND_MASK){
1808 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1809 ixgbe_vlan_hw_extend_enable(dev);
1811 ixgbe_vlan_hw_extend_disable(dev);
1816 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1818 struct ixgbe_hw *hw =
1819 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1820 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1821 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1822 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1823 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1827 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1832 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1835 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1841 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1842 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1848 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1850 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1851 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1852 uint16_t nb_tx_q = dev->data->nb_rx_queues;
1854 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1855 /* check multi-queue mode */
1856 switch (dev_conf->rxmode.mq_mode) {
1857 case ETH_MQ_RX_VMDQ_DCB:
1858 case ETH_MQ_RX_VMDQ_DCB_RSS:
1859 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1860 PMD_INIT_LOG(ERR, "SRIOV active,"
1861 " unsupported mq_mode rx %d.",
1862 dev_conf->rxmode.mq_mode);
1865 case ETH_MQ_RX_VMDQ_RSS:
1866 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1867 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1868 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1869 PMD_INIT_LOG(ERR, "SRIOV is active,"
1870 " invalid queue number"
1871 " for VMDQ RSS, allowed"
1872 " value are 1, 2 or 4.");
1876 case ETH_MQ_RX_VMDQ_ONLY:
1877 case ETH_MQ_RX_NONE:
1878 /* if nothing mq mode configure, use default scheme */
1879 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1880 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1881 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1883 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1884 /* SRIOV only works in VMDq enable mode */
1885 PMD_INIT_LOG(ERR, "SRIOV is active,"
1886 " wrong mq_mode rx %d.",
1887 dev_conf->rxmode.mq_mode);
1891 switch (dev_conf->txmode.mq_mode) {
1892 case ETH_MQ_TX_VMDQ_DCB:
1893 /* DCB VMDQ in SRIOV mode, not implement yet */
1894 PMD_INIT_LOG(ERR, "SRIOV is active,"
1895 " unsupported VMDQ mq_mode tx %d.",
1896 dev_conf->txmode.mq_mode);
1898 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1899 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1903 /* check valid queue number */
1904 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1905 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1906 PMD_INIT_LOG(ERR, "SRIOV is active,"
1907 " queue number must less equal to %d.",
1908 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1912 /* check configuration for vmdb+dcb mode */
1913 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1914 const struct rte_eth_vmdq_dcb_conf *conf;
1916 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1917 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1918 IXGBE_VMDQ_DCB_NB_QUEUES);
1921 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1922 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1923 conf->nb_queue_pools == ETH_32_POOLS)) {
1924 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1925 " nb_queue_pools must be %d or %d.",
1926 ETH_16_POOLS, ETH_32_POOLS);
1930 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1931 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1933 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1934 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1935 IXGBE_VMDQ_DCB_NB_QUEUES);
1938 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1939 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1940 conf->nb_queue_pools == ETH_32_POOLS)) {
1941 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1942 " nb_queue_pools != %d and"
1943 " nb_queue_pools != %d.",
1944 ETH_16_POOLS, ETH_32_POOLS);
1949 /* For DCB mode check our configuration before we go further */
1950 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1951 const struct rte_eth_dcb_rx_conf *conf;
1953 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1954 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1955 IXGBE_DCB_NB_QUEUES);
1958 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1959 if (!(conf->nb_tcs == ETH_4_TCS ||
1960 conf->nb_tcs == ETH_8_TCS)) {
1961 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1962 " and nb_tcs != %d.",
1963 ETH_4_TCS, ETH_8_TCS);
1968 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1969 const struct rte_eth_dcb_tx_conf *conf;
1971 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1972 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1973 IXGBE_DCB_NB_QUEUES);
1976 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1977 if (!(conf->nb_tcs == ETH_4_TCS ||
1978 conf->nb_tcs == ETH_8_TCS)) {
1979 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1980 " and nb_tcs != %d.",
1981 ETH_4_TCS, ETH_8_TCS);
1990 ixgbe_dev_configure(struct rte_eth_dev *dev)
1992 struct ixgbe_interrupt *intr =
1993 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1994 struct ixgbe_adapter *adapter =
1995 (struct ixgbe_adapter *)dev->data->dev_private;
1998 PMD_INIT_FUNC_TRACE();
1999 /* multipe queue mode checking */
2000 ret = ixgbe_check_mq_mode(dev);
2002 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2007 /* set flag to update link status after init */
2008 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2011 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2012 * allocation or vector Rx preconditions we will reset it.
2014 adapter->rx_bulk_alloc_allowed = true;
2015 adapter->rx_vec_allowed = true;
2021 * Configure device link speed and setup link.
2022 * It returns 0 on success.
2025 ixgbe_dev_start(struct rte_eth_dev *dev)
2027 struct ixgbe_hw *hw =
2028 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029 struct ixgbe_vf_info *vfinfo =
2030 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2031 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2032 uint32_t intr_vector = 0;
2033 int err, link_up = 0, negotiate = 0;
2039 PMD_INIT_FUNC_TRACE();
2041 /* IXGBE devices don't support half duplex */
2042 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2043 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2044 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2045 dev->data->dev_conf.link_duplex,
2046 dev->data->port_id);
2050 /* disable uio/vfio intr/eventfd mapping */
2051 rte_intr_disable(intr_handle);
2054 hw->adapter_stopped = 0;
2055 ixgbe_stop_adapter(hw);
2057 /* reinitialize adapter
2058 * this calls reset and start */
2059 status = ixgbe_pf_reset_hw(hw);
2062 hw->mac.ops.start_hw(hw);
2063 hw->mac.get_link_status = true;
2065 /* configure PF module if SRIOV enabled */
2066 ixgbe_pf_host_configure(dev);
2068 /* check and configure queue intr-vector mapping */
2069 if ((rte_intr_cap_multiple(intr_handle) ||
2070 !RTE_ETH_DEV_SRIOV(dev).active) &&
2071 dev->data->dev_conf.intr_conf.rxq != 0) {
2072 intr_vector = dev->data->nb_rx_queues;
2073 if (rte_intr_efd_enable(intr_handle, intr_vector))
2077 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2078 intr_handle->intr_vec =
2079 rte_zmalloc("intr_vec",
2080 dev->data->nb_rx_queues * sizeof(int), 0);
2081 if (intr_handle->intr_vec == NULL) {
2082 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2083 " intr_vec\n", dev->data->nb_rx_queues);
2088 /* confiugre msix for sleep until rx interrupt */
2089 ixgbe_configure_msix(dev);
2091 /* initialize transmission unit */
2092 ixgbe_dev_tx_init(dev);
2094 /* This can fail when allocating mbufs for descriptor rings */
2095 err = ixgbe_dev_rx_init(dev);
2097 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2101 err = ixgbe_dev_rxtx_start(dev);
2103 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2107 /* Skip link setup if loopback mode is enabled for 82599. */
2108 if (hw->mac.type == ixgbe_mac_82599EB &&
2109 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2110 goto skip_link_setup;
2112 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2113 err = hw->mac.ops.setup_sfp(hw);
2118 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2119 /* Turn on the copper */
2120 ixgbe_set_phy_power(hw, true);
2122 /* Turn on the laser */
2123 ixgbe_enable_tx_laser(hw);
2126 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2129 dev->data->dev_link.link_status = link_up;
2131 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2135 switch(dev->data->dev_conf.link_speed) {
2136 case ETH_LINK_SPEED_AUTONEG:
2137 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2138 IXGBE_LINK_SPEED_82599_AUTONEG :
2139 IXGBE_LINK_SPEED_82598_AUTONEG;
2141 case ETH_LINK_SPEED_100:
2143 * Invalid for 82598 but error will be detected by
2144 * ixgbe_setup_link()
2146 speed = IXGBE_LINK_SPEED_100_FULL;
2148 case ETH_LINK_SPEED_1000:
2149 speed = IXGBE_LINK_SPEED_1GB_FULL;
2151 case ETH_LINK_SPEED_10000:
2152 speed = IXGBE_LINK_SPEED_10GB_FULL;
2155 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2156 dev->data->dev_conf.link_speed,
2157 dev->data->port_id);
2161 err = ixgbe_setup_link(hw, speed, link_up);
2167 if (rte_intr_allow_others(intr_handle)) {
2168 /* check if lsc interrupt is enabled */
2169 if (dev->data->dev_conf.intr_conf.lsc != 0)
2170 ixgbe_dev_lsc_interrupt_setup(dev);
2172 rte_intr_callback_unregister(intr_handle,
2173 ixgbe_dev_interrupt_handler,
2175 if (dev->data->dev_conf.intr_conf.lsc != 0)
2176 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2177 " no intr multiplex\n");
2180 /* check if rxq interrupt is enabled */
2181 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2182 rte_intr_dp_is_en(intr_handle))
2183 ixgbe_dev_rxq_interrupt_setup(dev);
2185 /* enable uio/vfio intr/eventfd mapping */
2186 rte_intr_enable(intr_handle);
2188 /* resume enabled intr since hw reset */
2189 ixgbe_enable_intr(dev);
2191 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2192 ETH_VLAN_EXTEND_MASK;
2193 ixgbe_vlan_offload_set(dev, mask);
2195 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2196 /* Enable vlan filtering for VMDq */
2197 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2200 /* Configure DCB hw */
2201 ixgbe_configure_dcb(dev);
2203 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2204 err = ixgbe_fdir_configure(dev);
2209 /* Restore vf rate limit */
2210 if (vfinfo != NULL) {
2211 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2212 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2213 if (vfinfo[vf].tx_rate[idx] != 0)
2214 ixgbe_set_vf_rate_limit(dev, vf,
2215 vfinfo[vf].tx_rate[idx],
2219 ixgbe_restore_statistics_mapping(dev);
2224 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2225 ixgbe_dev_clear_queues(dev);
2230 * Stop device: disable rx and tx functions to allow for reconfiguring.
2233 ixgbe_dev_stop(struct rte_eth_dev *dev)
2235 struct rte_eth_link link;
2236 struct ixgbe_hw *hw =
2237 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238 struct ixgbe_vf_info *vfinfo =
2239 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2240 struct ixgbe_filter_info *filter_info =
2241 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2242 struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2243 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2246 PMD_INIT_FUNC_TRACE();
2248 /* disable interrupts */
2249 ixgbe_disable_intr(hw);
2251 /* disable intr eventfd mapping */
2252 rte_intr_disable(intr_handle);
2255 ixgbe_pf_reset_hw(hw);
2256 hw->adapter_stopped = 0;
2259 ixgbe_stop_adapter(hw);
2261 for (vf = 0; vfinfo != NULL &&
2262 vf < dev->pci_dev->max_vfs; vf++)
2263 vfinfo[vf].clear_to_send = false;
2265 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2266 /* Turn off the copper */
2267 ixgbe_set_phy_power(hw, false);
2269 /* Turn off the laser */
2270 ixgbe_disable_tx_laser(hw);
2273 ixgbe_dev_clear_queues(dev);
2275 /* Clear stored conf */
2276 dev->data->scattered_rx = 0;
2279 /* Clear recorded link status */
2280 memset(&link, 0, sizeof(link));
2281 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2283 /* Remove all ntuple filters of the device */
2284 for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2285 p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2286 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2287 TAILQ_REMOVE(&filter_info->fivetuple_list,
2291 memset(filter_info->fivetuple_mask, 0,
2292 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2294 if (!rte_intr_allow_others(intr_handle))
2295 /* resume to the default handler */
2296 rte_intr_callback_register(intr_handle,
2297 ixgbe_dev_interrupt_handler,
2300 /* Clean datapath event and queue/vec mapping */
2301 rte_intr_efd_disable(intr_handle);
2302 if (intr_handle->intr_vec != NULL) {
2303 rte_free(intr_handle->intr_vec);
2304 intr_handle->intr_vec = NULL;
2309 * Set device link up: enable tx.
2312 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2314 struct ixgbe_hw *hw =
2315 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316 if (hw->mac.type == ixgbe_mac_82599EB) {
2317 #ifdef RTE_NIC_BYPASS
2318 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2319 /* Not suported in bypass mode */
2320 PMD_INIT_LOG(ERR, "Set link up is not supported "
2321 "by device id 0x%x", hw->device_id);
2327 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2328 /* Turn on the copper */
2329 ixgbe_set_phy_power(hw, true);
2331 /* Turn on the laser */
2332 ixgbe_enable_tx_laser(hw);
2339 * Set device link down: disable tx.
2342 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2344 struct ixgbe_hw *hw =
2345 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2346 if (hw->mac.type == ixgbe_mac_82599EB) {
2347 #ifdef RTE_NIC_BYPASS
2348 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2349 /* Not suported in bypass mode */
2350 PMD_INIT_LOG(ERR, "Set link down is not supported "
2351 "by device id 0x%x", hw->device_id);
2357 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2358 /* Turn off the copper */
2359 ixgbe_set_phy_power(hw, false);
2361 /* Turn off the laser */
2362 ixgbe_disable_tx_laser(hw);
2369 * Reest and stop device.
2372 ixgbe_dev_close(struct rte_eth_dev *dev)
2374 struct ixgbe_hw *hw =
2375 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2377 PMD_INIT_FUNC_TRACE();
2379 ixgbe_pf_reset_hw(hw);
2381 ixgbe_dev_stop(dev);
2382 hw->adapter_stopped = 1;
2384 ixgbe_dev_free_queues(dev);
2386 ixgbe_disable_pcie_master(hw);
2388 /* reprogram the RAR[0] in case user changed it. */
2389 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2393 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2394 struct ixgbe_hw_stats *hw_stats,
2395 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2396 uint64_t *total_qprc, uint64_t *total_qprdc)
2398 uint32_t bprc, lxon, lxoff, total;
2399 uint32_t delta_gprc = 0;
2401 /* Workaround for RX byte count not including CRC bytes when CRC
2402 + * strip is enabled. CRC bytes are removed from counters when crc_strip
2405 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2406 IXGBE_HLREG0_RXCRCSTRP);
2408 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2409 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2410 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2411 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2413 for (i = 0; i < 8; i++) {
2415 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2416 /* global total per queue */
2417 hw_stats->mpc[i] += mp;
2418 /* Running comprehensive total for stats display */
2419 *total_missed_rx += hw_stats->mpc[i];
2420 if (hw->mac.type == ixgbe_mac_82598EB) {
2421 hw_stats->rnbc[i] +=
2422 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2423 hw_stats->pxonrxc[i] +=
2424 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2425 hw_stats->pxoffrxc[i] +=
2426 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2428 hw_stats->pxonrxc[i] +=
2429 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2430 hw_stats->pxoffrxc[i] +=
2431 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2432 hw_stats->pxon2offc[i] +=
2433 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2435 hw_stats->pxontxc[i] +=
2436 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2437 hw_stats->pxofftxc[i] +=
2438 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2440 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2441 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2442 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2443 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2445 delta_gprc += delta_qprc;
2447 hw_stats->qprc[i] += delta_qprc;
2448 hw_stats->qptc[i] += delta_qptc;
2450 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2451 hw_stats->qbrc[i] +=
2452 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2454 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2456 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2457 hw_stats->qbtc[i] +=
2458 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2460 hw_stats->qprdc[i] += delta_qprdc;
2461 *total_qprdc += hw_stats->qprdc[i];
2463 *total_qprc += hw_stats->qprc[i];
2464 *total_qbrc += hw_stats->qbrc[i];
2466 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2467 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2468 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2471 * An errata states that gprc actually counts good + missed packets:
2472 * Workaround to set gprc to summated queue packet receives
2474 hw_stats->gprc = *total_qprc;
2476 if (hw->mac.type != ixgbe_mac_82598EB) {
2477 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2478 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2479 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2480 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2481 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2482 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2483 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2484 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2486 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2487 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2488 /* 82598 only has a counter in the high register */
2489 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2490 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2491 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2493 uint64_t old_tpr = hw_stats->tpr;
2495 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2496 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2499 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2501 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2502 hw_stats->gptc += delta_gptc;
2503 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2504 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2507 * Workaround: mprc hardware is incorrectly counting
2508 * broadcasts, so for now we subtract those.
2510 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2511 hw_stats->bprc += bprc;
2512 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2513 if (hw->mac.type == ixgbe_mac_82598EB)
2514 hw_stats->mprc -= bprc;
2516 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2517 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2518 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2519 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2520 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2521 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2523 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2524 hw_stats->lxontxc += lxon;
2525 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2526 hw_stats->lxofftxc += lxoff;
2527 total = lxon + lxoff;
2529 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2530 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2531 hw_stats->gptc -= total;
2532 hw_stats->mptc -= total;
2533 hw_stats->ptc64 -= total;
2534 hw_stats->gotc -= total * ETHER_MIN_LEN;
2536 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2537 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2538 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2539 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2540 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2541 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2542 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2543 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2544 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2545 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2546 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2547 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2548 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2549 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2550 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2551 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2552 /* Only read FCOE on 82599 */
2553 if (hw->mac.type != ixgbe_mac_82598EB) {
2554 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2555 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2556 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2557 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2558 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2561 /* Flow Director Stats registers */
2562 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2563 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2567 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2570 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2572 struct ixgbe_hw *hw =
2573 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2574 struct ixgbe_hw_stats *hw_stats =
2575 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2576 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2579 total_missed_rx = 0;
2584 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2585 &total_qprc, &total_qprdc);
2590 /* Fill out the rte_eth_stats statistics structure */
2591 stats->ipackets = total_qprc;
2592 stats->ibytes = total_qbrc;
2593 stats->opackets = hw_stats->gptc;
2594 stats->obytes = hw_stats->gotc;
2596 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2597 stats->q_ipackets[i] = hw_stats->qprc[i];
2598 stats->q_opackets[i] = hw_stats->qptc[i];
2599 stats->q_ibytes[i] = hw_stats->qbrc[i];
2600 stats->q_obytes[i] = hw_stats->qbtc[i];
2601 stats->q_errors[i] = hw_stats->qprdc[i];
2605 stats->imissed = total_missed_rx;
2606 stats->ierrors = hw_stats->crcerrs +
2623 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2625 struct ixgbe_hw_stats *stats =
2626 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2628 /* HW registers are cleared on read */
2629 ixgbe_dev_stats_get(dev, NULL);
2631 /* Reset software totals */
2632 memset(stats, 0, sizeof(*stats));
2635 /* This function calculates the number of xstats based on the current config */
2637 ixgbe_xstats_calc_num(void) {
2638 return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2639 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2643 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2646 struct ixgbe_hw *hw =
2647 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2648 struct ixgbe_hw_stats *hw_stats =
2649 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2650 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2651 unsigned i, stat, count = 0;
2653 count = ixgbe_xstats_calc_num();
2658 total_missed_rx = 0;
2663 ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2664 &total_qprc, &total_qprdc);
2666 /* If this is a reset xstats is NULL, and we have cleared the
2667 * registers by reading them.
2672 /* Extended stats from ixgbe_hw_stats */
2674 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2675 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2676 rte_ixgbe_stats_strings[i].name);
2677 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2678 rte_ixgbe_stats_strings[i].offset);
2682 /* RX Priority Stats */
2683 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2684 for (i = 0; i < 8; i++) {
2685 snprintf(xstats[count].name, sizeof(xstats[count].name),
2686 "rx_priority%u_%s", i,
2687 rte_ixgbe_rxq_strings[stat].name);
2688 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2689 rte_ixgbe_rxq_strings[stat].offset +
2690 (sizeof(uint64_t) * i));
2695 /* TX Priority Stats */
2696 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2697 for (i = 0; i < 8; i++) {
2698 snprintf(xstats[count].name, sizeof(xstats[count].name),
2699 "tx_priority%u_%s", i,
2700 rte_ixgbe_txq_strings[stat].name);
2701 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2702 rte_ixgbe_txq_strings[stat].offset +
2703 (sizeof(uint64_t) * i));
2712 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2714 struct ixgbe_hw_stats *stats =
2715 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2717 unsigned count = ixgbe_xstats_calc_num();
2719 /* HW registers are cleared on read */
2720 ixgbe_dev_xstats_get(dev, NULL, count);
2722 /* Reset software totals */
2723 memset(stats, 0, sizeof(*stats));
2727 ixgbevf_update_stats(struct rte_eth_dev *dev)
2729 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2731 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2733 /* Good Rx packet, include VF loopback */
2734 UPDATE_VF_STAT(IXGBE_VFGPRC,
2735 hw_stats->last_vfgprc, hw_stats->vfgprc);
2737 /* Good Rx octets, include VF loopback */
2738 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2739 hw_stats->last_vfgorc, hw_stats->vfgorc);
2741 /* Good Tx packet, include VF loopback */
2742 UPDATE_VF_STAT(IXGBE_VFGPTC,
2743 hw_stats->last_vfgptc, hw_stats->vfgptc);
2745 /* Good Tx octets, include VF loopback */
2746 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2747 hw_stats->last_vfgotc, hw_stats->vfgotc);
2749 /* Rx Multicst Packet */
2750 UPDATE_VF_STAT(IXGBE_VFMPRC,
2751 hw_stats->last_vfmprc, hw_stats->vfmprc);
2755 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2758 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2759 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2762 if (n < IXGBEVF_NB_XSTATS)
2763 return IXGBEVF_NB_XSTATS;
2765 ixgbevf_update_stats(dev);
2770 /* Extended stats */
2771 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2772 snprintf(xstats[i].name, sizeof(xstats[i].name),
2773 "%s", rte_ixgbevf_stats_strings[i].name);
2774 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2775 rte_ixgbevf_stats_strings[i].offset);
2778 return IXGBEVF_NB_XSTATS;
2782 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2784 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2785 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2787 ixgbevf_update_stats(dev);
2792 stats->ipackets = hw_stats->vfgprc;
2793 stats->ibytes = hw_stats->vfgorc;
2794 stats->opackets = hw_stats->vfgptc;
2795 stats->obytes = hw_stats->vfgotc;
2796 stats->imcasts = hw_stats->vfmprc;
2797 /* stats->imcasts should be removed as imcasts is deprecated */
2801 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2803 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2804 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2806 /* Sync HW register to the last stats */
2807 ixgbevf_dev_stats_get(dev, NULL);
2809 /* reset HW current stats*/
2810 hw_stats->vfgprc = 0;
2811 hw_stats->vfgorc = 0;
2812 hw_stats->vfgptc = 0;
2813 hw_stats->vfgotc = 0;
2814 hw_stats->vfmprc = 0;
2819 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2821 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2823 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2824 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2825 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2826 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2827 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2828 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2829 dev_info->max_vfs = dev->pci_dev->max_vfs;
2830 if (hw->mac.type == ixgbe_mac_82598EB)
2831 dev_info->max_vmdq_pools = ETH_16_POOLS;
2833 dev_info->max_vmdq_pools = ETH_64_POOLS;
2834 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2835 dev_info->rx_offload_capa =
2836 DEV_RX_OFFLOAD_VLAN_STRIP |
2837 DEV_RX_OFFLOAD_IPV4_CKSUM |
2838 DEV_RX_OFFLOAD_UDP_CKSUM |
2839 DEV_RX_OFFLOAD_TCP_CKSUM;
2842 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2845 if ((hw->mac.type == ixgbe_mac_82599EB ||
2846 hw->mac.type == ixgbe_mac_X540) &&
2847 !RTE_ETH_DEV_SRIOV(dev).active)
2848 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2850 dev_info->tx_offload_capa =
2851 DEV_TX_OFFLOAD_VLAN_INSERT |
2852 DEV_TX_OFFLOAD_IPV4_CKSUM |
2853 DEV_TX_OFFLOAD_UDP_CKSUM |
2854 DEV_TX_OFFLOAD_TCP_CKSUM |
2855 DEV_TX_OFFLOAD_SCTP_CKSUM |
2856 DEV_TX_OFFLOAD_TCP_TSO;
2858 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2860 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2861 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2862 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2864 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2868 dev_info->default_txconf = (struct rte_eth_txconf) {
2870 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2871 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2872 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2874 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2875 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2876 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2877 ETH_TXQ_FLAGS_NOOFFLOADS,
2880 dev_info->rx_desc_lim = rx_desc_lim;
2881 dev_info->tx_desc_lim = tx_desc_lim;
2883 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2884 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2885 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2889 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2890 struct rte_eth_dev_info *dev_info)
2892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2895 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2896 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2897 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2898 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2899 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2900 dev_info->max_vfs = dev->pci_dev->max_vfs;
2901 if (hw->mac.type == ixgbe_mac_82598EB)
2902 dev_info->max_vmdq_pools = ETH_16_POOLS;
2904 dev_info->max_vmdq_pools = ETH_64_POOLS;
2905 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2906 DEV_RX_OFFLOAD_IPV4_CKSUM |
2907 DEV_RX_OFFLOAD_UDP_CKSUM |
2908 DEV_RX_OFFLOAD_TCP_CKSUM;
2909 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2910 DEV_TX_OFFLOAD_IPV4_CKSUM |
2911 DEV_TX_OFFLOAD_UDP_CKSUM |
2912 DEV_TX_OFFLOAD_TCP_CKSUM |
2913 DEV_TX_OFFLOAD_SCTP_CKSUM |
2914 DEV_TX_OFFLOAD_TCP_TSO;
2916 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2918 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2919 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2920 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2922 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2926 dev_info->default_txconf = (struct rte_eth_txconf) {
2928 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2929 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2930 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2932 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2933 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2934 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2935 ETH_TXQ_FLAGS_NOOFFLOADS,
2938 dev_info->rx_desc_lim = rx_desc_lim;
2939 dev_info->tx_desc_lim = tx_desc_lim;
2942 /* return 0 means link status changed, -1 means not changed */
2944 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2946 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2947 struct rte_eth_link link, old;
2948 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2952 link.link_status = 0;
2953 link.link_speed = 0;
2954 link.link_duplex = 0;
2955 memset(&old, 0, sizeof(old));
2956 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2958 hw->mac.get_link_status = true;
2960 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2961 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2962 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2964 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2967 link.link_speed = ETH_LINK_SPEED_100;
2968 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2969 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2970 if (link.link_status == old.link_status)
2976 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2977 if (link.link_status == old.link_status)
2981 link.link_status = 1;
2982 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2984 switch (link_speed) {
2986 case IXGBE_LINK_SPEED_UNKNOWN:
2987 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2988 link.link_speed = ETH_LINK_SPEED_100;
2991 case IXGBE_LINK_SPEED_100_FULL:
2992 link.link_speed = ETH_LINK_SPEED_100;
2995 case IXGBE_LINK_SPEED_1GB_FULL:
2996 link.link_speed = ETH_LINK_SPEED_1000;
2999 case IXGBE_LINK_SPEED_10GB_FULL:
3000 link.link_speed = ETH_LINK_SPEED_10000;
3003 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3005 if (link.link_status == old.link_status)
3012 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3014 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3017 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3018 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3019 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3023 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3025 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3029 fctrl &= (~IXGBE_FCTRL_UPE);
3030 if (dev->data->all_multicast == 1)
3031 fctrl |= IXGBE_FCTRL_MPE;
3033 fctrl &= (~IXGBE_FCTRL_MPE);
3034 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3038 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3040 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3044 fctrl |= IXGBE_FCTRL_MPE;
3045 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3049 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3051 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3054 if (dev->data->promiscuous == 1)
3055 return; /* must remain in all_multicast mode */
3057 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3058 fctrl &= (~IXGBE_FCTRL_MPE);
3059 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3063 * It clears the interrupt causes and enables the interrupt.
3064 * It will be called once only during nic initialized.
3067 * Pointer to struct rte_eth_dev.
3070 * - On success, zero.
3071 * - On failure, a negative value.
3074 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3076 struct ixgbe_interrupt *intr =
3077 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3079 ixgbe_dev_link_status_print(dev);
3080 intr->mask |= IXGBE_EICR_LSC;
3086 * It clears the interrupt causes and enables the interrupt.
3087 * It will be called once only during nic initialized.
3090 * Pointer to struct rte_eth_dev.
3093 * - On success, zero.
3094 * - On failure, a negative value.
3097 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3099 struct ixgbe_interrupt *intr =
3100 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3102 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3108 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3111 * Pointer to struct rte_eth_dev.
3114 * - On success, zero.
3115 * - On failure, a negative value.
3118 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3122 struct ixgbe_interrupt *intr =
3123 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3125 /* clear all cause mask */
3126 ixgbe_disable_intr(hw);
3128 /* read-on-clear nic registers here */
3129 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3130 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3134 /* set flag for async link update */
3135 if (eicr & IXGBE_EICR_LSC)
3136 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3138 if (eicr & IXGBE_EICR_MAILBOX)
3139 intr->flags |= IXGBE_FLAG_MAILBOX;
3145 * It gets and then prints the link status.
3148 * Pointer to struct rte_eth_dev.
3151 * - On success, zero.
3152 * - On failure, a negative value.
3155 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3157 struct rte_eth_link link;
3159 memset(&link, 0, sizeof(link));
3160 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3161 if (link.link_status) {
3162 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3163 (int)(dev->data->port_id),
3164 (unsigned)link.link_speed,
3165 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3166 "full-duplex" : "half-duplex");
3168 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3169 (int)(dev->data->port_id));
3171 PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3172 dev->pci_dev->addr.domain,
3173 dev->pci_dev->addr.bus,
3174 dev->pci_dev->addr.devid,
3175 dev->pci_dev->addr.function);
3179 * It executes link_update after knowing an interrupt occurred.
3182 * Pointer to struct rte_eth_dev.
3185 * - On success, zero.
3186 * - On failure, a negative value.
3189 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3191 struct ixgbe_interrupt *intr =
3192 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3194 struct rte_eth_link link;
3195 int intr_enable_delay = false;
3197 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3199 if (intr->flags & IXGBE_FLAG_MAILBOX) {
3200 ixgbe_pf_mbx_process(dev);
3201 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3204 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3205 /* get the link status before link update, for predicting later */
3206 memset(&link, 0, sizeof(link));
3207 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3209 ixgbe_dev_link_update(dev, 0);
3212 if (!link.link_status)
3213 /* handle it 1 sec later, wait it being stable */
3214 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3215 /* likely to down */
3217 /* handle it 4 sec later, wait it being stable */
3218 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3220 ixgbe_dev_link_status_print(dev);
3222 intr_enable_delay = true;
3225 if (intr_enable_delay) {
3226 if (rte_eal_alarm_set(timeout * 1000,
3227 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3228 PMD_DRV_LOG(ERR, "Error setting alarm");
3230 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3231 ixgbe_enable_intr(dev);
3232 rte_intr_enable(&(dev->pci_dev->intr_handle));
3240 * Interrupt handler which shall be registered for alarm callback for delayed
3241 * handling specific interrupt to wait for the stable nic state. As the
3242 * NIC interrupt state is not stable for ixgbe after link is just down,
3243 * it needs to wait 4 seconds to get the stable status.
3246 * Pointer to interrupt handle.
3248 * The address of parameter (struct rte_eth_dev *) regsitered before.
3254 ixgbe_dev_interrupt_delayed_handler(void *param)
3256 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3257 struct ixgbe_interrupt *intr =
3258 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3259 struct ixgbe_hw *hw =
3260 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3263 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3264 if (eicr & IXGBE_EICR_MAILBOX)
3265 ixgbe_pf_mbx_process(dev);
3267 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3268 ixgbe_dev_link_update(dev, 0);
3269 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3270 ixgbe_dev_link_status_print(dev);
3271 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3274 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3275 ixgbe_enable_intr(dev);
3276 rte_intr_enable(&(dev->pci_dev->intr_handle));
3280 * Interrupt handler triggered by NIC for handling
3281 * specific interrupt.
3284 * Pointer to interrupt handle.
3286 * The address of parameter (struct rte_eth_dev *) regsitered before.
3292 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3295 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3297 ixgbe_dev_interrupt_get_status(dev);
3298 ixgbe_dev_interrupt_action(dev);
3302 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3304 struct ixgbe_hw *hw;
3306 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3311 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3313 struct ixgbe_hw *hw;
3315 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3320 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3322 struct ixgbe_hw *hw;
3328 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3330 fc_conf->pause_time = hw->fc.pause_time;
3331 fc_conf->high_water = hw->fc.high_water[0];
3332 fc_conf->low_water = hw->fc.low_water[0];
3333 fc_conf->send_xon = hw->fc.send_xon;
3334 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3337 * Return rx_pause status according to actual setting of
3340 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3341 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3347 * Return tx_pause status according to actual setting of
3350 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3351 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3356 if (rx_pause && tx_pause)
3357 fc_conf->mode = RTE_FC_FULL;
3359 fc_conf->mode = RTE_FC_RX_PAUSE;
3361 fc_conf->mode = RTE_FC_TX_PAUSE;
3363 fc_conf->mode = RTE_FC_NONE;
3369 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3371 struct ixgbe_hw *hw;
3373 uint32_t rx_buf_size;
3374 uint32_t max_high_water;
3376 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3383 PMD_INIT_FUNC_TRACE();
3385 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3386 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3387 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3390 * At least reserve one Ethernet frame for watermark
3391 * high_water/low_water in kilo bytes for ixgbe
3393 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3394 if ((fc_conf->high_water > max_high_water) ||
3395 (fc_conf->high_water < fc_conf->low_water)) {
3396 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3397 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3401 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3402 hw->fc.pause_time = fc_conf->pause_time;
3403 hw->fc.high_water[0] = fc_conf->high_water;
3404 hw->fc.low_water[0] = fc_conf->low_water;
3405 hw->fc.send_xon = fc_conf->send_xon;
3406 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3408 err = ixgbe_fc_enable(hw);
3410 /* Not negotiated is not an error case */
3411 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3413 /* check if we want to forward MAC frames - driver doesn't have native
3414 * capability to do that, so we'll write the registers ourselves */
3416 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3418 /* set or clear MFLCN.PMCF bit depending on configuration */
3419 if (fc_conf->mac_ctrl_frame_fwd != 0)
3420 mflcn |= IXGBE_MFLCN_PMCF;
3422 mflcn &= ~IXGBE_MFLCN_PMCF;
3424 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3425 IXGBE_WRITE_FLUSH(hw);
3430 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3435 * ixgbe_pfc_enable_generic - Enable flow control
3436 * @hw: pointer to hardware structure
3437 * @tc_num: traffic class number
3438 * Enable flow control according to the current settings.
3441 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3444 uint32_t mflcn_reg, fccfg_reg;
3446 uint32_t fcrtl, fcrth;
3450 /* Validate the water mark configuration */
3451 if (!hw->fc.pause_time) {
3452 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3456 /* Low water mark of zero causes XOFF floods */
3457 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3458 /* High/Low water can not be 0 */
3459 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3460 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3461 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3465 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3466 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3467 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3471 /* Negotiate the fc mode to use */
3472 ixgbe_fc_autoneg(hw);
3474 /* Disable any previous flow control settings */
3475 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3476 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3478 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3479 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3481 switch (hw->fc.current_mode) {
3484 * If the count of enabled RX Priority Flow control >1,
3485 * and the TX pause can not be disabled
3488 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3489 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3490 if (reg & IXGBE_FCRTH_FCEN)
3494 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3496 case ixgbe_fc_rx_pause:
3498 * Rx Flow control is enabled and Tx Flow control is
3499 * disabled by software override. Since there really
3500 * isn't a way to advertise that we are capable of RX
3501 * Pause ONLY, we will advertise that we support both
3502 * symmetric and asymmetric Rx PAUSE. Later, we will
3503 * disable the adapter's ability to send PAUSE frames.
3505 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3507 * If the count of enabled RX Priority Flow control >1,
3508 * and the TX pause can not be disabled
3511 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3512 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3513 if (reg & IXGBE_FCRTH_FCEN)
3517 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3519 case ixgbe_fc_tx_pause:
3521 * Tx Flow control is enabled, and Rx Flow control is
3522 * disabled by software override.
3524 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3527 /* Flow control (both Rx and Tx) is enabled by SW override. */
3528 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3529 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3532 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3533 ret_val = IXGBE_ERR_CONFIG;
3538 /* Set 802.3x based flow control settings. */
3539 mflcn_reg |= IXGBE_MFLCN_DPF;
3540 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3541 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3543 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3544 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3545 hw->fc.high_water[tc_num]) {
3546 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3547 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3548 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3550 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3552 * In order to prevent Tx hangs when the internal Tx
3553 * switch is enabled we must set the high water mark
3554 * to the maximum FCRTH value. This allows the Tx
3555 * switch to function even under heavy Rx workloads.
3557 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3559 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3561 /* Configure pause time (2 TCs per register) */
3562 reg = hw->fc.pause_time * 0x00010001;
3563 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3564 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3566 /* Configure flow control refresh threshold value */
3567 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3574 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3576 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3577 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3579 if(hw->mac.type != ixgbe_mac_82598EB) {
3580 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3586 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3589 uint32_t rx_buf_size;
3590 uint32_t max_high_water;
3592 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3593 struct ixgbe_hw *hw =
3594 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595 struct ixgbe_dcb_config *dcb_config =
3596 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3598 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3605 PMD_INIT_FUNC_TRACE();
3607 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3608 tc_num = map[pfc_conf->priority];
3609 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3610 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3612 * At least reserve one Ethernet frame for watermark
3613 * high_water/low_water in kilo bytes for ixgbe
3615 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3616 if ((pfc_conf->fc.high_water > max_high_water) ||
3617 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3618 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3619 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3623 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3624 hw->fc.pause_time = pfc_conf->fc.pause_time;
3625 hw->fc.send_xon = pfc_conf->fc.send_xon;
3626 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3627 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3629 err = ixgbe_dcb_pfc_enable(dev,tc_num);
3631 /* Not negotiated is not an error case */
3632 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3635 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3640 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3641 struct rte_eth_rss_reta_entry64 *reta_conf,
3646 uint16_t idx, shift;
3647 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3648 uint16_t sp_reta_size;
3651 PMD_INIT_FUNC_TRACE();
3653 if (!ixgbe_rss_update_sp(hw->mac.type)) {
3654 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3659 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3660 if (reta_size != sp_reta_size) {
3661 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3662 "(%d) doesn't match the number hardware can supported "
3663 "(%d)\n", reta_size, sp_reta_size);
3667 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3668 idx = i / RTE_RETA_GROUP_SIZE;
3669 shift = i % RTE_RETA_GROUP_SIZE;
3670 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3674 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3675 if (mask == IXGBE_4_BIT_MASK)
3678 r = IXGBE_READ_REG(hw, reta_reg);
3679 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3680 if (mask & (0x1 << j))
3681 reta |= reta_conf[idx].reta[shift + j] <<
3684 reta |= r & (IXGBE_8_BIT_MASK <<
3687 IXGBE_WRITE_REG(hw, reta_reg, reta);
3694 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3695 struct rte_eth_rss_reta_entry64 *reta_conf,
3700 uint16_t idx, shift;
3701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702 uint16_t sp_reta_size;
3705 PMD_INIT_FUNC_TRACE();
3706 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3707 if (reta_size != sp_reta_size) {
3708 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3709 "(%d) doesn't match the number hardware can supported "
3710 "(%d)\n", reta_size, sp_reta_size);
3714 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3715 idx = i / RTE_RETA_GROUP_SIZE;
3716 shift = i % RTE_RETA_GROUP_SIZE;
3717 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3722 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3723 reta = IXGBE_READ_REG(hw, reta_reg);
3724 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3725 if (mask & (0x1 << j))
3726 reta_conf[idx].reta[shift + j] =
3727 ((reta >> (CHAR_BIT * j)) &
3736 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3737 uint32_t index, uint32_t pool)
3739 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740 uint32_t enable_addr = 1;
3742 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3746 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3748 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3750 ixgbe_clear_rar(hw, index);
3754 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3756 ixgbe_remove_rar(dev, 0);
3758 ixgbe_add_rar(dev, addr, 0, 0);
3762 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3766 struct ixgbe_hw *hw;
3767 struct rte_eth_dev_info dev_info;
3768 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3770 ixgbe_dev_info_get(dev, &dev_info);
3772 /* check that mtu is within the allowed range */
3773 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3776 /* refuse mtu that requires the support of scattered packets when this
3777 * feature has not been enabled before. */
3778 if (!dev->data->scattered_rx &&
3779 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3780 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3783 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3784 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3786 /* switch to jumbo mode if needed */
3787 if (frame_size > ETHER_MAX_LEN) {
3788 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3789 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3791 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3792 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3794 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3796 /* update max frame size */
3797 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3799 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3800 maxfrs &= 0x0000FFFF;
3801 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3802 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3808 * Virtual Function operations
3811 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3813 PMD_INIT_FUNC_TRACE();
3815 /* Clear interrupt mask to stop from interrupts being generated */
3816 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3818 IXGBE_WRITE_FLUSH(hw);
3822 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3824 PMD_INIT_FUNC_TRACE();
3826 /* VF enable interrupt autoclean */
3827 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3828 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3829 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3831 IXGBE_WRITE_FLUSH(hw);
3835 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3837 struct rte_eth_conf* conf = &dev->data->dev_conf;
3838 struct ixgbe_adapter *adapter =
3839 (struct ixgbe_adapter *)dev->data->dev_private;
3841 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3842 dev->data->port_id);
3845 * VF has no ability to enable/disable HW CRC
3846 * Keep the persistent behavior the same as Host PF
3848 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3849 if (!conf->rxmode.hw_strip_crc) {
3850 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3851 conf->rxmode.hw_strip_crc = 1;
3854 if (conf->rxmode.hw_strip_crc) {
3855 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3856 conf->rxmode.hw_strip_crc = 0;
3861 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3862 * allocation or vector Rx preconditions we will reset it.
3864 adapter->rx_bulk_alloc_allowed = true;
3865 adapter->rx_vec_allowed = true;
3871 ixgbevf_dev_start(struct rte_eth_dev *dev)
3873 struct ixgbe_hw *hw =
3874 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3875 uint32_t intr_vector = 0;
3876 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3880 PMD_INIT_FUNC_TRACE();
3882 hw->mac.ops.reset_hw(hw);
3883 hw->mac.get_link_status = true;
3885 /* negotiate mailbox API version to use with the PF. */
3886 ixgbevf_negotiate_api(hw);
3888 ixgbevf_dev_tx_init(dev);
3890 /* This can fail when allocating mbufs for descriptor rings */
3891 err = ixgbevf_dev_rx_init(dev);
3893 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3894 ixgbe_dev_clear_queues(dev);
3899 ixgbevf_set_vfta_all(dev,1);
3902 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3903 ETH_VLAN_EXTEND_MASK;
3904 ixgbevf_vlan_offload_set(dev, mask);
3906 ixgbevf_dev_rxtx_start(dev);
3908 /* check and configure queue intr-vector mapping */
3909 if (dev->data->dev_conf.intr_conf.rxq != 0) {
3910 intr_vector = dev->data->nb_rx_queues;
3911 if (rte_intr_efd_enable(intr_handle, intr_vector))
3915 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3916 intr_handle->intr_vec =
3917 rte_zmalloc("intr_vec",
3918 dev->data->nb_rx_queues * sizeof(int), 0);
3919 if (intr_handle->intr_vec == NULL) {
3920 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3921 " intr_vec\n", dev->data->nb_rx_queues);
3925 ixgbevf_configure_msix(dev);
3927 rte_intr_enable(intr_handle);
3929 /* Re-enable interrupt for VF */
3930 ixgbevf_intr_enable(hw);
3936 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3941 PMD_INIT_FUNC_TRACE();
3943 hw->adapter_stopped = 1;
3944 ixgbe_stop_adapter(hw);
3947 * Clear what we set, but we still keep shadow_vfta to
3948 * restore after device starts
3950 ixgbevf_set_vfta_all(dev,0);
3952 /* Clear stored conf */
3953 dev->data->scattered_rx = 0;
3955 ixgbe_dev_clear_queues(dev);
3957 /* disable intr eventfd mapping */
3958 rte_intr_disable(intr_handle);
3960 /* Clean datapath event and queue/vec mapping */
3961 rte_intr_efd_disable(intr_handle);
3962 if (intr_handle->intr_vec != NULL) {
3963 rte_free(intr_handle->intr_vec);
3964 intr_handle->intr_vec = NULL;
3969 ixgbevf_dev_close(struct rte_eth_dev *dev)
3971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973 PMD_INIT_FUNC_TRACE();
3977 ixgbevf_dev_stop(dev);
3979 ixgbe_dev_free_queues(dev);
3981 /* reprogram the RAR[0] in case user changed it. */
3982 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3985 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3987 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988 struct ixgbe_vfta * shadow_vfta =
3989 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3990 int i = 0, j = 0, vfta = 0, mask = 1;
3992 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3993 vfta = shadow_vfta->vfta[i];
3996 for (j = 0; j < 32; j++){
3998 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4007 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4009 struct ixgbe_hw *hw =
4010 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4011 struct ixgbe_vfta * shadow_vfta =
4012 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4013 uint32_t vid_idx = 0;
4014 uint32_t vid_bit = 0;
4017 PMD_INIT_FUNC_TRACE();
4019 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4020 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4022 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4025 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4026 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4028 /* Save what we set and retore it after device reset */
4030 shadow_vfta->vfta[vid_idx] |= vid_bit;
4032 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4038 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4040 struct ixgbe_hw *hw =
4041 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044 PMD_INIT_FUNC_TRACE();
4046 if(queue >= hw->mac.max_rx_queues)
4049 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4051 ctrl |= IXGBE_RXDCTL_VME;
4053 ctrl &= ~IXGBE_RXDCTL_VME;
4054 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4056 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4060 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4062 struct ixgbe_hw *hw =
4063 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067 /* VF function only support hw strip feature, others are not support */
4068 if(mask & ETH_VLAN_STRIP_MASK){
4069 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4071 for(i=0; i < hw->mac.max_rx_queues; i++)
4072 ixgbevf_vlan_strip_queue_set(dev,i,on);
4077 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4081 /* we only need to do this if VMDq is enabled */
4082 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4083 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4084 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4092 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4094 uint32_t vector = 0;
4095 switch (hw->mac.mc_filter_type) {
4096 case 0: /* use bits [47:36] of the address */
4097 vector = ((uc_addr->addr_bytes[4] >> 4) |
4098 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4100 case 1: /* use bits [46:35] of the address */
4101 vector = ((uc_addr->addr_bytes[4] >> 3) |
4102 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4104 case 2: /* use bits [45:34] of the address */
4105 vector = ((uc_addr->addr_bytes[4] >> 2) |
4106 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4108 case 3: /* use bits [43:32] of the address */
4109 vector = ((uc_addr->addr_bytes[4]) |
4110 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4112 default: /* Invalid mc_filter_type */
4116 /* vector can only be 12-bits or boundary will be exceeded */
4122 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4130 const uint32_t ixgbe_uta_idx_mask = 0x7F;
4131 const uint32_t ixgbe_uta_bit_shift = 5;
4132 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4133 const uint32_t bit1 = 0x1;
4135 struct ixgbe_hw *hw =
4136 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4137 struct ixgbe_uta_info *uta_info =
4138 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4140 /* The UTA table only exists on 82599 hardware and newer */
4141 if (hw->mac.type < ixgbe_mac_82599EB)
4144 vector = ixgbe_uta_vector(hw,mac_addr);
4145 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4146 uta_shift = vector & ixgbe_uta_bit_mask;
4148 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4152 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4154 uta_info->uta_in_use++;
4155 reg_val |= (bit1 << uta_shift);
4156 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4158 uta_info->uta_in_use--;
4159 reg_val &= ~(bit1 << uta_shift);
4160 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4163 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4165 if (uta_info->uta_in_use > 0)
4166 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4167 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4169 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4175 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4178 struct ixgbe_hw *hw =
4179 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4180 struct ixgbe_uta_info *uta_info =
4181 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4183 /* The UTA table only exists on 82599 hardware and newer */
4184 if (hw->mac.type < ixgbe_mac_82599EB)
4188 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4189 uta_info->uta_shadow[i] = ~0;
4190 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4193 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4194 uta_info->uta_shadow[i] = 0;
4195 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4203 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4205 uint32_t new_val = orig_val;
4207 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4208 new_val |= IXGBE_VMOLR_AUPE;
4209 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4210 new_val |= IXGBE_VMOLR_ROMPE;
4211 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4212 new_val |= IXGBE_VMOLR_ROPE;
4213 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4214 new_val |= IXGBE_VMOLR_BAM;
4215 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4216 new_val |= IXGBE_VMOLR_MPE;
4222 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4223 uint16_t rx_mask, uint8_t on)
4227 struct ixgbe_hw *hw =
4228 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4229 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4231 if (hw->mac.type == ixgbe_mac_82598EB) {
4232 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4233 " on 82599 hardware and newer");
4236 if (ixgbe_vmdq_mode_check(hw) < 0)
4239 val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4246 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4252 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4256 const uint8_t bit1 = 0x1;
4258 struct ixgbe_hw *hw =
4259 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4261 if (ixgbe_vmdq_mode_check(hw) < 0)
4264 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4265 reg = IXGBE_READ_REG(hw, addr);
4273 IXGBE_WRITE_REG(hw, addr,reg);
4279 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4283 const uint8_t bit1 = 0x1;
4285 struct ixgbe_hw *hw =
4286 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288 if (ixgbe_vmdq_mode_check(hw) < 0)
4291 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4292 reg = IXGBE_READ_REG(hw, addr);
4300 IXGBE_WRITE_REG(hw, addr,reg);
4306 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4307 uint64_t pool_mask, uint8_t vlan_on)
4311 struct ixgbe_hw *hw =
4312 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4314 if (ixgbe_vmdq_mode_check(hw) < 0)
4316 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4317 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4318 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4326 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
4327 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
4328 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
4329 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
4330 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4331 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4332 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4335 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4336 struct rte_eth_mirror_conf *mirror_conf,
4337 uint8_t rule_id, uint8_t on)
4339 uint32_t mr_ctl,vlvf;
4340 uint32_t mp_lsb = 0;
4341 uint32_t mv_msb = 0;
4342 uint32_t mv_lsb = 0;
4343 uint32_t mp_msb = 0;
4346 uint64_t vlan_mask = 0;
4348 const uint8_t pool_mask_offset = 32;
4349 const uint8_t vlan_mask_offset = 32;
4350 const uint8_t dst_pool_offset = 8;
4351 const uint8_t rule_mr_offset = 4;
4352 const uint8_t mirror_rule_mask= 0x0F;
4354 struct ixgbe_mirror_info *mr_info =
4355 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4356 struct ixgbe_hw *hw =
4357 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358 uint8_t mirror_type = 0;
4360 if (ixgbe_vmdq_mode_check(hw) < 0)
4363 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4366 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4367 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4368 mirror_conf->rule_type);
4372 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4373 mirror_type |= IXGBE_MRCTL_VLME;
4374 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4375 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4376 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4377 /* search vlan id related pool vlan filter index */
4378 reg_index = ixgbe_find_vlvf_slot(hw,
4379 mirror_conf->vlan.vlan_id[i]);
4382 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4383 if ((vlvf & IXGBE_VLVF_VIEN) &&
4384 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4385 mirror_conf->vlan.vlan_id[i]))
4386 vlan_mask |= (1ULL << reg_index);
4393 mv_lsb = vlan_mask & 0xFFFFFFFF;
4394 mv_msb = vlan_mask >> vlan_mask_offset;
4396 mr_info->mr_conf[rule_id].vlan.vlan_mask =
4397 mirror_conf->vlan.vlan_mask;
4398 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4399 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4400 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4401 mirror_conf->vlan.vlan_id[i];
4406 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4407 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4408 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4413 * if enable pool mirror, write related pool mask register,if disable
4414 * pool mirror, clear PFMRVM register
4416 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4417 mirror_type |= IXGBE_MRCTL_VPME;
4419 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4420 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4421 mr_info->mr_conf[rule_id].pool_mask =
4422 mirror_conf->pool_mask;
4427 mr_info->mr_conf[rule_id].pool_mask = 0;
4430 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4431 mirror_type |= IXGBE_MRCTL_UPME;
4432 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4433 mirror_type |= IXGBE_MRCTL_DPME;
4435 /* read mirror control register and recalculate it */
4436 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4439 mr_ctl |= mirror_type;
4440 mr_ctl &= mirror_rule_mask;
4441 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4443 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4445 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4446 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4448 /* write mirrror control register */
4449 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4451 /* write pool mirrror control register */
4452 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4453 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4454 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4457 /* write VLAN mirrror control register */
4458 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4459 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4460 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4468 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4471 uint32_t lsb_val = 0;
4472 uint32_t msb_val = 0;
4473 const uint8_t rule_mr_offset = 4;
4475 struct ixgbe_hw *hw =
4476 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4477 struct ixgbe_mirror_info *mr_info =
4478 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4480 if (ixgbe_vmdq_mode_check(hw) < 0)
4483 memset(&mr_info->mr_conf[rule_id], 0,
4484 sizeof(struct rte_eth_mirror_conf));
4486 /* clear PFVMCTL register */
4487 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4489 /* clear pool mask register */
4490 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4491 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4493 /* clear vlan mask register */
4494 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4495 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4501 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4504 struct ixgbe_hw *hw =
4505 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4507 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4508 mask |= (1 << IXGBE_MISC_VEC_ID);
4509 RTE_SET_USED(queue_id);
4510 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4512 rte_intr_enable(&dev->pci_dev->intr_handle);
4518 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4521 struct ixgbe_hw *hw =
4522 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4524 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4525 mask &= ~(1 << IXGBE_MISC_VEC_ID);
4526 RTE_SET_USED(queue_id);
4527 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4533 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4536 struct ixgbe_hw *hw =
4537 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4538 struct ixgbe_interrupt *intr =
4539 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4541 if (queue_id < 16) {
4542 ixgbe_disable_intr(hw);
4543 intr->mask |= (1 << queue_id);
4544 ixgbe_enable_intr(dev);
4545 } else if (queue_id < 32) {
4546 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4547 mask &= (1 << queue_id);
4548 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4549 } else if (queue_id < 64) {
4550 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4551 mask &= (1 << (queue_id - 32));
4552 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4554 rte_intr_enable(&dev->pci_dev->intr_handle);
4560 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4563 struct ixgbe_hw *hw =
4564 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4565 struct ixgbe_interrupt *intr =
4566 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4568 if (queue_id < 16) {
4569 ixgbe_disable_intr(hw);
4570 intr->mask &= ~(1 << queue_id);
4571 ixgbe_enable_intr(dev);
4572 } else if (queue_id < 32) {
4573 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4574 mask &= ~(1 << queue_id);
4575 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4576 } else if (queue_id < 64) {
4577 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4578 mask &= ~(1 << (queue_id - 32));
4579 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4586 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4587 uint8_t queue, uint8_t msix_vector)
4591 if (direction == -1) {
4593 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4594 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4597 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4599 /* rx or tx cause */
4600 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4601 idx = ((16 * (queue & 1)) + (8 * direction));
4602 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4603 tmp &= ~(0xFF << idx);
4604 tmp |= (msix_vector << idx);
4605 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4610 * set the IVAR registers, mapping interrupt causes to vectors
4612 * pointer to ixgbe_hw struct
4614 * 0 for Rx, 1 for Tx, -1 for other causes
4616 * queue to map the corresponding interrupt to
4618 * the vector to map to the corresponding queue
4621 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4622 uint8_t queue, uint8_t msix_vector)
4626 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4627 if (hw->mac.type == ixgbe_mac_82598EB) {
4628 if (direction == -1)
4630 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4631 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4632 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4633 tmp |= (msix_vector << (8 * (queue & 0x3)));
4634 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4635 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4636 (hw->mac.type == ixgbe_mac_X540)) {
4637 if (direction == -1) {
4639 idx = ((queue & 1) * 8);
4640 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4641 tmp &= ~(0xFF << idx);
4642 tmp |= (msix_vector << idx);
4643 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4645 /* rx or tx causes */
4646 idx = ((16 * (queue & 1)) + (8 * direction));
4647 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4648 tmp &= ~(0xFF << idx);
4649 tmp |= (msix_vector << idx);
4650 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4656 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4658 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4659 struct ixgbe_hw *hw =
4660 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4662 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4664 /* won't configure msix register if no mapping is done
4665 * between intr vector and event fd.
4667 if (!rte_intr_dp_is_en(intr_handle))
4670 /* Configure all RX queues of VF */
4671 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4672 /* Force all queue use vector 0,
4673 * as IXGBE_VF_MAXMSIVECOTR = 1
4675 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4676 intr_handle->intr_vec[q_idx] = vector_idx;
4679 /* Configure VF other cause ivar */
4680 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4684 * Sets up the hardware to properly generate MSI-X interrupts
4686 * board private structure
4689 ixgbe_configure_msix(struct rte_eth_dev *dev)
4691 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4692 struct ixgbe_hw *hw =
4693 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4694 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4695 uint32_t vec = IXGBE_MISC_VEC_ID;
4699 /* won't configure msix register if no mapping is done
4700 * between intr vector and event fd
4702 if (!rte_intr_dp_is_en(intr_handle))
4705 if (rte_intr_allow_others(intr_handle))
4706 vec = base = IXGBE_RX_VEC_START;
4708 /* setup GPIE for MSI-x mode */
4709 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4710 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4711 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4712 /* auto clearing and auto setting corresponding bits in EIMS
4713 * when MSI-X interrupt is triggered
4715 if (hw->mac.type == ixgbe_mac_82598EB) {
4716 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4718 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4719 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4721 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4723 /* Populate the IVAR table and set the ITR values to the
4724 * corresponding register.
4726 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4728 /* by default, 1:1 mapping */
4729 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4730 intr_handle->intr_vec[queue_id] = vec;
4731 if (vec < base + intr_handle->nb_efd - 1)
4735 switch (hw->mac.type) {
4736 case ixgbe_mac_82598EB:
4737 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4740 case ixgbe_mac_82599EB:
4741 case ixgbe_mac_X540:
4742 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4747 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4748 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4750 /* set up to autoclear timer, and the vectors */
4751 mask = IXGBE_EIMS_ENABLE_MASK;
4752 mask &= ~(IXGBE_EIMS_OTHER |
4753 IXGBE_EIMS_MAILBOX |
4756 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4759 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4760 uint16_t queue_idx, uint16_t tx_rate)
4762 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4763 uint32_t rf_dec, rf_int;
4765 uint16_t link_speed = dev->data->dev_link.link_speed;
4767 if (queue_idx >= hw->mac.max_tx_queues)
4771 /* Calculate the rate factor values to set */
4772 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4773 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4774 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4776 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4777 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4778 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4779 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4785 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4786 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4789 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4790 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4791 IXGBE_MAX_JUMBO_FRAME_SIZE))
4792 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4793 IXGBE_MMW_SIZE_JUMBO_FRAME);
4795 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4796 IXGBE_MMW_SIZE_DEFAULT);
4798 /* Set RTTBCNRC of queue X */
4799 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4800 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4801 IXGBE_WRITE_FLUSH(hw);
4806 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4807 uint16_t tx_rate, uint64_t q_msk)
4809 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4810 struct ixgbe_vf_info *vfinfo =
4811 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4812 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4813 uint32_t queue_stride =
4814 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4815 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4816 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4817 uint16_t total_rate = 0;
4819 if (queue_end >= hw->mac.max_tx_queues)
4822 if (vfinfo != NULL) {
4823 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4826 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4828 total_rate += vfinfo[vf_idx].tx_rate[idx];
4833 /* Store tx_rate for this vf. */
4834 for (idx = 0; idx < nb_q_per_pool; idx++) {
4835 if (((uint64_t)0x1 << idx) & q_msk) {
4836 if (vfinfo[vf].tx_rate[idx] != tx_rate)
4837 vfinfo[vf].tx_rate[idx] = tx_rate;
4838 total_rate += tx_rate;
4842 if (total_rate > dev->data->dev_link.link_speed) {
4844 * Reset stored TX rate of the VF if it causes exceed
4847 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4851 /* Set RTTBCNRC of each queue/pool for vf X */
4852 for (; queue_idx <= queue_end; queue_idx++) {
4854 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4862 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4863 __attribute__((unused)) uint32_t index,
4864 __attribute__((unused)) uint32_t pool)
4866 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4870 * On a 82599 VF, adding again the same MAC addr is not an idempotent
4871 * operation. Trap this case to avoid exhausting the [very limited]
4872 * set of PF resources used to store VF MAC addresses.
4874 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4876 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4879 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4883 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4887 struct ether_addr *mac_addr;
4892 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4893 * not support the deletion of a given MAC address.
4894 * Instead, it imposes to delete all MAC addresses, then to add again
4895 * all MAC addresses with the exception of the one to be deleted.
4897 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4900 * Add again all MAC addresses, with the exception of the deleted one
4901 * and of the permanent MAC address.
4903 for (i = 0, mac_addr = dev->data->mac_addrs;
4904 i < hw->mac.num_rar_entries; i++, mac_addr++) {
4905 /* Skip the deleted MAC address */
4908 /* Skip NULL MAC addresses */
4909 if (is_zero_ether_addr(mac_addr))
4911 /* Skip the permanent MAC address */
4912 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4914 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4917 "Adding again MAC address "
4918 "%02x:%02x:%02x:%02x:%02x:%02x failed "
4920 mac_addr->addr_bytes[0],
4921 mac_addr->addr_bytes[1],
4922 mac_addr->addr_bytes[2],
4923 mac_addr->addr_bytes[3],
4924 mac_addr->addr_bytes[4],
4925 mac_addr->addr_bytes[5],
4931 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4933 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4935 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4938 #define MAC_TYPE_FILTER_SUP(type) do {\
4939 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4940 (type) != ixgbe_mac_X550)\
4945 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4946 struct rte_eth_syn_filter *filter,
4949 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4952 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4955 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4958 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4960 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4961 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4963 if (filter->hig_pri)
4964 synqf |= IXGBE_SYN_FILTER_SYNQFP;
4966 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4968 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4970 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4972 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4973 IXGBE_WRITE_FLUSH(hw);
4978 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4979 struct rte_eth_syn_filter *filter)
4981 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4984 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4985 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4986 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4993 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4994 enum rte_filter_op filter_op,
4997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5000 MAC_TYPE_FILTER_SUP(hw->mac.type);
5002 if (filter_op == RTE_ETH_FILTER_NOP)
5006 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5011 switch (filter_op) {
5012 case RTE_ETH_FILTER_ADD:
5013 ret = ixgbe_syn_filter_set(dev,
5014 (struct rte_eth_syn_filter *)arg,
5017 case RTE_ETH_FILTER_DELETE:
5018 ret = ixgbe_syn_filter_set(dev,
5019 (struct rte_eth_syn_filter *)arg,
5022 case RTE_ETH_FILTER_GET:
5023 ret = ixgbe_syn_filter_get(dev,
5024 (struct rte_eth_syn_filter *)arg);
5027 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5036 static inline enum ixgbe_5tuple_protocol
5037 convert_protocol_type(uint8_t protocol_value)
5039 if (protocol_value == IPPROTO_TCP)
5040 return IXGBE_FILTER_PROTOCOL_TCP;
5041 else if (protocol_value == IPPROTO_UDP)
5042 return IXGBE_FILTER_PROTOCOL_UDP;
5043 else if (protocol_value == IPPROTO_SCTP)
5044 return IXGBE_FILTER_PROTOCOL_SCTP;
5046 return IXGBE_FILTER_PROTOCOL_NONE;
5050 * add a 5tuple filter
5053 * dev: Pointer to struct rte_eth_dev.
5054 * index: the index the filter allocates.
5055 * filter: ponter to the filter that will be added.
5056 * rx_queue: the queue id the filter assigned to.
5059 * - On success, zero.
5060 * - On failure, a negative value.
5063 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5064 struct ixgbe_5tuple_filter *filter)
5066 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5067 struct ixgbe_filter_info *filter_info =
5068 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5070 uint32_t ftqf, sdpqf;
5071 uint32_t l34timir = 0;
5072 uint8_t mask = 0xff;
5075 * look for an unused 5tuple filter index,
5076 * and insert the filter to list.
5078 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5079 idx = i / (sizeof(uint32_t) * NBBY);
5080 shift = i % (sizeof(uint32_t) * NBBY);
5081 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5082 filter_info->fivetuple_mask[idx] |= 1 << shift;
5084 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5090 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5091 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5095 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5096 IXGBE_SDPQF_DSTPORT_SHIFT);
5097 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5099 ftqf = (uint32_t)(filter->filter_info.proto &
5100 IXGBE_FTQF_PROTOCOL_MASK);
5101 ftqf |= (uint32_t)((filter->filter_info.priority &
5102 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5103 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5104 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5105 if (filter->filter_info.dst_ip_mask == 0)
5106 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5107 if (filter->filter_info.src_port_mask == 0)
5108 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5109 if (filter->filter_info.dst_port_mask == 0)
5110 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5111 if (filter->filter_info.proto_mask == 0)
5112 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5113 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5114 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5115 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5117 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5118 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5119 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5120 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5122 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5123 l34timir |= (uint32_t)(filter->queue <<
5124 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5125 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5130 * remove a 5tuple filter
5133 * dev: Pointer to struct rte_eth_dev.
5134 * filter: the pointer of the filter will be removed.
5137 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5138 struct ixgbe_5tuple_filter *filter)
5140 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5141 struct ixgbe_filter_info *filter_info =
5142 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5143 uint16_t index = filter->index;
5145 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5146 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5147 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5150 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5151 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5152 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5153 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5154 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5158 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5160 struct ixgbe_hw *hw;
5161 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5163 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5165 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5168 /* refuse mtu that requires the support of scattered packets when this
5169 * feature has not been enabled before. */
5170 if (!dev->data->scattered_rx &&
5171 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5172 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5176 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5177 * request of the version 2.0 of the mailbox API.
5178 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5179 * of the mailbox API.
5180 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5181 * prior to 3.11.33 which contains the following change:
5182 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5184 ixgbevf_rlpml_set_vf(hw, max_frame);
5186 /* update max frame size */
5187 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5191 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
5192 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5196 static inline struct ixgbe_5tuple_filter *
5197 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5198 struct ixgbe_5tuple_filter_info *key)
5200 struct ixgbe_5tuple_filter *it;
5202 TAILQ_FOREACH(it, filter_list, entries) {
5203 if (memcmp(key, &it->filter_info,
5204 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5211 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5213 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5214 struct ixgbe_5tuple_filter_info *filter_info)
5216 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5217 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5218 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5221 switch (filter->dst_ip_mask) {
5223 filter_info->dst_ip_mask = 0;
5224 filter_info->dst_ip = filter->dst_ip;
5227 filter_info->dst_ip_mask = 1;
5230 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5234 switch (filter->src_ip_mask) {
5236 filter_info->src_ip_mask = 0;
5237 filter_info->src_ip = filter->src_ip;
5240 filter_info->src_ip_mask = 1;
5243 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5247 switch (filter->dst_port_mask) {
5249 filter_info->dst_port_mask = 0;
5250 filter_info->dst_port = filter->dst_port;
5253 filter_info->dst_port_mask = 1;
5256 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5260 switch (filter->src_port_mask) {
5262 filter_info->src_port_mask = 0;
5263 filter_info->src_port = filter->src_port;
5266 filter_info->src_port_mask = 1;
5269 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5273 switch (filter->proto_mask) {
5275 filter_info->proto_mask = 0;
5276 filter_info->proto =
5277 convert_protocol_type(filter->proto);
5280 filter_info->proto_mask = 1;
5283 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5287 filter_info->priority = (uint8_t)filter->priority;
5292 * add or delete a ntuple filter
5295 * dev: Pointer to struct rte_eth_dev.
5296 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5297 * add: if true, add filter, if false, remove filter
5300 * - On success, zero.
5301 * - On failure, a negative value.
5304 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5305 struct rte_eth_ntuple_filter *ntuple_filter,
5308 struct ixgbe_filter_info *filter_info =
5309 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5310 struct ixgbe_5tuple_filter_info filter_5tuple;
5311 struct ixgbe_5tuple_filter *filter;
5314 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5315 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5319 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5320 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5324 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5326 if (filter != NULL && add) {
5327 PMD_DRV_LOG(ERR, "filter exists.");
5330 if (filter == NULL && !add) {
5331 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5336 filter = rte_zmalloc("ixgbe_5tuple_filter",
5337 sizeof(struct ixgbe_5tuple_filter), 0);
5340 (void)rte_memcpy(&filter->filter_info,
5342 sizeof(struct ixgbe_5tuple_filter_info));
5343 filter->queue = ntuple_filter->queue;
5344 ret = ixgbe_add_5tuple_filter(dev, filter);
5350 ixgbe_remove_5tuple_filter(dev, filter);
5356 * get a ntuple filter
5359 * dev: Pointer to struct rte_eth_dev.
5360 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5363 * - On success, zero.
5364 * - On failure, a negative value.
5367 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5368 struct rte_eth_ntuple_filter *ntuple_filter)
5370 struct ixgbe_filter_info *filter_info =
5371 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5372 struct ixgbe_5tuple_filter_info filter_5tuple;
5373 struct ixgbe_5tuple_filter *filter;
5376 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5377 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5381 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5382 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5386 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5388 if (filter == NULL) {
5389 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5392 ntuple_filter->queue = filter->queue;
5397 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5398 * @dev: pointer to rte_eth_dev structure
5399 * @filter_op:operation will be taken.
5400 * @arg: a pointer to specific structure corresponding to the filter_op
5403 * - On success, zero.
5404 * - On failure, a negative value.
5407 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5408 enum rte_filter_op filter_op,
5411 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5414 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5416 if (filter_op == RTE_ETH_FILTER_NOP)
5420 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5425 switch (filter_op) {
5426 case RTE_ETH_FILTER_ADD:
5427 ret = ixgbe_add_del_ntuple_filter(dev,
5428 (struct rte_eth_ntuple_filter *)arg,
5431 case RTE_ETH_FILTER_DELETE:
5432 ret = ixgbe_add_del_ntuple_filter(dev,
5433 (struct rte_eth_ntuple_filter *)arg,
5436 case RTE_ETH_FILTER_GET:
5437 ret = ixgbe_get_ntuple_filter(dev,
5438 (struct rte_eth_ntuple_filter *)arg);
5441 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5449 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5454 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5455 if (filter_info->ethertype_filters[i] == ethertype &&
5456 (filter_info->ethertype_mask & (1 << i)))
5463 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5468 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5469 if (!(filter_info->ethertype_mask & (1 << i))) {
5470 filter_info->ethertype_mask |= 1 << i;
5471 filter_info->ethertype_filters[i] = ethertype;
5479 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5482 if (idx >= IXGBE_MAX_ETQF_FILTERS)
5484 filter_info->ethertype_mask &= ~(1 << idx);
5485 filter_info->ethertype_filters[idx] = 0;
5490 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5491 struct rte_eth_ethertype_filter *filter,
5494 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5495 struct ixgbe_filter_info *filter_info =
5496 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5501 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5504 if (filter->ether_type == ETHER_TYPE_IPv4 ||
5505 filter->ether_type == ETHER_TYPE_IPv6) {
5506 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5507 " ethertype filter.", filter->ether_type);
5511 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5512 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5515 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5516 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5520 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5521 if (ret >= 0 && add) {
5522 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5523 filter->ether_type);
5526 if (ret < 0 && !add) {
5527 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5528 filter->ether_type);
5533 ret = ixgbe_ethertype_filter_insert(filter_info,
5534 filter->ether_type);
5536 PMD_DRV_LOG(ERR, "ethertype filters are full.");
5539 etqf = IXGBE_ETQF_FILTER_EN;
5540 etqf |= (uint32_t)filter->ether_type;
5541 etqs |= (uint32_t)((filter->queue <<
5542 IXGBE_ETQS_RX_QUEUE_SHIFT) &
5543 IXGBE_ETQS_RX_QUEUE);
5544 etqs |= IXGBE_ETQS_QUEUE_EN;
5546 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5550 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5551 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5552 IXGBE_WRITE_FLUSH(hw);
5558 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5559 struct rte_eth_ethertype_filter *filter)
5561 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5562 struct ixgbe_filter_info *filter_info =
5563 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5564 uint32_t etqf, etqs;
5567 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5569 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5570 filter->ether_type);
5574 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5575 if (etqf & IXGBE_ETQF_FILTER_EN) {
5576 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5577 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5579 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5580 IXGBE_ETQS_RX_QUEUE_SHIFT;
5587 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5588 * @dev: pointer to rte_eth_dev structure
5589 * @filter_op:operation will be taken.
5590 * @arg: a pointer to specific structure corresponding to the filter_op
5593 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5594 enum rte_filter_op filter_op,
5597 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5600 MAC_TYPE_FILTER_SUP(hw->mac.type);
5602 if (filter_op == RTE_ETH_FILTER_NOP)
5606 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5611 switch (filter_op) {
5612 case RTE_ETH_FILTER_ADD:
5613 ret = ixgbe_add_del_ethertype_filter(dev,
5614 (struct rte_eth_ethertype_filter *)arg,
5617 case RTE_ETH_FILTER_DELETE:
5618 ret = ixgbe_add_del_ethertype_filter(dev,
5619 (struct rte_eth_ethertype_filter *)arg,
5622 case RTE_ETH_FILTER_GET:
5623 ret = ixgbe_get_ethertype_filter(dev,
5624 (struct rte_eth_ethertype_filter *)arg);
5627 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5635 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5636 enum rte_filter_type filter_type,
5637 enum rte_filter_op filter_op,
5642 switch (filter_type) {
5643 case RTE_ETH_FILTER_NTUPLE:
5644 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5646 case RTE_ETH_FILTER_ETHERTYPE:
5647 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5649 case RTE_ETH_FILTER_SYN:
5650 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5652 case RTE_ETH_FILTER_FDIR:
5653 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5655 case RTE_ETH_FILTER_L2_TUNNEL:
5656 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5659 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5668 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5669 u8 **mc_addr_ptr, u32 *vmdq)
5674 mc_addr = *mc_addr_ptr;
5675 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5680 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5681 struct ether_addr *mc_addr_set,
5682 uint32_t nb_mc_addr)
5684 struct ixgbe_hw *hw;
5687 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5688 mc_addr_list = (u8 *)mc_addr_set;
5689 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5690 ixgbe_dev_addr_list_itr, TRUE);
5694 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5696 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5697 uint64_t systime_cycles;
5699 switch (hw->mac.type) {
5700 case ixgbe_mac_X550:
5701 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5702 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5703 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5707 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5708 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5712 return systime_cycles;
5716 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5718 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5719 uint64_t rx_tstamp_cycles;
5721 switch (hw->mac.type) {
5722 case ixgbe_mac_X550:
5723 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5724 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5725 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5729 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5730 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5731 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5735 return rx_tstamp_cycles;
5739 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5741 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5742 uint64_t tx_tstamp_cycles;
5744 switch (hw->mac.type) {
5745 case ixgbe_mac_X550:
5746 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5747 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5748 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5752 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5753 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5754 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5758 return tx_tstamp_cycles;
5762 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5764 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5765 struct ixgbe_adapter *adapter =
5766 (struct ixgbe_adapter *)dev->data->dev_private;
5767 struct rte_eth_link link;
5768 uint32_t incval = 0;
5771 /* Get current link speed. */
5772 memset(&link, 0, sizeof(link));
5773 ixgbe_dev_link_update(dev, 1);
5774 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5776 switch (link.link_speed) {
5777 case ETH_LINK_SPEED_100:
5778 incval = IXGBE_INCVAL_100;
5779 shift = IXGBE_INCVAL_SHIFT_100;
5781 case ETH_LINK_SPEED_1000:
5782 incval = IXGBE_INCVAL_1GB;
5783 shift = IXGBE_INCVAL_SHIFT_1GB;
5785 case ETH_LINK_SPEED_10000:
5787 incval = IXGBE_INCVAL_10GB;
5788 shift = IXGBE_INCVAL_SHIFT_10GB;
5792 switch (hw->mac.type) {
5793 case ixgbe_mac_X550:
5794 /* Independent of link speed. */
5796 /* Cycles read will be interpreted as ns. */
5799 case ixgbe_mac_X540:
5800 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5802 case ixgbe_mac_82599EB:
5803 incval >>= IXGBE_INCVAL_SHIFT_82599;
5804 shift -= IXGBE_INCVAL_SHIFT_82599;
5805 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5806 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5809 /* Not supported. */
5813 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5814 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5815 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5817 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5818 adapter->systime_tc.cc_shift = shift;
5819 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5821 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5822 adapter->rx_tstamp_tc.cc_shift = shift;
5823 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5825 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5826 adapter->tx_tstamp_tc.cc_shift = shift;
5827 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5831 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5833 struct ixgbe_adapter *adapter =
5834 (struct ixgbe_adapter *)dev->data->dev_private;
5836 adapter->systime_tc.nsec += delta;
5837 adapter->rx_tstamp_tc.nsec += delta;
5838 adapter->tx_tstamp_tc.nsec += delta;
5844 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5847 struct ixgbe_adapter *adapter =
5848 (struct ixgbe_adapter *)dev->data->dev_private;
5850 ns = rte_timespec_to_ns(ts);
5851 /* Set the timecounters to a new value. */
5852 adapter->systime_tc.nsec = ns;
5853 adapter->rx_tstamp_tc.nsec = ns;
5854 adapter->tx_tstamp_tc.nsec = ns;
5860 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5862 uint64_t ns, systime_cycles;
5863 struct ixgbe_adapter *adapter =
5864 (struct ixgbe_adapter *)dev->data->dev_private;
5866 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5867 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5868 *ts = rte_ns_to_timespec(ns);
5874 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5880 /* Stop the timesync system time. */
5881 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5882 /* Reset the timesync system time value. */
5883 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5884 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5886 /* Enable system time for platforms where it isn't on by default. */
5887 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5888 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5889 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5891 ixgbe_start_timecounters(dev);
5893 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5894 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5896 IXGBE_ETQF_FILTER_EN |
5899 /* Enable timestamping of received PTP packets. */
5900 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5901 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5902 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5904 /* Enable timestamping of transmitted PTP packets. */
5905 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5906 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5907 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5909 IXGBE_WRITE_FLUSH(hw);
5915 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5917 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5920 /* Disable timestamping of transmitted PTP packets. */
5921 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5922 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5923 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5925 /* Disable timestamping of received PTP packets. */
5926 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5927 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5928 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5930 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5931 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5933 /* Stop incrementating the System Time registers. */
5934 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5940 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5941 struct timespec *timestamp,
5942 uint32_t flags __rte_unused)
5944 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5945 struct ixgbe_adapter *adapter =
5946 (struct ixgbe_adapter *)dev->data->dev_private;
5947 uint32_t tsync_rxctl;
5948 uint64_t rx_tstamp_cycles;
5951 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5952 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5955 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
5956 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5957 *timestamp = rte_ns_to_timespec(ns);
5963 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5964 struct timespec *timestamp)
5966 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5967 struct ixgbe_adapter *adapter =
5968 (struct ixgbe_adapter *)dev->data->dev_private;
5969 uint32_t tsync_txctl;
5970 uint64_t tx_tstamp_cycles;
5973 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5974 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5977 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
5978 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5979 *timestamp = rte_ns_to_timespec(ns);
5985 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5987 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5990 const struct reg_info *reg_group;
5991 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5992 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5994 while ((reg_group = reg_set[g_ind++]))
5995 count += ixgbe_regs_group_count(reg_group);
6001 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6005 const struct reg_info *reg_group;
6007 while ((reg_group = ixgbevf_regs[g_ind++]))
6008 count += ixgbe_regs_group_count(reg_group);
6014 ixgbe_get_regs(struct rte_eth_dev *dev,
6015 struct rte_dev_reg_info *regs)
6017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6018 uint32_t *data = regs->data;
6021 const struct reg_info *reg_group;
6022 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6023 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6025 /* Support only full register dump */
6026 if ((regs->length == 0) ||
6027 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6028 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6030 while ((reg_group = reg_set[g_ind++]))
6031 count += ixgbe_read_regs_group(dev, &data[count],
6040 ixgbevf_get_regs(struct rte_eth_dev *dev,
6041 struct rte_dev_reg_info *regs)
6043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6044 uint32_t *data = regs->data;
6047 const struct reg_info *reg_group;
6049 /* Support only full register dump */
6050 if ((regs->length == 0) ||
6051 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6052 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6054 while ((reg_group = ixgbevf_regs[g_ind++]))
6055 count += ixgbe_read_regs_group(dev, &data[count],
6064 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6066 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6068 /* Return unit is byte count */
6069 return hw->eeprom.word_size * 2;
6073 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6074 struct rte_dev_eeprom_info *in_eeprom)
6076 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6077 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6078 uint16_t *data = in_eeprom->data;
6081 first = in_eeprom->offset >> 1;
6082 length = in_eeprom->length >> 1;
6083 if ((first > hw->eeprom.word_size) ||
6084 ((first + length) > hw->eeprom.word_size))
6087 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6089 return eeprom->ops.read_buffer(hw, first, length, data);
6093 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6094 struct rte_dev_eeprom_info *in_eeprom)
6096 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6097 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6098 uint16_t *data = in_eeprom->data;
6101 first = in_eeprom->offset >> 1;
6102 length = in_eeprom->length >> 1;
6103 if ((first > hw->eeprom.word_size) ||
6104 ((first + length) > hw->eeprom.word_size))
6107 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6109 return eeprom->ops.write_buffer(hw, first, length, data);
6113 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6115 case ixgbe_mac_X550:
6116 case ixgbe_mac_X550EM_x:
6117 return ETH_RSS_RETA_SIZE_512;
6118 case ixgbe_mac_X550_vf:
6119 case ixgbe_mac_X550EM_x_vf:
6120 return ETH_RSS_RETA_SIZE_64;
6122 return ETH_RSS_RETA_SIZE_128;
6127 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6129 case ixgbe_mac_X550:
6130 case ixgbe_mac_X550EM_x:
6131 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6132 return IXGBE_RETA(reta_idx >> 2);
6134 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6135 case ixgbe_mac_X550_vf:
6136 case ixgbe_mac_X550EM_x_vf:
6137 return IXGBE_VFRETA(reta_idx >> 2);
6139 return IXGBE_RETA(reta_idx >> 2);
6144 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6146 case ixgbe_mac_X550_vf:
6147 case ixgbe_mac_X550EM_x_vf:
6148 return IXGBE_VFMRQC;
6155 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6157 case ixgbe_mac_X550_vf:
6158 case ixgbe_mac_X550EM_x_vf:
6159 return IXGBE_VFRSSRK(i);
6161 return IXGBE_RSSRK(i);
6166 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6168 case ixgbe_mac_82599_vf:
6169 case ixgbe_mac_X540_vf:
6177 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6178 struct rte_eth_dcb_info *dcb_info)
6180 struct ixgbe_dcb_config *dcb_config =
6181 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6182 struct ixgbe_dcb_tc_config *tc;
6185 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6186 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6188 dcb_info->nb_tcs = 1;
6190 if (dcb_config->vt_mode) { /* vt is enabled*/
6191 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6192 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6193 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6194 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6195 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6196 for (j = 0; j < dcb_info->nb_tcs; j++) {
6197 dcb_info->tc_queue.tc_rxq[i][j].base =
6198 i * dcb_info->nb_tcs + j;
6199 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6200 dcb_info->tc_queue.tc_txq[i][j].base =
6201 i * dcb_info->nb_tcs + j;
6202 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6205 } else { /* vt is disabled*/
6206 struct rte_eth_dcb_rx_conf *rx_conf =
6207 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6208 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6209 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6210 if (dcb_info->nb_tcs == ETH_4_TCS) {
6211 for (i = 0; i < dcb_info->nb_tcs; i++) {
6212 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6213 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6215 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6216 dcb_info->tc_queue.tc_txq[0][1].base = 64;
6217 dcb_info->tc_queue.tc_txq[0][2].base = 96;
6218 dcb_info->tc_queue.tc_txq[0][3].base = 112;
6219 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6220 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6221 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6222 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6223 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6224 for (i = 0; i < dcb_info->nb_tcs; i++) {
6225 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6226 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6228 dcb_info->tc_queue.tc_txq[0][0].base = 0;
6229 dcb_info->tc_queue.tc_txq[0][1].base = 32;
6230 dcb_info->tc_queue.tc_txq[0][2].base = 64;
6231 dcb_info->tc_queue.tc_txq[0][3].base = 80;
6232 dcb_info->tc_queue.tc_txq[0][4].base = 96;
6233 dcb_info->tc_queue.tc_txq[0][5].base = 104;
6234 dcb_info->tc_queue.tc_txq[0][6].base = 112;
6235 dcb_info->tc_queue.tc_txq[0][7].base = 120;
6236 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6237 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6238 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6239 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6240 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6241 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6242 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6243 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6246 for (i = 0; i < dcb_info->nb_tcs; i++) {
6247 tc = &dcb_config->tc_config[i];
6248 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6253 /* Update e-tag ether type */
6255 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6256 uint16_t ether_type)
6258 uint32_t etag_etype;
6260 if (hw->mac.type != ixgbe_mac_X550 &&
6261 hw->mac.type != ixgbe_mac_X550EM_x) {
6265 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6266 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6267 etag_etype |= ether_type;
6268 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6269 IXGBE_WRITE_FLUSH(hw);
6274 /* Config l2 tunnel ether type */
6276 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6277 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6280 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6282 if (l2_tunnel == NULL)
6285 switch (l2_tunnel->l2_tunnel_type) {
6286 case RTE_L2_TUNNEL_TYPE_E_TAG:
6287 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6290 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6298 /* Enable e-tag tunnel */
6300 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6302 uint32_t etag_etype;
6304 if (hw->mac.type != ixgbe_mac_X550 &&
6305 hw->mac.type != ixgbe_mac_X550EM_x) {
6309 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6310 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6311 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6312 IXGBE_WRITE_FLUSH(hw);
6317 /* Enable l2 tunnel */
6319 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6320 enum rte_eth_tunnel_type l2_tunnel_type)
6323 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6325 switch (l2_tunnel_type) {
6326 case RTE_L2_TUNNEL_TYPE_E_TAG:
6327 ret = ixgbe_e_tag_enable(hw);
6330 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6338 /* Disable e-tag tunnel */
6340 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6342 uint32_t etag_etype;
6344 if (hw->mac.type != ixgbe_mac_X550 &&
6345 hw->mac.type != ixgbe_mac_X550EM_x) {
6349 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6350 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6351 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6352 IXGBE_WRITE_FLUSH(hw);
6357 /* Disable l2 tunnel */
6359 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6360 enum rte_eth_tunnel_type l2_tunnel_type)
6363 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6365 switch (l2_tunnel_type) {
6366 case RTE_L2_TUNNEL_TYPE_E_TAG:
6367 ret = ixgbe_e_tag_disable(hw);
6370 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6379 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6380 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6383 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6384 uint32_t i, rar_entries;
6385 uint32_t rar_low, rar_high;
6387 if (hw->mac.type != ixgbe_mac_X550 &&
6388 hw->mac.type != ixgbe_mac_X550EM_x) {
6392 rar_entries = ixgbe_get_num_rx_addrs(hw);
6394 for (i = 1; i < rar_entries; i++) {
6395 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6396 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6397 if ((rar_high & IXGBE_RAH_AV) &&
6398 (rar_high & IXGBE_RAH_ADTYPE) &&
6399 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6400 l2_tunnel->tunnel_id)) {
6401 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6402 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6404 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6414 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6415 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6418 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6419 uint32_t i, rar_entries;
6420 uint32_t rar_low, rar_high;
6422 if (hw->mac.type != ixgbe_mac_X550 &&
6423 hw->mac.type != ixgbe_mac_X550EM_x) {
6427 /* One entry for one tunnel. Try to remove potential existing entry. */
6428 ixgbe_e_tag_filter_del(dev, l2_tunnel);
6430 rar_entries = ixgbe_get_num_rx_addrs(hw);
6432 for (i = 1; i < rar_entries; i++) {
6433 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6434 if (rar_high & IXGBE_RAH_AV) {
6437 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6438 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6439 rar_low = l2_tunnel->tunnel_id;
6441 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6442 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6448 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6449 " Please remove a rule before adding a new one.");
6453 /* Add l2 tunnel filter */
6455 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6456 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6460 switch (l2_tunnel->l2_tunnel_type) {
6461 case RTE_L2_TUNNEL_TYPE_E_TAG:
6462 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6465 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6473 /* Delete l2 tunnel filter */
6475 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6476 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6480 switch (l2_tunnel->l2_tunnel_type) {
6481 case RTE_L2_TUNNEL_TYPE_E_TAG:
6482 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6485 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6494 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6495 * @dev: pointer to rte_eth_dev structure
6496 * @filter_op:operation will be taken.
6497 * @arg: a pointer to specific structure corresponding to the filter_op
6500 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6501 enum rte_filter_op filter_op,
6506 if (filter_op == RTE_ETH_FILTER_NOP)
6510 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6515 switch (filter_op) {
6516 case RTE_ETH_FILTER_ADD:
6517 ret = ixgbe_dev_l2_tunnel_filter_add
6519 (struct rte_eth_l2_tunnel_conf *)arg);
6521 case RTE_ETH_FILTER_DELETE:
6522 ret = ixgbe_dev_l2_tunnel_filter_del
6524 (struct rte_eth_l2_tunnel_conf *)arg);
6527 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6535 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6539 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6541 if (hw->mac.type != ixgbe_mac_X550 &&
6542 hw->mac.type != ixgbe_mac_X550EM_x) {
6546 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6547 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6549 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6550 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6555 /* Enable l2 tunnel forwarding */
6557 ixgbe_dev_l2_tunnel_forwarding_enable
6558 (struct rte_eth_dev *dev,
6559 enum rte_eth_tunnel_type l2_tunnel_type)
6563 switch (l2_tunnel_type) {
6564 case RTE_L2_TUNNEL_TYPE_E_TAG:
6565 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6568 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6576 /* Disable l2 tunnel forwarding */
6578 ixgbe_dev_l2_tunnel_forwarding_disable
6579 (struct rte_eth_dev *dev,
6580 enum rte_eth_tunnel_type l2_tunnel_type)
6584 switch (l2_tunnel_type) {
6585 case RTE_L2_TUNNEL_TYPE_E_TAG:
6586 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6589 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6598 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6599 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6603 uint32_t vmtir, vmvir;
6604 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6606 if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6608 "VF id %u should be less than %u",
6610 dev->pci_dev->max_vfs);
6614 if (hw->mac.type != ixgbe_mac_X550 &&
6615 hw->mac.type != ixgbe_mac_X550EM_x) {
6620 vmtir = l2_tunnel->tunnel_id;
6624 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6626 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6627 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6629 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6630 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6635 /* Enable l2 tunnel tag insertion */
6637 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6638 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6642 switch (l2_tunnel->l2_tunnel_type) {
6643 case RTE_L2_TUNNEL_TYPE_E_TAG:
6644 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6647 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6655 /* Disable l2 tunnel tag insertion */
6657 ixgbe_dev_l2_tunnel_insertion_disable
6658 (struct rte_eth_dev *dev,
6659 struct rte_eth_l2_tunnel_conf *l2_tunnel)
6663 switch (l2_tunnel->l2_tunnel_type) {
6664 case RTE_L2_TUNNEL_TYPE_E_TAG:
6665 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6668 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6677 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6682 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6684 if (hw->mac.type != ixgbe_mac_X550 &&
6685 hw->mac.type != ixgbe_mac_X550EM_x) {
6689 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6691 qde |= IXGBE_QDE_STRIP_TAG;
6693 qde &= ~IXGBE_QDE_STRIP_TAG;
6694 qde &= ~IXGBE_QDE_READ;
6695 qde |= IXGBE_QDE_WRITE;
6696 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6701 /* Enable l2 tunnel tag stripping */
6703 ixgbe_dev_l2_tunnel_stripping_enable
6704 (struct rte_eth_dev *dev,
6705 enum rte_eth_tunnel_type l2_tunnel_type)
6709 switch (l2_tunnel_type) {
6710 case RTE_L2_TUNNEL_TYPE_E_TAG:
6711 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6714 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6722 /* Disable l2 tunnel tag stripping */
6724 ixgbe_dev_l2_tunnel_stripping_disable
6725 (struct rte_eth_dev *dev,
6726 enum rte_eth_tunnel_type l2_tunnel_type)
6730 switch (l2_tunnel_type) {
6731 case RTE_L2_TUNNEL_TYPE_E_TAG:
6732 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6735 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6743 /* Enable/disable l2 tunnel offload functions */
6745 ixgbe_dev_l2_tunnel_offload_set
6746 (struct rte_eth_dev *dev,
6747 struct rte_eth_l2_tunnel_conf *l2_tunnel,
6753 if (l2_tunnel == NULL)
6757 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6759 ret = ixgbe_dev_l2_tunnel_enable(
6761 l2_tunnel->l2_tunnel_type);
6763 ret = ixgbe_dev_l2_tunnel_disable(
6765 l2_tunnel->l2_tunnel_type);
6768 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6770 ret = ixgbe_dev_l2_tunnel_insertion_enable(
6774 ret = ixgbe_dev_l2_tunnel_insertion_disable(
6779 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6781 ret = ixgbe_dev_l2_tunnel_stripping_enable(
6783 l2_tunnel->l2_tunnel_type);
6785 ret = ixgbe_dev_l2_tunnel_stripping_disable(
6787 l2_tunnel->l2_tunnel_type);
6790 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6792 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6794 l2_tunnel->l2_tunnel_type);
6796 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6798 l2_tunnel->l2_tunnel_type);
6805 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6808 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6809 IXGBE_WRITE_FLUSH(hw);
6814 /* There's only one register for VxLAN UDP port.
6815 * So, we cannot add several ports. Will update it.
6818 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6822 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6826 return ixgbe_update_vxlan_port(hw, port);
6829 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6830 * UDP port, it must have a value.
6831 * So, will reset it to the original value 0.
6834 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6839 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6841 if (cur_port != port) {
6842 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6846 return ixgbe_update_vxlan_port(hw, 0);
6849 /* Add UDP tunneling port */
6851 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6852 struct rte_eth_udp_tunnel *udp_tunnel)
6855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6857 if (hw->mac.type != ixgbe_mac_X550 &&
6858 hw->mac.type != ixgbe_mac_X550EM_x) {
6862 if (udp_tunnel == NULL)
6865 switch (udp_tunnel->prot_type) {
6866 case RTE_TUNNEL_TYPE_VXLAN:
6867 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6870 case RTE_TUNNEL_TYPE_GENEVE:
6871 case RTE_TUNNEL_TYPE_TEREDO:
6872 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6877 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6885 /* Remove UDP tunneling port */
6887 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6888 struct rte_eth_udp_tunnel *udp_tunnel)
6891 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893 if (hw->mac.type != ixgbe_mac_X550 &&
6894 hw->mac.type != ixgbe_mac_X550EM_x) {
6898 if (udp_tunnel == NULL)
6901 switch (udp_tunnel->prot_type) {
6902 case RTE_TUNNEL_TYPE_VXLAN:
6903 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6905 case RTE_TUNNEL_TYPE_GENEVE:
6906 case RTE_TUNNEL_TYPE_TEREDO:
6907 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6911 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6919 static struct rte_driver rte_ixgbe_driver = {
6921 .init = rte_ixgbe_pmd_init,
6924 static struct rte_driver rte_ixgbevf_driver = {
6926 .init = rte_ixgbevf_pmd_init,
6929 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6930 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);