drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int  ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 549         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 550         .dev_led_on           = ixgbe_dev_led_on,
 551         .dev_led_off          = ixgbe_dev_led_off,
 552         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 553         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 554         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 555         .mac_addr_add         = ixgbe_add_rar,
 556         .mac_addr_remove      = ixgbe_remove_rar,
 557         .mac_addr_set         = ixgbe_set_default_mac_addr,
 558         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 559         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 560         .mirror_rule_set      = ixgbe_mirror_rule_set,
 561         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 562         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 563         .reta_update          = ixgbe_dev_rss_reta_update,
 564         .reta_query           = ixgbe_dev_rss_reta_query,
 565         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 566         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 567         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 568         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 569         .rxq_info_get         = ixgbe_rxq_info_get,
 570         .txq_info_get         = ixgbe_txq_info_get,
 571         .timesync_enable      = ixgbe_timesync_enable,
 572         .timesync_disable     = ixgbe_timesync_disable,
 573         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 574         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 575         .get_reg              = ixgbe_get_regs,
 576         .get_eeprom_length    = ixgbe_get_eeprom_length,
 577         .get_eeprom           = ixgbe_get_eeprom,
 578         .set_eeprom           = ixgbe_set_eeprom,
 579         .get_module_info      = ixgbe_get_module_info,
 580         .get_module_eeprom    = ixgbe_get_module_eeprom,
 581         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 582         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 583         .timesync_read_time   = ixgbe_timesync_read_time,
 584         .timesync_write_time  = ixgbe_timesync_write_time,
 585         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 586         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 587         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 588         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 589         .tm_ops_get           = ixgbe_tm_ops_get,
 590         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 591 };
 592
 593 /*
 594  * dev_ops for virtual function, bare necessities for basic vf
 595  * operation have been implemented
 596  */
 597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 598         .dev_configure        = ixgbevf_dev_configure,
 599         .dev_start            = ixgbevf_dev_start,
 600         .dev_stop             = ixgbevf_dev_stop,
 601         .link_update          = ixgbevf_dev_link_update,
 602         .stats_get            = ixgbevf_dev_stats_get,
 603         .xstats_get           = ixgbevf_dev_xstats_get,
 604         .stats_reset          = ixgbevf_dev_stats_reset,
 605         .xstats_reset         = ixgbevf_dev_stats_reset,
 606         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 607         .dev_close            = ixgbevf_dev_close,
 608         .dev_reset            = ixgbevf_dev_reset,
 609         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 610         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 611         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 612         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 613         .dev_infos_get        = ixgbevf_dev_info_get,
 614         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 615         .mtu_set              = ixgbevf_dev_set_mtu,
 616         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 617         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 618         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 619         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 620         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 621         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 622         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 623         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 624         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 625         .mac_addr_add         = ixgbevf_add_mac_addr,
 626         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 627         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 628         .rxq_info_get         = ixgbe_rxq_info_get,
 629         .txq_info_get         = ixgbe_txq_info_get,
 630         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 631         .get_reg              = ixgbevf_get_regs,
 632         .reta_update          = ixgbe_dev_rss_reta_update,
 633         .reta_query           = ixgbe_dev_rss_reta_query,
 634         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 635         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 636         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 637 };
 638
 639 /* store statistics names and its offset in stats structure */
 640 struct rte_ixgbe_xstats_name_off {
 641         char name[RTE_ETH_XSTATS_NAME_SIZE];
 642         unsigned offset;
 643 };
 644
 645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 646         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 647         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 648         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 649         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 650         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 651         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 652         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 653         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 654         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 655         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 656         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 657         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 658         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 659         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 660         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 661                 prc1023)},
 662         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 663                 prc1522)},
 664         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 665         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 666         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 667         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 668         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 669         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 670         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 671         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 672         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 673         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 674         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 675         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 676         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 677         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 678         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 679         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 680         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 ptc1023)},
 682         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 ptc1522)},
 684         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 685         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 686         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 687         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 688
 689         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirustat_add)},
 691         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirustat_remove)},
 693         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 694                 fdirfstat_fadd)},
 695         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 696                 fdirfstat_fremove)},
 697         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirmatch)},
 699         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirmiss)},
 701
 702         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 703         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 704         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 705                 fclast)},
 706         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 707         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 708         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 709         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 710         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 711                 fcoe_noddp)},
 712         {"rx_fcoe_no_direct_data_placement_ext_buff",
 713                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 714
 715         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxontxc)},
 717         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 718                 lxonrxc)},
 719         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 720                 lxofftxc)},
 721         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxoffrxc)},
 723         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 724 };
 725
 726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 727                            sizeof(rte_ixgbe_stats_strings[0]))
 728
 729 /* MACsec statistics */
 730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 731         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 out_pkts_untagged)},
 733         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 734                 out_pkts_encrypted)},
 735         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 736                 out_pkts_protected)},
 737         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 738                 out_octets_encrypted)},
 739         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 740                 out_octets_protected)},
 741         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_untagged)},
 743         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_badtag)},
 745         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_nosci)},
 747         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_unknownsci)},
 749         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 750                 in_octets_decrypted)},
 751         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 752                 in_octets_validated)},
 753         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unchecked)},
 755         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_delayed)},
 757         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_late)},
 759         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_ok)},
 761         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_invalid)},
 763         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_notvalid)},
 765         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unusedsa)},
 767         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_notusingsa)},
 769 };
 770
 771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 772                            sizeof(rte_ixgbe_macsec_strings[0]))
 773
 774 /* Per-queue statistics */
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 776         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 777         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 778         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 779         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 780 };
 781
 782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 783                            sizeof(rte_ixgbe_rxq_strings[0]))
 784 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 787         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 788         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 789         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 790                 pxon2offc)},
 791 };
 792
 793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 794                            sizeof(rte_ixgbe_txq_strings[0]))
 795 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 798         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 799 };
 800
 801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 802                 sizeof(rte_ixgbevf_stats_strings[0]))
 803
 804 /*
 805  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 806  */
 807 static inline int
 808 ixgbe_is_sfp(struct ixgbe_hw *hw)
 809 {
 810         switch (hw->phy.type) {
 811         case ixgbe_phy_sfp_avago:
 812         case ixgbe_phy_sfp_ftl:
 813         case ixgbe_phy_sfp_intel:
 814         case ixgbe_phy_sfp_unknown:
 815         case ixgbe_phy_sfp_passive_tyco:
 816         case ixgbe_phy_sfp_passive_unknown:
 817                 return 1;
 818         default:
 819                 return 0;
 820         }
 821 }
 822
 823 static inline int32_t
 824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 825 {
 826         uint32_t ctrl_ext;
 827         int32_t status;
 828
 829         status = ixgbe_reset_hw(hw);
 830
 831         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 832         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 833         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 834         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 835         IXGBE_WRITE_FLUSH(hw);
 836
 837         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 838                 status = IXGBE_SUCCESS;
 839         return status;
 840 }
 841
 842 static inline void
 843 ixgbe_enable_intr(struct rte_eth_dev *dev)
 844 {
 845         struct ixgbe_interrupt *intr =
 846                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 847         struct ixgbe_hw *hw =
 848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 849
 850         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 851         IXGBE_WRITE_FLUSH(hw);
 852 }
 853
 854 /*
 855  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 856  */
 857 static void
 858 ixgbe_disable_intr(struct ixgbe_hw *hw)
 859 {
 860         PMD_INIT_FUNC_TRACE();
 861
 862         if (hw->mac.type == ixgbe_mac_82598EB) {
 863                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 864         } else {
 865                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 866                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 867                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 868         }
 869         IXGBE_WRITE_FLUSH(hw);
 870 }
 871
 872 /*
 873  * This function resets queue statistics mapping registers.
 874  * From Niantic datasheet, Initialization of Statistics section:
 875  * "...if software requires the queue counters, the RQSMR and TQSM registers
 876  * must be re-programmed following a device reset.
 877  */
 878 static void
 879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 880 {
 881         uint32_t i;
 882
 883         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 884                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 885                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 886         }
 887 }
 888
 889
 890 static int
 891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 892                                   uint16_t queue_id,
 893                                   uint8_t stat_idx,
 894                                   uint8_t is_rx)
 895 {
 896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 897 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 899
 900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 901         struct ixgbe_stat_mapping_registers *stat_mappings =
 902                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 903         uint32_t qsmr_mask = 0;
 904         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 905         uint32_t q_map;
 906         uint8_t n, offset;
 907
 908         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 909                 (hw->mac.type != ixgbe_mac_X540) &&
 910                 (hw->mac.type != ixgbe_mac_X550) &&
 911                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 912                 (hw->mac.type != ixgbe_mac_X550EM_a))
 913                 return -ENOSYS;
 914
 915         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 916                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 917                      queue_id, stat_idx);
 918
 919         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 920         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 921                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 922                 return -EIO;
 923         }
 924         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 925
 926         /* Now clear any previous stat_idx set */
 927         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 928         if (!is_rx)
 929                 stat_mappings->tqsm[n] &= ~clearing_mask;
 930         else
 931                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 932
 933         q_map = (uint32_t)stat_idx;
 934         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 935         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 936         if (!is_rx)
 937                 stat_mappings->tqsm[n] |= qsmr_mask;
 938         else
 939                 stat_mappings->rqsmr[n] |= qsmr_mask;
 940
 941         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 942                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 943                      queue_id, stat_idx);
 944         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 945                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 946
 947         /* Now write the mapping in the appropriate register */
 948         if (is_rx) {
 949                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 950                              stat_mappings->rqsmr[n], n);
 951                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 952         } else {
 953                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 954                              stat_mappings->tqsm[n], n);
 955                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 956         }
 957         return 0;
 958 }
 959
 960 static void
 961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 962 {
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         int i;
 967
 968         /* write whatever was in stat mapping table to the NIC */
 969         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 970                 /* rx */
 971                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 972
 973                 /* tx */
 974                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 975         }
 976 }
 977
 978 static void
 979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 980 {
 981         uint8_t i;
 982         struct ixgbe_dcb_tc_config *tc;
 983         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 984
 985         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 986         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 987         for (i = 0; i < dcb_max_tc; i++) {
 988                 tc = &dcb_config->tc_config[i];
 989                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 990                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 991                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 992                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 993                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 994                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 995                 tc->pfc = ixgbe_dcb_pfc_disabled;
 996         }
 997
 998         /* Initialize default user to priority mapping, UPx->TC0 */
 999         tc = &dcb_config->tc_config[0];
1000         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1001         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1002         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1003                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1004                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1005         }
1006         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1007         dcb_config->pfc_mode_enable = false;
1008         dcb_config->vt_mode = true;
1009         dcb_config->round_robin_enable = false;
1010         /* support all DCB capabilities in 82599 */
1011         dcb_config->support.capabilities = 0xFF;
1012
1013         /*we only support 4 Tcs for X540, X550 */
1014         if (hw->mac.type == ixgbe_mac_X540 ||
1015                 hw->mac.type == ixgbe_mac_X550 ||
1016                 hw->mac.type == ixgbe_mac_X550EM_x ||
1017                 hw->mac.type == ixgbe_mac_X550EM_a) {
1018                 dcb_config->num_tcs.pg_tcs = 4;
1019                 dcb_config->num_tcs.pfc_tcs = 4;
1020         }
1021 }
1022
1023 /*
1024  * Ensure that all locks are released before first NVM or PHY access
1025  */
1026 static void
1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1028 {
1029         uint16_t mask;
1030
1031         /*
1032          * Phy lock should not fail in this early stage. If this is the case,
1033          * it is due to an improper exit of the application.
1034          * So force the release of the faulty lock. Release of common lock
1035          * is done automatically by swfw_sync function.
1036          */
1037         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1038         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1040         }
1041         ixgbe_release_swfw_semaphore(hw, mask);
1042
1043         /*
1044          * These ones are more tricky since they are common to all ports; but
1045          * swfw_sync retries last long enough (1s) to be almost sure that if
1046          * lock can not be taken it is due to an improper lock of the
1047          * semaphore.
1048          */
1049         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1050         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1051                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1052         }
1053         ixgbe_release_swfw_semaphore(hw, mask);
1054 }
1055
1056 /*
1057  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1058  * It returns 0 on success.
1059  */
1060 static int
1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1062 {
1063         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1064         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1065         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1066         struct ixgbe_hw *hw =
1067                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1068         struct ixgbe_vfta *shadow_vfta =
1069                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1070         struct ixgbe_hwstrip *hwstrip =
1071                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1072         struct ixgbe_dcb_config *dcb_config =
1073                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1074         struct ixgbe_filter_info *filter_info =
1075                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1076         struct ixgbe_bw_conf *bw_conf =
1077                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1078         uint32_t ctrl_ext;
1079         uint16_t csum;
1080         int diag, i;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         ixgbe_dev_macsec_setting_reset(eth_dev);
1085
1086         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1087         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1088         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1089         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1090         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1091         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1092         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1093         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1094
1095         /*
1096          * For secondary processes, we don't initialise any further as primary
1097          * has already done this work. Only check we don't need a different
1098          * RX and TX function.
1099          */
1100         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1101                 struct ixgbe_tx_queue *txq;
1102                 /* TX queue function in primary, set by last queue initialized
1103                  * Tx queue may not initialized by primary process
1104                  */
1105                 if (eth_dev->data->tx_queues) {
1106                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1107                         ixgbe_set_tx_function(eth_dev, txq);
1108                 } else {
1109                         /* Use default TX function if we get here */
1110                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1111                                      "Using default TX function.");
1112                 }
1113
1114                 ixgbe_set_rx_function(eth_dev);
1115
1116                 return 0;
1117         }
1118
1119         rte_atomic32_clear(&ad->link_thread_running);
1120         rte_eth_copy_pci_info(eth_dev, pci_dev);
1121
1122         /* Vendor and Device ID need to be set before init of shared code */
1123         hw->device_id = pci_dev->id.device_id;
1124         hw->vendor_id = pci_dev->id.vendor_id;
1125         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1126         hw->allow_unsupported_sfp = 1;
1127
1128         /* Initialize the shared code (base driver) */
1129 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1130         diag = ixgbe_bypass_init_shared_code(hw);
1131 #else
1132         diag = ixgbe_init_shared_code(hw);
1133 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1134
1135         if (diag != IXGBE_SUCCESS) {
1136                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1137                 return -EIO;
1138         }
1139
1140         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1141                 PMD_INIT_LOG(ERR, "\nERROR: "
1142                         "Firmware recovery mode detected. Limiting functionality.\n"
1143                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1144                         "User Guide for details on firmware recovery mode.");
1145                 return -EIO;
1146         }
1147
1148         /* pick up the PCI bus settings for reporting later */
1149         ixgbe_get_bus_info(hw);
1150
1151         /* Unlock any pending hardware semaphore */
1152         ixgbe_swfw_lock_reset(hw);
1153
1154 #ifdef RTE_LIBRTE_SECURITY
1155         /* Initialize security_ctx only for primary process*/
1156         if (ixgbe_ipsec_ctx_create(eth_dev))
1157                 return -ENOMEM;
1158 #endif
1159
1160         /* Initialize DCB configuration*/
1161         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1162         ixgbe_dcb_init(hw, dcb_config);
1163         /* Get Hardware Flow Control setting */
1164         hw->fc.requested_mode = ixgbe_fc_none;
1165         hw->fc.current_mode = ixgbe_fc_none;
1166         hw->fc.pause_time = IXGBE_FC_PAUSE;
1167         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1168                 hw->fc.low_water[i] = IXGBE_FC_LO;
1169                 hw->fc.high_water[i] = IXGBE_FC_HI;
1170         }
1171         hw->fc.send_xon = 1;
1172
1173         /* Make sure we have a good EEPROM before we read from it */
1174         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1175         if (diag != IXGBE_SUCCESS) {
1176                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1177                 return -EIO;
1178         }
1179
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181         diag = ixgbe_bypass_init_hw(hw);
1182 #else
1183         diag = ixgbe_init_hw(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1185
1186         /*
1187          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1188          * is called too soon after the kernel driver unbinding/binding occurs.
1189          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1190          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1191          * also called. See ixgbe_identify_phy_82599(). The reason for the
1192          * failure is not known, and only occuts when virtualisation features
1193          * are disabled in the bios. A delay of 100ms  was found to be enough by
1194          * trial-and-error, and is doubled to be safe.
1195          */
1196         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1197                 rte_delay_ms(200);
1198                 diag = ixgbe_init_hw(hw);
1199         }
1200
1201         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1202                 diag = IXGBE_SUCCESS;
1203
1204         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206                              "LOM.  Please be aware there may be issues associated "
1207                              "with your hardware.");
1208                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209                              "please contact your Intel or hardware representative "
1210                              "who provided you with this hardware.");
1211         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1213         if (diag) {
1214                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215                 return -EIO;
1216         }
1217
1218         /* Reset the hw statistics */
1219         ixgbe_dev_stats_reset(eth_dev);
1220
1221         /* disable interrupt */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset mappings for queue statistics hw counters*/
1225         ixgbe_reset_qstat_mappings(hw);
1226
1227         /* Allocate memory for storing MAC addresses */
1228         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1229                                                hw->mac.num_rar_entries, 0);
1230         if (eth_dev->data->mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %u bytes needed to store "
1233                              "MAC addresses",
1234                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1235                 return -ENOMEM;
1236         }
1237         /* Copy the permanent MAC address */
1238         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1239                         &eth_dev->data->mac_addrs[0]);
1240
1241         /* Allocate memory for storing hash filter MAC addresses */
1242         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1243                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1244         if (eth_dev->data->hash_mac_addrs == NULL) {
1245                 PMD_INIT_LOG(ERR,
1246                              "Failed to allocate %d bytes needed to store MAC addresses",
1247                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248                 return -ENOMEM;
1249         }
1250
1251         /* initialize the vfta */
1252         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1253
1254         /* initialize the hw strip bitmap*/
1255         memset(hwstrip, 0, sizeof(*hwstrip));
1256
1257         /* initialize PF if max_vfs not zero */
1258         ixgbe_pf_host_init(eth_dev);
1259
1260         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261         /* let hardware know driver is loaded */
1262         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266         IXGBE_WRITE_FLUSH(hw);
1267
1268         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type,
1271                              (int) hw->phy.sfp_type);
1272         else
1273                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274                              (int) hw->mac.type, (int) hw->phy.type);
1275
1276         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1278                      pci_dev->id.device_id);
1279
1280         rte_intr_callback_register(intr_handle,
1281                                    ixgbe_dev_interrupt_handler, eth_dev);
1282
1283         /* enable uio/vfio intr/eventfd mapping */
1284         rte_intr_enable(intr_handle);
1285
1286         /* enable support intr */
1287         ixgbe_enable_intr(eth_dev);
1288
1289         /* initialize filter info */
1290         memset(filter_info, 0,
1291                sizeof(struct ixgbe_filter_info));
1292
1293         /* initialize 5tuple filter list */
1294         TAILQ_INIT(&filter_info->fivetuple_list);
1295
1296         /* initialize flow director filter list & hash */
1297         ixgbe_fdir_filter_init(eth_dev);
1298
1299         /* initialize l2 tunnel filter list & hash */
1300         ixgbe_l2_tn_filter_init(eth_dev);
1301
1302         /* initialize flow filter lists */
1303         ixgbe_filterlist_init();
1304
1305         /* initialize bandwidth configuration info */
1306         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1307
1308         /* initialize Traffic Manager configuration */
1309         ixgbe_tm_conf_init(eth_dev);
1310
1311         return 0;
1312 }
1313
1314 static int
1315 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1316 {
1317         PMD_INIT_FUNC_TRACE();
1318
1319         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1320                 return 0;
1321
1322         ixgbe_dev_close(eth_dev);
1323
1324         return 0;
1325 }
1326
1327 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1328 {
1329         struct ixgbe_filter_info *filter_info =
1330                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1331         struct ixgbe_5tuple_filter *p_5tuple;
1332
1333         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1334                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1335                              p_5tuple,
1336                              entries);
1337                 rte_free(p_5tuple);
1338         }
1339         memset(filter_info->fivetuple_mask, 0,
1340                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1341
1342         return 0;
1343 }
1344
1345 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1346 {
1347         struct ixgbe_hw_fdir_info *fdir_info =
1348                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1349         struct ixgbe_fdir_filter *fdir_filter;
1350
1351                 if (fdir_info->hash_map)
1352                 rte_free(fdir_info->hash_map);
1353         if (fdir_info->hash_handle)
1354                 rte_hash_free(fdir_info->hash_handle);
1355
1356         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1357                 TAILQ_REMOVE(&fdir_info->fdir_list,
1358                              fdir_filter,
1359                              entries);
1360                 rte_free(fdir_filter);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct ixgbe_l2_tn_info *l2_tn_info =
1369                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1370         struct ixgbe_l2_tn_filter *l2_tn_filter;
1371
1372         if (l2_tn_info->hash_map)
1373                 rte_free(l2_tn_info->hash_map);
1374         if (l2_tn_info->hash_handle)
1375                 rte_hash_free(l2_tn_info->hash_handle);
1376
1377         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1378                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1379                              l2_tn_filter,
1380                              entries);
1381                 rte_free(l2_tn_filter);
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1388 {
1389         struct ixgbe_hw_fdir_info *fdir_info =
1390                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1391         char fdir_hash_name[RTE_HASH_NAMESIZE];
1392         struct rte_hash_parameters fdir_hash_params = {
1393                 .name = fdir_hash_name,
1394                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1395                 .key_len = sizeof(union ixgbe_atr_input),
1396                 .hash_func = rte_hash_crc,
1397                 .hash_func_init_val = 0,
1398                 .socket_id = rte_socket_id(),
1399         };
1400
1401         TAILQ_INIT(&fdir_info->fdir_list);
1402         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1403                  "fdir_%s", eth_dev->device->name);
1404         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1405         if (!fdir_info->hash_handle) {
1406                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1407                 return -EINVAL;
1408         }
1409         fdir_info->hash_map = rte_zmalloc("ixgbe",
1410                                           sizeof(struct ixgbe_fdir_filter *) *
1411                                           IXGBE_MAX_FDIR_FILTER_NUM,
1412                                           0);
1413         if (!fdir_info->hash_map) {
1414                 PMD_INIT_LOG(ERR,
1415                              "Failed to allocate memory for fdir hash map!");
1416                 return -ENOMEM;
1417         }
1418         fdir_info->mask_added = FALSE;
1419
1420         return 0;
1421 }
1422
1423 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1424 {
1425         struct ixgbe_l2_tn_info *l2_tn_info =
1426                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1427         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1428         struct rte_hash_parameters l2_tn_hash_params = {
1429                 .name = l2_tn_hash_name,
1430                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1431                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1432                 .hash_func = rte_hash_crc,
1433                 .hash_func_init_val = 0,
1434                 .socket_id = rte_socket_id(),
1435         };
1436
1437         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1438         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1439                  "l2_tn_%s", eth_dev->device->name);
1440         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1441         if (!l2_tn_info->hash_handle) {
1442                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1443                 return -EINVAL;
1444         }
1445         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1446                                    sizeof(struct ixgbe_l2_tn_filter *) *
1447                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1448                                    0);
1449         if (!l2_tn_info->hash_map) {
1450                 PMD_INIT_LOG(ERR,
1451                         "Failed to allocate memory for L2 TN hash map!");
1452                 return -ENOMEM;
1453         }
1454         l2_tn_info->e_tag_en = FALSE;
1455         l2_tn_info->e_tag_fwd_en = FALSE;
1456         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1457
1458         return 0;
1459 }
1460 /*
1461  * Negotiate mailbox API version with the PF.
1462  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1463  * Then we try to negotiate starting with the most recent one.
1464  * If all negotiation attempts fail, then we will proceed with
1465  * the default one (ixgbe_mbox_api_10).
1466  */
1467 static void
1468 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1469 {
1470         int32_t i;
1471
1472         /* start with highest supported, proceed down */
1473         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1474                 ixgbe_mbox_api_13,
1475                 ixgbe_mbox_api_12,
1476                 ixgbe_mbox_api_11,
1477                 ixgbe_mbox_api_10,
1478         };
1479
1480         for (i = 0;
1481                         i != RTE_DIM(sup_ver) &&
1482                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1483                         i++)
1484                 ;
1485 }
1486
1487 static void
1488 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1489 {
1490         uint64_t random;
1491
1492         /* Set Organizationally Unique Identifier (OUI) prefix. */
1493         mac_addr->addr_bytes[0] = 0x00;
1494         mac_addr->addr_bytes[1] = 0x09;
1495         mac_addr->addr_bytes[2] = 0xC0;
1496         /* Force indication of locally assigned MAC address. */
1497         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1498         /* Generate the last 3 bytes of the MAC address with a random number. */
1499         random = rte_rand();
1500         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1501 }
1502
1503 static int
1504 devarg_handle_int(__rte_unused const char *key, const char *value,
1505                   void *extra_args)
1506 {
1507         uint16_t *n = extra_args;
1508
1509         if (value == NULL || extra_args == NULL)
1510                 return -EINVAL;
1511
1512         *n = (uint16_t)strtoul(value, NULL, 0);
1513         if (*n == USHRT_MAX && errno == ERANGE)
1514                 return -1;
1515
1516         return 0;
1517 }
1518
1519 static void
1520 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1521                       struct rte_devargs *devargs)
1522 {
1523         struct rte_kvargs *kvlist;
1524         uint16_t pflink_fullchk;
1525
1526         if (devargs == NULL)
1527                 return;
1528
1529         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1530         if (kvlist == NULL)
1531                 return;
1532
1533         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1534             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1535                                devarg_handle_int, &pflink_fullchk) == 0 &&
1536             pflink_fullchk == 1)
1537                 adapter->pflink_fullchk = 1;
1538
1539         rte_kvargs_free(kvlist);
1540 }
1541
1542 /*
1543  * Virtual Function device init
1544  */
1545 static int
1546 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1547 {
1548         int diag;
1549         uint32_t tc, tcs;
1550         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1551         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1552         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1553         struct ixgbe_hw *hw =
1554                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1555         struct ixgbe_vfta *shadow_vfta =
1556                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1557         struct ixgbe_hwstrip *hwstrip =
1558                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1559         struct rte_ether_addr *perm_addr =
1560                 (struct rte_ether_addr *)hw->mac.perm_addr;
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1565         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1566         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1567         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1568         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1569         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1570
1571         /* for secondary processes, we don't initialise any further as primary
1572          * has already done this work. Only check we don't need a different
1573          * RX function
1574          */
1575         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1576                 struct ixgbe_tx_queue *txq;
1577                 /* TX queue function in primary, set by last queue initialized
1578                  * Tx queue may not initialized by primary process
1579                  */
1580                 if (eth_dev->data->tx_queues) {
1581                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1582                         ixgbe_set_tx_function(eth_dev, txq);
1583                 } else {
1584                         /* Use default TX function if we get here */
1585                         PMD_INIT_LOG(NOTICE,
1586                                      "No TX queues configured yet. Using default TX function.");
1587                 }
1588
1589                 ixgbe_set_rx_function(eth_dev);
1590
1591                 return 0;
1592         }
1593
1594         rte_atomic32_clear(&ad->link_thread_running);
1595         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1596                               pci_dev->device.devargs);
1597
1598         rte_eth_copy_pci_info(eth_dev, pci_dev);
1599
1600         hw->device_id = pci_dev->id.device_id;
1601         hw->vendor_id = pci_dev->id.vendor_id;
1602         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1603
1604         /* initialize the vfta */
1605         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1606
1607         /* initialize the hw strip bitmap*/
1608         memset(hwstrip, 0, sizeof(*hwstrip));
1609
1610         /* Initialize the shared code (base driver) */
1611         diag = ixgbe_init_shared_code(hw);
1612         if (diag != IXGBE_SUCCESS) {
1613                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1614                 return -EIO;
1615         }
1616
1617         /* init_mailbox_params */
1618         hw->mbx.ops.init_params(hw);
1619
1620         /* Reset the hw statistics */
1621         ixgbevf_dev_stats_reset(eth_dev);
1622
1623         /* Disable the interrupts for VF */
1624         ixgbevf_intr_disable(eth_dev);
1625
1626         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1627         diag = hw->mac.ops.reset_hw(hw);
1628
1629         /*
1630          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1631          * the underlying PF driver has not assigned a MAC address to the VF.
1632          * In this case, assign a random MAC address.
1633          */
1634         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1635                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1636                 /*
1637                  * This error code will be propagated to the app by
1638                  * rte_eth_dev_reset, so use a public error code rather than
1639                  * the internal-only IXGBE_ERR_RESET_FAILED
1640                  */
1641                 return -EAGAIN;
1642         }
1643
1644         /* negotiate mailbox API version to use with the PF. */
1645         ixgbevf_negotiate_api(hw);
1646
1647         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1648         ixgbevf_get_queues(hw, &tcs, &tc);
1649
1650         /* Allocate memory for storing MAC addresses */
1651         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1652                                                hw->mac.num_rar_entries, 0);
1653         if (eth_dev->data->mac_addrs == NULL) {
1654                 PMD_INIT_LOG(ERR,
1655                              "Failed to allocate %u bytes needed to store "
1656                              "MAC addresses",
1657                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1658                 return -ENOMEM;
1659         }
1660
1661         /* Generate a random MAC address, if none was assigned by PF. */
1662         if (rte_is_zero_ether_addr(perm_addr)) {
1663                 generate_random_mac_addr(perm_addr);
1664                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1665                 if (diag) {
1666                         rte_free(eth_dev->data->mac_addrs);
1667                         eth_dev->data->mac_addrs = NULL;
1668                         return diag;
1669                 }
1670                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1671                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1672                              "%02x:%02x:%02x:%02x:%02x:%02x",
1673                              perm_addr->addr_bytes[0],
1674                              perm_addr->addr_bytes[1],
1675                              perm_addr->addr_bytes[2],
1676                              perm_addr->addr_bytes[3],
1677                              perm_addr->addr_bytes[4],
1678                              perm_addr->addr_bytes[5]);
1679         }
1680
1681         /* Copy the permanent MAC address */
1682         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1683
1684         /* reset the hardware with the new settings */
1685         diag = hw->mac.ops.start_hw(hw);
1686         switch (diag) {
1687         case  0:
1688                 break;
1689
1690         default:
1691                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1692                 return -EIO;
1693         }
1694
1695         rte_intr_callback_register(intr_handle,
1696                                    ixgbevf_dev_interrupt_handler, eth_dev);
1697         rte_intr_enable(intr_handle);
1698         ixgbevf_intr_enable(eth_dev);
1699
1700         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1701                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1702                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1703
1704         return 0;
1705 }
1706
1707 /* Virtual Function device uninit */
1708
1709 static int
1710 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1711 {
1712         PMD_INIT_FUNC_TRACE();
1713
1714         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1715                 return 0;
1716
1717         ixgbevf_dev_close(eth_dev);
1718
1719         return 0;
1720 }
1721
1722 static int
1723 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1724                 struct rte_pci_device *pci_dev)
1725 {
1726         char name[RTE_ETH_NAME_MAX_LEN];
1727         struct rte_eth_dev *pf_ethdev;
1728         struct rte_eth_devargs eth_da;
1729         int i, retval;
1730
1731         if (pci_dev->device.devargs) {
1732                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1733                                 &eth_da);
1734                 if (retval)
1735                         return retval;
1736         } else
1737                 memset(&eth_da, 0, sizeof(eth_da));
1738
1739         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1740                 sizeof(struct ixgbe_adapter),
1741                 eth_dev_pci_specific_init, pci_dev,
1742                 eth_ixgbe_dev_init, NULL);
1743
1744         if (retval || eth_da.nb_representor_ports < 1)
1745                 return retval;
1746
1747         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1748         if (pf_ethdev == NULL)
1749                 return -ENODEV;
1750
1751         /* probe VF representor ports */
1752         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1753                 struct ixgbe_vf_info *vfinfo;
1754                 struct ixgbe_vf_representor representor;
1755
1756                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1757                         pf_ethdev->data->dev_private);
1758                 if (vfinfo == NULL) {
1759                         PMD_DRV_LOG(ERR,
1760                                 "no virtual functions supported by PF");
1761                         break;
1762                 }
1763
1764                 representor.vf_id = eth_da.representor_ports[i];
1765                 representor.switch_domain_id = vfinfo->switch_domain_id;
1766                 representor.pf_ethdev = pf_ethdev;
1767
1768                 /* representor port net_bdf_port */
1769                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1770                         pci_dev->device.name,
1771                         eth_da.representor_ports[i]);
1772
1773                 retval = rte_eth_dev_create(&pci_dev->device, name,
1774                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1775                         ixgbe_vf_representor_init, &representor);
1776
1777                 if (retval)
1778                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1779                                 "representor %s.", name);
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1786 {
1787         struct rte_eth_dev *ethdev;
1788
1789         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1790         if (!ethdev)
1791                 return 0;
1792
1793         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1794                 return rte_eth_dev_pci_generic_remove(pci_dev,
1795                                         ixgbe_vf_representor_uninit);
1796         else
1797                 return rte_eth_dev_pci_generic_remove(pci_dev,
1798                                                 eth_ixgbe_dev_uninit);
1799 }
1800
1801 static struct rte_pci_driver rte_ixgbe_pmd = {
1802         .id_table = pci_id_ixgbe_map,
1803         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1804         .probe = eth_ixgbe_pci_probe,
1805         .remove = eth_ixgbe_pci_remove,
1806 };
1807
1808 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1809         struct rte_pci_device *pci_dev)
1810 {
1811         return rte_eth_dev_pci_generic_probe(pci_dev,
1812                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1813 }
1814
1815 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1816 {
1817         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1818 }
1819
1820 /*
1821  * virtual function driver struct
1822  */
1823 static struct rte_pci_driver rte_ixgbevf_pmd = {
1824         .id_table = pci_id_ixgbevf_map,
1825         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1826         .probe = eth_ixgbevf_pci_probe,
1827         .remove = eth_ixgbevf_pci_remove,
1828 };
1829
1830 static int
1831 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1832 {
1833         struct ixgbe_hw *hw =
1834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct ixgbe_vfta *shadow_vfta =
1836                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1837         uint32_t vfta;
1838         uint32_t vid_idx;
1839         uint32_t vid_bit;
1840
1841         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1842         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1843         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1844         if (on)
1845                 vfta |= vid_bit;
1846         else
1847                 vfta &= ~vid_bit;
1848         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1849
1850         /* update local VFTA copy */
1851         shadow_vfta->vfta[vid_idx] = vfta;
1852
1853         return 0;
1854 }
1855
1856 static void
1857 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1858 {
1859         if (on)
1860                 ixgbe_vlan_hw_strip_enable(dev, queue);
1861         else
1862                 ixgbe_vlan_hw_strip_disable(dev, queue);
1863 }
1864
1865 static int
1866 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1867                     enum rte_vlan_type vlan_type,
1868                     uint16_t tpid)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         int ret = 0;
1873         uint32_t reg;
1874         uint32_t qinq;
1875
1876         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1877         qinq &= IXGBE_DMATXCTL_GDV;
1878
1879         switch (vlan_type) {
1880         case ETH_VLAN_TYPE_INNER:
1881                 if (qinq) {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 } else {
1890                         ret = -ENOTSUP;
1891                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1892                                     " by single VLAN");
1893                 }
1894                 break;
1895         case ETH_VLAN_TYPE_OUTER:
1896                 if (qinq) {
1897                         /* Only the high 16-bits is valid */
1898                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1899                                         IXGBE_EXVET_VET_EXT_SHIFT);
1900                 } else {
1901                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1903                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1904                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1905                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1906                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1907                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1908                 }
1909
1910                 break;
1911         default:
1912                 ret = -EINVAL;
1913                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1914                 break;
1915         }
1916
1917         return ret;
1918 }
1919
1920 void
1921 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1922 {
1923         struct ixgbe_hw *hw =
1924                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925         uint32_t vlnctrl;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Disable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1932
1933         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1934 }
1935
1936 void
1937 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct ixgbe_vfta *shadow_vfta =
1942                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1943         uint32_t vlnctrl;
1944         uint16_t i;
1945
1946         PMD_INIT_FUNC_TRACE();
1947
1948         /* Filter Table Enable */
1949         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1950         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1951         vlnctrl |= IXGBE_VLNCTRL_VFE;
1952
1953         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954
1955         /* write whatever is in local vfta copy */
1956         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1957                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1958 }
1959
1960 static void
1961 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1962 {
1963         struct ixgbe_hwstrip *hwstrip =
1964                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1965         struct ixgbe_rx_queue *rxq;
1966
1967         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1968                 return;
1969
1970         if (on)
1971                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1972         else
1973                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1974
1975         if (queue >= dev->data->nb_rx_queues)
1976                 return;
1977
1978         rxq = dev->data->rx_queues[queue];
1979
1980         if (on) {
1981                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1982                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1983         } else {
1984                 rxq->vlan_flags = PKT_RX_VLAN;
1985                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1986         }
1987 }
1988
1989 static void
1990 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1991 {
1992         struct ixgbe_hw *hw =
1993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994         uint32_t ctrl;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         if (hw->mac.type == ixgbe_mac_82598EB) {
1999                 /* No queue level support */
2000                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2001                 return;
2002         }
2003
2004         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2005         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2006         ctrl &= ~IXGBE_RXDCTL_VME;
2007         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2008
2009         /* record those setting for HW strip per queue */
2010         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2011 }
2012
2013 static void
2014 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2015 {
2016         struct ixgbe_hw *hw =
2017                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         uint32_t ctrl;
2019
2020         PMD_INIT_FUNC_TRACE();
2021
2022         if (hw->mac.type == ixgbe_mac_82598EB) {
2023                 /* No queue level supported */
2024                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2025                 return;
2026         }
2027
2028         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2029         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2030         ctrl |= IXGBE_RXDCTL_VME;
2031         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2032
2033         /* record those setting for HW strip per queue */
2034         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2035 }
2036
2037 static void
2038 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2039 {
2040         struct ixgbe_hw *hw =
2041                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042         uint32_t ctrl;
2043
2044         PMD_INIT_FUNC_TRACE();
2045
2046         /* DMATXCTRL: Geric Double VLAN Disable */
2047         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2048         ctrl &= ~IXGBE_DMATXCTL_GDV;
2049         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2050
2051         /* CTRL_EXT: Global Double VLAN Disable */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2053         ctrl &= ~IXGBE_EXTENDED_VLAN;
2054         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2055
2056 }
2057
2058 static void
2059 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t ctrl;
2064
2065         PMD_INIT_FUNC_TRACE();
2066
2067         /* DMATXCTRL: Geric Double VLAN Enable */
2068         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2069         ctrl |= IXGBE_DMATXCTL_GDV;
2070         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2071
2072         /* CTRL_EXT: Global Double VLAN Enable */
2073         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2074         ctrl |= IXGBE_EXTENDED_VLAN;
2075         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2076
2077         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2078         if (hw->mac.type == ixgbe_mac_X550 ||
2079             hw->mac.type == ixgbe_mac_X550EM_x ||
2080             hw->mac.type == ixgbe_mac_X550EM_a) {
2081                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2082                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2083                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2084         }
2085
2086         /*
2087          * VET EXT field in the EXVET register = 0x8100 by default
2088          * So no need to change. Same to VT field of DMATXCTL register
2089          */
2090 }
2091
2092 void
2093 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2094 {
2095         struct ixgbe_hw *hw =
2096                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2098         uint32_t ctrl;
2099         uint16_t i;
2100         struct ixgbe_rx_queue *rxq;
2101         bool on;
2102
2103         PMD_INIT_FUNC_TRACE();
2104
2105         if (hw->mac.type == ixgbe_mac_82598EB) {
2106                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2107                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2108                         ctrl |= IXGBE_VLNCTRL_VME;
2109                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2110                 } else {
2111                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2112                         ctrl &= ~IXGBE_VLNCTRL_VME;
2113                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2114                 }
2115         } else {
2116                 /*
2117                  * Other 10G NIC, the VLAN strip can be setup
2118                  * per queue in RXDCTL
2119                  */
2120                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2121                         rxq = dev->data->rx_queues[i];
2122                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2123                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2124                                 ctrl |= IXGBE_RXDCTL_VME;
2125                                 on = TRUE;
2126                         } else {
2127                                 ctrl &= ~IXGBE_RXDCTL_VME;
2128                                 on = FALSE;
2129                         }
2130                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2131
2132                         /* record those setting for HW strip per queue */
2133                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2134                 }
2135         }
2136 }
2137
2138 static void
2139 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2140 {
2141         uint16_t i;
2142         struct rte_eth_rxmode *rxmode;
2143         struct ixgbe_rx_queue *rxq;
2144
2145         if (mask & ETH_VLAN_STRIP_MASK) {
2146                 rxmode = &dev->data->dev_conf.rxmode;
2147                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2148                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2149                                 rxq = dev->data->rx_queues[i];
2150                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2151                         }
2152                 else
2153                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2154                                 rxq = dev->data->rx_queues[i];
2155                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2156                         }
2157         }
2158 }
2159
2160 static int
2161 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2162 {
2163         struct rte_eth_rxmode *rxmode;
2164         rxmode = &dev->data->dev_conf.rxmode;
2165
2166         if (mask & ETH_VLAN_STRIP_MASK) {
2167                 ixgbe_vlan_hw_strip_config(dev);
2168         }
2169
2170         if (mask & ETH_VLAN_FILTER_MASK) {
2171                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2172                         ixgbe_vlan_hw_filter_enable(dev);
2173                 else
2174                         ixgbe_vlan_hw_filter_disable(dev);
2175         }
2176
2177         if (mask & ETH_VLAN_EXTEND_MASK) {
2178                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2179                         ixgbe_vlan_hw_extend_enable(dev);
2180                 else
2181                         ixgbe_vlan_hw_extend_disable(dev);
2182         }
2183
2184         return 0;
2185 }
2186
2187 static int
2188 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2189 {
2190         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2191
2192         ixgbe_vlan_offload_config(dev, mask);
2193
2194         return 0;
2195 }
2196
2197 static void
2198 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2199 {
2200         struct ixgbe_hw *hw =
2201                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2203         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2204
2205         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2206         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2207 }
2208
2209 static int
2210 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2211 {
2212         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2213
2214         switch (nb_rx_q) {
2215         case 1:
2216         case 2:
2217                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2218                 break;
2219         case 4:
2220                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2221                 break;
2222         default:
2223                 return -EINVAL;
2224         }
2225
2226         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2227                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2228         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2229                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2230         return 0;
2231 }
2232
2233 static int
2234 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2235 {
2236         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2239         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2240
2241         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2242                 /* check multi-queue mode */
2243                 switch (dev_conf->rxmode.mq_mode) {
2244                 case ETH_MQ_RX_VMDQ_DCB:
2245                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2246                         break;
2247                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2248                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2249                         PMD_INIT_LOG(ERR, "SRIOV active,"
2250                                         " unsupported mq_mode rx %d.",
2251                                         dev_conf->rxmode.mq_mode);
2252                         return -EINVAL;
2253                 case ETH_MQ_RX_RSS:
2254                 case ETH_MQ_RX_VMDQ_RSS:
2255                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2256                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2257                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2258                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2259                                                 " invalid queue number"
2260                                                 " for VMDQ RSS, allowed"
2261                                                 " value are 1, 2 or 4.");
2262                                         return -EINVAL;
2263                                 }
2264                         break;
2265                 case ETH_MQ_RX_VMDQ_ONLY:
2266                 case ETH_MQ_RX_NONE:
2267                         /* if nothing mq mode configure, use default scheme */
2268                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2269                         break;
2270                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2271                         /* SRIOV only works in VMDq enable mode */
2272                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2273                                         " wrong mq_mode rx %d.",
2274                                         dev_conf->rxmode.mq_mode);
2275                         return -EINVAL;
2276                 }
2277
2278                 switch (dev_conf->txmode.mq_mode) {
2279                 case ETH_MQ_TX_VMDQ_DCB:
2280                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2281                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2282                         break;
2283                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2284                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2285                         break;
2286                 }
2287
2288                 /* check valid queue number */
2289                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2290                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2291                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2292                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2293                                         " must be less than or equal to %d.",
2294                                         nb_rx_q, nb_tx_q,
2295                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2296                         return -EINVAL;
2297                 }
2298         } else {
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2300                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2301                                           " not supported.");
2302                         return -EINVAL;
2303                 }
2304                 /* check configuration for vmdb+dcb mode */
2305                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2306                         const struct rte_eth_vmdq_dcb_conf *conf;
2307
2308                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2309                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2310                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2311                                 return -EINVAL;
2312                         }
2313                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2314                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2315                                conf->nb_queue_pools == ETH_32_POOLS)) {
2316                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2317                                                 " nb_queue_pools must be %d or %d.",
2318                                                 ETH_16_POOLS, ETH_32_POOLS);
2319                                 return -EINVAL;
2320                         }
2321                 }
2322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2323                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2324
2325                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2327                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2331                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2332                                conf->nb_queue_pools == ETH_32_POOLS)) {
2333                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2334                                                 " nb_queue_pools != %d and"
2335                                                 " nb_queue_pools != %d.",
2336                                                 ETH_16_POOLS, ETH_32_POOLS);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340
2341                 /* For DCB mode check our configuration before we go further */
2342                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2343                         const struct rte_eth_dcb_rx_conf *conf;
2344
2345                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2346                         if (!(conf->nb_tcs == ETH_4_TCS ||
2347                                conf->nb_tcs == ETH_8_TCS)) {
2348                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2349                                                 " and nb_tcs != %d.",
2350                                                 ETH_4_TCS, ETH_8_TCS);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354
2355                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2356                         const struct rte_eth_dcb_tx_conf *conf;
2357
2358                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2359                         if (!(conf->nb_tcs == ETH_4_TCS ||
2360                                conf->nb_tcs == ETH_8_TCS)) {
2361                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2362                                                 " and nb_tcs != %d.",
2363                                                 ETH_4_TCS, ETH_8_TCS);
2364                                 return -EINVAL;
2365                         }
2366                 }
2367
2368                 /*
2369                  * When DCB/VT is off, maximum number of queues changes,
2370                  * except for 82598EB, which remains constant.
2371                  */
2372                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2373                                 hw->mac.type != ixgbe_mac_82598EB) {
2374                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2375                                 PMD_INIT_LOG(ERR,
2376                                              "Neither VT nor DCB are enabled, "
2377                                              "nb_tx_q > %d.",
2378                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2379                                 return -EINVAL;
2380                         }
2381                 }
2382         }
2383         return 0;
2384 }
2385
2386 static int
2387 ixgbe_dev_configure(struct rte_eth_dev *dev)
2388 {
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         struct ixgbe_adapter *adapter = dev->data->dev_private;
2392         int ret;
2393
2394         PMD_INIT_FUNC_TRACE();
2395
2396         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2397                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2398
2399         /* multipe queue mode checking */
2400         ret  = ixgbe_check_mq_mode(dev);
2401         if (ret != 0) {
2402                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2403                             ret);
2404                 return ret;
2405         }
2406
2407         /* set flag to update link status after init */
2408         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2409
2410         /*
2411          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2412          * allocation or vector Rx preconditions we will reset it.
2413          */
2414         adapter->rx_bulk_alloc_allowed = true;
2415         adapter->rx_vec_allowed = true;
2416
2417         return 0;
2418 }
2419
2420 static void
2421 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2422 {
2423         struct ixgbe_hw *hw =
2424                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         struct ixgbe_interrupt *intr =
2426                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2427         uint32_t gpie;
2428
2429         /* only set up it on X550EM_X */
2430         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2431                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2432                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2433                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2434                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2435                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2436         }
2437 }
2438
2439 int
2440 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2441                         uint16_t tx_rate, uint64_t q_msk)
2442 {
2443         struct ixgbe_hw *hw;
2444         struct ixgbe_vf_info *vfinfo;
2445         struct rte_eth_link link;
2446         uint8_t  nb_q_per_pool;
2447         uint32_t queue_stride;
2448         uint32_t queue_idx, idx = 0, vf_idx;
2449         uint32_t queue_end;
2450         uint16_t total_rate = 0;
2451         struct rte_pci_device *pci_dev;
2452         int ret;
2453
2454         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2455         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2456         if (ret < 0)
2457                 return ret;
2458
2459         if (vf >= pci_dev->max_vfs)
2460                 return -EINVAL;
2461
2462         if (tx_rate > link.link_speed)
2463                 return -EINVAL;
2464
2465         if (q_msk == 0)
2466                 return 0;
2467
2468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2470         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2471         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2472         queue_idx = vf * queue_stride;
2473         queue_end = queue_idx + nb_q_per_pool - 1;
2474         if (queue_end >= hw->mac.max_tx_queues)
2475                 return -EINVAL;
2476
2477         if (vfinfo) {
2478                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2479                         if (vf_idx == vf)
2480                                 continue;
2481                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2482                                 idx++)
2483                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2484                 }
2485         } else {
2486                 return -EINVAL;
2487         }
2488
2489         /* Store tx_rate for this vf. */
2490         for (idx = 0; idx < nb_q_per_pool; idx++) {
2491                 if (((uint64_t)0x1 << idx) & q_msk) {
2492                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2493                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2494                         total_rate += tx_rate;
2495                 }
2496         }
2497
2498         if (total_rate > dev->data->dev_link.link_speed) {
2499                 /* Reset stored TX rate of the VF if it causes exceed
2500                  * link speed.
2501                  */
2502                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2503                 return -EINVAL;
2504         }
2505
2506         /* Set RTTBCNRC of each queue/pool for vf X  */
2507         for (; queue_idx <= queue_end; queue_idx++) {
2508                 if (0x1 & q_msk)
2509                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2510                 q_msk = q_msk >> 1;
2511         }
2512
2513         return 0;
2514 }
2515
2516 static int
2517 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2518 {
2519         struct ixgbe_adapter *adapter = dev->data->dev_private;
2520         int err;
2521         uint32_t mflcn;
2522
2523         ixgbe_setup_fc(hw);
2524
2525         err = ixgbe_fc_enable(hw);
2526
2527         /* Not negotiated is not an error case */
2528         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2529                 /*
2530                  *check if we want to forward MAC frames - driver doesn't
2531                  *have native capability to do that,
2532                  *so we'll write the registers ourselves
2533                  */
2534
2535                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2536
2537                 /* set or clear MFLCN.PMCF bit depending on configuration */
2538                 if (adapter->mac_ctrl_frame_fwd != 0)
2539                         mflcn |= IXGBE_MFLCN_PMCF;
2540                 else
2541                         mflcn &= ~IXGBE_MFLCN_PMCF;
2542
2543                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2544                 IXGBE_WRITE_FLUSH(hw);
2545
2546                 return 0;
2547         }
2548         return err;
2549 }
2550
2551 /*
2552  * Configure device link speed and setup link.
2553  * It returns 0 on success.
2554  */
2555 static int
2556 ixgbe_dev_start(struct rte_eth_dev *dev)
2557 {
2558         struct ixgbe_hw *hw =
2559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560         struct ixgbe_vf_info *vfinfo =
2561                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2564         uint32_t intr_vector = 0;
2565         int err;
2566         bool link_up = false, negotiate = 0;
2567         uint32_t speed = 0;
2568         uint32_t allowed_speeds = 0;
2569         int mask = 0;
2570         int status;
2571         uint16_t vf, idx;
2572         uint32_t *link_speeds;
2573         struct ixgbe_tm_conf *tm_conf =
2574                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2575         struct ixgbe_macsec_setting *macsec_setting =
2576                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2577
2578         PMD_INIT_FUNC_TRACE();
2579
2580         /* Stop the link setup handler before resetting the HW. */
2581         ixgbe_dev_wait_setup_link_complete(dev, 0);
2582
2583         /* disable uio/vfio intr/eventfd mapping */
2584         rte_intr_disable(intr_handle);
2585
2586         /* stop adapter */
2587         hw->adapter_stopped = 0;
2588         ixgbe_stop_adapter(hw);
2589
2590         /* reinitialize adapter
2591          * this calls reset and start
2592          */
2593         status = ixgbe_pf_reset_hw(hw);
2594         if (status != 0)
2595                 return -1;
2596         hw->mac.ops.start_hw(hw);
2597         hw->mac.get_link_status = true;
2598
2599         /* configure PF module if SRIOV enabled */
2600         ixgbe_pf_host_configure(dev);
2601
2602         ixgbe_dev_phy_intr_setup(dev);
2603
2604         /* check and configure queue intr-vector mapping */
2605         if ((rte_intr_cap_multiple(intr_handle) ||
2606              !RTE_ETH_DEV_SRIOV(dev).active) &&
2607             dev->data->dev_conf.intr_conf.rxq != 0) {
2608                 intr_vector = dev->data->nb_rx_queues;
2609                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2610                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2611                                         IXGBE_MAX_INTR_QUEUE_NUM);
2612                         return -ENOTSUP;
2613                 }
2614                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2615                         return -1;
2616         }
2617
2618         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2619                 intr_handle->intr_vec =
2620                         rte_zmalloc("intr_vec",
2621                                     dev->data->nb_rx_queues * sizeof(int), 0);
2622                 if (intr_handle->intr_vec == NULL) {
2623                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2624                                      " intr_vec", dev->data->nb_rx_queues);
2625                         return -ENOMEM;
2626                 }
2627         }
2628
2629         /* confiugre msix for sleep until rx interrupt */
2630         ixgbe_configure_msix(dev);
2631
2632         /* initialize transmission unit */
2633         ixgbe_dev_tx_init(dev);
2634
2635         /* This can fail when allocating mbufs for descriptor rings */
2636         err = ixgbe_dev_rx_init(dev);
2637         if (err) {
2638                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2639                 goto error;
2640         }
2641
2642         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2643                 ETH_VLAN_EXTEND_MASK;
2644         err = ixgbe_vlan_offload_config(dev, mask);
2645         if (err) {
2646                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2647                 goto error;
2648         }
2649
2650         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2651                 /* Enable vlan filtering for VMDq */
2652                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2653         }
2654
2655         /* Configure DCB hw */
2656         ixgbe_configure_dcb(dev);
2657
2658         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2659                 err = ixgbe_fdir_configure(dev);
2660                 if (err)
2661                         goto error;
2662         }
2663
2664         /* Restore vf rate limit */
2665         if (vfinfo != NULL) {
2666                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2667                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2668                                 if (vfinfo[vf].tx_rate[idx] != 0)
2669                                         ixgbe_set_vf_rate_limit(
2670                                                 dev, vf,
2671                                                 vfinfo[vf].tx_rate[idx],
2672                                                 1 << idx);
2673         }
2674
2675         ixgbe_restore_statistics_mapping(dev);
2676
2677         err = ixgbe_flow_ctrl_enable(dev, hw);
2678         if (err < 0) {
2679                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2680                 goto error;
2681         }
2682
2683         err = ixgbe_dev_rxtx_start(dev);
2684         if (err < 0) {
2685                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2686                 goto error;
2687         }
2688
2689         /* Skip link setup if loopback mode is enabled. */
2690         if (dev->data->dev_conf.lpbk_mode != 0) {
2691                 err = ixgbe_check_supported_loopback_mode(dev);
2692                 if (err < 0) {
2693                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2694                         goto error;
2695                 } else {
2696                         goto skip_link_setup;
2697                 }
2698         }
2699
2700         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2701                 err = hw->mac.ops.setup_sfp(hw);
2702                 if (err)
2703                         goto error;
2704         }
2705
2706         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2707                 /* Turn on the copper */
2708                 ixgbe_set_phy_power(hw, true);
2709         } else {
2710                 /* Turn on the laser */
2711                 ixgbe_enable_tx_laser(hw);
2712         }
2713
2714         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2715         if (err)
2716                 goto error;
2717         dev->data->dev_link.link_status = link_up;
2718
2719         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2720         if (err)
2721                 goto error;
2722
2723         switch (hw->mac.type) {
2724         case ixgbe_mac_X550:
2725         case ixgbe_mac_X550EM_x:
2726         case ixgbe_mac_X550EM_a:
2727                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2728                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2729                         ETH_LINK_SPEED_10G;
2730                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2731                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2732                         allowed_speeds = ETH_LINK_SPEED_10M |
2733                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2734                 break;
2735         default:
2736                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2737                         ETH_LINK_SPEED_10G;
2738         }
2739
2740         link_speeds = &dev->data->dev_conf.link_speeds;
2741
2742         /* Ignore autoneg flag bit and check the validity of
2743          * link_speed
2744          */
2745         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2746                 PMD_INIT_LOG(ERR, "Invalid link setting");
2747                 goto error;
2748         }
2749
2750         speed = 0x0;
2751         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2752                 switch (hw->mac.type) {
2753                 case ixgbe_mac_82598EB:
2754                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2755                         break;
2756                 case ixgbe_mac_82599EB:
2757                 case ixgbe_mac_X540:
2758                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2759                         break;
2760                 case ixgbe_mac_X550:
2761                 case ixgbe_mac_X550EM_x:
2762                 case ixgbe_mac_X550EM_a:
2763                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2764                         break;
2765                 default:
2766                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2767                 }
2768         } else {
2769                 if (*link_speeds & ETH_LINK_SPEED_10G)
2770                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2771                 if (*link_speeds & ETH_LINK_SPEED_5G)
2772                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2773                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2774                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2775                 if (*link_speeds & ETH_LINK_SPEED_1G)
2776                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2777                 if (*link_speeds & ETH_LINK_SPEED_100M)
2778                         speed |= IXGBE_LINK_SPEED_100_FULL;
2779                 if (*link_speeds & ETH_LINK_SPEED_10M)
2780                         speed |= IXGBE_LINK_SPEED_10_FULL;
2781         }
2782
2783         err = ixgbe_setup_link(hw, speed, link_up);
2784         if (err)
2785                 goto error;
2786
2787 skip_link_setup:
2788
2789         if (rte_intr_allow_others(intr_handle)) {
2790                 /* check if lsc interrupt is enabled */
2791                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2792                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2793                 else
2794                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2795                 ixgbe_dev_macsec_interrupt_setup(dev);
2796         } else {
2797                 rte_intr_callback_unregister(intr_handle,
2798                                              ixgbe_dev_interrupt_handler, dev);
2799                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2800                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2801                                      " no intr multiplex");
2802         }
2803
2804         /* check if rxq interrupt is enabled */
2805         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2806             rte_intr_dp_is_en(intr_handle))
2807                 ixgbe_dev_rxq_interrupt_setup(dev);
2808
2809         /* enable uio/vfio intr/eventfd mapping */
2810         rte_intr_enable(intr_handle);
2811
2812         /* resume enabled intr since hw reset */
2813         ixgbe_enable_intr(dev);
2814         ixgbe_l2_tunnel_conf(dev);
2815         ixgbe_filter_restore(dev);
2816
2817         if (tm_conf->root && !tm_conf->committed)
2818                 PMD_DRV_LOG(WARNING,
2819                             "please call hierarchy_commit() "
2820                             "before starting the port");
2821
2822         /* wait for the controller to acquire link */
2823         err = ixgbe_wait_for_link_up(hw);
2824         if (err)
2825                 goto error;
2826
2827         /*
2828          * Update link status right before return, because it may
2829          * start link configuration process in a separate thread.
2830          */
2831         ixgbe_dev_link_update(dev, 0);
2832
2833         /* setup the macsec setting register */
2834         if (macsec_setting->offload_en)
2835                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2836
2837         return 0;
2838
2839 error:
2840         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2841         ixgbe_dev_clear_queues(dev);
2842         return -EIO;
2843 }
2844
2845 /*
2846  * Stop device: disable rx and tx functions to allow for reconfiguring.
2847  */
2848 static void
2849 ixgbe_dev_stop(struct rte_eth_dev *dev)
2850 {
2851         struct rte_eth_link link;
2852         struct ixgbe_adapter *adapter = dev->data->dev_private;
2853         struct ixgbe_hw *hw =
2854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855         struct ixgbe_vf_info *vfinfo =
2856                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2858         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2859         int vf;
2860         struct ixgbe_tm_conf *tm_conf =
2861                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2862
2863         if (hw->adapter_stopped)
2864                 return;
2865
2866         PMD_INIT_FUNC_TRACE();
2867
2868         ixgbe_dev_wait_setup_link_complete(dev, 0);
2869
2870         /* disable interrupts */
2871         ixgbe_disable_intr(hw);
2872
2873         /* reset the NIC */
2874         ixgbe_pf_reset_hw(hw);
2875         hw->adapter_stopped = 0;
2876
2877         /* stop adapter */
2878         ixgbe_stop_adapter(hw);
2879
2880         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2881                 vfinfo[vf].clear_to_send = false;
2882
2883         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2884                 /* Turn off the copper */
2885                 ixgbe_set_phy_power(hw, false);
2886         } else {
2887                 /* Turn off the laser */
2888                 ixgbe_disable_tx_laser(hw);
2889         }
2890
2891         ixgbe_dev_clear_queues(dev);
2892
2893         /* Clear stored conf */
2894         dev->data->scattered_rx = 0;
2895         dev->data->lro = 0;
2896
2897         /* Clear recorded link status */
2898         memset(&link, 0, sizeof(link));
2899         rte_eth_linkstatus_set(dev, &link);
2900
2901         if (!rte_intr_allow_others(intr_handle))
2902                 /* resume to the default handler */
2903                 rte_intr_callback_register(intr_handle,
2904                                            ixgbe_dev_interrupt_handler,
2905                                            (void *)dev);
2906
2907         /* Clean datapath event and queue/vec mapping */
2908         rte_intr_efd_disable(intr_handle);
2909         if (intr_handle->intr_vec != NULL) {
2910                 rte_free(intr_handle->intr_vec);
2911                 intr_handle->intr_vec = NULL;
2912         }
2913
2914         /* reset hierarchy commit */
2915         tm_conf->committed = false;
2916
2917         adapter->rss_reta_updated = 0;
2918
2919         hw->adapter_stopped = true;
2920         dev->data->dev_started = 0;
2921 }
2922
2923 /*
2924  * Set device link up: enable tx.
2925  */
2926 static int
2927 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2928 {
2929         struct ixgbe_hw *hw =
2930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2931         if (hw->mac.type == ixgbe_mac_82599EB) {
2932 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2933                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2934                         /* Not suported in bypass mode */
2935                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2936                                      "by device id 0x%x", hw->device_id);
2937                         return -ENOTSUP;
2938                 }
2939 #endif
2940         }
2941
2942         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2943                 /* Turn on the copper */
2944                 ixgbe_set_phy_power(hw, true);
2945         } else {
2946                 /* Turn on the laser */
2947                 ixgbe_enable_tx_laser(hw);
2948                 ixgbe_dev_link_update(dev, 0);
2949         }
2950
2951         return 0;
2952 }
2953
2954 /*
2955  * Set device link down: disable tx.
2956  */
2957 static int
2958 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2959 {
2960         struct ixgbe_hw *hw =
2961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2962         if (hw->mac.type == ixgbe_mac_82599EB) {
2963 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2964                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2965                         /* Not suported in bypass mode */
2966                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2967                                      "by device id 0x%x", hw->device_id);
2968                         return -ENOTSUP;
2969                 }
2970 #endif
2971         }
2972
2973         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2974                 /* Turn off the copper */
2975                 ixgbe_set_phy_power(hw, false);
2976         } else {
2977                 /* Turn off the laser */
2978                 ixgbe_disable_tx_laser(hw);
2979                 ixgbe_dev_link_update(dev, 0);
2980         }
2981
2982         return 0;
2983 }
2984
2985 /*
2986  * Reset and stop device.
2987  */
2988 static int
2989 ixgbe_dev_close(struct rte_eth_dev *dev)
2990 {
2991         struct ixgbe_hw *hw =
2992                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2994         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2995         int retries = 0;
2996         int ret;
2997
2998         PMD_INIT_FUNC_TRACE();
2999         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3000                 return 0;
3001
3002         ixgbe_pf_reset_hw(hw);
3003
3004         ixgbe_dev_stop(dev);
3005
3006         ixgbe_dev_free_queues(dev);
3007
3008         ixgbe_disable_pcie_master(hw);
3009
3010         /* reprogram the RAR[0] in case user changed it. */
3011         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3012
3013         /* Unlock any pending hardware semaphore */
3014         ixgbe_swfw_lock_reset(hw);
3015
3016         /* disable uio intr before callback unregister */
3017         rte_intr_disable(intr_handle);
3018
3019         do {
3020                 ret = rte_intr_callback_unregister(intr_handle,
3021                                 ixgbe_dev_interrupt_handler, dev);
3022                 if (ret >= 0 || ret == -ENOENT) {
3023                         break;
3024                 } else if (ret != -EAGAIN) {
3025                         PMD_INIT_LOG(ERR,
3026                                 "intr callback unregister failed: %d",
3027                                 ret);
3028                 }
3029                 rte_delay_ms(100);
3030         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3031
3032         /* cancel the delay handler before remove dev */
3033         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3034
3035         /* uninitialize PF if max_vfs not zero */
3036         ixgbe_pf_host_uninit(dev);
3037
3038         /* remove all the fdir filters & hash */
3039         ixgbe_fdir_filter_uninit(dev);
3040
3041         /* remove all the L2 tunnel filters & hash */
3042         ixgbe_l2_tn_filter_uninit(dev);
3043
3044         /* Remove all ntuple filters of the device */
3045         ixgbe_ntuple_filter_uninit(dev);
3046
3047         /* clear all the filters list */
3048         ixgbe_filterlist_flush();
3049
3050         /* Remove all Traffic Manager configuration */
3051         ixgbe_tm_conf_uninit(dev);
3052
3053 #ifdef RTE_LIBRTE_SECURITY
3054         rte_free(dev->security_ctx);
3055 #endif
3056
3057         return 0;
3058 }
3059
3060 /*
3061  * Reset PF device.
3062  */
3063 static int
3064 ixgbe_dev_reset(struct rte_eth_dev *dev)
3065 {
3066         int ret;
3067
3068         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3069          * its VF to make them align with it. The detailed notification
3070          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3071          * To avoid unexpected behavior in VF, currently reset of PF with
3072          * SR-IOV activation is not supported. It might be supported later.
3073          */
3074         if (dev->data->sriov.active)
3075                 return -ENOTSUP;
3076
3077         ret = eth_ixgbe_dev_uninit(dev);
3078         if (ret)
3079                 return ret;
3080
3081         ret = eth_ixgbe_dev_init(dev, NULL);
3082
3083         return ret;
3084 }
3085
3086 static void
3087 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3088                            struct ixgbe_hw_stats *hw_stats,
3089                            struct ixgbe_macsec_stats *macsec_stats,
3090                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3091                            uint64_t *total_qprc, uint64_t *total_qprdc)
3092 {
3093         uint32_t bprc, lxon, lxoff, total;
3094         uint32_t delta_gprc = 0;
3095         unsigned i;
3096         /* Workaround for RX byte count not including CRC bytes when CRC
3097          * strip is enabled. CRC bytes are removed from counters when crc_strip
3098          * is disabled.
3099          */
3100         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3101                         IXGBE_HLREG0_RXCRCSTRP);
3102
3103         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3104         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3105         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3106         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3107
3108         for (i = 0; i < 8; i++) {
3109                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3110
3111                 /* global total per queue */
3112                 hw_stats->mpc[i] += mp;
3113                 /* Running comprehensive total for stats display */
3114                 *total_missed_rx += hw_stats->mpc[i];
3115                 if (hw->mac.type == ixgbe_mac_82598EB) {
3116                         hw_stats->rnbc[i] +=
3117                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3118                         hw_stats->pxonrxc[i] +=
3119                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3120                         hw_stats->pxoffrxc[i] +=
3121                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3122                 } else {
3123                         hw_stats->pxonrxc[i] +=
3124                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3125                         hw_stats->pxoffrxc[i] +=
3126                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3127                         hw_stats->pxon2offc[i] +=
3128                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3129                 }
3130                 hw_stats->pxontxc[i] +=
3131                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3132                 hw_stats->pxofftxc[i] +=
3133                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3134         }
3135         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3136                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3137                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3138                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3139
3140                 delta_gprc += delta_qprc;
3141
3142                 hw_stats->qprc[i] += delta_qprc;
3143                 hw_stats->qptc[i] += delta_qptc;
3144
3145                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3146                 hw_stats->qbrc[i] +=
3147                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3148                 if (crc_strip == 0)
3149                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3150
3151                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3152                 hw_stats->qbtc[i] +=
3153                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3154
3155                 hw_stats->qprdc[i] += delta_qprdc;
3156                 *total_qprdc += hw_stats->qprdc[i];
3157
3158                 *total_qprc += hw_stats->qprc[i];
3159                 *total_qbrc += hw_stats->qbrc[i];
3160         }
3161         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3162         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3163         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3164
3165         /*
3166          * An errata states that gprc actually counts good + missed packets:
3167          * Workaround to set gprc to summated queue packet receives
3168          */
3169         hw_stats->gprc = *total_qprc;
3170
3171         if (hw->mac.type != ixgbe_mac_82598EB) {
3172                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3173                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3174                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3175                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3176                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3177                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3178                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3179                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3180         } else {
3181                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3182                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3183                 /* 82598 only has a counter in the high register */
3184                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3185                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3186                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3187         }
3188         uint64_t old_tpr = hw_stats->tpr;
3189
3190         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3191         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3192
3193         if (crc_strip == 0)
3194                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3195
3196         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3197         hw_stats->gptc += delta_gptc;
3198         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3199         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3200
3201         /*
3202          * Workaround: mprc hardware is incorrectly counting
3203          * broadcasts, so for now we subtract those.
3204          */
3205         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3206         hw_stats->bprc += bprc;
3207         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3208         if (hw->mac.type == ixgbe_mac_82598EB)
3209                 hw_stats->mprc -= bprc;
3210
3211         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3212         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3213         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3214         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3215         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3216         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3217
3218         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3219         hw_stats->lxontxc += lxon;
3220         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3221         hw_stats->lxofftxc += lxoff;
3222         total = lxon + lxoff;
3223
3224         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3225         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3226         hw_stats->gptc -= total;
3227         hw_stats->mptc -= total;
3228         hw_stats->ptc64 -= total;
3229         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3230
3231         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3232         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3233         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3234         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3235         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3236         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3237         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3238         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3239         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3240         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3241         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3242         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3243         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3244         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3245         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3246         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3247         /* Only read FCOE on 82599 */
3248         if (hw->mac.type != ixgbe_mac_82598EB) {
3249                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3250                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3251                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3252                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3253                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3254         }
3255
3256         /* Flow Director Stats registers */
3257         if (hw->mac.type != ixgbe_mac_82598EB) {
3258                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3259                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3260                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3261                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3262                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3263                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3264                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3265                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3266                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3267                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3268         }
3269         /* MACsec Stats registers */
3270         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3271         macsec_stats->out_pkts_encrypted +=
3272                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3273         macsec_stats->out_pkts_protected +=
3274                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3275         macsec_stats->out_octets_encrypted +=
3276                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3277         macsec_stats->out_octets_protected +=
3278                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3279         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3280         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3281         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3282         macsec_stats->in_pkts_unknownsci +=
3283                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3284         macsec_stats->in_octets_decrypted +=
3285                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3286         macsec_stats->in_octets_validated +=
3287                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3288         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3289         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3290         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3291         for (i = 0; i < 2; i++) {
3292                 macsec_stats->in_pkts_ok +=
3293                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3294                 macsec_stats->in_pkts_invalid +=
3295                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3296                 macsec_stats->in_pkts_notvalid +=
3297                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3298         }
3299         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3300         macsec_stats->in_pkts_notusingsa +=
3301                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3302 }
3303
3304 /*
3305  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3306  */
3307 static int
3308 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3309 {
3310         struct ixgbe_hw *hw =
3311                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312         struct ixgbe_hw_stats *hw_stats =
3313                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3314         struct ixgbe_macsec_stats *macsec_stats =
3315                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3316                                 dev->data->dev_private);
3317         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3318         unsigned i;
3319
3320         total_missed_rx = 0;
3321         total_qbrc = 0;
3322         total_qprc = 0;
3323         total_qprdc = 0;
3324
3325         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3326                         &total_qbrc, &total_qprc, &total_qprdc);
3327
3328         if (stats == NULL)
3329                 return -EINVAL;
3330
3331         /* Fill out the rte_eth_stats statistics structure */
3332         stats->ipackets = total_qprc;
3333         stats->ibytes = total_qbrc;
3334         stats->opackets = hw_stats->gptc;
3335         stats->obytes = hw_stats->gotc;
3336
3337         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3338                 stats->q_ipackets[i] = hw_stats->qprc[i];
3339                 stats->q_opackets[i] = hw_stats->qptc[i];
3340                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3341                 stats->q_obytes[i] = hw_stats->qbtc[i];
3342                 stats->q_errors[i] = hw_stats->qprdc[i];
3343         }
3344
3345         /* Rx Errors */
3346         stats->imissed  = total_missed_rx;
3347         stats->ierrors  = hw_stats->crcerrs +
3348                           hw_stats->mspdc +
3349                           hw_stats->rlec +
3350                           hw_stats->ruc +
3351                           hw_stats->roc +
3352                           hw_stats->illerrc +
3353                           hw_stats->errbc +
3354                           hw_stats->rfc +
3355                           hw_stats->fccrc +
3356                           hw_stats->fclast;
3357
3358         /* Tx Errors */
3359         stats->oerrors  = 0;
3360         return 0;
3361 }
3362
3363 static int
3364 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3365 {
3366         struct ixgbe_hw_stats *stats =
3367                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3368
3369         /* HW registers are cleared on read */
3370         ixgbe_dev_stats_get(dev, NULL);
3371
3372         /* Reset software totals */
3373         memset(stats, 0, sizeof(*stats));
3374
3375         return 0;
3376 }
3377
3378 /* This function calculates the number of xstats based on the current config */
3379 static unsigned
3380 ixgbe_xstats_calc_num(void) {
3381         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3382                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3383                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3384 }
3385
3386 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3387         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3388 {
3389         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3390         unsigned stat, i, count;
3391
3392         if (xstats_names != NULL) {
3393                 count = 0;
3394
3395                 /* Note: limit >= cnt_stats checked upstream
3396                  * in rte_eth_xstats_names()
3397                  */
3398
3399                 /* Extended stats from ixgbe_hw_stats */
3400                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3401                         strlcpy(xstats_names[count].name,
3402                                 rte_ixgbe_stats_strings[i].name,
3403                                 sizeof(xstats_names[count].name));
3404                         count++;
3405                 }
3406
3407                 /* MACsec Stats */
3408                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3409                         strlcpy(xstats_names[count].name,
3410                                 rte_ixgbe_macsec_strings[i].name,
3411                                 sizeof(xstats_names[count].name));
3412                         count++;
3413                 }
3414
3415                 /* RX Priority Stats */
3416                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3417                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3418                                 snprintf(xstats_names[count].name,
3419                                         sizeof(xstats_names[count].name),
3420                                         "rx_priority%u_%s", i,
3421                                         rte_ixgbe_rxq_strings[stat].name);
3422                                 count++;
3423                         }
3424                 }
3425
3426                 /* TX Priority Stats */
3427                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3428                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3429                                 snprintf(xstats_names[count].name,
3430                                         sizeof(xstats_names[count].name),
3431                                         "tx_priority%u_%s", i,
3432                                         rte_ixgbe_txq_strings[stat].name);
3433                                 count++;
3434                         }
3435                 }
3436         }
3437         return cnt_stats;
3438 }
3439
3440 static int ixgbe_dev_xstats_get_names_by_id(
3441         struct rte_eth_dev *dev,
3442         struct rte_eth_xstat_name *xstats_names,
3443         const uint64_t *ids,
3444         unsigned int limit)
3445 {
3446         if (!ids) {
3447                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3448                 unsigned int stat, i, count;
3449
3450                 if (xstats_names != NULL) {
3451                         count = 0;
3452
3453                         /* Note: limit >= cnt_stats checked upstream
3454                          * in rte_eth_xstats_names()
3455                          */
3456
3457                         /* Extended stats from ixgbe_hw_stats */
3458                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3459                                 strlcpy(xstats_names[count].name,
3460                                         rte_ixgbe_stats_strings[i].name,
3461                                         sizeof(xstats_names[count].name));
3462                                 count++;
3463                         }
3464
3465                         /* MACsec Stats */
3466                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3467                                 strlcpy(xstats_names[count].name,
3468                                         rte_ixgbe_macsec_strings[i].name,
3469                                         sizeof(xstats_names[count].name));
3470                                 count++;
3471                         }
3472
3473                         /* RX Priority Stats */
3474                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3475                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3476                                         snprintf(xstats_names[count].name,
3477                                             sizeof(xstats_names[count].name),
3478                                             "rx_priority%u_%s", i,
3479                                             rte_ixgbe_rxq_strings[stat].name);
3480                                         count++;
3481                                 }
3482                         }
3483
3484                         /* TX Priority Stats */
3485                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3486                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3487                                         snprintf(xstats_names[count].name,
3488                                             sizeof(xstats_names[count].name),
3489                                             "tx_priority%u_%s", i,
3490                                             rte_ixgbe_txq_strings[stat].name);
3491                                         count++;
3492                                 }
3493                         }
3494                 }
3495                 return cnt_stats;
3496         }
3497
3498         uint16_t i;
3499         uint16_t size = ixgbe_xstats_calc_num();
3500         struct rte_eth_xstat_name xstats_names_copy[size];
3501
3502         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3503                         size);
3504
3505         for (i = 0; i < limit; i++) {
3506                 if (ids[i] >= size) {
3507                         PMD_INIT_LOG(ERR, "id value isn't valid");
3508                         return -1;
3509                 }
3510                 strcpy(xstats_names[i].name,
3511                                 xstats_names_copy[ids[i]].name);
3512         }
3513         return limit;
3514 }
3515
3516 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3517         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3518 {
3519         unsigned i;
3520
3521         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3522                 return -ENOMEM;
3523
3524         if (xstats_names != NULL)
3525                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3526                         strlcpy(xstats_names[i].name,
3527                                 rte_ixgbevf_stats_strings[i].name,
3528                                 sizeof(xstats_names[i].name));
3529         return IXGBEVF_NB_XSTATS;
3530 }
3531
3532 static int
3533 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3534                                          unsigned n)
3535 {
3536         struct ixgbe_hw *hw =
3537                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538         struct ixgbe_hw_stats *hw_stats =
3539                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3540         struct ixgbe_macsec_stats *macsec_stats =
3541                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3542                                 dev->data->dev_private);
3543         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3544         unsigned i, stat, count = 0;
3545
3546         count = ixgbe_xstats_calc_num();
3547
3548         if (n < count)
3549                 return count;
3550
3551         total_missed_rx = 0;
3552         total_qbrc = 0;
3553         total_qprc = 0;
3554         total_qprdc = 0;
3555
3556         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3557                         &total_qbrc, &total_qprc, &total_qprdc);
3558
3559         /* If this is a reset xstats is NULL, and we have cleared the
3560          * registers by reading them.
3561          */
3562         if (!xstats)
3563                 return 0;
3564
3565         /* Extended stats from ixgbe_hw_stats */
3566         count = 0;
3567         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3568                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3569                                 rte_ixgbe_stats_strings[i].offset);
3570                 xstats[count].id = count;
3571                 count++;
3572         }
3573
3574         /* MACsec Stats */
3575         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3576                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3577                                 rte_ixgbe_macsec_strings[i].offset);
3578                 xstats[count].id = count;
3579                 count++;
3580         }
3581
3582         /* RX Priority Stats */
3583         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3584                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3585                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3586                                         rte_ixgbe_rxq_strings[stat].offset +
3587                                         (sizeof(uint64_t) * i));
3588                         xstats[count].id = count;
3589                         count++;
3590                 }
3591         }
3592
3593         /* TX Priority Stats */
3594         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3595                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3596                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3597                                         rte_ixgbe_txq_strings[stat].offset +
3598                                         (sizeof(uint64_t) * i));
3599                         xstats[count].id = count;
3600                         count++;
3601                 }
3602         }
3603         return count;
3604 }
3605
3606 static int
3607 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3608                 uint64_t *values, unsigned int n)
3609 {
3610         if (!ids) {
3611                 struct ixgbe_hw *hw =
3612                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3613                 struct ixgbe_hw_stats *hw_stats =
3614                                 IXGBE_DEV_PRIVATE_TO_STATS(
3615                                                 dev->data->dev_private);
3616                 struct ixgbe_macsec_stats *macsec_stats =
3617                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3618                                         dev->data->dev_private);
3619                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3620                 unsigned int i, stat, count = 0;
3621
3622                 count = ixgbe_xstats_calc_num();
3623
3624                 if (!ids && n < count)
3625                         return count;
3626
3627                 total_missed_rx = 0;
3628                 total_qbrc = 0;
3629                 total_qprc = 0;
3630                 total_qprdc = 0;
3631
3632                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3633                                 &total_missed_rx, &total_qbrc, &total_qprc,
3634                                 &total_qprdc);
3635
3636                 /* If this is a reset xstats is NULL, and we have cleared the
3637                  * registers by reading them.
3638                  */
3639                 if (!ids && !values)
3640                         return 0;
3641
3642                 /* Extended stats from ixgbe_hw_stats */
3643                 count = 0;
3644                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3645                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3646                                         rte_ixgbe_stats_strings[i].offset);
3647                         count++;
3648                 }
3649
3650                 /* MACsec Stats */
3651                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3652                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3653                                         rte_ixgbe_macsec_strings[i].offset);
3654                         count++;
3655                 }
3656
3657                 /* RX Priority Stats */
3658                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3659                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3660                                 values[count] =
3661                                         *(uint64_t *)(((char *)hw_stats) +
3662                                         rte_ixgbe_rxq_strings[stat].offset +
3663                                         (sizeof(uint64_t) * i));
3664                                 count++;
3665                         }
3666                 }
3667
3668                 /* TX Priority Stats */
3669                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3670                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3671                                 values[count] =
3672                                         *(uint64_t *)(((char *)hw_stats) +
3673                                         rte_ixgbe_txq_strings[stat].offset +
3674                                         (sizeof(uint64_t) * i));
3675                                 count++;
3676                         }
3677                 }
3678                 return count;
3679         }
3680
3681         uint16_t i;
3682         uint16_t size = ixgbe_xstats_calc_num();
3683         uint64_t values_copy[size];
3684
3685         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3686
3687         for (i = 0; i < n; i++) {
3688                 if (ids[i] >= size) {
3689                         PMD_INIT_LOG(ERR, "id value isn't valid");
3690                         return -1;
3691                 }
3692                 values[i] = values_copy[ids[i]];
3693         }
3694         return n;
3695 }
3696
3697 static int
3698 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3699 {
3700         struct ixgbe_hw_stats *stats =
3701                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3702         struct ixgbe_macsec_stats *macsec_stats =
3703                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3704                                 dev->data->dev_private);
3705
3706         unsigned count = ixgbe_xstats_calc_num();
3707
3708         /* HW registers are cleared on read */
3709         ixgbe_dev_xstats_get(dev, NULL, count);
3710
3711         /* Reset software totals */
3712         memset(stats, 0, sizeof(*stats));
3713         memset(macsec_stats, 0, sizeof(*macsec_stats));
3714
3715         return 0;
3716 }
3717
3718 static void
3719 ixgbevf_update_stats(struct rte_eth_dev *dev)
3720 {
3721         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3722         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3723                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3724
3725         /* Good Rx packet, include VF loopback */
3726         UPDATE_VF_STAT(IXGBE_VFGPRC,
3727             hw_stats->last_vfgprc, hw_stats->vfgprc);
3728
3729         /* Good Rx octets, include VF loopback */
3730         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3731             hw_stats->last_vfgorc, hw_stats->vfgorc);
3732
3733         /* Good Tx packet, include VF loopback */
3734         UPDATE_VF_STAT(IXGBE_VFGPTC,
3735             hw_stats->last_vfgptc, hw_stats->vfgptc);
3736
3737         /* Good Tx octets, include VF loopback */
3738         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3739             hw_stats->last_vfgotc, hw_stats->vfgotc);
3740
3741         /* Rx Multicst Packet */
3742         UPDATE_VF_STAT(IXGBE_VFMPRC,
3743             hw_stats->last_vfmprc, hw_stats->vfmprc);
3744 }
3745
3746 static int
3747 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3748                        unsigned n)
3749 {
3750         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3751                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3752         unsigned i;
3753
3754         if (n < IXGBEVF_NB_XSTATS)
3755                 return IXGBEVF_NB_XSTATS;
3756
3757         ixgbevf_update_stats(dev);
3758
3759         if (!xstats)
3760                 return 0;
3761
3762         /* Extended stats */
3763         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3764                 xstats[i].id = i;
3765                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3766                         rte_ixgbevf_stats_strings[i].offset);
3767         }
3768
3769         return IXGBEVF_NB_XSTATS;
3770 }
3771
3772 static int
3773 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3774 {
3775         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3776                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3777
3778         ixgbevf_update_stats(dev);
3779
3780         if (stats == NULL)
3781                 return -EINVAL;
3782
3783         stats->ipackets = hw_stats->vfgprc;
3784         stats->ibytes = hw_stats->vfgorc;
3785         stats->opackets = hw_stats->vfgptc;
3786         stats->obytes = hw_stats->vfgotc;
3787         return 0;
3788 }
3789
3790 static int
3791 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3792 {
3793         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3794                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3795
3796         /* Sync HW register to the last stats */
3797         ixgbevf_dev_stats_get(dev, NULL);
3798
3799         /* reset HW current stats*/
3800         hw_stats->vfgprc = 0;
3801         hw_stats->vfgorc = 0;
3802         hw_stats->vfgptc = 0;
3803         hw_stats->vfgotc = 0;
3804
3805         return 0;
3806 }
3807
3808 static int
3809 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3810 {
3811         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3812         u16 eeprom_verh, eeprom_verl;
3813         u32 etrack_id;
3814         int ret;
3815
3816         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3817         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3818
3819         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3820         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3821
3822         ret += 1; /* add the size of '\0' */
3823         if (fw_size < (u32)ret)
3824                 return ret;
3825         else
3826                 return 0;
3827 }
3828
3829 static int
3830 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3831 {
3832         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3834         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3835
3836         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3837         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3838         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3839                 /*
3840                  * When DCB/VT is off, maximum number of queues changes,
3841                  * except for 82598EB, which remains constant.
3842                  */
3843                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3844                                 hw->mac.type != ixgbe_mac_82598EB)
3845                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3846         }
3847         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3848         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3849         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3850         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3851         dev_info->max_vfs = pci_dev->max_vfs;
3852         if (hw->mac.type == ixgbe_mac_82598EB)
3853                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3854         else
3855                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3856         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3857         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3858         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3859         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3860         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3861                                      dev_info->rx_queue_offload_capa);
3862         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3863         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3864
3865         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3866                 .rx_thresh = {
3867                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3868                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3869                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3870                 },
3871                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3872                 .rx_drop_en = 0,
3873                 .offloads = 0,
3874         };
3875
3876         dev_info->default_txconf = (struct rte_eth_txconf) {
3877                 .tx_thresh = {
3878                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3879                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3880                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3881                 },
3882                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3883                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3884                 .offloads = 0,
3885         };
3886
3887         dev_info->rx_desc_lim = rx_desc_lim;
3888         dev_info->tx_desc_lim = tx_desc_lim;
3889
3890         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3891         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3892         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3893
3894         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3895         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3896                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3897                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3898                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3899
3900         if (hw->mac.type == ixgbe_mac_X540 ||
3901             hw->mac.type == ixgbe_mac_X540_vf ||
3902             hw->mac.type == ixgbe_mac_X550 ||
3903             hw->mac.type == ixgbe_mac_X550_vf) {
3904                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3905         }
3906         if (hw->mac.type == ixgbe_mac_X550) {
3907                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3908                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3909         }
3910
3911         /* Driver-preferred Rx/Tx parameters */
3912         dev_info->default_rxportconf.burst_size = 32;
3913         dev_info->default_txportconf.burst_size = 32;
3914         dev_info->default_rxportconf.nb_queues = 1;
3915         dev_info->default_txportconf.nb_queues = 1;
3916         dev_info->default_rxportconf.ring_size = 256;
3917         dev_info->default_txportconf.ring_size = 256;
3918
3919         return 0;
3920 }
3921
3922 static const uint32_t *
3923 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3924 {
3925         static const uint32_t ptypes[] = {
3926                 /* For non-vec functions,
3927                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3928                  * for vec functions,
3929                  * refers to _recv_raw_pkts_vec().
3930                  */
3931                 RTE_PTYPE_L2_ETHER,
3932                 RTE_PTYPE_L3_IPV4,
3933                 RTE_PTYPE_L3_IPV4_EXT,
3934                 RTE_PTYPE_L3_IPV6,
3935                 RTE_PTYPE_L3_IPV6_EXT,
3936                 RTE_PTYPE_L4_SCTP,
3937                 RTE_PTYPE_L4_TCP,
3938                 RTE_PTYPE_L4_UDP,
3939                 RTE_PTYPE_TUNNEL_IP,
3940                 RTE_PTYPE_INNER_L3_IPV6,
3941                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3942                 RTE_PTYPE_INNER_L4_TCP,
3943                 RTE_PTYPE_INNER_L4_UDP,
3944                 RTE_PTYPE_UNKNOWN
3945         };
3946
3947         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3948             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3949             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3950             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3951                 return ptypes;
3952
3953 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3954         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3955             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3956                 return ptypes;
3957 #endif
3958         return NULL;
3959 }
3960
3961 static int
3962 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3963                      struct rte_eth_dev_info *dev_info)
3964 {
3965         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3967
3968         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3969         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3970         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3971         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3972         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3973         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3974         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3975         dev_info->max_vfs = pci_dev->max_vfs;
3976         if (hw->mac.type == ixgbe_mac_82598EB)
3977                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3978         else
3979                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3980         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3981         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3982                                      dev_info->rx_queue_offload_capa);
3983         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3984         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3985         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3986         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3987         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3988
3989         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3990                 .rx_thresh = {
3991                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3992                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3993                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3994                 },
3995                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3996                 .rx_drop_en = 0,
3997                 .offloads = 0,
3998         };
3999
4000         dev_info->default_txconf = (struct rte_eth_txconf) {
4001                 .tx_thresh = {
4002                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4003                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4004                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4005                 },
4006                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4007                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4008                 .offloads = 0,
4009         };
4010
4011         dev_info->rx_desc_lim = rx_desc_lim;
4012         dev_info->tx_desc_lim = tx_desc_lim;
4013
4014         return 0;
4015 }
4016
4017 static int
4018 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4019                    bool *link_up, int wait_to_complete)
4020 {
4021         struct ixgbe_adapter *adapter = container_of(hw,
4022                                                      struct ixgbe_adapter, hw);
4023         struct ixgbe_mbx_info *mbx = &hw->mbx;
4024         struct ixgbe_mac_info *mac = &hw->mac;
4025         uint32_t links_reg, in_msg;
4026         int ret_val = 0;
4027
4028         /* If we were hit with a reset drop the link */
4029         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4030                 mac->get_link_status = true;
4031
4032         if (!mac->get_link_status)
4033                 goto out;
4034
4035         /* if link status is down no point in checking to see if pf is up */
4036         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4037         if (!(links_reg & IXGBE_LINKS_UP))
4038                 goto out;
4039
4040         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4041          * before the link status is correct
4042          */
4043         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4044                 int i;
4045
4046                 for (i = 0; i < 5; i++) {
4047                         rte_delay_us(100);
4048                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4049
4050                         if (!(links_reg & IXGBE_LINKS_UP))
4051                                 goto out;
4052                 }
4053         }
4054
4055         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4056         case IXGBE_LINKS_SPEED_10G_82599:
4057                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4058                 if (hw->mac.type >= ixgbe_mac_X550) {
4059                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4060                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4061                 }
4062                 break;
4063         case IXGBE_LINKS_SPEED_1G_82599:
4064                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4065                 break;
4066         case IXGBE_LINKS_SPEED_100_82599:
4067                 *speed = IXGBE_LINK_SPEED_100_FULL;
4068                 if (hw->mac.type == ixgbe_mac_X550) {
4069                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4070                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4071                 }
4072                 break;
4073         case IXGBE_LINKS_SPEED_10_X550EM_A:
4074                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4075                 /* Since Reserved in older MAC's */
4076                 if (hw->mac.type >= ixgbe_mac_X550)
4077                         *speed = IXGBE_LINK_SPEED_10_FULL;
4078                 break;
4079         default:
4080                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4081         }
4082
4083         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4084                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4085                         mac->get_link_status = true;
4086                 else
4087                         mac->get_link_status = false;
4088
4089                 goto out;
4090         }
4091
4092         /* if the read failed it could just be a mailbox collision, best wait
4093          * until we are called again and don't report an error
4094          */
4095         if (mbx->ops.read(hw, &in_msg, 1, 0))
4096                 goto out;
4097
4098         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4099                 /* msg is not CTS and is NACK we must have lost CTS status */
4100                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4101                         mac->get_link_status = false;
4102                 goto out;
4103         }
4104
4105         /* the pf is talking, if we timed out in the past we reinit */
4106         if (!mbx->timeout) {
4107                 ret_val = -1;
4108                 goto out;
4109         }
4110
4111         /* if we passed all the tests above then the link is up and we no
4112          * longer need to check for link
4113          */
4114         mac->get_link_status = false;
4115
4116 out:
4117         *link_up = !mac->get_link_status;
4118         return ret_val;
4119 }
4120
4121 /*
4122  * If @timeout_ms was 0, it means that it will not return until link complete.
4123  * It returns 1 on complete, return 0 on timeout.
4124  */
4125 static int
4126 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4127 {
4128 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4129         struct ixgbe_adapter *ad = dev->data->dev_private;
4130         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4131
4132         while (rte_atomic32_read(&ad->link_thread_running)) {
4133                 msec_delay(1);
4134                 timeout--;
4135
4136                 if (timeout_ms) {
4137                         if (!timeout)
4138                                 return 0;
4139                 } else if (!timeout) {
4140                         /* It will not return until link complete */
4141                         timeout = WARNING_TIMEOUT;
4142                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4143                 }
4144         }
4145
4146         return 1;
4147 }
4148
4149 static void *
4150 ixgbe_dev_setup_link_thread_handler(void *param)
4151 {
4152         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4153         struct ixgbe_adapter *ad = dev->data->dev_private;
4154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4155         struct ixgbe_interrupt *intr =
4156                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4157         u32 speed;
4158         bool autoneg = false;
4159
4160         pthread_detach(pthread_self());
4161         speed = hw->phy.autoneg_advertised;
4162         if (!speed)
4163                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4164
4165         ixgbe_setup_link(hw, speed, true);
4166
4167         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4168         rte_atomic32_clear(&ad->link_thread_running);
4169         return NULL;
4170 }
4171
4172 /*
4173  * In freebsd environment, nic_uio drivers do not support interrupts,
4174  * rte_intr_callback_register() will fail to register interrupts.
4175  * We can not make link status to change from down to up by interrupt
4176  * callback. So we need to wait for the controller to acquire link
4177  * when ports start.
4178  * It returns 0 on link up.
4179  */
4180 static int
4181 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4182 {
4183 #ifdef RTE_EXEC_ENV_FREEBSD
4184         int err, i;
4185         bool link_up = false;
4186         uint32_t speed = 0;
4187         const int nb_iter = 25;
4188
4189         for (i = 0; i < nb_iter; i++) {
4190                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4191                 if (err)
4192                         return err;
4193                 if (link_up)
4194                         return 0;
4195                 msec_delay(200);
4196         }
4197
4198         return 0;
4199 #else
4200         RTE_SET_USED(hw);
4201         return 0;
4202 #endif
4203 }
4204
4205 /* return 0 means link status changed, -1 means not changed */
4206 int
4207 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4208                             int wait_to_complete, int vf)
4209 {
4210         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211         struct ixgbe_adapter *ad = dev->data->dev_private;
4212         struct rte_eth_link link;
4213         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4214         struct ixgbe_interrupt *intr =
4215                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4216         bool link_up;
4217         int diag;
4218         int wait = 1;
4219         u32 esdp_reg;
4220
4221         memset(&link, 0, sizeof(link));
4222         link.link_status = ETH_LINK_DOWN;
4223         link.link_speed = ETH_SPEED_NUM_NONE;
4224         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4225         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4226                         ETH_LINK_SPEED_FIXED);
4227
4228         hw->mac.get_link_status = true;
4229
4230         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4231                 return rte_eth_linkstatus_set(dev, &link);
4232
4233         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4234         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4235                 wait = 0;
4236
4237 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4238 #ifdef RTE_EXEC_ENV_FREEBSD
4239         wait = 1;
4240 #endif
4241
4242         if (vf)
4243                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4244         else
4245                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4246
4247         if (diag != 0) {
4248                 link.link_speed = ETH_SPEED_NUM_100M;
4249                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4250                 return rte_eth_linkstatus_set(dev, &link);
4251         }
4252
4253         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4254                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4255                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4256                         link_up = 0;
4257         }
4258
4259         if (link_up == 0) {
4260                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4261                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4262                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4263                                 /* To avoid race condition between threads, set
4264                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4265                                  * when there is no link thread running.
4266                                  */
4267                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4268                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4269                                         "ixgbe-link-handler",
4270                                         NULL,
4271                                         ixgbe_dev_setup_link_thread_handler,
4272                                         dev) < 0) {
4273                                         PMD_DRV_LOG(ERR,
4274                                                 "Create link thread failed!");
4275                                         rte_atomic32_clear(&ad->link_thread_running);
4276                                 }
4277                         } else {
4278                                 PMD_DRV_LOG(ERR,
4279                                         "Other link thread is running now!");
4280                         }
4281                 }
4282                 return rte_eth_linkstatus_set(dev, &link);
4283         }
4284
4285         link.link_status = ETH_LINK_UP;
4286         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4287
4288         switch (link_speed) {
4289         default:
4290         case IXGBE_LINK_SPEED_UNKNOWN:
4291                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4292                 break;
4293
4294         case IXGBE_LINK_SPEED_10_FULL:
4295                 link.link_speed = ETH_SPEED_NUM_10M;
4296                 break;
4297
4298         case IXGBE_LINK_SPEED_100_FULL:
4299                 link.link_speed = ETH_SPEED_NUM_100M;
4300                 break;
4301
4302         case IXGBE_LINK_SPEED_1GB_FULL:
4303                 link.link_speed = ETH_SPEED_NUM_1G;
4304                 break;
4305
4306         case IXGBE_LINK_SPEED_2_5GB_FULL:
4307                 link.link_speed = ETH_SPEED_NUM_2_5G;
4308                 break;
4309
4310         case IXGBE_LINK_SPEED_5GB_FULL:
4311                 link.link_speed = ETH_SPEED_NUM_5G;
4312                 break;
4313
4314         case IXGBE_LINK_SPEED_10GB_FULL:
4315                 link.link_speed = ETH_SPEED_NUM_10G;
4316                 break;
4317         }
4318
4319         return rte_eth_linkstatus_set(dev, &link);
4320 }
4321
4322 static int
4323 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4324 {
4325         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4326 }
4327
4328 static int
4329 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4330 {
4331         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4332 }
4333
4334 static int
4335 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4336 {
4337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4338         uint32_t fctrl;
4339
4340         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4341         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4342         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4343
4344         return 0;
4345 }
4346
4347 static int
4348 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4349 {
4350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4351         uint32_t fctrl;
4352
4353         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4354         fctrl &= (~IXGBE_FCTRL_UPE);
4355         if (dev->data->all_multicast == 1)
4356                 fctrl |= IXGBE_FCTRL_MPE;
4357         else
4358                 fctrl &= (~IXGBE_FCTRL_MPE);
4359         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4360
4361         return 0;
4362 }
4363
4364 static int
4365 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4366 {
4367         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4368         uint32_t fctrl;
4369
4370         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4371         fctrl |= IXGBE_FCTRL_MPE;
4372         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4373
4374         return 0;
4375 }
4376
4377 static int
4378 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4379 {
4380         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4381         uint32_t fctrl;
4382
4383         if (dev->data->promiscuous == 1)
4384                 return 0; /* must remain in all_multicast mode */
4385
4386         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4387         fctrl &= (~IXGBE_FCTRL_MPE);
4388         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4389
4390         return 0;
4391 }
4392
4393 /**
4394  * It clears the interrupt causes and enables the interrupt.
4395  * It will be called once only during nic initialized.
4396  *
4397  * @param dev
4398  *  Pointer to struct rte_eth_dev.
4399  * @param on
4400  *  Enable or Disable.
4401  *
4402  * @return
4403  *  - On success, zero.
4404  *  - On failure, a negative value.
4405  */
4406 static int
4407 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4408 {
4409         struct ixgbe_interrupt *intr =
4410                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4411
4412         ixgbe_dev_link_status_print(dev);
4413         if (on)
4414                 intr->mask |= IXGBE_EICR_LSC;
4415         else
4416                 intr->mask &= ~IXGBE_EICR_LSC;
4417
4418         return 0;
4419 }
4420
4421 /**
4422  * It clears the interrupt causes and enables the interrupt.
4423  * It will be called once only during nic initialized.
4424  *
4425  * @param dev
4426  *  Pointer to struct rte_eth_dev.
4427  *
4428  * @return
4429  *  - On success, zero.
4430  *  - On failure, a negative value.
4431  */
4432 static int
4433 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4434 {
4435         struct ixgbe_interrupt *intr =
4436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4437
4438         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4439
4440         return 0;
4441 }
4442
4443 /**
4444  * It clears the interrupt causes and enables the interrupt.
4445  * It will be called once only during nic initialized.
4446  *
4447  * @param dev
4448  *  Pointer to struct rte_eth_dev.
4449  *
4450  * @return
4451  *  - On success, zero.
4452  *  - On failure, a negative value.
4453  */
4454 static int
4455 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4456 {
4457         struct ixgbe_interrupt *intr =
4458                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4459
4460         intr->mask |= IXGBE_EICR_LINKSEC;
4461
4462         return 0;
4463 }
4464
4465 /*
4466  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4467  *
4468  * @param dev
4469  *  Pointer to struct rte_eth_dev.
4470  *
4471  * @return
4472  *  - On success, zero.
4473  *  - On failure, a negative value.
4474  */
4475 static int
4476 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4477 {
4478         uint32_t eicr;
4479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4480         struct ixgbe_interrupt *intr =
4481                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4482
4483         /* clear all cause mask */
4484         ixgbe_disable_intr(hw);
4485
4486         /* read-on-clear nic registers here */
4487         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4488         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4489
4490         intr->flags = 0;
4491
4492         /* set flag for async link update */
4493         if (eicr & IXGBE_EICR_LSC)
4494                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4495
4496         if (eicr & IXGBE_EICR_MAILBOX)
4497                 intr->flags |= IXGBE_FLAG_MAILBOX;
4498
4499         if (eicr & IXGBE_EICR_LINKSEC)
4500                 intr->flags |= IXGBE_FLAG_MACSEC;
4501
4502         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4503             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4504             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4505                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4506
4507         return 0;
4508 }
4509
4510 /**
4511  * It gets and then prints the link status.
4512  *
4513  * @param dev
4514  *  Pointer to struct rte_eth_dev.
4515  *
4516  * @return
4517  *  - On success, zero.
4518  *  - On failure, a negative value.
4519  */
4520 static void
4521 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4522 {
4523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4524         struct rte_eth_link link;
4525
4526         rte_eth_linkstatus_get(dev, &link);
4527
4528         if (link.link_status) {
4529                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4530                                         (int)(dev->data->port_id),
4531                                         (unsigned)link.link_speed,
4532                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4533                                         "full-duplex" : "half-duplex");
4534         } else {
4535                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4536                                 (int)(dev->data->port_id));
4537         }
4538         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4539                                 pci_dev->addr.domain,
4540                                 pci_dev->addr.bus,
4541                                 pci_dev->addr.devid,
4542                                 pci_dev->addr.function);
4543 }
4544
4545 /*
4546  * It executes link_update after knowing an interrupt occurred.
4547  *
4548  * @param dev
4549  *  Pointer to struct rte_eth_dev.
4550  *
4551  * @return
4552  *  - On success, zero.
4553  *  - On failure, a negative value.
4554  */
4555 static int
4556 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4557 {
4558         struct ixgbe_interrupt *intr =
4559                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4560         int64_t timeout;
4561         struct ixgbe_hw *hw =
4562                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4563
4564         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4565
4566         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4567                 ixgbe_pf_mbx_process(dev);
4568                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4569         }
4570
4571         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4572                 ixgbe_handle_lasi(hw);
4573                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4574         }
4575
4576         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4577                 struct rte_eth_link link;
4578
4579                 /* get the link status before link update, for predicting later */
4580                 rte_eth_linkstatus_get(dev, &link);
4581
4582                 ixgbe_dev_link_update(dev, 0);
4583
4584                 /* likely to up */
4585                 if (!link.link_status)
4586                         /* handle it 1 sec later, wait it being stable */
4587                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4588                 /* likely to down */
4589                 else
4590                         /* handle it 4 sec later, wait it being stable */
4591                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4592
4593                 ixgbe_dev_link_status_print(dev);
4594                 if (rte_eal_alarm_set(timeout * 1000,
4595                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4596                         PMD_DRV_LOG(ERR, "Error setting alarm");
4597                 else {
4598                         /* remember original mask */
4599                         intr->mask_original = intr->mask;
4600                         /* only disable lsc interrupt */
4601                         intr->mask &= ~IXGBE_EIMS_LSC;
4602                 }
4603         }
4604
4605         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4606         ixgbe_enable_intr(dev);
4607
4608         return 0;
4609 }
4610
4611 /**
4612  * Interrupt handler which shall be registered for alarm callback for delayed
4613  * handling specific interrupt to wait for the stable nic state. As the
4614  * NIC interrupt state is not stable for ixgbe after link is just down,
4615  * it needs to wait 4 seconds to get the stable status.
4616  *
4617  * @param handle
4618  *  Pointer to interrupt handle.
4619  * @param param
4620  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4621  *
4622  * @return
4623  *  void
4624  */
4625 static void
4626 ixgbe_dev_interrupt_delayed_handler(void *param)
4627 {
4628         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4629         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4630         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4631         struct ixgbe_interrupt *intr =
4632                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4633         struct ixgbe_hw *hw =
4634                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635         uint32_t eicr;
4636
4637         ixgbe_disable_intr(hw);
4638
4639         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4640         if (eicr & IXGBE_EICR_MAILBOX)
4641                 ixgbe_pf_mbx_process(dev);
4642
4643         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4644                 ixgbe_handle_lasi(hw);
4645                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4646         }
4647
4648         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4649                 ixgbe_dev_link_update(dev, 0);
4650                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4651                 ixgbe_dev_link_status_print(dev);
4652                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4653         }
4654
4655         if (intr->flags & IXGBE_FLAG_MACSEC) {
4656                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4657                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4658         }
4659
4660         /* restore original mask */
4661         intr->mask = intr->mask_original;
4662         intr->mask_original = 0;
4663
4664         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4665         ixgbe_enable_intr(dev);
4666         rte_intr_ack(intr_handle);
4667 }
4668
4669 /**
4670  * Interrupt handler triggered by NIC  for handling
4671  * specific interrupt.
4672  *
4673  * @param handle
4674  *  Pointer to interrupt handle.
4675  * @param param
4676  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4677  *
4678  * @return
4679  *  void
4680  */
4681 static void
4682 ixgbe_dev_interrupt_handler(void *param)
4683 {
4684         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4685
4686         ixgbe_dev_interrupt_get_status(dev);
4687         ixgbe_dev_interrupt_action(dev);
4688 }
4689
4690 static int
4691 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4692 {
4693         struct ixgbe_hw *hw;
4694
4695         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4697 }
4698
4699 static int
4700 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4701 {
4702         struct ixgbe_hw *hw;
4703
4704         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4705         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4706 }
4707
4708 static int
4709 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4710 {
4711         struct ixgbe_hw *hw;
4712         uint32_t mflcn_reg;
4713         uint32_t fccfg_reg;
4714         int rx_pause;
4715         int tx_pause;
4716
4717         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4718
4719         fc_conf->pause_time = hw->fc.pause_time;
4720         fc_conf->high_water = hw->fc.high_water[0];
4721         fc_conf->low_water = hw->fc.low_water[0];
4722         fc_conf->send_xon = hw->fc.send_xon;
4723         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4724
4725         /*
4726          * Return rx_pause status according to actual setting of
4727          * MFLCN register.
4728          */
4729         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4730         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4731                 fc_conf->mac_ctrl_frame_fwd = 1;
4732         else
4733                 fc_conf->mac_ctrl_frame_fwd = 0;
4734
4735         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4736                 rx_pause = 1;
4737         else
4738                 rx_pause = 0;
4739
4740         /*
4741          * Return tx_pause status according to actual setting of
4742          * FCCFG register.
4743          */
4744         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4745         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4746                 tx_pause = 1;
4747         else
4748                 tx_pause = 0;
4749
4750         if (rx_pause && tx_pause)
4751                 fc_conf->mode = RTE_FC_FULL;
4752         else if (rx_pause)
4753                 fc_conf->mode = RTE_FC_RX_PAUSE;
4754         else if (tx_pause)
4755                 fc_conf->mode = RTE_FC_TX_PAUSE;
4756         else
4757                 fc_conf->mode = RTE_FC_NONE;
4758
4759         return 0;
4760 }
4761
4762 static int
4763 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4764 {
4765         struct ixgbe_hw *hw;
4766         struct ixgbe_adapter *adapter = dev->data->dev_private;
4767         int err;
4768         uint32_t rx_buf_size;
4769         uint32_t max_high_water;
4770         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4771                 ixgbe_fc_none,
4772                 ixgbe_fc_rx_pause,
4773                 ixgbe_fc_tx_pause,
4774                 ixgbe_fc_full
4775         };
4776
4777         PMD_INIT_FUNC_TRACE();
4778
4779         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4780         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4781         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4782
4783         /*
4784          * At least reserve one Ethernet frame for watermark
4785          * high_water/low_water in kilo bytes for ixgbe
4786          */
4787         max_high_water = (rx_buf_size -
4788                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4789         if ((fc_conf->high_water > max_high_water) ||
4790                 (fc_conf->high_water < fc_conf->low_water)) {
4791                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4792                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4793                 return -EINVAL;
4794         }
4795
4796         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4797         hw->fc.pause_time     = fc_conf->pause_time;
4798         hw->fc.high_water[0]  = fc_conf->high_water;
4799         hw->fc.low_water[0]   = fc_conf->low_water;
4800         hw->fc.send_xon       = fc_conf->send_xon;
4801         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4802         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4803
4804         err = ixgbe_flow_ctrl_enable(dev, hw);
4805         if (err < 0) {
4806                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4807                 return -EIO;
4808         }
4809         return err;
4810 }
4811
4812 /**
4813  *  ixgbe_pfc_enable_generic - Enable flow control
4814  *  @hw: pointer to hardware structure
4815  *  @tc_num: traffic class number
4816  *  Enable flow control according to the current settings.
4817  */
4818 static int
4819 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4820 {
4821         int ret_val = 0;
4822         uint32_t mflcn_reg, fccfg_reg;
4823         uint32_t reg;
4824         uint32_t fcrtl, fcrth;
4825         uint8_t i;
4826         uint8_t nb_rx_en;
4827
4828         /* Validate the water mark configuration */
4829         if (!hw->fc.pause_time) {
4830                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4831                 goto out;
4832         }
4833
4834         /* Low water mark of zero causes XOFF floods */
4835         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4836                  /* High/Low water can not be 0 */
4837                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4838                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4839                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4840                         goto out;
4841                 }
4842
4843                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4844                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4845                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4846                         goto out;
4847                 }
4848         }
4849         /* Negotiate the fc mode to use */
4850         ixgbe_fc_autoneg(hw);
4851
4852         /* Disable any previous flow control settings */
4853         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4854         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4855
4856         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4857         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4858
4859         switch (hw->fc.current_mode) {
4860         case ixgbe_fc_none:
4861                 /*
4862                  * If the count of enabled RX Priority Flow control >1,
4863                  * and the TX pause can not be disabled
4864                  */
4865                 nb_rx_en = 0;
4866                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4867                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4868                         if (reg & IXGBE_FCRTH_FCEN)
4869                                 nb_rx_en++;
4870                 }
4871                 if (nb_rx_en > 1)
4872                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4873                 break;
4874         case ixgbe_fc_rx_pause:
4875                 /*
4876                  * Rx Flow control is enabled and Tx Flow control is
4877                  * disabled by software override. Since there really
4878                  * isn't a way to advertise that we are capable of RX
4879                  * Pause ONLY, we will advertise that we support both
4880                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4881                  * disable the adapter's ability to send PAUSE frames.
4882                  */
4883                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4884                 /*
4885                  * If the count of enabled RX Priority Flow control >1,
4886                  * and the TX pause can not be disabled
4887                  */
4888                 nb_rx_en = 0;
4889                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4890                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4891                         if (reg & IXGBE_FCRTH_FCEN)
4892                                 nb_rx_en++;
4893                 }
4894                 if (nb_rx_en > 1)
4895                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4896                 break;
4897         case ixgbe_fc_tx_pause:
4898                 /*
4899                  * Tx Flow control is enabled, and Rx Flow control is
4900                  * disabled by software override.
4901                  */
4902                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4903                 break;
4904         case ixgbe_fc_full:
4905                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4906                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4907                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4908                 break;
4909         default:
4910                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4911                 ret_val = IXGBE_ERR_CONFIG;
4912                 goto out;
4913         }
4914
4915         /* Set 802.3x based flow control settings. */
4916         mflcn_reg |= IXGBE_MFLCN_DPF;
4917         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4918         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4919
4920         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4921         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4922                 hw->fc.high_water[tc_num]) {
4923                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4924                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4925                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4926         } else {
4927                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4928                 /*
4929                  * In order to prevent Tx hangs when the internal Tx
4930                  * switch is enabled we must set the high water mark
4931                  * to the maximum FCRTH value.  This allows the Tx
4932                  * switch to function even under heavy Rx workloads.
4933                  */
4934                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4935         }
4936         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4937
4938         /* Configure pause time (2 TCs per register) */
4939         reg = hw->fc.pause_time * 0x00010001;
4940         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4941                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4942
4943         /* Configure flow control refresh threshold value */
4944         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4945
4946 out:
4947         return ret_val;
4948 }
4949
4950 static int
4951 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4952 {
4953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4955
4956         if (hw->mac.type != ixgbe_mac_82598EB) {
4957                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4958         }
4959         return ret_val;
4960 }
4961
4962 static int
4963 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4964 {
4965         int err;
4966         uint32_t rx_buf_size;
4967         uint32_t max_high_water;
4968         uint8_t tc_num;
4969         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4970         struct ixgbe_hw *hw =
4971                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4972         struct ixgbe_dcb_config *dcb_config =
4973                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4974
4975         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4976                 ixgbe_fc_none,
4977                 ixgbe_fc_rx_pause,
4978                 ixgbe_fc_tx_pause,
4979                 ixgbe_fc_full
4980         };
4981
4982         PMD_INIT_FUNC_TRACE();
4983
4984         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4985         tc_num = map[pfc_conf->priority];
4986         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4987         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4988         /*
4989          * At least reserve one Ethernet frame for watermark
4990          * high_water/low_water in kilo bytes for ixgbe
4991          */
4992         max_high_water = (rx_buf_size -
4993                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4994         if ((pfc_conf->fc.high_water > max_high_water) ||
4995             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4996                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4997                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4998                 return -EINVAL;
4999         }
5000
5001         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5002         hw->fc.pause_time = pfc_conf->fc.pause_time;
5003         hw->fc.send_xon = pfc_conf->fc.send_xon;
5004         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5005         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5006
5007         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5008
5009         /* Not negotiated is not an error case */
5010         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5011                 return 0;
5012
5013         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5014         return -EIO;
5015 }
5016
5017 static int
5018 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5019                           struct rte_eth_rss_reta_entry64 *reta_conf,
5020                           uint16_t reta_size)
5021 {
5022         uint16_t i, sp_reta_size;
5023         uint8_t j, mask;
5024         uint32_t reta, r;
5025         uint16_t idx, shift;
5026         struct ixgbe_adapter *adapter = dev->data->dev_private;
5027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5028         uint32_t reta_reg;
5029
5030         PMD_INIT_FUNC_TRACE();
5031
5032         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5033                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5034                         "NIC.");
5035                 return -ENOTSUP;
5036         }
5037
5038         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5039         if (reta_size != sp_reta_size) {
5040                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5041                         "(%d) doesn't match the number hardware can supported "
5042                         "(%d)", reta_size, sp_reta_size);
5043                 return -EINVAL;
5044         }
5045
5046         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5047                 idx = i / RTE_RETA_GROUP_SIZE;
5048                 shift = i % RTE_RETA_GROUP_SIZE;
5049                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5050                                                 IXGBE_4_BIT_MASK);
5051                 if (!mask)
5052                         continue;
5053                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5054                 if (mask == IXGBE_4_BIT_MASK)
5055                         r = 0;
5056                 else
5057                         r = IXGBE_READ_REG(hw, reta_reg);
5058                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5059                         if (mask & (0x1 << j))
5060                                 reta |= reta_conf[idx].reta[shift + j] <<
5061                                                         (CHAR_BIT * j);
5062                         else
5063                                 reta |= r & (IXGBE_8_BIT_MASK <<
5064                                                 (CHAR_BIT * j));
5065                 }
5066                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5067         }
5068         adapter->rss_reta_updated = 1;
5069
5070         return 0;
5071 }
5072
5073 static int
5074 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5075                          struct rte_eth_rss_reta_entry64 *reta_conf,
5076                          uint16_t reta_size)
5077 {
5078         uint16_t i, sp_reta_size;
5079         uint8_t j, mask;
5080         uint32_t reta;
5081         uint16_t idx, shift;
5082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5083         uint32_t reta_reg;
5084
5085         PMD_INIT_FUNC_TRACE();
5086         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5087         if (reta_size != sp_reta_size) {
5088                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5089                         "(%d) doesn't match the number hardware can supported "
5090                         "(%d)", reta_size, sp_reta_size);
5091                 return -EINVAL;
5092         }
5093
5094         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5095                 idx = i / RTE_RETA_GROUP_SIZE;
5096                 shift = i % RTE_RETA_GROUP_SIZE;
5097                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5098                                                 IXGBE_4_BIT_MASK);
5099                 if (!mask)
5100                         continue;
5101
5102                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5103                 reta = IXGBE_READ_REG(hw, reta_reg);
5104                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5105                         if (mask & (0x1 << j))
5106                                 reta_conf[idx].reta[shift + j] =
5107                                         ((reta >> (CHAR_BIT * j)) &
5108                                                 IXGBE_8_BIT_MASK);
5109                 }
5110         }
5111
5112         return 0;
5113 }
5114
5115 static int
5116 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5117                                 uint32_t index, uint32_t pool)
5118 {
5119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120         uint32_t enable_addr = 1;
5121
5122         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5123                              pool, enable_addr);
5124 }
5125
5126 static void
5127 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5128 {
5129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5130
5131         ixgbe_clear_rar(hw, index);
5132 }
5133
5134 static int
5135 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5136 {
5137         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5138
5139         ixgbe_remove_rar(dev, 0);
5140         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5141
5142         return 0;
5143 }
5144
5145 static bool
5146 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5147 {
5148         if (strcmp(dev->device->driver->name, drv->driver.name))
5149                 return false;
5150
5151         return true;
5152 }
5153
5154 bool
5155 is_ixgbe_supported(struct rte_eth_dev *dev)
5156 {
5157         return is_device_supported(dev, &rte_ixgbe_pmd);
5158 }
5159
5160 static int
5161 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5162 {
5163         uint32_t hlreg0;
5164         uint32_t maxfrs;
5165         struct ixgbe_hw *hw;
5166         struct rte_eth_dev_info dev_info;
5167         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5168         struct rte_eth_dev_data *dev_data = dev->data;
5169         int ret;
5170
5171         ret = ixgbe_dev_info_get(dev, &dev_info);
5172         if (ret != 0)
5173                 return ret;
5174
5175         /* check that mtu is within the allowed range */
5176         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5177                 return -EINVAL;
5178
5179         /* If device is started, refuse mtu that requires the support of
5180          * scattered packets when this feature has not been enabled before.
5181          */
5182         if (dev_data->dev_started && !dev_data->scattered_rx &&
5183             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5184              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5185                 PMD_INIT_LOG(ERR, "Stop port first.");
5186                 return -EINVAL;
5187         }
5188
5189         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5190         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5191
5192         /* switch to jumbo mode if needed */
5193         if (frame_size > RTE_ETHER_MAX_LEN) {
5194                 dev->data->dev_conf.rxmode.offloads |=
5195                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5196                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5197         } else {
5198                 dev->data->dev_conf.rxmode.offloads &=
5199                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5200                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5201         }
5202         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5203
5204         /* update max frame size */
5205         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5206
5207         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5208         maxfrs &= 0x0000FFFF;
5209         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5210         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5211
5212         return 0;
5213 }
5214
5215 /*
5216  * Virtual Function operations
5217  */
5218 static void
5219 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5220 {
5221         struct ixgbe_interrupt *intr =
5222                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5223         struct ixgbe_hw *hw =
5224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225
5226         PMD_INIT_FUNC_TRACE();
5227
5228         /* Clear interrupt mask to stop from interrupts being generated */
5229         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5230
5231         IXGBE_WRITE_FLUSH(hw);
5232
5233         /* Clear mask value. */
5234         intr->mask = 0;
5235 }
5236
5237 static void
5238 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5239 {
5240         struct ixgbe_interrupt *intr =
5241                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5242         struct ixgbe_hw *hw =
5243                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244
5245         PMD_INIT_FUNC_TRACE();
5246
5247         /* VF enable interrupt autoclean */
5248         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5249         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5250         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5251
5252         IXGBE_WRITE_FLUSH(hw);
5253
5254         /* Save IXGBE_VTEIMS value to mask. */
5255         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5256 }
5257
5258 static int
5259 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5260 {
5261         struct rte_eth_conf *conf = &dev->data->dev_conf;
5262         struct ixgbe_adapter *adapter = dev->data->dev_private;
5263
5264         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5265                      dev->data->port_id);
5266
5267         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5268                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5269
5270         /*
5271          * VF has no ability to enable/disable HW CRC
5272          * Keep the persistent behavior the same as Host PF
5273          */
5274 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5275         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5276                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5277                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5278         }
5279 #else
5280         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5281                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5282                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5283         }
5284 #endif
5285
5286         /*
5287          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5288          * allocation or vector Rx preconditions we will reset it.
5289          */
5290         adapter->rx_bulk_alloc_allowed = true;
5291         adapter->rx_vec_allowed = true;
5292
5293         return 0;
5294 }
5295
5296 static int
5297 ixgbevf_dev_start(struct rte_eth_dev *dev)
5298 {
5299         struct ixgbe_hw *hw =
5300                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5301         uint32_t intr_vector = 0;
5302         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5303         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5304
5305         int err, mask = 0;
5306
5307         PMD_INIT_FUNC_TRACE();
5308
5309         /* Stop the link setup handler before resetting the HW. */
5310         ixgbe_dev_wait_setup_link_complete(dev, 0);
5311
5312         err = hw->mac.ops.reset_hw(hw);
5313
5314         /**
5315          * In this case, reuses the MAC address assigned by VF
5316          * initialization.
5317          */
5318         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5319                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5320                 return err;
5321         }
5322
5323         hw->mac.get_link_status = true;
5324
5325         /* negotiate mailbox API version to use with the PF. */
5326         ixgbevf_negotiate_api(hw);
5327
5328         ixgbevf_dev_tx_init(dev);
5329
5330         /* This can fail when allocating mbufs for descriptor rings */
5331         err = ixgbevf_dev_rx_init(dev);
5332         if (err) {
5333                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5334                 ixgbe_dev_clear_queues(dev);
5335                 return err;
5336         }
5337
5338         /* Set vfta */
5339         ixgbevf_set_vfta_all(dev, 1);
5340
5341         /* Set HW strip */
5342         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5343                 ETH_VLAN_EXTEND_MASK;
5344         err = ixgbevf_vlan_offload_config(dev, mask);
5345         if (err) {
5346                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5347                 ixgbe_dev_clear_queues(dev);
5348                 return err;
5349         }
5350
5351         ixgbevf_dev_rxtx_start(dev);
5352
5353         /* check and configure queue intr-vector mapping */
5354         if (rte_intr_cap_multiple(intr_handle) &&
5355             dev->data->dev_conf.intr_conf.rxq) {
5356                 /* According to datasheet, only vector 0/1/2 can be used,
5357                  * now only one vector is used for Rx queue
5358                  */
5359                 intr_vector = 1;
5360                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5361                         return -1;
5362         }
5363
5364         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5365                 intr_handle->intr_vec =
5366                         rte_zmalloc("intr_vec",
5367                                     dev->data->nb_rx_queues * sizeof(int), 0);
5368                 if (intr_handle->intr_vec == NULL) {
5369                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5370                                      " intr_vec", dev->data->nb_rx_queues);
5371                         return -ENOMEM;
5372                 }
5373         }
5374         ixgbevf_configure_msix(dev);
5375
5376         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5377          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5378          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5379          * is not cleared, it will fail when following rte_intr_enable( ) tries
5380          * to map Rx queue interrupt to other VFIO vectors.
5381          * So clear uio/vfio intr/evevnfd first to avoid failure.
5382          */
5383         rte_intr_disable(intr_handle);
5384
5385         rte_intr_enable(intr_handle);
5386
5387         /* Re-enable interrupt for VF */
5388         ixgbevf_intr_enable(dev);
5389
5390         /*
5391          * Update link status right before return, because it may
5392          * start link configuration process in a separate thread.
5393          */
5394         ixgbevf_dev_link_update(dev, 0);
5395
5396         hw->adapter_stopped = false;
5397
5398         return 0;
5399 }
5400
5401 static void
5402 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5403 {
5404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405         struct ixgbe_adapter *adapter = dev->data->dev_private;
5406         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5407         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5408
5409         if (hw->adapter_stopped)
5410                 return;
5411
5412         PMD_INIT_FUNC_TRACE();
5413
5414         ixgbe_dev_wait_setup_link_complete(dev, 0);
5415
5416         ixgbevf_intr_disable(dev);
5417
5418         dev->data->dev_started = 0;
5419         hw->adapter_stopped = 1;
5420         ixgbe_stop_adapter(hw);
5421
5422         /*
5423           * Clear what we set, but we still keep shadow_vfta to
5424           * restore after device starts
5425           */
5426         ixgbevf_set_vfta_all(dev, 0);
5427
5428         /* Clear stored conf */
5429         dev->data->scattered_rx = 0;
5430
5431         ixgbe_dev_clear_queues(dev);
5432
5433         /* Clean datapath event and queue/vec mapping */
5434         rte_intr_efd_disable(intr_handle);
5435         if (intr_handle->intr_vec != NULL) {
5436                 rte_free(intr_handle->intr_vec);
5437                 intr_handle->intr_vec = NULL;
5438         }
5439
5440         adapter->rss_reta_updated = 0;
5441 }
5442
5443 static int
5444 ixgbevf_dev_close(struct rte_eth_dev *dev)
5445 {
5446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5447         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5448         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5449
5450         PMD_INIT_FUNC_TRACE();
5451         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5452                 return 0;
5453
5454         ixgbe_reset_hw(hw);
5455
5456         ixgbevf_dev_stop(dev);
5457
5458         ixgbe_dev_free_queues(dev);
5459
5460         /**
5461          * Remove the VF MAC address ro ensure
5462          * that the VF traffic goes to the PF
5463          * after stop, close and detach of the VF
5464          **/
5465         ixgbevf_remove_mac_addr(dev, 0);
5466
5467         rte_intr_disable(intr_handle);
5468         rte_intr_callback_unregister(intr_handle,
5469                                      ixgbevf_dev_interrupt_handler, dev);
5470
5471         return 0;
5472 }
5473
5474 /*
5475  * Reset VF device
5476  */
5477 static int
5478 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5479 {
5480         int ret;
5481
5482         ret = eth_ixgbevf_dev_uninit(dev);
5483         if (ret)
5484                 return ret;
5485
5486         ret = eth_ixgbevf_dev_init(dev);
5487
5488         return ret;
5489 }
5490
5491 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5492 {
5493         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5494         struct ixgbe_vfta *shadow_vfta =
5495                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5496         int i = 0, j = 0, vfta = 0, mask = 1;
5497
5498         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5499                 vfta = shadow_vfta->vfta[i];
5500                 if (vfta) {
5501                         mask = 1;
5502                         for (j = 0; j < 32; j++) {
5503                                 if (vfta & mask)
5504                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5505                                                        on, false);
5506                                 mask <<= 1;
5507                         }
5508                 }
5509         }
5510
5511 }
5512
5513 static int
5514 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5515 {
5516         struct ixgbe_hw *hw =
5517                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5518         struct ixgbe_vfta *shadow_vfta =
5519                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5520         uint32_t vid_idx = 0;
5521         uint32_t vid_bit = 0;
5522         int ret = 0;
5523
5524         PMD_INIT_FUNC_TRACE();
5525
5526         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5527         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5528         if (ret) {
5529                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5530                 return ret;
5531         }
5532         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5533         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5534
5535         /* Save what we set and retore it after device reset */
5536         if (on)
5537                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5538         else
5539                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5540
5541         return 0;
5542 }
5543
5544 static void
5545 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5546 {
5547         struct ixgbe_hw *hw =
5548                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549         uint32_t ctrl;
5550
5551         PMD_INIT_FUNC_TRACE();
5552
5553         if (queue >= hw->mac.max_rx_queues)
5554                 return;
5555
5556         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5557         if (on)
5558                 ctrl |= IXGBE_RXDCTL_VME;
5559         else
5560                 ctrl &= ~IXGBE_RXDCTL_VME;
5561         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5562
5563         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5564 }
5565
5566 static int
5567 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5568 {
5569         struct ixgbe_rx_queue *rxq;
5570         uint16_t i;
5571         int on = 0;
5572
5573         /* VF function only support hw strip feature, others are not support */
5574         if (mask & ETH_VLAN_STRIP_MASK) {
5575                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5576                         rxq = dev->data->rx_queues[i];
5577                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5578                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5579                 }
5580         }
5581
5582         return 0;
5583 }
5584
5585 static int
5586 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5587 {
5588         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5589
5590         ixgbevf_vlan_offload_config(dev, mask);
5591
5592         return 0;
5593 }
5594
5595 int
5596 ixgbe_vt_check(struct ixgbe_hw *hw)
5597 {
5598         uint32_t reg_val;
5599
5600         /* if Virtualization Technology is enabled */
5601         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5602         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5603                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5604                 return -1;
5605         }
5606
5607         return 0;
5608 }
5609
5610 static uint32_t
5611 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5612 {
5613         uint32_t vector = 0;
5614
5615         switch (hw->mac.mc_filter_type) {
5616         case 0:   /* use bits [47:36] of the address */
5617                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5618                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5619                 break;
5620         case 1:   /* use bits [46:35] of the address */
5621                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5622                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5623                 break;
5624         case 2:   /* use bits [45:34] of the address */
5625                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5626                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5627                 break;
5628         case 3:   /* use bits [43:32] of the address */
5629                 vector = ((uc_addr->addr_bytes[4]) |
5630                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5631                 break;
5632         default:  /* Invalid mc_filter_type */
5633                 break;
5634         }
5635
5636         /* vector can only be 12-bits or boundary will be exceeded */
5637         vector &= 0xFFF;
5638         return vector;
5639 }
5640
5641 static int
5642 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5643                         struct rte_ether_addr *mac_addr, uint8_t on)
5644 {
5645         uint32_t vector;
5646         uint32_t uta_idx;
5647         uint32_t reg_val;
5648         uint32_t uta_shift;
5649         uint32_t rc;
5650         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5651         const uint32_t ixgbe_uta_bit_shift = 5;
5652         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5653         const uint32_t bit1 = 0x1;
5654
5655         struct ixgbe_hw *hw =
5656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5657         struct ixgbe_uta_info *uta_info =
5658                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5659
5660         /* The UTA table only exists on 82599 hardware and newer */
5661         if (hw->mac.type < ixgbe_mac_82599EB)
5662                 return -ENOTSUP;
5663
5664         vector = ixgbe_uta_vector(hw, mac_addr);
5665         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5666         uta_shift = vector & ixgbe_uta_bit_mask;
5667
5668         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5669         if (rc == on)
5670                 return 0;
5671
5672         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5673         if (on) {
5674                 uta_info->uta_in_use++;
5675                 reg_val |= (bit1 << uta_shift);
5676                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5677         } else {
5678                 uta_info->uta_in_use--;
5679                 reg_val &= ~(bit1 << uta_shift);
5680                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5681         }
5682
5683         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5684
5685         if (uta_info->uta_in_use > 0)
5686                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5687                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5688         else
5689                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5690
5691         return 0;
5692 }
5693
5694 static int
5695 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5696 {
5697         int i;
5698         struct ixgbe_hw *hw =
5699                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5700         struct ixgbe_uta_info *uta_info =
5701                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5702
5703         /* The UTA table only exists on 82599 hardware and newer */
5704         if (hw->mac.type < ixgbe_mac_82599EB)
5705                 return -ENOTSUP;
5706
5707         if (on) {
5708                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5709                         uta_info->uta_shadow[i] = ~0;
5710                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5711                 }
5712         } else {
5713                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5714                         uta_info->uta_shadow[i] = 0;
5715                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5716                 }
5717         }
5718         return 0;
5719
5720 }
5721
5722 uint32_t
5723 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5724 {
5725         uint32_t new_val = orig_val;
5726
5727         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5728                 new_val |= IXGBE_VMOLR_AUPE;
5729         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5730                 new_val |= IXGBE_VMOLR_ROMPE;
5731         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5732                 new_val |= IXGBE_VMOLR_ROPE;
5733         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5734                 new_val |= IXGBE_VMOLR_BAM;
5735         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5736                 new_val |= IXGBE_VMOLR_MPE;
5737
5738         return new_val;
5739 }
5740
5741 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5742 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5743 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5744 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5745 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5746         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5747         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5748
5749 static int
5750 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5751                       struct rte_eth_mirror_conf *mirror_conf,
5752                       uint8_t rule_id, uint8_t on)
5753 {
5754         uint32_t mr_ctl, vlvf;
5755         uint32_t mp_lsb = 0;
5756         uint32_t mv_msb = 0;
5757         uint32_t mv_lsb = 0;
5758         uint32_t mp_msb = 0;
5759         uint8_t i = 0;
5760         int reg_index = 0;
5761         uint64_t vlan_mask = 0;
5762
5763         const uint8_t pool_mask_offset = 32;
5764         const uint8_t vlan_mask_offset = 32;
5765         const uint8_t dst_pool_offset = 8;
5766         const uint8_t rule_mr_offset  = 4;
5767         const uint8_t mirror_rule_mask = 0x0F;
5768
5769         struct ixgbe_mirror_info *mr_info =
5770                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5771         struct ixgbe_hw *hw =
5772                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5773         uint8_t mirror_type = 0;
5774
5775         if (ixgbe_vt_check(hw) < 0)
5776                 return -ENOTSUP;
5777
5778         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5779                 return -EINVAL;
5780
5781         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5782                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5783                             mirror_conf->rule_type);
5784                 return -EINVAL;
5785         }
5786
5787         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5788                 mirror_type |= IXGBE_MRCTL_VLME;
5789                 /* Check if vlan id is valid and find conresponding VLAN ID
5790                  * index in VLVF
5791                  */
5792                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5793                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5794                                 /* search vlan id related pool vlan filter
5795                                  * index
5796                                  */
5797                                 reg_index = ixgbe_find_vlvf_slot(
5798                                                 hw,
5799                                                 mirror_conf->vlan.vlan_id[i],
5800                                                 false);
5801                                 if (reg_index < 0)
5802                                         return -EINVAL;
5803                                 vlvf = IXGBE_READ_REG(hw,
5804                                                       IXGBE_VLVF(reg_index));
5805                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5806                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5807                                       mirror_conf->vlan.vlan_id[i]))
5808                                         vlan_mask |= (1ULL << reg_index);
5809                                 else
5810                                         return -EINVAL;
5811                         }
5812                 }
5813
5814                 if (on) {
5815                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5816                         mv_msb = vlan_mask >> vlan_mask_offset;
5817
5818                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5819                                                 mirror_conf->vlan.vlan_mask;
5820                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5821                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5822                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5823                                                 mirror_conf->vlan.vlan_id[i];
5824                         }
5825                 } else {
5826                         mv_lsb = 0;
5827                         mv_msb = 0;
5828                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5829                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5830                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5831                 }
5832         }
5833
5834         /**
5835          * if enable pool mirror, write related pool mask register,if disable
5836          * pool mirror, clear PFMRVM register
5837          */
5838         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5839                 mirror_type |= IXGBE_MRCTL_VPME;
5840                 if (on) {
5841                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5842                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5843                         mr_info->mr_conf[rule_id].pool_mask =
5844                                         mirror_conf->pool_mask;
5845
5846                 } else {
5847                         mp_lsb = 0;
5848                         mp_msb = 0;
5849                         mr_info->mr_conf[rule_id].pool_mask = 0;
5850                 }
5851         }
5852         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5853                 mirror_type |= IXGBE_MRCTL_UPME;
5854         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5855                 mirror_type |= IXGBE_MRCTL_DPME;
5856
5857         /* read  mirror control register and recalculate it */
5858         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5859
5860         if (on) {
5861                 mr_ctl |= mirror_type;
5862                 mr_ctl &= mirror_rule_mask;
5863                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5864         } else {
5865                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5866         }
5867
5868         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5869         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5870
5871         /* write mirrror control  register */
5872         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5873
5874         /* write pool mirrror control  register */
5875         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5876                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5877                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5878                                 mp_msb);
5879         }
5880         /* write VLAN mirrror control  register */
5881         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5882                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5883                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5884                                 mv_msb);
5885         }
5886
5887         return 0;
5888 }
5889
5890 static int
5891 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5892 {
5893         int mr_ctl = 0;
5894         uint32_t lsb_val = 0;
5895         uint32_t msb_val = 0;
5896         const uint8_t rule_mr_offset = 4;
5897
5898         struct ixgbe_hw *hw =
5899                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5900         struct ixgbe_mirror_info *mr_info =
5901                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5902
5903         if (ixgbe_vt_check(hw) < 0)
5904                 return -ENOTSUP;
5905
5906         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5907                 return -EINVAL;
5908
5909         memset(&mr_info->mr_conf[rule_id], 0,
5910                sizeof(struct rte_eth_mirror_conf));
5911
5912         /* clear PFVMCTL register */
5913         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5914
5915         /* clear pool mask register */
5916         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5917         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5918
5919         /* clear vlan mask register */
5920         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5921         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5922
5923         return 0;
5924 }
5925
5926 static int
5927 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5928 {
5929         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5930         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5931         struct ixgbe_interrupt *intr =
5932                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5933         struct ixgbe_hw *hw =
5934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5935         uint32_t vec = IXGBE_MISC_VEC_ID;
5936
5937         if (rte_intr_allow_others(intr_handle))
5938                 vec = IXGBE_RX_VEC_START;
5939         intr->mask |= (1 << vec);
5940         RTE_SET_USED(queue_id);
5941         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5942
5943         rte_intr_ack(intr_handle);
5944
5945         return 0;
5946 }
5947
5948 static int
5949 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5950 {
5951         struct ixgbe_interrupt *intr =
5952                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5953         struct ixgbe_hw *hw =
5954                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5955         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5956         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5957         uint32_t vec = IXGBE_MISC_VEC_ID;
5958
5959         if (rte_intr_allow_others(intr_handle))
5960                 vec = IXGBE_RX_VEC_START;
5961         intr->mask &= ~(1 << vec);
5962         RTE_SET_USED(queue_id);
5963         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5964
5965         return 0;
5966 }
5967
5968 static int
5969 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5970 {
5971         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5972         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5973         uint32_t mask;
5974         struct ixgbe_hw *hw =
5975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5976         struct ixgbe_interrupt *intr =
5977                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5978
5979         if (queue_id < 16) {
5980                 ixgbe_disable_intr(hw);
5981                 intr->mask |= (1 << queue_id);
5982                 ixgbe_enable_intr(dev);
5983         } else if (queue_id < 32) {
5984                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5985                 mask &= (1 << queue_id);
5986                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5987         } else if (queue_id < 64) {
5988                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5989                 mask &= (1 << (queue_id - 32));
5990                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5991         }
5992         rte_intr_ack(intr_handle);
5993
5994         return 0;
5995 }
5996
5997 static int
5998 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5999 {
6000         uint32_t mask;
6001         struct ixgbe_hw *hw =
6002                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6003         struct ixgbe_interrupt *intr =
6004                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6005
6006         if (queue_id < 16) {
6007                 ixgbe_disable_intr(hw);
6008                 intr->mask &= ~(1 << queue_id);
6009                 ixgbe_enable_intr(dev);
6010         } else if (queue_id < 32) {
6011                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6012                 mask &= ~(1 << queue_id);
6013                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6014         } else if (queue_id < 64) {
6015                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6016                 mask &= ~(1 << (queue_id - 32));
6017                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6018         }
6019
6020         return 0;
6021 }
6022
6023 static void
6024 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6025                      uint8_t queue, uint8_t msix_vector)
6026 {
6027         uint32_t tmp, idx;
6028
6029         if (direction == -1) {
6030                 /* other causes */
6031                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6032                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6033                 tmp &= ~0xFF;
6034                 tmp |= msix_vector;
6035                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6036         } else {
6037                 /* rx or tx cause */
6038                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6039                 idx = ((16 * (queue & 1)) + (8 * direction));
6040                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6041                 tmp &= ~(0xFF << idx);
6042                 tmp |= (msix_vector << idx);
6043                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6044         }
6045 }
6046
6047 /**
6048  * set the IVAR registers, mapping interrupt causes to vectors
6049  * @param hw
6050  *  pointer to ixgbe_hw struct
6051  * @direction
6052  *  0 for Rx, 1 for Tx, -1 for other causes
6053  * @queue
6054  *  queue to map the corresponding interrupt to
6055  * @msix_vector
6056  *  the vector to map to the corresponding queue
6057  */
6058 static void
6059 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6060                    uint8_t queue, uint8_t msix_vector)
6061 {
6062         uint32_t tmp, idx;
6063
6064         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6065         if (hw->mac.type == ixgbe_mac_82598EB) {
6066                 if (direction == -1)
6067                         direction = 0;
6068                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6069                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6070                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6071                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6072                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6073         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6074                         (hw->mac.type == ixgbe_mac_X540) ||
6075                         (hw->mac.type == ixgbe_mac_X550) ||
6076                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6077                 if (direction == -1) {
6078                         /* other causes */
6079                         idx = ((queue & 1) * 8);
6080                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6081                         tmp &= ~(0xFF << idx);
6082                         tmp |= (msix_vector << idx);
6083                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6084                 } else {
6085                         /* rx or tx causes */
6086                         idx = ((16 * (queue & 1)) + (8 * direction));
6087                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6088                         tmp &= ~(0xFF << idx);
6089                         tmp |= (msix_vector << idx);
6090                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6091                 }
6092         }
6093 }
6094
6095 static void
6096 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6097 {
6098         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6099         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6100         struct ixgbe_hw *hw =
6101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6102         uint32_t q_idx;
6103         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6104         uint32_t base = IXGBE_MISC_VEC_ID;
6105
6106         /* Configure VF other cause ivar */
6107         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6108
6109         /* won't configure msix register if no mapping is done
6110          * between intr vector and event fd.
6111          */
6112         if (!rte_intr_dp_is_en(intr_handle))
6113                 return;
6114
6115         if (rte_intr_allow_others(intr_handle)) {
6116                 base = IXGBE_RX_VEC_START;
6117                 vector_idx = IXGBE_RX_VEC_START;
6118         }
6119
6120         /* Configure all RX queues of VF */
6121         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6122                 /* Force all queue use vector 0,
6123                  * as IXGBE_VF_MAXMSIVECOTR = 1
6124                  */
6125                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6126                 intr_handle->intr_vec[q_idx] = vector_idx;
6127                 if (vector_idx < base + intr_handle->nb_efd - 1)
6128                         vector_idx++;
6129         }
6130
6131         /* As RX queue setting above show, all queues use the vector 0.
6132          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6133          */
6134         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6135                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6136                         | IXGBE_EITR_CNT_WDIS);
6137 }
6138
6139 /**
6140  * Sets up the hardware to properly generate MSI-X interrupts
6141  * @hw
6142  *  board private structure
6143  */
6144 static void
6145 ixgbe_configure_msix(struct rte_eth_dev *dev)
6146 {
6147         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6148         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6149         struct ixgbe_hw *hw =
6150                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6151         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6152         uint32_t vec = IXGBE_MISC_VEC_ID;
6153         uint32_t mask;
6154         uint32_t gpie;
6155
6156         /* won't configure msix register if no mapping is done
6157          * between intr vector and event fd
6158          * but if misx has been enabled already, need to configure
6159          * auto clean, auto mask and throttling.
6160          */
6161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6162         if (!rte_intr_dp_is_en(intr_handle) &&
6163             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6164                 return;
6165
6166         if (rte_intr_allow_others(intr_handle))
6167                 vec = base = IXGBE_RX_VEC_START;
6168
6169         /* setup GPIE for MSI-x mode */
6170         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6171         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6172                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6173         /* auto clearing and auto setting corresponding bits in EIMS
6174          * when MSI-X interrupt is triggered
6175          */
6176         if (hw->mac.type == ixgbe_mac_82598EB) {
6177                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6178         } else {
6179                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6180                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6181         }
6182         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6183
6184         /* Populate the IVAR table and set the ITR values to the
6185          * corresponding register.
6186          */
6187         if (rte_intr_dp_is_en(intr_handle)) {
6188                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6189                         queue_id++) {
6190                         /* by default, 1:1 mapping */
6191                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6192                         intr_handle->intr_vec[queue_id] = vec;
6193                         if (vec < base + intr_handle->nb_efd - 1)
6194                                 vec++;
6195                 }
6196
6197                 switch (hw->mac.type) {
6198                 case ixgbe_mac_82598EB:
6199                         ixgbe_set_ivar_map(hw, -1,
6200                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6201                                            IXGBE_MISC_VEC_ID);
6202                         break;
6203                 case ixgbe_mac_82599EB:
6204                 case ixgbe_mac_X540:
6205                 case ixgbe_mac_X550:
6206                 case ixgbe_mac_X550EM_x:
6207                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6208                         break;
6209                 default:
6210                         break;
6211                 }
6212         }
6213         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6214                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6215                         | IXGBE_EITR_CNT_WDIS);
6216
6217         /* set up to autoclear timer, and the vectors */
6218         mask = IXGBE_EIMS_ENABLE_MASK;
6219         mask &= ~(IXGBE_EIMS_OTHER |
6220                   IXGBE_EIMS_MAILBOX |
6221                   IXGBE_EIMS_LSC);
6222
6223         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6224 }
6225
6226 int
6227 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6228                            uint16_t queue_idx, uint16_t tx_rate)
6229 {
6230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6231         struct rte_eth_rxmode *rxmode;
6232         uint32_t rf_dec, rf_int;
6233         uint32_t bcnrc_val;
6234         uint16_t link_speed = dev->data->dev_link.link_speed;
6235
6236         if (queue_idx >= hw->mac.max_tx_queues)
6237                 return -EINVAL;
6238
6239         if (tx_rate != 0) {
6240                 /* Calculate the rate factor values to set */
6241                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6242                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6243                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6244
6245                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6246                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6247                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6248                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6249         } else {
6250                 bcnrc_val = 0;
6251         }
6252
6253         rxmode = &dev->data->dev_conf.rxmode;
6254         /*
6255          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6256          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6257          * set as 0x4.
6258          */
6259         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6260             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6261                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6262                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6263         else
6264                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6265                         IXGBE_MMW_SIZE_DEFAULT);
6266
6267         /* Set RTTBCNRC of queue X */
6268         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6269         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6270         IXGBE_WRITE_FLUSH(hw);
6271
6272         return 0;
6273 }
6274
6275 static int
6276 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6277                      __rte_unused uint32_t index,
6278                      __rte_unused uint32_t pool)
6279 {
6280         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6281         int diag;
6282
6283         /*
6284          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6285          * operation. Trap this case to avoid exhausting the [very limited]
6286          * set of PF resources used to store VF MAC addresses.
6287          */
6288         if (memcmp(hw->mac.perm_addr, mac_addr,
6289                         sizeof(struct rte_ether_addr)) == 0)
6290                 return -1;
6291         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6292         if (diag != 0)
6293                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6294                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6295                             mac_addr->addr_bytes[0],
6296                             mac_addr->addr_bytes[1],
6297                             mac_addr->addr_bytes[2],
6298                             mac_addr->addr_bytes[3],
6299                             mac_addr->addr_bytes[4],
6300                             mac_addr->addr_bytes[5],
6301                             diag);
6302         return diag;
6303 }
6304
6305 static void
6306 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6307 {
6308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6309         struct rte_ether_addr *perm_addr =
6310                 (struct rte_ether_addr *)hw->mac.perm_addr;
6311         struct rte_ether_addr *mac_addr;
6312         uint32_t i;
6313         int diag;
6314
6315         /*
6316          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6317          * not support the deletion of a given MAC address.
6318          * Instead, it imposes to delete all MAC addresses, then to add again
6319          * all MAC addresses with the exception of the one to be deleted.
6320          */
6321         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6322
6323         /*
6324          * Add again all MAC addresses, with the exception of the deleted one
6325          * and of the permanent MAC address.
6326          */
6327         for (i = 0, mac_addr = dev->data->mac_addrs;
6328              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6329                 /* Skip the deleted MAC address */
6330                 if (i == index)
6331                         continue;
6332                 /* Skip NULL MAC addresses */
6333                 if (rte_is_zero_ether_addr(mac_addr))
6334                         continue;
6335                 /* Skip the permanent MAC address */
6336                 if (memcmp(perm_addr, mac_addr,
6337                                 sizeof(struct rte_ether_addr)) == 0)
6338                         continue;
6339                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6340                 if (diag != 0)
6341                         PMD_DRV_LOG(ERR,
6342                                     "Adding again MAC address "
6343                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6344                                     "diag=%d",
6345                                     mac_addr->addr_bytes[0],
6346                                     mac_addr->addr_bytes[1],
6347                                     mac_addr->addr_bytes[2],
6348                                     mac_addr->addr_bytes[3],
6349                                     mac_addr->addr_bytes[4],
6350                                     mac_addr->addr_bytes[5],
6351                                     diag);
6352         }
6353 }
6354
6355 static int
6356 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6357                         struct rte_ether_addr *addr)
6358 {
6359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6360
6361         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6362
6363         return 0;
6364 }
6365
6366 int
6367 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6368                         struct rte_eth_syn_filter *filter,
6369                         bool add)
6370 {
6371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6372         struct ixgbe_filter_info *filter_info =
6373                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6374         uint32_t syn_info;
6375         uint32_t synqf;
6376
6377         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6378                 return -EINVAL;
6379
6380         syn_info = filter_info->syn_info;
6381
6382         if (add) {
6383                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6384                         return -EINVAL;
6385                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6386                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6387
6388                 if (filter->hig_pri)
6389                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6390                 else
6391                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6392         } else {
6393                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6394                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6395                         return -ENOENT;
6396                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6397         }
6398
6399         filter_info->syn_info = synqf;
6400         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6401         IXGBE_WRITE_FLUSH(hw);
6402         return 0;
6403 }
6404
6405 static int
6406 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6407                         struct rte_eth_syn_filter *filter)
6408 {
6409         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6410         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6411
6412         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6413                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6414                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6415                 return 0;
6416         }
6417         return -ENOENT;
6418 }
6419
6420 static int
6421 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6422                         enum rte_filter_op filter_op,
6423                         void *arg)
6424 {
6425         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6426         int ret;
6427
6428         MAC_TYPE_FILTER_SUP(hw->mac.type);
6429
6430         if (filter_op == RTE_ETH_FILTER_NOP)
6431                 return 0;
6432
6433         if (arg == NULL) {
6434                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6435                             filter_op);
6436                 return -EINVAL;
6437         }
6438
6439         switch (filter_op) {
6440         case RTE_ETH_FILTER_ADD:
6441                 ret = ixgbe_syn_filter_set(dev,
6442                                 (struct rte_eth_syn_filter *)arg,
6443                                 TRUE);
6444                 break;
6445         case RTE_ETH_FILTER_DELETE:
6446                 ret = ixgbe_syn_filter_set(dev,
6447                                 (struct rte_eth_syn_filter *)arg,
6448                                 FALSE);
6449                 break;
6450         case RTE_ETH_FILTER_GET:
6451                 ret = ixgbe_syn_filter_get(dev,
6452                                 (struct rte_eth_syn_filter *)arg);
6453                 break;
6454         default:
6455                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6456                 ret = -EINVAL;
6457                 break;
6458         }
6459
6460         return ret;
6461 }
6462
6463
6464 static inline enum ixgbe_5tuple_protocol
6465 convert_protocol_type(uint8_t protocol_value)
6466 {
6467         if (protocol_value == IPPROTO_TCP)
6468                 return IXGBE_FILTER_PROTOCOL_TCP;
6469         else if (protocol_value == IPPROTO_UDP)
6470                 return IXGBE_FILTER_PROTOCOL_UDP;
6471         else if (protocol_value == IPPROTO_SCTP)
6472                 return IXGBE_FILTER_PROTOCOL_SCTP;
6473         else
6474                 return IXGBE_FILTER_PROTOCOL_NONE;
6475 }
6476
6477 /* inject a 5-tuple filter to HW */
6478 static inline void
6479 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6480                            struct ixgbe_5tuple_filter *filter)
6481 {
6482         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6483         int i;
6484         uint32_t ftqf, sdpqf;
6485         uint32_t l34timir = 0;
6486         uint8_t mask = 0xff;
6487
6488         i = filter->index;
6489
6490         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6491                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6492         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6493
6494         ftqf = (uint32_t)(filter->filter_info.proto &
6495                 IXGBE_FTQF_PROTOCOL_MASK);
6496         ftqf |= (uint32_t)((filter->filter_info.priority &
6497                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6498         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6499                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6500         if (filter->filter_info.dst_ip_mask == 0)
6501                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6502         if (filter->filter_info.src_port_mask == 0)
6503                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6504         if (filter->filter_info.dst_port_mask == 0)
6505                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6506         if (filter->filter_info.proto_mask == 0)
6507                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6508         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6509         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6510         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6511
6512         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6513         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6514         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6515         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6516
6517         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6518         l34timir |= (uint32_t)(filter->queue <<
6519                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6520         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6521 }
6522
6523 /*
6524  * add a 5tuple filter
6525  *
6526  * @param
6527  * dev: Pointer to struct rte_eth_dev.
6528  * index: the index the filter allocates.
6529  * filter: ponter to the filter that will be added.
6530  * rx_queue: the queue id the filter assigned to.
6531  *
6532  * @return
6533  *    - On success, zero.
6534  *    - On failure, a negative value.
6535  */
6536 static int
6537 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6538                         struct ixgbe_5tuple_filter *filter)
6539 {
6540         struct ixgbe_filter_info *filter_info =
6541                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6542         int i, idx, shift;
6543
6544         /*
6545          * look for an unused 5tuple filter index,
6546          * and insert the filter to list.
6547          */
6548         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6549                 idx = i / (sizeof(uint32_t) * NBBY);
6550                 shift = i % (sizeof(uint32_t) * NBBY);
6551                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6552                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6553                         filter->index = i;
6554                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6555                                           filter,
6556                                           entries);
6557                         break;
6558                 }
6559         }
6560         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6561                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6562                 return -ENOSYS;
6563         }
6564
6565         ixgbe_inject_5tuple_filter(dev, filter);
6566
6567         return 0;
6568 }
6569
6570 /*
6571  * remove a 5tuple filter
6572  *
6573  * @param
6574  * dev: Pointer to struct rte_eth_dev.
6575  * filter: the pointer of the filter will be removed.
6576  */
6577 static void
6578 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6579                         struct ixgbe_5tuple_filter *filter)
6580 {
6581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6582         struct ixgbe_filter_info *filter_info =
6583                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6584         uint16_t index = filter->index;
6585
6586         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6587                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6588         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6589         rte_free(filter);
6590
6591         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6592         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6593         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6594         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6595         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6596 }
6597
6598 static int
6599 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6600 {
6601         struct ixgbe_hw *hw;
6602         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6603         struct rte_eth_dev_data *dev_data = dev->data;
6604
6605         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6606
6607         if (mtu < RTE_ETHER_MIN_MTU ||
6608                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6609                 return -EINVAL;
6610
6611         /* If device is started, refuse mtu that requires the support of
6612          * scattered packets when this feature has not been enabled before.
6613          */
6614         if (dev_data->dev_started && !dev_data->scattered_rx &&
6615             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6616              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6617                 PMD_INIT_LOG(ERR, "Stop port first.");
6618                 return -EINVAL;
6619         }
6620
6621         /*
6622          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6623          * request of the version 2.0 of the mailbox API.
6624          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6625          * of the mailbox API.
6626          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6627          * prior to 3.11.33 which contains the following change:
6628          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6629          */
6630         ixgbevf_rlpml_set_vf(hw, max_frame);
6631
6632         /* update max frame size */
6633         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6634         return 0;
6635 }
6636
6637 static inline struct ixgbe_5tuple_filter *
6638 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6639                         struct ixgbe_5tuple_filter_info *key)
6640 {
6641         struct ixgbe_5tuple_filter *it;
6642
6643         TAILQ_FOREACH(it, filter_list, entries) {
6644                 if (memcmp(key, &it->filter_info,
6645                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6646                         return it;
6647                 }
6648         }
6649         return NULL;
6650 }
6651
6652 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6653 static inline int
6654 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6655                         struct ixgbe_5tuple_filter_info *filter_info)
6656 {
6657         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6658                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6659                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6660                 return -EINVAL;
6661
6662         switch (filter->dst_ip_mask) {
6663         case UINT32_MAX:
6664                 filter_info->dst_ip_mask = 0;
6665                 filter_info->dst_ip = filter->dst_ip;
6666                 break;
6667         case 0:
6668                 filter_info->dst_ip_mask = 1;
6669                 break;
6670         default:
6671                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6672                 return -EINVAL;
6673         }
6674
6675         switch (filter->src_ip_mask) {
6676         case UINT32_MAX:
6677                 filter_info->src_ip_mask = 0;
6678                 filter_info->src_ip = filter->src_ip;
6679                 break;
6680         case 0:
6681                 filter_info->src_ip_mask = 1;
6682                 break;
6683         default:
6684                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6685                 return -EINVAL;
6686         }
6687
6688         switch (filter->dst_port_mask) {
6689         case UINT16_MAX:
6690                 filter_info->dst_port_mask = 0;
6691                 filter_info->dst_port = filter->dst_port;
6692                 break;
6693         case 0:
6694                 filter_info->dst_port_mask = 1;
6695                 break;
6696         default:
6697                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6698                 return -EINVAL;
6699         }
6700
6701         switch (filter->src_port_mask) {
6702         case UINT16_MAX:
6703                 filter_info->src_port_mask = 0;
6704                 filter_info->src_port = filter->src_port;
6705                 break;
6706         case 0:
6707                 filter_info->src_port_mask = 1;
6708                 break;
6709         default:
6710                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6711                 return -EINVAL;
6712         }
6713
6714         switch (filter->proto_mask) {
6715         case UINT8_MAX:
6716                 filter_info->proto_mask = 0;
6717                 filter_info->proto =
6718                         convert_protocol_type(filter->proto);
6719                 break;
6720         case 0:
6721                 filter_info->proto_mask = 1;
6722                 break;
6723         default:
6724                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6725                 return -EINVAL;
6726         }
6727
6728         filter_info->priority = (uint8_t)filter->priority;
6729         return 0;
6730 }
6731
6732 /*
6733  * add or delete a ntuple filter
6734  *
6735  * @param
6736  * dev: Pointer to struct rte_eth_dev.
6737  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6738  * add: if true, add filter, if false, remove filter
6739  *
6740  * @return
6741  *    - On success, zero.
6742  *    - On failure, a negative value.
6743  */
6744 int
6745 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6746                         struct rte_eth_ntuple_filter *ntuple_filter,
6747                         bool add)
6748 {
6749         struct ixgbe_filter_info *filter_info =
6750                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6751         struct ixgbe_5tuple_filter_info filter_5tuple;
6752         struct ixgbe_5tuple_filter *filter;
6753         int ret;
6754
6755         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6756                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6757                 return -EINVAL;
6758         }
6759
6760         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6761         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6762         if (ret < 0)
6763                 return ret;
6764
6765         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6766                                          &filter_5tuple);
6767         if (filter != NULL && add) {
6768                 PMD_DRV_LOG(ERR, "filter exists.");
6769                 return -EEXIST;
6770         }
6771         if (filter == NULL && !add) {
6772                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6773                 return -ENOENT;
6774         }
6775
6776         if (add) {
6777                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6778                                 sizeof(struct ixgbe_5tuple_filter), 0);
6779                 if (filter == NULL)
6780                         return -ENOMEM;
6781                 rte_memcpy(&filter->filter_info,
6782                                  &filter_5tuple,
6783                                  sizeof(struct ixgbe_5tuple_filter_info));
6784                 filter->queue = ntuple_filter->queue;
6785                 ret = ixgbe_add_5tuple_filter(dev, filter);
6786                 if (ret < 0) {
6787                         rte_free(filter);
6788                         return ret;
6789                 }
6790         } else
6791                 ixgbe_remove_5tuple_filter(dev, filter);
6792
6793         return 0;
6794 }
6795
6796 /*
6797  * get a ntuple filter
6798  *
6799  * @param
6800  * dev: Pointer to struct rte_eth_dev.
6801  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6802  *
6803  * @return
6804  *    - On success, zero.
6805  *    - On failure, a negative value.
6806  */
6807 static int
6808 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6809                         struct rte_eth_ntuple_filter *ntuple_filter)
6810 {
6811         struct ixgbe_filter_info *filter_info =
6812                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6813         struct ixgbe_5tuple_filter_info filter_5tuple;
6814         struct ixgbe_5tuple_filter *filter;
6815         int ret;
6816
6817         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6818                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6819                 return -EINVAL;
6820         }
6821
6822         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6823         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6824         if (ret < 0)
6825                 return ret;
6826
6827         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6828                                          &filter_5tuple);
6829         if (filter == NULL) {
6830                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6831                 return -ENOENT;
6832         }
6833         ntuple_filter->queue = filter->queue;
6834         return 0;
6835 }
6836
6837 /*
6838  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6839  * @dev: pointer to rte_eth_dev structure
6840  * @filter_op:operation will be taken.
6841  * @arg: a pointer to specific structure corresponding to the filter_op
6842  *
6843  * @return
6844  *    - On success, zero.
6845  *    - On failure, a negative value.
6846  */
6847 static int
6848 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6849                                 enum rte_filter_op filter_op,
6850                                 void *arg)
6851 {
6852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6853         int ret;
6854
6855         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6856
6857         if (filter_op == RTE_ETH_FILTER_NOP)
6858                 return 0;
6859
6860         if (arg == NULL) {
6861                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6862                             filter_op);
6863                 return -EINVAL;
6864         }
6865
6866         switch (filter_op) {
6867         case RTE_ETH_FILTER_ADD:
6868                 ret = ixgbe_add_del_ntuple_filter(dev,
6869                         (struct rte_eth_ntuple_filter *)arg,
6870                         TRUE);
6871                 break;
6872         case RTE_ETH_FILTER_DELETE:
6873                 ret = ixgbe_add_del_ntuple_filter(dev,
6874                         (struct rte_eth_ntuple_filter *)arg,
6875                         FALSE);
6876                 break;
6877         case RTE_ETH_FILTER_GET:
6878                 ret = ixgbe_get_ntuple_filter(dev,
6879                         (struct rte_eth_ntuple_filter *)arg);
6880                 break;
6881         default:
6882                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6883                 ret = -EINVAL;
6884                 break;
6885         }
6886         return ret;
6887 }
6888
6889 int
6890 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6891                         struct rte_eth_ethertype_filter *filter,
6892                         bool add)
6893 {
6894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6895         struct ixgbe_filter_info *filter_info =
6896                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6897         uint32_t etqf = 0;
6898         uint32_t etqs = 0;
6899         int ret;
6900         struct ixgbe_ethertype_filter ethertype_filter;
6901
6902         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6903                 return -EINVAL;
6904
6905         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6906                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6907                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6908                         " ethertype filter.", filter->ether_type);
6909                 return -EINVAL;
6910         }
6911
6912         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6913                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6914                 return -EINVAL;
6915         }
6916         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6917                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6918                 return -EINVAL;
6919         }
6920
6921         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6922         if (ret >= 0 && add) {
6923                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6924                             filter->ether_type);
6925                 return -EEXIST;
6926         }
6927         if (ret < 0 && !add) {
6928                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6929                             filter->ether_type);
6930                 return -ENOENT;
6931         }
6932
6933         if (add) {
6934                 etqf = IXGBE_ETQF_FILTER_EN;
6935                 etqf |= (uint32_t)filter->ether_type;
6936                 etqs |= (uint32_t)((filter->queue <<
6937                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6938                                     IXGBE_ETQS_RX_QUEUE);
6939                 etqs |= IXGBE_ETQS_QUEUE_EN;
6940
6941                 ethertype_filter.ethertype = filter->ether_type;
6942                 ethertype_filter.etqf = etqf;
6943                 ethertype_filter.etqs = etqs;
6944                 ethertype_filter.conf = FALSE;
6945                 ret = ixgbe_ethertype_filter_insert(filter_info,
6946                                                     &ethertype_filter);
6947                 if (ret < 0) {
6948                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6949                         return -ENOSPC;
6950                 }
6951         } else {
6952                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6953                 if (ret < 0)
6954                         return -ENOSYS;
6955         }
6956         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6957         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6958         IXGBE_WRITE_FLUSH(hw);
6959
6960         return 0;
6961 }
6962
6963 static int
6964 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6965                         struct rte_eth_ethertype_filter *filter)
6966 {
6967         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6968         struct ixgbe_filter_info *filter_info =
6969                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6970         uint32_t etqf, etqs;
6971         int ret;
6972
6973         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6974         if (ret < 0) {
6975                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6976                             filter->ether_type);
6977                 return -ENOENT;
6978         }
6979
6980         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6981         if (etqf & IXGBE_ETQF_FILTER_EN) {
6982                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6983                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6984                 filter->flags = 0;
6985                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6986                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6987                 return 0;
6988         }
6989         return -ENOENT;
6990 }
6991
6992 /*
6993  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6994  * @dev: pointer to rte_eth_dev structure
6995  * @filter_op:operation will be taken.
6996  * @arg: a pointer to specific structure corresponding to the filter_op
6997  */
6998 static int
6999 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7000                                 enum rte_filter_op filter_op,
7001                                 void *arg)
7002 {
7003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7004         int ret;
7005
7006         MAC_TYPE_FILTER_SUP(hw->mac.type);
7007
7008         if (filter_op == RTE_ETH_FILTER_NOP)
7009                 return 0;
7010
7011         if (arg == NULL) {
7012                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7013                             filter_op);
7014                 return -EINVAL;
7015         }
7016
7017         switch (filter_op) {
7018         case RTE_ETH_FILTER_ADD:
7019                 ret = ixgbe_add_del_ethertype_filter(dev,
7020                         (struct rte_eth_ethertype_filter *)arg,
7021                         TRUE);
7022                 break;
7023         case RTE_ETH_FILTER_DELETE:
7024                 ret = ixgbe_add_del_ethertype_filter(dev,
7025                         (struct rte_eth_ethertype_filter *)arg,
7026                         FALSE);
7027                 break;
7028         case RTE_ETH_FILTER_GET:
7029                 ret = ixgbe_get_ethertype_filter(dev,
7030                         (struct rte_eth_ethertype_filter *)arg);
7031                 break;
7032         default:
7033                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7034                 ret = -EINVAL;
7035                 break;
7036         }
7037         return ret;
7038 }
7039
7040 static int
7041 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7042                      enum rte_filter_type filter_type,
7043                      enum rte_filter_op filter_op,
7044                      void *arg)
7045 {
7046         int ret = 0;
7047
7048         switch (filter_type) {
7049         case RTE_ETH_FILTER_NTUPLE:
7050                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7051                 break;
7052         case RTE_ETH_FILTER_ETHERTYPE:
7053                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7054                 break;
7055         case RTE_ETH_FILTER_SYN:
7056                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7057                 break;
7058         case RTE_ETH_FILTER_FDIR:
7059                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7060                 break;
7061         case RTE_ETH_FILTER_L2_TUNNEL:
7062                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7063                 break;
7064         case RTE_ETH_FILTER_GENERIC:
7065                 if (filter_op != RTE_ETH_FILTER_GET)
7066                         return -EINVAL;
7067                 *(const void **)arg = &ixgbe_flow_ops;
7068                 break;
7069         default:
7070                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7071                                                         filter_type);
7072                 ret = -EINVAL;
7073                 break;
7074         }
7075
7076         return ret;
7077 }
7078
7079 static u8 *
7080 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7081                         u8 **mc_addr_ptr, u32 *vmdq)
7082 {
7083         u8 *mc_addr;
7084
7085         *vmdq = 0;
7086         mc_addr = *mc_addr_ptr;
7087         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7088         return mc_addr;
7089 }
7090
7091 static int
7092 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7093                           struct rte_ether_addr *mc_addr_set,
7094                           uint32_t nb_mc_addr)
7095 {
7096         struct ixgbe_hw *hw;
7097         u8 *mc_addr_list;
7098
7099         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7100         mc_addr_list = (u8 *)mc_addr_set;
7101         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7102                                          ixgbe_dev_addr_list_itr, TRUE);
7103 }
7104
7105 static uint64_t
7106 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7107 {
7108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7109         uint64_t systime_cycles;
7110
7111         switch (hw->mac.type) {
7112         case ixgbe_mac_X550:
7113         case ixgbe_mac_X550EM_x:
7114         case ixgbe_mac_X550EM_a:
7115                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7116                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7117                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7118                                 * NSEC_PER_SEC;
7119                 break;
7120         default:
7121                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7122                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7123                                 << 32;
7124         }
7125
7126         return systime_cycles;
7127 }
7128
7129 static uint64_t
7130 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7131 {
7132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7133         uint64_t rx_tstamp_cycles;
7134
7135         switch (hw->mac.type) {
7136         case ixgbe_mac_X550:
7137         case ixgbe_mac_X550EM_x:
7138         case ixgbe_mac_X550EM_a:
7139                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7140                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7141                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7142                                 * NSEC_PER_SEC;
7143                 break;
7144         default:
7145                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7146                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7147                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7148                                 << 32;
7149         }
7150
7151         return rx_tstamp_cycles;
7152 }
7153
7154 static uint64_t
7155 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7156 {
7157         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7158         uint64_t tx_tstamp_cycles;
7159
7160         switch (hw->mac.type) {
7161         case ixgbe_mac_X550:
7162         case ixgbe_mac_X550EM_x:
7163         case ixgbe_mac_X550EM_a:
7164                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7165                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7166                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7167                                 * NSEC_PER_SEC;
7168                 break;
7169         default:
7170                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7171                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7172                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7173                                 << 32;
7174         }
7175
7176         return tx_tstamp_cycles;
7177 }
7178
7179 static void
7180 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7181 {
7182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7183         struct ixgbe_adapter *adapter = dev->data->dev_private;
7184         struct rte_eth_link link;
7185         uint32_t incval = 0;
7186         uint32_t shift = 0;
7187
7188         /* Get current link speed. */
7189         ixgbe_dev_link_update(dev, 1);
7190         rte_eth_linkstatus_get(dev, &link);
7191
7192         switch (link.link_speed) {
7193         case ETH_SPEED_NUM_100M:
7194                 incval = IXGBE_INCVAL_100;
7195                 shift = IXGBE_INCVAL_SHIFT_100;
7196                 break;
7197         case ETH_SPEED_NUM_1G:
7198                 incval = IXGBE_INCVAL_1GB;
7199                 shift = IXGBE_INCVAL_SHIFT_1GB;
7200                 break;
7201         case ETH_SPEED_NUM_10G:
7202         default:
7203                 incval = IXGBE_INCVAL_10GB;
7204                 shift = IXGBE_INCVAL_SHIFT_10GB;
7205                 break;
7206         }
7207
7208         switch (hw->mac.type) {
7209         case ixgbe_mac_X550:
7210         case ixgbe_mac_X550EM_x:
7211         case ixgbe_mac_X550EM_a:
7212                 /* Independent of link speed. */
7213                 incval = 1;
7214                 /* Cycles read will be interpreted as ns. */
7215                 shift = 0;
7216                 /* Fall-through */
7217         case ixgbe_mac_X540:
7218                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7219                 break;
7220         case ixgbe_mac_82599EB:
7221                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7222                 shift -= IXGBE_INCVAL_SHIFT_82599;
7223                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7224                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7225                 break;
7226         default:
7227                 /* Not supported. */
7228                 return;
7229         }
7230
7231         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7232         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7233         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7234
7235         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7236         adapter->systime_tc.cc_shift = shift;
7237         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7238
7239         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7240         adapter->rx_tstamp_tc.cc_shift = shift;
7241         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7242
7243         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7244         adapter->tx_tstamp_tc.cc_shift = shift;
7245         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7246 }
7247
7248 static int
7249 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7250 {
7251         struct ixgbe_adapter *adapter = dev->data->dev_private;
7252
7253         adapter->systime_tc.nsec += delta;
7254         adapter->rx_tstamp_tc.nsec += delta;
7255         adapter->tx_tstamp_tc.nsec += delta;
7256
7257         return 0;
7258 }
7259
7260 static int
7261 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7262 {
7263         uint64_t ns;
7264         struct ixgbe_adapter *adapter = dev->data->dev_private;
7265
7266         ns = rte_timespec_to_ns(ts);
7267         /* Set the timecounters to a new value. */
7268         adapter->systime_tc.nsec = ns;
7269         adapter->rx_tstamp_tc.nsec = ns;
7270         adapter->tx_tstamp_tc.nsec = ns;
7271
7272         return 0;
7273 }
7274
7275 static int
7276 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7277 {
7278         uint64_t ns, systime_cycles;
7279         struct ixgbe_adapter *adapter = dev->data->dev_private;
7280
7281         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7282         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7283         *ts = rte_ns_to_timespec(ns);
7284
7285         return 0;
7286 }
7287
7288 static int
7289 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7290 {
7291         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7292         uint32_t tsync_ctl;
7293         uint32_t tsauxc;
7294
7295         /* Stop the timesync system time. */
7296         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7297         /* Reset the timesync system time value. */
7298         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7299         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7300
7301         /* Enable system time for platforms where it isn't on by default. */
7302         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7303         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7304         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7305
7306         ixgbe_start_timecounters(dev);
7307
7308         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7309         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7310                         (RTE_ETHER_TYPE_1588 |
7311                          IXGBE_ETQF_FILTER_EN |
7312                          IXGBE_ETQF_1588));
7313
7314         /* Enable timestamping of received PTP packets. */
7315         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7316         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7317         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7318
7319         /* Enable timestamping of transmitted PTP packets. */
7320         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7321         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7322         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7323
7324         IXGBE_WRITE_FLUSH(hw);
7325
7326         return 0;
7327 }
7328
7329 static int
7330 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7331 {
7332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7333         uint32_t tsync_ctl;
7334
7335         /* Disable timestamping of transmitted PTP packets. */
7336         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7337         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7338         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7339
7340         /* Disable timestamping of received PTP packets. */
7341         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7342         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7343         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7344
7345         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7346         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7347
7348         /* Stop incrementating the System Time registers. */
7349         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7350
7351         return 0;
7352 }
7353
7354 static int
7355 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7356                                  struct timespec *timestamp,
7357                                  uint32_t flags __rte_unused)
7358 {
7359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7360         struct ixgbe_adapter *adapter = dev->data->dev_private;
7361         uint32_t tsync_rxctl;
7362         uint64_t rx_tstamp_cycles;
7363         uint64_t ns;
7364
7365         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7366         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7367                 return -EINVAL;
7368
7369         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7370         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7371         *timestamp = rte_ns_to_timespec(ns);
7372
7373         return  0;
7374 }
7375
7376 static int
7377 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7378                                  struct timespec *timestamp)
7379 {
7380         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7381         struct ixgbe_adapter *adapter = dev->data->dev_private;
7382         uint32_t tsync_txctl;
7383         uint64_t tx_tstamp_cycles;
7384         uint64_t ns;
7385
7386         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7387         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7388                 return -EINVAL;
7389
7390         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7391         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7392         *timestamp = rte_ns_to_timespec(ns);
7393
7394         return 0;
7395 }
7396
7397 static int
7398 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7399 {
7400         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7401         int count = 0;
7402         int g_ind = 0;
7403         const struct reg_info *reg_group;
7404         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7405                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7406
7407         while ((reg_group = reg_set[g_ind++]))
7408                 count += ixgbe_regs_group_count(reg_group);
7409
7410         return count;
7411 }
7412
7413 static int
7414 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7415 {
7416         int count = 0;
7417         int g_ind = 0;
7418         const struct reg_info *reg_group;
7419
7420         while ((reg_group = ixgbevf_regs[g_ind++]))
7421                 count += ixgbe_regs_group_count(reg_group);
7422
7423         return count;
7424 }
7425
7426 static int
7427 ixgbe_get_regs(struct rte_eth_dev *dev,
7428               struct rte_dev_reg_info *regs)
7429 {
7430         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7431         uint32_t *data = regs->data;
7432         int g_ind = 0;
7433         int count = 0;
7434         const struct reg_info *reg_group;
7435         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7436                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7437
7438         if (data == NULL) {
7439                 regs->length = ixgbe_get_reg_length(dev);
7440                 regs->width = sizeof(uint32_t);
7441                 return 0;
7442         }
7443
7444         /* Support only full register dump */
7445         if ((regs->length == 0) ||
7446             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7447                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7448                         hw->device_id;
7449                 while ((reg_group = reg_set[g_ind++]))
7450                         count += ixgbe_read_regs_group(dev, &data[count],
7451                                 reg_group);
7452                 return 0;
7453         }
7454
7455         return -ENOTSUP;
7456 }
7457
7458 static int
7459 ixgbevf_get_regs(struct rte_eth_dev *dev,
7460                 struct rte_dev_reg_info *regs)
7461 {
7462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7463         uint32_t *data = regs->data;
7464         int g_ind = 0;
7465         int count = 0;
7466         const struct reg_info *reg_group;
7467
7468         if (data == NULL) {
7469                 regs->length = ixgbevf_get_reg_length(dev);
7470                 regs->width = sizeof(uint32_t);
7471                 return 0;
7472         }
7473
7474         /* Support only full register dump */
7475         if ((regs->length == 0) ||
7476             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7477                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7478                         hw->device_id;
7479                 while ((reg_group = ixgbevf_regs[g_ind++]))
7480                         count += ixgbe_read_regs_group(dev, &data[count],
7481                                                       reg_group);
7482                 return 0;
7483         }
7484
7485         return -ENOTSUP;
7486 }
7487
7488 static int
7489 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7490 {
7491         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7492
7493         /* Return unit is byte count */
7494         return hw->eeprom.word_size * 2;
7495 }
7496
7497 static int
7498 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7499                 struct rte_dev_eeprom_info *in_eeprom)
7500 {
7501         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7502         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7503         uint16_t *data = in_eeprom->data;
7504         int first, length;
7505
7506         first = in_eeprom->offset >> 1;
7507         length = in_eeprom->length >> 1;
7508         if ((first > hw->eeprom.word_size) ||
7509             ((first + length) > hw->eeprom.word_size))
7510                 return -EINVAL;
7511
7512         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7513
7514         return eeprom->ops.read_buffer(hw, first, length, data);
7515 }
7516
7517 static int
7518 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7519                 struct rte_dev_eeprom_info *in_eeprom)
7520 {
7521         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7522         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7523         uint16_t *data = in_eeprom->data;
7524         int first, length;
7525
7526         first = in_eeprom->offset >> 1;
7527         length = in_eeprom->length >> 1;
7528         if ((first > hw->eeprom.word_size) ||
7529             ((first + length) > hw->eeprom.word_size))
7530                 return -EINVAL;
7531
7532         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7533
7534         return eeprom->ops.write_buffer(hw,  first, length, data);
7535 }
7536
7537 static int
7538 ixgbe_get_module_info(struct rte_eth_dev *dev,
7539                       struct rte_eth_dev_module_info *modinfo)
7540 {
7541         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7542         uint32_t status;
7543         uint8_t sff8472_rev, addr_mode;
7544         bool page_swap = false;
7545
7546         /* Check whether we support SFF-8472 or not */
7547         status = hw->phy.ops.read_i2c_eeprom(hw,
7548                                              IXGBE_SFF_SFF_8472_COMP,
7549                                              &sff8472_rev);
7550         if (status != 0)
7551                 return -EIO;
7552
7553         /* addressing mode is not supported */
7554         status = hw->phy.ops.read_i2c_eeprom(hw,
7555                                              IXGBE_SFF_SFF_8472_SWAP,
7556                                              &addr_mode);
7557         if (status != 0)
7558                 return -EIO;
7559
7560         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7561                 PMD_DRV_LOG(ERR,
7562                             "Address change required to access page 0xA2, "
7563                             "but not supported. Please report the module "
7564                             "type to the driver maintainers.");
7565                 page_swap = true;
7566         }
7567
7568         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7569                 /* We have a SFP, but it does not support SFF-8472 */
7570                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7571                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7572         } else {
7573                 /* We have a SFP which supports a revision of SFF-8472. */
7574                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7575                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7576         }
7577
7578         return 0;
7579 }
7580
7581 static int
7582 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7583                         struct rte_dev_eeprom_info *info)
7584 {
7585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7586         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7587         uint8_t databyte = 0xFF;
7588         uint8_t *data = info->data;
7589         uint32_t i = 0;
7590
7591         if (info->length == 0)
7592                 return -EINVAL;
7593
7594         for (i = info->offset; i < info->offset + info->length; i++) {
7595                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7596                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7597                 else
7598                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7599
7600                 if (status != 0)
7601                         return -EIO;
7602
7603                 data[i - info->offset] = databyte;
7604         }
7605
7606         return 0;
7607 }
7608
7609 uint16_t
7610 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7611         switch (mac_type) {
7612         case ixgbe_mac_X550:
7613         case ixgbe_mac_X550EM_x:
7614         case ixgbe_mac_X550EM_a:
7615                 return ETH_RSS_RETA_SIZE_512;
7616         case ixgbe_mac_X550_vf:
7617         case ixgbe_mac_X550EM_x_vf:
7618         case ixgbe_mac_X550EM_a_vf:
7619                 return ETH_RSS_RETA_SIZE_64;
7620         case ixgbe_mac_X540_vf:
7621         case ixgbe_mac_82599_vf:
7622                 return 0;
7623         default:
7624                 return ETH_RSS_RETA_SIZE_128;
7625         }
7626 }
7627
7628 uint32_t
7629 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7630         switch (mac_type) {
7631         case ixgbe_mac_X550:
7632         case ixgbe_mac_X550EM_x:
7633         case ixgbe_mac_X550EM_a:
7634                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7635                         return IXGBE_RETA(reta_idx >> 2);
7636                 else
7637                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7638         case ixgbe_mac_X550_vf:
7639         case ixgbe_mac_X550EM_x_vf:
7640         case ixgbe_mac_X550EM_a_vf:
7641                 return IXGBE_VFRETA(reta_idx >> 2);
7642         default:
7643                 return IXGBE_RETA(reta_idx >> 2);
7644         }
7645 }
7646
7647 uint32_t
7648 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7649         switch (mac_type) {
7650         case ixgbe_mac_X550_vf:
7651         case ixgbe_mac_X550EM_x_vf:
7652         case ixgbe_mac_X550EM_a_vf:
7653                 return IXGBE_VFMRQC;
7654         default:
7655                 return IXGBE_MRQC;
7656         }
7657 }
7658
7659 uint32_t
7660 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7661         switch (mac_type) {
7662         case ixgbe_mac_X550_vf:
7663         case ixgbe_mac_X550EM_x_vf:
7664         case ixgbe_mac_X550EM_a_vf:
7665                 return IXGBE_VFRSSRK(i);
7666         default:
7667                 return IXGBE_RSSRK(i);
7668         }
7669 }
7670
7671 bool
7672 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7673         switch (mac_type) {
7674         case ixgbe_mac_82599_vf:
7675         case ixgbe_mac_X540_vf:
7676                 return 0;
7677         default:
7678                 return 1;
7679         }
7680 }
7681
7682 static int
7683 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7684                         struct rte_eth_dcb_info *dcb_info)
7685 {
7686         struct ixgbe_dcb_config *dcb_config =
7687                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7688         struct ixgbe_dcb_tc_config *tc;
7689         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7690         uint8_t nb_tcs;
7691         uint8_t i, j;
7692
7693         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7694                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7695         else
7696                 dcb_info->nb_tcs = 1;
7697
7698         tc_queue = &dcb_info->tc_queue;
7699         nb_tcs = dcb_info->nb_tcs;
7700
7701         if (dcb_config->vt_mode) { /* vt is enabled*/
7702                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7703                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7704                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7705                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7706                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7707                         for (j = 0; j < nb_tcs; j++) {
7708                                 tc_queue->tc_rxq[0][j].base = j;
7709                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7710                                 tc_queue->tc_txq[0][j].base = j;
7711                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7712                         }
7713                 } else {
7714                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7715                                 for (j = 0; j < nb_tcs; j++) {
7716                                         tc_queue->tc_rxq[i][j].base =
7717                                                 i * nb_tcs + j;
7718                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7719                                         tc_queue->tc_txq[i][j].base =
7720                                                 i * nb_tcs + j;
7721                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7722                                 }
7723                         }
7724                 }
7725         } else { /* vt is disabled*/
7726                 struct rte_eth_dcb_rx_conf *rx_conf =
7727                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7728                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7729                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7730                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7731                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7732                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7733                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7734                         }
7735                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7736                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7737                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7738                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7739                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7740                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7741                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7742                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7743                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7744                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7745                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7746                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7747                         }
7748                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7749                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7750                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7751                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7752                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7753                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7754                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7755                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7756                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7757                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7758                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7759                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7760                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7761                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7762                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7763                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7764                 }
7765         }
7766         for (i = 0; i < dcb_info->nb_tcs; i++) {
7767                 tc = &dcb_config->tc_config[i];
7768                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7769         }
7770         return 0;
7771 }
7772
7773 /* Update e-tag ether type */
7774 static int
7775 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7776                             uint16_t ether_type)
7777 {
7778         uint32_t etag_etype;
7779
7780         if (hw->mac.type != ixgbe_mac_X550 &&
7781             hw->mac.type != ixgbe_mac_X550EM_x &&
7782             hw->mac.type != ixgbe_mac_X550EM_a) {
7783                 return -ENOTSUP;
7784         }
7785
7786         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7787         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7788         etag_etype |= ether_type;
7789         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7790         IXGBE_WRITE_FLUSH(hw);
7791
7792         return 0;
7793 }
7794
7795 /* Config l2 tunnel ether type */
7796 static int
7797 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7798                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7799 {
7800         int ret = 0;
7801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7802         struct ixgbe_l2_tn_info *l2_tn_info =
7803                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7804
7805         if (l2_tunnel == NULL)
7806                 return -EINVAL;
7807
7808         switch (l2_tunnel->l2_tunnel_type) {
7809         case RTE_L2_TUNNEL_TYPE_E_TAG:
7810                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7811                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7812                 break;
7813         default:
7814                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7815                 ret = -EINVAL;
7816                 break;
7817         }
7818
7819         return ret;
7820 }
7821
7822 /* Enable e-tag tunnel */
7823 static int
7824 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7825 {
7826         uint32_t etag_etype;
7827
7828         if (hw->mac.type != ixgbe_mac_X550 &&
7829             hw->mac.type != ixgbe_mac_X550EM_x &&
7830             hw->mac.type != ixgbe_mac_X550EM_a) {
7831                 return -ENOTSUP;
7832         }
7833
7834         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7835         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7836         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7837         IXGBE_WRITE_FLUSH(hw);
7838
7839         return 0;
7840 }
7841
7842 /* Enable l2 tunnel */
7843 static int
7844 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7845                            enum rte_eth_tunnel_type l2_tunnel_type)
7846 {
7847         int ret = 0;
7848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7849         struct ixgbe_l2_tn_info *l2_tn_info =
7850                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7851
7852         switch (l2_tunnel_type) {
7853         case RTE_L2_TUNNEL_TYPE_E_TAG:
7854                 l2_tn_info->e_tag_en = TRUE;
7855                 ret = ixgbe_e_tag_enable(hw);
7856                 break;
7857         default:
7858                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7859                 ret = -EINVAL;
7860                 break;
7861         }
7862
7863         return ret;
7864 }
7865
7866 /* Disable e-tag tunnel */
7867 static int
7868 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7869 {
7870         uint32_t etag_etype;
7871
7872         if (hw->mac.type != ixgbe_mac_X550 &&
7873             hw->mac.type != ixgbe_mac_X550EM_x &&
7874             hw->mac.type != ixgbe_mac_X550EM_a) {
7875                 return -ENOTSUP;
7876         }
7877
7878         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7879         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7880         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7881         IXGBE_WRITE_FLUSH(hw);
7882
7883         return 0;
7884 }
7885
7886 /* Disable l2 tunnel */
7887 static int
7888 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7889                             enum rte_eth_tunnel_type l2_tunnel_type)
7890 {
7891         int ret = 0;
7892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7893         struct ixgbe_l2_tn_info *l2_tn_info =
7894                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7895
7896         switch (l2_tunnel_type) {
7897         case RTE_L2_TUNNEL_TYPE_E_TAG:
7898                 l2_tn_info->e_tag_en = FALSE;
7899                 ret = ixgbe_e_tag_disable(hw);
7900                 break;
7901         default:
7902                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7903                 ret = -EINVAL;
7904                 break;
7905         }
7906
7907         return ret;
7908 }
7909
7910 static int
7911 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7912                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7913 {
7914         int ret = 0;
7915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7916         uint32_t i, rar_entries;
7917         uint32_t rar_low, rar_high;
7918
7919         if (hw->mac.type != ixgbe_mac_X550 &&
7920             hw->mac.type != ixgbe_mac_X550EM_x &&
7921             hw->mac.type != ixgbe_mac_X550EM_a) {
7922                 return -ENOTSUP;
7923         }
7924
7925         rar_entries = ixgbe_get_num_rx_addrs(hw);
7926
7927         for (i = 1; i < rar_entries; i++) {
7928                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7929                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7930                 if ((rar_high & IXGBE_RAH_AV) &&
7931                     (rar_high & IXGBE_RAH_ADTYPE) &&
7932                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7933                      l2_tunnel->tunnel_id)) {
7934                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7935                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7936
7937                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7938
7939                         return ret;
7940                 }
7941         }
7942
7943         return ret;
7944 }
7945
7946 static int
7947 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7948                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7949 {
7950         int ret = 0;
7951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7952         uint32_t i, rar_entries;
7953         uint32_t rar_low, rar_high;
7954
7955         if (hw->mac.type != ixgbe_mac_X550 &&
7956             hw->mac.type != ixgbe_mac_X550EM_x &&
7957             hw->mac.type != ixgbe_mac_X550EM_a) {
7958                 return -ENOTSUP;
7959         }
7960
7961         /* One entry for one tunnel. Try to remove potential existing entry. */
7962         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7963
7964         rar_entries = ixgbe_get_num_rx_addrs(hw);
7965
7966         for (i = 1; i < rar_entries; i++) {
7967                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7968                 if (rar_high & IXGBE_RAH_AV) {
7969                         continue;
7970                 } else {
7971                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7972                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7973                         rar_low = l2_tunnel->tunnel_id;
7974
7975                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7976                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7977
7978                         return ret;
7979                 }
7980         }
7981
7982         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7983                      " Please remove a rule before adding a new one.");
7984         return -EINVAL;
7985 }
7986
7987 static inline struct ixgbe_l2_tn_filter *
7988 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7989                           struct ixgbe_l2_tn_key *key)
7990 {
7991         int ret;
7992
7993         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7994         if (ret < 0)
7995                 return NULL;
7996
7997         return l2_tn_info->hash_map[ret];
7998 }
7999
8000 static inline int
8001 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8002                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8003 {
8004         int ret;
8005
8006         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8007                                &l2_tn_filter->key);
8008
8009         if (ret < 0) {
8010                 PMD_DRV_LOG(ERR,
8011                             "Failed to insert L2 tunnel filter"
8012                             " to hash table %d!",
8013                             ret);
8014                 return ret;
8015         }
8016
8017         l2_tn_info->hash_map[ret] = l2_tn_filter;
8018
8019         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8020
8021         return 0;
8022 }
8023
8024 static inline int
8025 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8026                           struct ixgbe_l2_tn_key *key)
8027 {
8028         int ret;
8029         struct ixgbe_l2_tn_filter *l2_tn_filter;
8030
8031         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8032
8033         if (ret < 0) {
8034                 PMD_DRV_LOG(ERR,
8035                             "No such L2 tunnel filter to delete %d!",
8036                             ret);
8037                 return ret;
8038         }
8039
8040         l2_tn_filter = l2_tn_info->hash_map[ret];
8041         l2_tn_info->hash_map[ret] = NULL;
8042
8043         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8044         rte_free(l2_tn_filter);
8045
8046         return 0;
8047 }
8048
8049 /* Add l2 tunnel filter */
8050 int
8051 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8052                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8053                                bool restore)
8054 {
8055         int ret;
8056         struct ixgbe_l2_tn_info *l2_tn_info =
8057                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8058         struct ixgbe_l2_tn_key key;
8059         struct ixgbe_l2_tn_filter *node;
8060
8061         if (!restore) {
8062                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8063                 key.tn_id = l2_tunnel->tunnel_id;
8064
8065                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8066
8067                 if (node) {
8068                         PMD_DRV_LOG(ERR,
8069                                     "The L2 tunnel filter already exists!");
8070                         return -EINVAL;
8071                 }
8072
8073                 node = rte_zmalloc("ixgbe_l2_tn",
8074                                    sizeof(struct ixgbe_l2_tn_filter),
8075                                    0);
8076                 if (!node)
8077                         return -ENOMEM;
8078
8079                 rte_memcpy(&node->key,
8080                                  &key,
8081                                  sizeof(struct ixgbe_l2_tn_key));
8082                 node->pool = l2_tunnel->pool;
8083                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8084                 if (ret < 0) {
8085                         rte_free(node);
8086                         return ret;
8087                 }
8088         }
8089
8090         switch (l2_tunnel->l2_tunnel_type) {
8091         case RTE_L2_TUNNEL_TYPE_E_TAG:
8092                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8093                 break;
8094         default:
8095                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8096                 ret = -EINVAL;
8097                 break;
8098         }
8099
8100         if ((!restore) && (ret < 0))
8101                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8102
8103         return ret;
8104 }
8105
8106 /* Delete l2 tunnel filter */
8107 int
8108 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8109                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8110 {
8111         int ret;
8112         struct ixgbe_l2_tn_info *l2_tn_info =
8113                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8114         struct ixgbe_l2_tn_key key;
8115
8116         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8117         key.tn_id = l2_tunnel->tunnel_id;
8118         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8119         if (ret < 0)
8120                 return ret;
8121
8122         switch (l2_tunnel->l2_tunnel_type) {
8123         case RTE_L2_TUNNEL_TYPE_E_TAG:
8124                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8125                 break;
8126         default:
8127                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8128                 ret = -EINVAL;
8129                 break;
8130         }
8131
8132         return ret;
8133 }
8134
8135 /**
8136  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8137  * @dev: pointer to rte_eth_dev structure
8138  * @filter_op:operation will be taken.
8139  * @arg: a pointer to specific structure corresponding to the filter_op
8140  */
8141 static int
8142 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8143                                   enum rte_filter_op filter_op,
8144                                   void *arg)
8145 {
8146         int ret;
8147
8148         if (filter_op == RTE_ETH_FILTER_NOP)
8149                 return 0;
8150
8151         if (arg == NULL) {
8152                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8153                             filter_op);
8154                 return -EINVAL;
8155         }
8156
8157         switch (filter_op) {
8158         case RTE_ETH_FILTER_ADD:
8159                 ret = ixgbe_dev_l2_tunnel_filter_add
8160                         (dev,
8161                          (struct rte_eth_l2_tunnel_conf *)arg,
8162                          FALSE);
8163                 break;
8164         case RTE_ETH_FILTER_DELETE:
8165                 ret = ixgbe_dev_l2_tunnel_filter_del
8166                         (dev,
8167                          (struct rte_eth_l2_tunnel_conf *)arg);
8168                 break;
8169         default:
8170                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8171                 ret = -EINVAL;
8172                 break;
8173         }
8174         return ret;
8175 }
8176
8177 static int
8178 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8179 {
8180         int ret = 0;
8181         uint32_t ctrl;
8182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8183
8184         if (hw->mac.type != ixgbe_mac_X550 &&
8185             hw->mac.type != ixgbe_mac_X550EM_x &&
8186             hw->mac.type != ixgbe_mac_X550EM_a) {
8187                 return -ENOTSUP;
8188         }
8189
8190         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8191         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8192         if (en)
8193                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8194         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8195
8196         return ret;
8197 }
8198
8199 /* Enable l2 tunnel forwarding */
8200 static int
8201 ixgbe_dev_l2_tunnel_forwarding_enable
8202         (struct rte_eth_dev *dev,
8203          enum rte_eth_tunnel_type l2_tunnel_type)
8204 {
8205         struct ixgbe_l2_tn_info *l2_tn_info =
8206                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8207         int ret = 0;
8208
8209         switch (l2_tunnel_type) {
8210         case RTE_L2_TUNNEL_TYPE_E_TAG:
8211                 l2_tn_info->e_tag_fwd_en = TRUE;
8212                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8213                 break;
8214         default:
8215                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8216                 ret = -EINVAL;
8217                 break;
8218         }
8219
8220         return ret;
8221 }
8222
8223 /* Disable l2 tunnel forwarding */
8224 static int
8225 ixgbe_dev_l2_tunnel_forwarding_disable
8226         (struct rte_eth_dev *dev,
8227          enum rte_eth_tunnel_type l2_tunnel_type)
8228 {
8229         struct ixgbe_l2_tn_info *l2_tn_info =
8230                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8231         int ret = 0;
8232
8233         switch (l2_tunnel_type) {
8234         case RTE_L2_TUNNEL_TYPE_E_TAG:
8235                 l2_tn_info->e_tag_fwd_en = FALSE;
8236                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8237                 break;
8238         default:
8239                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8240                 ret = -EINVAL;
8241                 break;
8242         }
8243
8244         return ret;
8245 }
8246
8247 static int
8248 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8249                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8250                              bool en)
8251 {
8252         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8253         int ret = 0;
8254         uint32_t vmtir, vmvir;
8255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8256
8257         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8258                 PMD_DRV_LOG(ERR,
8259                             "VF id %u should be less than %u",
8260                             l2_tunnel->vf_id,
8261                             pci_dev->max_vfs);
8262                 return -EINVAL;
8263         }
8264
8265         if (hw->mac.type != ixgbe_mac_X550 &&
8266             hw->mac.type != ixgbe_mac_X550EM_x &&
8267             hw->mac.type != ixgbe_mac_X550EM_a) {
8268                 return -ENOTSUP;
8269         }
8270
8271         if (en)
8272                 vmtir = l2_tunnel->tunnel_id;
8273         else
8274                 vmtir = 0;
8275
8276         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8277
8278         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8279         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8280         if (en)
8281                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8282         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8283
8284         return ret;
8285 }
8286
8287 /* Enable l2 tunnel tag insertion */
8288 static int
8289 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8290                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8291 {
8292         int ret = 0;
8293
8294         switch (l2_tunnel->l2_tunnel_type) {
8295         case RTE_L2_TUNNEL_TYPE_E_TAG:
8296                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8297                 break;
8298         default:
8299                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8300                 ret = -EINVAL;
8301                 break;
8302         }
8303
8304         return ret;
8305 }
8306
8307 /* Disable l2 tunnel tag insertion */
8308 static int
8309 ixgbe_dev_l2_tunnel_insertion_disable
8310         (struct rte_eth_dev *dev,
8311          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8312 {
8313         int ret = 0;
8314
8315         switch (l2_tunnel->l2_tunnel_type) {
8316         case RTE_L2_TUNNEL_TYPE_E_TAG:
8317                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8318                 break;
8319         default:
8320                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8321                 ret = -EINVAL;
8322                 break;
8323         }
8324
8325         return ret;
8326 }
8327
8328 static int
8329 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8330                              bool en)
8331 {
8332         int ret = 0;
8333         uint32_t qde;
8334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8335
8336         if (hw->mac.type != ixgbe_mac_X550 &&
8337             hw->mac.type != ixgbe_mac_X550EM_x &&
8338             hw->mac.type != ixgbe_mac_X550EM_a) {
8339                 return -ENOTSUP;
8340         }
8341
8342         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8343         if (en)
8344                 qde |= IXGBE_QDE_STRIP_TAG;
8345         else
8346                 qde &= ~IXGBE_QDE_STRIP_TAG;
8347         qde &= ~IXGBE_QDE_READ;
8348         qde |= IXGBE_QDE_WRITE;
8349         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8350
8351         return ret;
8352 }
8353
8354 /* Enable l2 tunnel tag stripping */
8355 static int
8356 ixgbe_dev_l2_tunnel_stripping_enable
8357         (struct rte_eth_dev *dev,
8358          enum rte_eth_tunnel_type l2_tunnel_type)
8359 {
8360         int ret = 0;
8361
8362         switch (l2_tunnel_type) {
8363         case RTE_L2_TUNNEL_TYPE_E_TAG:
8364                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8365                 break;
8366         default:
8367                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8368                 ret = -EINVAL;
8369                 break;
8370         }
8371
8372         return ret;
8373 }
8374
8375 /* Disable l2 tunnel tag stripping */
8376 static int
8377 ixgbe_dev_l2_tunnel_stripping_disable
8378         (struct rte_eth_dev *dev,
8379          enum rte_eth_tunnel_type l2_tunnel_type)
8380 {
8381         int ret = 0;
8382
8383         switch (l2_tunnel_type) {
8384         case RTE_L2_TUNNEL_TYPE_E_TAG:
8385                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8386                 break;
8387         default:
8388                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8389                 ret = -EINVAL;
8390                 break;
8391         }
8392
8393         return ret;
8394 }
8395
8396 /* Enable/disable l2 tunnel offload functions */
8397 static int
8398 ixgbe_dev_l2_tunnel_offload_set
8399         (struct rte_eth_dev *dev,
8400          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8401          uint32_t mask,
8402          uint8_t en)
8403 {
8404         int ret = 0;
8405
8406         if (l2_tunnel == NULL)
8407                 return -EINVAL;
8408
8409         ret = -EINVAL;
8410         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8411                 if (en)
8412                         ret = ixgbe_dev_l2_tunnel_enable(
8413                                 dev,
8414                                 l2_tunnel->l2_tunnel_type);
8415                 else
8416                         ret = ixgbe_dev_l2_tunnel_disable(
8417                                 dev,
8418                                 l2_tunnel->l2_tunnel_type);
8419         }
8420
8421         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8422                 if (en)
8423                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8424                                 dev,
8425                                 l2_tunnel);
8426                 else
8427                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8428                                 dev,
8429                                 l2_tunnel);
8430         }
8431
8432         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8433                 if (en)
8434                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8435                                 dev,
8436                                 l2_tunnel->l2_tunnel_type);
8437                 else
8438                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8439                                 dev,
8440                                 l2_tunnel->l2_tunnel_type);
8441         }
8442
8443         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8444                 if (en)
8445                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8446                                 dev,
8447                                 l2_tunnel->l2_tunnel_type);
8448                 else
8449                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8450                                 dev,
8451                                 l2_tunnel->l2_tunnel_type);
8452         }
8453
8454         return ret;
8455 }
8456
8457 static int
8458 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8459                         uint16_t port)
8460 {
8461         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8462         IXGBE_WRITE_FLUSH(hw);
8463
8464         return 0;
8465 }
8466
8467 /* There's only one register for VxLAN UDP port.
8468  * So, we cannot add several ports. Will update it.
8469  */
8470 static int
8471 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8472                      uint16_t port)
8473 {
8474         if (port == 0) {
8475                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8476                 return -EINVAL;
8477         }
8478
8479         return ixgbe_update_vxlan_port(hw, port);
8480 }
8481
8482 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8483  * UDP port, it must have a value.
8484  * So, will reset it to the original value 0.
8485  */
8486 static int
8487 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8488                      uint16_t port)
8489 {
8490         uint16_t cur_port;
8491
8492         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8493
8494         if (cur_port != port) {
8495                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8496                 return -EINVAL;
8497         }
8498
8499         return ixgbe_update_vxlan_port(hw, 0);
8500 }
8501
8502 /* Add UDP tunneling port */
8503 static int
8504 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8505                               struct rte_eth_udp_tunnel *udp_tunnel)
8506 {
8507         int ret = 0;
8508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8509
8510         if (hw->mac.type != ixgbe_mac_X550 &&
8511             hw->mac.type != ixgbe_mac_X550EM_x &&
8512             hw->mac.type != ixgbe_mac_X550EM_a) {
8513                 return -ENOTSUP;
8514         }
8515
8516         if (udp_tunnel == NULL)
8517                 return -EINVAL;
8518
8519         switch (udp_tunnel->prot_type) {
8520         case RTE_TUNNEL_TYPE_VXLAN:
8521                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8522                 break;
8523
8524         case RTE_TUNNEL_TYPE_GENEVE:
8525         case RTE_TUNNEL_TYPE_TEREDO:
8526                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8527                 ret = -EINVAL;
8528                 break;
8529
8530         default:
8531                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8532                 ret = -EINVAL;
8533                 break;
8534         }
8535
8536         return ret;
8537 }
8538
8539 /* Remove UDP tunneling port */
8540 static int
8541 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8542                               struct rte_eth_udp_tunnel *udp_tunnel)
8543 {
8544         int ret = 0;
8545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8546
8547         if (hw->mac.type != ixgbe_mac_X550 &&
8548             hw->mac.type != ixgbe_mac_X550EM_x &&
8549             hw->mac.type != ixgbe_mac_X550EM_a) {
8550                 return -ENOTSUP;
8551         }
8552
8553         if (udp_tunnel == NULL)
8554                 return -EINVAL;
8555
8556         switch (udp_tunnel->prot_type) {
8557         case RTE_TUNNEL_TYPE_VXLAN:
8558                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8559                 break;
8560         case RTE_TUNNEL_TYPE_GENEVE:
8561         case RTE_TUNNEL_TYPE_TEREDO:
8562                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8563                 ret = -EINVAL;
8564                 break;
8565         default:
8566                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8567                 ret = -EINVAL;
8568                 break;
8569         }
8570
8571         return ret;
8572 }
8573
8574 static int
8575 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8576 {
8577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8578         int ret;
8579
8580         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8581         case IXGBE_SUCCESS:
8582                 ret = 0;
8583                 break;
8584         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8585                 ret = -ENOTSUP;
8586                 break;
8587         default:
8588                 ret = -EAGAIN;
8589                 break;
8590         }
8591
8592         return ret;
8593 }
8594
8595 static int
8596 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8597 {
8598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8599         int ret;
8600
8601         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8602         case IXGBE_SUCCESS:
8603                 ret = 0;
8604                 break;
8605         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8606                 ret = -ENOTSUP;
8607                 break;
8608         default:
8609                 ret = -EAGAIN;
8610                 break;
8611         }
8612
8613         return ret;
8614 }
8615
8616 static int
8617 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8618 {
8619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8620         int ret;
8621         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8622
8623         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8624         case IXGBE_SUCCESS:
8625                 ret = 0;
8626                 break;
8627         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8628                 ret = -ENOTSUP;
8629                 break;
8630         default:
8631                 ret = -EAGAIN;
8632                 break;
8633         }
8634
8635         return ret;
8636 }
8637
8638 static int
8639 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8640 {
8641         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8642         int ret;
8643
8644         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8645         case IXGBE_SUCCESS:
8646                 ret = 0;
8647                 break;
8648         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8649                 ret = -ENOTSUP;
8650                 break;
8651         default:
8652                 ret = -EAGAIN;
8653                 break;
8654         }
8655
8656         return ret;
8657 }
8658
8659 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8660 {
8661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8662         u32 in_msg = 0;
8663
8664         /* peek the message first */
8665         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8666
8667         /* PF reset VF event */
8668         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8669                 /* dummy mbx read to ack pf */
8670                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8671                         return;
8672                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8673                                              NULL);
8674         }
8675 }
8676
8677 static int
8678 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8679 {
8680         uint32_t eicr;
8681         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8682         struct ixgbe_interrupt *intr =
8683                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8684         ixgbevf_intr_disable(dev);
8685
8686         /* read-on-clear nic registers here */
8687         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8688         intr->flags = 0;
8689
8690         /* only one misc vector supported - mailbox */
8691         eicr &= IXGBE_VTEICR_MASK;
8692         if (eicr == IXGBE_MISC_VEC_ID)
8693                 intr->flags |= IXGBE_FLAG_MAILBOX;
8694
8695         return 0;
8696 }
8697
8698 static int
8699 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8700 {
8701         struct ixgbe_interrupt *intr =
8702                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8703
8704         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8705                 ixgbevf_mbx_process(dev);
8706                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8707         }
8708
8709         ixgbevf_intr_enable(dev);
8710
8711         return 0;
8712 }
8713
8714 static void
8715 ixgbevf_dev_interrupt_handler(void *param)
8716 {
8717         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8718
8719         ixgbevf_dev_interrupt_get_status(dev);
8720         ixgbevf_dev_interrupt_action(dev);
8721 }
8722
8723 /**
8724  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8725  *  @hw: pointer to hardware structure
8726  *
8727  *  Stops the transmit data path and waits for the HW to internally empty
8728  *  the Tx security block
8729  **/
8730 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8731 {
8732 #define IXGBE_MAX_SECTX_POLL 40
8733
8734         int i;
8735         int sectxreg;
8736
8737         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8738         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8739         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8740         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8741                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8742                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8743                         break;
8744                 /* Use interrupt-safe sleep just in case */
8745                 usec_delay(1000);
8746         }
8747
8748         /* For informational purposes only */
8749         if (i >= IXGBE_MAX_SECTX_POLL)
8750                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8751                          "path fully disabled.  Continuing with init.");
8752
8753         return IXGBE_SUCCESS;
8754 }
8755
8756 /**
8757  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8758  *  @hw: pointer to hardware structure
8759  *
8760  *  Enables the transmit data path.
8761  **/
8762 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8763 {
8764         uint32_t sectxreg;
8765
8766         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8767         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8768         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8769         IXGBE_WRITE_FLUSH(hw);
8770
8771         return IXGBE_SUCCESS;
8772 }
8773
8774 /* restore n-tuple filter */
8775 static inline void
8776 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8777 {
8778         struct ixgbe_filter_info *filter_info =
8779                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8780         struct ixgbe_5tuple_filter *node;
8781
8782         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8783                 ixgbe_inject_5tuple_filter(dev, node);
8784         }
8785 }
8786
8787 /* restore ethernet type filter */
8788 static inline void
8789 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8790 {
8791         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8792         struct ixgbe_filter_info *filter_info =
8793                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8794         int i;
8795
8796         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8797                 if (filter_info->ethertype_mask & (1 << i)) {
8798                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8799                                         filter_info->ethertype_filters[i].etqf);
8800                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8801                                         filter_info->ethertype_filters[i].etqs);
8802                         IXGBE_WRITE_FLUSH(hw);
8803                 }
8804         }
8805 }
8806
8807 /* restore SYN filter */
8808 static inline void
8809 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8810 {
8811         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8812         struct ixgbe_filter_info *filter_info =
8813                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8814         uint32_t synqf;
8815
8816         synqf = filter_info->syn_info;
8817
8818         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8819                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8820                 IXGBE_WRITE_FLUSH(hw);
8821         }
8822 }
8823
8824 /* restore L2 tunnel filter */
8825 static inline void
8826 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8827 {
8828         struct ixgbe_l2_tn_info *l2_tn_info =
8829                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8830         struct ixgbe_l2_tn_filter *node;
8831         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8832
8833         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8834                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8835                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8836                 l2_tn_conf.pool           = node->pool;
8837                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8838         }
8839 }
8840
8841 /* restore rss filter */
8842 static inline void
8843 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8844 {
8845         struct ixgbe_filter_info *filter_info =
8846                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8847
8848         if (filter_info->rss_info.conf.queue_num)
8849                 ixgbe_config_rss_filter(dev,
8850                         &filter_info->rss_info, TRUE);
8851 }
8852
8853 static int
8854 ixgbe_filter_restore(struct rte_eth_dev *dev)
8855 {
8856         ixgbe_ntuple_filter_restore(dev);
8857         ixgbe_ethertype_filter_restore(dev);
8858         ixgbe_syn_filter_restore(dev);
8859         ixgbe_fdir_filter_restore(dev);
8860         ixgbe_l2_tn_filter_restore(dev);
8861         ixgbe_rss_filter_restore(dev);
8862
8863         return 0;
8864 }
8865
8866 static void
8867 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8868 {
8869         struct ixgbe_l2_tn_info *l2_tn_info =
8870                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8872
8873         if (l2_tn_info->e_tag_en)
8874                 (void)ixgbe_e_tag_enable(hw);
8875
8876         if (l2_tn_info->e_tag_fwd_en)
8877                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8878
8879         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8880 }
8881
8882 /* remove all the n-tuple filters */
8883 void
8884 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8885 {
8886         struct ixgbe_filter_info *filter_info =
8887                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8888         struct ixgbe_5tuple_filter *p_5tuple;
8889
8890         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8891                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8892 }
8893
8894 /* remove all the ether type filters */
8895 void
8896 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8897 {
8898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8899         struct ixgbe_filter_info *filter_info =
8900                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8901         int i;
8902
8903         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8904                 if (filter_info->ethertype_mask & (1 << i) &&
8905                     !filter_info->ethertype_filters[i].conf) {
8906                         (void)ixgbe_ethertype_filter_remove(filter_info,
8907                                                             (uint8_t)i);
8908                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8909                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8910                         IXGBE_WRITE_FLUSH(hw);
8911                 }
8912         }
8913 }
8914
8915 /* remove the SYN filter */
8916 void
8917 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8918 {
8919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8920         struct ixgbe_filter_info *filter_info =
8921                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8922
8923         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8924                 filter_info->syn_info = 0;
8925
8926                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8927                 IXGBE_WRITE_FLUSH(hw);
8928         }
8929 }
8930
8931 /* remove all the L2 tunnel filters */
8932 int
8933 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8934 {
8935         struct ixgbe_l2_tn_info *l2_tn_info =
8936                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8937         struct ixgbe_l2_tn_filter *l2_tn_filter;
8938         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8939         int ret = 0;
8940
8941         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8942                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8943                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8944                 l2_tn_conf.pool           = l2_tn_filter->pool;
8945                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8946                 if (ret < 0)
8947                         return ret;
8948         }
8949
8950         return 0;
8951 }
8952
8953 void
8954 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8955                                 struct ixgbe_macsec_setting *macsec_setting)
8956 {
8957         struct ixgbe_macsec_setting *macsec =
8958                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8959
8960         macsec->offload_en = macsec_setting->offload_en;
8961         macsec->encrypt_en = macsec_setting->encrypt_en;
8962         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8963 }
8964
8965 void
8966 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8967 {
8968         struct ixgbe_macsec_setting *macsec =
8969                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8970
8971         macsec->offload_en = 0;
8972         macsec->encrypt_en = 0;
8973         macsec->replayprotect_en = 0;
8974 }
8975
8976 void
8977 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8978                                 struct ixgbe_macsec_setting *macsec_setting)
8979 {
8980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8981         uint32_t ctrl;
8982         uint8_t en = macsec_setting->encrypt_en;
8983         uint8_t rp = macsec_setting->replayprotect_en;
8984
8985         /**
8986          * Workaround:
8987          * As no ixgbe_disable_sec_rx_path equivalent is
8988          * implemented for tx in the base code, and we are
8989          * not allowed to modify the base code in DPDK, so
8990          * just call the hand-written one directly for now.
8991          * The hardware support has been checked by
8992          * ixgbe_disable_sec_rx_path().
8993          */
8994         ixgbe_disable_sec_tx_path_generic(hw);
8995
8996         /* Enable Ethernet CRC (required by MACsec offload) */
8997         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8998         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8999         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9000
9001         /* Enable the TX and RX crypto engines */
9002         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9003         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9004         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9005
9006         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9007         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9008         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9009
9010         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9011         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9012         ctrl |= 0x3;
9013         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9014
9015         /* Enable SA lookup */
9016         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9017         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9018         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9019                      IXGBE_LSECTXCTRL_AUTH;
9020         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9021         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9022         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9023         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9024
9025         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9026         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9027         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9028         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9029         if (rp)
9030                 ctrl |= IXGBE_LSECRXCTRL_RP;
9031         else
9032                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9033         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9034
9035         /* Start the data paths */
9036         ixgbe_enable_sec_rx_path(hw);
9037         /**
9038          * Workaround:
9039          * As no ixgbe_enable_sec_rx_path equivalent is
9040          * implemented for tx in the base code, and we are
9041          * not allowed to modify the base code in DPDK, so
9042          * just call the hand-written one directly for now.
9043          */
9044         ixgbe_enable_sec_tx_path_generic(hw);
9045 }
9046
9047 void
9048 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9049 {
9050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9051         uint32_t ctrl;
9052
9053         /**
9054          * Workaround:
9055          * As no ixgbe_disable_sec_rx_path equivalent is
9056          * implemented for tx in the base code, and we are
9057          * not allowed to modify the base code in DPDK, so
9058          * just call the hand-written one directly for now.
9059          * The hardware support has been checked by
9060          * ixgbe_disable_sec_rx_path().
9061          */
9062         ixgbe_disable_sec_tx_path_generic(hw);
9063
9064         /* Disable the TX and RX crypto engines */
9065         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9066         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9067         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9068
9069         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9070         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9071         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9072
9073         /* Disable SA lookup */
9074         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9075         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9076         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9077         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9078
9079         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9080         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9081         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9082         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9083
9084         /* Start the data paths */
9085         ixgbe_enable_sec_rx_path(hw);
9086         /**
9087          * Workaround:
9088          * As no ixgbe_enable_sec_rx_path equivalent is
9089          * implemented for tx in the base code, and we are
9090          * not allowed to modify the base code in DPDK, so
9091          * just call the hand-written one directly for now.
9092          */
9093         ixgbe_enable_sec_tx_path_generic(hw);
9094 }
9095
9096 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9097 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9098 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9099 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9100 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9101 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9102 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9103                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9104
9105 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9106 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9107
9108 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9109 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9110 #endif
9111 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9112 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9113 #endif
9114 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9115 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9116 #endif