drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 /* Additional timesync values. */
 104 #define NSEC_PER_SEC             1000000000L
 105 #define IXGBE_INCVAL_10GB        0x66666666
 106 #define IXGBE_INCVAL_1GB         0x40000000
 107 #define IXGBE_INCVAL_100         0x50000000
 108 #define IXGBE_INCVAL_SHIFT_10GB  28
 109 #define IXGBE_INCVAL_SHIFT_1GB   24
 110 #define IXGBE_INCVAL_SHIFT_100   21
 111 #define IXGBE_INCVAL_SHIFT_82599 7
 112 #define IXGBE_INCPER_SHIFT_82599 24
 113
 114 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 118 #define IXGBE_ETAG_ETYPE                       0x00005084
 119 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 120 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 121 #define IXGBE_RAH_ADTYPE                       0x40000000
 122 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 123 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 124 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 125 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 126 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 127 #define IXGBE_VTEICR_MASK                      0x07
 128
 129 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 130 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 131
 132 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 133 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 151                                 int wait_to_complete);
 152 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 153                                 struct rte_eth_stats *stats);
 154 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 155                                 struct rte_eth_xstat *xstats, unsigned n);
 156 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 157                                   struct rte_eth_xstat *xstats, unsigned n);
 158 static int
 159 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 160                 uint64_t *values, unsigned int n);
 161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names,
 165         unsigned int size);
 166 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 168 static int ixgbe_dev_xstats_get_names_by_id(
 169         struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         const uint64_t *ids,
 172         unsigned int limit);
 173 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 174                                              uint16_t queue_id,
 175                                              uint8_t stat_idx,
 176                                              uint8_t is_rx);
 177 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 178                                  size_t fw_size);
 179 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_dev_info *dev_info);
 181 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 221                                       struct rte_intr_handle *handle);
 222 static void ixgbe_dev_interrupt_handler(void *param);
 223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 224 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 225                          uint32_t index, uint32_t pool);
 226 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 227 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 228                                            struct ether_addr *mac_addr);
 229 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 230 static bool is_device_supported(struct rte_eth_dev *dev,
 231                                 struct rte_pci_driver *drv);
 232
 233 /* For Virtual Function support */
 234 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 235 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 236 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 237 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 238 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 239                                    int wait_to_complete);
 240 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 242 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr * mac_addr, uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 268 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 269                 struct rte_eth_mirror_conf *mirror_conf,
 270                 uint8_t rule_id, uint8_t on);
 271 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 272                 uint8_t rule_id);
 273 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 274                                           uint16_t queue_id);
 275 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 276                                            uint16_t queue_id);
 277 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 278                                uint8_t queue, uint8_t msix_vector);
 279 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 280
 281 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 282                                 struct ether_addr *mac_addr,
 283                                 uint32_t index, uint32_t pool);
 284 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 285 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 286                                              struct ether_addr *mac_addr);
 287 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 288                         struct rte_eth_syn_filter *filter);
 289 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 290                         enum rte_filter_op filter_op,
 291                         void *arg);
 292 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 293                         struct ixgbe_5tuple_filter *filter);
 294 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 297                                 enum rte_filter_op filter_op,
 298                                 void *arg);
 299 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 300                         struct rte_eth_ntuple_filter *filter);
 301 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 302                                 enum rte_filter_op filter_op,
 303                                 void *arg);
 304 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 305                         struct rte_eth_ethertype_filter *filter);
 306 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 307                      enum rte_filter_type filter_type,
 308                      enum rte_filter_op filter_op,
 309                      void *arg);
 310 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 311
 312 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 313                                       struct ether_addr *mc_addr_set,
 314                                       uint32_t nb_mc_addr);
 315 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 316                                    struct rte_eth_dcb_info *dcb_info);
 317
 318 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 320                             struct rte_dev_reg_info *regs);
 321 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 323                                 struct rte_dev_eeprom_info *eeprom);
 324 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326
 327 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 328                                  struct rte_eth_dev_module_info *modinfo);
 329 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 330                                    struct rte_dev_eeprom_info *info);
 331
 332 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 334                                 struct rte_dev_reg_info *regs);
 335
 336 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 337 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 339                                             struct timespec *timestamp,
 340                                             uint32_t flags);
 341 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 342                                             struct timespec *timestamp);
 343 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 344 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 345                                    struct timespec *timestamp);
 346 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 347                                    const struct timespec *timestamp);
 348 static void ixgbevf_dev_interrupt_handler(void *param);
 349
 350 static int ixgbe_dev_l2_tunnel_eth_type_conf
 351         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 352 static int ixgbe_dev_l2_tunnel_offload_set
 353         (struct rte_eth_dev *dev,
 354          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 355          uint32_t mask,
 356          uint8_t en);
 357 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 358                                              enum rte_filter_op filter_op,
 359                                              void *arg);
 360
 361 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 362                                          struct rte_eth_udp_tunnel *udp_tunnel);
 363 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 366 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 367
 368 /*
 369  * Define VF Stats MACRO for Non "cleared on read" register
 370  */
 371 #define UPDATE_VF_STAT(reg, last, cur)                          \
 372 {                                                               \
 373         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 374         cur += (latest - last) & UINT_MAX;                      \
 375         last = latest;                                          \
 376 }
 377
 378 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 379 {                                                                \
 380         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 381         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 382         u64 latest = ((new_msb << 32) | new_lsb);                \
 383         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 384         last = latest;                                           \
 385 }
 386
 387 #define IXGBE_SET_HWSTRIP(h, q) do {\
 388                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 389                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 390                 (h)->bitmap[idx] |= 1 << bit;\
 391         } while (0)
 392
 393 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 394                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 395                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 396                 (h)->bitmap[idx] &= ~(1 << bit);\
 397         } while (0)
 398
 399 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 400                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 402                 (r) = (h)->bitmap[idx] >> bit & 1;\
 403         } while (0)
 404
 405 int ixgbe_logtype_init;
 406 int ixgbe_logtype_driver;
 407
 408 /*
 409  * The set of PCI devices this driver supports
 410  */
 411 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 460 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 462 #endif
 463         { .vendor_id = 0, /* sentinel */ },
 464 };
 465
 466 /*
 467  * The set of PCI devices this driver supports (for 82599 VF)
 468  */
 469 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 480         { .vendor_id = 0, /* sentinel */ },
 481 };
 482
 483 static const struct rte_eth_desc_lim rx_desc_lim = {
 484         .nb_max = IXGBE_MAX_RING_DESC,
 485         .nb_min = IXGBE_MIN_RING_DESC,
 486         .nb_align = IXGBE_RXD_ALIGN,
 487 };
 488
 489 static const struct rte_eth_desc_lim tx_desc_lim = {
 490         .nb_max = IXGBE_MAX_RING_DESC,
 491         .nb_min = IXGBE_MIN_RING_DESC,
 492         .nb_align = IXGBE_TXD_ALIGN,
 493         .nb_seg_max = IXGBE_TX_MAX_SEG,
 494         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 495 };
 496
 497 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 498         .dev_configure        = ixgbe_dev_configure,
 499         .dev_start            = ixgbe_dev_start,
 500         .dev_stop             = ixgbe_dev_stop,
 501         .dev_set_link_up    = ixgbe_dev_set_link_up,
 502         .dev_set_link_down  = ixgbe_dev_set_link_down,
 503         .dev_close            = ixgbe_dev_close,
 504         .dev_reset            = ixgbe_dev_reset,
 505         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 506         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 507         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 508         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 509         .link_update          = ixgbe_dev_link_update,
 510         .stats_get            = ixgbe_dev_stats_get,
 511         .xstats_get           = ixgbe_dev_xstats_get,
 512         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 513         .stats_reset          = ixgbe_dev_stats_reset,
 514         .xstats_reset         = ixgbe_dev_xstats_reset,
 515         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 516         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 517         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 518         .fw_version_get       = ixgbe_fw_version_get,
 519         .dev_infos_get        = ixgbe_dev_info_get,
 520         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 521         .mtu_set              = ixgbe_dev_mtu_set,
 522         .vlan_filter_set      = ixgbe_vlan_filter_set,
 523         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 524         .vlan_offload_set     = ixgbe_vlan_offload_set,
 525         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 526         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 527         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 528         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 529         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 530         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 531         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 532         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 533         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 534         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 535         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 536         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 537         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 538         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 539         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 540         .dev_led_on           = ixgbe_dev_led_on,
 541         .dev_led_off          = ixgbe_dev_led_off,
 542         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 543         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 544         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 545         .mac_addr_add         = ixgbe_add_rar,
 546         .mac_addr_remove      = ixgbe_remove_rar,
 547         .mac_addr_set         = ixgbe_set_default_mac_addr,
 548         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 549         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 550         .mirror_rule_set      = ixgbe_mirror_rule_set,
 551         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 552         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 553         .reta_update          = ixgbe_dev_rss_reta_update,
 554         .reta_query           = ixgbe_dev_rss_reta_query,
 555         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 556         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 557         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 558         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 559         .rxq_info_get         = ixgbe_rxq_info_get,
 560         .txq_info_get         = ixgbe_txq_info_get,
 561         .timesync_enable      = ixgbe_timesync_enable,
 562         .timesync_disable     = ixgbe_timesync_disable,
 563         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 564         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 565         .get_reg              = ixgbe_get_regs,
 566         .get_eeprom_length    = ixgbe_get_eeprom_length,
 567         .get_eeprom           = ixgbe_get_eeprom,
 568         .set_eeprom           = ixgbe_set_eeprom,
 569         .get_module_info      = ixgbe_get_module_info,
 570         .get_module_eeprom    = ixgbe_get_module_eeprom,
 571         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 572         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 573         .timesync_read_time   = ixgbe_timesync_read_time,
 574         .timesync_write_time  = ixgbe_timesync_write_time,
 575         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 576         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 577         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 578         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 579         .tm_ops_get           = ixgbe_tm_ops_get,
 580 };
 581
 582 /*
 583  * dev_ops for virtual function, bare necessities for basic vf
 584  * operation have been implemented
 585  */
 586 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 587         .dev_configure        = ixgbevf_dev_configure,
 588         .dev_start            = ixgbevf_dev_start,
 589         .dev_stop             = ixgbevf_dev_stop,
 590         .link_update          = ixgbevf_dev_link_update,
 591         .stats_get            = ixgbevf_dev_stats_get,
 592         .xstats_get           = ixgbevf_dev_xstats_get,
 593         .stats_reset          = ixgbevf_dev_stats_reset,
 594         .xstats_reset         = ixgbevf_dev_stats_reset,
 595         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 596         .dev_close            = ixgbevf_dev_close,
 597         .dev_reset            = ixgbevf_dev_reset,
 598         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 599         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 600         .dev_infos_get        = ixgbevf_dev_info_get,
 601         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 602         .mtu_set              = ixgbevf_dev_set_mtu,
 603         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 604         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 605         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 606         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 607         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 608         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 609         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 610         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 611         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 612         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 613         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 614         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 615         .mac_addr_add         = ixgbevf_add_mac_addr,
 616         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 617         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 618         .rxq_info_get         = ixgbe_rxq_info_get,
 619         .txq_info_get         = ixgbe_txq_info_get,
 620         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 621         .get_reg              = ixgbevf_get_regs,
 622         .reta_update          = ixgbe_dev_rss_reta_update,
 623         .reta_query           = ixgbe_dev_rss_reta_query,
 624         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 625         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 626 };
 627
 628 /* store statistics names and its offset in stats structure */
 629 struct rte_ixgbe_xstats_name_off {
 630         char name[RTE_ETH_XSTATS_NAME_SIZE];
 631         unsigned offset;
 632 };
 633
 634 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 635         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 636         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 637         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 638         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 639         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 640         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 641         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 642         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 643         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 644         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 645         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 646         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 647         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 648         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 649         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 650                 prc1023)},
 651         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 652                 prc1522)},
 653         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 654         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 655         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 656         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 657         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 658         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 659         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 660         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 661         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 662         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 663         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 664         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 665         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 666         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 667         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 668         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 669         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 670                 ptc1023)},
 671         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 672                 ptc1522)},
 673         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 674         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 675         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 676         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 677
 678         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 679                 fdirustat_add)},
 680         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 681                 fdirustat_remove)},
 682         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 683                 fdirfstat_fadd)},
 684         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 685                 fdirfstat_fremove)},
 686         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 687                 fdirmatch)},
 688         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 689                 fdirmiss)},
 690
 691         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 692         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 693         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 694                 fclast)},
 695         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 696         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 697         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 698         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 699         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 700                 fcoe_noddp)},
 701         {"rx_fcoe_no_direct_data_placement_ext_buff",
 702                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 703
 704         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 705                 lxontxc)},
 706         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 707                 lxonrxc)},
 708         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 709                 lxofftxc)},
 710         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 711                 lxoffrxc)},
 712         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 713 };
 714
 715 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 716                            sizeof(rte_ixgbe_stats_strings[0]))
 717
 718 /* MACsec statistics */
 719 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 720         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 721                 out_pkts_untagged)},
 722         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 723                 out_pkts_encrypted)},
 724         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 725                 out_pkts_protected)},
 726         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 727                 out_octets_encrypted)},
 728         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 729                 out_octets_protected)},
 730         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 731                 in_pkts_untagged)},
 732         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_badtag)},
 734         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 735                 in_pkts_nosci)},
 736         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_unknownsci)},
 738         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 739                 in_octets_decrypted)},
 740         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 741                 in_octets_validated)},
 742         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_unchecked)},
 744         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_delayed)},
 746         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_late)},
 748         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_ok)},
 750         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_invalid)},
 752         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_notvalid)},
 754         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unusedsa)},
 756         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_notusingsa)},
 758 };
 759
 760 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 761                            sizeof(rte_ixgbe_macsec_strings[0]))
 762
 763 /* Per-queue statistics */
 764 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 765         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 766         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 767         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 768         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 769 };
 770
 771 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 772                            sizeof(rte_ixgbe_rxq_strings[0]))
 773 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 774
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 776         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 777         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 778         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 779                 pxon2offc)},
 780 };
 781
 782 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 783                            sizeof(rte_ixgbe_txq_strings[0]))
 784 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 787         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 788 };
 789
 790 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 791                 sizeof(rte_ixgbevf_stats_strings[0]))
 792
 793 /*
 794  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 795  */
 796 static inline int
 797 ixgbe_is_sfp(struct ixgbe_hw *hw)
 798 {
 799         switch (hw->phy.type) {
 800         case ixgbe_phy_sfp_avago:
 801         case ixgbe_phy_sfp_ftl:
 802         case ixgbe_phy_sfp_intel:
 803         case ixgbe_phy_sfp_unknown:
 804         case ixgbe_phy_sfp_passive_tyco:
 805         case ixgbe_phy_sfp_passive_unknown:
 806                 return 1;
 807         default:
 808                 return 0;
 809         }
 810 }
 811
 812 static inline int32_t
 813 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 814 {
 815         uint32_t ctrl_ext;
 816         int32_t status;
 817
 818         status = ixgbe_reset_hw(hw);
 819
 820         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 821         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 822         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 823         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 824         IXGBE_WRITE_FLUSH(hw);
 825
 826         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 827                 status = IXGBE_SUCCESS;
 828         return status;
 829 }
 830
 831 static inline void
 832 ixgbe_enable_intr(struct rte_eth_dev *dev)
 833 {
 834         struct ixgbe_interrupt *intr =
 835                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 836         struct ixgbe_hw *hw =
 837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 838
 839         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 840         IXGBE_WRITE_FLUSH(hw);
 841 }
 842
 843 /*
 844  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 845  */
 846 static void
 847 ixgbe_disable_intr(struct ixgbe_hw *hw)
 848 {
 849         PMD_INIT_FUNC_TRACE();
 850
 851         if (hw->mac.type == ixgbe_mac_82598EB) {
 852                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 853         } else {
 854                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 857         }
 858         IXGBE_WRITE_FLUSH(hw);
 859 }
 860
 861 /*
 862  * This function resets queue statistics mapping registers.
 863  * From Niantic datasheet, Initialization of Statistics section:
 864  * "...if software requires the queue counters, the RQSMR and TQSM registers
 865  * must be re-programmed following a device reset.
 866  */
 867 static void
 868 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 869 {
 870         uint32_t i;
 871
 872         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 873                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 874                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 875         }
 876 }
 877
 878
 879 static int
 880 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 881                                   uint16_t queue_id,
 882                                   uint8_t stat_idx,
 883                                   uint8_t is_rx)
 884 {
 885 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 886 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 887 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 888
 889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 890         struct ixgbe_stat_mapping_registers *stat_mappings =
 891                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 892         uint32_t qsmr_mask = 0;
 893         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 894         uint32_t q_map;
 895         uint8_t n, offset;
 896
 897         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 898                 (hw->mac.type != ixgbe_mac_X540) &&
 899                 (hw->mac.type != ixgbe_mac_X550) &&
 900                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_a))
 902                 return -ENOSYS;
 903
 904         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 905                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 906                      queue_id, stat_idx);
 907
 908         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 909         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 910                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 911                 return -EIO;
 912         }
 913         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 914
 915         /* Now clear any previous stat_idx set */
 916         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 917         if (!is_rx)
 918                 stat_mappings->tqsm[n] &= ~clearing_mask;
 919         else
 920                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 921
 922         q_map = (uint32_t)stat_idx;
 923         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 924         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 925         if (!is_rx)
 926                 stat_mappings->tqsm[n] |= qsmr_mask;
 927         else
 928                 stat_mappings->rqsmr[n] |= qsmr_mask;
 929
 930         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 931                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 932                      queue_id, stat_idx);
 933         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 934                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 935
 936         /* Now write the mapping in the appropriate register */
 937         if (is_rx) {
 938                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 939                              stat_mappings->rqsmr[n], n);
 940                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 941         } else {
 942                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 943                              stat_mappings->tqsm[n], n);
 944                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 945         }
 946         return 0;
 947 }
 948
 949 static void
 950 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 951 {
 952         struct ixgbe_stat_mapping_registers *stat_mappings =
 953                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 955         int i;
 956
 957         /* write whatever was in stat mapping table to the NIC */
 958         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 959                 /* rx */
 960                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 961
 962                 /* tx */
 963                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 964         }
 965 }
 966
 967 static void
 968 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 969 {
 970         uint8_t i;
 971         struct ixgbe_dcb_tc_config *tc;
 972         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 973
 974         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 975         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 976         for (i = 0; i < dcb_max_tc; i++) {
 977                 tc = &dcb_config->tc_config[i];
 978                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 980                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 981                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 983                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 984                 tc->pfc = ixgbe_dcb_pfc_disabled;
 985         }
 986
 987         /* Initialize default user to priority mapping, UPx->TC0 */
 988         tc = &dcb_config->tc_config[0];
 989         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 990         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 992                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 993                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 994         }
 995         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 996         dcb_config->pfc_mode_enable = false;
 997         dcb_config->vt_mode = true;
 998         dcb_config->round_robin_enable = false;
 999         /* support all DCB capabilities in 82599 */
1000         dcb_config->support.capabilities = 0xFF;
1001
1002         /*we only support 4 Tcs for X540, X550 */
1003         if (hw->mac.type == ixgbe_mac_X540 ||
1004                 hw->mac.type == ixgbe_mac_X550 ||
1005                 hw->mac.type == ixgbe_mac_X550EM_x ||
1006                 hw->mac.type == ixgbe_mac_X550EM_a) {
1007                 dcb_config->num_tcs.pg_tcs = 4;
1008                 dcb_config->num_tcs.pfc_tcs = 4;
1009         }
1010 }
1011
1012 /*
1013  * Ensure that all locks are released before first NVM or PHY access
1014  */
1015 static void
1016 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1017 {
1018         uint16_t mask;
1019
1020         /*
1021          * Phy lock should not fail in this early stage. If this is the case,
1022          * it is due to an improper exit of the application.
1023          * So force the release of the faulty lock. Release of common lock
1024          * is done automatically by swfw_sync function.
1025          */
1026         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1027         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1028                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1029         }
1030         ixgbe_release_swfw_semaphore(hw, mask);
1031
1032         /*
1033          * These ones are more tricky since they are common to all ports; but
1034          * swfw_sync retries last long enough (1s) to be almost sure that if
1035          * lock can not be taken it is due to an improper lock of the
1036          * semaphore.
1037          */
1038         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1039         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1040                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1041         }
1042         ixgbe_release_swfw_semaphore(hw, mask);
1043 }
1044
1045 /*
1046  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1047  * It returns 0 on success.
1048  */
1049 static int
1050 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1051 {
1052         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1053         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1054         struct ixgbe_hw *hw =
1055                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1056         struct ixgbe_vfta *shadow_vfta =
1057                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1058         struct ixgbe_hwstrip *hwstrip =
1059                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1060         struct ixgbe_dcb_config *dcb_config =
1061                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1062         struct ixgbe_filter_info *filter_info =
1063                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1064         struct ixgbe_bw_conf *bw_conf =
1065                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1066         uint32_t ctrl_ext;
1067         uint16_t csum;
1068         int diag, i;
1069
1070         PMD_INIT_FUNC_TRACE();
1071
1072         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1073         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1074         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1075         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1076
1077         /*
1078          * For secondary processes, we don't initialise any further as primary
1079          * has already done this work. Only check we don't need a different
1080          * RX and TX function.
1081          */
1082         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1083                 struct ixgbe_tx_queue *txq;
1084                 /* TX queue function in primary, set by last queue initialized
1085                  * Tx queue may not initialized by primary process
1086                  */
1087                 if (eth_dev->data->tx_queues) {
1088                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1089                         ixgbe_set_tx_function(eth_dev, txq);
1090                 } else {
1091                         /* Use default TX function if we get here */
1092                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1093                                      "Using default TX function.");
1094                 }
1095
1096                 ixgbe_set_rx_function(eth_dev);
1097
1098                 return 0;
1099         }
1100
1101         rte_eth_copy_pci_info(eth_dev, pci_dev);
1102
1103         /* Vendor and Device ID need to be set before init of shared code */
1104         hw->device_id = pci_dev->id.device_id;
1105         hw->vendor_id = pci_dev->id.vendor_id;
1106         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1107         hw->allow_unsupported_sfp = 1;
1108
1109         /* Initialize the shared code (base driver) */
1110 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1111         diag = ixgbe_bypass_init_shared_code(hw);
1112 #else
1113         diag = ixgbe_init_shared_code(hw);
1114 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1115
1116         if (diag != IXGBE_SUCCESS) {
1117                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1118                 return -EIO;
1119         }
1120
1121         /* pick up the PCI bus settings for reporting later */
1122         ixgbe_get_bus_info(hw);
1123
1124         /* Unlock any pending hardware semaphore */
1125         ixgbe_swfw_lock_reset(hw);
1126
1127 #ifdef RTE_LIBRTE_SECURITY
1128         /* Initialize security_ctx only for primary process*/
1129         if (ixgbe_ipsec_ctx_create(eth_dev))
1130                 return -ENOMEM;
1131 #endif
1132
1133         /* Initialize DCB configuration*/
1134         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1135         ixgbe_dcb_init(hw, dcb_config);
1136         /* Get Hardware Flow Control setting */
1137         hw->fc.requested_mode = ixgbe_fc_full;
1138         hw->fc.current_mode = ixgbe_fc_full;
1139         hw->fc.pause_time = IXGBE_FC_PAUSE;
1140         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1141                 hw->fc.low_water[i] = IXGBE_FC_LO;
1142                 hw->fc.high_water[i] = IXGBE_FC_HI;
1143         }
1144         hw->fc.send_xon = 1;
1145
1146         /* Make sure we have a good EEPROM before we read from it */
1147         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150                 return -EIO;
1151         }
1152
1153 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1154         diag = ixgbe_bypass_init_hw(hw);
1155 #else
1156         diag = ixgbe_init_hw(hw);
1157 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1158
1159         /*
1160          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1161          * is called too soon after the kernel driver unbinding/binding occurs.
1162          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1163          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1164          * also called. See ixgbe_identify_phy_82599(). The reason for the
1165          * failure is not known, and only occuts when virtualisation features
1166          * are disabled in the bios. A delay of 100ms  was found to be enough by
1167          * trial-and-error, and is doubled to be safe.
1168          */
1169         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1170                 rte_delay_ms(200);
1171                 diag = ixgbe_init_hw(hw);
1172         }
1173
1174         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1175                 diag = IXGBE_SUCCESS;
1176
1177         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1178                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1179                              "LOM.  Please be aware there may be issues associated "
1180                              "with your hardware.");
1181                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1182                              "please contact your Intel or hardware representative "
1183                              "who provided you with this hardware.");
1184         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1186         if (diag) {
1187                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188                 return -EIO;
1189         }
1190
1191         /* Reset the hw statistics */
1192         ixgbe_dev_stats_reset(eth_dev);
1193
1194         /* disable interrupt */
1195         ixgbe_disable_intr(hw);
1196
1197         /* reset mappings for queue statistics hw counters*/
1198         ixgbe_reset_qstat_mappings(hw);
1199
1200         /* Allocate memory for storing MAC addresses */
1201         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1202                                                hw->mac.num_rar_entries, 0);
1203         if (eth_dev->data->mac_addrs == NULL) {
1204                 PMD_INIT_LOG(ERR,
1205                              "Failed to allocate %u bytes needed to store "
1206                              "MAC addresses",
1207                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1208                 return -ENOMEM;
1209         }
1210         /* Copy the permanent MAC address */
1211         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1212                         &eth_dev->data->mac_addrs[0]);
1213
1214         /* Allocate memory for storing hash filter MAC addresses */
1215         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1216                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1217         if (eth_dev->data->hash_mac_addrs == NULL) {
1218                 PMD_INIT_LOG(ERR,
1219                              "Failed to allocate %d bytes needed to store MAC addresses",
1220                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221                 return -ENOMEM;
1222         }
1223
1224         /* initialize the vfta */
1225         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1226
1227         /* initialize the hw strip bitmap*/
1228         memset(hwstrip, 0, sizeof(*hwstrip));
1229
1230         /* initialize PF if max_vfs not zero */
1231         ixgbe_pf_host_init(eth_dev);
1232
1233         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1234         /* let hardware know driver is loaded */
1235         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1236         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1237         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1238         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1239         IXGBE_WRITE_FLUSH(hw);
1240
1241         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1242                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1243                              (int) hw->mac.type, (int) hw->phy.type,
1244                              (int) hw->phy.sfp_type);
1245         else
1246                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1247                              (int) hw->mac.type, (int) hw->phy.type);
1248
1249         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1250                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1251                      pci_dev->id.device_id);
1252
1253         rte_intr_callback_register(intr_handle,
1254                                    ixgbe_dev_interrupt_handler, eth_dev);
1255
1256         /* enable uio/vfio intr/eventfd mapping */
1257         rte_intr_enable(intr_handle);
1258
1259         /* enable support intr */
1260         ixgbe_enable_intr(eth_dev);
1261
1262         /* initialize filter info */
1263         memset(filter_info, 0,
1264                sizeof(struct ixgbe_filter_info));
1265
1266         /* initialize 5tuple filter list */
1267         TAILQ_INIT(&filter_info->fivetuple_list);
1268
1269         /* initialize flow director filter list & hash */
1270         ixgbe_fdir_filter_init(eth_dev);
1271
1272         /* initialize l2 tunnel filter list & hash */
1273         ixgbe_l2_tn_filter_init(eth_dev);
1274
1275         /* initialize flow filter lists */
1276         ixgbe_filterlist_init();
1277
1278         /* initialize bandwidth configuration info */
1279         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1280
1281         /* initialize Traffic Manager configuration */
1282         ixgbe_tm_conf_init(eth_dev);
1283
1284         return 0;
1285 }
1286
1287 static int
1288 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1289 {
1290         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1291         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1292         struct ixgbe_hw *hw;
1293         int retries = 0;
1294         int ret;
1295
1296         PMD_INIT_FUNC_TRACE();
1297
1298         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1299                 return -EPERM;
1300
1301         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1302
1303         if (hw->adapter_stopped == 0)
1304                 ixgbe_dev_close(eth_dev);
1305
1306         eth_dev->dev_ops = NULL;
1307         eth_dev->rx_pkt_burst = NULL;
1308         eth_dev->tx_pkt_burst = NULL;
1309
1310         /* Unlock any pending hardware semaphore */
1311         ixgbe_swfw_lock_reset(hw);
1312
1313         /* disable uio intr before callback unregister */
1314         rte_intr_disable(intr_handle);
1315
1316         do {
1317                 ret = rte_intr_callback_unregister(intr_handle,
1318                                 ixgbe_dev_interrupt_handler, eth_dev);
1319                 if (ret >= 0) {
1320                         break;
1321                 } else if (ret != -EAGAIN) {
1322                         PMD_INIT_LOG(ERR,
1323                                 "intr callback unregister failed: %d",
1324                                 ret);
1325                         return ret;
1326                 }
1327                 rte_delay_ms(100);
1328         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1329
1330         /* uninitialize PF if max_vfs not zero */
1331         ixgbe_pf_host_uninit(eth_dev);
1332
1333         rte_free(eth_dev->data->mac_addrs);
1334         eth_dev->data->mac_addrs = NULL;
1335
1336         rte_free(eth_dev->data->hash_mac_addrs);
1337         eth_dev->data->hash_mac_addrs = NULL;
1338
1339         /* remove all the fdir filters & hash */
1340         ixgbe_fdir_filter_uninit(eth_dev);
1341
1342         /* remove all the L2 tunnel filters & hash */
1343         ixgbe_l2_tn_filter_uninit(eth_dev);
1344
1345         /* Remove all ntuple filters of the device */
1346         ixgbe_ntuple_filter_uninit(eth_dev);
1347
1348         /* clear all the filters list */
1349         ixgbe_filterlist_flush();
1350
1351         /* Remove all Traffic Manager configuration */
1352         ixgbe_tm_conf_uninit(eth_dev);
1353
1354 #ifdef RTE_LIBRTE_SECURITY
1355         rte_free(eth_dev->security_ctx);
1356 #endif
1357
1358         return 0;
1359 }
1360
1361 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1362 {
1363         struct ixgbe_filter_info *filter_info =
1364                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1365         struct ixgbe_5tuple_filter *p_5tuple;
1366
1367         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1368                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1369                              p_5tuple,
1370                              entries);
1371                 rte_free(p_5tuple);
1372         }
1373         memset(filter_info->fivetuple_mask, 0,
1374                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1375
1376         return 0;
1377 }
1378
1379 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1380 {
1381         struct ixgbe_hw_fdir_info *fdir_info =
1382                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1383         struct ixgbe_fdir_filter *fdir_filter;
1384
1385                 if (fdir_info->hash_map)
1386                 rte_free(fdir_info->hash_map);
1387         if (fdir_info->hash_handle)
1388                 rte_hash_free(fdir_info->hash_handle);
1389
1390         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1391                 TAILQ_REMOVE(&fdir_info->fdir_list,
1392                              fdir_filter,
1393                              entries);
1394                 rte_free(fdir_filter);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1401 {
1402         struct ixgbe_l2_tn_info *l2_tn_info =
1403                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1404         struct ixgbe_l2_tn_filter *l2_tn_filter;
1405
1406         if (l2_tn_info->hash_map)
1407                 rte_free(l2_tn_info->hash_map);
1408         if (l2_tn_info->hash_handle)
1409                 rte_hash_free(l2_tn_info->hash_handle);
1410
1411         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1412                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1413                              l2_tn_filter,
1414                              entries);
1415                 rte_free(l2_tn_filter);
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1422 {
1423         struct ixgbe_hw_fdir_info *fdir_info =
1424                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1425         char fdir_hash_name[RTE_HASH_NAMESIZE];
1426         struct rte_hash_parameters fdir_hash_params = {
1427                 .name = fdir_hash_name,
1428                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1429                 .key_len = sizeof(union ixgbe_atr_input),
1430                 .hash_func = rte_hash_crc,
1431                 .hash_func_init_val = 0,
1432                 .socket_id = rte_socket_id(),
1433         };
1434
1435         TAILQ_INIT(&fdir_info->fdir_list);
1436         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1437                  "fdir_%s", eth_dev->device->name);
1438         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1439         if (!fdir_info->hash_handle) {
1440                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1441                 return -EINVAL;
1442         }
1443         fdir_info->hash_map = rte_zmalloc("ixgbe",
1444                                           sizeof(struct ixgbe_fdir_filter *) *
1445                                           IXGBE_MAX_FDIR_FILTER_NUM,
1446                                           0);
1447         if (!fdir_info->hash_map) {
1448                 PMD_INIT_LOG(ERR,
1449                              "Failed to allocate memory for fdir hash map!");
1450                 return -ENOMEM;
1451         }
1452         fdir_info->mask_added = FALSE;
1453
1454         return 0;
1455 }
1456
1457 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1458 {
1459         struct ixgbe_l2_tn_info *l2_tn_info =
1460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1461         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1462         struct rte_hash_parameters l2_tn_hash_params = {
1463                 .name = l2_tn_hash_name,
1464                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1465                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1466                 .hash_func = rte_hash_crc,
1467                 .hash_func_init_val = 0,
1468                 .socket_id = rte_socket_id(),
1469         };
1470
1471         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1472         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1473                  "l2_tn_%s", eth_dev->device->name);
1474         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1475         if (!l2_tn_info->hash_handle) {
1476                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1477                 return -EINVAL;
1478         }
1479         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1480                                    sizeof(struct ixgbe_l2_tn_filter *) *
1481                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1482                                    0);
1483         if (!l2_tn_info->hash_map) {
1484                 PMD_INIT_LOG(ERR,
1485                         "Failed to allocate memory for L2 TN hash map!");
1486                 return -ENOMEM;
1487         }
1488         l2_tn_info->e_tag_en = FALSE;
1489         l2_tn_info->e_tag_fwd_en = FALSE;
1490         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1491
1492         return 0;
1493 }
1494 /*
1495  * Negotiate mailbox API version with the PF.
1496  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1497  * Then we try to negotiate starting with the most recent one.
1498  * If all negotiation attempts fail, then we will proceed with
1499  * the default one (ixgbe_mbox_api_10).
1500  */
1501 static void
1502 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1503 {
1504         int32_t i;
1505
1506         /* start with highest supported, proceed down */
1507         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1508                 ixgbe_mbox_api_12,
1509                 ixgbe_mbox_api_11,
1510                 ixgbe_mbox_api_10,
1511         };
1512
1513         for (i = 0;
1514                         i != RTE_DIM(sup_ver) &&
1515                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1516                         i++)
1517                 ;
1518 }
1519
1520 static void
1521 generate_random_mac_addr(struct ether_addr *mac_addr)
1522 {
1523         uint64_t random;
1524
1525         /* Set Organizationally Unique Identifier (OUI) prefix. */
1526         mac_addr->addr_bytes[0] = 0x00;
1527         mac_addr->addr_bytes[1] = 0x09;
1528         mac_addr->addr_bytes[2] = 0xC0;
1529         /* Force indication of locally assigned MAC address. */
1530         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1531         /* Generate the last 3 bytes of the MAC address with a random number. */
1532         random = rte_rand();
1533         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1534 }
1535
1536 /*
1537  * Virtual Function device init
1538  */
1539 static int
1540 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1541 {
1542         int diag;
1543         uint32_t tc, tcs;
1544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1546         struct ixgbe_hw *hw =
1547                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1548         struct ixgbe_vfta *shadow_vfta =
1549                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1550         struct ixgbe_hwstrip *hwstrip =
1551                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1552         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1553
1554         PMD_INIT_FUNC_TRACE();
1555
1556         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1557         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1558         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1559
1560         /* for secondary processes, we don't initialise any further as primary
1561          * has already done this work. Only check we don't need a different
1562          * RX function
1563          */
1564         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1565                 struct ixgbe_tx_queue *txq;
1566                 /* TX queue function in primary, set by last queue initialized
1567                  * Tx queue may not initialized by primary process
1568                  */
1569                 if (eth_dev->data->tx_queues) {
1570                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1571                         ixgbe_set_tx_function(eth_dev, txq);
1572                 } else {
1573                         /* Use default TX function if we get here */
1574                         PMD_INIT_LOG(NOTICE,
1575                                      "No TX queues configured yet. Using default TX function.");
1576                 }
1577
1578                 ixgbe_set_rx_function(eth_dev);
1579
1580                 return 0;
1581         }
1582
1583         rte_eth_copy_pci_info(eth_dev, pci_dev);
1584
1585         hw->device_id = pci_dev->id.device_id;
1586         hw->vendor_id = pci_dev->id.vendor_id;
1587         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1588
1589         /* initialize the vfta */
1590         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1591
1592         /* initialize the hw strip bitmap*/
1593         memset(hwstrip, 0, sizeof(*hwstrip));
1594
1595         /* Initialize the shared code (base driver) */
1596         diag = ixgbe_init_shared_code(hw);
1597         if (diag != IXGBE_SUCCESS) {
1598                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1599                 return -EIO;
1600         }
1601
1602         /* init_mailbox_params */
1603         hw->mbx.ops.init_params(hw);
1604
1605         /* Reset the hw statistics */
1606         ixgbevf_dev_stats_reset(eth_dev);
1607
1608         /* Disable the interrupts for VF */
1609         ixgbevf_intr_disable(hw);
1610
1611         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1612         diag = hw->mac.ops.reset_hw(hw);
1613
1614         /*
1615          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1616          * the underlying PF driver has not assigned a MAC address to the VF.
1617          * In this case, assign a random MAC address.
1618          */
1619         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1620                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1621                 return diag;
1622         }
1623
1624         /* negotiate mailbox API version to use with the PF. */
1625         ixgbevf_negotiate_api(hw);
1626
1627         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1628         ixgbevf_get_queues(hw, &tcs, &tc);
1629
1630         /* Allocate memory for storing MAC addresses */
1631         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1632                                                hw->mac.num_rar_entries, 0);
1633         if (eth_dev->data->mac_addrs == NULL) {
1634                 PMD_INIT_LOG(ERR,
1635                              "Failed to allocate %u bytes needed to store "
1636                              "MAC addresses",
1637                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1638                 return -ENOMEM;
1639         }
1640
1641         /* Generate a random MAC address, if none was assigned by PF. */
1642         if (is_zero_ether_addr(perm_addr)) {
1643                 generate_random_mac_addr(perm_addr);
1644                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1645                 if (diag) {
1646                         rte_free(eth_dev->data->mac_addrs);
1647                         eth_dev->data->mac_addrs = NULL;
1648                         return diag;
1649                 }
1650                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1651                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1652                              "%02x:%02x:%02x:%02x:%02x:%02x",
1653                              perm_addr->addr_bytes[0],
1654                              perm_addr->addr_bytes[1],
1655                              perm_addr->addr_bytes[2],
1656                              perm_addr->addr_bytes[3],
1657                              perm_addr->addr_bytes[4],
1658                              perm_addr->addr_bytes[5]);
1659         }
1660
1661         /* Copy the permanent MAC address */
1662         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1663
1664         /* reset the hardware with the new settings */
1665         diag = hw->mac.ops.start_hw(hw);
1666         switch (diag) {
1667         case  0:
1668                 break;
1669
1670         default:
1671                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672                 return -EIO;
1673         }
1674
1675         rte_intr_callback_register(intr_handle,
1676                                    ixgbevf_dev_interrupt_handler, eth_dev);
1677         rte_intr_enable(intr_handle);
1678         ixgbevf_intr_enable(hw);
1679
1680         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1681                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1682                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1683
1684         return 0;
1685 }
1686
1687 /* Virtual Function device uninit */
1688
1689 static int
1690 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1691 {
1692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694         struct ixgbe_hw *hw;
1695
1696         PMD_INIT_FUNC_TRACE();
1697
1698         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1699                 return -EPERM;
1700
1701         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1702
1703         if (hw->adapter_stopped == 0)
1704                 ixgbevf_dev_close(eth_dev);
1705
1706         eth_dev->dev_ops = NULL;
1707         eth_dev->rx_pkt_burst = NULL;
1708         eth_dev->tx_pkt_burst = NULL;
1709
1710         /* Disable the interrupts for VF */
1711         ixgbevf_intr_disable(hw);
1712
1713         rte_free(eth_dev->data->mac_addrs);
1714         eth_dev->data->mac_addrs = NULL;
1715
1716         rte_intr_disable(intr_handle);
1717         rte_intr_callback_unregister(intr_handle,
1718                                      ixgbevf_dev_interrupt_handler, eth_dev);
1719
1720         return 0;
1721 }
1722
1723 static int
1724 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1725                 struct rte_pci_device *pci_dev)
1726 {
1727         char name[RTE_ETH_NAME_MAX_LEN];
1728         struct rte_eth_dev *pf_ethdev;
1729         struct rte_eth_devargs eth_da;
1730         int i, retval;
1731
1732         if (pci_dev->device.devargs) {
1733                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1734                                 &eth_da);
1735                 if (retval)
1736                         return retval;
1737         } else
1738                 memset(&eth_da, 0, sizeof(eth_da));
1739
1740         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1741                 sizeof(struct ixgbe_adapter),
1742                 eth_dev_pci_specific_init, pci_dev,
1743                 eth_ixgbe_dev_init, NULL);
1744
1745         if (retval || eth_da.nb_representor_ports < 1)
1746                 return retval;
1747
1748         /* probe VF representor ports */
1749         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1750
1751         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1752                 struct ixgbe_vf_info *vfinfo;
1753                 struct ixgbe_vf_representor representor;
1754
1755                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1756                         pf_ethdev->data->dev_private);
1757                 if (vfinfo == NULL) {
1758                         PMD_DRV_LOG(ERR,
1759                                 "no virtual functions supported by PF");
1760                         break;
1761                 }
1762
1763                 representor.vf_id = eth_da.representor_ports[i];
1764                 representor.switch_domain_id = vfinfo->switch_domain_id;
1765                 representor.pf_ethdev = pf_ethdev;
1766
1767                 /* representor port net_bdf_port */
1768                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1769                         pci_dev->device.name,
1770                         eth_da.representor_ports[i]);
1771
1772                 retval = rte_eth_dev_create(&pci_dev->device, name,
1773                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1774                         ixgbe_vf_representor_init, &representor);
1775
1776                 if (retval)
1777                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1778                                 "representor %s.", name);
1779         }
1780
1781         return 0;
1782 }
1783
1784 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1785 {
1786         struct rte_eth_dev *ethdev;
1787
1788         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1789         if (!ethdev)
1790                 return -ENODEV;
1791
1792         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1793                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1794         else
1795                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1796 }
1797
1798 static struct rte_pci_driver rte_ixgbe_pmd = {
1799         .id_table = pci_id_ixgbe_map,
1800         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1801                      RTE_PCI_DRV_IOVA_AS_VA,
1802         .probe = eth_ixgbe_pci_probe,
1803         .remove = eth_ixgbe_pci_remove,
1804 };
1805
1806 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1807         struct rte_pci_device *pci_dev)
1808 {
1809         return rte_eth_dev_pci_generic_probe(pci_dev,
1810                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1811 }
1812
1813 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1814 {
1815         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1816 }
1817
1818 /*
1819  * virtual function driver struct
1820  */
1821 static struct rte_pci_driver rte_ixgbevf_pmd = {
1822         .id_table = pci_id_ixgbevf_map,
1823         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1824         .probe = eth_ixgbevf_pci_probe,
1825         .remove = eth_ixgbevf_pci_remove,
1826 };
1827
1828 static int
1829 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1830 {
1831         struct ixgbe_hw *hw =
1832                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         struct ixgbe_vfta *shadow_vfta =
1834                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1835         uint32_t vfta;
1836         uint32_t vid_idx;
1837         uint32_t vid_bit;
1838
1839         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1840         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1841         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1842         if (on)
1843                 vfta |= vid_bit;
1844         else
1845                 vfta &= ~vid_bit;
1846         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1847
1848         /* update local VFTA copy */
1849         shadow_vfta->vfta[vid_idx] = vfta;
1850
1851         return 0;
1852 }
1853
1854 static void
1855 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1856 {
1857         if (on)
1858                 ixgbe_vlan_hw_strip_enable(dev, queue);
1859         else
1860                 ixgbe_vlan_hw_strip_disable(dev, queue);
1861 }
1862
1863 static int
1864 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1865                     enum rte_vlan_type vlan_type,
1866                     uint16_t tpid)
1867 {
1868         struct ixgbe_hw *hw =
1869                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         int ret = 0;
1871         uint32_t reg;
1872         uint32_t qinq;
1873
1874         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1875         qinq &= IXGBE_DMATXCTL_GDV;
1876
1877         switch (vlan_type) {
1878         case ETH_VLAN_TYPE_INNER:
1879                 if (qinq) {
1880                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1882                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1883                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1884                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1885                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1886                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1887                 } else {
1888                         ret = -ENOTSUP;
1889                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1890                                     " by single VLAN");
1891                 }
1892                 break;
1893         case ETH_VLAN_TYPE_OUTER:
1894                 if (qinq) {
1895                         /* Only the high 16-bits is valid */
1896                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1897                                         IXGBE_EXVET_VET_EXT_SHIFT);
1898                 } else {
1899                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1900                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1901                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1902                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1903                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1904                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1905                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1906                 }
1907
1908                 break;
1909         default:
1910                 ret = -EINVAL;
1911                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1912                 break;
1913         }
1914
1915         return ret;
1916 }
1917
1918 void
1919 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1920 {
1921         struct ixgbe_hw *hw =
1922                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923         uint32_t vlnctrl;
1924
1925         PMD_INIT_FUNC_TRACE();
1926
1927         /* Filter Table Disable */
1928         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1929         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1930
1931         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1932 }
1933
1934 void
1935 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1936 {
1937         struct ixgbe_hw *hw =
1938                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct ixgbe_vfta *shadow_vfta =
1940                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1941         uint32_t vlnctrl;
1942         uint16_t i;
1943
1944         PMD_INIT_FUNC_TRACE();
1945
1946         /* Filter Table Enable */
1947         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1948         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1949         vlnctrl |= IXGBE_VLNCTRL_VFE;
1950
1951         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1952
1953         /* write whatever is in local vfta copy */
1954         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1955                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1956 }
1957
1958 static void
1959 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1960 {
1961         struct ixgbe_hwstrip *hwstrip =
1962                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1963         struct ixgbe_rx_queue *rxq;
1964
1965         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1966                 return;
1967
1968         if (on)
1969                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1970         else
1971                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1972
1973         if (queue >= dev->data->nb_rx_queues)
1974                 return;
1975
1976         rxq = dev->data->rx_queues[queue];
1977
1978         if (on)
1979                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1980         else
1981                 rxq->vlan_flags = PKT_RX_VLAN;
1982 }
1983
1984 static void
1985 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1986 {
1987         struct ixgbe_hw *hw =
1988                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1989         uint32_t ctrl;
1990
1991         PMD_INIT_FUNC_TRACE();
1992
1993         if (hw->mac.type == ixgbe_mac_82598EB) {
1994                 /* No queue level support */
1995                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1996                 return;
1997         }
1998
1999         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2000         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2001         ctrl &= ~IXGBE_RXDCTL_VME;
2002         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2003
2004         /* record those setting for HW strip per queue */
2005         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2006 }
2007
2008 static void
2009 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2010 {
2011         struct ixgbe_hw *hw =
2012                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013         uint32_t ctrl;
2014
2015         PMD_INIT_FUNC_TRACE();
2016
2017         if (hw->mac.type == ixgbe_mac_82598EB) {
2018                 /* No queue level supported */
2019                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2020                 return;
2021         }
2022
2023         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2024         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2025         ctrl |= IXGBE_RXDCTL_VME;
2026         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2027
2028         /* record those setting for HW strip per queue */
2029         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2030 }
2031
2032 static void
2033 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2034 {
2035         struct ixgbe_hw *hw =
2036                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2037         uint32_t ctrl;
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         /* DMATXCTRL: Geric Double VLAN Disable */
2042         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2043         ctrl &= ~IXGBE_DMATXCTL_GDV;
2044         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2045
2046         /* CTRL_EXT: Global Double VLAN Disable */
2047         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2048         ctrl &= ~IXGBE_EXTENDED_VLAN;
2049         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2050
2051 }
2052
2053 static void
2054 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2055 {
2056         struct ixgbe_hw *hw =
2057                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058         uint32_t ctrl;
2059
2060         PMD_INIT_FUNC_TRACE();
2061
2062         /* DMATXCTRL: Geric Double VLAN Enable */
2063         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2064         ctrl |= IXGBE_DMATXCTL_GDV;
2065         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2066
2067         /* CTRL_EXT: Global Double VLAN Enable */
2068         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2069         ctrl |= IXGBE_EXTENDED_VLAN;
2070         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2071
2072         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2073         if (hw->mac.type == ixgbe_mac_X550 ||
2074             hw->mac.type == ixgbe_mac_X550EM_x ||
2075             hw->mac.type == ixgbe_mac_X550EM_a) {
2076                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2077                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2078                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2079         }
2080
2081         /*
2082          * VET EXT field in the EXVET register = 0x8100 by default
2083          * So no need to change. Same to VT field of DMATXCTL register
2084          */
2085 }
2086
2087 void
2088 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2089 {
2090         struct ixgbe_hw *hw =
2091                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2093         uint32_t ctrl;
2094         uint16_t i;
2095         struct ixgbe_rx_queue *rxq;
2096         bool on;
2097
2098         PMD_INIT_FUNC_TRACE();
2099
2100         if (hw->mac.type == ixgbe_mac_82598EB) {
2101                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2102                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2103                         ctrl |= IXGBE_VLNCTRL_VME;
2104                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2105                 } else {
2106                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2107                         ctrl &= ~IXGBE_VLNCTRL_VME;
2108                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2109                 }
2110         } else {
2111                 /*
2112                  * Other 10G NIC, the VLAN strip can be setup
2113                  * per queue in RXDCTL
2114                  */
2115                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2116                         rxq = dev->data->rx_queues[i];
2117                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2118                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2119                                 ctrl |= IXGBE_RXDCTL_VME;
2120                                 on = TRUE;
2121                         } else {
2122                                 ctrl &= ~IXGBE_RXDCTL_VME;
2123                                 on = FALSE;
2124                         }
2125                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2126
2127                         /* record those setting for HW strip per queue */
2128                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2129                 }
2130         }
2131 }
2132
2133 static int
2134 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2135 {
2136         struct rte_eth_rxmode *rxmode;
2137         rxmode = &dev->data->dev_conf.rxmode;
2138
2139         if (mask & ETH_VLAN_STRIP_MASK) {
2140                 ixgbe_vlan_hw_strip_config(dev);
2141         }
2142
2143         if (mask & ETH_VLAN_FILTER_MASK) {
2144                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2145                         ixgbe_vlan_hw_filter_enable(dev);
2146                 else
2147                         ixgbe_vlan_hw_filter_disable(dev);
2148         }
2149
2150         if (mask & ETH_VLAN_EXTEND_MASK) {
2151                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2152                         ixgbe_vlan_hw_extend_enable(dev);
2153                 else
2154                         ixgbe_vlan_hw_extend_disable(dev);
2155         }
2156
2157         return 0;
2158 }
2159
2160 static void
2161 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2162 {
2163         struct ixgbe_hw *hw =
2164                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2166         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2167
2168         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2169         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2170 }
2171
2172 static int
2173 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2174 {
2175         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2176
2177         switch (nb_rx_q) {
2178         case 1:
2179         case 2:
2180                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2181                 break;
2182         case 4:
2183                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2184                 break;
2185         default:
2186                 return -EINVAL;
2187         }
2188
2189         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2190                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2191         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2192                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2193         return 0;
2194 }
2195
2196 static int
2197 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2198 {
2199         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2202         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2203
2204         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2205                 /* check multi-queue mode */
2206                 switch (dev_conf->rxmode.mq_mode) {
2207                 case ETH_MQ_RX_VMDQ_DCB:
2208                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2209                         break;
2210                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2211                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2212                         PMD_INIT_LOG(ERR, "SRIOV active,"
2213                                         " unsupported mq_mode rx %d.",
2214                                         dev_conf->rxmode.mq_mode);
2215                         return -EINVAL;
2216                 case ETH_MQ_RX_RSS:
2217                 case ETH_MQ_RX_VMDQ_RSS:
2218                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2219                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2220                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2221                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2222                                                 " invalid queue number"
2223                                                 " for VMDQ RSS, allowed"
2224                                                 " value are 1, 2 or 4.");
2225                                         return -EINVAL;
2226                                 }
2227                         break;
2228                 case ETH_MQ_RX_VMDQ_ONLY:
2229                 case ETH_MQ_RX_NONE:
2230                         /* if nothing mq mode configure, use default scheme */
2231                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2232                         break;
2233                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2234                         /* SRIOV only works in VMDq enable mode */
2235                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2236                                         " wrong mq_mode rx %d.",
2237                                         dev_conf->rxmode.mq_mode);
2238                         return -EINVAL;
2239                 }
2240
2241                 switch (dev_conf->txmode.mq_mode) {
2242                 case ETH_MQ_TX_VMDQ_DCB:
2243                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2244                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2245                         break;
2246                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2247                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2248                         break;
2249                 }
2250
2251                 /* check valid queue number */
2252                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2253                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2254                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2255                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2256                                         " must be less than or equal to %d.",
2257                                         nb_rx_q, nb_tx_q,
2258                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2259                         return -EINVAL;
2260                 }
2261         } else {
2262                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2263                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2264                                           " not supported.");
2265                         return -EINVAL;
2266                 }
2267                 /* check configuration for vmdb+dcb mode */
2268                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2269                         const struct rte_eth_vmdq_dcb_conf *conf;
2270
2271                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2272                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2273                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2274                                 return -EINVAL;
2275                         }
2276                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2277                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2278                                conf->nb_queue_pools == ETH_32_POOLS)) {
2279                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2280                                                 " nb_queue_pools must be %d or %d.",
2281                                                 ETH_16_POOLS, ETH_32_POOLS);
2282                                 return -EINVAL;
2283                         }
2284                 }
2285                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2286                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2287
2288                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2289                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2290                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2291                                 return -EINVAL;
2292                         }
2293                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2294                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2295                                conf->nb_queue_pools == ETH_32_POOLS)) {
2296                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2297                                                 " nb_queue_pools != %d and"
2298                                                 " nb_queue_pools != %d.",
2299                                                 ETH_16_POOLS, ETH_32_POOLS);
2300                                 return -EINVAL;
2301                         }
2302                 }
2303
2304                 /* For DCB mode check our configuration before we go further */
2305                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2306                         const struct rte_eth_dcb_rx_conf *conf;
2307
2308                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2309                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2310                                                  IXGBE_DCB_NB_QUEUES);
2311                                 return -EINVAL;
2312                         }
2313                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2314                         if (!(conf->nb_tcs == ETH_4_TCS ||
2315                                conf->nb_tcs == ETH_8_TCS)) {
2316                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2317                                                 " and nb_tcs != %d.",
2318                                                 ETH_4_TCS, ETH_8_TCS);
2319                                 return -EINVAL;
2320                         }
2321                 }
2322
2323                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2324                         const struct rte_eth_dcb_tx_conf *conf;
2325
2326                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2327                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2328                                                  IXGBE_DCB_NB_QUEUES);
2329                                 return -EINVAL;
2330                         }
2331                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2332                         if (!(conf->nb_tcs == ETH_4_TCS ||
2333                                conf->nb_tcs == ETH_8_TCS)) {
2334                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2335                                                 " and nb_tcs != %d.",
2336                                                 ETH_4_TCS, ETH_8_TCS);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340
2341                 /*
2342                  * When DCB/VT is off, maximum number of queues changes,
2343                  * except for 82598EB, which remains constant.
2344                  */
2345                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2346                                 hw->mac.type != ixgbe_mac_82598EB) {
2347                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2348                                 PMD_INIT_LOG(ERR,
2349                                              "Neither VT nor DCB are enabled, "
2350                                              "nb_tx_q > %d.",
2351                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2352                                 return -EINVAL;
2353                         }
2354                 }
2355         }
2356         return 0;
2357 }
2358
2359 static int
2360 ixgbe_dev_configure(struct rte_eth_dev *dev)
2361 {
2362         struct ixgbe_interrupt *intr =
2363                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2364         struct ixgbe_adapter *adapter =
2365                 (struct ixgbe_adapter *)dev->data->dev_private;
2366         struct rte_eth_dev_info dev_info;
2367         uint64_t rx_offloads;
2368         uint64_t tx_offloads;
2369         int ret;
2370
2371         PMD_INIT_FUNC_TRACE();
2372         /* multipe queue mode checking */
2373         ret  = ixgbe_check_mq_mode(dev);
2374         if (ret != 0) {
2375                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2376                             ret);
2377                 return ret;
2378         }
2379
2380         ixgbe_dev_info_get(dev, &dev_info);
2381         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2382         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2383                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2384                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2385                             rx_offloads, dev_info.rx_offload_capa);
2386                 return -ENOTSUP;
2387         }
2388         tx_offloads = dev->data->dev_conf.txmode.offloads;
2389         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2390                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2391                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2392                             tx_offloads, dev_info.tx_offload_capa);
2393                 return -ENOTSUP;
2394         }
2395
2396         /* set flag to update link status after init */
2397         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2398
2399         /*
2400          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2401          * allocation or vector Rx preconditions we will reset it.
2402          */
2403         adapter->rx_bulk_alloc_allowed = true;
2404         adapter->rx_vec_allowed = true;
2405
2406         return 0;
2407 }
2408
2409 static void
2410 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2411 {
2412         struct ixgbe_hw *hw =
2413                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2414         struct ixgbe_interrupt *intr =
2415                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2416         uint32_t gpie;
2417
2418         /* only set up it on X550EM_X */
2419         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2420                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2421                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2422                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2423                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2424                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2425         }
2426 }
2427
2428 int
2429 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2430                         uint16_t tx_rate, uint64_t q_msk)
2431 {
2432         struct ixgbe_hw *hw;
2433         struct ixgbe_vf_info *vfinfo;
2434         struct rte_eth_link link;
2435         uint8_t  nb_q_per_pool;
2436         uint32_t queue_stride;
2437         uint32_t queue_idx, idx = 0, vf_idx;
2438         uint32_t queue_end;
2439         uint16_t total_rate = 0;
2440         struct rte_pci_device *pci_dev;
2441
2442         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2443         rte_eth_link_get_nowait(dev->data->port_id, &link);
2444
2445         if (vf >= pci_dev->max_vfs)
2446                 return -EINVAL;
2447
2448         if (tx_rate > link.link_speed)
2449                 return -EINVAL;
2450
2451         if (q_msk == 0)
2452                 return 0;
2453
2454         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2455         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2456         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2457         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2458         queue_idx = vf * queue_stride;
2459         queue_end = queue_idx + nb_q_per_pool - 1;
2460         if (queue_end >= hw->mac.max_tx_queues)
2461                 return -EINVAL;
2462
2463         if (vfinfo) {
2464                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2465                         if (vf_idx == vf)
2466                                 continue;
2467                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2468                                 idx++)
2469                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2470                 }
2471         } else {
2472                 return -EINVAL;
2473         }
2474
2475         /* Store tx_rate for this vf. */
2476         for (idx = 0; idx < nb_q_per_pool; idx++) {
2477                 if (((uint64_t)0x1 << idx) & q_msk) {
2478                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2479                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2480                         total_rate += tx_rate;
2481                 }
2482         }
2483
2484         if (total_rate > dev->data->dev_link.link_speed) {
2485                 /* Reset stored TX rate of the VF if it causes exceed
2486                  * link speed.
2487                  */
2488                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2489                 return -EINVAL;
2490         }
2491
2492         /* Set RTTBCNRC of each queue/pool for vf X  */
2493         for (; queue_idx <= queue_end; queue_idx++) {
2494                 if (0x1 & q_msk)
2495                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2496                 q_msk = q_msk >> 1;
2497         }
2498
2499         return 0;
2500 }
2501
2502 /*
2503  * Configure device link speed and setup link.
2504  * It returns 0 on success.
2505  */
2506 static int
2507 ixgbe_dev_start(struct rte_eth_dev *dev)
2508 {
2509         struct ixgbe_hw *hw =
2510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2511         struct ixgbe_vf_info *vfinfo =
2512                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2513         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2514         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2515         uint32_t intr_vector = 0;
2516         int err, link_up = 0, negotiate = 0;
2517         uint32_t speed = 0;
2518         uint32_t allowed_speeds = 0;
2519         int mask = 0;
2520         int status;
2521         uint16_t vf, idx;
2522         uint32_t *link_speeds;
2523         struct ixgbe_tm_conf *tm_conf =
2524                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2525
2526         PMD_INIT_FUNC_TRACE();
2527
2528         /* IXGBE devices don't support:
2529         *    - half duplex (checked afterwards for valid speeds)
2530         *    - fixed speed: TODO implement
2531         */
2532         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2533                 PMD_INIT_LOG(ERR,
2534                 "Invalid link_speeds for port %u, fix speed not supported",
2535                                 dev->data->port_id);
2536                 return -EINVAL;
2537         }
2538
2539         /* disable uio/vfio intr/eventfd mapping */
2540         rte_intr_disable(intr_handle);
2541
2542         /* stop adapter */
2543         hw->adapter_stopped = 0;
2544         ixgbe_stop_adapter(hw);
2545
2546         /* reinitialize adapter
2547          * this calls reset and start
2548          */
2549         status = ixgbe_pf_reset_hw(hw);
2550         if (status != 0)
2551                 return -1;
2552         hw->mac.ops.start_hw(hw);
2553         hw->mac.get_link_status = true;
2554
2555         /* configure PF module if SRIOV enabled */
2556         ixgbe_pf_host_configure(dev);
2557
2558         ixgbe_dev_phy_intr_setup(dev);
2559
2560         /* check and configure queue intr-vector mapping */
2561         if ((rte_intr_cap_multiple(intr_handle) ||
2562              !RTE_ETH_DEV_SRIOV(dev).active) &&
2563             dev->data->dev_conf.intr_conf.rxq != 0) {
2564                 intr_vector = dev->data->nb_rx_queues;
2565                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2566                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2567                                         IXGBE_MAX_INTR_QUEUE_NUM);
2568                         return -ENOTSUP;
2569                 }
2570                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2571                         return -1;
2572         }
2573
2574         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2575                 intr_handle->intr_vec =
2576                         rte_zmalloc("intr_vec",
2577                                     dev->data->nb_rx_queues * sizeof(int), 0);
2578                 if (intr_handle->intr_vec == NULL) {
2579                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2580                                      " intr_vec", dev->data->nb_rx_queues);
2581                         return -ENOMEM;
2582                 }
2583         }
2584
2585         /* confiugre msix for sleep until rx interrupt */
2586         ixgbe_configure_msix(dev);
2587
2588         /* initialize transmission unit */
2589         ixgbe_dev_tx_init(dev);
2590
2591         /* This can fail when allocating mbufs for descriptor rings */
2592         err = ixgbe_dev_rx_init(dev);
2593         if (err) {
2594                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2595                 goto error;
2596         }
2597
2598         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2599                 ETH_VLAN_EXTEND_MASK;
2600         err = ixgbe_vlan_offload_set(dev, mask);
2601         if (err) {
2602                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2603                 goto error;
2604         }
2605
2606         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2607                 /* Enable vlan filtering for VMDq */
2608                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2609         }
2610
2611         /* Configure DCB hw */
2612         ixgbe_configure_dcb(dev);
2613
2614         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2615                 err = ixgbe_fdir_configure(dev);
2616                 if (err)
2617                         goto error;
2618         }
2619
2620         /* Restore vf rate limit */
2621         if (vfinfo != NULL) {
2622                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2623                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2624                                 if (vfinfo[vf].tx_rate[idx] != 0)
2625                                         ixgbe_set_vf_rate_limit(
2626                                                 dev, vf,
2627                                                 vfinfo[vf].tx_rate[idx],
2628                                                 1 << idx);
2629         }
2630
2631         ixgbe_restore_statistics_mapping(dev);
2632
2633         err = ixgbe_dev_rxtx_start(dev);
2634         if (err < 0) {
2635                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2636                 goto error;
2637         }
2638
2639         /* Skip link setup if loopback mode is enabled for 82599. */
2640         if (hw->mac.type == ixgbe_mac_82599EB &&
2641                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2642                 goto skip_link_setup;
2643
2644         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2645                 err = hw->mac.ops.setup_sfp(hw);
2646                 if (err)
2647                         goto error;
2648         }
2649
2650         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2651                 /* Turn on the copper */
2652                 ixgbe_set_phy_power(hw, true);
2653         } else {
2654                 /* Turn on the laser */
2655                 ixgbe_enable_tx_laser(hw);
2656         }
2657
2658         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2659         if (err)
2660                 goto error;
2661         dev->data->dev_link.link_status = link_up;
2662
2663         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2664         if (err)
2665                 goto error;
2666
2667         switch (hw->mac.type) {
2668         case ixgbe_mac_X550:
2669         case ixgbe_mac_X550EM_x:
2670         case ixgbe_mac_X550EM_a:
2671                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2672                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2673                         ETH_LINK_SPEED_10G;
2674                 break;
2675         default:
2676                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2677                         ETH_LINK_SPEED_10G;
2678         }
2679
2680         link_speeds = &dev->data->dev_conf.link_speeds;
2681         if (*link_speeds & ~allowed_speeds) {
2682                 PMD_INIT_LOG(ERR, "Invalid link setting");
2683                 goto error;
2684         }
2685
2686         speed = 0x0;
2687         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2688                 switch (hw->mac.type) {
2689                 case ixgbe_mac_82598EB:
2690                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2691                         break;
2692                 case ixgbe_mac_82599EB:
2693                 case ixgbe_mac_X540:
2694                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2695                         break;
2696                 case ixgbe_mac_X550:
2697                 case ixgbe_mac_X550EM_x:
2698                 case ixgbe_mac_X550EM_a:
2699                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2700                         break;
2701                 default:
2702                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2703                 }
2704         } else {
2705                 if (*link_speeds & ETH_LINK_SPEED_10G)
2706                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2707                 if (*link_speeds & ETH_LINK_SPEED_5G)
2708                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2709                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2710                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2711                 if (*link_speeds & ETH_LINK_SPEED_1G)
2712                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2713                 if (*link_speeds & ETH_LINK_SPEED_100M)
2714                         speed |= IXGBE_LINK_SPEED_100_FULL;
2715         }
2716
2717         err = ixgbe_setup_link(hw, speed, link_up);
2718         if (err)
2719                 goto error;
2720
2721         ixgbe_dev_link_update(dev, 0);
2722
2723 skip_link_setup:
2724
2725         if (rte_intr_allow_others(intr_handle)) {
2726                 /* check if lsc interrupt is enabled */
2727                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2728                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2729                 else
2730                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2731                 ixgbe_dev_macsec_interrupt_setup(dev);
2732         } else {
2733                 rte_intr_callback_unregister(intr_handle,
2734                                              ixgbe_dev_interrupt_handler, dev);
2735                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2736                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2737                                      " no intr multiplex");
2738         }
2739
2740         /* check if rxq interrupt is enabled */
2741         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2742             rte_intr_dp_is_en(intr_handle))
2743                 ixgbe_dev_rxq_interrupt_setup(dev);
2744
2745         /* enable uio/vfio intr/eventfd mapping */
2746         rte_intr_enable(intr_handle);
2747
2748         /* resume enabled intr since hw reset */
2749         ixgbe_enable_intr(dev);
2750         ixgbe_l2_tunnel_conf(dev);
2751         ixgbe_filter_restore(dev);
2752
2753         if (tm_conf->root && !tm_conf->committed)
2754                 PMD_DRV_LOG(WARNING,
2755                             "please call hierarchy_commit() "
2756                             "before starting the port");
2757
2758         return 0;
2759
2760 error:
2761         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2762         ixgbe_dev_clear_queues(dev);
2763         return -EIO;
2764 }
2765
2766 /*
2767  * Stop device: disable rx and tx functions to allow for reconfiguring.
2768  */
2769 static void
2770 ixgbe_dev_stop(struct rte_eth_dev *dev)
2771 {
2772         struct rte_eth_link link;
2773         struct ixgbe_hw *hw =
2774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2775         struct ixgbe_vf_info *vfinfo =
2776                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2777         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2778         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2779         int vf;
2780         struct ixgbe_tm_conf *tm_conf =
2781                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2782
2783         PMD_INIT_FUNC_TRACE();
2784
2785         /* disable interrupts */
2786         ixgbe_disable_intr(hw);
2787
2788         /* reset the NIC */
2789         ixgbe_pf_reset_hw(hw);
2790         hw->adapter_stopped = 0;
2791
2792         /* stop adapter */
2793         ixgbe_stop_adapter(hw);
2794
2795         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2796                 vfinfo[vf].clear_to_send = false;
2797
2798         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2799                 /* Turn off the copper */
2800                 ixgbe_set_phy_power(hw, false);
2801         } else {
2802                 /* Turn off the laser */
2803                 ixgbe_disable_tx_laser(hw);
2804         }
2805
2806         ixgbe_dev_clear_queues(dev);
2807
2808         /* Clear stored conf */
2809         dev->data->scattered_rx = 0;
2810         dev->data->lro = 0;
2811
2812         /* Clear recorded link status */
2813         memset(&link, 0, sizeof(link));
2814         rte_eth_linkstatus_set(dev, &link);
2815
2816         if (!rte_intr_allow_others(intr_handle))
2817                 /* resume to the default handler */
2818                 rte_intr_callback_register(intr_handle,
2819                                            ixgbe_dev_interrupt_handler,
2820                                            (void *)dev);
2821
2822         /* Clean datapath event and queue/vec mapping */
2823         rte_intr_efd_disable(intr_handle);
2824         if (intr_handle->intr_vec != NULL) {
2825                 rte_free(intr_handle->intr_vec);
2826                 intr_handle->intr_vec = NULL;
2827         }
2828
2829         /* reset hierarchy commit */
2830         tm_conf->committed = false;
2831 }
2832
2833 /*
2834  * Set device link up: enable tx.
2835  */
2836 static int
2837 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2838 {
2839         struct ixgbe_hw *hw =
2840                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841         if (hw->mac.type == ixgbe_mac_82599EB) {
2842 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2843                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2844                         /* Not suported in bypass mode */
2845                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2846                                      "by device id 0x%x", hw->device_id);
2847                         return -ENOTSUP;
2848                 }
2849 #endif
2850         }
2851
2852         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2853                 /* Turn on the copper */
2854                 ixgbe_set_phy_power(hw, true);
2855         } else {
2856                 /* Turn on the laser */
2857                 ixgbe_enable_tx_laser(hw);
2858         }
2859
2860         return 0;
2861 }
2862
2863 /*
2864  * Set device link down: disable tx.
2865  */
2866 static int
2867 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2868 {
2869         struct ixgbe_hw *hw =
2870                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         if (hw->mac.type == ixgbe_mac_82599EB) {
2872 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2873                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2874                         /* Not suported in bypass mode */
2875                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2876                                      "by device id 0x%x", hw->device_id);
2877                         return -ENOTSUP;
2878                 }
2879 #endif
2880         }
2881
2882         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2883                 /* Turn off the copper */
2884                 ixgbe_set_phy_power(hw, false);
2885         } else {
2886                 /* Turn off the laser */
2887                 ixgbe_disable_tx_laser(hw);
2888         }
2889
2890         return 0;
2891 }
2892
2893 /*
2894  * Reset and stop device.
2895  */
2896 static void
2897 ixgbe_dev_close(struct rte_eth_dev *dev)
2898 {
2899         struct ixgbe_hw *hw =
2900                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901
2902         PMD_INIT_FUNC_TRACE();
2903
2904         ixgbe_pf_reset_hw(hw);
2905
2906         ixgbe_dev_stop(dev);
2907         hw->adapter_stopped = 1;
2908
2909         ixgbe_dev_free_queues(dev);
2910
2911         ixgbe_disable_pcie_master(hw);
2912
2913         /* reprogram the RAR[0] in case user changed it. */
2914         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2915 }
2916
2917 /*
2918  * Reset PF device.
2919  */
2920 static int
2921 ixgbe_dev_reset(struct rte_eth_dev *dev)
2922 {
2923         int ret;
2924
2925         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2926          * its VF to make them align with it. The detailed notification
2927          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2928          * To avoid unexpected behavior in VF, currently reset of PF with
2929          * SR-IOV activation is not supported. It might be supported later.
2930          */
2931         if (dev->data->sriov.active)
2932                 return -ENOTSUP;
2933
2934         ret = eth_ixgbe_dev_uninit(dev);
2935         if (ret)
2936                 return ret;
2937
2938         ret = eth_ixgbe_dev_init(dev, NULL);
2939
2940         return ret;
2941 }
2942
2943 static void
2944 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2945                            struct ixgbe_hw_stats *hw_stats,
2946                            struct ixgbe_macsec_stats *macsec_stats,
2947                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2948                            uint64_t *total_qprc, uint64_t *total_qprdc)
2949 {
2950         uint32_t bprc, lxon, lxoff, total;
2951         uint32_t delta_gprc = 0;
2952         unsigned i;
2953         /* Workaround for RX byte count not including CRC bytes when CRC
2954          * strip is enabled. CRC bytes are removed from counters when crc_strip
2955          * is disabled.
2956          */
2957         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2958                         IXGBE_HLREG0_RXCRCSTRP);
2959
2960         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2961         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2962         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2963         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2964
2965         for (i = 0; i < 8; i++) {
2966                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2967
2968                 /* global total per queue */
2969                 hw_stats->mpc[i] += mp;
2970                 /* Running comprehensive total for stats display */
2971                 *total_missed_rx += hw_stats->mpc[i];
2972                 if (hw->mac.type == ixgbe_mac_82598EB) {
2973                         hw_stats->rnbc[i] +=
2974                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2975                         hw_stats->pxonrxc[i] +=
2976                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2977                         hw_stats->pxoffrxc[i] +=
2978                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2979                 } else {
2980                         hw_stats->pxonrxc[i] +=
2981                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2982                         hw_stats->pxoffrxc[i] +=
2983                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2984                         hw_stats->pxon2offc[i] +=
2985                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2986                 }
2987                 hw_stats->pxontxc[i] +=
2988                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2989                 hw_stats->pxofftxc[i] +=
2990                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2991         }
2992         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2993                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2994                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2995                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2996
2997                 delta_gprc += delta_qprc;
2998
2999                 hw_stats->qprc[i] += delta_qprc;
3000                 hw_stats->qptc[i] += delta_qptc;
3001
3002                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3003                 hw_stats->qbrc[i] +=
3004                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3005                 if (crc_strip == 0)
3006                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3007
3008                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3009                 hw_stats->qbtc[i] +=
3010                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3011
3012                 hw_stats->qprdc[i] += delta_qprdc;
3013                 *total_qprdc += hw_stats->qprdc[i];
3014
3015                 *total_qprc += hw_stats->qprc[i];
3016                 *total_qbrc += hw_stats->qbrc[i];
3017         }
3018         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3019         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3020         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3021
3022         /*
3023          * An errata states that gprc actually counts good + missed packets:
3024          * Workaround to set gprc to summated queue packet receives
3025          */
3026         hw_stats->gprc = *total_qprc;
3027
3028         if (hw->mac.type != ixgbe_mac_82598EB) {
3029                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3030                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3031                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3032                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3033                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3034                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3035                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3036                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3037         } else {
3038                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3039                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3040                 /* 82598 only has a counter in the high register */
3041                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3042                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3043                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3044         }
3045         uint64_t old_tpr = hw_stats->tpr;
3046
3047         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3048         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3049
3050         if (crc_strip == 0)
3051                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3052
3053         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3054         hw_stats->gptc += delta_gptc;
3055         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3056         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3057
3058         /*
3059          * Workaround: mprc hardware is incorrectly counting
3060          * broadcasts, so for now we subtract those.
3061          */
3062         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3063         hw_stats->bprc += bprc;
3064         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3065         if (hw->mac.type == ixgbe_mac_82598EB)
3066                 hw_stats->mprc -= bprc;
3067
3068         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3069         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3070         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3071         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3072         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3073         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3074
3075         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3076         hw_stats->lxontxc += lxon;
3077         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3078         hw_stats->lxofftxc += lxoff;
3079         total = lxon + lxoff;
3080
3081         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3082         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3083         hw_stats->gptc -= total;
3084         hw_stats->mptc -= total;
3085         hw_stats->ptc64 -= total;
3086         hw_stats->gotc -= total * ETHER_MIN_LEN;
3087
3088         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3089         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3090         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3091         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3092         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3093         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3094         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3095         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3096         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3097         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3098         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3099         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3100         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3101         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3102         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3103         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3104         /* Only read FCOE on 82599 */
3105         if (hw->mac.type != ixgbe_mac_82598EB) {
3106                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3107                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3108                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3109                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3110                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3111         }
3112
3113         /* Flow Director Stats registers */
3114         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3115         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3116
3117         /* MACsec Stats registers */
3118         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3119         macsec_stats->out_pkts_encrypted +=
3120                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3121         macsec_stats->out_pkts_protected +=
3122                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3123         macsec_stats->out_octets_encrypted +=
3124                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3125         macsec_stats->out_octets_protected +=
3126                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3127         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3128         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3129         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3130         macsec_stats->in_pkts_unknownsci +=
3131                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3132         macsec_stats->in_octets_decrypted +=
3133                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3134         macsec_stats->in_octets_validated +=
3135                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3136         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3137         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3138         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3139         for (i = 0; i < 2; i++) {
3140                 macsec_stats->in_pkts_ok +=
3141                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3142                 macsec_stats->in_pkts_invalid +=
3143                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3144                 macsec_stats->in_pkts_notvalid +=
3145                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3146         }
3147         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3148         macsec_stats->in_pkts_notusingsa +=
3149                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3150 }
3151
3152 /*
3153  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3154  */
3155 static int
3156 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3157 {
3158         struct ixgbe_hw *hw =
3159                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3160         struct ixgbe_hw_stats *hw_stats =
3161                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3162         struct ixgbe_macsec_stats *macsec_stats =
3163                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3164                                 dev->data->dev_private);
3165         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3166         unsigned i;
3167
3168         total_missed_rx = 0;
3169         total_qbrc = 0;
3170         total_qprc = 0;
3171         total_qprdc = 0;
3172
3173         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3174                         &total_qbrc, &total_qprc, &total_qprdc);
3175
3176         if (stats == NULL)
3177                 return -EINVAL;
3178
3179         /* Fill out the rte_eth_stats statistics structure */
3180         stats->ipackets = total_qprc;
3181         stats->ibytes = total_qbrc;
3182         stats->opackets = hw_stats->gptc;
3183         stats->obytes = hw_stats->gotc;
3184
3185         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3186                 stats->q_ipackets[i] = hw_stats->qprc[i];
3187                 stats->q_opackets[i] = hw_stats->qptc[i];
3188                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3189                 stats->q_obytes[i] = hw_stats->qbtc[i];
3190                 stats->q_errors[i] = hw_stats->qprdc[i];
3191         }
3192
3193         /* Rx Errors */
3194         stats->imissed  = total_missed_rx;
3195         stats->ierrors  = hw_stats->crcerrs +
3196                           hw_stats->mspdc +
3197                           hw_stats->rlec +
3198                           hw_stats->ruc +
3199                           hw_stats->roc +
3200                           hw_stats->illerrc +
3201                           hw_stats->errbc +
3202                           hw_stats->rfc +
3203                           hw_stats->fccrc +
3204                           hw_stats->fclast;
3205
3206         /* Tx Errors */
3207         stats->oerrors  = 0;
3208         return 0;
3209 }
3210
3211 static void
3212 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3213 {
3214         struct ixgbe_hw_stats *stats =
3215                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3216
3217         /* HW registers are cleared on read */
3218         ixgbe_dev_stats_get(dev, NULL);
3219
3220         /* Reset software totals */
3221         memset(stats, 0, sizeof(*stats));
3222 }
3223
3224 /* This function calculates the number of xstats based on the current config */
3225 static unsigned
3226 ixgbe_xstats_calc_num(void) {
3227         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3228                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3229                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3230 }
3231
3232 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3233         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3234 {
3235         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3236         unsigned stat, i, count;
3237
3238         if (xstats_names != NULL) {
3239                 count = 0;
3240
3241                 /* Note: limit >= cnt_stats checked upstream
3242                  * in rte_eth_xstats_names()
3243                  */
3244
3245                 /* Extended stats from ixgbe_hw_stats */
3246                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3247                         snprintf(xstats_names[count].name,
3248                                 sizeof(xstats_names[count].name),
3249                                 "%s",
3250                                 rte_ixgbe_stats_strings[i].name);
3251                         count++;
3252                 }
3253
3254                 /* MACsec Stats */
3255                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3256                         snprintf(xstats_names[count].name,
3257                                 sizeof(xstats_names[count].name),
3258                                 "%s",
3259                                 rte_ixgbe_macsec_strings[i].name);
3260                         count++;
3261                 }
3262
3263                 /* RX Priority Stats */
3264                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3265                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3266                                 snprintf(xstats_names[count].name,
3267                                         sizeof(xstats_names[count].name),
3268                                         "rx_priority%u_%s", i,
3269                                         rte_ixgbe_rxq_strings[stat].name);
3270                                 count++;
3271                         }
3272                 }
3273
3274                 /* TX Priority Stats */
3275                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3276                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3277                                 snprintf(xstats_names[count].name,
3278                                         sizeof(xstats_names[count].name),
3279                                         "tx_priority%u_%s", i,
3280                                         rte_ixgbe_txq_strings[stat].name);
3281                                 count++;
3282                         }
3283                 }
3284         }
3285         return cnt_stats;
3286 }
3287
3288 static int ixgbe_dev_xstats_get_names_by_id(
3289         struct rte_eth_dev *dev,
3290         struct rte_eth_xstat_name *xstats_names,
3291         const uint64_t *ids,
3292         unsigned int limit)
3293 {
3294         if (!ids) {
3295                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3296                 unsigned int stat, i, count;
3297
3298                 if (xstats_names != NULL) {
3299                         count = 0;
3300
3301                         /* Note: limit >= cnt_stats checked upstream
3302                          * in rte_eth_xstats_names()
3303                          */
3304
3305                         /* Extended stats from ixgbe_hw_stats */
3306                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3307                                 snprintf(xstats_names[count].name,
3308                                         sizeof(xstats_names[count].name),
3309                                         "%s",
3310                                         rte_ixgbe_stats_strings[i].name);
3311                                 count++;
3312                         }
3313
3314                         /* MACsec Stats */
3315                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3316                                 snprintf(xstats_names[count].name,
3317                                         sizeof(xstats_names[count].name),
3318                                         "%s",
3319                                         rte_ixgbe_macsec_strings[i].name);
3320                                 count++;
3321                         }
3322
3323                         /* RX Priority Stats */
3324                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3325                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3326                                         snprintf(xstats_names[count].name,
3327                                             sizeof(xstats_names[count].name),
3328                                             "rx_priority%u_%s", i,
3329                                             rte_ixgbe_rxq_strings[stat].name);
3330                                         count++;
3331                                 }
3332                         }
3333
3334                         /* TX Priority Stats */
3335                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3336                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3337                                         snprintf(xstats_names[count].name,
3338                                             sizeof(xstats_names[count].name),
3339                                             "tx_priority%u_%s", i,
3340                                             rte_ixgbe_txq_strings[stat].name);
3341                                         count++;
3342                                 }
3343                         }
3344                 }
3345                 return cnt_stats;
3346         }
3347
3348         uint16_t i;
3349         uint16_t size = ixgbe_xstats_calc_num();
3350         struct rte_eth_xstat_name xstats_names_copy[size];
3351
3352         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3353                         size);
3354
3355         for (i = 0; i < limit; i++) {
3356                 if (ids[i] >= size) {
3357                         PMD_INIT_LOG(ERR, "id value isn't valid");
3358                         return -1;
3359                 }
3360                 strcpy(xstats_names[i].name,
3361                                 xstats_names_copy[ids[i]].name);
3362         }
3363         return limit;
3364 }
3365
3366 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3367         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3368 {
3369         unsigned i;
3370
3371         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3372                 return -ENOMEM;
3373
3374         if (xstats_names != NULL)
3375                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3376                         snprintf(xstats_names[i].name,
3377                                 sizeof(xstats_names[i].name),
3378                                 "%s", rte_ixgbevf_stats_strings[i].name);
3379         return IXGBEVF_NB_XSTATS;
3380 }
3381
3382 static int
3383 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3384                                          unsigned n)
3385 {
3386         struct ixgbe_hw *hw =
3387                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3388         struct ixgbe_hw_stats *hw_stats =
3389                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3390         struct ixgbe_macsec_stats *macsec_stats =
3391                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3392                                 dev->data->dev_private);
3393         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3394         unsigned i, stat, count = 0;
3395
3396         count = ixgbe_xstats_calc_num();
3397
3398         if (n < count)
3399                 return count;
3400
3401         total_missed_rx = 0;
3402         total_qbrc = 0;
3403         total_qprc = 0;
3404         total_qprdc = 0;
3405
3406         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3407                         &total_qbrc, &total_qprc, &total_qprdc);
3408
3409         /* If this is a reset xstats is NULL, and we have cleared the
3410          * registers by reading them.
3411          */
3412         if (!xstats)
3413                 return 0;
3414
3415         /* Extended stats from ixgbe_hw_stats */
3416         count = 0;
3417         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3418                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3419                                 rte_ixgbe_stats_strings[i].offset);
3420                 xstats[count].id = count;
3421                 count++;
3422         }
3423
3424         /* MACsec Stats */
3425         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3426                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3427                                 rte_ixgbe_macsec_strings[i].offset);
3428                 xstats[count].id = count;
3429                 count++;
3430         }
3431
3432         /* RX Priority Stats */
3433         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3434                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3435                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3436                                         rte_ixgbe_rxq_strings[stat].offset +
3437                                         (sizeof(uint64_t) * i));
3438                         xstats[count].id = count;
3439                         count++;
3440                 }
3441         }
3442
3443         /* TX Priority Stats */
3444         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3445                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3446                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3447                                         rte_ixgbe_txq_strings[stat].offset +
3448                                         (sizeof(uint64_t) * i));
3449                         xstats[count].id = count;
3450                         count++;
3451                 }
3452         }
3453         return count;
3454 }
3455
3456 static int
3457 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3458                 uint64_t *values, unsigned int n)
3459 {
3460         if (!ids) {
3461                 struct ixgbe_hw *hw =
3462                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3463                 struct ixgbe_hw_stats *hw_stats =
3464                                 IXGBE_DEV_PRIVATE_TO_STATS(
3465                                                 dev->data->dev_private);
3466                 struct ixgbe_macsec_stats *macsec_stats =
3467                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3468                                         dev->data->dev_private);
3469                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3470                 unsigned int i, stat, count = 0;
3471
3472                 count = ixgbe_xstats_calc_num();
3473
3474                 if (!ids && n < count)
3475                         return count;
3476
3477                 total_missed_rx = 0;
3478                 total_qbrc = 0;
3479                 total_qprc = 0;
3480                 total_qprdc = 0;
3481
3482                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3483                                 &total_missed_rx, &total_qbrc, &total_qprc,
3484                                 &total_qprdc);
3485
3486                 /* If this is a reset xstats is NULL, and we have cleared the
3487                  * registers by reading them.
3488                  */
3489                 if (!ids && !values)
3490                         return 0;
3491
3492                 /* Extended stats from ixgbe_hw_stats */
3493                 count = 0;
3494                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3495                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3496                                         rte_ixgbe_stats_strings[i].offset);
3497                         count++;
3498                 }
3499
3500                 /* MACsec Stats */
3501                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3502                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3503                                         rte_ixgbe_macsec_strings[i].offset);
3504                         count++;
3505                 }
3506
3507                 /* RX Priority Stats */
3508                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3509                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3510                                 values[count] =
3511                                         *(uint64_t *)(((char *)hw_stats) +
3512                                         rte_ixgbe_rxq_strings[stat].offset +
3513                                         (sizeof(uint64_t) * i));
3514                                 count++;
3515                         }
3516                 }
3517
3518                 /* TX Priority Stats */
3519                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3520                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3521                                 values[count] =
3522                                         *(uint64_t *)(((char *)hw_stats) +
3523                                         rte_ixgbe_txq_strings[stat].offset +
3524                                         (sizeof(uint64_t) * i));
3525                                 count++;
3526                         }
3527                 }
3528                 return count;
3529         }
3530
3531         uint16_t i;
3532         uint16_t size = ixgbe_xstats_calc_num();
3533         uint64_t values_copy[size];
3534
3535         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3536
3537         for (i = 0; i < n; i++) {
3538                 if (ids[i] >= size) {
3539                         PMD_INIT_LOG(ERR, "id value isn't valid");
3540                         return -1;
3541                 }
3542                 values[i] = values_copy[ids[i]];
3543         }
3544         return n;
3545 }
3546
3547 static void
3548 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3549 {
3550         struct ixgbe_hw_stats *stats =
3551                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3552         struct ixgbe_macsec_stats *macsec_stats =
3553                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3554                                 dev->data->dev_private);
3555
3556         unsigned count = ixgbe_xstats_calc_num();
3557
3558         /* HW registers are cleared on read */
3559         ixgbe_dev_xstats_get(dev, NULL, count);
3560
3561         /* Reset software totals */
3562         memset(stats, 0, sizeof(*stats));
3563         memset(macsec_stats, 0, sizeof(*macsec_stats));
3564 }
3565
3566 static void
3567 ixgbevf_update_stats(struct rte_eth_dev *dev)
3568 {
3569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3571                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3572
3573         /* Good Rx packet, include VF loopback */
3574         UPDATE_VF_STAT(IXGBE_VFGPRC,
3575             hw_stats->last_vfgprc, hw_stats->vfgprc);
3576
3577         /* Good Rx octets, include VF loopback */
3578         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3579             hw_stats->last_vfgorc, hw_stats->vfgorc);
3580
3581         /* Good Tx packet, include VF loopback */
3582         UPDATE_VF_STAT(IXGBE_VFGPTC,
3583             hw_stats->last_vfgptc, hw_stats->vfgptc);
3584
3585         /* Good Tx octets, include VF loopback */
3586         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3587             hw_stats->last_vfgotc, hw_stats->vfgotc);
3588
3589         /* Rx Multicst Packet */
3590         UPDATE_VF_STAT(IXGBE_VFMPRC,
3591             hw_stats->last_vfmprc, hw_stats->vfmprc);
3592 }
3593
3594 static int
3595 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3596                        unsigned n)
3597 {
3598         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3599                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3600         unsigned i;
3601
3602         if (n < IXGBEVF_NB_XSTATS)
3603                 return IXGBEVF_NB_XSTATS;
3604
3605         ixgbevf_update_stats(dev);
3606
3607         if (!xstats)
3608                 return 0;
3609
3610         /* Extended stats */
3611         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3612                 xstats[i].id = i;
3613                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3614                         rte_ixgbevf_stats_strings[i].offset);
3615         }
3616
3617         return IXGBEVF_NB_XSTATS;
3618 }
3619
3620 static int
3621 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3622 {
3623         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3624                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3625
3626         ixgbevf_update_stats(dev);
3627
3628         if (stats == NULL)
3629                 return -EINVAL;
3630
3631         stats->ipackets = hw_stats->vfgprc;
3632         stats->ibytes = hw_stats->vfgorc;
3633         stats->opackets = hw_stats->vfgptc;
3634         stats->obytes = hw_stats->vfgotc;
3635         return 0;
3636 }
3637
3638 static void
3639 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3640 {
3641         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3642                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3643
3644         /* Sync HW register to the last stats */
3645         ixgbevf_dev_stats_get(dev, NULL);
3646
3647         /* reset HW current stats*/
3648         hw_stats->vfgprc = 0;
3649         hw_stats->vfgorc = 0;
3650         hw_stats->vfgptc = 0;
3651         hw_stats->vfgotc = 0;
3652 }
3653
3654 static int
3655 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3656 {
3657         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         u16 eeprom_verh, eeprom_verl;
3659         u32 etrack_id;
3660         int ret;
3661
3662         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3663         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3664
3665         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3666         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3667
3668         ret += 1; /* add the size of '\0' */
3669         if (fw_size < (u32)ret)
3670                 return ret;
3671         else
3672                 return 0;
3673 }
3674
3675 static void
3676 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3677 {
3678         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3679         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3680         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3681
3682         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3683         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3684         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3685                 /*
3686                  * When DCB/VT is off, maximum number of queues changes,
3687                  * except for 82598EB, which remains constant.
3688                  */
3689                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3690                                 hw->mac.type != ixgbe_mac_82598EB)
3691                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3692         }
3693         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3694         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3695         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3696         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3697         dev_info->max_vfs = pci_dev->max_vfs;
3698         if (hw->mac.type == ixgbe_mac_82598EB)
3699                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3700         else
3701                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3702         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3703         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3704         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3705                                      dev_info->rx_queue_offload_capa);
3706         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3707         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3708
3709         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3710                 .rx_thresh = {
3711                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3712                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3713                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3714                 },
3715                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3716                 .rx_drop_en = 0,
3717                 .offloads = 0,
3718         };
3719
3720         dev_info->default_txconf = (struct rte_eth_txconf) {
3721                 .tx_thresh = {
3722                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3723                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3724                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3725                 },
3726                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3727                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3728                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3729                              ETH_TXQ_FLAGS_NOOFFLOADS |
3730                              ETH_TXQ_FLAGS_IGNORE,
3731                 .offloads = 0,
3732         };
3733
3734         dev_info->rx_desc_lim = rx_desc_lim;
3735         dev_info->tx_desc_lim = tx_desc_lim;
3736
3737         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3738         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3739         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3740
3741         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3742         if (hw->mac.type == ixgbe_mac_X540 ||
3743             hw->mac.type == ixgbe_mac_X540_vf ||
3744             hw->mac.type == ixgbe_mac_X550 ||
3745             hw->mac.type == ixgbe_mac_X550_vf) {
3746                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3747         }
3748         if (hw->mac.type == ixgbe_mac_X550) {
3749                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3750                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3751         }
3752 }
3753
3754 static const uint32_t *
3755 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3756 {
3757         static const uint32_t ptypes[] = {
3758                 /* For non-vec functions,
3759                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3760                  * for vec functions,
3761                  * refers to _recv_raw_pkts_vec().
3762                  */
3763                 RTE_PTYPE_L2_ETHER,
3764                 RTE_PTYPE_L3_IPV4,
3765                 RTE_PTYPE_L3_IPV4_EXT,
3766                 RTE_PTYPE_L3_IPV6,
3767                 RTE_PTYPE_L3_IPV6_EXT,
3768                 RTE_PTYPE_L4_SCTP,
3769                 RTE_PTYPE_L4_TCP,
3770                 RTE_PTYPE_L4_UDP,
3771                 RTE_PTYPE_TUNNEL_IP,
3772                 RTE_PTYPE_INNER_L3_IPV6,
3773                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3774                 RTE_PTYPE_INNER_L4_TCP,
3775                 RTE_PTYPE_INNER_L4_UDP,
3776                 RTE_PTYPE_UNKNOWN
3777         };
3778
3779         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3780             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3781             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3782             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3783                 return ptypes;
3784
3785 #if defined(RTE_ARCH_X86)
3786         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3787             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3788                 return ptypes;
3789 #endif
3790         return NULL;
3791 }
3792
3793 static void
3794 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3795                      struct rte_eth_dev_info *dev_info)
3796 {
3797         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799
3800         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3801         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3802         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3803         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3804         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3805         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3806         dev_info->max_vfs = pci_dev->max_vfs;
3807         if (hw->mac.type == ixgbe_mac_82598EB)
3808                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3809         else
3810                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3811         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3812         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3813                                      dev_info->rx_queue_offload_capa);
3814         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3815         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3816
3817         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3818                 .rx_thresh = {
3819                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3820                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3821                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3822                 },
3823                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3824                 .rx_drop_en = 0,
3825                 .offloads = 0,
3826         };
3827
3828         dev_info->default_txconf = (struct rte_eth_txconf) {
3829                 .tx_thresh = {
3830                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3831                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3832                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3833                 },
3834                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3835                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3836                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3837                              ETH_TXQ_FLAGS_NOOFFLOADS |
3838                              ETH_TXQ_FLAGS_IGNORE,
3839                 .offloads = 0,
3840         };
3841
3842         dev_info->rx_desc_lim = rx_desc_lim;
3843         dev_info->tx_desc_lim = tx_desc_lim;
3844 }
3845
3846 static int
3847 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3848                    int *link_up, int wait_to_complete)
3849 {
3850         /**
3851          * for a quick link status checking, wait_to_compelet == 0,
3852          * skip PF link status checking
3853          */
3854         bool no_pflink_check = wait_to_complete == 0;
3855         struct ixgbe_mbx_info *mbx = &hw->mbx;
3856         struct ixgbe_mac_info *mac = &hw->mac;
3857         uint32_t links_reg, in_msg;
3858         int ret_val = 0;
3859
3860         /* If we were hit with a reset drop the link */
3861         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3862                 mac->get_link_status = true;
3863
3864         if (!mac->get_link_status)
3865                 goto out;
3866
3867         /* if link status is down no point in checking to see if pf is up */
3868         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3869         if (!(links_reg & IXGBE_LINKS_UP))
3870                 goto out;
3871
3872         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3873          * before the link status is correct
3874          */
3875         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3876                 int i;
3877
3878                 for (i = 0; i < 5; i++) {
3879                         rte_delay_us(100);
3880                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3881
3882                         if (!(links_reg & IXGBE_LINKS_UP))
3883                                 goto out;
3884                 }
3885         }
3886
3887         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3888         case IXGBE_LINKS_SPEED_10G_82599:
3889                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3890                 if (hw->mac.type >= ixgbe_mac_X550) {
3891                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3892                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3893                 }
3894                 break;
3895         case IXGBE_LINKS_SPEED_1G_82599:
3896                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3897                 break;
3898         case IXGBE_LINKS_SPEED_100_82599:
3899                 *speed = IXGBE_LINK_SPEED_100_FULL;
3900                 if (hw->mac.type == ixgbe_mac_X550) {
3901                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3902                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3903                 }
3904                 break;
3905         case IXGBE_LINKS_SPEED_10_X550EM_A:
3906                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3907                 /* Since Reserved in older MAC's */
3908                 if (hw->mac.type >= ixgbe_mac_X550)
3909                         *speed = IXGBE_LINK_SPEED_10_FULL;
3910                 break;
3911         default:
3912                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3913         }
3914
3915         if (no_pflink_check) {
3916                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3917                         mac->get_link_status = true;
3918                 else
3919                         mac->get_link_status = false;
3920
3921                 goto out;
3922         }
3923         /* if the read failed it could just be a mailbox collision, best wait
3924          * until we are called again and don't report an error
3925          */
3926         if (mbx->ops.read(hw, &in_msg, 1, 0))
3927                 goto out;
3928
3929         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3930                 /* msg is not CTS and is NACK we must have lost CTS status */
3931                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3932                         ret_val = -1;
3933                 goto out;
3934         }
3935
3936         /* the pf is talking, if we timed out in the past we reinit */
3937         if (!mbx->timeout) {
3938                 ret_val = -1;
3939                 goto out;
3940         }
3941
3942         /* if we passed all the tests above then the link is up and we no
3943          * longer need to check for link
3944          */
3945         mac->get_link_status = false;
3946
3947 out:
3948         *link_up = !mac->get_link_status;
3949         return ret_val;
3950 }
3951
3952 /* return 0 means link status changed, -1 means not changed */
3953 int
3954 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3955                             int wait_to_complete, int vf)
3956 {
3957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3958         struct rte_eth_link link;
3959         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3960         struct ixgbe_interrupt *intr =
3961                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3962         int link_up;
3963         int diag;
3964         u32 speed = 0;
3965         int wait = 1;
3966         bool autoneg = false;
3967
3968         memset(&link, 0, sizeof(link));
3969         link.link_status = ETH_LINK_DOWN;
3970         link.link_speed = ETH_SPEED_NUM_NONE;
3971         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3972         link.link_autoneg = ETH_LINK_AUTONEG;
3973
3974         hw->mac.get_link_status = true;
3975
3976         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3977                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3978                 speed = hw->phy.autoneg_advertised;
3979                 if (!speed)
3980                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3981                 ixgbe_setup_link(hw, speed, true);
3982         }
3983
3984         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3985         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3986                 wait = 0;
3987
3988         if (vf)
3989                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3990         else
3991                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3992
3993         if (diag != 0) {
3994                 link.link_speed = ETH_SPEED_NUM_100M;
3995                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3996                 return rte_eth_linkstatus_set(dev, &link);
3997         }
3998
3999         if (link_up == 0) {
4000                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4001                 return rte_eth_linkstatus_set(dev, &link);
4002         }
4003
4004         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4005         link.link_status = ETH_LINK_UP;
4006         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4007
4008         switch (link_speed) {
4009         default:
4010         case IXGBE_LINK_SPEED_UNKNOWN:
4011                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4012                 link.link_speed = ETH_SPEED_NUM_100M;
4013                 break;
4014
4015         case IXGBE_LINK_SPEED_100_FULL:
4016                 link.link_speed = ETH_SPEED_NUM_100M;
4017                 break;
4018
4019         case IXGBE_LINK_SPEED_1GB_FULL:
4020                 link.link_speed = ETH_SPEED_NUM_1G;
4021                 break;
4022
4023         case IXGBE_LINK_SPEED_2_5GB_FULL:
4024                 link.link_speed = ETH_SPEED_NUM_2_5G;
4025                 break;
4026
4027         case IXGBE_LINK_SPEED_5GB_FULL:
4028                 link.link_speed = ETH_SPEED_NUM_5G;
4029                 break;
4030
4031         case IXGBE_LINK_SPEED_10GB_FULL:
4032                 link.link_speed = ETH_SPEED_NUM_10G;
4033                 break;
4034         }
4035
4036         return rte_eth_linkstatus_set(dev, &link);
4037 }
4038
4039 static int
4040 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4041 {
4042         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4043 }
4044
4045 static int
4046 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4047 {
4048         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4049 }
4050
4051 static void
4052 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4053 {
4054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         uint32_t fctrl;
4056
4057         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4058         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4059         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4060 }
4061
4062 static void
4063 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4064 {
4065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4066         uint32_t fctrl;
4067
4068         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4069         fctrl &= (~IXGBE_FCTRL_UPE);
4070         if (dev->data->all_multicast == 1)
4071                 fctrl |= IXGBE_FCTRL_MPE;
4072         else
4073                 fctrl &= (~IXGBE_FCTRL_MPE);
4074         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4075 }
4076
4077 static void
4078 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4079 {
4080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4081         uint32_t fctrl;
4082
4083         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4084         fctrl |= IXGBE_FCTRL_MPE;
4085         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4086 }
4087
4088 static void
4089 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4090 {
4091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092         uint32_t fctrl;
4093
4094         if (dev->data->promiscuous == 1)
4095                 return; /* must remain in all_multicast mode */
4096
4097         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4098         fctrl &= (~IXGBE_FCTRL_MPE);
4099         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4100 }
4101
4102 /**
4103  * It clears the interrupt causes and enables the interrupt.
4104  * It will be called once only during nic initialized.
4105  *
4106  * @param dev
4107  *  Pointer to struct rte_eth_dev.
4108  * @param on
4109  *  Enable or Disable.
4110  *
4111  * @return
4112  *  - On success, zero.
4113  *  - On failure, a negative value.
4114  */
4115 static int
4116 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4117 {
4118         struct ixgbe_interrupt *intr =
4119                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4120
4121         ixgbe_dev_link_status_print(dev);
4122         if (on)
4123                 intr->mask |= IXGBE_EICR_LSC;
4124         else
4125                 intr->mask &= ~IXGBE_EICR_LSC;
4126
4127         return 0;
4128 }
4129
4130 /**
4131  * It clears the interrupt causes and enables the interrupt.
4132  * It will be called once only during nic initialized.
4133  *
4134  * @param dev
4135  *  Pointer to struct rte_eth_dev.
4136  *
4137  * @return
4138  *  - On success, zero.
4139  *  - On failure, a negative value.
4140  */
4141 static int
4142 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4143 {
4144         struct ixgbe_interrupt *intr =
4145                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4146
4147         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4148
4149         return 0;
4150 }
4151
4152 /**
4153  * It clears the interrupt causes and enables the interrupt.
4154  * It will be called once only during nic initialized.
4155  *
4156  * @param dev
4157  *  Pointer to struct rte_eth_dev.
4158  *
4159  * @return
4160  *  - On success, zero.
4161  *  - On failure, a negative value.
4162  */
4163 static int
4164 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4165 {
4166         struct ixgbe_interrupt *intr =
4167                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168
4169         intr->mask |= IXGBE_EICR_LINKSEC;
4170
4171         return 0;
4172 }
4173
4174 /*
4175  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4176  *
4177  * @param dev
4178  *  Pointer to struct rte_eth_dev.
4179  *
4180  * @return
4181  *  - On success, zero.
4182  *  - On failure, a negative value.
4183  */
4184 static int
4185 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4186 {
4187         uint32_t eicr;
4188         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4189         struct ixgbe_interrupt *intr =
4190                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4191
4192         /* clear all cause mask */
4193         ixgbe_disable_intr(hw);
4194
4195         /* read-on-clear nic registers here */
4196         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4197         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4198
4199         intr->flags = 0;
4200
4201         /* set flag for async link update */
4202         if (eicr & IXGBE_EICR_LSC)
4203                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4204
4205         if (eicr & IXGBE_EICR_MAILBOX)
4206                 intr->flags |= IXGBE_FLAG_MAILBOX;
4207
4208         if (eicr & IXGBE_EICR_LINKSEC)
4209                 intr->flags |= IXGBE_FLAG_MACSEC;
4210
4211         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4212             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4213             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4214                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4215
4216         return 0;
4217 }
4218
4219 /**
4220  * It gets and then prints the link status.
4221  *
4222  * @param dev
4223  *  Pointer to struct rte_eth_dev.
4224  *
4225  * @return
4226  *  - On success, zero.
4227  *  - On failure, a negative value.
4228  */
4229 static void
4230 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4231 {
4232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4233         struct rte_eth_link link;
4234
4235         rte_eth_linkstatus_get(dev, &link);
4236
4237         if (link.link_status) {
4238                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4239                                         (int)(dev->data->port_id),
4240                                         (unsigned)link.link_speed,
4241                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4242                                         "full-duplex" : "half-duplex");
4243         } else {
4244                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4245                                 (int)(dev->data->port_id));
4246         }
4247         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4248                                 pci_dev->addr.domain,
4249                                 pci_dev->addr.bus,
4250                                 pci_dev->addr.devid,
4251                                 pci_dev->addr.function);
4252 }
4253
4254 /*
4255  * It executes link_update after knowing an interrupt occurred.
4256  *
4257  * @param dev
4258  *  Pointer to struct rte_eth_dev.
4259  *
4260  * @return
4261  *  - On success, zero.
4262  *  - On failure, a negative value.
4263  */
4264 static int
4265 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4266                            struct rte_intr_handle *intr_handle)
4267 {
4268         struct ixgbe_interrupt *intr =
4269                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4270         int64_t timeout;
4271         struct ixgbe_hw *hw =
4272                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4273
4274         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4275
4276         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4277                 ixgbe_pf_mbx_process(dev);
4278                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4279         }
4280
4281         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4282                 ixgbe_handle_lasi(hw);
4283                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4284         }
4285
4286         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4287                 struct rte_eth_link link;
4288
4289                 /* get the link status before link update, for predicting later */
4290                 rte_eth_linkstatus_get(dev, &link);
4291
4292                 ixgbe_dev_link_update(dev, 0);
4293
4294                 /* likely to up */
4295                 if (!link.link_status)
4296                         /* handle it 1 sec later, wait it being stable */
4297                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4298                 /* likely to down */
4299                 else
4300                         /* handle it 4 sec later, wait it being stable */
4301                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4302
4303                 ixgbe_dev_link_status_print(dev);
4304                 if (rte_eal_alarm_set(timeout * 1000,
4305                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4306                         PMD_DRV_LOG(ERR, "Error setting alarm");
4307                 else {
4308                         /* remember original mask */
4309                         intr->mask_original = intr->mask;
4310                         /* only disable lsc interrupt */
4311                         intr->mask &= ~IXGBE_EIMS_LSC;
4312                 }
4313         }
4314
4315         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4316         ixgbe_enable_intr(dev);
4317         rte_intr_enable(intr_handle);
4318
4319         return 0;
4320 }
4321
4322 /**
4323  * Interrupt handler which shall be registered for alarm callback for delayed
4324  * handling specific interrupt to wait for the stable nic state. As the
4325  * NIC interrupt state is not stable for ixgbe after link is just down,
4326  * it needs to wait 4 seconds to get the stable status.
4327  *
4328  * @param handle
4329  *  Pointer to interrupt handle.
4330  * @param param
4331  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4332  *
4333  * @return
4334  *  void
4335  */
4336 static void
4337 ixgbe_dev_interrupt_delayed_handler(void *param)
4338 {
4339         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4340         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4341         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4342         struct ixgbe_interrupt *intr =
4343                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4344         struct ixgbe_hw *hw =
4345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346         uint32_t eicr;
4347
4348         ixgbe_disable_intr(hw);
4349
4350         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4351         if (eicr & IXGBE_EICR_MAILBOX)
4352                 ixgbe_pf_mbx_process(dev);
4353
4354         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4355                 ixgbe_handle_lasi(hw);
4356                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4357         }
4358
4359         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4360                 ixgbe_dev_link_update(dev, 0);
4361                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4362                 ixgbe_dev_link_status_print(dev);
4363                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4364                                               NULL);
4365         }
4366
4367         if (intr->flags & IXGBE_FLAG_MACSEC) {
4368                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4369                                               NULL);
4370                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4371         }
4372
4373         /* restore original mask */
4374         intr->mask = intr->mask_original;
4375         intr->mask_original = 0;
4376
4377         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4378         ixgbe_enable_intr(dev);
4379         rte_intr_enable(intr_handle);
4380 }
4381
4382 /**
4383  * Interrupt handler triggered by NIC  for handling
4384  * specific interrupt.
4385  *
4386  * @param handle
4387  *  Pointer to interrupt handle.
4388  * @param param
4389  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4390  *
4391  * @return
4392  *  void
4393  */
4394 static void
4395 ixgbe_dev_interrupt_handler(void *param)
4396 {
4397         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4398
4399         ixgbe_dev_interrupt_get_status(dev);
4400         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4401 }
4402
4403 static int
4404 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4405 {
4406         struct ixgbe_hw *hw;
4407
4408         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4409         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4410 }
4411
4412 static int
4413 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4414 {
4415         struct ixgbe_hw *hw;
4416
4417         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4419 }
4420
4421 static int
4422 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4423 {
4424         struct ixgbe_hw *hw;
4425         uint32_t mflcn_reg;
4426         uint32_t fccfg_reg;
4427         int rx_pause;
4428         int tx_pause;
4429
4430         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4431
4432         fc_conf->pause_time = hw->fc.pause_time;
4433         fc_conf->high_water = hw->fc.high_water[0];
4434         fc_conf->low_water = hw->fc.low_water[0];
4435         fc_conf->send_xon = hw->fc.send_xon;
4436         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4437
4438         /*
4439          * Return rx_pause status according to actual setting of
4440          * MFLCN register.
4441          */
4442         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4443         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4444                 rx_pause = 1;
4445         else
4446                 rx_pause = 0;
4447
4448         /*
4449          * Return tx_pause status according to actual setting of
4450          * FCCFG register.
4451          */
4452         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4453         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4454                 tx_pause = 1;
4455         else
4456                 tx_pause = 0;
4457
4458         if (rx_pause && tx_pause)
4459                 fc_conf->mode = RTE_FC_FULL;
4460         else if (rx_pause)
4461                 fc_conf->mode = RTE_FC_RX_PAUSE;
4462         else if (tx_pause)
4463                 fc_conf->mode = RTE_FC_TX_PAUSE;
4464         else
4465                 fc_conf->mode = RTE_FC_NONE;
4466
4467         return 0;
4468 }
4469
4470 static int
4471 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4472 {
4473         struct ixgbe_hw *hw;
4474         int err;
4475         uint32_t rx_buf_size;
4476         uint32_t max_high_water;
4477         uint32_t mflcn;
4478         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4479                 ixgbe_fc_none,
4480                 ixgbe_fc_rx_pause,
4481                 ixgbe_fc_tx_pause,
4482                 ixgbe_fc_full
4483         };
4484
4485         PMD_INIT_FUNC_TRACE();
4486
4487         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4488         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4489         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4490
4491         /*
4492          * At least reserve one Ethernet frame for watermark
4493          * high_water/low_water in kilo bytes for ixgbe
4494          */
4495         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4496         if ((fc_conf->high_water > max_high_water) ||
4497                 (fc_conf->high_water < fc_conf->low_water)) {
4498                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4499                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4500                 return -EINVAL;
4501         }
4502
4503         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4504         hw->fc.pause_time     = fc_conf->pause_time;
4505         hw->fc.high_water[0]  = fc_conf->high_water;
4506         hw->fc.low_water[0]   = fc_conf->low_water;
4507         hw->fc.send_xon       = fc_conf->send_xon;
4508         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4509
4510         err = ixgbe_fc_enable(hw);
4511
4512         /* Not negotiated is not an error case */
4513         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4514
4515                 /* check if we want to forward MAC frames - driver doesn't have native
4516                  * capability to do that, so we'll write the registers ourselves */
4517
4518                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4519
4520                 /* set or clear MFLCN.PMCF bit depending on configuration */
4521                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4522                         mflcn |= IXGBE_MFLCN_PMCF;
4523                 else
4524                         mflcn &= ~IXGBE_MFLCN_PMCF;
4525
4526                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4527                 IXGBE_WRITE_FLUSH(hw);
4528
4529                 return 0;
4530         }
4531
4532         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4533         return -EIO;
4534 }
4535
4536 /**
4537  *  ixgbe_pfc_enable_generic - Enable flow control
4538  *  @hw: pointer to hardware structure
4539  *  @tc_num: traffic class number
4540  *  Enable flow control according to the current settings.
4541  */
4542 static int
4543 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4544 {
4545         int ret_val = 0;
4546         uint32_t mflcn_reg, fccfg_reg;
4547         uint32_t reg;
4548         uint32_t fcrtl, fcrth;
4549         uint8_t i;
4550         uint8_t nb_rx_en;
4551
4552         /* Validate the water mark configuration */
4553         if (!hw->fc.pause_time) {
4554                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4555                 goto out;
4556         }
4557
4558         /* Low water mark of zero causes XOFF floods */
4559         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4560                  /* High/Low water can not be 0 */
4561                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4562                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4563                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4564                         goto out;
4565                 }
4566
4567                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4568                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4569                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4570                         goto out;
4571                 }
4572         }
4573         /* Negotiate the fc mode to use */
4574         ixgbe_fc_autoneg(hw);
4575
4576         /* Disable any previous flow control settings */
4577         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4578         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4579
4580         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4581         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4582
4583         switch (hw->fc.current_mode) {
4584         case ixgbe_fc_none:
4585                 /*
4586                  * If the count of enabled RX Priority Flow control >1,
4587                  * and the TX pause can not be disabled
4588                  */
4589                 nb_rx_en = 0;
4590                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4591                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4592                         if (reg & IXGBE_FCRTH_FCEN)
4593                                 nb_rx_en++;
4594                 }
4595                 if (nb_rx_en > 1)
4596                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4597                 break;
4598         case ixgbe_fc_rx_pause:
4599                 /*
4600                  * Rx Flow control is enabled and Tx Flow control is
4601                  * disabled by software override. Since there really
4602                  * isn't a way to advertise that we are capable of RX
4603                  * Pause ONLY, we will advertise that we support both
4604                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4605                  * disable the adapter's ability to send PAUSE frames.
4606                  */
4607                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4608                 /*
4609                  * If the count of enabled RX Priority Flow control >1,
4610                  * and the TX pause can not be disabled
4611                  */
4612                 nb_rx_en = 0;
4613                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4614                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4615                         if (reg & IXGBE_FCRTH_FCEN)
4616                                 nb_rx_en++;
4617                 }
4618                 if (nb_rx_en > 1)
4619                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4620                 break;
4621         case ixgbe_fc_tx_pause:
4622                 /*
4623                  * Tx Flow control is enabled, and Rx Flow control is
4624                  * disabled by software override.
4625                  */
4626                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4627                 break;
4628         case ixgbe_fc_full:
4629                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4630                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4631                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4632                 break;
4633         default:
4634                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4635                 ret_val = IXGBE_ERR_CONFIG;
4636                 goto out;
4637         }
4638
4639         /* Set 802.3x based flow control settings. */
4640         mflcn_reg |= IXGBE_MFLCN_DPF;
4641         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4642         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4643
4644         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4645         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4646                 hw->fc.high_water[tc_num]) {
4647                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4648                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4649                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4650         } else {
4651                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4652                 /*
4653                  * In order to prevent Tx hangs when the internal Tx
4654                  * switch is enabled we must set the high water mark
4655                  * to the maximum FCRTH value.  This allows the Tx
4656                  * switch to function even under heavy Rx workloads.
4657                  */
4658                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4659         }
4660         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4661
4662         /* Configure pause time (2 TCs per register) */
4663         reg = hw->fc.pause_time * 0x00010001;
4664         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4665                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4666
4667         /* Configure flow control refresh threshold value */
4668         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4669
4670 out:
4671         return ret_val;
4672 }
4673
4674 static int
4675 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4676 {
4677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4678         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4679
4680         if (hw->mac.type != ixgbe_mac_82598EB) {
4681                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4682         }
4683         return ret_val;
4684 }
4685
4686 static int
4687 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4688 {
4689         int err;
4690         uint32_t rx_buf_size;
4691         uint32_t max_high_water;
4692         uint8_t tc_num;
4693         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4694         struct ixgbe_hw *hw =
4695                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4696         struct ixgbe_dcb_config *dcb_config =
4697                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4698
4699         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4700                 ixgbe_fc_none,
4701                 ixgbe_fc_rx_pause,
4702                 ixgbe_fc_tx_pause,
4703                 ixgbe_fc_full
4704         };
4705
4706         PMD_INIT_FUNC_TRACE();
4707
4708         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4709         tc_num = map[pfc_conf->priority];
4710         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4711         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4712         /*
4713          * At least reserve one Ethernet frame for watermark
4714          * high_water/low_water in kilo bytes for ixgbe
4715          */
4716         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4717         if ((pfc_conf->fc.high_water > max_high_water) ||
4718             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4719                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4720                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4721                 return -EINVAL;
4722         }
4723
4724         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4725         hw->fc.pause_time = pfc_conf->fc.pause_time;
4726         hw->fc.send_xon = pfc_conf->fc.send_xon;
4727         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4728         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4729
4730         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4731
4732         /* Not negotiated is not an error case */
4733         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4734                 return 0;
4735
4736         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4737         return -EIO;
4738 }
4739
4740 static int
4741 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4742                           struct rte_eth_rss_reta_entry64 *reta_conf,
4743                           uint16_t reta_size)
4744 {
4745         uint16_t i, sp_reta_size;
4746         uint8_t j, mask;
4747         uint32_t reta, r;
4748         uint16_t idx, shift;
4749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4750         uint32_t reta_reg;
4751
4752         PMD_INIT_FUNC_TRACE();
4753
4754         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4755                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4756                         "NIC.");
4757                 return -ENOTSUP;
4758         }
4759
4760         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4761         if (reta_size != sp_reta_size) {
4762                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4763                         "(%d) doesn't match the number hardware can supported "
4764                         "(%d)", reta_size, sp_reta_size);
4765                 return -EINVAL;
4766         }
4767
4768         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4769                 idx = i / RTE_RETA_GROUP_SIZE;
4770                 shift = i % RTE_RETA_GROUP_SIZE;
4771                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4772                                                 IXGBE_4_BIT_MASK);
4773                 if (!mask)
4774                         continue;
4775                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4776                 if (mask == IXGBE_4_BIT_MASK)
4777                         r = 0;
4778                 else
4779                         r = IXGBE_READ_REG(hw, reta_reg);
4780                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4781                         if (mask & (0x1 << j))
4782                                 reta |= reta_conf[idx].reta[shift + j] <<
4783                                                         (CHAR_BIT * j);
4784                         else
4785                                 reta |= r & (IXGBE_8_BIT_MASK <<
4786                                                 (CHAR_BIT * j));
4787                 }
4788                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4789         }
4790
4791         return 0;
4792 }
4793
4794 static int
4795 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4796                          struct rte_eth_rss_reta_entry64 *reta_conf,
4797                          uint16_t reta_size)
4798 {
4799         uint16_t i, sp_reta_size;
4800         uint8_t j, mask;
4801         uint32_t reta;
4802         uint16_t idx, shift;
4803         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804         uint32_t reta_reg;
4805
4806         PMD_INIT_FUNC_TRACE();
4807         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4808         if (reta_size != sp_reta_size) {
4809                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4810                         "(%d) doesn't match the number hardware can supported "
4811                         "(%d)", reta_size, sp_reta_size);
4812                 return -EINVAL;
4813         }
4814
4815         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4816                 idx = i / RTE_RETA_GROUP_SIZE;
4817                 shift = i % RTE_RETA_GROUP_SIZE;
4818                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4819                                                 IXGBE_4_BIT_MASK);
4820                 if (!mask)
4821                         continue;
4822
4823                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4824                 reta = IXGBE_READ_REG(hw, reta_reg);
4825                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4826                         if (mask & (0x1 << j))
4827                                 reta_conf[idx].reta[shift + j] =
4828                                         ((reta >> (CHAR_BIT * j)) &
4829                                                 IXGBE_8_BIT_MASK);
4830                 }
4831         }
4832
4833         return 0;
4834 }
4835
4836 static int
4837 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4838                                 uint32_t index, uint32_t pool)
4839 {
4840         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4841         uint32_t enable_addr = 1;
4842
4843         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4844                              pool, enable_addr);
4845 }
4846
4847 static void
4848 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4849 {
4850         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851
4852         ixgbe_clear_rar(hw, index);
4853 }
4854
4855 static int
4856 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4857 {
4858         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4859
4860         ixgbe_remove_rar(dev, 0);
4861         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4862
4863         return 0;
4864 }
4865
4866 static bool
4867 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4868 {
4869         if (strcmp(dev->device->driver->name, drv->driver.name))
4870                 return false;
4871
4872         return true;
4873 }
4874
4875 bool
4876 is_ixgbe_supported(struct rte_eth_dev *dev)
4877 {
4878         return is_device_supported(dev, &rte_ixgbe_pmd);
4879 }
4880
4881 static int
4882 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4883 {
4884         uint32_t hlreg0;
4885         uint32_t maxfrs;
4886         struct ixgbe_hw *hw;
4887         struct rte_eth_dev_info dev_info;
4888         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4889         struct rte_eth_dev_data *dev_data = dev->data;
4890
4891         ixgbe_dev_info_get(dev, &dev_info);
4892
4893         /* check that mtu is within the allowed range */
4894         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4895                 return -EINVAL;
4896
4897         /* If device is started, refuse mtu that requires the support of
4898          * scattered packets when this feature has not been enabled before.
4899          */
4900         if (dev_data->dev_started && !dev_data->scattered_rx &&
4901             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4902              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4903                 PMD_INIT_LOG(ERR, "Stop port first.");
4904                 return -EINVAL;
4905         }
4906
4907         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4908         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4909
4910         /* switch to jumbo mode if needed */
4911         if (frame_size > ETHER_MAX_LEN) {
4912                 dev->data->dev_conf.rxmode.offloads |=
4913                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4914                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4915         } else {
4916                 dev->data->dev_conf.rxmode.offloads &=
4917                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4918                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4919         }
4920         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4921
4922         /* update max frame size */
4923         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4924
4925         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4926         maxfrs &= 0x0000FFFF;
4927         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4928         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4929
4930         return 0;
4931 }
4932
4933 /*
4934  * Virtual Function operations
4935  */
4936 static void
4937 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4938 {
4939         PMD_INIT_FUNC_TRACE();
4940
4941         /* Clear interrupt mask to stop from interrupts being generated */
4942         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4943
4944         IXGBE_WRITE_FLUSH(hw);
4945 }
4946
4947 static void
4948 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4949 {
4950         PMD_INIT_FUNC_TRACE();
4951
4952         /* VF enable interrupt autoclean */
4953         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4954         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4955         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4956
4957         IXGBE_WRITE_FLUSH(hw);
4958 }
4959
4960 static int
4961 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4962 {
4963         struct rte_eth_conf *conf = &dev->data->dev_conf;
4964         struct ixgbe_adapter *adapter =
4965                         (struct ixgbe_adapter *)dev->data->dev_private;
4966         struct rte_eth_dev_info dev_info;
4967         uint64_t rx_offloads;
4968         uint64_t tx_offloads;
4969
4970         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4971                      dev->data->port_id);
4972
4973         ixgbevf_dev_info_get(dev, &dev_info);
4974         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4975         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4976                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4977                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4978                             rx_offloads, dev_info.rx_offload_capa);
4979                 return -ENOTSUP;
4980         }
4981         tx_offloads = dev->data->dev_conf.txmode.offloads;
4982         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4983                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4984                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4985                             tx_offloads, dev_info.tx_offload_capa);
4986                 return -ENOTSUP;
4987         }
4988
4989         /*
4990          * VF has no ability to enable/disable HW CRC
4991          * Keep the persistent behavior the same as Host PF
4992          */
4993 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4994         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4995                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4996                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4997         }
4998 #else
4999         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
5000                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5001                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
5002         }
5003 #endif
5004
5005         /*
5006          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5007          * allocation or vector Rx preconditions we will reset it.
5008          */
5009         adapter->rx_bulk_alloc_allowed = true;
5010         adapter->rx_vec_allowed = true;
5011
5012         return 0;
5013 }
5014
5015 static int
5016 ixgbevf_dev_start(struct rte_eth_dev *dev)
5017 {
5018         struct ixgbe_hw *hw =
5019                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020         uint32_t intr_vector = 0;
5021         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5022         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5023
5024         int err, mask = 0;
5025
5026         PMD_INIT_FUNC_TRACE();
5027
5028         err = hw->mac.ops.reset_hw(hw);
5029         if (err) {
5030                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5031                 return err;
5032         }
5033         hw->mac.get_link_status = true;
5034
5035         /* negotiate mailbox API version to use with the PF. */
5036         ixgbevf_negotiate_api(hw);
5037
5038         ixgbevf_dev_tx_init(dev);
5039
5040         /* This can fail when allocating mbufs for descriptor rings */
5041         err = ixgbevf_dev_rx_init(dev);
5042         if (err) {
5043                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5044                 ixgbe_dev_clear_queues(dev);
5045                 return err;
5046         }
5047
5048         /* Set vfta */
5049         ixgbevf_set_vfta_all(dev, 1);
5050
5051         /* Set HW strip */
5052         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5053                 ETH_VLAN_EXTEND_MASK;
5054         err = ixgbevf_vlan_offload_set(dev, mask);
5055         if (err) {
5056                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5057                 ixgbe_dev_clear_queues(dev);
5058                 return err;
5059         }
5060
5061         ixgbevf_dev_rxtx_start(dev);
5062
5063         ixgbevf_dev_link_update(dev, 0);
5064
5065         /* check and configure queue intr-vector mapping */
5066         if (rte_intr_cap_multiple(intr_handle) &&
5067             dev->data->dev_conf.intr_conf.rxq) {
5068                 /* According to datasheet, only vector 0/1/2 can be used,
5069                  * now only one vector is used for Rx queue
5070                  */
5071                 intr_vector = 1;
5072                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5073                         return -1;
5074         }
5075
5076         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5077                 intr_handle->intr_vec =
5078                         rte_zmalloc("intr_vec",
5079                                     dev->data->nb_rx_queues * sizeof(int), 0);
5080                 if (intr_handle->intr_vec == NULL) {
5081                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5082                                      " intr_vec", dev->data->nb_rx_queues);
5083                         return -ENOMEM;
5084                 }
5085         }
5086         ixgbevf_configure_msix(dev);
5087
5088         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5089          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5090          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5091          * is not cleared, it will fail when following rte_intr_enable( ) tries
5092          * to map Rx queue interrupt to other VFIO vectors.
5093          * So clear uio/vfio intr/evevnfd first to avoid failure.
5094          */
5095         rte_intr_disable(intr_handle);
5096
5097         rte_intr_enable(intr_handle);
5098
5099         /* Re-enable interrupt for VF */
5100         ixgbevf_intr_enable(hw);
5101
5102         return 0;
5103 }
5104
5105 static void
5106 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5107 {
5108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5110         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5111
5112         PMD_INIT_FUNC_TRACE();
5113
5114         ixgbevf_intr_disable(hw);
5115
5116         hw->adapter_stopped = 1;
5117         ixgbe_stop_adapter(hw);
5118
5119         /*
5120           * Clear what we set, but we still keep shadow_vfta to
5121           * restore after device starts
5122           */
5123         ixgbevf_set_vfta_all(dev, 0);
5124
5125         /* Clear stored conf */
5126         dev->data->scattered_rx = 0;
5127
5128         ixgbe_dev_clear_queues(dev);
5129
5130         /* Clean datapath event and queue/vec mapping */
5131         rte_intr_efd_disable(intr_handle);
5132         if (intr_handle->intr_vec != NULL) {
5133                 rte_free(intr_handle->intr_vec);
5134                 intr_handle->intr_vec = NULL;
5135         }
5136 }
5137
5138 static void
5139 ixgbevf_dev_close(struct rte_eth_dev *dev)
5140 {
5141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142
5143         PMD_INIT_FUNC_TRACE();
5144
5145         ixgbe_reset_hw(hw);
5146
5147         ixgbevf_dev_stop(dev);
5148
5149         ixgbe_dev_free_queues(dev);
5150
5151         /**
5152          * Remove the VF MAC address ro ensure
5153          * that the VF traffic goes to the PF
5154          * after stop, close and detach of the VF
5155          **/
5156         ixgbevf_remove_mac_addr(dev, 0);
5157 }
5158
5159 /*
5160  * Reset VF device
5161  */
5162 static int
5163 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5164 {
5165         int ret;
5166
5167         ret = eth_ixgbevf_dev_uninit(dev);
5168         if (ret)
5169                 return ret;
5170
5171         ret = eth_ixgbevf_dev_init(dev);
5172
5173         return ret;
5174 }
5175
5176 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5177 {
5178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5179         struct ixgbe_vfta *shadow_vfta =
5180                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5181         int i = 0, j = 0, vfta = 0, mask = 1;
5182
5183         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5184                 vfta = shadow_vfta->vfta[i];
5185                 if (vfta) {
5186                         mask = 1;
5187                         for (j = 0; j < 32; j++) {
5188                                 if (vfta & mask)
5189                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5190                                                        on, false);
5191                                 mask <<= 1;
5192                         }
5193                 }
5194         }
5195
5196 }
5197
5198 static int
5199 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5200 {
5201         struct ixgbe_hw *hw =
5202                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203         struct ixgbe_vfta *shadow_vfta =
5204                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5205         uint32_t vid_idx = 0;
5206         uint32_t vid_bit = 0;
5207         int ret = 0;
5208
5209         PMD_INIT_FUNC_TRACE();
5210
5211         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5212         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5213         if (ret) {
5214                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5215                 return ret;
5216         }
5217         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5218         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5219
5220         /* Save what we set and retore it after device reset */
5221         if (on)
5222                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5223         else
5224                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5225
5226         return 0;
5227 }
5228
5229 static void
5230 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5231 {
5232         struct ixgbe_hw *hw =
5233                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5234         uint32_t ctrl;
5235
5236         PMD_INIT_FUNC_TRACE();
5237
5238         if (queue >= hw->mac.max_rx_queues)
5239                 return;
5240
5241         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5242         if (on)
5243                 ctrl |= IXGBE_RXDCTL_VME;
5244         else
5245                 ctrl &= ~IXGBE_RXDCTL_VME;
5246         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5247
5248         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5249 }
5250
5251 static int
5252 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5253 {
5254         struct ixgbe_rx_queue *rxq;
5255         uint16_t i;
5256         int on = 0;
5257
5258         /* VF function only support hw strip feature, others are not support */
5259         if (mask & ETH_VLAN_STRIP_MASK) {
5260                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5261                         rxq = dev->data->rx_queues[i];
5262                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5263                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5264                 }
5265         }
5266
5267         return 0;
5268 }
5269
5270 int
5271 ixgbe_vt_check(struct ixgbe_hw *hw)
5272 {
5273         uint32_t reg_val;
5274
5275         /* if Virtualization Technology is enabled */
5276         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5277         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5278                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5279                 return -1;
5280         }
5281
5282         return 0;
5283 }
5284
5285 static uint32_t
5286 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5287 {
5288         uint32_t vector = 0;
5289
5290         switch (hw->mac.mc_filter_type) {
5291         case 0:   /* use bits [47:36] of the address */
5292                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5293                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5294                 break;
5295         case 1:   /* use bits [46:35] of the address */
5296                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5297                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5298                 break;
5299         case 2:   /* use bits [45:34] of the address */
5300                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5301                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5302                 break;
5303         case 3:   /* use bits [43:32] of the address */
5304                 vector = ((uc_addr->addr_bytes[4]) |
5305                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5306                 break;
5307         default:  /* Invalid mc_filter_type */
5308                 break;
5309         }
5310
5311         /* vector can only be 12-bits or boundary will be exceeded */
5312         vector &= 0xFFF;
5313         return vector;
5314 }
5315
5316 static int
5317 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5318                         uint8_t on)
5319 {
5320         uint32_t vector;
5321         uint32_t uta_idx;
5322         uint32_t reg_val;
5323         uint32_t uta_shift;
5324         uint32_t rc;
5325         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5326         const uint32_t ixgbe_uta_bit_shift = 5;
5327         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5328         const uint32_t bit1 = 0x1;
5329
5330         struct ixgbe_hw *hw =
5331                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5332         struct ixgbe_uta_info *uta_info =
5333                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5334
5335         /* The UTA table only exists on 82599 hardware and newer */
5336         if (hw->mac.type < ixgbe_mac_82599EB)
5337                 return -ENOTSUP;
5338
5339         vector = ixgbe_uta_vector(hw, mac_addr);
5340         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5341         uta_shift = vector & ixgbe_uta_bit_mask;
5342
5343         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5344         if (rc == on)
5345                 return 0;
5346
5347         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5348         if (on) {
5349                 uta_info->uta_in_use++;
5350                 reg_val |= (bit1 << uta_shift);
5351                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5352         } else {
5353                 uta_info->uta_in_use--;
5354                 reg_val &= ~(bit1 << uta_shift);
5355                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5356         }
5357
5358         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5359
5360         if (uta_info->uta_in_use > 0)
5361                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5362                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5363         else
5364                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5365
5366         return 0;
5367 }
5368
5369 static int
5370 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5371 {
5372         int i;
5373         struct ixgbe_hw *hw =
5374                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5375         struct ixgbe_uta_info *uta_info =
5376                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5377
5378         /* The UTA table only exists on 82599 hardware and newer */
5379         if (hw->mac.type < ixgbe_mac_82599EB)
5380                 return -ENOTSUP;
5381
5382         if (on) {
5383                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5384                         uta_info->uta_shadow[i] = ~0;
5385                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5386                 }
5387         } else {
5388                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5389                         uta_info->uta_shadow[i] = 0;
5390                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5391                 }
5392         }
5393         return 0;
5394
5395 }
5396
5397 uint32_t
5398 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5399 {
5400         uint32_t new_val = orig_val;
5401
5402         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5403                 new_val |= IXGBE_VMOLR_AUPE;
5404         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5405                 new_val |= IXGBE_VMOLR_ROMPE;
5406         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5407                 new_val |= IXGBE_VMOLR_ROPE;
5408         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5409                 new_val |= IXGBE_VMOLR_BAM;
5410         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5411                 new_val |= IXGBE_VMOLR_MPE;
5412
5413         return new_val;
5414 }
5415
5416 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5417 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5418 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5419 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5420 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5421         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5422         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5423
5424 static int
5425 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5426                       struct rte_eth_mirror_conf *mirror_conf,
5427                       uint8_t rule_id, uint8_t on)
5428 {
5429         uint32_t mr_ctl, vlvf;
5430         uint32_t mp_lsb = 0;
5431         uint32_t mv_msb = 0;
5432         uint32_t mv_lsb = 0;
5433         uint32_t mp_msb = 0;
5434         uint8_t i = 0;
5435         int reg_index = 0;
5436         uint64_t vlan_mask = 0;
5437
5438         const uint8_t pool_mask_offset = 32;
5439         const uint8_t vlan_mask_offset = 32;
5440         const uint8_t dst_pool_offset = 8;
5441         const uint8_t rule_mr_offset  = 4;
5442         const uint8_t mirror_rule_mask = 0x0F;
5443
5444         struct ixgbe_mirror_info *mr_info =
5445                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5446         struct ixgbe_hw *hw =
5447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448         uint8_t mirror_type = 0;
5449
5450         if (ixgbe_vt_check(hw) < 0)
5451                 return -ENOTSUP;
5452
5453         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5454                 return -EINVAL;
5455
5456         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5457                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5458                             mirror_conf->rule_type);
5459                 return -EINVAL;
5460         }
5461
5462         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5463                 mirror_type |= IXGBE_MRCTL_VLME;
5464                 /* Check if vlan id is valid and find conresponding VLAN ID
5465                  * index in VLVF
5466                  */
5467                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5468                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5469                                 /* search vlan id related pool vlan filter
5470                                  * index
5471                                  */
5472                                 reg_index = ixgbe_find_vlvf_slot(
5473                                                 hw,
5474                                                 mirror_conf->vlan.vlan_id[i],
5475                                                 false);
5476                                 if (reg_index < 0)
5477                                         return -EINVAL;
5478                                 vlvf = IXGBE_READ_REG(hw,
5479                                                       IXGBE_VLVF(reg_index));
5480                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5481                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5482                                       mirror_conf->vlan.vlan_id[i]))
5483                                         vlan_mask |= (1ULL << reg_index);
5484                                 else
5485                                         return -EINVAL;
5486                         }
5487                 }
5488
5489                 if (on) {
5490                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5491                         mv_msb = vlan_mask >> vlan_mask_offset;
5492
5493                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5494                                                 mirror_conf->vlan.vlan_mask;
5495                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5496                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5497                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5498                                                 mirror_conf->vlan.vlan_id[i];
5499                         }
5500                 } else {
5501                         mv_lsb = 0;
5502                         mv_msb = 0;
5503                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5504                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5505                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5506                 }
5507         }
5508
5509         /**
5510          * if enable pool mirror, write related pool mask register,if disable
5511          * pool mirror, clear PFMRVM register
5512          */
5513         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5514                 mirror_type |= IXGBE_MRCTL_VPME;
5515                 if (on) {
5516                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5517                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5518                         mr_info->mr_conf[rule_id].pool_mask =
5519                                         mirror_conf->pool_mask;
5520
5521                 } else {
5522                         mp_lsb = 0;
5523                         mp_msb = 0;
5524                         mr_info->mr_conf[rule_id].pool_mask = 0;
5525                 }
5526         }
5527         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5528                 mirror_type |= IXGBE_MRCTL_UPME;
5529         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5530                 mirror_type |= IXGBE_MRCTL_DPME;
5531
5532         /* read  mirror control register and recalculate it */
5533         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5534
5535         if (on) {
5536                 mr_ctl |= mirror_type;
5537                 mr_ctl &= mirror_rule_mask;
5538                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5539         } else {
5540                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5541         }
5542
5543         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5544         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5545
5546         /* write mirrror control  register */
5547         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5548
5549         /* write pool mirrror control  register */
5550         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5551                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5552                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5553                                 mp_msb);
5554         }
5555         /* write VLAN mirrror control  register */
5556         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5557                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5558                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5559                                 mv_msb);
5560         }
5561
5562         return 0;
5563 }
5564
5565 static int
5566 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5567 {
5568         int mr_ctl = 0;
5569         uint32_t lsb_val = 0;
5570         uint32_t msb_val = 0;
5571         const uint8_t rule_mr_offset = 4;
5572
5573         struct ixgbe_hw *hw =
5574                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5575         struct ixgbe_mirror_info *mr_info =
5576                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5577
5578         if (ixgbe_vt_check(hw) < 0)
5579                 return -ENOTSUP;
5580
5581         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5582                 return -EINVAL;
5583
5584         memset(&mr_info->mr_conf[rule_id], 0,
5585                sizeof(struct rte_eth_mirror_conf));
5586
5587         /* clear PFVMCTL register */
5588         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5589
5590         /* clear pool mask register */
5591         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5592         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5593
5594         /* clear vlan mask register */
5595         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5596         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5597
5598         return 0;
5599 }
5600
5601 static int
5602 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5603 {
5604         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5605         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5606         uint32_t mask;
5607         struct ixgbe_hw *hw =
5608                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5609         uint32_t vec = IXGBE_MISC_VEC_ID;
5610
5611         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5612         if (rte_intr_allow_others(intr_handle))
5613                 vec = IXGBE_RX_VEC_START;
5614         mask |= (1 << vec);
5615         RTE_SET_USED(queue_id);
5616         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5617
5618         rte_intr_enable(intr_handle);
5619
5620         return 0;
5621 }
5622
5623 static int
5624 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5625 {
5626         uint32_t mask;
5627         struct ixgbe_hw *hw =
5628                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5629         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5630         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5631         uint32_t vec = IXGBE_MISC_VEC_ID;
5632
5633         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5634         if (rte_intr_allow_others(intr_handle))
5635                 vec = IXGBE_RX_VEC_START;
5636         mask &= ~(1 << vec);
5637         RTE_SET_USED(queue_id);
5638         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5639
5640         return 0;
5641 }
5642
5643 static int
5644 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5645 {
5646         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5647         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5648         uint32_t mask;
5649         struct ixgbe_hw *hw =
5650                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5651         struct ixgbe_interrupt *intr =
5652                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5653
5654         if (queue_id < 16) {
5655                 ixgbe_disable_intr(hw);
5656                 intr->mask |= (1 << queue_id);
5657                 ixgbe_enable_intr(dev);
5658         } else if (queue_id < 32) {
5659                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5660                 mask &= (1 << queue_id);
5661                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5662         } else if (queue_id < 64) {
5663                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5664                 mask &= (1 << (queue_id - 32));
5665                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5666         }
5667         rte_intr_enable(intr_handle);
5668
5669         return 0;
5670 }
5671
5672 static int
5673 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5674 {
5675         uint32_t mask;
5676         struct ixgbe_hw *hw =
5677                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5678         struct ixgbe_interrupt *intr =
5679                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5680
5681         if (queue_id < 16) {
5682                 ixgbe_disable_intr(hw);
5683                 intr->mask &= ~(1 << queue_id);
5684                 ixgbe_enable_intr(dev);
5685         } else if (queue_id < 32) {
5686                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5687                 mask &= ~(1 << queue_id);
5688                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5689         } else if (queue_id < 64) {
5690                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5691                 mask &= ~(1 << (queue_id - 32));
5692                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5693         }
5694
5695         return 0;
5696 }
5697
5698 static void
5699 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5700                      uint8_t queue, uint8_t msix_vector)
5701 {
5702         uint32_t tmp, idx;
5703
5704         if (direction == -1) {
5705                 /* other causes */
5706                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5707                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5708                 tmp &= ~0xFF;
5709                 tmp |= msix_vector;
5710                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5711         } else {
5712                 /* rx or tx cause */
5713                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5714                 idx = ((16 * (queue & 1)) + (8 * direction));
5715                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5716                 tmp &= ~(0xFF << idx);
5717                 tmp |= (msix_vector << idx);
5718                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5719         }
5720 }
5721
5722 /**
5723  * set the IVAR registers, mapping interrupt causes to vectors
5724  * @param hw
5725  *  pointer to ixgbe_hw struct
5726  * @direction
5727  *  0 for Rx, 1 for Tx, -1 for other causes
5728  * @queue
5729  *  queue to map the corresponding interrupt to
5730  * @msix_vector
5731  *  the vector to map to the corresponding queue
5732  */
5733 static void
5734 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5735                    uint8_t queue, uint8_t msix_vector)
5736 {
5737         uint32_t tmp, idx;
5738
5739         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5740         if (hw->mac.type == ixgbe_mac_82598EB) {
5741                 if (direction == -1)
5742                         direction = 0;
5743                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5744                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5745                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5746                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5747                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5748         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5749                         (hw->mac.type == ixgbe_mac_X540) ||
5750                         (hw->mac.type == ixgbe_mac_X550)) {
5751                 if (direction == -1) {
5752                         /* other causes */
5753                         idx = ((queue & 1) * 8);
5754                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5755                         tmp &= ~(0xFF << idx);
5756                         tmp |= (msix_vector << idx);
5757                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5758                 } else {
5759                         /* rx or tx causes */
5760                         idx = ((16 * (queue & 1)) + (8 * direction));
5761                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5762                         tmp &= ~(0xFF << idx);
5763                         tmp |= (msix_vector << idx);
5764                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5765                 }
5766         }
5767 }
5768
5769 static void
5770 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5771 {
5772         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5773         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5774         struct ixgbe_hw *hw =
5775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5776         uint32_t q_idx;
5777         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5778         uint32_t base = IXGBE_MISC_VEC_ID;
5779
5780         /* Configure VF other cause ivar */
5781         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5782
5783         /* won't configure msix register if no mapping is done
5784          * between intr vector and event fd.
5785          */
5786         if (!rte_intr_dp_is_en(intr_handle))
5787                 return;
5788
5789         if (rte_intr_allow_others(intr_handle)) {
5790                 base = IXGBE_RX_VEC_START;
5791                 vector_idx = IXGBE_RX_VEC_START;
5792         }
5793
5794         /* Configure all RX queues of VF */
5795         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5796                 /* Force all queue use vector 0,
5797                  * as IXGBE_VF_MAXMSIVECOTR = 1
5798                  */
5799                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5800                 intr_handle->intr_vec[q_idx] = vector_idx;
5801                 if (vector_idx < base + intr_handle->nb_efd - 1)
5802                         vector_idx++;
5803         }
5804 }
5805
5806 /**
5807  * Sets up the hardware to properly generate MSI-X interrupts
5808  * @hw
5809  *  board private structure
5810  */
5811 static void
5812 ixgbe_configure_msix(struct rte_eth_dev *dev)
5813 {
5814         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5815         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5816         struct ixgbe_hw *hw =
5817                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5818         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5819         uint32_t vec = IXGBE_MISC_VEC_ID;
5820         uint32_t mask;
5821         uint32_t gpie;
5822
5823         /* won't configure msix register if no mapping is done
5824          * between intr vector and event fd
5825          */
5826         if (!rte_intr_dp_is_en(intr_handle))
5827                 return;
5828
5829         if (rte_intr_allow_others(intr_handle))
5830                 vec = base = IXGBE_RX_VEC_START;
5831
5832         /* setup GPIE for MSI-x mode */
5833         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5834         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5835                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5836         /* auto clearing and auto setting corresponding bits in EIMS
5837          * when MSI-X interrupt is triggered
5838          */
5839         if (hw->mac.type == ixgbe_mac_82598EB) {
5840                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5841         } else {
5842                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5843                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5844         }
5845         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5846
5847         /* Populate the IVAR table and set the ITR values to the
5848          * corresponding register.
5849          */
5850         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5851              queue_id++) {
5852                 /* by default, 1:1 mapping */
5853                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5854                 intr_handle->intr_vec[queue_id] = vec;
5855                 if (vec < base + intr_handle->nb_efd - 1)
5856                         vec++;
5857         }
5858
5859         switch (hw->mac.type) {
5860         case ixgbe_mac_82598EB:
5861                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5862                                    IXGBE_MISC_VEC_ID);
5863                 break;
5864         case ixgbe_mac_82599EB:
5865         case ixgbe_mac_X540:
5866         case ixgbe_mac_X550:
5867                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5868                 break;
5869         default:
5870                 break;
5871         }
5872         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5873                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5874
5875         /* set up to autoclear timer, and the vectors */
5876         mask = IXGBE_EIMS_ENABLE_MASK;
5877         mask &= ~(IXGBE_EIMS_OTHER |
5878                   IXGBE_EIMS_MAILBOX |
5879                   IXGBE_EIMS_LSC);
5880
5881         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5882 }
5883
5884 int
5885 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5886                            uint16_t queue_idx, uint16_t tx_rate)
5887 {
5888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5889         struct rte_eth_rxmode *rxmode;
5890         uint32_t rf_dec, rf_int;
5891         uint32_t bcnrc_val;
5892         uint16_t link_speed = dev->data->dev_link.link_speed;
5893
5894         if (queue_idx >= hw->mac.max_tx_queues)
5895                 return -EINVAL;
5896
5897         if (tx_rate != 0) {
5898                 /* Calculate the rate factor values to set */
5899                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5900                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5901                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5902
5903                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5904                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5905                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5906                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5907         } else {
5908                 bcnrc_val = 0;
5909         }
5910
5911         rxmode = &dev->data->dev_conf.rxmode;
5912         /*
5913          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5914          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5915          * set as 0x4.
5916          */
5917         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5918             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5919                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5920                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5921         else
5922                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5923                         IXGBE_MMW_SIZE_DEFAULT);
5924
5925         /* Set RTTBCNRC of queue X */
5926         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5927         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5928         IXGBE_WRITE_FLUSH(hw);
5929
5930         return 0;
5931 }
5932
5933 static int
5934 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5935                      __attribute__((unused)) uint32_t index,
5936                      __attribute__((unused)) uint32_t pool)
5937 {
5938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939         int diag;
5940
5941         /*
5942          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5943          * operation. Trap this case to avoid exhausting the [very limited]
5944          * set of PF resources used to store VF MAC addresses.
5945          */
5946         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5947                 return -1;
5948         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5949         if (diag != 0)
5950                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5951                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5952                             mac_addr->addr_bytes[0],
5953                             mac_addr->addr_bytes[1],
5954                             mac_addr->addr_bytes[2],
5955                             mac_addr->addr_bytes[3],
5956                             mac_addr->addr_bytes[4],
5957                             mac_addr->addr_bytes[5],
5958                             diag);
5959         return diag;
5960 }
5961
5962 static void
5963 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5964 {
5965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5966         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5967         struct ether_addr *mac_addr;
5968         uint32_t i;
5969         int diag;
5970
5971         /*
5972          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5973          * not support the deletion of a given MAC address.
5974          * Instead, it imposes to delete all MAC addresses, then to add again
5975          * all MAC addresses with the exception of the one to be deleted.
5976          */
5977         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5978
5979         /*
5980          * Add again all MAC addresses, with the exception of the deleted one
5981          * and of the permanent MAC address.
5982          */
5983         for (i = 0, mac_addr = dev->data->mac_addrs;
5984              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5985                 /* Skip the deleted MAC address */
5986                 if (i == index)
5987                         continue;
5988                 /* Skip NULL MAC addresses */
5989                 if (is_zero_ether_addr(mac_addr))
5990                         continue;
5991                 /* Skip the permanent MAC address */
5992                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5993                         continue;
5994                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5995                 if (diag != 0)
5996                         PMD_DRV_LOG(ERR,
5997                                     "Adding again MAC address "
5998                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5999                                     "diag=%d",
6000                                     mac_addr->addr_bytes[0],
6001                                     mac_addr->addr_bytes[1],
6002                                     mac_addr->addr_bytes[2],
6003                                     mac_addr->addr_bytes[3],
6004                                     mac_addr->addr_bytes[4],
6005                                     mac_addr->addr_bytes[5],
6006                                     diag);
6007         }
6008 }
6009
6010 static int
6011 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6012 {
6013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014
6015         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6016
6017         return 0;
6018 }
6019
6020 int
6021 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6022                         struct rte_eth_syn_filter *filter,
6023                         bool add)
6024 {
6025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6026         struct ixgbe_filter_info *filter_info =
6027                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6028         uint32_t syn_info;
6029         uint32_t synqf;
6030
6031         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6032                 return -EINVAL;
6033
6034         syn_info = filter_info->syn_info;
6035
6036         if (add) {
6037                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6038                         return -EINVAL;
6039                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6040                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6041
6042                 if (filter->hig_pri)
6043                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6044                 else
6045                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6046         } else {
6047                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6048                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6049                         return -ENOENT;
6050                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6051         }
6052
6053         filter_info->syn_info = synqf;
6054         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6055         IXGBE_WRITE_FLUSH(hw);
6056         return 0;
6057 }
6058
6059 static int
6060 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6061                         struct rte_eth_syn_filter *filter)
6062 {
6063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6064         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6065
6066         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6067                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6068                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6069                 return 0;
6070         }
6071         return -ENOENT;
6072 }
6073
6074 static int
6075 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6076                         enum rte_filter_op filter_op,
6077                         void *arg)
6078 {
6079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6080         int ret;
6081
6082         MAC_TYPE_FILTER_SUP(hw->mac.type);
6083
6084         if (filter_op == RTE_ETH_FILTER_NOP)
6085                 return 0;
6086
6087         if (arg == NULL) {
6088                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6089                             filter_op);
6090                 return -EINVAL;
6091         }
6092
6093         switch (filter_op) {
6094         case RTE_ETH_FILTER_ADD:
6095                 ret = ixgbe_syn_filter_set(dev,
6096                                 (struct rte_eth_syn_filter *)arg,
6097                                 TRUE);
6098                 break;
6099         case RTE_ETH_FILTER_DELETE:
6100                 ret = ixgbe_syn_filter_set(dev,
6101                                 (struct rte_eth_syn_filter *)arg,
6102                                 FALSE);
6103                 break;
6104         case RTE_ETH_FILTER_GET:
6105                 ret = ixgbe_syn_filter_get(dev,
6106                                 (struct rte_eth_syn_filter *)arg);
6107                 break;
6108         default:
6109                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6110                 ret = -EINVAL;
6111                 break;
6112         }
6113
6114         return ret;
6115 }
6116
6117
6118 static inline enum ixgbe_5tuple_protocol
6119 convert_protocol_type(uint8_t protocol_value)
6120 {
6121         if (protocol_value == IPPROTO_TCP)
6122                 return IXGBE_FILTER_PROTOCOL_TCP;
6123         else if (protocol_value == IPPROTO_UDP)
6124                 return IXGBE_FILTER_PROTOCOL_UDP;
6125         else if (protocol_value == IPPROTO_SCTP)
6126                 return IXGBE_FILTER_PROTOCOL_SCTP;
6127         else
6128                 return IXGBE_FILTER_PROTOCOL_NONE;
6129 }
6130
6131 /* inject a 5-tuple filter to HW */
6132 static inline void
6133 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6134                            struct ixgbe_5tuple_filter *filter)
6135 {
6136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6137         int i;
6138         uint32_t ftqf, sdpqf;
6139         uint32_t l34timir = 0;
6140         uint8_t mask = 0xff;
6141
6142         i = filter->index;
6143
6144         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6145                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6146         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6147
6148         ftqf = (uint32_t)(filter->filter_info.proto &
6149                 IXGBE_FTQF_PROTOCOL_MASK);
6150         ftqf |= (uint32_t)((filter->filter_info.priority &
6151                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6152         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6153                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6154         if (filter->filter_info.dst_ip_mask == 0)
6155                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6156         if (filter->filter_info.src_port_mask == 0)
6157                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6158         if (filter->filter_info.dst_port_mask == 0)
6159                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6160         if (filter->filter_info.proto_mask == 0)
6161                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6162         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6163         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6164         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6165
6166         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6167         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6168         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6169         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6170
6171         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6172         l34timir |= (uint32_t)(filter->queue <<
6173                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6174         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6175 }
6176
6177 /*
6178  * add a 5tuple filter
6179  *
6180  * @param
6181  * dev: Pointer to struct rte_eth_dev.
6182  * index: the index the filter allocates.
6183  * filter: ponter to the filter that will be added.
6184  * rx_queue: the queue id the filter assigned to.
6185  *
6186  * @return
6187  *    - On success, zero.
6188  *    - On failure, a negative value.
6189  */
6190 static int
6191 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6192                         struct ixgbe_5tuple_filter *filter)
6193 {
6194         struct ixgbe_filter_info *filter_info =
6195                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6196         int i, idx, shift;
6197
6198         /*
6199          * look for an unused 5tuple filter index,
6200          * and insert the filter to list.
6201          */
6202         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6203                 idx = i / (sizeof(uint32_t) * NBBY);
6204                 shift = i % (sizeof(uint32_t) * NBBY);
6205                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6206                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6207                         filter->index = i;
6208                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6209                                           filter,
6210                                           entries);
6211                         break;
6212                 }
6213         }
6214         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6215                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6216                 return -ENOSYS;
6217         }
6218
6219         ixgbe_inject_5tuple_filter(dev, filter);
6220
6221         return 0;
6222 }
6223
6224 /*
6225  * remove a 5tuple filter
6226  *
6227  * @param
6228  * dev: Pointer to struct rte_eth_dev.
6229  * filter: the pointer of the filter will be removed.
6230  */
6231 static void
6232 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6233                         struct ixgbe_5tuple_filter *filter)
6234 {
6235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6236         struct ixgbe_filter_info *filter_info =
6237                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6238         uint16_t index = filter->index;
6239
6240         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6241                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6242         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6243         rte_free(filter);
6244
6245         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6246         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6247         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6248         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6249         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6250 }
6251
6252 static int
6253 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6254 {
6255         struct ixgbe_hw *hw;
6256         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6257         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6258
6259         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6260
6261         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6262                 return -EINVAL;
6263
6264         /* refuse mtu that requires the support of scattered packets when this
6265          * feature has not been enabled before.
6266          */
6267         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6268             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6269              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6270                 return -EINVAL;
6271
6272         /*
6273          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6274          * request of the version 2.0 of the mailbox API.
6275          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6276          * of the mailbox API.
6277          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6278          * prior to 3.11.33 which contains the following change:
6279          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6280          */
6281         ixgbevf_rlpml_set_vf(hw, max_frame);
6282
6283         /* update max frame size */
6284         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6285         return 0;
6286 }
6287
6288 static inline struct ixgbe_5tuple_filter *
6289 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6290                         struct ixgbe_5tuple_filter_info *key)
6291 {
6292         struct ixgbe_5tuple_filter *it;
6293
6294         TAILQ_FOREACH(it, filter_list, entries) {
6295                 if (memcmp(key, &it->filter_info,
6296                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6297                         return it;
6298                 }
6299         }
6300         return NULL;
6301 }
6302
6303 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6304 static inline int
6305 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6306                         struct ixgbe_5tuple_filter_info *filter_info)
6307 {
6308         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6309                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6310                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6311                 return -EINVAL;
6312
6313         switch (filter->dst_ip_mask) {
6314         case UINT32_MAX:
6315                 filter_info->dst_ip_mask = 0;
6316                 filter_info->dst_ip = filter->dst_ip;
6317                 break;
6318         case 0:
6319                 filter_info->dst_ip_mask = 1;
6320                 break;
6321         default:
6322                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6323                 return -EINVAL;
6324         }
6325
6326         switch (filter->src_ip_mask) {
6327         case UINT32_MAX:
6328                 filter_info->src_ip_mask = 0;
6329                 filter_info->src_ip = filter->src_ip;
6330                 break;
6331         case 0:
6332                 filter_info->src_ip_mask = 1;
6333                 break;
6334         default:
6335                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6336                 return -EINVAL;
6337         }
6338
6339         switch (filter->dst_port_mask) {
6340         case UINT16_MAX:
6341                 filter_info->dst_port_mask = 0;
6342                 filter_info->dst_port = filter->dst_port;
6343                 break;
6344         case 0:
6345                 filter_info->dst_port_mask = 1;
6346                 break;
6347         default:
6348                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6349                 return -EINVAL;
6350         }
6351
6352         switch (filter->src_port_mask) {
6353         case UINT16_MAX:
6354                 filter_info->src_port_mask = 0;
6355                 filter_info->src_port = filter->src_port;
6356                 break;
6357         case 0:
6358                 filter_info->src_port_mask = 1;
6359                 break;
6360         default:
6361                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6362                 return -EINVAL;
6363         }
6364
6365         switch (filter->proto_mask) {
6366         case UINT8_MAX:
6367                 filter_info->proto_mask = 0;
6368                 filter_info->proto =
6369                         convert_protocol_type(filter->proto);
6370                 break;
6371         case 0:
6372                 filter_info->proto_mask = 1;
6373                 break;
6374         default:
6375                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6376                 return -EINVAL;
6377         }
6378
6379         filter_info->priority = (uint8_t)filter->priority;
6380         return 0;
6381 }
6382
6383 /*
6384  * add or delete a ntuple filter
6385  *
6386  * @param
6387  * dev: Pointer to struct rte_eth_dev.
6388  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6389  * add: if true, add filter, if false, remove filter
6390  *
6391  * @return
6392  *    - On success, zero.
6393  *    - On failure, a negative value.
6394  */
6395 int
6396 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6397                         struct rte_eth_ntuple_filter *ntuple_filter,
6398                         bool add)
6399 {
6400         struct ixgbe_filter_info *filter_info =
6401                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6402         struct ixgbe_5tuple_filter_info filter_5tuple;
6403         struct ixgbe_5tuple_filter *filter;
6404         int ret;
6405
6406         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6407                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6408                 return -EINVAL;
6409         }
6410
6411         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6412         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6413         if (ret < 0)
6414                 return ret;
6415
6416         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6417                                          &filter_5tuple);
6418         if (filter != NULL && add) {
6419                 PMD_DRV_LOG(ERR, "filter exists.");
6420                 return -EEXIST;
6421         }
6422         if (filter == NULL && !add) {
6423                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6424                 return -ENOENT;
6425         }
6426
6427         if (add) {
6428                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6429                                 sizeof(struct ixgbe_5tuple_filter), 0);
6430                 if (filter == NULL)
6431                         return -ENOMEM;
6432                 rte_memcpy(&filter->filter_info,
6433                                  &filter_5tuple,
6434                                  sizeof(struct ixgbe_5tuple_filter_info));
6435                 filter->queue = ntuple_filter->queue;
6436                 ret = ixgbe_add_5tuple_filter(dev, filter);
6437                 if (ret < 0) {
6438                         rte_free(filter);
6439                         return ret;
6440                 }
6441         } else
6442                 ixgbe_remove_5tuple_filter(dev, filter);
6443
6444         return 0;
6445 }
6446
6447 /*
6448  * get a ntuple filter
6449  *
6450  * @param
6451  * dev: Pointer to struct rte_eth_dev.
6452  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6453  *
6454  * @return
6455  *    - On success, zero.
6456  *    - On failure, a negative value.
6457  */
6458 static int
6459 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6460                         struct rte_eth_ntuple_filter *ntuple_filter)
6461 {
6462         struct ixgbe_filter_info *filter_info =
6463                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6464         struct ixgbe_5tuple_filter_info filter_5tuple;
6465         struct ixgbe_5tuple_filter *filter;
6466         int ret;
6467
6468         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6469                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6470                 return -EINVAL;
6471         }
6472
6473         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6474         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6475         if (ret < 0)
6476                 return ret;
6477
6478         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6479                                          &filter_5tuple);
6480         if (filter == NULL) {
6481                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6482                 return -ENOENT;
6483         }
6484         ntuple_filter->queue = filter->queue;
6485         return 0;
6486 }
6487
6488 /*
6489  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6490  * @dev: pointer to rte_eth_dev structure
6491  * @filter_op:operation will be taken.
6492  * @arg: a pointer to specific structure corresponding to the filter_op
6493  *
6494  * @return
6495  *    - On success, zero.
6496  *    - On failure, a negative value.
6497  */
6498 static int
6499 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6500                                 enum rte_filter_op filter_op,
6501                                 void *arg)
6502 {
6503         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6504         int ret;
6505
6506         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6507
6508         if (filter_op == RTE_ETH_FILTER_NOP)
6509                 return 0;
6510
6511         if (arg == NULL) {
6512                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6513                             filter_op);
6514                 return -EINVAL;
6515         }
6516
6517         switch (filter_op) {
6518         case RTE_ETH_FILTER_ADD:
6519                 ret = ixgbe_add_del_ntuple_filter(dev,
6520                         (struct rte_eth_ntuple_filter *)arg,
6521                         TRUE);
6522                 break;
6523         case RTE_ETH_FILTER_DELETE:
6524                 ret = ixgbe_add_del_ntuple_filter(dev,
6525                         (struct rte_eth_ntuple_filter *)arg,
6526                         FALSE);
6527                 break;
6528         case RTE_ETH_FILTER_GET:
6529                 ret = ixgbe_get_ntuple_filter(dev,
6530                         (struct rte_eth_ntuple_filter *)arg);
6531                 break;
6532         default:
6533                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6534                 ret = -EINVAL;
6535                 break;
6536         }
6537         return ret;
6538 }
6539
6540 int
6541 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6542                         struct rte_eth_ethertype_filter *filter,
6543                         bool add)
6544 {
6545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6546         struct ixgbe_filter_info *filter_info =
6547                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6548         uint32_t etqf = 0;
6549         uint32_t etqs = 0;
6550         int ret;
6551         struct ixgbe_ethertype_filter ethertype_filter;
6552
6553         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6554                 return -EINVAL;
6555
6556         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6557                 filter->ether_type == ETHER_TYPE_IPv6) {
6558                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6559                         " ethertype filter.", filter->ether_type);
6560                 return -EINVAL;
6561         }
6562
6563         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6564                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6565                 return -EINVAL;
6566         }
6567         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6568                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6569                 return -EINVAL;
6570         }
6571
6572         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6573         if (ret >= 0 && add) {
6574                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6575                             filter->ether_type);
6576                 return -EEXIST;
6577         }
6578         if (ret < 0 && !add) {
6579                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6580                             filter->ether_type);
6581                 return -ENOENT;
6582         }
6583
6584         if (add) {
6585                 etqf = IXGBE_ETQF_FILTER_EN;
6586                 etqf |= (uint32_t)filter->ether_type;
6587                 etqs |= (uint32_t)((filter->queue <<
6588                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6589                                     IXGBE_ETQS_RX_QUEUE);
6590                 etqs |= IXGBE_ETQS_QUEUE_EN;
6591
6592                 ethertype_filter.ethertype = filter->ether_type;
6593                 ethertype_filter.etqf = etqf;
6594                 ethertype_filter.etqs = etqs;
6595                 ethertype_filter.conf = FALSE;
6596                 ret = ixgbe_ethertype_filter_insert(filter_info,
6597                                                     &ethertype_filter);
6598                 if (ret < 0) {
6599                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6600                         return -ENOSPC;
6601                 }
6602         } else {
6603                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6604                 if (ret < 0)
6605                         return -ENOSYS;
6606         }
6607         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6608         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6609         IXGBE_WRITE_FLUSH(hw);
6610
6611         return 0;
6612 }
6613
6614 static int
6615 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6616                         struct rte_eth_ethertype_filter *filter)
6617 {
6618         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6619         struct ixgbe_filter_info *filter_info =
6620                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6621         uint32_t etqf, etqs;
6622         int ret;
6623
6624         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6625         if (ret < 0) {
6626                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6627                             filter->ether_type);
6628                 return -ENOENT;
6629         }
6630
6631         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6632         if (etqf & IXGBE_ETQF_FILTER_EN) {
6633                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6634                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6635                 filter->flags = 0;
6636                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6637                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6638                 return 0;
6639         }
6640         return -ENOENT;
6641 }
6642
6643 /*
6644  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6645  * @dev: pointer to rte_eth_dev structure
6646  * @filter_op:operation will be taken.
6647  * @arg: a pointer to specific structure corresponding to the filter_op
6648  */
6649 static int
6650 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6651                                 enum rte_filter_op filter_op,
6652                                 void *arg)
6653 {
6654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6655         int ret;
6656
6657         MAC_TYPE_FILTER_SUP(hw->mac.type);
6658
6659         if (filter_op == RTE_ETH_FILTER_NOP)
6660                 return 0;
6661
6662         if (arg == NULL) {
6663                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6664                             filter_op);
6665                 return -EINVAL;
6666         }
6667
6668         switch (filter_op) {
6669         case RTE_ETH_FILTER_ADD:
6670                 ret = ixgbe_add_del_ethertype_filter(dev,
6671                         (struct rte_eth_ethertype_filter *)arg,
6672                         TRUE);
6673                 break;
6674         case RTE_ETH_FILTER_DELETE:
6675                 ret = ixgbe_add_del_ethertype_filter(dev,
6676                         (struct rte_eth_ethertype_filter *)arg,
6677                         FALSE);
6678                 break;
6679         case RTE_ETH_FILTER_GET:
6680                 ret = ixgbe_get_ethertype_filter(dev,
6681                         (struct rte_eth_ethertype_filter *)arg);
6682                 break;
6683         default:
6684                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6685                 ret = -EINVAL;
6686                 break;
6687         }
6688         return ret;
6689 }
6690
6691 static int
6692 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6693                      enum rte_filter_type filter_type,
6694                      enum rte_filter_op filter_op,
6695                      void *arg)
6696 {
6697         int ret = 0;
6698
6699         switch (filter_type) {
6700         case RTE_ETH_FILTER_NTUPLE:
6701                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6702                 break;
6703         case RTE_ETH_FILTER_ETHERTYPE:
6704                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6705                 break;
6706         case RTE_ETH_FILTER_SYN:
6707                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6708                 break;
6709         case RTE_ETH_FILTER_FDIR:
6710                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6711                 break;
6712         case RTE_ETH_FILTER_L2_TUNNEL:
6713                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6714                 break;
6715         case RTE_ETH_FILTER_GENERIC:
6716                 if (filter_op != RTE_ETH_FILTER_GET)
6717                         return -EINVAL;
6718                 *(const void **)arg = &ixgbe_flow_ops;
6719                 break;
6720         default:
6721                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6722                                                         filter_type);
6723                 ret = -EINVAL;
6724                 break;
6725         }
6726
6727         return ret;
6728 }
6729
6730 static u8 *
6731 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6732                         u8 **mc_addr_ptr, u32 *vmdq)
6733 {
6734         u8 *mc_addr;
6735
6736         *vmdq = 0;
6737         mc_addr = *mc_addr_ptr;
6738         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6739         return mc_addr;
6740 }
6741
6742 static int
6743 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6744                           struct ether_addr *mc_addr_set,
6745                           uint32_t nb_mc_addr)
6746 {
6747         struct ixgbe_hw *hw;
6748         u8 *mc_addr_list;
6749
6750         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6751         mc_addr_list = (u8 *)mc_addr_set;
6752         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6753                                          ixgbe_dev_addr_list_itr, TRUE);
6754 }
6755
6756 static uint64_t
6757 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6758 {
6759         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6760         uint64_t systime_cycles;
6761
6762         switch (hw->mac.type) {
6763         case ixgbe_mac_X550:
6764         case ixgbe_mac_X550EM_x:
6765         case ixgbe_mac_X550EM_a:
6766                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6767                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6768                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6769                                 * NSEC_PER_SEC;
6770                 break;
6771         default:
6772                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6773                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6774                                 << 32;
6775         }
6776
6777         return systime_cycles;
6778 }
6779
6780 static uint64_t
6781 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6782 {
6783         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6784         uint64_t rx_tstamp_cycles;
6785
6786         switch (hw->mac.type) {
6787         case ixgbe_mac_X550:
6788         case ixgbe_mac_X550EM_x:
6789         case ixgbe_mac_X550EM_a:
6790                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6791                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6792                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6793                                 * NSEC_PER_SEC;
6794                 break;
6795         default:
6796                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6797                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6798                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6799                                 << 32;
6800         }
6801
6802         return rx_tstamp_cycles;
6803 }
6804
6805 static uint64_t
6806 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6807 {
6808         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6809         uint64_t tx_tstamp_cycles;
6810
6811         switch (hw->mac.type) {
6812         case ixgbe_mac_X550:
6813         case ixgbe_mac_X550EM_x:
6814         case ixgbe_mac_X550EM_a:
6815                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6816                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6817                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6818                                 * NSEC_PER_SEC;
6819                 break;
6820         default:
6821                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6822                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6823                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6824                                 << 32;
6825         }
6826
6827         return tx_tstamp_cycles;
6828 }
6829
6830 static void
6831 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6832 {
6833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6834         struct ixgbe_adapter *adapter =
6835                 (struct ixgbe_adapter *)dev->data->dev_private;
6836         struct rte_eth_link link;
6837         uint32_t incval = 0;
6838         uint32_t shift = 0;
6839
6840         /* Get current link speed. */
6841         ixgbe_dev_link_update(dev, 1);
6842         rte_eth_linkstatus_get(dev, &link);
6843
6844         switch (link.link_speed) {
6845         case ETH_SPEED_NUM_100M:
6846                 incval = IXGBE_INCVAL_100;
6847                 shift = IXGBE_INCVAL_SHIFT_100;
6848                 break;
6849         case ETH_SPEED_NUM_1G:
6850                 incval = IXGBE_INCVAL_1GB;
6851                 shift = IXGBE_INCVAL_SHIFT_1GB;
6852                 break;
6853         case ETH_SPEED_NUM_10G:
6854         default:
6855                 incval = IXGBE_INCVAL_10GB;
6856                 shift = IXGBE_INCVAL_SHIFT_10GB;
6857                 break;
6858         }
6859
6860         switch (hw->mac.type) {
6861         case ixgbe_mac_X550:
6862         case ixgbe_mac_X550EM_x:
6863         case ixgbe_mac_X550EM_a:
6864                 /* Independent of link speed. */
6865                 incval = 1;
6866                 /* Cycles read will be interpreted as ns. */
6867                 shift = 0;
6868                 /* Fall-through */
6869         case ixgbe_mac_X540:
6870                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6871                 break;
6872         case ixgbe_mac_82599EB:
6873                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6874                 shift -= IXGBE_INCVAL_SHIFT_82599;
6875                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6876                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6877                 break;
6878         default:
6879                 /* Not supported. */
6880                 return;
6881         }
6882
6883         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6884         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6885         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6886
6887         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6888         adapter->systime_tc.cc_shift = shift;
6889         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6890
6891         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6892         adapter->rx_tstamp_tc.cc_shift = shift;
6893         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6894
6895         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6896         adapter->tx_tstamp_tc.cc_shift = shift;
6897         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6898 }
6899
6900 static int
6901 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6902 {
6903         struct ixgbe_adapter *adapter =
6904                         (struct ixgbe_adapter *)dev->data->dev_private;
6905
6906         adapter->systime_tc.nsec += delta;
6907         adapter->rx_tstamp_tc.nsec += delta;
6908         adapter->tx_tstamp_tc.nsec += delta;
6909
6910         return 0;
6911 }
6912
6913 static int
6914 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6915 {
6916         uint64_t ns;
6917         struct ixgbe_adapter *adapter =
6918                         (struct ixgbe_adapter *)dev->data->dev_private;
6919
6920         ns = rte_timespec_to_ns(ts);
6921         /* Set the timecounters to a new value. */
6922         adapter->systime_tc.nsec = ns;
6923         adapter->rx_tstamp_tc.nsec = ns;
6924         adapter->tx_tstamp_tc.nsec = ns;
6925
6926         return 0;
6927 }
6928
6929 static int
6930 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6931 {
6932         uint64_t ns, systime_cycles;
6933         struct ixgbe_adapter *adapter =
6934                         (struct ixgbe_adapter *)dev->data->dev_private;
6935
6936         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6937         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6938         *ts = rte_ns_to_timespec(ns);
6939
6940         return 0;
6941 }
6942
6943 static int
6944 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6945 {
6946         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6947         uint32_t tsync_ctl;
6948         uint32_t tsauxc;
6949
6950         /* Stop the timesync system time. */
6951         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6952         /* Reset the timesync system time value. */
6953         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6954         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6955
6956         /* Enable system time for platforms where it isn't on by default. */
6957         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6958         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6959         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6960
6961         ixgbe_start_timecounters(dev);
6962
6963         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6964         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6965                         (ETHER_TYPE_1588 |
6966                          IXGBE_ETQF_FILTER_EN |
6967                          IXGBE_ETQF_1588));
6968
6969         /* Enable timestamping of received PTP packets. */
6970         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6971         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6972         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6973
6974         /* Enable timestamping of transmitted PTP packets. */
6975         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6976         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6977         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6978
6979         IXGBE_WRITE_FLUSH(hw);
6980
6981         return 0;
6982 }
6983
6984 static int
6985 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6986 {
6987         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6988         uint32_t tsync_ctl;
6989
6990         /* Disable timestamping of transmitted PTP packets. */
6991         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6992         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6993         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6994
6995         /* Disable timestamping of received PTP packets. */
6996         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6997         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6998         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6999
7000         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7001         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7002
7003         /* Stop incrementating the System Time registers. */
7004         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7005
7006         return 0;
7007 }
7008
7009 static int
7010 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7011                                  struct timespec *timestamp,
7012                                  uint32_t flags __rte_unused)
7013 {
7014         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7015         struct ixgbe_adapter *adapter =
7016                 (struct ixgbe_adapter *)dev->data->dev_private;
7017         uint32_t tsync_rxctl;
7018         uint64_t rx_tstamp_cycles;
7019         uint64_t ns;
7020
7021         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7022         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7023                 return -EINVAL;
7024
7025         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7026         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7027         *timestamp = rte_ns_to_timespec(ns);
7028
7029         return  0;
7030 }
7031
7032 static int
7033 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7034                                  struct timespec *timestamp)
7035 {
7036         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7037         struct ixgbe_adapter *adapter =
7038                 (struct ixgbe_adapter *)dev->data->dev_private;
7039         uint32_t tsync_txctl;
7040         uint64_t tx_tstamp_cycles;
7041         uint64_t ns;
7042
7043         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7044         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7045                 return -EINVAL;
7046
7047         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7048         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7049         *timestamp = rte_ns_to_timespec(ns);
7050
7051         return 0;
7052 }
7053
7054 static int
7055 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7056 {
7057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7058         int count = 0;
7059         int g_ind = 0;
7060         const struct reg_info *reg_group;
7061         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7062                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7063
7064         while ((reg_group = reg_set[g_ind++]))
7065                 count += ixgbe_regs_group_count(reg_group);
7066
7067         return count;
7068 }
7069
7070 static int
7071 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7072 {
7073         int count = 0;
7074         int g_ind = 0;
7075         const struct reg_info *reg_group;
7076
7077         while ((reg_group = ixgbevf_regs[g_ind++]))
7078                 count += ixgbe_regs_group_count(reg_group);
7079
7080         return count;
7081 }
7082
7083 static int
7084 ixgbe_get_regs(struct rte_eth_dev *dev,
7085               struct rte_dev_reg_info *regs)
7086 {
7087         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7088         uint32_t *data = regs->data;
7089         int g_ind = 0;
7090         int count = 0;
7091         const struct reg_info *reg_group;
7092         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7093                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7094
7095         if (data == NULL) {
7096                 regs->length = ixgbe_get_reg_length(dev);
7097                 regs->width = sizeof(uint32_t);
7098                 return 0;
7099         }
7100
7101         /* Support only full register dump */
7102         if ((regs->length == 0) ||
7103             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7104                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7105                         hw->device_id;
7106                 while ((reg_group = reg_set[g_ind++]))
7107                         count += ixgbe_read_regs_group(dev, &data[count],
7108                                 reg_group);
7109                 return 0;
7110         }
7111
7112         return -ENOTSUP;
7113 }
7114
7115 static int
7116 ixgbevf_get_regs(struct rte_eth_dev *dev,
7117                 struct rte_dev_reg_info *regs)
7118 {
7119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7120         uint32_t *data = regs->data;
7121         int g_ind = 0;
7122         int count = 0;
7123         const struct reg_info *reg_group;
7124
7125         if (data == NULL) {
7126                 regs->length = ixgbevf_get_reg_length(dev);
7127                 regs->width = sizeof(uint32_t);
7128                 return 0;
7129         }
7130
7131         /* Support only full register dump */
7132         if ((regs->length == 0) ||
7133             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7134                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7135                         hw->device_id;
7136                 while ((reg_group = ixgbevf_regs[g_ind++]))
7137                         count += ixgbe_read_regs_group(dev, &data[count],
7138                                                       reg_group);
7139                 return 0;
7140         }
7141
7142         return -ENOTSUP;
7143 }
7144
7145 static int
7146 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7147 {
7148         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7149
7150         /* Return unit is byte count */
7151         return hw->eeprom.word_size * 2;
7152 }
7153
7154 static int
7155 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7156                 struct rte_dev_eeprom_info *in_eeprom)
7157 {
7158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7159         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7160         uint16_t *data = in_eeprom->data;
7161         int first, length;
7162
7163         first = in_eeprom->offset >> 1;
7164         length = in_eeprom->length >> 1;
7165         if ((first > hw->eeprom.word_size) ||
7166             ((first + length) > hw->eeprom.word_size))
7167                 return -EINVAL;
7168
7169         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7170
7171         return eeprom->ops.read_buffer(hw, first, length, data);
7172 }
7173
7174 static int
7175 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7176                 struct rte_dev_eeprom_info *in_eeprom)
7177 {
7178         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7179         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7180         uint16_t *data = in_eeprom->data;
7181         int first, length;
7182
7183         first = in_eeprom->offset >> 1;
7184         length = in_eeprom->length >> 1;
7185         if ((first > hw->eeprom.word_size) ||
7186             ((first + length) > hw->eeprom.word_size))
7187                 return -EINVAL;
7188
7189         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7190
7191         return eeprom->ops.write_buffer(hw,  first, length, data);
7192 }
7193
7194 static int
7195 ixgbe_get_module_info(struct rte_eth_dev *dev,
7196                       struct rte_eth_dev_module_info *modinfo)
7197 {
7198         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7199         uint32_t status;
7200         uint8_t sff8472_rev, addr_mode;
7201         bool page_swap = false;
7202
7203         /* Check whether we support SFF-8472 or not */
7204         status = hw->phy.ops.read_i2c_eeprom(hw,
7205                                              IXGBE_SFF_SFF_8472_COMP,
7206                                              &sff8472_rev);
7207         if (status != 0)
7208                 return -EIO;
7209
7210         /* addressing mode is not supported */
7211         status = hw->phy.ops.read_i2c_eeprom(hw,
7212                                              IXGBE_SFF_SFF_8472_SWAP,
7213                                              &addr_mode);
7214         if (status != 0)
7215                 return -EIO;
7216
7217         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7218                 PMD_DRV_LOG(ERR,
7219                             "Address change required to access page 0xA2, "
7220                             "but not supported. Please report the module "
7221                             "type to the driver maintainers.");
7222                 page_swap = true;
7223         }
7224
7225         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7226                 /* We have a SFP, but it does not support SFF-8472 */
7227                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7228                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7229         } else {
7230                 /* We have a SFP which supports a revision of SFF-8472. */
7231                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7232                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7233         }
7234
7235         return 0;
7236 }
7237
7238 static int
7239 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7240                         struct rte_dev_eeprom_info *info)
7241 {
7242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7243         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7244         uint8_t databyte = 0xFF;
7245         uint8_t *data = info->data;
7246         uint32_t i = 0;
7247
7248         if (info->length == 0)
7249                 return -EINVAL;
7250
7251         for (i = info->offset; i < info->offset + info->length; i++) {
7252                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7253                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7254                 else
7255                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7256
7257                 if (status != 0)
7258                         return -EIO;
7259
7260                 data[i - info->offset] = databyte;
7261         }
7262
7263         return 0;
7264 }
7265
7266 uint16_t
7267 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7268         switch (mac_type) {
7269         case ixgbe_mac_X550:
7270         case ixgbe_mac_X550EM_x:
7271         case ixgbe_mac_X550EM_a:
7272                 return ETH_RSS_RETA_SIZE_512;
7273         case ixgbe_mac_X550_vf:
7274         case ixgbe_mac_X550EM_x_vf:
7275         case ixgbe_mac_X550EM_a_vf:
7276                 return ETH_RSS_RETA_SIZE_64;
7277         default:
7278                 return ETH_RSS_RETA_SIZE_128;
7279         }
7280 }
7281
7282 uint32_t
7283 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7284         switch (mac_type) {
7285         case ixgbe_mac_X550:
7286         case ixgbe_mac_X550EM_x:
7287         case ixgbe_mac_X550EM_a:
7288                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7289                         return IXGBE_RETA(reta_idx >> 2);
7290                 else
7291                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7292         case ixgbe_mac_X550_vf:
7293         case ixgbe_mac_X550EM_x_vf:
7294         case ixgbe_mac_X550EM_a_vf:
7295                 return IXGBE_VFRETA(reta_idx >> 2);
7296         default:
7297                 return IXGBE_RETA(reta_idx >> 2);
7298         }
7299 }
7300
7301 uint32_t
7302 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7303         switch (mac_type) {
7304         case ixgbe_mac_X550_vf:
7305         case ixgbe_mac_X550EM_x_vf:
7306         case ixgbe_mac_X550EM_a_vf:
7307                 return IXGBE_VFMRQC;
7308         default:
7309                 return IXGBE_MRQC;
7310         }
7311 }
7312
7313 uint32_t
7314 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7315         switch (mac_type) {
7316         case ixgbe_mac_X550_vf:
7317         case ixgbe_mac_X550EM_x_vf:
7318         case ixgbe_mac_X550EM_a_vf:
7319                 return IXGBE_VFRSSRK(i);
7320         default:
7321                 return IXGBE_RSSRK(i);
7322         }
7323 }
7324
7325 bool
7326 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7327         switch (mac_type) {
7328         case ixgbe_mac_82599_vf:
7329         case ixgbe_mac_X540_vf:
7330                 return 0;
7331         default:
7332                 return 1;
7333         }
7334 }
7335
7336 static int
7337 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7338                         struct rte_eth_dcb_info *dcb_info)
7339 {
7340         struct ixgbe_dcb_config *dcb_config =
7341                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7342         struct ixgbe_dcb_tc_config *tc;
7343         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7344         uint8_t nb_tcs;
7345         uint8_t i, j;
7346
7347         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7348                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7349         else
7350                 dcb_info->nb_tcs = 1;
7351
7352         tc_queue = &dcb_info->tc_queue;
7353         nb_tcs = dcb_info->nb_tcs;
7354
7355         if (dcb_config->vt_mode) { /* vt is enabled*/
7356                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7357                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7358                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7359                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7360                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7361                         for (j = 0; j < nb_tcs; j++) {
7362                                 tc_queue->tc_rxq[0][j].base = j;
7363                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7364                                 tc_queue->tc_txq[0][j].base = j;
7365                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7366                         }
7367                 } else {
7368                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7369                                 for (j = 0; j < nb_tcs; j++) {
7370                                         tc_queue->tc_rxq[i][j].base =
7371                                                 i * nb_tcs + j;
7372                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7373                                         tc_queue->tc_txq[i][j].base =
7374                                                 i * nb_tcs + j;
7375                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7376                                 }
7377                         }
7378                 }
7379         } else { /* vt is disabled*/
7380                 struct rte_eth_dcb_rx_conf *rx_conf =
7381                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7382                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7383                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7384                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7385                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7386                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7387                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7388                         }
7389                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7390                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7391                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7392                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7393                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7394                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7395                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7396                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7397                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7398                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7399                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7400                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7401                         }
7402                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7403                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7404                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7405                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7406                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7407                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7408                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7409                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7410                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7411                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7412                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7413                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7414                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7415                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7416                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7417                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7418                 }
7419         }
7420         for (i = 0; i < dcb_info->nb_tcs; i++) {
7421                 tc = &dcb_config->tc_config[i];
7422                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7423         }
7424         return 0;
7425 }
7426
7427 /* Update e-tag ether type */
7428 static int
7429 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7430                             uint16_t ether_type)
7431 {
7432         uint32_t etag_etype;
7433
7434         if (hw->mac.type != ixgbe_mac_X550 &&
7435             hw->mac.type != ixgbe_mac_X550EM_x &&
7436             hw->mac.type != ixgbe_mac_X550EM_a) {
7437                 return -ENOTSUP;
7438         }
7439
7440         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7441         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7442         etag_etype |= ether_type;
7443         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7444         IXGBE_WRITE_FLUSH(hw);
7445
7446         return 0;
7447 }
7448
7449 /* Config l2 tunnel ether type */
7450 static int
7451 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7452                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7453 {
7454         int ret = 0;
7455         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7456         struct ixgbe_l2_tn_info *l2_tn_info =
7457                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7458
7459         if (l2_tunnel == NULL)
7460                 return -EINVAL;
7461
7462         switch (l2_tunnel->l2_tunnel_type) {
7463         case RTE_L2_TUNNEL_TYPE_E_TAG:
7464                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7465                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7466                 break;
7467         default:
7468                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7469                 ret = -EINVAL;
7470                 break;
7471         }
7472
7473         return ret;
7474 }
7475
7476 /* Enable e-tag tunnel */
7477 static int
7478 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7479 {
7480         uint32_t etag_etype;
7481
7482         if (hw->mac.type != ixgbe_mac_X550 &&
7483             hw->mac.type != ixgbe_mac_X550EM_x &&
7484             hw->mac.type != ixgbe_mac_X550EM_a) {
7485                 return -ENOTSUP;
7486         }
7487
7488         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7489         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7490         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7491         IXGBE_WRITE_FLUSH(hw);
7492
7493         return 0;
7494 }
7495
7496 /* Enable l2 tunnel */
7497 static int
7498 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7499                            enum rte_eth_tunnel_type l2_tunnel_type)
7500 {
7501         int ret = 0;
7502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7503         struct ixgbe_l2_tn_info *l2_tn_info =
7504                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7505
7506         switch (l2_tunnel_type) {
7507         case RTE_L2_TUNNEL_TYPE_E_TAG:
7508                 l2_tn_info->e_tag_en = TRUE;
7509                 ret = ixgbe_e_tag_enable(hw);
7510                 break;
7511         default:
7512                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7513                 ret = -EINVAL;
7514                 break;
7515         }
7516
7517         return ret;
7518 }
7519
7520 /* Disable e-tag tunnel */
7521 static int
7522 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7523 {
7524         uint32_t etag_etype;
7525
7526         if (hw->mac.type != ixgbe_mac_X550 &&
7527             hw->mac.type != ixgbe_mac_X550EM_x &&
7528             hw->mac.type != ixgbe_mac_X550EM_a) {
7529                 return -ENOTSUP;
7530         }
7531
7532         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7533         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7534         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7535         IXGBE_WRITE_FLUSH(hw);
7536
7537         return 0;
7538 }
7539
7540 /* Disable l2 tunnel */
7541 static int
7542 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7543                             enum rte_eth_tunnel_type l2_tunnel_type)
7544 {
7545         int ret = 0;
7546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7547         struct ixgbe_l2_tn_info *l2_tn_info =
7548                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7549
7550         switch (l2_tunnel_type) {
7551         case RTE_L2_TUNNEL_TYPE_E_TAG:
7552                 l2_tn_info->e_tag_en = FALSE;
7553                 ret = ixgbe_e_tag_disable(hw);
7554                 break;
7555         default:
7556                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7557                 ret = -EINVAL;
7558                 break;
7559         }
7560
7561         return ret;
7562 }
7563
7564 static int
7565 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7566                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7567 {
7568         int ret = 0;
7569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7570         uint32_t i, rar_entries;
7571         uint32_t rar_low, rar_high;
7572
7573         if (hw->mac.type != ixgbe_mac_X550 &&
7574             hw->mac.type != ixgbe_mac_X550EM_x &&
7575             hw->mac.type != ixgbe_mac_X550EM_a) {
7576                 return -ENOTSUP;
7577         }
7578
7579         rar_entries = ixgbe_get_num_rx_addrs(hw);
7580
7581         for (i = 1; i < rar_entries; i++) {
7582                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7583                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7584                 if ((rar_high & IXGBE_RAH_AV) &&
7585                     (rar_high & IXGBE_RAH_ADTYPE) &&
7586                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7587                      l2_tunnel->tunnel_id)) {
7588                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7589                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7590
7591                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7592
7593                         return ret;
7594                 }
7595         }
7596
7597         return ret;
7598 }
7599
7600 static int
7601 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7602                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7603 {
7604         int ret = 0;
7605         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7606         uint32_t i, rar_entries;
7607         uint32_t rar_low, rar_high;
7608
7609         if (hw->mac.type != ixgbe_mac_X550 &&
7610             hw->mac.type != ixgbe_mac_X550EM_x &&
7611             hw->mac.type != ixgbe_mac_X550EM_a) {
7612                 return -ENOTSUP;
7613         }
7614
7615         /* One entry for one tunnel. Try to remove potential existing entry. */
7616         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7617
7618         rar_entries = ixgbe_get_num_rx_addrs(hw);
7619
7620         for (i = 1; i < rar_entries; i++) {
7621                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7622                 if (rar_high & IXGBE_RAH_AV) {
7623                         continue;
7624                 } else {
7625                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7626                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7627                         rar_low = l2_tunnel->tunnel_id;
7628
7629                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7630                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7631
7632                         return ret;
7633                 }
7634         }
7635
7636         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7637                      " Please remove a rule before adding a new one.");
7638         return -EINVAL;
7639 }
7640
7641 static inline struct ixgbe_l2_tn_filter *
7642 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7643                           struct ixgbe_l2_tn_key *key)
7644 {
7645         int ret;
7646
7647         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7648         if (ret < 0)
7649                 return NULL;
7650
7651         return l2_tn_info->hash_map[ret];
7652 }
7653
7654 static inline int
7655 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7656                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7657 {
7658         int ret;
7659
7660         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7661                                &l2_tn_filter->key);
7662
7663         if (ret < 0) {
7664                 PMD_DRV_LOG(ERR,
7665                             "Failed to insert L2 tunnel filter"
7666                             " to hash table %d!",
7667                             ret);
7668                 return ret;
7669         }
7670
7671         l2_tn_info->hash_map[ret] = l2_tn_filter;
7672
7673         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7674
7675         return 0;
7676 }
7677
7678 static inline int
7679 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7680                           struct ixgbe_l2_tn_key *key)
7681 {
7682         int ret;
7683         struct ixgbe_l2_tn_filter *l2_tn_filter;
7684
7685         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7686
7687         if (ret < 0) {
7688                 PMD_DRV_LOG(ERR,
7689                             "No such L2 tunnel filter to delete %d!",
7690                             ret);
7691                 return ret;
7692         }
7693
7694         l2_tn_filter = l2_tn_info->hash_map[ret];
7695         l2_tn_info->hash_map[ret] = NULL;
7696
7697         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7698         rte_free(l2_tn_filter);
7699
7700         return 0;
7701 }
7702
7703 /* Add l2 tunnel filter */
7704 int
7705 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7706                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7707                                bool restore)
7708 {
7709         int ret;
7710         struct ixgbe_l2_tn_info *l2_tn_info =
7711                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7712         struct ixgbe_l2_tn_key key;
7713         struct ixgbe_l2_tn_filter *node;
7714
7715         if (!restore) {
7716                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7717                 key.tn_id = l2_tunnel->tunnel_id;
7718
7719                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7720
7721                 if (node) {
7722                         PMD_DRV_LOG(ERR,
7723                                     "The L2 tunnel filter already exists!");
7724                         return -EINVAL;
7725                 }
7726
7727                 node = rte_zmalloc("ixgbe_l2_tn",
7728                                    sizeof(struct ixgbe_l2_tn_filter),
7729                                    0);
7730                 if (!node)
7731                         return -ENOMEM;
7732
7733                 rte_memcpy(&node->key,
7734                                  &key,
7735                                  sizeof(struct ixgbe_l2_tn_key));
7736                 node->pool = l2_tunnel->pool;
7737                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7738                 if (ret < 0) {
7739                         rte_free(node);
7740                         return ret;
7741                 }
7742         }
7743
7744         switch (l2_tunnel->l2_tunnel_type) {
7745         case RTE_L2_TUNNEL_TYPE_E_TAG:
7746                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7747                 break;
7748         default:
7749                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7750                 ret = -EINVAL;
7751                 break;
7752         }
7753
7754         if ((!restore) && (ret < 0))
7755                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7756
7757         return ret;
7758 }
7759
7760 /* Delete l2 tunnel filter */
7761 int
7762 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7763                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7764 {
7765         int ret;
7766         struct ixgbe_l2_tn_info *l2_tn_info =
7767                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7768         struct ixgbe_l2_tn_key key;
7769
7770         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7771         key.tn_id = l2_tunnel->tunnel_id;
7772         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7773         if (ret < 0)
7774                 return ret;
7775
7776         switch (l2_tunnel->l2_tunnel_type) {
7777         case RTE_L2_TUNNEL_TYPE_E_TAG:
7778                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7779                 break;
7780         default:
7781                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7782                 ret = -EINVAL;
7783                 break;
7784         }
7785
7786         return ret;
7787 }
7788
7789 /**
7790  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7791  * @dev: pointer to rte_eth_dev structure
7792  * @filter_op:operation will be taken.
7793  * @arg: a pointer to specific structure corresponding to the filter_op
7794  */
7795 static int
7796 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7797                                   enum rte_filter_op filter_op,
7798                                   void *arg)
7799 {
7800         int ret;
7801
7802         if (filter_op == RTE_ETH_FILTER_NOP)
7803                 return 0;
7804
7805         if (arg == NULL) {
7806                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7807                             filter_op);
7808                 return -EINVAL;
7809         }
7810
7811         switch (filter_op) {
7812         case RTE_ETH_FILTER_ADD:
7813                 ret = ixgbe_dev_l2_tunnel_filter_add
7814                         (dev,
7815                          (struct rte_eth_l2_tunnel_conf *)arg,
7816                          FALSE);
7817                 break;
7818         case RTE_ETH_FILTER_DELETE:
7819                 ret = ixgbe_dev_l2_tunnel_filter_del
7820                         (dev,
7821                          (struct rte_eth_l2_tunnel_conf *)arg);
7822                 break;
7823         default:
7824                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7825                 ret = -EINVAL;
7826                 break;
7827         }
7828         return ret;
7829 }
7830
7831 static int
7832 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7833 {
7834         int ret = 0;
7835         uint32_t ctrl;
7836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7837
7838         if (hw->mac.type != ixgbe_mac_X550 &&
7839             hw->mac.type != ixgbe_mac_X550EM_x &&
7840             hw->mac.type != ixgbe_mac_X550EM_a) {
7841                 return -ENOTSUP;
7842         }
7843
7844         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7845         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7846         if (en)
7847                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7848         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7849
7850         return ret;
7851 }
7852
7853 /* Enable l2 tunnel forwarding */
7854 static int
7855 ixgbe_dev_l2_tunnel_forwarding_enable
7856         (struct rte_eth_dev *dev,
7857          enum rte_eth_tunnel_type l2_tunnel_type)
7858 {
7859         struct ixgbe_l2_tn_info *l2_tn_info =
7860                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7861         int ret = 0;
7862
7863         switch (l2_tunnel_type) {
7864         case RTE_L2_TUNNEL_TYPE_E_TAG:
7865                 l2_tn_info->e_tag_fwd_en = TRUE;
7866                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7867                 break;
7868         default:
7869                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7870                 ret = -EINVAL;
7871                 break;
7872         }
7873
7874         return ret;
7875 }
7876
7877 /* Disable l2 tunnel forwarding */
7878 static int
7879 ixgbe_dev_l2_tunnel_forwarding_disable
7880         (struct rte_eth_dev *dev,
7881          enum rte_eth_tunnel_type l2_tunnel_type)
7882 {
7883         struct ixgbe_l2_tn_info *l2_tn_info =
7884                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7885         int ret = 0;
7886
7887         switch (l2_tunnel_type) {
7888         case RTE_L2_TUNNEL_TYPE_E_TAG:
7889                 l2_tn_info->e_tag_fwd_en = FALSE;
7890                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7891                 break;
7892         default:
7893                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7894                 ret = -EINVAL;
7895                 break;
7896         }
7897
7898         return ret;
7899 }
7900
7901 static int
7902 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7903                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7904                              bool en)
7905 {
7906         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7907         int ret = 0;
7908         uint32_t vmtir, vmvir;
7909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7910
7911         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7912                 PMD_DRV_LOG(ERR,
7913                             "VF id %u should be less than %u",
7914                             l2_tunnel->vf_id,
7915                             pci_dev->max_vfs);
7916                 return -EINVAL;
7917         }
7918
7919         if (hw->mac.type != ixgbe_mac_X550 &&
7920             hw->mac.type != ixgbe_mac_X550EM_x &&
7921             hw->mac.type != ixgbe_mac_X550EM_a) {
7922                 return -ENOTSUP;
7923         }
7924
7925         if (en)
7926                 vmtir = l2_tunnel->tunnel_id;
7927         else
7928                 vmtir = 0;
7929
7930         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7931
7932         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7933         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7934         if (en)
7935                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7936         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7937
7938         return ret;
7939 }
7940
7941 /* Enable l2 tunnel tag insertion */
7942 static int
7943 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7944                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7945 {
7946         int ret = 0;
7947
7948         switch (l2_tunnel->l2_tunnel_type) {
7949         case RTE_L2_TUNNEL_TYPE_E_TAG:
7950                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7951                 break;
7952         default:
7953                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7954                 ret = -EINVAL;
7955                 break;
7956         }
7957
7958         return ret;
7959 }
7960
7961 /* Disable l2 tunnel tag insertion */
7962 static int
7963 ixgbe_dev_l2_tunnel_insertion_disable
7964         (struct rte_eth_dev *dev,
7965          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7966 {
7967         int ret = 0;
7968
7969         switch (l2_tunnel->l2_tunnel_type) {
7970         case RTE_L2_TUNNEL_TYPE_E_TAG:
7971                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7972                 break;
7973         default:
7974                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7975                 ret = -EINVAL;
7976                 break;
7977         }
7978
7979         return ret;
7980 }
7981
7982 static int
7983 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7984                              bool en)
7985 {
7986         int ret = 0;
7987         uint32_t qde;
7988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7989
7990         if (hw->mac.type != ixgbe_mac_X550 &&
7991             hw->mac.type != ixgbe_mac_X550EM_x &&
7992             hw->mac.type != ixgbe_mac_X550EM_a) {
7993                 return -ENOTSUP;
7994         }
7995
7996         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7997         if (en)
7998                 qde |= IXGBE_QDE_STRIP_TAG;
7999         else
8000                 qde &= ~IXGBE_QDE_STRIP_TAG;
8001         qde &= ~IXGBE_QDE_READ;
8002         qde |= IXGBE_QDE_WRITE;
8003         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8004
8005         return ret;
8006 }
8007
8008 /* Enable l2 tunnel tag stripping */
8009 static int
8010 ixgbe_dev_l2_tunnel_stripping_enable
8011         (struct rte_eth_dev *dev,
8012          enum rte_eth_tunnel_type l2_tunnel_type)
8013 {
8014         int ret = 0;
8015
8016         switch (l2_tunnel_type) {
8017         case RTE_L2_TUNNEL_TYPE_E_TAG:
8018                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8019                 break;
8020         default:
8021                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8022                 ret = -EINVAL;
8023                 break;
8024         }
8025
8026         return ret;
8027 }
8028
8029 /* Disable l2 tunnel tag stripping */
8030 static int
8031 ixgbe_dev_l2_tunnel_stripping_disable
8032         (struct rte_eth_dev *dev,
8033          enum rte_eth_tunnel_type l2_tunnel_type)
8034 {
8035         int ret = 0;
8036
8037         switch (l2_tunnel_type) {
8038         case RTE_L2_TUNNEL_TYPE_E_TAG:
8039                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8040                 break;
8041         default:
8042                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8043                 ret = -EINVAL;
8044                 break;
8045         }
8046
8047         return ret;
8048 }
8049
8050 /* Enable/disable l2 tunnel offload functions */
8051 static int
8052 ixgbe_dev_l2_tunnel_offload_set
8053         (struct rte_eth_dev *dev,
8054          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8055          uint32_t mask,
8056          uint8_t en)
8057 {
8058         int ret = 0;
8059
8060         if (l2_tunnel == NULL)
8061                 return -EINVAL;
8062
8063         ret = -EINVAL;
8064         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8065                 if (en)
8066                         ret = ixgbe_dev_l2_tunnel_enable(
8067                                 dev,
8068                                 l2_tunnel->l2_tunnel_type);
8069                 else
8070                         ret = ixgbe_dev_l2_tunnel_disable(
8071                                 dev,
8072                                 l2_tunnel->l2_tunnel_type);
8073         }
8074
8075         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8076                 if (en)
8077                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8078                                 dev,
8079                                 l2_tunnel);
8080                 else
8081                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8082                                 dev,
8083                                 l2_tunnel);
8084         }
8085
8086         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8087                 if (en)
8088                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8089                                 dev,
8090                                 l2_tunnel->l2_tunnel_type);
8091                 else
8092                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8093                                 dev,
8094                                 l2_tunnel->l2_tunnel_type);
8095         }
8096
8097         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8098                 if (en)
8099                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8100                                 dev,
8101                                 l2_tunnel->l2_tunnel_type);
8102                 else
8103                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8104                                 dev,
8105                                 l2_tunnel->l2_tunnel_type);
8106         }
8107
8108         return ret;
8109 }
8110
8111 static int
8112 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8113                         uint16_t port)
8114 {
8115         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8116         IXGBE_WRITE_FLUSH(hw);
8117
8118         return 0;
8119 }
8120
8121 /* There's only one register for VxLAN UDP port.
8122  * So, we cannot add several ports. Will update it.
8123  */
8124 static int
8125 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8126                      uint16_t port)
8127 {
8128         if (port == 0) {
8129                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8130                 return -EINVAL;
8131         }
8132
8133         return ixgbe_update_vxlan_port(hw, port);
8134 }
8135
8136 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8137  * UDP port, it must have a value.
8138  * So, will reset it to the original value 0.
8139  */
8140 static int
8141 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8142                      uint16_t port)
8143 {
8144         uint16_t cur_port;
8145
8146         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8147
8148         if (cur_port != port) {
8149                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8150                 return -EINVAL;
8151         }
8152
8153         return ixgbe_update_vxlan_port(hw, 0);
8154 }
8155
8156 /* Add UDP tunneling port */
8157 static int
8158 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8159                               struct rte_eth_udp_tunnel *udp_tunnel)
8160 {
8161         int ret = 0;
8162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8163
8164         if (hw->mac.type != ixgbe_mac_X550 &&
8165             hw->mac.type != ixgbe_mac_X550EM_x &&
8166             hw->mac.type != ixgbe_mac_X550EM_a) {
8167                 return -ENOTSUP;
8168         }
8169
8170         if (udp_tunnel == NULL)
8171                 return -EINVAL;
8172
8173         switch (udp_tunnel->prot_type) {
8174         case RTE_TUNNEL_TYPE_VXLAN:
8175                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8176                 break;
8177
8178         case RTE_TUNNEL_TYPE_GENEVE:
8179         case RTE_TUNNEL_TYPE_TEREDO:
8180                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8181                 ret = -EINVAL;
8182                 break;
8183
8184         default:
8185                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8186                 ret = -EINVAL;
8187                 break;
8188         }
8189
8190         return ret;
8191 }
8192
8193 /* Remove UDP tunneling port */
8194 static int
8195 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8196                               struct rte_eth_udp_tunnel *udp_tunnel)
8197 {
8198         int ret = 0;
8199         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8200
8201         if (hw->mac.type != ixgbe_mac_X550 &&
8202             hw->mac.type != ixgbe_mac_X550EM_x &&
8203             hw->mac.type != ixgbe_mac_X550EM_a) {
8204                 return -ENOTSUP;
8205         }
8206
8207         if (udp_tunnel == NULL)
8208                 return -EINVAL;
8209
8210         switch (udp_tunnel->prot_type) {
8211         case RTE_TUNNEL_TYPE_VXLAN:
8212                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8213                 break;
8214         case RTE_TUNNEL_TYPE_GENEVE:
8215         case RTE_TUNNEL_TYPE_TEREDO:
8216                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8217                 ret = -EINVAL;
8218                 break;
8219         default:
8220                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8221                 ret = -EINVAL;
8222                 break;
8223         }
8224
8225         return ret;
8226 }
8227
8228 static void
8229 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8230 {
8231         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8232
8233         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8234 }
8235
8236 static void
8237 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8238 {
8239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8240
8241         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8242 }
8243
8244 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8245 {
8246         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8247         u32 in_msg = 0;
8248
8249         /* peek the message first */
8250         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8251
8252         /* PF reset VF event */
8253         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8254                 /* dummy mbx read to ack pf */
8255                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8256                         return;
8257                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8258                                               NULL);
8259         }
8260 }
8261
8262 static int
8263 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8264 {
8265         uint32_t eicr;
8266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8267         struct ixgbe_interrupt *intr =
8268                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8269         ixgbevf_intr_disable(hw);
8270
8271         /* read-on-clear nic registers here */
8272         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8273         intr->flags = 0;
8274
8275         /* only one misc vector supported - mailbox */
8276         eicr &= IXGBE_VTEICR_MASK;
8277         if (eicr == IXGBE_MISC_VEC_ID)
8278                 intr->flags |= IXGBE_FLAG_MAILBOX;
8279
8280         return 0;
8281 }
8282
8283 static int
8284 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8285 {
8286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8287         struct ixgbe_interrupt *intr =
8288                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8289
8290         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8291                 ixgbevf_mbx_process(dev);
8292                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8293         }
8294
8295         ixgbevf_intr_enable(hw);
8296
8297         return 0;
8298 }
8299
8300 static void
8301 ixgbevf_dev_interrupt_handler(void *param)
8302 {
8303         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8304
8305         ixgbevf_dev_interrupt_get_status(dev);
8306         ixgbevf_dev_interrupt_action(dev);
8307 }
8308
8309 /**
8310  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8311  *  @hw: pointer to hardware structure
8312  *
8313  *  Stops the transmit data path and waits for the HW to internally empty
8314  *  the Tx security block
8315  **/
8316 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8317 {
8318 #define IXGBE_MAX_SECTX_POLL 40
8319
8320         int i;
8321         int sectxreg;
8322
8323         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8324         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8325         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8326         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8327                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8328                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8329                         break;
8330                 /* Use interrupt-safe sleep just in case */
8331                 usec_delay(1000);
8332         }
8333
8334         /* For informational purposes only */
8335         if (i >= IXGBE_MAX_SECTX_POLL)
8336                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8337                          "path fully disabled.  Continuing with init.");
8338
8339         return IXGBE_SUCCESS;
8340 }
8341
8342 /**
8343  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8344  *  @hw: pointer to hardware structure
8345  *
8346  *  Enables the transmit data path.
8347  **/
8348 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8349 {
8350         uint32_t sectxreg;
8351
8352         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8353         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8354         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8355         IXGBE_WRITE_FLUSH(hw);
8356
8357         return IXGBE_SUCCESS;
8358 }
8359
8360 /* restore n-tuple filter */
8361 static inline void
8362 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8363 {
8364         struct ixgbe_filter_info *filter_info =
8365                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8366         struct ixgbe_5tuple_filter *node;
8367
8368         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8369                 ixgbe_inject_5tuple_filter(dev, node);
8370         }
8371 }
8372
8373 /* restore ethernet type filter */
8374 static inline void
8375 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8376 {
8377         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8378         struct ixgbe_filter_info *filter_info =
8379                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8380         int i;
8381
8382         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8383                 if (filter_info->ethertype_mask & (1 << i)) {
8384                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8385                                         filter_info->ethertype_filters[i].etqf);
8386                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8387                                         filter_info->ethertype_filters[i].etqs);
8388                         IXGBE_WRITE_FLUSH(hw);
8389                 }
8390         }
8391 }
8392
8393 /* restore SYN filter */
8394 static inline void
8395 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8396 {
8397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8398         struct ixgbe_filter_info *filter_info =
8399                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8400         uint32_t synqf;
8401
8402         synqf = filter_info->syn_info;
8403
8404         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8405                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8406                 IXGBE_WRITE_FLUSH(hw);
8407         }
8408 }
8409
8410 /* restore L2 tunnel filter */
8411 static inline void
8412 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8413 {
8414         struct ixgbe_l2_tn_info *l2_tn_info =
8415                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8416         struct ixgbe_l2_tn_filter *node;
8417         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8418
8419         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8420                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8421                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8422                 l2_tn_conf.pool           = node->pool;
8423                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8424         }
8425 }
8426
8427 /* restore rss filter */
8428 static inline void
8429 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8430 {
8431         struct ixgbe_filter_info *filter_info =
8432                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8433
8434         if (filter_info->rss_info.conf.queue_num)
8435                 ixgbe_config_rss_filter(dev,
8436                         &filter_info->rss_info, TRUE);
8437 }
8438
8439 static int
8440 ixgbe_filter_restore(struct rte_eth_dev *dev)
8441 {
8442         ixgbe_ntuple_filter_restore(dev);
8443         ixgbe_ethertype_filter_restore(dev);
8444         ixgbe_syn_filter_restore(dev);
8445         ixgbe_fdir_filter_restore(dev);
8446         ixgbe_l2_tn_filter_restore(dev);
8447         ixgbe_rss_filter_restore(dev);
8448
8449         return 0;
8450 }
8451
8452 static void
8453 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8454 {
8455         struct ixgbe_l2_tn_info *l2_tn_info =
8456                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8458
8459         if (l2_tn_info->e_tag_en)
8460                 (void)ixgbe_e_tag_enable(hw);
8461
8462         if (l2_tn_info->e_tag_fwd_en)
8463                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8464
8465         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8466 }
8467
8468 /* remove all the n-tuple filters */
8469 void
8470 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8471 {
8472         struct ixgbe_filter_info *filter_info =
8473                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8474         struct ixgbe_5tuple_filter *p_5tuple;
8475
8476         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8477                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8478 }
8479
8480 /* remove all the ether type filters */
8481 void
8482 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8483 {
8484         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8485         struct ixgbe_filter_info *filter_info =
8486                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8487         int i;
8488
8489         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8490                 if (filter_info->ethertype_mask & (1 << i) &&
8491                     !filter_info->ethertype_filters[i].conf) {
8492                         (void)ixgbe_ethertype_filter_remove(filter_info,
8493                                                             (uint8_t)i);
8494                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8495                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8496                         IXGBE_WRITE_FLUSH(hw);
8497                 }
8498         }
8499 }
8500
8501 /* remove the SYN filter */
8502 void
8503 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8504 {
8505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8506         struct ixgbe_filter_info *filter_info =
8507                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8508
8509         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8510                 filter_info->syn_info = 0;
8511
8512                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8513                 IXGBE_WRITE_FLUSH(hw);
8514         }
8515 }
8516
8517 /* remove all the L2 tunnel filters */
8518 int
8519 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8520 {
8521         struct ixgbe_l2_tn_info *l2_tn_info =
8522                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8523         struct ixgbe_l2_tn_filter *l2_tn_filter;
8524         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8525         int ret = 0;
8526
8527         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8528                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8529                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8530                 l2_tn_conf.pool           = l2_tn_filter->pool;
8531                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8532                 if (ret < 0)
8533                         return ret;
8534         }
8535
8536         return 0;
8537 }
8538
8539 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8540 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8541 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8542 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8543 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8544 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8545
8546 RTE_INIT(ixgbe_init_log);
8547 static void
8548 ixgbe_init_log(void)
8549 {
8550         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8551         if (ixgbe_logtype_init >= 0)
8552                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8553         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8554         if (ixgbe_logtype_driver >= 0)
8555                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8556 }