1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_kvargs.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_hash_crc.h>
36 #ifdef RTE_LIBRTE_SECURITY
37 #include <rte_security_driver.h>
40 #include "ixgbe_logs.h"
41 #include "base/ixgbe_api.h"
42 #include "base/ixgbe_vf.h"
43 #include "base/ixgbe_common.h"
44 #include "ixgbe_ethdev.h"
45 #include "ixgbe_bypass.h"
46 #include "ixgbe_rxtx.h"
47 #include "base/ixgbe_type.h"
48 #include "base/ixgbe_phy.h"
49 #include "ixgbe_regs.h"
52 * High threshold controlling when to start sending XOFF frames. Must be at
53 * least 8 bytes less than receive packet buffer size. This value is in units
56 #define IXGBE_FC_HI 0x80
59 * Low threshold controlling when to start sending XON frames. This value is
60 * in units of 1024 bytes.
62 #define IXGBE_FC_LO 0x40
64 /* Timer value included in XOFF frames. */
65 #define IXGBE_FC_PAUSE 0x680
67 /*Default value of Max Rx Queue*/
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
71 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
72 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
74 #define IXGBE_MMW_SIZE_DEFAULT 0x4
75 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
76 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
79 * Default values for RX/TX configuration
81 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
82 #define IXGBE_DEFAULT_RX_PTHRESH 8
83 #define IXGBE_DEFAULT_RX_HTHRESH 8
84 #define IXGBE_DEFAULT_RX_WTHRESH 0
86 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
87 #define IXGBE_DEFAULT_TX_PTHRESH 32
88 #define IXGBE_DEFAULT_TX_HTHRESH 0
89 #define IXGBE_DEFAULT_TX_WTHRESH 0
90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
92 /* Bit shift and mask */
93 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
94 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
95 #define IXGBE_8_BIT_WIDTH CHAR_BIT
96 #define IXGBE_8_BIT_MASK UINT8_MAX
98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
102 /* Additional timesync values. */
103 #define NSEC_PER_SEC 1000000000L
104 #define IXGBE_INCVAL_10GB 0x66666666
105 #define IXGBE_INCVAL_1GB 0x40000000
106 #define IXGBE_INCVAL_100 0x50000000
107 #define IXGBE_INCVAL_SHIFT_10GB 28
108 #define IXGBE_INCVAL_SHIFT_1GB 24
109 #define IXGBE_INCVAL_SHIFT_100 21
110 #define IXGBE_INCVAL_SHIFT_82599 7
111 #define IXGBE_INCPER_SHIFT_82599 24
113 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
117 #define IXGBE_ETAG_ETYPE 0x00005084
118 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
119 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
120 #define IXGBE_RAH_ADTYPE 0x40000000
121 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
122 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
125 #define IXGBE_QDE_STRIP_TAG 0x00000004
126 #define IXGBE_VTEICR_MASK 0x07
128 #define IXGBE_EXVET_VET_EXT_SHIFT 16
129 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK "pflink_fullchk"
133 static const char * const ixgbevf_valid_arguments[] = {
134 IXGBEVF_DEVARG_PFLINK_FULLCHK,
138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
157 int wait_to_complete);
158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
161 struct rte_eth_xstat *xstats, unsigned n);
162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
163 struct rte_eth_xstat *xstats, unsigned n);
165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
166 uint64_t *values, unsigned int n);
167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names,
172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names, unsigned limit);
174 static int ixgbe_dev_xstats_get_names_by_id(
175 struct rte_eth_dev *dev,
176 struct rte_eth_xstat_name *xstats_names,
179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
189 struct rte_eth_dev_info *dev_info);
190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
193 uint16_t vlan_id, int on);
194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
195 enum rte_vlan_type vlan_type,
197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
198 uint16_t queue, bool on);
199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
213 struct rte_eth_fc_conf *fc_conf);
214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
215 struct rte_eth_fc_conf *fc_conf);
216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
217 struct rte_eth_pfc_conf *pfc_conf);
218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
219 struct rte_eth_rss_reta_entry64 *reta_conf,
221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
222 struct rte_eth_rss_reta_entry64 *reta_conf,
224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
230 static void ixgbe_dev_interrupt_handler(void *param);
231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
235 struct rte_ether_addr *mac_addr,
236 uint32_t index, uint32_t pool);
237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
239 struct rte_ether_addr *mac_addr);
240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
241 static bool is_device_supported(struct rte_eth_dev *dev,
242 struct rte_pci_driver *drv);
244 /* For Virtual Function support */
245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
247 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
248 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
250 int wait_to_complete);
251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
253 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
260 uint16_t vlan_id, int on);
261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
262 uint16_t queue, int on);
263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
271 uint8_t queue, uint8_t msix_vector);
272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
278 /* For Eth VMDQ APIs support */
279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
280 rte_ether_addr * mac_addr, uint8_t on);
281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
283 struct rte_eth_mirror_conf *mirror_conf,
284 uint8_t rule_id, uint8_t on);
285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
292 uint8_t queue, uint8_t msix_vector);
293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
296 struct rte_ether_addr *mac_addr,
297 uint32_t index, uint32_t pool);
298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
300 struct rte_ether_addr *mac_addr);
301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
302 struct rte_eth_syn_filter *filter);
303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
304 enum rte_filter_op filter_op,
306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
307 struct ixgbe_5tuple_filter *filter);
308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
309 struct ixgbe_5tuple_filter *filter);
310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
311 enum rte_filter_op filter_op,
313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
314 struct rte_eth_ntuple_filter *filter);
315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
316 enum rte_filter_op filter_op,
318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
319 struct rte_eth_ethertype_filter *filter);
320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
321 enum rte_filter_type filter_type,
322 enum rte_filter_op filter_op,
324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
327 struct rte_ether_addr *mc_addr_set,
328 uint32_t nb_mc_addr);
329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
334 struct rte_dev_reg_info *regs);
335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
337 struct rte_dev_eeprom_info *eeprom);
338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
339 struct rte_dev_eeprom_info *eeprom);
341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
342 struct rte_eth_dev_module_info *modinfo);
343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
344 struct rte_dev_eeprom_info *info);
346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
353 struct timespec *timestamp,
355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
359 struct timespec *timestamp);
360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
361 const struct timespec *timestamp);
362 static void ixgbevf_dev_interrupt_handler(void *param);
364 static int ixgbe_dev_l2_tunnel_eth_type_conf
365 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
366 static int ixgbe_dev_l2_tunnel_offload_set
367 (struct rte_eth_dev *dev,
368 struct rte_eth_l2_tunnel_conf *l2_tunnel,
371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
372 enum rte_filter_op filter_op,
375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
376 struct rte_eth_udp_tunnel *udp_tunnel);
377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
383 * Define VF Stats MACRO for Non "cleared on read" register
385 #define UPDATE_VF_STAT(reg, last, cur) \
387 uint32_t latest = IXGBE_READ_REG(hw, reg); \
388 cur += (latest - last) & UINT_MAX; \
392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
394 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
395 u64 new_msb = IXGBE_READ_REG(hw, msb); \
396 u64 latest = ((new_msb << 32) | new_lsb); \
397 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
401 #define IXGBE_SET_HWSTRIP(h, q) do {\
402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
404 (h)->bitmap[idx] |= 1 << bit;\
407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
410 (h)->bitmap[idx] &= ~(1 << bit);\
413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
416 (r) = (h)->bitmap[idx] >> bit & 1;\
419 int ixgbe_logtype_init;
420 int ixgbe_logtype_driver;
422 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
423 int ixgbe_logtype_rx;
425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
426 int ixgbe_logtype_tx;
428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
429 int ixgbe_logtype_tx_free;
433 * The set of PCI devices this driver supports
435 static const struct rte_pci_id pci_id_ixgbe_map[] = {
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
487 { .vendor_id = 0, /* sentinel */ },
491 * The set of PCI devices this driver supports (for 82599 VF)
493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
504 { .vendor_id = 0, /* sentinel */ },
507 static const struct rte_eth_desc_lim rx_desc_lim = {
508 .nb_max = IXGBE_MAX_RING_DESC,
509 .nb_min = IXGBE_MIN_RING_DESC,
510 .nb_align = IXGBE_RXD_ALIGN,
513 static const struct rte_eth_desc_lim tx_desc_lim = {
514 .nb_max = IXGBE_MAX_RING_DESC,
515 .nb_min = IXGBE_MIN_RING_DESC,
516 .nb_align = IXGBE_TXD_ALIGN,
517 .nb_seg_max = IXGBE_TX_MAX_SEG,
518 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
522 .dev_configure = ixgbe_dev_configure,
523 .dev_start = ixgbe_dev_start,
524 .dev_stop = ixgbe_dev_stop,
525 .dev_set_link_up = ixgbe_dev_set_link_up,
526 .dev_set_link_down = ixgbe_dev_set_link_down,
527 .dev_close = ixgbe_dev_close,
528 .dev_reset = ixgbe_dev_reset,
529 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
530 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
531 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
532 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
533 .link_update = ixgbe_dev_link_update,
534 .stats_get = ixgbe_dev_stats_get,
535 .xstats_get = ixgbe_dev_xstats_get,
536 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
537 .stats_reset = ixgbe_dev_stats_reset,
538 .xstats_reset = ixgbe_dev_xstats_reset,
539 .xstats_get_names = ixgbe_dev_xstats_get_names,
540 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
541 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
542 .fw_version_get = ixgbe_fw_version_get,
543 .dev_infos_get = ixgbe_dev_info_get,
544 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
545 .mtu_set = ixgbe_dev_mtu_set,
546 .vlan_filter_set = ixgbe_vlan_filter_set,
547 .vlan_tpid_set = ixgbe_vlan_tpid_set,
548 .vlan_offload_set = ixgbe_vlan_offload_set,
549 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
550 .rx_queue_start = ixgbe_dev_rx_queue_start,
551 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
552 .tx_queue_start = ixgbe_dev_tx_queue_start,
553 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
554 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
555 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
556 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
557 .rx_queue_release = ixgbe_dev_rx_queue_release,
558 .rx_queue_count = ixgbe_dev_rx_queue_count,
559 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
560 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
561 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
562 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
563 .tx_queue_release = ixgbe_dev_tx_queue_release,
564 .dev_led_on = ixgbe_dev_led_on,
565 .dev_led_off = ixgbe_dev_led_off,
566 .flow_ctrl_get = ixgbe_flow_ctrl_get,
567 .flow_ctrl_set = ixgbe_flow_ctrl_set,
568 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
569 .mac_addr_add = ixgbe_add_rar,
570 .mac_addr_remove = ixgbe_remove_rar,
571 .mac_addr_set = ixgbe_set_default_mac_addr,
572 .uc_hash_table_set = ixgbe_uc_hash_table_set,
573 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
574 .mirror_rule_set = ixgbe_mirror_rule_set,
575 .mirror_rule_reset = ixgbe_mirror_rule_reset,
576 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
577 .reta_update = ixgbe_dev_rss_reta_update,
578 .reta_query = ixgbe_dev_rss_reta_query,
579 .rss_hash_update = ixgbe_dev_rss_hash_update,
580 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
581 .filter_ctrl = ixgbe_dev_filter_ctrl,
582 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
583 .rxq_info_get = ixgbe_rxq_info_get,
584 .txq_info_get = ixgbe_txq_info_get,
585 .timesync_enable = ixgbe_timesync_enable,
586 .timesync_disable = ixgbe_timesync_disable,
587 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
588 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
589 .get_reg = ixgbe_get_regs,
590 .get_eeprom_length = ixgbe_get_eeprom_length,
591 .get_eeprom = ixgbe_get_eeprom,
592 .set_eeprom = ixgbe_set_eeprom,
593 .get_module_info = ixgbe_get_module_info,
594 .get_module_eeprom = ixgbe_get_module_eeprom,
595 .get_dcb_info = ixgbe_dev_get_dcb_info,
596 .timesync_adjust_time = ixgbe_timesync_adjust_time,
597 .timesync_read_time = ixgbe_timesync_read_time,
598 .timesync_write_time = ixgbe_timesync_write_time,
599 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
600 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
601 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
602 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
603 .tm_ops_get = ixgbe_tm_ops_get,
607 * dev_ops for virtual function, bare necessities for basic vf
608 * operation have been implemented
610 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
611 .dev_configure = ixgbevf_dev_configure,
612 .dev_start = ixgbevf_dev_start,
613 .dev_stop = ixgbevf_dev_stop,
614 .link_update = ixgbevf_dev_link_update,
615 .stats_get = ixgbevf_dev_stats_get,
616 .xstats_get = ixgbevf_dev_xstats_get,
617 .stats_reset = ixgbevf_dev_stats_reset,
618 .xstats_reset = ixgbevf_dev_stats_reset,
619 .xstats_get_names = ixgbevf_dev_xstats_get_names,
620 .dev_close = ixgbevf_dev_close,
621 .dev_reset = ixgbevf_dev_reset,
622 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
623 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
624 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
625 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
626 .dev_infos_get = ixgbevf_dev_info_get,
627 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
628 .mtu_set = ixgbevf_dev_set_mtu,
629 .vlan_filter_set = ixgbevf_vlan_filter_set,
630 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
631 .vlan_offload_set = ixgbevf_vlan_offload_set,
632 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
633 .rx_queue_release = ixgbe_dev_rx_queue_release,
634 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
635 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
636 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
637 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
638 .tx_queue_release = ixgbe_dev_tx_queue_release,
639 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
640 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
641 .mac_addr_add = ixgbevf_add_mac_addr,
642 .mac_addr_remove = ixgbevf_remove_mac_addr,
643 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
644 .rxq_info_get = ixgbe_rxq_info_get,
645 .txq_info_get = ixgbe_txq_info_get,
646 .mac_addr_set = ixgbevf_set_default_mac_addr,
647 .get_reg = ixgbevf_get_regs,
648 .reta_update = ixgbe_dev_rss_reta_update,
649 .reta_query = ixgbe_dev_rss_reta_query,
650 .rss_hash_update = ixgbe_dev_rss_hash_update,
651 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
654 /* store statistics names and its offset in stats structure */
655 struct rte_ixgbe_xstats_name_off {
656 char name[RTE_ETH_XSTATS_NAME_SIZE];
660 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
661 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
662 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
663 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
664 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
665 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
666 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
667 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
668 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
669 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
670 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
671 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
672 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
673 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
674 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
675 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
677 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
679 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
680 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
681 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
682 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
683 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
684 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
685 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
686 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
687 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
688 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
689 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
690 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
691 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
692 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
693 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
694 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
695 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
697 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
699 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
700 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
701 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
702 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
704 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
708 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
710 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
712 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
714 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
717 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
718 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
719 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
721 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
722 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
723 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
724 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
725 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
727 {"rx_fcoe_no_direct_data_placement_ext_buff",
728 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
730 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
732 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
734 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
736 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
738 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
741 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
742 sizeof(rte_ixgbe_stats_strings[0]))
744 /* MACsec statistics */
745 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
746 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
748 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
749 out_pkts_encrypted)},
750 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
751 out_pkts_protected)},
752 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
753 out_octets_encrypted)},
754 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
755 out_octets_protected)},
756 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
758 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
760 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
763 in_pkts_unknownsci)},
764 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
765 in_octets_decrypted)},
766 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
767 in_octets_validated)},
768 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
778 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
780 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
782 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
783 in_pkts_notusingsa)},
786 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
787 sizeof(rte_ixgbe_macsec_strings[0]))
789 /* Per-queue statistics */
790 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
791 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
792 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
793 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
794 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
797 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
798 sizeof(rte_ixgbe_rxq_strings[0]))
799 #define IXGBE_NB_RXQ_PRIO_VALUES 8
801 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
802 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
803 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
804 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
808 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
809 sizeof(rte_ixgbe_txq_strings[0]))
810 #define IXGBE_NB_TXQ_PRIO_VALUES 8
812 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
813 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
816 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
817 sizeof(rte_ixgbevf_stats_strings[0]))
820 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
823 ixgbe_is_sfp(struct ixgbe_hw *hw)
825 switch (hw->phy.type) {
826 case ixgbe_phy_sfp_avago:
827 case ixgbe_phy_sfp_ftl:
828 case ixgbe_phy_sfp_intel:
829 case ixgbe_phy_sfp_unknown:
830 case ixgbe_phy_sfp_passive_tyco:
831 case ixgbe_phy_sfp_passive_unknown:
838 static inline int32_t
839 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
844 status = ixgbe_reset_hw(hw);
846 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
847 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
848 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
849 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
850 IXGBE_WRITE_FLUSH(hw);
852 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
853 status = IXGBE_SUCCESS;
858 ixgbe_enable_intr(struct rte_eth_dev *dev)
860 struct ixgbe_interrupt *intr =
861 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
862 struct ixgbe_hw *hw =
863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
865 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
866 IXGBE_WRITE_FLUSH(hw);
870 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
873 ixgbe_disable_intr(struct ixgbe_hw *hw)
875 PMD_INIT_FUNC_TRACE();
877 if (hw->mac.type == ixgbe_mac_82598EB) {
878 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
880 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
881 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
882 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
884 IXGBE_WRITE_FLUSH(hw);
888 * This function resets queue statistics mapping registers.
889 * From Niantic datasheet, Initialization of Statistics section:
890 * "...if software requires the queue counters, the RQSMR and TQSM registers
891 * must be re-programmed following a device reset.
894 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
898 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
899 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
900 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
906 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
911 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
912 #define NB_QMAP_FIELDS_PER_QSM_REG 4
913 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
915 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
916 struct ixgbe_stat_mapping_registers *stat_mappings =
917 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
918 uint32_t qsmr_mask = 0;
919 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
923 if ((hw->mac.type != ixgbe_mac_82599EB) &&
924 (hw->mac.type != ixgbe_mac_X540) &&
925 (hw->mac.type != ixgbe_mac_X550) &&
926 (hw->mac.type != ixgbe_mac_X550EM_x) &&
927 (hw->mac.type != ixgbe_mac_X550EM_a))
930 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
931 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
934 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
935 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
936 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
939 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
941 /* Now clear any previous stat_idx set */
942 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
944 stat_mappings->tqsm[n] &= ~clearing_mask;
946 stat_mappings->rqsmr[n] &= ~clearing_mask;
948 q_map = (uint32_t)stat_idx;
949 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
950 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
952 stat_mappings->tqsm[n] |= qsmr_mask;
954 stat_mappings->rqsmr[n] |= qsmr_mask;
956 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
957 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
959 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
960 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
962 /* Now write the mapping in the appropriate register */
964 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
965 stat_mappings->rqsmr[n], n);
966 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
968 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
969 stat_mappings->tqsm[n], n);
970 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
976 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
978 struct ixgbe_stat_mapping_registers *stat_mappings =
979 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
983 /* write whatever was in stat mapping table to the NIC */
984 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
986 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
989 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
994 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
997 struct ixgbe_dcb_tc_config *tc;
998 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1000 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1001 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1002 for (i = 0; i < dcb_max_tc; i++) {
1003 tc = &dcb_config->tc_config[i];
1004 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1005 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1006 (uint8_t)(100/dcb_max_tc + (i & 1));
1007 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1008 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1009 (uint8_t)(100/dcb_max_tc + (i & 1));
1010 tc->pfc = ixgbe_dcb_pfc_disabled;
1013 /* Initialize default user to priority mapping, UPx->TC0 */
1014 tc = &dcb_config->tc_config[0];
1015 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1016 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1017 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1018 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1019 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1021 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1022 dcb_config->pfc_mode_enable = false;
1023 dcb_config->vt_mode = true;
1024 dcb_config->round_robin_enable = false;
1025 /* support all DCB capabilities in 82599 */
1026 dcb_config->support.capabilities = 0xFF;
1028 /*we only support 4 Tcs for X540, X550 */
1029 if (hw->mac.type == ixgbe_mac_X540 ||
1030 hw->mac.type == ixgbe_mac_X550 ||
1031 hw->mac.type == ixgbe_mac_X550EM_x ||
1032 hw->mac.type == ixgbe_mac_X550EM_a) {
1033 dcb_config->num_tcs.pg_tcs = 4;
1034 dcb_config->num_tcs.pfc_tcs = 4;
1039 * Ensure that all locks are released before first NVM or PHY access
1042 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1047 * Phy lock should not fail in this early stage. If this is the case,
1048 * it is due to an improper exit of the application.
1049 * So force the release of the faulty lock. Release of common lock
1050 * is done automatically by swfw_sync function.
1052 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1053 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1054 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1056 ixgbe_release_swfw_semaphore(hw, mask);
1059 * These ones are more tricky since they are common to all ports; but
1060 * swfw_sync retries last long enough (1s) to be almost sure that if
1061 * lock can not be taken it is due to an improper lock of the
1064 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1065 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1066 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1068 ixgbe_release_swfw_semaphore(hw, mask);
1072 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1073 * It returns 0 on success.
1076 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1078 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1079 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1080 struct ixgbe_hw *hw =
1081 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1082 struct ixgbe_vfta *shadow_vfta =
1083 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1084 struct ixgbe_hwstrip *hwstrip =
1085 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1086 struct ixgbe_dcb_config *dcb_config =
1087 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1088 struct ixgbe_filter_info *filter_info =
1089 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1090 struct ixgbe_bw_conf *bw_conf =
1091 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1096 PMD_INIT_FUNC_TRACE();
1098 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1099 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1100 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1101 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1104 * For secondary processes, we don't initialise any further as primary
1105 * has already done this work. Only check we don't need a different
1106 * RX and TX function.
1108 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1109 struct ixgbe_tx_queue *txq;
1110 /* TX queue function in primary, set by last queue initialized
1111 * Tx queue may not initialized by primary process
1113 if (eth_dev->data->tx_queues) {
1114 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1115 ixgbe_set_tx_function(eth_dev, txq);
1117 /* Use default TX function if we get here */
1118 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1119 "Using default TX function.");
1122 ixgbe_set_rx_function(eth_dev);
1127 rte_eth_copy_pci_info(eth_dev, pci_dev);
1129 /* Vendor and Device ID need to be set before init of shared code */
1130 hw->device_id = pci_dev->id.device_id;
1131 hw->vendor_id = pci_dev->id.vendor_id;
1132 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1133 hw->allow_unsupported_sfp = 1;
1135 /* Initialize the shared code (base driver) */
1136 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1137 diag = ixgbe_bypass_init_shared_code(hw);
1139 diag = ixgbe_init_shared_code(hw);
1140 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1142 if (diag != IXGBE_SUCCESS) {
1143 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1147 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1148 PMD_INIT_LOG(ERR, "\nERROR: "
1149 "Firmware recovery mode detected. Limiting functionality.\n"
1150 "Refer to the Intel(R) Ethernet Adapters and Devices "
1151 "User Guide for details on firmware recovery mode.");
1155 /* pick up the PCI bus settings for reporting later */
1156 ixgbe_get_bus_info(hw);
1158 /* Unlock any pending hardware semaphore */
1159 ixgbe_swfw_lock_reset(hw);
1161 #ifdef RTE_LIBRTE_SECURITY
1162 /* Initialize security_ctx only for primary process*/
1163 if (ixgbe_ipsec_ctx_create(eth_dev))
1167 /* Initialize DCB configuration*/
1168 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1169 ixgbe_dcb_init(hw, dcb_config);
1170 /* Get Hardware Flow Control setting */
1171 hw->fc.requested_mode = ixgbe_fc_full;
1172 hw->fc.current_mode = ixgbe_fc_full;
1173 hw->fc.pause_time = IXGBE_FC_PAUSE;
1174 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1175 hw->fc.low_water[i] = IXGBE_FC_LO;
1176 hw->fc.high_water[i] = IXGBE_FC_HI;
1178 hw->fc.send_xon = 1;
1180 /* Make sure we have a good EEPROM before we read from it */
1181 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1182 if (diag != IXGBE_SUCCESS) {
1183 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1187 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1188 diag = ixgbe_bypass_init_hw(hw);
1190 diag = ixgbe_init_hw(hw);
1191 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1194 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1195 * is called too soon after the kernel driver unbinding/binding occurs.
1196 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1197 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1198 * also called. See ixgbe_identify_phy_82599(). The reason for the
1199 * failure is not known, and only occuts when virtualisation features
1200 * are disabled in the bios. A delay of 100ms was found to be enough by
1201 * trial-and-error, and is doubled to be safe.
1203 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1205 diag = ixgbe_init_hw(hw);
1208 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1209 diag = IXGBE_SUCCESS;
1211 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1212 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1213 "LOM. Please be aware there may be issues associated "
1214 "with your hardware.");
1215 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1216 "please contact your Intel or hardware representative "
1217 "who provided you with this hardware.");
1218 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1219 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1221 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1225 /* Reset the hw statistics */
1226 ixgbe_dev_stats_reset(eth_dev);
1228 /* disable interrupt */
1229 ixgbe_disable_intr(hw);
1231 /* reset mappings for queue statistics hw counters*/
1232 ixgbe_reset_qstat_mappings(hw);
1234 /* Allocate memory for storing MAC addresses */
1235 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1236 hw->mac.num_rar_entries, 0);
1237 if (eth_dev->data->mac_addrs == NULL) {
1239 "Failed to allocate %u bytes needed to store "
1241 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1244 /* Copy the permanent MAC address */
1245 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1246 ð_dev->data->mac_addrs[0]);
1248 /* Allocate memory for storing hash filter MAC addresses */
1249 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1250 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1251 if (eth_dev->data->hash_mac_addrs == NULL) {
1253 "Failed to allocate %d bytes needed to store MAC addresses",
1254 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1258 /* Pass the information to the rte_eth_dev_close() that it should also
1259 * release the private port resources.
1261 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1263 /* initialize the vfta */
1264 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1266 /* initialize the hw strip bitmap*/
1267 memset(hwstrip, 0, sizeof(*hwstrip));
1269 /* initialize PF if max_vfs not zero */
1270 ixgbe_pf_host_init(eth_dev);
1272 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1273 /* let hardware know driver is loaded */
1274 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1275 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1276 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1277 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1278 IXGBE_WRITE_FLUSH(hw);
1280 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1281 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1282 (int) hw->mac.type, (int) hw->phy.type,
1283 (int) hw->phy.sfp_type);
1285 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1286 (int) hw->mac.type, (int) hw->phy.type);
1288 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1289 eth_dev->data->port_id, pci_dev->id.vendor_id,
1290 pci_dev->id.device_id);
1292 rte_intr_callback_register(intr_handle,
1293 ixgbe_dev_interrupt_handler, eth_dev);
1295 /* enable uio/vfio intr/eventfd mapping */
1296 rte_intr_enable(intr_handle);
1298 /* enable support intr */
1299 ixgbe_enable_intr(eth_dev);
1301 /* initialize filter info */
1302 memset(filter_info, 0,
1303 sizeof(struct ixgbe_filter_info));
1305 /* initialize 5tuple filter list */
1306 TAILQ_INIT(&filter_info->fivetuple_list);
1308 /* initialize flow director filter list & hash */
1309 ixgbe_fdir_filter_init(eth_dev);
1311 /* initialize l2 tunnel filter list & hash */
1312 ixgbe_l2_tn_filter_init(eth_dev);
1314 /* initialize flow filter lists */
1315 ixgbe_filterlist_init();
1317 /* initialize bandwidth configuration info */
1318 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1320 /* initialize Traffic Manager configuration */
1321 ixgbe_tm_conf_init(eth_dev);
1327 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1329 PMD_INIT_FUNC_TRACE();
1331 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1334 ixgbe_dev_close(eth_dev);
1339 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1341 struct ixgbe_filter_info *filter_info =
1342 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1343 struct ixgbe_5tuple_filter *p_5tuple;
1345 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1346 TAILQ_REMOVE(&filter_info->fivetuple_list,
1351 memset(filter_info->fivetuple_mask, 0,
1352 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1357 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1359 struct ixgbe_hw_fdir_info *fdir_info =
1360 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1361 struct ixgbe_fdir_filter *fdir_filter;
1363 if (fdir_info->hash_map)
1364 rte_free(fdir_info->hash_map);
1365 if (fdir_info->hash_handle)
1366 rte_hash_free(fdir_info->hash_handle);
1368 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1369 TAILQ_REMOVE(&fdir_info->fdir_list,
1372 rte_free(fdir_filter);
1378 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1380 struct ixgbe_l2_tn_info *l2_tn_info =
1381 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1382 struct ixgbe_l2_tn_filter *l2_tn_filter;
1384 if (l2_tn_info->hash_map)
1385 rte_free(l2_tn_info->hash_map);
1386 if (l2_tn_info->hash_handle)
1387 rte_hash_free(l2_tn_info->hash_handle);
1389 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1390 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1393 rte_free(l2_tn_filter);
1399 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1401 struct ixgbe_hw_fdir_info *fdir_info =
1402 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1403 char fdir_hash_name[RTE_HASH_NAMESIZE];
1404 struct rte_hash_parameters fdir_hash_params = {
1405 .name = fdir_hash_name,
1406 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1407 .key_len = sizeof(union ixgbe_atr_input),
1408 .hash_func = rte_hash_crc,
1409 .hash_func_init_val = 0,
1410 .socket_id = rte_socket_id(),
1413 TAILQ_INIT(&fdir_info->fdir_list);
1414 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1415 "fdir_%s", eth_dev->device->name);
1416 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1417 if (!fdir_info->hash_handle) {
1418 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1421 fdir_info->hash_map = rte_zmalloc("ixgbe",
1422 sizeof(struct ixgbe_fdir_filter *) *
1423 IXGBE_MAX_FDIR_FILTER_NUM,
1425 if (!fdir_info->hash_map) {
1427 "Failed to allocate memory for fdir hash map!");
1430 fdir_info->mask_added = FALSE;
1435 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1437 struct ixgbe_l2_tn_info *l2_tn_info =
1438 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1439 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1440 struct rte_hash_parameters l2_tn_hash_params = {
1441 .name = l2_tn_hash_name,
1442 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1443 .key_len = sizeof(struct ixgbe_l2_tn_key),
1444 .hash_func = rte_hash_crc,
1445 .hash_func_init_val = 0,
1446 .socket_id = rte_socket_id(),
1449 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1450 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1451 "l2_tn_%s", eth_dev->device->name);
1452 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1453 if (!l2_tn_info->hash_handle) {
1454 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1457 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1458 sizeof(struct ixgbe_l2_tn_filter *) *
1459 IXGBE_MAX_L2_TN_FILTER_NUM,
1461 if (!l2_tn_info->hash_map) {
1463 "Failed to allocate memory for L2 TN hash map!");
1466 l2_tn_info->e_tag_en = FALSE;
1467 l2_tn_info->e_tag_fwd_en = FALSE;
1468 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1473 * Negotiate mailbox API version with the PF.
1474 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1475 * Then we try to negotiate starting with the most recent one.
1476 * If all negotiation attempts fail, then we will proceed with
1477 * the default one (ixgbe_mbox_api_10).
1480 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1484 /* start with highest supported, proceed down */
1485 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1493 i != RTE_DIM(sup_ver) &&
1494 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1500 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1504 /* Set Organizationally Unique Identifier (OUI) prefix. */
1505 mac_addr->addr_bytes[0] = 0x00;
1506 mac_addr->addr_bytes[1] = 0x09;
1507 mac_addr->addr_bytes[2] = 0xC0;
1508 /* Force indication of locally assigned MAC address. */
1509 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1510 /* Generate the last 3 bytes of the MAC address with a random number. */
1511 random = rte_rand();
1512 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1516 devarg_handle_int(__rte_unused const char *key, const char *value,
1519 uint16_t *n = extra_args;
1521 if (value == NULL || extra_args == NULL)
1524 *n = (uint16_t)strtoul(value, NULL, 0);
1525 if (*n == USHRT_MAX && errno == ERANGE)
1532 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1533 struct rte_devargs *devargs)
1535 struct rte_kvargs *kvlist;
1536 uint16_t pflink_fullchk;
1538 if (devargs == NULL)
1541 kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1545 if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1546 rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1547 devarg_handle_int, &pflink_fullchk) == 0 &&
1548 pflink_fullchk == 1)
1549 adapter->pflink_fullchk = 1;
1551 rte_kvargs_free(kvlist);
1555 * Virtual Function device init
1558 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564 struct ixgbe_hw *hw =
1565 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1566 struct ixgbe_vfta *shadow_vfta =
1567 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1568 struct ixgbe_hwstrip *hwstrip =
1569 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1570 struct rte_ether_addr *perm_addr =
1571 (struct rte_ether_addr *)hw->mac.perm_addr;
1573 PMD_INIT_FUNC_TRACE();
1575 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1576 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1577 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1579 /* for secondary processes, we don't initialise any further as primary
1580 * has already done this work. Only check we don't need a different
1583 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1584 struct ixgbe_tx_queue *txq;
1585 /* TX queue function in primary, set by last queue initialized
1586 * Tx queue may not initialized by primary process
1588 if (eth_dev->data->tx_queues) {
1589 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1590 ixgbe_set_tx_function(eth_dev, txq);
1592 /* Use default TX function if we get here */
1593 PMD_INIT_LOG(NOTICE,
1594 "No TX queues configured yet. Using default TX function.");
1597 ixgbe_set_rx_function(eth_dev);
1602 ixgbevf_parse_devargs(eth_dev->data->dev_private,
1603 pci_dev->device.devargs);
1605 rte_eth_copy_pci_info(eth_dev, pci_dev);
1607 hw->device_id = pci_dev->id.device_id;
1608 hw->vendor_id = pci_dev->id.vendor_id;
1609 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1611 /* initialize the vfta */
1612 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1614 /* initialize the hw strip bitmap*/
1615 memset(hwstrip, 0, sizeof(*hwstrip));
1617 /* Initialize the shared code (base driver) */
1618 diag = ixgbe_init_shared_code(hw);
1619 if (diag != IXGBE_SUCCESS) {
1620 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1624 /* init_mailbox_params */
1625 hw->mbx.ops.init_params(hw);
1627 /* Reset the hw statistics */
1628 ixgbevf_dev_stats_reset(eth_dev);
1630 /* Disable the interrupts for VF */
1631 ixgbevf_intr_disable(eth_dev);
1633 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1634 diag = hw->mac.ops.reset_hw(hw);
1637 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1638 * the underlying PF driver has not assigned a MAC address to the VF.
1639 * In this case, assign a random MAC address.
1641 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1642 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1644 * This error code will be propagated to the app by
1645 * rte_eth_dev_reset, so use a public error code rather than
1646 * the internal-only IXGBE_ERR_RESET_FAILED
1651 /* negotiate mailbox API version to use with the PF. */
1652 ixgbevf_negotiate_api(hw);
1654 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1655 ixgbevf_get_queues(hw, &tcs, &tc);
1657 /* Allocate memory for storing MAC addresses */
1658 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1659 hw->mac.num_rar_entries, 0);
1660 if (eth_dev->data->mac_addrs == NULL) {
1662 "Failed to allocate %u bytes needed to store "
1664 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1668 /* Pass the information to the rte_eth_dev_close() that it should also
1669 * release the private port resources.
1671 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1673 /* Generate a random MAC address, if none was assigned by PF. */
1674 if (rte_is_zero_ether_addr(perm_addr)) {
1675 generate_random_mac_addr(perm_addr);
1676 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1678 rte_free(eth_dev->data->mac_addrs);
1679 eth_dev->data->mac_addrs = NULL;
1682 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1683 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1684 "%02x:%02x:%02x:%02x:%02x:%02x",
1685 perm_addr->addr_bytes[0],
1686 perm_addr->addr_bytes[1],
1687 perm_addr->addr_bytes[2],
1688 perm_addr->addr_bytes[3],
1689 perm_addr->addr_bytes[4],
1690 perm_addr->addr_bytes[5]);
1693 /* Copy the permanent MAC address */
1694 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1696 /* reset the hardware with the new settings */
1697 diag = hw->mac.ops.start_hw(hw);
1703 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1707 rte_intr_callback_register(intr_handle,
1708 ixgbevf_dev_interrupt_handler, eth_dev);
1709 rte_intr_enable(intr_handle);
1710 ixgbevf_intr_enable(eth_dev);
1712 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1713 eth_dev->data->port_id, pci_dev->id.vendor_id,
1714 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1719 /* Virtual Function device uninit */
1722 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1724 PMD_INIT_FUNC_TRACE();
1726 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1729 ixgbevf_dev_close(eth_dev);
1735 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1736 struct rte_pci_device *pci_dev)
1738 char name[RTE_ETH_NAME_MAX_LEN];
1739 struct rte_eth_dev *pf_ethdev;
1740 struct rte_eth_devargs eth_da;
1743 if (pci_dev->device.devargs) {
1744 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1749 memset(ð_da, 0, sizeof(eth_da));
1751 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1752 sizeof(struct ixgbe_adapter),
1753 eth_dev_pci_specific_init, pci_dev,
1754 eth_ixgbe_dev_init, NULL);
1756 if (retval || eth_da.nb_representor_ports < 1)
1759 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1760 if (pf_ethdev == NULL)
1763 /* probe VF representor ports */
1764 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1765 struct ixgbe_vf_info *vfinfo;
1766 struct ixgbe_vf_representor representor;
1768 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1769 pf_ethdev->data->dev_private);
1770 if (vfinfo == NULL) {
1772 "no virtual functions supported by PF");
1776 representor.vf_id = eth_da.representor_ports[i];
1777 representor.switch_domain_id = vfinfo->switch_domain_id;
1778 representor.pf_ethdev = pf_ethdev;
1780 /* representor port net_bdf_port */
1781 snprintf(name, sizeof(name), "net_%s_representor_%d",
1782 pci_dev->device.name,
1783 eth_da.representor_ports[i]);
1785 retval = rte_eth_dev_create(&pci_dev->device, name,
1786 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1787 ixgbe_vf_representor_init, &representor);
1790 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1791 "representor %s.", name);
1797 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1799 struct rte_eth_dev *ethdev;
1801 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1805 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1806 return rte_eth_dev_pci_generic_remove(pci_dev,
1807 ixgbe_vf_representor_uninit);
1809 return rte_eth_dev_pci_generic_remove(pci_dev,
1810 eth_ixgbe_dev_uninit);
1813 static struct rte_pci_driver rte_ixgbe_pmd = {
1814 .id_table = pci_id_ixgbe_map,
1815 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1816 .probe = eth_ixgbe_pci_probe,
1817 .remove = eth_ixgbe_pci_remove,
1820 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1821 struct rte_pci_device *pci_dev)
1823 return rte_eth_dev_pci_generic_probe(pci_dev,
1824 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1827 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1829 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1833 * virtual function driver struct
1835 static struct rte_pci_driver rte_ixgbevf_pmd = {
1836 .id_table = pci_id_ixgbevf_map,
1837 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1838 .probe = eth_ixgbevf_pci_probe,
1839 .remove = eth_ixgbevf_pci_remove,
1843 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1845 struct ixgbe_hw *hw =
1846 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847 struct ixgbe_vfta *shadow_vfta =
1848 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1853 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1854 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1855 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1860 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1862 /* update local VFTA copy */
1863 shadow_vfta->vfta[vid_idx] = vfta;
1869 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1872 ixgbe_vlan_hw_strip_enable(dev, queue);
1874 ixgbe_vlan_hw_strip_disable(dev, queue);
1878 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1879 enum rte_vlan_type vlan_type,
1882 struct ixgbe_hw *hw =
1883 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1888 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1889 qinq &= IXGBE_DMATXCTL_GDV;
1891 switch (vlan_type) {
1892 case ETH_VLAN_TYPE_INNER:
1894 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1895 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1896 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1897 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1898 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1899 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1900 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1903 PMD_DRV_LOG(ERR, "Inner type is not supported"
1907 case ETH_VLAN_TYPE_OUTER:
1909 /* Only the high 16-bits is valid */
1910 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1911 IXGBE_EXVET_VET_EXT_SHIFT);
1913 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1914 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1915 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1916 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1917 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1918 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1919 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1925 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1933 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1935 struct ixgbe_hw *hw =
1936 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939 PMD_INIT_FUNC_TRACE();
1941 /* Filter Table Disable */
1942 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1943 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1945 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1949 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1951 struct ixgbe_hw *hw =
1952 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953 struct ixgbe_vfta *shadow_vfta =
1954 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1958 PMD_INIT_FUNC_TRACE();
1960 /* Filter Table Enable */
1961 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1962 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1963 vlnctrl |= IXGBE_VLNCTRL_VFE;
1965 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1967 /* write whatever is in local vfta copy */
1968 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1969 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1973 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1975 struct ixgbe_hwstrip *hwstrip =
1976 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1977 struct ixgbe_rx_queue *rxq;
1979 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1983 IXGBE_SET_HWSTRIP(hwstrip, queue);
1985 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1987 if (queue >= dev->data->nb_rx_queues)
1990 rxq = dev->data->rx_queues[queue];
1993 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1994 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1996 rxq->vlan_flags = PKT_RX_VLAN;
1997 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2002 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2004 struct ixgbe_hw *hw =
2005 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008 PMD_INIT_FUNC_TRACE();
2010 if (hw->mac.type == ixgbe_mac_82598EB) {
2011 /* No queue level support */
2012 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2016 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2017 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2018 ctrl &= ~IXGBE_RXDCTL_VME;
2019 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2021 /* record those setting for HW strip per queue */
2022 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2026 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2028 struct ixgbe_hw *hw =
2029 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032 PMD_INIT_FUNC_TRACE();
2034 if (hw->mac.type == ixgbe_mac_82598EB) {
2035 /* No queue level supported */
2036 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2040 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2042 ctrl |= IXGBE_RXDCTL_VME;
2043 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2045 /* record those setting for HW strip per queue */
2046 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2050 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2052 struct ixgbe_hw *hw =
2053 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056 PMD_INIT_FUNC_TRACE();
2058 /* DMATXCTRL: Geric Double VLAN Disable */
2059 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2060 ctrl &= ~IXGBE_DMATXCTL_GDV;
2061 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2063 /* CTRL_EXT: Global Double VLAN Disable */
2064 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2065 ctrl &= ~IXGBE_EXTENDED_VLAN;
2066 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2071 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2073 struct ixgbe_hw *hw =
2074 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2077 PMD_INIT_FUNC_TRACE();
2079 /* DMATXCTRL: Geric Double VLAN Enable */
2080 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2081 ctrl |= IXGBE_DMATXCTL_GDV;
2082 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2084 /* CTRL_EXT: Global Double VLAN Enable */
2085 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2086 ctrl |= IXGBE_EXTENDED_VLAN;
2087 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2089 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2090 if (hw->mac.type == ixgbe_mac_X550 ||
2091 hw->mac.type == ixgbe_mac_X550EM_x ||
2092 hw->mac.type == ixgbe_mac_X550EM_a) {
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2094 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2095 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2099 * VET EXT field in the EXVET register = 0x8100 by default
2100 * So no need to change. Same to VT field of DMATXCTL register
2105 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2107 struct ixgbe_hw *hw =
2108 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2112 struct ixgbe_rx_queue *rxq;
2115 PMD_INIT_FUNC_TRACE();
2117 if (hw->mac.type == ixgbe_mac_82598EB) {
2118 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2119 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2120 ctrl |= IXGBE_VLNCTRL_VME;
2121 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2123 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2124 ctrl &= ~IXGBE_VLNCTRL_VME;
2125 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2129 * Other 10G NIC, the VLAN strip can be setup
2130 * per queue in RXDCTL
2132 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2133 rxq = dev->data->rx_queues[i];
2134 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2135 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2136 ctrl |= IXGBE_RXDCTL_VME;
2139 ctrl &= ~IXGBE_RXDCTL_VME;
2142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2144 /* record those setting for HW strip per queue */
2145 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2151 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2154 struct rte_eth_rxmode *rxmode;
2155 struct ixgbe_rx_queue *rxq;
2157 if (mask & ETH_VLAN_STRIP_MASK) {
2158 rxmode = &dev->data->dev_conf.rxmode;
2159 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2160 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2161 rxq = dev->data->rx_queues[i];
2162 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2165 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2166 rxq = dev->data->rx_queues[i];
2167 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2173 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2175 struct rte_eth_rxmode *rxmode;
2176 rxmode = &dev->data->dev_conf.rxmode;
2178 if (mask & ETH_VLAN_STRIP_MASK) {
2179 ixgbe_vlan_hw_strip_config(dev);
2182 if (mask & ETH_VLAN_FILTER_MASK) {
2183 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2184 ixgbe_vlan_hw_filter_enable(dev);
2186 ixgbe_vlan_hw_filter_disable(dev);
2189 if (mask & ETH_VLAN_EXTEND_MASK) {
2190 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2191 ixgbe_vlan_hw_extend_enable(dev);
2193 ixgbe_vlan_hw_extend_disable(dev);
2200 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2202 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2204 ixgbe_vlan_offload_config(dev, mask);
2210 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2212 struct ixgbe_hw *hw =
2213 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2214 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2215 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2217 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2218 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2222 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2224 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2229 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2232 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2238 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2239 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2240 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2241 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2246 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2248 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2251 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2253 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2254 /* check multi-queue mode */
2255 switch (dev_conf->rxmode.mq_mode) {
2256 case ETH_MQ_RX_VMDQ_DCB:
2257 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2259 case ETH_MQ_RX_VMDQ_DCB_RSS:
2260 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2261 PMD_INIT_LOG(ERR, "SRIOV active,"
2262 " unsupported mq_mode rx %d.",
2263 dev_conf->rxmode.mq_mode);
2266 case ETH_MQ_RX_VMDQ_RSS:
2267 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2268 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2269 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2270 PMD_INIT_LOG(ERR, "SRIOV is active,"
2271 " invalid queue number"
2272 " for VMDQ RSS, allowed"
2273 " value are 1, 2 or 4.");
2277 case ETH_MQ_RX_VMDQ_ONLY:
2278 case ETH_MQ_RX_NONE:
2279 /* if nothing mq mode configure, use default scheme */
2280 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2282 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2283 /* SRIOV only works in VMDq enable mode */
2284 PMD_INIT_LOG(ERR, "SRIOV is active,"
2285 " wrong mq_mode rx %d.",
2286 dev_conf->rxmode.mq_mode);
2290 switch (dev_conf->txmode.mq_mode) {
2291 case ETH_MQ_TX_VMDQ_DCB:
2292 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2293 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2295 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2296 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2300 /* check valid queue number */
2301 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2302 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2303 PMD_INIT_LOG(ERR, "SRIOV is active,"
2304 " nb_rx_q=%d nb_tx_q=%d queue number"
2305 " must be less than or equal to %d.",
2307 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2311 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2312 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2316 /* check configuration for vmdb+dcb mode */
2317 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2318 const struct rte_eth_vmdq_dcb_conf *conf;
2320 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2321 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2322 IXGBE_VMDQ_DCB_NB_QUEUES);
2325 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2326 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2327 conf->nb_queue_pools == ETH_32_POOLS)) {
2328 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2329 " nb_queue_pools must be %d or %d.",
2330 ETH_16_POOLS, ETH_32_POOLS);
2334 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2335 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2337 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2338 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2339 IXGBE_VMDQ_DCB_NB_QUEUES);
2342 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2343 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2344 conf->nb_queue_pools == ETH_32_POOLS)) {
2345 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2346 " nb_queue_pools != %d and"
2347 " nb_queue_pools != %d.",
2348 ETH_16_POOLS, ETH_32_POOLS);
2353 /* For DCB mode check our configuration before we go further */
2354 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2355 const struct rte_eth_dcb_rx_conf *conf;
2357 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2358 if (!(conf->nb_tcs == ETH_4_TCS ||
2359 conf->nb_tcs == ETH_8_TCS)) {
2360 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2361 " and nb_tcs != %d.",
2362 ETH_4_TCS, ETH_8_TCS);
2367 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2368 const struct rte_eth_dcb_tx_conf *conf;
2370 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2371 if (!(conf->nb_tcs == ETH_4_TCS ||
2372 conf->nb_tcs == ETH_8_TCS)) {
2373 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2374 " and nb_tcs != %d.",
2375 ETH_4_TCS, ETH_8_TCS);
2381 * When DCB/VT is off, maximum number of queues changes,
2382 * except for 82598EB, which remains constant.
2384 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2385 hw->mac.type != ixgbe_mac_82598EB) {
2386 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2388 "Neither VT nor DCB are enabled, "
2390 IXGBE_NONE_MODE_TX_NB_QUEUES);
2399 ixgbe_dev_configure(struct rte_eth_dev *dev)
2401 struct ixgbe_interrupt *intr =
2402 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2403 struct ixgbe_adapter *adapter = dev->data->dev_private;
2406 PMD_INIT_FUNC_TRACE();
2408 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2410 /* multipe queue mode checking */
2411 ret = ixgbe_check_mq_mode(dev);
2413 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2418 /* set flag to update link status after init */
2419 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2422 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2423 * allocation or vector Rx preconditions we will reset it.
2425 adapter->rx_bulk_alloc_allowed = true;
2426 adapter->rx_vec_allowed = true;
2432 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2434 struct ixgbe_hw *hw =
2435 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436 struct ixgbe_interrupt *intr =
2437 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2440 /* only set up it on X550EM_X */
2441 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2442 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2443 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2444 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2445 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2446 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2451 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2452 uint16_t tx_rate, uint64_t q_msk)
2454 struct ixgbe_hw *hw;
2455 struct ixgbe_vf_info *vfinfo;
2456 struct rte_eth_link link;
2457 uint8_t nb_q_per_pool;
2458 uint32_t queue_stride;
2459 uint32_t queue_idx, idx = 0, vf_idx;
2461 uint16_t total_rate = 0;
2462 struct rte_pci_device *pci_dev;
2465 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2466 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2470 if (vf >= pci_dev->max_vfs)
2473 if (tx_rate > link.link_speed)
2479 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2480 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2481 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2482 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2483 queue_idx = vf * queue_stride;
2484 queue_end = queue_idx + nb_q_per_pool - 1;
2485 if (queue_end >= hw->mac.max_tx_queues)
2489 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2492 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2494 total_rate += vfinfo[vf_idx].tx_rate[idx];
2500 /* Store tx_rate for this vf. */
2501 for (idx = 0; idx < nb_q_per_pool; idx++) {
2502 if (((uint64_t)0x1 << idx) & q_msk) {
2503 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2504 vfinfo[vf].tx_rate[idx] = tx_rate;
2505 total_rate += tx_rate;
2509 if (total_rate > dev->data->dev_link.link_speed) {
2510 /* Reset stored TX rate of the VF if it causes exceed
2513 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2517 /* Set RTTBCNRC of each queue/pool for vf X */
2518 for (; queue_idx <= queue_end; queue_idx++) {
2520 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2528 * Configure device link speed and setup link.
2529 * It returns 0 on success.
2532 ixgbe_dev_start(struct rte_eth_dev *dev)
2534 struct ixgbe_hw *hw =
2535 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536 struct ixgbe_vf_info *vfinfo =
2537 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2538 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2539 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2540 uint32_t intr_vector = 0;
2541 int err, link_up = 0, negotiate = 0;
2543 uint32_t allowed_speeds = 0;
2547 uint32_t *link_speeds;
2548 struct ixgbe_tm_conf *tm_conf =
2549 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2550 struct ixgbe_macsec_setting *macsec_ctrl =
2551 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2553 PMD_INIT_FUNC_TRACE();
2555 /* IXGBE devices don't support:
2556 * - half duplex (checked afterwards for valid speeds)
2557 * - fixed speed: TODO implement
2559 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2561 "Invalid link_speeds for port %u, fix speed not supported",
2562 dev->data->port_id);
2566 /* Stop the link setup handler before resetting the HW. */
2567 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2569 /* disable uio/vfio intr/eventfd mapping */
2570 rte_intr_disable(intr_handle);
2573 hw->adapter_stopped = 0;
2574 ixgbe_stop_adapter(hw);
2576 /* reinitialize adapter
2577 * this calls reset and start
2579 status = ixgbe_pf_reset_hw(hw);
2582 hw->mac.ops.start_hw(hw);
2583 hw->mac.get_link_status = true;
2585 /* configure PF module if SRIOV enabled */
2586 ixgbe_pf_host_configure(dev);
2588 ixgbe_dev_phy_intr_setup(dev);
2590 /* check and configure queue intr-vector mapping */
2591 if ((rte_intr_cap_multiple(intr_handle) ||
2592 !RTE_ETH_DEV_SRIOV(dev).active) &&
2593 dev->data->dev_conf.intr_conf.rxq != 0) {
2594 intr_vector = dev->data->nb_rx_queues;
2595 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2596 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2597 IXGBE_MAX_INTR_QUEUE_NUM);
2600 if (rte_intr_efd_enable(intr_handle, intr_vector))
2604 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2605 intr_handle->intr_vec =
2606 rte_zmalloc("intr_vec",
2607 dev->data->nb_rx_queues * sizeof(int), 0);
2608 if (intr_handle->intr_vec == NULL) {
2609 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2610 " intr_vec", dev->data->nb_rx_queues);
2615 /* confiugre msix for sleep until rx interrupt */
2616 ixgbe_configure_msix(dev);
2618 /* initialize transmission unit */
2619 ixgbe_dev_tx_init(dev);
2621 /* This can fail when allocating mbufs for descriptor rings */
2622 err = ixgbe_dev_rx_init(dev);
2624 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2628 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2629 ETH_VLAN_EXTEND_MASK;
2630 err = ixgbe_vlan_offload_config(dev, mask);
2632 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2636 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2637 /* Enable vlan filtering for VMDq */
2638 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2641 /* Configure DCB hw */
2642 ixgbe_configure_dcb(dev);
2644 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2645 err = ixgbe_fdir_configure(dev);
2650 /* Restore vf rate limit */
2651 if (vfinfo != NULL) {
2652 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2653 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2654 if (vfinfo[vf].tx_rate[idx] != 0)
2655 ixgbe_set_vf_rate_limit(
2657 vfinfo[vf].tx_rate[idx],
2661 ixgbe_restore_statistics_mapping(dev);
2663 err = ixgbe_dev_rxtx_start(dev);
2665 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2669 /* Skip link setup if loopback mode is enabled. */
2670 if (dev->data->dev_conf.lpbk_mode != 0) {
2671 err = ixgbe_check_supported_loopback_mode(dev);
2673 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2676 goto skip_link_setup;
2680 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2681 err = hw->mac.ops.setup_sfp(hw);
2686 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2687 /* Turn on the copper */
2688 ixgbe_set_phy_power(hw, true);
2690 /* Turn on the laser */
2691 ixgbe_enable_tx_laser(hw);
2694 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2697 dev->data->dev_link.link_status = link_up;
2699 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2703 switch (hw->mac.type) {
2704 case ixgbe_mac_X550:
2705 case ixgbe_mac_X550EM_x:
2706 case ixgbe_mac_X550EM_a:
2707 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2708 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2710 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2711 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2712 allowed_speeds = ETH_LINK_SPEED_10M |
2713 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2716 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2720 link_speeds = &dev->data->dev_conf.link_speeds;
2721 if (*link_speeds & ~allowed_speeds) {
2722 PMD_INIT_LOG(ERR, "Invalid link setting");
2727 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2728 switch (hw->mac.type) {
2729 case ixgbe_mac_82598EB:
2730 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2732 case ixgbe_mac_82599EB:
2733 case ixgbe_mac_X540:
2734 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2736 case ixgbe_mac_X550:
2737 case ixgbe_mac_X550EM_x:
2738 case ixgbe_mac_X550EM_a:
2739 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2742 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2745 if (*link_speeds & ETH_LINK_SPEED_10G)
2746 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2747 if (*link_speeds & ETH_LINK_SPEED_5G)
2748 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2749 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2750 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2751 if (*link_speeds & ETH_LINK_SPEED_1G)
2752 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2753 if (*link_speeds & ETH_LINK_SPEED_100M)
2754 speed |= IXGBE_LINK_SPEED_100_FULL;
2755 if (*link_speeds & ETH_LINK_SPEED_10M)
2756 speed |= IXGBE_LINK_SPEED_10_FULL;
2759 err = ixgbe_setup_link(hw, speed, link_up);
2765 if (rte_intr_allow_others(intr_handle)) {
2766 /* check if lsc interrupt is enabled */
2767 if (dev->data->dev_conf.intr_conf.lsc != 0)
2768 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2770 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2771 ixgbe_dev_macsec_interrupt_setup(dev);
2773 rte_intr_callback_unregister(intr_handle,
2774 ixgbe_dev_interrupt_handler, dev);
2775 if (dev->data->dev_conf.intr_conf.lsc != 0)
2776 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2777 " no intr multiplex");
2780 /* check if rxq interrupt is enabled */
2781 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2782 rte_intr_dp_is_en(intr_handle))
2783 ixgbe_dev_rxq_interrupt_setup(dev);
2785 /* enable uio/vfio intr/eventfd mapping */
2786 rte_intr_enable(intr_handle);
2788 /* resume enabled intr since hw reset */
2789 ixgbe_enable_intr(dev);
2790 ixgbe_l2_tunnel_conf(dev);
2791 ixgbe_filter_restore(dev);
2793 if (tm_conf->root && !tm_conf->committed)
2794 PMD_DRV_LOG(WARNING,
2795 "please call hierarchy_commit() "
2796 "before starting the port");
2799 * Update link status right before return, because it may
2800 * start link configuration process in a separate thread.
2802 ixgbe_dev_link_update(dev, 0);
2804 /* setup the macsec ctrl register */
2805 ixgbe_dev_macsec_register_enable(dev, macsec_ctrl);
2810 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2811 ixgbe_dev_clear_queues(dev);
2816 * Stop device: disable rx and tx functions to allow for reconfiguring.
2819 ixgbe_dev_stop(struct rte_eth_dev *dev)
2821 struct rte_eth_link link;
2822 struct ixgbe_adapter *adapter = dev->data->dev_private;
2823 struct ixgbe_hw *hw =
2824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2825 struct ixgbe_vf_info *vfinfo =
2826 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2827 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2828 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2830 struct ixgbe_tm_conf *tm_conf =
2831 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2833 if (hw->adapter_stopped)
2836 PMD_INIT_FUNC_TRACE();
2838 /* disable mecsec register */
2839 ixgbe_dev_macsec_register_disable(dev);
2841 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2843 /* disable interrupts */
2844 ixgbe_disable_intr(hw);
2847 ixgbe_pf_reset_hw(hw);
2848 hw->adapter_stopped = 0;
2851 ixgbe_stop_adapter(hw);
2853 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2854 vfinfo[vf].clear_to_send = false;
2856 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2857 /* Turn off the copper */
2858 ixgbe_set_phy_power(hw, false);
2860 /* Turn off the laser */
2861 ixgbe_disable_tx_laser(hw);
2864 ixgbe_dev_clear_queues(dev);
2866 /* Clear stored conf */
2867 dev->data->scattered_rx = 0;
2870 /* Clear recorded link status */
2871 memset(&link, 0, sizeof(link));
2872 rte_eth_linkstatus_set(dev, &link);
2874 if (!rte_intr_allow_others(intr_handle))
2875 /* resume to the default handler */
2876 rte_intr_callback_register(intr_handle,
2877 ixgbe_dev_interrupt_handler,
2880 /* Clean datapath event and queue/vec mapping */
2881 rte_intr_efd_disable(intr_handle);
2882 if (intr_handle->intr_vec != NULL) {
2883 rte_free(intr_handle->intr_vec);
2884 intr_handle->intr_vec = NULL;
2887 /* reset hierarchy commit */
2888 tm_conf->committed = false;
2890 adapter->rss_reta_updated = 0;
2892 hw->adapter_stopped = true;
2896 * Set device link up: enable tx.
2899 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2901 struct ixgbe_hw *hw =
2902 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2903 if (hw->mac.type == ixgbe_mac_82599EB) {
2904 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2905 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2906 /* Not suported in bypass mode */
2907 PMD_INIT_LOG(ERR, "Set link up is not supported "
2908 "by device id 0x%x", hw->device_id);
2914 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2915 /* Turn on the copper */
2916 ixgbe_set_phy_power(hw, true);
2918 /* Turn on the laser */
2919 ixgbe_enable_tx_laser(hw);
2920 ixgbe_dev_link_update(dev, 0);
2927 * Set device link down: disable tx.
2930 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2932 struct ixgbe_hw *hw =
2933 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2934 if (hw->mac.type == ixgbe_mac_82599EB) {
2935 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2936 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2937 /* Not suported in bypass mode */
2938 PMD_INIT_LOG(ERR, "Set link down is not supported "
2939 "by device id 0x%x", hw->device_id);
2945 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2946 /* Turn off the copper */
2947 ixgbe_set_phy_power(hw, false);
2949 /* Turn off the laser */
2950 ixgbe_disable_tx_laser(hw);
2951 ixgbe_dev_link_update(dev, 0);
2958 * Reset and stop device.
2961 ixgbe_dev_close(struct rte_eth_dev *dev)
2963 struct ixgbe_hw *hw =
2964 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2965 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2966 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2970 PMD_INIT_FUNC_TRACE();
2972 ixgbe_pf_reset_hw(hw);
2974 ixgbe_dev_stop(dev);
2976 ixgbe_dev_free_queues(dev);
2978 ixgbe_disable_pcie_master(hw);
2980 /* reprogram the RAR[0] in case user changed it. */
2981 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2983 dev->dev_ops = NULL;
2984 dev->rx_pkt_burst = NULL;
2985 dev->tx_pkt_burst = NULL;
2987 /* Unlock any pending hardware semaphore */
2988 ixgbe_swfw_lock_reset(hw);
2990 /* disable uio intr before callback unregister */
2991 rte_intr_disable(intr_handle);
2994 ret = rte_intr_callback_unregister(intr_handle,
2995 ixgbe_dev_interrupt_handler, dev);
2996 if (ret >= 0 || ret == -ENOENT) {
2998 } else if (ret != -EAGAIN) {
3000 "intr callback unregister failed: %d",
3004 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3006 /* cancel the delay handler before remove dev */
3007 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3009 /* uninitialize PF if max_vfs not zero */
3010 ixgbe_pf_host_uninit(dev);
3012 /* remove all the fdir filters & hash */
3013 ixgbe_fdir_filter_uninit(dev);
3015 /* remove all the L2 tunnel filters & hash */
3016 ixgbe_l2_tn_filter_uninit(dev);
3018 /* Remove all ntuple filters of the device */
3019 ixgbe_ntuple_filter_uninit(dev);
3021 /* clear all the filters list */
3022 ixgbe_filterlist_flush();
3024 /* Remove all Traffic Manager configuration */
3025 ixgbe_tm_conf_uninit(dev);
3027 #ifdef RTE_LIBRTE_SECURITY
3028 rte_free(dev->security_ctx);
3037 ixgbe_dev_reset(struct rte_eth_dev *dev)
3041 /* When a DPDK PMD PF begin to reset PF port, it should notify all
3042 * its VF to make them align with it. The detailed notification
3043 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3044 * To avoid unexpected behavior in VF, currently reset of PF with
3045 * SR-IOV activation is not supported. It might be supported later.
3047 if (dev->data->sriov.active)
3050 ret = eth_ixgbe_dev_uninit(dev);
3054 ret = eth_ixgbe_dev_init(dev, NULL);
3060 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3061 struct ixgbe_hw_stats *hw_stats,
3062 struct ixgbe_macsec_stats *macsec_stats,
3063 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3064 uint64_t *total_qprc, uint64_t *total_qprdc)
3066 uint32_t bprc, lxon, lxoff, total;
3067 uint32_t delta_gprc = 0;
3069 /* Workaround for RX byte count not including CRC bytes when CRC
3070 * strip is enabled. CRC bytes are removed from counters when crc_strip
3073 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3074 IXGBE_HLREG0_RXCRCSTRP);
3076 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3077 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3078 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3079 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3081 for (i = 0; i < 8; i++) {
3082 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3084 /* global total per queue */
3085 hw_stats->mpc[i] += mp;
3086 /* Running comprehensive total for stats display */
3087 *total_missed_rx += hw_stats->mpc[i];
3088 if (hw->mac.type == ixgbe_mac_82598EB) {
3089 hw_stats->rnbc[i] +=
3090 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3091 hw_stats->pxonrxc[i] +=
3092 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3093 hw_stats->pxoffrxc[i] +=
3094 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3096 hw_stats->pxonrxc[i] +=
3097 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3098 hw_stats->pxoffrxc[i] +=
3099 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3100 hw_stats->pxon2offc[i] +=
3101 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3103 hw_stats->pxontxc[i] +=
3104 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3105 hw_stats->pxofftxc[i] +=
3106 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3108 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3109 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3110 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3111 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3113 delta_gprc += delta_qprc;
3115 hw_stats->qprc[i] += delta_qprc;
3116 hw_stats->qptc[i] += delta_qptc;
3118 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3119 hw_stats->qbrc[i] +=
3120 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3122 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3124 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3125 hw_stats->qbtc[i] +=
3126 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3128 hw_stats->qprdc[i] += delta_qprdc;
3129 *total_qprdc += hw_stats->qprdc[i];
3131 *total_qprc += hw_stats->qprc[i];
3132 *total_qbrc += hw_stats->qbrc[i];
3134 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3135 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3136 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3139 * An errata states that gprc actually counts good + missed packets:
3140 * Workaround to set gprc to summated queue packet receives
3142 hw_stats->gprc = *total_qprc;
3144 if (hw->mac.type != ixgbe_mac_82598EB) {
3145 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3146 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3147 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3148 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3149 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3150 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3151 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3152 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3154 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3155 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3156 /* 82598 only has a counter in the high register */
3157 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3158 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3159 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3161 uint64_t old_tpr = hw_stats->tpr;
3163 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3164 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3167 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3169 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3170 hw_stats->gptc += delta_gptc;
3171 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3172 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3175 * Workaround: mprc hardware is incorrectly counting
3176 * broadcasts, so for now we subtract those.
3178 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3179 hw_stats->bprc += bprc;
3180 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3181 if (hw->mac.type == ixgbe_mac_82598EB)
3182 hw_stats->mprc -= bprc;
3184 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3185 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3186 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3187 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3188 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3189 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3191 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3192 hw_stats->lxontxc += lxon;
3193 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3194 hw_stats->lxofftxc += lxoff;
3195 total = lxon + lxoff;
3197 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3198 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3199 hw_stats->gptc -= total;
3200 hw_stats->mptc -= total;
3201 hw_stats->ptc64 -= total;
3202 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3204 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3205 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3206 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3207 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3208 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3209 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3210 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3211 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3212 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3213 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3214 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3215 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3216 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3217 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3218 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3219 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3220 /* Only read FCOE on 82599 */
3221 if (hw->mac.type != ixgbe_mac_82598EB) {
3222 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3223 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3224 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3225 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3226 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3229 /* Flow Director Stats registers */
3230 if (hw->mac.type != ixgbe_mac_82598EB) {
3231 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3232 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3233 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3234 IXGBE_FDIRUSTAT) & 0xFFFF;
3235 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3236 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3237 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3238 IXGBE_FDIRFSTAT) & 0xFFFF;
3239 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3240 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3242 /* MACsec Stats registers */
3243 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3244 macsec_stats->out_pkts_encrypted +=
3245 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3246 macsec_stats->out_pkts_protected +=
3247 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3248 macsec_stats->out_octets_encrypted +=
3249 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3250 macsec_stats->out_octets_protected +=
3251 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3252 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3253 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3254 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3255 macsec_stats->in_pkts_unknownsci +=
3256 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3257 macsec_stats->in_octets_decrypted +=
3258 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3259 macsec_stats->in_octets_validated +=
3260 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3261 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3262 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3263 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3264 for (i = 0; i < 2; i++) {
3265 macsec_stats->in_pkts_ok +=
3266 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3267 macsec_stats->in_pkts_invalid +=
3268 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3269 macsec_stats->in_pkts_notvalid +=
3270 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3272 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3273 macsec_stats->in_pkts_notusingsa +=
3274 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3278 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3281 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3283 struct ixgbe_hw *hw =
3284 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285 struct ixgbe_hw_stats *hw_stats =
3286 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3287 struct ixgbe_macsec_stats *macsec_stats =
3288 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3289 dev->data->dev_private);
3290 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3293 total_missed_rx = 0;
3298 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3299 &total_qbrc, &total_qprc, &total_qprdc);
3304 /* Fill out the rte_eth_stats statistics structure */
3305 stats->ipackets = total_qprc;
3306 stats->ibytes = total_qbrc;
3307 stats->opackets = hw_stats->gptc;
3308 stats->obytes = hw_stats->gotc;
3310 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3311 stats->q_ipackets[i] = hw_stats->qprc[i];
3312 stats->q_opackets[i] = hw_stats->qptc[i];
3313 stats->q_ibytes[i] = hw_stats->qbrc[i];
3314 stats->q_obytes[i] = hw_stats->qbtc[i];
3315 stats->q_errors[i] = hw_stats->qprdc[i];
3319 stats->imissed = total_missed_rx;
3320 stats->ierrors = hw_stats->crcerrs +
3337 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3339 struct ixgbe_hw_stats *stats =
3340 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3342 /* HW registers are cleared on read */
3343 ixgbe_dev_stats_get(dev, NULL);
3345 /* Reset software totals */
3346 memset(stats, 0, sizeof(*stats));
3351 /* This function calculates the number of xstats based on the current config */
3353 ixgbe_xstats_calc_num(void) {
3354 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3355 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3356 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3359 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3360 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3362 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3363 unsigned stat, i, count;
3365 if (xstats_names != NULL) {
3368 /* Note: limit >= cnt_stats checked upstream
3369 * in rte_eth_xstats_names()
3372 /* Extended stats from ixgbe_hw_stats */
3373 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3374 strlcpy(xstats_names[count].name,
3375 rte_ixgbe_stats_strings[i].name,
3376 sizeof(xstats_names[count].name));
3381 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3382 strlcpy(xstats_names[count].name,
3383 rte_ixgbe_macsec_strings[i].name,
3384 sizeof(xstats_names[count].name));
3388 /* RX Priority Stats */
3389 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3390 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3391 snprintf(xstats_names[count].name,
3392 sizeof(xstats_names[count].name),
3393 "rx_priority%u_%s", i,
3394 rte_ixgbe_rxq_strings[stat].name);
3399 /* TX Priority Stats */
3400 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3401 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3402 snprintf(xstats_names[count].name,
3403 sizeof(xstats_names[count].name),
3404 "tx_priority%u_%s", i,
3405 rte_ixgbe_txq_strings[stat].name);
3413 static int ixgbe_dev_xstats_get_names_by_id(
3414 struct rte_eth_dev *dev,
3415 struct rte_eth_xstat_name *xstats_names,
3416 const uint64_t *ids,
3420 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3421 unsigned int stat, i, count;
3423 if (xstats_names != NULL) {
3426 /* Note: limit >= cnt_stats checked upstream
3427 * in rte_eth_xstats_names()
3430 /* Extended stats from ixgbe_hw_stats */
3431 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3432 strlcpy(xstats_names[count].name,
3433 rte_ixgbe_stats_strings[i].name,
3434 sizeof(xstats_names[count].name));
3439 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3440 strlcpy(xstats_names[count].name,
3441 rte_ixgbe_macsec_strings[i].name,
3442 sizeof(xstats_names[count].name));
3446 /* RX Priority Stats */
3447 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3448 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3449 snprintf(xstats_names[count].name,
3450 sizeof(xstats_names[count].name),
3451 "rx_priority%u_%s", i,
3452 rte_ixgbe_rxq_strings[stat].name);
3457 /* TX Priority Stats */
3458 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3459 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3460 snprintf(xstats_names[count].name,
3461 sizeof(xstats_names[count].name),
3462 "tx_priority%u_%s", i,
3463 rte_ixgbe_txq_strings[stat].name);
3472 uint16_t size = ixgbe_xstats_calc_num();
3473 struct rte_eth_xstat_name xstats_names_copy[size];
3475 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3478 for (i = 0; i < limit; i++) {
3479 if (ids[i] >= size) {
3480 PMD_INIT_LOG(ERR, "id value isn't valid");
3483 strcpy(xstats_names[i].name,
3484 xstats_names_copy[ids[i]].name);
3489 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3490 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3494 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3497 if (xstats_names != NULL)
3498 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3499 strlcpy(xstats_names[i].name,
3500 rte_ixgbevf_stats_strings[i].name,
3501 sizeof(xstats_names[i].name));
3502 return IXGBEVF_NB_XSTATS;
3506 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3509 struct ixgbe_hw *hw =
3510 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3511 struct ixgbe_hw_stats *hw_stats =
3512 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3513 struct ixgbe_macsec_stats *macsec_stats =
3514 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3515 dev->data->dev_private);
3516 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3517 unsigned i, stat, count = 0;
3519 count = ixgbe_xstats_calc_num();
3524 total_missed_rx = 0;
3529 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3530 &total_qbrc, &total_qprc, &total_qprdc);
3532 /* If this is a reset xstats is NULL, and we have cleared the
3533 * registers by reading them.
3538 /* Extended stats from ixgbe_hw_stats */
3540 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3541 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3542 rte_ixgbe_stats_strings[i].offset);
3543 xstats[count].id = count;
3548 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3549 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3550 rte_ixgbe_macsec_strings[i].offset);
3551 xstats[count].id = count;
3555 /* RX Priority Stats */
3556 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3557 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3558 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3559 rte_ixgbe_rxq_strings[stat].offset +
3560 (sizeof(uint64_t) * i));
3561 xstats[count].id = count;
3566 /* TX Priority Stats */
3567 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3568 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3569 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3570 rte_ixgbe_txq_strings[stat].offset +
3571 (sizeof(uint64_t) * i));
3572 xstats[count].id = count;
3580 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3581 uint64_t *values, unsigned int n)
3584 struct ixgbe_hw *hw =
3585 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586 struct ixgbe_hw_stats *hw_stats =
3587 IXGBE_DEV_PRIVATE_TO_STATS(
3588 dev->data->dev_private);
3589 struct ixgbe_macsec_stats *macsec_stats =
3590 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3591 dev->data->dev_private);
3592 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3593 unsigned int i, stat, count = 0;
3595 count = ixgbe_xstats_calc_num();
3597 if (!ids && n < count)
3600 total_missed_rx = 0;
3605 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3606 &total_missed_rx, &total_qbrc, &total_qprc,
3609 /* If this is a reset xstats is NULL, and we have cleared the
3610 * registers by reading them.
3612 if (!ids && !values)
3615 /* Extended stats from ixgbe_hw_stats */
3617 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3618 values[count] = *(uint64_t *)(((char *)hw_stats) +
3619 rte_ixgbe_stats_strings[i].offset);
3624 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3625 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3626 rte_ixgbe_macsec_strings[i].offset);
3630 /* RX Priority Stats */
3631 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3632 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3634 *(uint64_t *)(((char *)hw_stats) +
3635 rte_ixgbe_rxq_strings[stat].offset +
3636 (sizeof(uint64_t) * i));
3641 /* TX Priority Stats */
3642 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3643 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3645 *(uint64_t *)(((char *)hw_stats) +
3646 rte_ixgbe_txq_strings[stat].offset +
3647 (sizeof(uint64_t) * i));
3655 uint16_t size = ixgbe_xstats_calc_num();
3656 uint64_t values_copy[size];
3658 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3660 for (i = 0; i < n; i++) {
3661 if (ids[i] >= size) {
3662 PMD_INIT_LOG(ERR, "id value isn't valid");
3665 values[i] = values_copy[ids[i]];
3671 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3673 struct ixgbe_hw_stats *stats =
3674 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3675 struct ixgbe_macsec_stats *macsec_stats =
3676 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3677 dev->data->dev_private);
3679 unsigned count = ixgbe_xstats_calc_num();
3681 /* HW registers are cleared on read */
3682 ixgbe_dev_xstats_get(dev, NULL, count);
3684 /* Reset software totals */
3685 memset(stats, 0, sizeof(*stats));
3686 memset(macsec_stats, 0, sizeof(*macsec_stats));
3692 ixgbevf_update_stats(struct rte_eth_dev *dev)
3694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3695 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3696 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3698 /* Good Rx packet, include VF loopback */
3699 UPDATE_VF_STAT(IXGBE_VFGPRC,
3700 hw_stats->last_vfgprc, hw_stats->vfgprc);
3702 /* Good Rx octets, include VF loopback */
3703 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3704 hw_stats->last_vfgorc, hw_stats->vfgorc);
3706 /* Good Tx packet, include VF loopback */
3707 UPDATE_VF_STAT(IXGBE_VFGPTC,
3708 hw_stats->last_vfgptc, hw_stats->vfgptc);
3710 /* Good Tx octets, include VF loopback */
3711 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3712 hw_stats->last_vfgotc, hw_stats->vfgotc);
3714 /* Rx Multicst Packet */
3715 UPDATE_VF_STAT(IXGBE_VFMPRC,
3716 hw_stats->last_vfmprc, hw_stats->vfmprc);
3720 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3723 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3724 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3727 if (n < IXGBEVF_NB_XSTATS)
3728 return IXGBEVF_NB_XSTATS;
3730 ixgbevf_update_stats(dev);
3735 /* Extended stats */
3736 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3738 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3739 rte_ixgbevf_stats_strings[i].offset);
3742 return IXGBEVF_NB_XSTATS;
3746 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3748 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3749 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3751 ixgbevf_update_stats(dev);
3756 stats->ipackets = hw_stats->vfgprc;
3757 stats->ibytes = hw_stats->vfgorc;
3758 stats->opackets = hw_stats->vfgptc;
3759 stats->obytes = hw_stats->vfgotc;
3764 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3766 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3767 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3769 /* Sync HW register to the last stats */
3770 ixgbevf_dev_stats_get(dev, NULL);
3772 /* reset HW current stats*/
3773 hw_stats->vfgprc = 0;
3774 hw_stats->vfgorc = 0;
3775 hw_stats->vfgptc = 0;
3776 hw_stats->vfgotc = 0;
3782 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3784 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785 u16 eeprom_verh, eeprom_verl;
3789 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3790 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3792 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3793 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3795 ret += 1; /* add the size of '\0' */
3796 if (fw_size < (u32)ret)
3803 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3805 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3806 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3809 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3810 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3811 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3813 * When DCB/VT is off, maximum number of queues changes,
3814 * except for 82598EB, which remains constant.
3816 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3817 hw->mac.type != ixgbe_mac_82598EB)
3818 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3820 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3821 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3822 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3823 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3824 dev_info->max_vfs = pci_dev->max_vfs;
3825 if (hw->mac.type == ixgbe_mac_82598EB)
3826 dev_info->max_vmdq_pools = ETH_16_POOLS;
3828 dev_info->max_vmdq_pools = ETH_64_POOLS;
3829 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3830 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3831 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3832 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3833 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3834 dev_info->rx_queue_offload_capa);
3835 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3836 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3838 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3840 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3841 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3842 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3844 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3849 dev_info->default_txconf = (struct rte_eth_txconf) {
3851 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3852 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3853 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3855 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3856 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3860 dev_info->rx_desc_lim = rx_desc_lim;
3861 dev_info->tx_desc_lim = tx_desc_lim;
3863 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3864 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3865 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3867 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3868 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3869 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3870 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3871 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3873 if (hw->mac.type == ixgbe_mac_X540 ||
3874 hw->mac.type == ixgbe_mac_X540_vf ||
3875 hw->mac.type == ixgbe_mac_X550 ||
3876 hw->mac.type == ixgbe_mac_X550_vf) {
3877 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3879 if (hw->mac.type == ixgbe_mac_X550) {
3880 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3881 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3884 /* Driver-preferred Rx/Tx parameters */
3885 dev_info->default_rxportconf.burst_size = 32;
3886 dev_info->default_txportconf.burst_size = 32;
3887 dev_info->default_rxportconf.nb_queues = 1;
3888 dev_info->default_txportconf.nb_queues = 1;
3889 dev_info->default_rxportconf.ring_size = 256;
3890 dev_info->default_txportconf.ring_size = 256;
3895 static const uint32_t *
3896 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3898 static const uint32_t ptypes[] = {
3899 /* For non-vec functions,
3900 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3901 * for vec functions,
3902 * refers to _recv_raw_pkts_vec().
3906 RTE_PTYPE_L3_IPV4_EXT,
3908 RTE_PTYPE_L3_IPV6_EXT,
3912 RTE_PTYPE_TUNNEL_IP,
3913 RTE_PTYPE_INNER_L3_IPV6,
3914 RTE_PTYPE_INNER_L3_IPV6_EXT,
3915 RTE_PTYPE_INNER_L4_TCP,
3916 RTE_PTYPE_INNER_L4_UDP,
3920 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3921 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3922 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3923 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3926 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3927 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3928 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3935 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3936 struct rte_eth_dev_info *dev_info)
3938 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3939 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3941 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3942 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3943 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3944 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3945 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3946 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3947 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3948 dev_info->max_vfs = pci_dev->max_vfs;
3949 if (hw->mac.type == ixgbe_mac_82598EB)
3950 dev_info->max_vmdq_pools = ETH_16_POOLS;
3952 dev_info->max_vmdq_pools = ETH_64_POOLS;
3953 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3954 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3955 dev_info->rx_queue_offload_capa);
3956 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3957 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3958 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3959 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3960 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3962 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3964 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3965 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3966 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3968 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3973 dev_info->default_txconf = (struct rte_eth_txconf) {
3975 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3976 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3977 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3979 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3980 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3984 dev_info->rx_desc_lim = rx_desc_lim;
3985 dev_info->tx_desc_lim = tx_desc_lim;
3991 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3992 int *link_up, int wait_to_complete)
3994 struct ixgbe_adapter *adapter = container_of(hw,
3995 struct ixgbe_adapter, hw);
3996 struct ixgbe_mbx_info *mbx = &hw->mbx;
3997 struct ixgbe_mac_info *mac = &hw->mac;
3998 uint32_t links_reg, in_msg;
4001 /* If we were hit with a reset drop the link */
4002 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4003 mac->get_link_status = true;
4005 if (!mac->get_link_status)
4008 /* if link status is down no point in checking to see if pf is up */
4009 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4010 if (!(links_reg & IXGBE_LINKS_UP))
4013 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4014 * before the link status is correct
4016 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4019 for (i = 0; i < 5; i++) {
4021 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4023 if (!(links_reg & IXGBE_LINKS_UP))
4028 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4029 case IXGBE_LINKS_SPEED_10G_82599:
4030 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4031 if (hw->mac.type >= ixgbe_mac_X550) {
4032 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4033 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4036 case IXGBE_LINKS_SPEED_1G_82599:
4037 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4039 case IXGBE_LINKS_SPEED_100_82599:
4040 *speed = IXGBE_LINK_SPEED_100_FULL;
4041 if (hw->mac.type == ixgbe_mac_X550) {
4042 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4043 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4046 case IXGBE_LINKS_SPEED_10_X550EM_A:
4047 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4048 /* Since Reserved in older MAC's */
4049 if (hw->mac.type >= ixgbe_mac_X550)
4050 *speed = IXGBE_LINK_SPEED_10_FULL;
4053 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4056 if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4057 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4058 mac->get_link_status = true;
4060 mac->get_link_status = false;
4065 /* if the read failed it could just be a mailbox collision, best wait
4066 * until we are called again and don't report an error
4068 if (mbx->ops.read(hw, &in_msg, 1, 0))
4071 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4072 /* msg is not CTS and is NACK we must have lost CTS status */
4073 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4074 mac->get_link_status = false;
4078 /* the pf is talking, if we timed out in the past we reinit */
4079 if (!mbx->timeout) {
4084 /* if we passed all the tests above then the link is up and we no
4085 * longer need to check for link
4087 mac->get_link_status = false;
4090 *link_up = !mac->get_link_status;
4095 ixgbe_dev_setup_link_alarm_handler(void *param)
4097 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4098 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4099 struct ixgbe_interrupt *intr =
4100 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4102 bool autoneg = false;
4104 speed = hw->phy.autoneg_advertised;
4106 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4108 ixgbe_setup_link(hw, speed, true);
4110 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4113 /* return 0 means link status changed, -1 means not changed */
4115 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4116 int wait_to_complete, int vf)
4118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4119 struct rte_eth_link link;
4120 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4121 struct ixgbe_interrupt *intr =
4122 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4128 memset(&link, 0, sizeof(link));
4129 link.link_status = ETH_LINK_DOWN;
4130 link.link_speed = ETH_SPEED_NUM_NONE;
4131 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4132 link.link_autoneg = ETH_LINK_AUTONEG;
4134 hw->mac.get_link_status = true;
4136 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4137 return rte_eth_linkstatus_set(dev, &link);
4139 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4140 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4144 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4146 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4149 link.link_speed = ETH_SPEED_NUM_100M;
4150 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4151 return rte_eth_linkstatus_set(dev, &link);
4154 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4155 if ((esdp_reg & IXGBE_ESDP_SDP3))
4159 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4160 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4161 rte_eal_alarm_set(10,
4162 ixgbe_dev_setup_link_alarm_handler, dev);
4164 return rte_eth_linkstatus_set(dev, &link);
4167 link.link_status = ETH_LINK_UP;
4168 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4170 switch (link_speed) {
4172 case IXGBE_LINK_SPEED_UNKNOWN:
4173 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4174 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4175 link.link_speed = ETH_SPEED_NUM_10M;
4177 link.link_speed = ETH_SPEED_NUM_100M;
4180 case IXGBE_LINK_SPEED_100_FULL:
4181 link.link_speed = ETH_SPEED_NUM_100M;
4184 case IXGBE_LINK_SPEED_1GB_FULL:
4185 link.link_speed = ETH_SPEED_NUM_1G;
4188 case IXGBE_LINK_SPEED_2_5GB_FULL:
4189 link.link_speed = ETH_SPEED_NUM_2_5G;
4192 case IXGBE_LINK_SPEED_5GB_FULL:
4193 link.link_speed = ETH_SPEED_NUM_5G;
4196 case IXGBE_LINK_SPEED_10GB_FULL:
4197 link.link_speed = ETH_SPEED_NUM_10G;
4201 return rte_eth_linkstatus_set(dev, &link);
4205 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4207 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4211 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4213 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4217 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4223 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4224 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4230 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4232 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4236 fctrl &= (~IXGBE_FCTRL_UPE);
4237 if (dev->data->all_multicast == 1)
4238 fctrl |= IXGBE_FCTRL_MPE;
4240 fctrl &= (~IXGBE_FCTRL_MPE);
4241 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4247 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4249 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4252 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4253 fctrl |= IXGBE_FCTRL_MPE;
4254 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4260 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4262 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4265 if (dev->data->promiscuous == 1)
4266 return 0; /* must remain in all_multicast mode */
4268 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4269 fctrl &= (~IXGBE_FCTRL_MPE);
4270 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4276 * It clears the interrupt causes and enables the interrupt.
4277 * It will be called once only during nic initialized.
4280 * Pointer to struct rte_eth_dev.
4282 * Enable or Disable.
4285 * - On success, zero.
4286 * - On failure, a negative value.
4289 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4291 struct ixgbe_interrupt *intr =
4292 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4294 ixgbe_dev_link_status_print(dev);
4296 intr->mask |= IXGBE_EICR_LSC;
4298 intr->mask &= ~IXGBE_EICR_LSC;
4304 * It clears the interrupt causes and enables the interrupt.
4305 * It will be called once only during nic initialized.
4308 * Pointer to struct rte_eth_dev.
4311 * - On success, zero.
4312 * - On failure, a negative value.
4315 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4317 struct ixgbe_interrupt *intr =
4318 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4320 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4326 * It clears the interrupt causes and enables the interrupt.
4327 * It will be called once only during nic initialized.
4330 * Pointer to struct rte_eth_dev.
4333 * - On success, zero.
4334 * - On failure, a negative value.
4337 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4339 struct ixgbe_interrupt *intr =
4340 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4342 intr->mask |= IXGBE_EICR_LINKSEC;
4348 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4351 * Pointer to struct rte_eth_dev.
4354 * - On success, zero.
4355 * - On failure, a negative value.
4358 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4361 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362 struct ixgbe_interrupt *intr =
4363 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4365 /* clear all cause mask */
4366 ixgbe_disable_intr(hw);
4368 /* read-on-clear nic registers here */
4369 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4370 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4374 /* set flag for async link update */
4375 if (eicr & IXGBE_EICR_LSC)
4376 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4378 if (eicr & IXGBE_EICR_MAILBOX)
4379 intr->flags |= IXGBE_FLAG_MAILBOX;
4381 if (eicr & IXGBE_EICR_LINKSEC)
4382 intr->flags |= IXGBE_FLAG_MACSEC;
4384 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4385 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4386 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4387 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4393 * It gets and then prints the link status.
4396 * Pointer to struct rte_eth_dev.
4399 * - On success, zero.
4400 * - On failure, a negative value.
4403 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4405 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4406 struct rte_eth_link link;
4408 rte_eth_linkstatus_get(dev, &link);
4410 if (link.link_status) {
4411 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4412 (int)(dev->data->port_id),
4413 (unsigned)link.link_speed,
4414 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4415 "full-duplex" : "half-duplex");
4417 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4418 (int)(dev->data->port_id));
4420 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4421 pci_dev->addr.domain,
4423 pci_dev->addr.devid,
4424 pci_dev->addr.function);
4428 * It executes link_update after knowing an interrupt occurred.
4431 * Pointer to struct rte_eth_dev.
4434 * - On success, zero.
4435 * - On failure, a negative value.
4438 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4440 struct ixgbe_interrupt *intr =
4441 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4443 struct ixgbe_hw *hw =
4444 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4448 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4449 ixgbe_pf_mbx_process(dev);
4450 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4453 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4454 ixgbe_handle_lasi(hw);
4455 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4458 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4459 struct rte_eth_link link;
4461 /* get the link status before link update, for predicting later */
4462 rte_eth_linkstatus_get(dev, &link);
4464 ixgbe_dev_link_update(dev, 0);
4467 if (!link.link_status)
4468 /* handle it 1 sec later, wait it being stable */
4469 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4470 /* likely to down */
4472 /* handle it 4 sec later, wait it being stable */
4473 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4475 ixgbe_dev_link_status_print(dev);
4476 if (rte_eal_alarm_set(timeout * 1000,
4477 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4478 PMD_DRV_LOG(ERR, "Error setting alarm");
4480 /* remember original mask */
4481 intr->mask_original = intr->mask;
4482 /* only disable lsc interrupt */
4483 intr->mask &= ~IXGBE_EIMS_LSC;
4487 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4488 ixgbe_enable_intr(dev);
4494 * Interrupt handler which shall be registered for alarm callback for delayed
4495 * handling specific interrupt to wait for the stable nic state. As the
4496 * NIC interrupt state is not stable for ixgbe after link is just down,
4497 * it needs to wait 4 seconds to get the stable status.
4500 * Pointer to interrupt handle.
4502 * The address of parameter (struct rte_eth_dev *) regsitered before.
4508 ixgbe_dev_interrupt_delayed_handler(void *param)
4510 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4511 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4512 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4513 struct ixgbe_interrupt *intr =
4514 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4515 struct ixgbe_hw *hw =
4516 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4519 ixgbe_disable_intr(hw);
4521 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4522 if (eicr & IXGBE_EICR_MAILBOX)
4523 ixgbe_pf_mbx_process(dev);
4525 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4526 ixgbe_handle_lasi(hw);
4527 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4530 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4531 ixgbe_dev_link_update(dev, 0);
4532 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4533 ixgbe_dev_link_status_print(dev);
4534 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4538 if (intr->flags & IXGBE_FLAG_MACSEC) {
4539 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4541 intr->flags &= ~IXGBE_FLAG_MACSEC;
4544 /* restore original mask */
4545 intr->mask = intr->mask_original;
4546 intr->mask_original = 0;
4548 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4549 ixgbe_enable_intr(dev);
4550 rte_intr_ack(intr_handle);
4554 * Interrupt handler triggered by NIC for handling
4555 * specific interrupt.
4558 * Pointer to interrupt handle.
4560 * The address of parameter (struct rte_eth_dev *) regsitered before.
4566 ixgbe_dev_interrupt_handler(void *param)
4568 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4570 ixgbe_dev_interrupt_get_status(dev);
4571 ixgbe_dev_interrupt_action(dev);
4575 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4577 struct ixgbe_hw *hw;
4579 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4580 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4584 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4586 struct ixgbe_hw *hw;
4588 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4589 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4593 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4595 struct ixgbe_hw *hw;
4601 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4603 fc_conf->pause_time = hw->fc.pause_time;
4604 fc_conf->high_water = hw->fc.high_water[0];
4605 fc_conf->low_water = hw->fc.low_water[0];
4606 fc_conf->send_xon = hw->fc.send_xon;
4607 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4610 * Return rx_pause status according to actual setting of
4613 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4614 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4620 * Return tx_pause status according to actual setting of
4623 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4624 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4629 if (rx_pause && tx_pause)
4630 fc_conf->mode = RTE_FC_FULL;
4632 fc_conf->mode = RTE_FC_RX_PAUSE;
4634 fc_conf->mode = RTE_FC_TX_PAUSE;
4636 fc_conf->mode = RTE_FC_NONE;
4642 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4644 struct ixgbe_hw *hw;
4646 uint32_t rx_buf_size;
4647 uint32_t max_high_water;
4649 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4656 PMD_INIT_FUNC_TRACE();
4658 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4659 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4660 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4663 * At least reserve one Ethernet frame for watermark
4664 * high_water/low_water in kilo bytes for ixgbe
4666 max_high_water = (rx_buf_size -
4667 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4668 if ((fc_conf->high_water > max_high_water) ||
4669 (fc_conf->high_water < fc_conf->low_water)) {
4670 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4671 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4675 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4676 hw->fc.pause_time = fc_conf->pause_time;
4677 hw->fc.high_water[0] = fc_conf->high_water;
4678 hw->fc.low_water[0] = fc_conf->low_water;
4679 hw->fc.send_xon = fc_conf->send_xon;
4680 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4682 err = ixgbe_fc_enable(hw);
4684 /* Not negotiated is not an error case */
4685 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4687 /* check if we want to forward MAC frames - driver doesn't have native
4688 * capability to do that, so we'll write the registers ourselves */
4690 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4692 /* set or clear MFLCN.PMCF bit depending on configuration */
4693 if (fc_conf->mac_ctrl_frame_fwd != 0)
4694 mflcn |= IXGBE_MFLCN_PMCF;
4696 mflcn &= ~IXGBE_MFLCN_PMCF;
4698 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4699 IXGBE_WRITE_FLUSH(hw);
4704 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4709 * ixgbe_pfc_enable_generic - Enable flow control
4710 * @hw: pointer to hardware structure
4711 * @tc_num: traffic class number
4712 * Enable flow control according to the current settings.
4715 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4718 uint32_t mflcn_reg, fccfg_reg;
4720 uint32_t fcrtl, fcrth;
4724 /* Validate the water mark configuration */
4725 if (!hw->fc.pause_time) {
4726 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4730 /* Low water mark of zero causes XOFF floods */
4731 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4732 /* High/Low water can not be 0 */
4733 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4734 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4735 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4739 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4740 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4741 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4745 /* Negotiate the fc mode to use */
4746 ixgbe_fc_autoneg(hw);
4748 /* Disable any previous flow control settings */
4749 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4750 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4752 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4753 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4755 switch (hw->fc.current_mode) {
4758 * If the count of enabled RX Priority Flow control >1,
4759 * and the TX pause can not be disabled
4762 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4763 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4764 if (reg & IXGBE_FCRTH_FCEN)
4768 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4770 case ixgbe_fc_rx_pause:
4772 * Rx Flow control is enabled and Tx Flow control is
4773 * disabled by software override. Since there really
4774 * isn't a way to advertise that we are capable of RX
4775 * Pause ONLY, we will advertise that we support both
4776 * symmetric and asymmetric Rx PAUSE. Later, we will
4777 * disable the adapter's ability to send PAUSE frames.
4779 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4781 * If the count of enabled RX Priority Flow control >1,
4782 * and the TX pause can not be disabled
4785 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4786 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4787 if (reg & IXGBE_FCRTH_FCEN)
4791 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4793 case ixgbe_fc_tx_pause:
4795 * Tx Flow control is enabled, and Rx Flow control is
4796 * disabled by software override.
4798 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4801 /* Flow control (both Rx and Tx) is enabled by SW override. */
4802 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4803 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4806 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4807 ret_val = IXGBE_ERR_CONFIG;
4811 /* Set 802.3x based flow control settings. */
4812 mflcn_reg |= IXGBE_MFLCN_DPF;
4813 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4814 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4816 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4817 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4818 hw->fc.high_water[tc_num]) {
4819 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4820 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4821 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4823 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4825 * In order to prevent Tx hangs when the internal Tx
4826 * switch is enabled we must set the high water mark
4827 * to the maximum FCRTH value. This allows the Tx
4828 * switch to function even under heavy Rx workloads.
4830 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4832 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4834 /* Configure pause time (2 TCs per register) */
4835 reg = hw->fc.pause_time * 0x00010001;
4836 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4837 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4839 /* Configure flow control refresh threshold value */
4840 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4847 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4849 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4852 if (hw->mac.type != ixgbe_mac_82598EB) {
4853 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4859 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4862 uint32_t rx_buf_size;
4863 uint32_t max_high_water;
4865 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4866 struct ixgbe_hw *hw =
4867 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4868 struct ixgbe_dcb_config *dcb_config =
4869 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4871 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4878 PMD_INIT_FUNC_TRACE();
4880 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4881 tc_num = map[pfc_conf->priority];
4882 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4883 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4885 * At least reserve one Ethernet frame for watermark
4886 * high_water/low_water in kilo bytes for ixgbe
4888 max_high_water = (rx_buf_size -
4889 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4890 if ((pfc_conf->fc.high_water > max_high_water) ||
4891 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4892 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4893 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4897 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4898 hw->fc.pause_time = pfc_conf->fc.pause_time;
4899 hw->fc.send_xon = pfc_conf->fc.send_xon;
4900 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4901 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4903 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4905 /* Not negotiated is not an error case */
4906 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4909 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4914 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4915 struct rte_eth_rss_reta_entry64 *reta_conf,
4918 uint16_t i, sp_reta_size;
4921 uint16_t idx, shift;
4922 struct ixgbe_adapter *adapter = dev->data->dev_private;
4923 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4926 PMD_INIT_FUNC_TRACE();
4928 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4929 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4934 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4935 if (reta_size != sp_reta_size) {
4936 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4937 "(%d) doesn't match the number hardware can supported "
4938 "(%d)", reta_size, sp_reta_size);
4942 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4943 idx = i / RTE_RETA_GROUP_SIZE;
4944 shift = i % RTE_RETA_GROUP_SIZE;
4945 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4949 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4950 if (mask == IXGBE_4_BIT_MASK)
4953 r = IXGBE_READ_REG(hw, reta_reg);
4954 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4955 if (mask & (0x1 << j))
4956 reta |= reta_conf[idx].reta[shift + j] <<
4959 reta |= r & (IXGBE_8_BIT_MASK <<
4962 IXGBE_WRITE_REG(hw, reta_reg, reta);
4964 adapter->rss_reta_updated = 1;
4970 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4971 struct rte_eth_rss_reta_entry64 *reta_conf,
4974 uint16_t i, sp_reta_size;
4977 uint16_t idx, shift;
4978 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4981 PMD_INIT_FUNC_TRACE();
4982 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4983 if (reta_size != sp_reta_size) {
4984 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4985 "(%d) doesn't match the number hardware can supported "
4986 "(%d)", reta_size, sp_reta_size);
4990 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4991 idx = i / RTE_RETA_GROUP_SIZE;
4992 shift = i % RTE_RETA_GROUP_SIZE;
4993 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4998 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4999 reta = IXGBE_READ_REG(hw, reta_reg);
5000 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5001 if (mask & (0x1 << j))
5002 reta_conf[idx].reta[shift + j] =
5003 ((reta >> (CHAR_BIT * j)) &
5012 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5013 uint32_t index, uint32_t pool)
5015 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5016 uint32_t enable_addr = 1;
5018 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5023 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5025 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5027 ixgbe_clear_rar(hw, index);
5031 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5033 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5035 ixgbe_remove_rar(dev, 0);
5036 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5042 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5044 if (strcmp(dev->device->driver->name, drv->driver.name))
5051 is_ixgbe_supported(struct rte_eth_dev *dev)
5053 return is_device_supported(dev, &rte_ixgbe_pmd);
5057 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5061 struct ixgbe_hw *hw;
5062 struct rte_eth_dev_info dev_info;
5063 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5064 struct rte_eth_dev_data *dev_data = dev->data;
5067 ret = ixgbe_dev_info_get(dev, &dev_info);
5071 /* check that mtu is within the allowed range */
5072 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5075 /* If device is started, refuse mtu that requires the support of
5076 * scattered packets when this feature has not been enabled before.
5078 if (dev_data->dev_started && !dev_data->scattered_rx &&
5079 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5080 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5081 PMD_INIT_LOG(ERR, "Stop port first.");
5085 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5088 /* switch to jumbo mode if needed */
5089 if (frame_size > RTE_ETHER_MAX_LEN) {
5090 dev->data->dev_conf.rxmode.offloads |=
5091 DEV_RX_OFFLOAD_JUMBO_FRAME;
5092 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5094 dev->data->dev_conf.rxmode.offloads &=
5095 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5096 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5098 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5100 /* update max frame size */
5101 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5103 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5104 maxfrs &= 0x0000FFFF;
5105 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5106 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5112 * Virtual Function operations
5115 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5117 struct ixgbe_interrupt *intr =
5118 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5119 struct ixgbe_hw *hw =
5120 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122 PMD_INIT_FUNC_TRACE();
5124 /* Clear interrupt mask to stop from interrupts being generated */
5125 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5127 IXGBE_WRITE_FLUSH(hw);
5129 /* Clear mask value. */
5134 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5136 struct ixgbe_interrupt *intr =
5137 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5138 struct ixgbe_hw *hw =
5139 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5141 PMD_INIT_FUNC_TRACE();
5143 /* VF enable interrupt autoclean */
5144 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5145 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5146 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5148 IXGBE_WRITE_FLUSH(hw);
5150 /* Save IXGBE_VTEIMS value to mask. */
5151 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5155 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5157 struct rte_eth_conf *conf = &dev->data->dev_conf;
5158 struct ixgbe_adapter *adapter = dev->data->dev_private;
5160 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5161 dev->data->port_id);
5163 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5166 * VF has no ability to enable/disable HW CRC
5167 * Keep the persistent behavior the same as Host PF
5169 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5170 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5171 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5172 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5175 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5176 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5177 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5182 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5183 * allocation or vector Rx preconditions we will reset it.
5185 adapter->rx_bulk_alloc_allowed = true;
5186 adapter->rx_vec_allowed = true;
5192 ixgbevf_dev_start(struct rte_eth_dev *dev)
5194 struct ixgbe_hw *hw =
5195 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5196 uint32_t intr_vector = 0;
5197 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5198 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5202 PMD_INIT_FUNC_TRACE();
5204 /* Stop the link setup handler before resetting the HW. */
5205 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5207 err = hw->mac.ops.reset_hw(hw);
5209 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5212 hw->mac.get_link_status = true;
5214 /* negotiate mailbox API version to use with the PF. */
5215 ixgbevf_negotiate_api(hw);
5217 ixgbevf_dev_tx_init(dev);
5219 /* This can fail when allocating mbufs for descriptor rings */
5220 err = ixgbevf_dev_rx_init(dev);
5222 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5223 ixgbe_dev_clear_queues(dev);
5228 ixgbevf_set_vfta_all(dev, 1);
5231 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5232 ETH_VLAN_EXTEND_MASK;
5233 err = ixgbevf_vlan_offload_config(dev, mask);
5235 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5236 ixgbe_dev_clear_queues(dev);
5240 ixgbevf_dev_rxtx_start(dev);
5242 /* check and configure queue intr-vector mapping */
5243 if (rte_intr_cap_multiple(intr_handle) &&
5244 dev->data->dev_conf.intr_conf.rxq) {
5245 /* According to datasheet, only vector 0/1/2 can be used,
5246 * now only one vector is used for Rx queue
5249 if (rte_intr_efd_enable(intr_handle, intr_vector))
5253 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5254 intr_handle->intr_vec =
5255 rte_zmalloc("intr_vec",
5256 dev->data->nb_rx_queues * sizeof(int), 0);
5257 if (intr_handle->intr_vec == NULL) {
5258 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5259 " intr_vec", dev->data->nb_rx_queues);
5263 ixgbevf_configure_msix(dev);
5265 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5266 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5267 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5268 * is not cleared, it will fail when following rte_intr_enable( ) tries
5269 * to map Rx queue interrupt to other VFIO vectors.
5270 * So clear uio/vfio intr/evevnfd first to avoid failure.
5272 rte_intr_disable(intr_handle);
5274 rte_intr_enable(intr_handle);
5276 /* Re-enable interrupt for VF */
5277 ixgbevf_intr_enable(dev);
5280 * Update link status right before return, because it may
5281 * start link configuration process in a separate thread.
5283 ixgbevf_dev_link_update(dev, 0);
5285 hw->adapter_stopped = false;
5291 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5293 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5294 struct ixgbe_adapter *adapter = dev->data->dev_private;
5295 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5296 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5298 if (hw->adapter_stopped)
5301 PMD_INIT_FUNC_TRACE();
5303 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5305 ixgbevf_intr_disable(dev);
5307 hw->adapter_stopped = 1;
5308 ixgbe_stop_adapter(hw);
5311 * Clear what we set, but we still keep shadow_vfta to
5312 * restore after device starts
5314 ixgbevf_set_vfta_all(dev, 0);
5316 /* Clear stored conf */
5317 dev->data->scattered_rx = 0;
5319 ixgbe_dev_clear_queues(dev);
5321 /* Clean datapath event and queue/vec mapping */
5322 rte_intr_efd_disable(intr_handle);
5323 if (intr_handle->intr_vec != NULL) {
5324 rte_free(intr_handle->intr_vec);
5325 intr_handle->intr_vec = NULL;
5328 adapter->rss_reta_updated = 0;
5332 ixgbevf_dev_close(struct rte_eth_dev *dev)
5334 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5336 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5338 PMD_INIT_FUNC_TRACE();
5342 ixgbevf_dev_stop(dev);
5344 ixgbe_dev_free_queues(dev);
5347 * Remove the VF MAC address ro ensure
5348 * that the VF traffic goes to the PF
5349 * after stop, close and detach of the VF
5351 ixgbevf_remove_mac_addr(dev, 0);
5353 dev->dev_ops = NULL;
5354 dev->rx_pkt_burst = NULL;
5355 dev->tx_pkt_burst = NULL;
5357 rte_intr_disable(intr_handle);
5358 rte_intr_callback_unregister(intr_handle,
5359 ixgbevf_dev_interrupt_handler, dev);
5366 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5370 ret = eth_ixgbevf_dev_uninit(dev);
5374 ret = eth_ixgbevf_dev_init(dev);
5379 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5382 struct ixgbe_vfta *shadow_vfta =
5383 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5384 int i = 0, j = 0, vfta = 0, mask = 1;
5386 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5387 vfta = shadow_vfta->vfta[i];
5390 for (j = 0; j < 32; j++) {
5392 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5402 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5404 struct ixgbe_hw *hw =
5405 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5406 struct ixgbe_vfta *shadow_vfta =
5407 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5408 uint32_t vid_idx = 0;
5409 uint32_t vid_bit = 0;
5412 PMD_INIT_FUNC_TRACE();
5414 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5415 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5417 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5420 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5421 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5423 /* Save what we set and retore it after device reset */
5425 shadow_vfta->vfta[vid_idx] |= vid_bit;
5427 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5433 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5435 struct ixgbe_hw *hw =
5436 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5439 PMD_INIT_FUNC_TRACE();
5441 if (queue >= hw->mac.max_rx_queues)
5444 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5446 ctrl |= IXGBE_RXDCTL_VME;
5448 ctrl &= ~IXGBE_RXDCTL_VME;
5449 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5451 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5455 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5457 struct ixgbe_rx_queue *rxq;
5461 /* VF function only support hw strip feature, others are not support */
5462 if (mask & ETH_VLAN_STRIP_MASK) {
5463 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5464 rxq = dev->data->rx_queues[i];
5465 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5466 ixgbevf_vlan_strip_queue_set(dev, i, on);
5474 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5476 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5478 ixgbevf_vlan_offload_config(dev, mask);
5484 ixgbe_vt_check(struct ixgbe_hw *hw)
5488 /* if Virtualization Technology is enabled */
5489 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5490 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5491 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5499 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5501 uint32_t vector = 0;
5503 switch (hw->mac.mc_filter_type) {
5504 case 0: /* use bits [47:36] of the address */
5505 vector = ((uc_addr->addr_bytes[4] >> 4) |
5506 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5508 case 1: /* use bits [46:35] of the address */
5509 vector = ((uc_addr->addr_bytes[4] >> 3) |
5510 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5512 case 2: /* use bits [45:34] of the address */
5513 vector = ((uc_addr->addr_bytes[4] >> 2) |
5514 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5516 case 3: /* use bits [43:32] of the address */
5517 vector = ((uc_addr->addr_bytes[4]) |
5518 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5520 default: /* Invalid mc_filter_type */
5524 /* vector can only be 12-bits or boundary will be exceeded */
5530 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5531 struct rte_ether_addr *mac_addr, uint8_t on)
5538 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5539 const uint32_t ixgbe_uta_bit_shift = 5;
5540 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5541 const uint32_t bit1 = 0x1;
5543 struct ixgbe_hw *hw =
5544 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5545 struct ixgbe_uta_info *uta_info =
5546 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5548 /* The UTA table only exists on 82599 hardware and newer */
5549 if (hw->mac.type < ixgbe_mac_82599EB)
5552 vector = ixgbe_uta_vector(hw, mac_addr);
5553 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5554 uta_shift = vector & ixgbe_uta_bit_mask;
5556 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5560 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5562 uta_info->uta_in_use++;
5563 reg_val |= (bit1 << uta_shift);
5564 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5566 uta_info->uta_in_use--;
5567 reg_val &= ~(bit1 << uta_shift);
5568 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5571 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5573 if (uta_info->uta_in_use > 0)
5574 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5575 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5577 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5583 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5586 struct ixgbe_hw *hw =
5587 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5588 struct ixgbe_uta_info *uta_info =
5589 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5591 /* The UTA table only exists on 82599 hardware and newer */
5592 if (hw->mac.type < ixgbe_mac_82599EB)
5596 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5597 uta_info->uta_shadow[i] = ~0;
5598 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5601 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5602 uta_info->uta_shadow[i] = 0;
5603 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5611 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5613 uint32_t new_val = orig_val;
5615 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5616 new_val |= IXGBE_VMOLR_AUPE;
5617 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5618 new_val |= IXGBE_VMOLR_ROMPE;
5619 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5620 new_val |= IXGBE_VMOLR_ROPE;
5621 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5622 new_val |= IXGBE_VMOLR_BAM;
5623 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5624 new_val |= IXGBE_VMOLR_MPE;
5629 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5630 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5631 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5632 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5633 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5634 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5635 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5638 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5639 struct rte_eth_mirror_conf *mirror_conf,
5640 uint8_t rule_id, uint8_t on)
5642 uint32_t mr_ctl, vlvf;
5643 uint32_t mp_lsb = 0;
5644 uint32_t mv_msb = 0;
5645 uint32_t mv_lsb = 0;
5646 uint32_t mp_msb = 0;
5649 uint64_t vlan_mask = 0;
5651 const uint8_t pool_mask_offset = 32;
5652 const uint8_t vlan_mask_offset = 32;
5653 const uint8_t dst_pool_offset = 8;
5654 const uint8_t rule_mr_offset = 4;
5655 const uint8_t mirror_rule_mask = 0x0F;
5657 struct ixgbe_mirror_info *mr_info =
5658 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5659 struct ixgbe_hw *hw =
5660 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5661 uint8_t mirror_type = 0;
5663 if (ixgbe_vt_check(hw) < 0)
5666 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5669 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5670 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5671 mirror_conf->rule_type);
5675 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5676 mirror_type |= IXGBE_MRCTL_VLME;
5677 /* Check if vlan id is valid and find conresponding VLAN ID
5680 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5681 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5682 /* search vlan id related pool vlan filter
5685 reg_index = ixgbe_find_vlvf_slot(
5687 mirror_conf->vlan.vlan_id[i],
5691 vlvf = IXGBE_READ_REG(hw,
5692 IXGBE_VLVF(reg_index));
5693 if ((vlvf & IXGBE_VLVF_VIEN) &&
5694 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5695 mirror_conf->vlan.vlan_id[i]))
5696 vlan_mask |= (1ULL << reg_index);
5703 mv_lsb = vlan_mask & 0xFFFFFFFF;
5704 mv_msb = vlan_mask >> vlan_mask_offset;
5706 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5707 mirror_conf->vlan.vlan_mask;
5708 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5709 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5710 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5711 mirror_conf->vlan.vlan_id[i];
5716 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5717 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5718 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5723 * if enable pool mirror, write related pool mask register,if disable
5724 * pool mirror, clear PFMRVM register
5726 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5727 mirror_type |= IXGBE_MRCTL_VPME;
5729 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5730 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5731 mr_info->mr_conf[rule_id].pool_mask =
5732 mirror_conf->pool_mask;
5737 mr_info->mr_conf[rule_id].pool_mask = 0;
5740 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5741 mirror_type |= IXGBE_MRCTL_UPME;
5742 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5743 mirror_type |= IXGBE_MRCTL_DPME;
5745 /* read mirror control register and recalculate it */
5746 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5749 mr_ctl |= mirror_type;
5750 mr_ctl &= mirror_rule_mask;
5751 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5753 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5756 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5757 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5759 /* write mirrror control register */
5760 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5762 /* write pool mirrror control register */
5763 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5764 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5765 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5768 /* write VLAN mirrror control register */
5769 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5770 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5771 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5779 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5782 uint32_t lsb_val = 0;
5783 uint32_t msb_val = 0;
5784 const uint8_t rule_mr_offset = 4;
5786 struct ixgbe_hw *hw =
5787 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5788 struct ixgbe_mirror_info *mr_info =
5789 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5791 if (ixgbe_vt_check(hw) < 0)
5794 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5797 memset(&mr_info->mr_conf[rule_id], 0,
5798 sizeof(struct rte_eth_mirror_conf));
5800 /* clear PFVMCTL register */
5801 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5803 /* clear pool mask register */
5804 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5805 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5807 /* clear vlan mask register */
5808 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5809 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5815 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5817 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5818 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5819 struct ixgbe_interrupt *intr =
5820 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5821 struct ixgbe_hw *hw =
5822 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5823 uint32_t vec = IXGBE_MISC_VEC_ID;
5825 if (rte_intr_allow_others(intr_handle))
5826 vec = IXGBE_RX_VEC_START;
5827 intr->mask |= (1 << vec);
5828 RTE_SET_USED(queue_id);
5829 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5831 rte_intr_ack(intr_handle);
5837 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5839 struct ixgbe_interrupt *intr =
5840 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5841 struct ixgbe_hw *hw =
5842 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5843 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5844 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5845 uint32_t vec = IXGBE_MISC_VEC_ID;
5847 if (rte_intr_allow_others(intr_handle))
5848 vec = IXGBE_RX_VEC_START;
5849 intr->mask &= ~(1 << vec);
5850 RTE_SET_USED(queue_id);
5851 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5857 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5859 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5860 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5862 struct ixgbe_hw *hw =
5863 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5864 struct ixgbe_interrupt *intr =
5865 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5867 if (queue_id < 16) {
5868 ixgbe_disable_intr(hw);
5869 intr->mask |= (1 << queue_id);
5870 ixgbe_enable_intr(dev);
5871 } else if (queue_id < 32) {
5872 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5873 mask &= (1 << queue_id);
5874 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5875 } else if (queue_id < 64) {
5876 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5877 mask &= (1 << (queue_id - 32));
5878 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5880 rte_intr_ack(intr_handle);
5886 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5889 struct ixgbe_hw *hw =
5890 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5891 struct ixgbe_interrupt *intr =
5892 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5894 if (queue_id < 16) {
5895 ixgbe_disable_intr(hw);
5896 intr->mask &= ~(1 << queue_id);
5897 ixgbe_enable_intr(dev);
5898 } else if (queue_id < 32) {
5899 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5900 mask &= ~(1 << queue_id);
5901 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5902 } else if (queue_id < 64) {
5903 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5904 mask &= ~(1 << (queue_id - 32));
5905 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5912 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5913 uint8_t queue, uint8_t msix_vector)
5917 if (direction == -1) {
5919 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5920 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5923 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5925 /* rx or tx cause */
5926 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5927 idx = ((16 * (queue & 1)) + (8 * direction));
5928 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5929 tmp &= ~(0xFF << idx);
5930 tmp |= (msix_vector << idx);
5931 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5936 * set the IVAR registers, mapping interrupt causes to vectors
5938 * pointer to ixgbe_hw struct
5940 * 0 for Rx, 1 for Tx, -1 for other causes
5942 * queue to map the corresponding interrupt to
5944 * the vector to map to the corresponding queue
5947 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5948 uint8_t queue, uint8_t msix_vector)
5952 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5953 if (hw->mac.type == ixgbe_mac_82598EB) {
5954 if (direction == -1)
5956 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5957 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5958 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5959 tmp |= (msix_vector << (8 * (queue & 0x3)));
5960 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5961 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5962 (hw->mac.type == ixgbe_mac_X540) ||
5963 (hw->mac.type == ixgbe_mac_X550) ||
5964 (hw->mac.type == ixgbe_mac_X550EM_x)) {
5965 if (direction == -1) {
5967 idx = ((queue & 1) * 8);
5968 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5969 tmp &= ~(0xFF << idx);
5970 tmp |= (msix_vector << idx);
5971 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5973 /* rx or tx causes */
5974 idx = ((16 * (queue & 1)) + (8 * direction));
5975 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5976 tmp &= ~(0xFF << idx);
5977 tmp |= (msix_vector << idx);
5978 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5984 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5988 struct ixgbe_hw *hw =
5989 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5991 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5992 uint32_t base = IXGBE_MISC_VEC_ID;
5994 /* Configure VF other cause ivar */
5995 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5997 /* won't configure msix register if no mapping is done
5998 * between intr vector and event fd.
6000 if (!rte_intr_dp_is_en(intr_handle))
6003 if (rte_intr_allow_others(intr_handle)) {
6004 base = IXGBE_RX_VEC_START;
6005 vector_idx = IXGBE_RX_VEC_START;
6008 /* Configure all RX queues of VF */
6009 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6010 /* Force all queue use vector 0,
6011 * as IXGBE_VF_MAXMSIVECOTR = 1
6013 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6014 intr_handle->intr_vec[q_idx] = vector_idx;
6015 if (vector_idx < base + intr_handle->nb_efd - 1)
6019 /* As RX queue setting above show, all queues use the vector 0.
6020 * Set only the ITR value of IXGBE_MISC_VEC_ID.
6022 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6023 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6024 | IXGBE_EITR_CNT_WDIS);
6028 * Sets up the hardware to properly generate MSI-X interrupts
6030 * board private structure
6033 ixgbe_configure_msix(struct rte_eth_dev *dev)
6035 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6036 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6037 struct ixgbe_hw *hw =
6038 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6039 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6040 uint32_t vec = IXGBE_MISC_VEC_ID;
6044 /* won't configure msix register if no mapping is done
6045 * between intr vector and event fd
6046 * but if misx has been enabled already, need to configure
6047 * auto clean, auto mask and throttling.
6049 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6050 if (!rte_intr_dp_is_en(intr_handle) &&
6051 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6054 if (rte_intr_allow_others(intr_handle))
6055 vec = base = IXGBE_RX_VEC_START;
6057 /* setup GPIE for MSI-x mode */
6058 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6059 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6060 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6061 /* auto clearing and auto setting corresponding bits in EIMS
6062 * when MSI-X interrupt is triggered
6064 if (hw->mac.type == ixgbe_mac_82598EB) {
6065 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6067 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6068 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6070 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6072 /* Populate the IVAR table and set the ITR values to the
6073 * corresponding register.
6075 if (rte_intr_dp_is_en(intr_handle)) {
6076 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6078 /* by default, 1:1 mapping */
6079 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6080 intr_handle->intr_vec[queue_id] = vec;
6081 if (vec < base + intr_handle->nb_efd - 1)
6085 switch (hw->mac.type) {
6086 case ixgbe_mac_82598EB:
6087 ixgbe_set_ivar_map(hw, -1,
6088 IXGBE_IVAR_OTHER_CAUSES_INDEX,
6091 case ixgbe_mac_82599EB:
6092 case ixgbe_mac_X540:
6093 case ixgbe_mac_X550:
6094 case ixgbe_mac_X550EM_x:
6095 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6101 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6102 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6103 | IXGBE_EITR_CNT_WDIS);
6105 /* set up to autoclear timer, and the vectors */
6106 mask = IXGBE_EIMS_ENABLE_MASK;
6107 mask &= ~(IXGBE_EIMS_OTHER |
6108 IXGBE_EIMS_MAILBOX |
6111 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6115 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6116 uint16_t queue_idx, uint16_t tx_rate)
6118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6119 struct rte_eth_rxmode *rxmode;
6120 uint32_t rf_dec, rf_int;
6122 uint16_t link_speed = dev->data->dev_link.link_speed;
6124 if (queue_idx >= hw->mac.max_tx_queues)
6128 /* Calculate the rate factor values to set */
6129 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6130 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6131 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6133 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6134 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6135 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6136 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6141 rxmode = &dev->data->dev_conf.rxmode;
6143 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6144 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6147 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6148 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6149 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6150 IXGBE_MMW_SIZE_JUMBO_FRAME);
6152 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6153 IXGBE_MMW_SIZE_DEFAULT);
6155 /* Set RTTBCNRC of queue X */
6156 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6157 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6158 IXGBE_WRITE_FLUSH(hw);
6164 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6165 __attribute__((unused)) uint32_t index,
6166 __attribute__((unused)) uint32_t pool)
6168 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6172 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6173 * operation. Trap this case to avoid exhausting the [very limited]
6174 * set of PF resources used to store VF MAC addresses.
6176 if (memcmp(hw->mac.perm_addr, mac_addr,
6177 sizeof(struct rte_ether_addr)) == 0)
6179 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6181 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6182 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6183 mac_addr->addr_bytes[0],
6184 mac_addr->addr_bytes[1],
6185 mac_addr->addr_bytes[2],
6186 mac_addr->addr_bytes[3],
6187 mac_addr->addr_bytes[4],
6188 mac_addr->addr_bytes[5],
6194 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6196 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6197 struct rte_ether_addr *perm_addr =
6198 (struct rte_ether_addr *)hw->mac.perm_addr;
6199 struct rte_ether_addr *mac_addr;
6204 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6205 * not support the deletion of a given MAC address.
6206 * Instead, it imposes to delete all MAC addresses, then to add again
6207 * all MAC addresses with the exception of the one to be deleted.
6209 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6212 * Add again all MAC addresses, with the exception of the deleted one
6213 * and of the permanent MAC address.
6215 for (i = 0, mac_addr = dev->data->mac_addrs;
6216 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6217 /* Skip the deleted MAC address */
6220 /* Skip NULL MAC addresses */
6221 if (rte_is_zero_ether_addr(mac_addr))
6223 /* Skip the permanent MAC address */
6224 if (memcmp(perm_addr, mac_addr,
6225 sizeof(struct rte_ether_addr)) == 0)
6227 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6230 "Adding again MAC address "
6231 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6233 mac_addr->addr_bytes[0],
6234 mac_addr->addr_bytes[1],
6235 mac_addr->addr_bytes[2],
6236 mac_addr->addr_bytes[3],
6237 mac_addr->addr_bytes[4],
6238 mac_addr->addr_bytes[5],
6244 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6245 struct rte_ether_addr *addr)
6247 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6249 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6255 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6256 struct rte_eth_syn_filter *filter,
6259 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6260 struct ixgbe_filter_info *filter_info =
6261 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6265 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6268 syn_info = filter_info->syn_info;
6271 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6273 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6274 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6276 if (filter->hig_pri)
6277 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6279 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6281 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6282 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6284 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6287 filter_info->syn_info = synqf;
6288 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6289 IXGBE_WRITE_FLUSH(hw);
6294 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6295 struct rte_eth_syn_filter *filter)
6297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6298 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6300 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6301 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6302 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6309 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6310 enum rte_filter_op filter_op,
6313 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6316 MAC_TYPE_FILTER_SUP(hw->mac.type);
6318 if (filter_op == RTE_ETH_FILTER_NOP)
6322 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6327 switch (filter_op) {
6328 case RTE_ETH_FILTER_ADD:
6329 ret = ixgbe_syn_filter_set(dev,
6330 (struct rte_eth_syn_filter *)arg,
6333 case RTE_ETH_FILTER_DELETE:
6334 ret = ixgbe_syn_filter_set(dev,
6335 (struct rte_eth_syn_filter *)arg,
6338 case RTE_ETH_FILTER_GET:
6339 ret = ixgbe_syn_filter_get(dev,
6340 (struct rte_eth_syn_filter *)arg);
6343 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6352 static inline enum ixgbe_5tuple_protocol
6353 convert_protocol_type(uint8_t protocol_value)
6355 if (protocol_value == IPPROTO_TCP)
6356 return IXGBE_FILTER_PROTOCOL_TCP;
6357 else if (protocol_value == IPPROTO_UDP)
6358 return IXGBE_FILTER_PROTOCOL_UDP;
6359 else if (protocol_value == IPPROTO_SCTP)
6360 return IXGBE_FILTER_PROTOCOL_SCTP;
6362 return IXGBE_FILTER_PROTOCOL_NONE;
6365 /* inject a 5-tuple filter to HW */
6367 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6368 struct ixgbe_5tuple_filter *filter)
6370 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6372 uint32_t ftqf, sdpqf;
6373 uint32_t l34timir = 0;
6374 uint8_t mask = 0xff;
6378 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6379 IXGBE_SDPQF_DSTPORT_SHIFT);
6380 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6382 ftqf = (uint32_t)(filter->filter_info.proto &
6383 IXGBE_FTQF_PROTOCOL_MASK);
6384 ftqf |= (uint32_t)((filter->filter_info.priority &
6385 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6386 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6387 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6388 if (filter->filter_info.dst_ip_mask == 0)
6389 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6390 if (filter->filter_info.src_port_mask == 0)
6391 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6392 if (filter->filter_info.dst_port_mask == 0)
6393 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6394 if (filter->filter_info.proto_mask == 0)
6395 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6396 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6397 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6398 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6400 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6401 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6402 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6403 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6405 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6406 l34timir |= (uint32_t)(filter->queue <<
6407 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6408 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6412 * add a 5tuple filter
6415 * dev: Pointer to struct rte_eth_dev.
6416 * index: the index the filter allocates.
6417 * filter: ponter to the filter that will be added.
6418 * rx_queue: the queue id the filter assigned to.
6421 * - On success, zero.
6422 * - On failure, a negative value.
6425 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6426 struct ixgbe_5tuple_filter *filter)
6428 struct ixgbe_filter_info *filter_info =
6429 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6433 * look for an unused 5tuple filter index,
6434 * and insert the filter to list.
6436 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6437 idx = i / (sizeof(uint32_t) * NBBY);
6438 shift = i % (sizeof(uint32_t) * NBBY);
6439 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6440 filter_info->fivetuple_mask[idx] |= 1 << shift;
6442 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6448 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6449 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6453 ixgbe_inject_5tuple_filter(dev, filter);
6459 * remove a 5tuple filter
6462 * dev: Pointer to struct rte_eth_dev.
6463 * filter: the pointer of the filter will be removed.
6466 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6467 struct ixgbe_5tuple_filter *filter)
6469 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6470 struct ixgbe_filter_info *filter_info =
6471 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6472 uint16_t index = filter->index;
6474 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6475 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6476 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6479 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6480 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6481 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6482 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6483 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6487 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6489 struct ixgbe_hw *hw;
6490 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6491 struct rte_eth_dev_data *dev_data = dev->data;
6493 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6495 if (mtu < RTE_ETHER_MIN_MTU ||
6496 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6499 /* If device is started, refuse mtu that requires the support of
6500 * scattered packets when this feature has not been enabled before.
6502 if (dev_data->dev_started && !dev_data->scattered_rx &&
6503 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6504 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6505 PMD_INIT_LOG(ERR, "Stop port first.");
6510 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6511 * request of the version 2.0 of the mailbox API.
6512 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6513 * of the mailbox API.
6514 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6515 * prior to 3.11.33 which contains the following change:
6516 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6518 ixgbevf_rlpml_set_vf(hw, max_frame);
6520 /* update max frame size */
6521 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6525 static inline struct ixgbe_5tuple_filter *
6526 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6527 struct ixgbe_5tuple_filter_info *key)
6529 struct ixgbe_5tuple_filter *it;
6531 TAILQ_FOREACH(it, filter_list, entries) {
6532 if (memcmp(key, &it->filter_info,
6533 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6540 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6542 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6543 struct ixgbe_5tuple_filter_info *filter_info)
6545 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6546 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6547 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6550 switch (filter->dst_ip_mask) {
6552 filter_info->dst_ip_mask = 0;
6553 filter_info->dst_ip = filter->dst_ip;
6556 filter_info->dst_ip_mask = 1;
6559 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6563 switch (filter->src_ip_mask) {
6565 filter_info->src_ip_mask = 0;
6566 filter_info->src_ip = filter->src_ip;
6569 filter_info->src_ip_mask = 1;
6572 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6576 switch (filter->dst_port_mask) {
6578 filter_info->dst_port_mask = 0;
6579 filter_info->dst_port = filter->dst_port;
6582 filter_info->dst_port_mask = 1;
6585 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6589 switch (filter->src_port_mask) {
6591 filter_info->src_port_mask = 0;
6592 filter_info->src_port = filter->src_port;
6595 filter_info->src_port_mask = 1;
6598 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6602 switch (filter->proto_mask) {
6604 filter_info->proto_mask = 0;
6605 filter_info->proto =
6606 convert_protocol_type(filter->proto);
6609 filter_info->proto_mask = 1;
6612 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6616 filter_info->priority = (uint8_t)filter->priority;
6621 * add or delete a ntuple filter
6624 * dev: Pointer to struct rte_eth_dev.
6625 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6626 * add: if true, add filter, if false, remove filter
6629 * - On success, zero.
6630 * - On failure, a negative value.
6633 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6634 struct rte_eth_ntuple_filter *ntuple_filter,
6637 struct ixgbe_filter_info *filter_info =
6638 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6639 struct ixgbe_5tuple_filter_info filter_5tuple;
6640 struct ixgbe_5tuple_filter *filter;
6643 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6644 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6648 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6649 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6653 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6655 if (filter != NULL && add) {
6656 PMD_DRV_LOG(ERR, "filter exists.");
6659 if (filter == NULL && !add) {
6660 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6665 filter = rte_zmalloc("ixgbe_5tuple_filter",
6666 sizeof(struct ixgbe_5tuple_filter), 0);
6669 rte_memcpy(&filter->filter_info,
6671 sizeof(struct ixgbe_5tuple_filter_info));
6672 filter->queue = ntuple_filter->queue;
6673 ret = ixgbe_add_5tuple_filter(dev, filter);
6679 ixgbe_remove_5tuple_filter(dev, filter);
6685 * get a ntuple filter
6688 * dev: Pointer to struct rte_eth_dev.
6689 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6692 * - On success, zero.
6693 * - On failure, a negative value.
6696 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6697 struct rte_eth_ntuple_filter *ntuple_filter)
6699 struct ixgbe_filter_info *filter_info =
6700 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6701 struct ixgbe_5tuple_filter_info filter_5tuple;
6702 struct ixgbe_5tuple_filter *filter;
6705 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6706 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6710 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6711 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6715 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6717 if (filter == NULL) {
6718 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6721 ntuple_filter->queue = filter->queue;
6726 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6727 * @dev: pointer to rte_eth_dev structure
6728 * @filter_op:operation will be taken.
6729 * @arg: a pointer to specific structure corresponding to the filter_op
6732 * - On success, zero.
6733 * - On failure, a negative value.
6736 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6737 enum rte_filter_op filter_op,
6740 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6743 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6745 if (filter_op == RTE_ETH_FILTER_NOP)
6749 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6754 switch (filter_op) {
6755 case RTE_ETH_FILTER_ADD:
6756 ret = ixgbe_add_del_ntuple_filter(dev,
6757 (struct rte_eth_ntuple_filter *)arg,
6760 case RTE_ETH_FILTER_DELETE:
6761 ret = ixgbe_add_del_ntuple_filter(dev,
6762 (struct rte_eth_ntuple_filter *)arg,
6765 case RTE_ETH_FILTER_GET:
6766 ret = ixgbe_get_ntuple_filter(dev,
6767 (struct rte_eth_ntuple_filter *)arg);
6770 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6778 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6779 struct rte_eth_ethertype_filter *filter,
6782 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783 struct ixgbe_filter_info *filter_info =
6784 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6788 struct ixgbe_ethertype_filter ethertype_filter;
6790 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6793 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6794 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6795 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6796 " ethertype filter.", filter->ether_type);
6800 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6801 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6804 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6805 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6809 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6810 if (ret >= 0 && add) {
6811 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6812 filter->ether_type);
6815 if (ret < 0 && !add) {
6816 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6817 filter->ether_type);
6822 etqf = IXGBE_ETQF_FILTER_EN;
6823 etqf |= (uint32_t)filter->ether_type;
6824 etqs |= (uint32_t)((filter->queue <<
6825 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6826 IXGBE_ETQS_RX_QUEUE);
6827 etqs |= IXGBE_ETQS_QUEUE_EN;
6829 ethertype_filter.ethertype = filter->ether_type;
6830 ethertype_filter.etqf = etqf;
6831 ethertype_filter.etqs = etqs;
6832 ethertype_filter.conf = FALSE;
6833 ret = ixgbe_ethertype_filter_insert(filter_info,
6836 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6840 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6844 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6845 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6846 IXGBE_WRITE_FLUSH(hw);
6852 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6853 struct rte_eth_ethertype_filter *filter)
6855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6856 struct ixgbe_filter_info *filter_info =
6857 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6858 uint32_t etqf, etqs;
6861 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6863 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6864 filter->ether_type);
6868 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6869 if (etqf & IXGBE_ETQF_FILTER_EN) {
6870 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6871 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6873 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6874 IXGBE_ETQS_RX_QUEUE_SHIFT;
6881 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6882 * @dev: pointer to rte_eth_dev structure
6883 * @filter_op:operation will be taken.
6884 * @arg: a pointer to specific structure corresponding to the filter_op
6887 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6888 enum rte_filter_op filter_op,
6891 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6894 MAC_TYPE_FILTER_SUP(hw->mac.type);
6896 if (filter_op == RTE_ETH_FILTER_NOP)
6900 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6905 switch (filter_op) {
6906 case RTE_ETH_FILTER_ADD:
6907 ret = ixgbe_add_del_ethertype_filter(dev,
6908 (struct rte_eth_ethertype_filter *)arg,
6911 case RTE_ETH_FILTER_DELETE:
6912 ret = ixgbe_add_del_ethertype_filter(dev,
6913 (struct rte_eth_ethertype_filter *)arg,
6916 case RTE_ETH_FILTER_GET:
6917 ret = ixgbe_get_ethertype_filter(dev,
6918 (struct rte_eth_ethertype_filter *)arg);
6921 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6929 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6930 enum rte_filter_type filter_type,
6931 enum rte_filter_op filter_op,
6936 switch (filter_type) {
6937 case RTE_ETH_FILTER_NTUPLE:
6938 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6940 case RTE_ETH_FILTER_ETHERTYPE:
6941 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6943 case RTE_ETH_FILTER_SYN:
6944 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6946 case RTE_ETH_FILTER_FDIR:
6947 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6949 case RTE_ETH_FILTER_L2_TUNNEL:
6950 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6952 case RTE_ETH_FILTER_GENERIC:
6953 if (filter_op != RTE_ETH_FILTER_GET)
6955 *(const void **)arg = &ixgbe_flow_ops;
6958 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6968 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6969 u8 **mc_addr_ptr, u32 *vmdq)
6974 mc_addr = *mc_addr_ptr;
6975 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6980 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6981 struct rte_ether_addr *mc_addr_set,
6982 uint32_t nb_mc_addr)
6984 struct ixgbe_hw *hw;
6987 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6988 mc_addr_list = (u8 *)mc_addr_set;
6989 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6990 ixgbe_dev_addr_list_itr, TRUE);
6994 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6997 uint64_t systime_cycles;
6999 switch (hw->mac.type) {
7000 case ixgbe_mac_X550:
7001 case ixgbe_mac_X550EM_x:
7002 case ixgbe_mac_X550EM_a:
7003 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7004 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7005 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7009 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7010 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7014 return systime_cycles;
7018 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7020 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7021 uint64_t rx_tstamp_cycles;
7023 switch (hw->mac.type) {
7024 case ixgbe_mac_X550:
7025 case ixgbe_mac_X550EM_x:
7026 case ixgbe_mac_X550EM_a:
7027 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7028 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7029 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7033 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7034 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7035 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7039 return rx_tstamp_cycles;
7043 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7046 uint64_t tx_tstamp_cycles;
7048 switch (hw->mac.type) {
7049 case ixgbe_mac_X550:
7050 case ixgbe_mac_X550EM_x:
7051 case ixgbe_mac_X550EM_a:
7052 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7053 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7054 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7058 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7059 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7060 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7064 return tx_tstamp_cycles;
7068 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7070 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7071 struct ixgbe_adapter *adapter = dev->data->dev_private;
7072 struct rte_eth_link link;
7073 uint32_t incval = 0;
7076 /* Get current link speed. */
7077 ixgbe_dev_link_update(dev, 1);
7078 rte_eth_linkstatus_get(dev, &link);
7080 switch (link.link_speed) {
7081 case ETH_SPEED_NUM_100M:
7082 incval = IXGBE_INCVAL_100;
7083 shift = IXGBE_INCVAL_SHIFT_100;
7085 case ETH_SPEED_NUM_1G:
7086 incval = IXGBE_INCVAL_1GB;
7087 shift = IXGBE_INCVAL_SHIFT_1GB;
7089 case ETH_SPEED_NUM_10G:
7091 incval = IXGBE_INCVAL_10GB;
7092 shift = IXGBE_INCVAL_SHIFT_10GB;
7096 switch (hw->mac.type) {
7097 case ixgbe_mac_X550:
7098 case ixgbe_mac_X550EM_x:
7099 case ixgbe_mac_X550EM_a:
7100 /* Independent of link speed. */
7102 /* Cycles read will be interpreted as ns. */
7105 case ixgbe_mac_X540:
7106 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7108 case ixgbe_mac_82599EB:
7109 incval >>= IXGBE_INCVAL_SHIFT_82599;
7110 shift -= IXGBE_INCVAL_SHIFT_82599;
7111 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7112 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7115 /* Not supported. */
7119 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7120 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7121 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7123 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7124 adapter->systime_tc.cc_shift = shift;
7125 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7127 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7128 adapter->rx_tstamp_tc.cc_shift = shift;
7129 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7131 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7132 adapter->tx_tstamp_tc.cc_shift = shift;
7133 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7137 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7139 struct ixgbe_adapter *adapter = dev->data->dev_private;
7141 adapter->systime_tc.nsec += delta;
7142 adapter->rx_tstamp_tc.nsec += delta;
7143 adapter->tx_tstamp_tc.nsec += delta;
7149 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7152 struct ixgbe_adapter *adapter = dev->data->dev_private;
7154 ns = rte_timespec_to_ns(ts);
7155 /* Set the timecounters to a new value. */
7156 adapter->systime_tc.nsec = ns;
7157 adapter->rx_tstamp_tc.nsec = ns;
7158 adapter->tx_tstamp_tc.nsec = ns;
7164 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7166 uint64_t ns, systime_cycles;
7167 struct ixgbe_adapter *adapter = dev->data->dev_private;
7169 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7170 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7171 *ts = rte_ns_to_timespec(ns);
7177 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7179 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7183 /* Stop the timesync system time. */
7184 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7185 /* Reset the timesync system time value. */
7186 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7187 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7189 /* Enable system time for platforms where it isn't on by default. */
7190 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7191 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7192 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7194 ixgbe_start_timecounters(dev);
7196 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7197 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7198 (RTE_ETHER_TYPE_1588 |
7199 IXGBE_ETQF_FILTER_EN |
7202 /* Enable timestamping of received PTP packets. */
7203 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7204 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7205 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7207 /* Enable timestamping of transmitted PTP packets. */
7208 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7209 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7210 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7212 IXGBE_WRITE_FLUSH(hw);
7218 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223 /* Disable timestamping of transmitted PTP packets. */
7224 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7225 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7226 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7228 /* Disable timestamping of received PTP packets. */
7229 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7230 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7231 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7233 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7234 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7236 /* Stop incrementating the System Time registers. */
7237 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7243 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7244 struct timespec *timestamp,
7245 uint32_t flags __rte_unused)
7247 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7248 struct ixgbe_adapter *adapter = dev->data->dev_private;
7249 uint32_t tsync_rxctl;
7250 uint64_t rx_tstamp_cycles;
7253 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7254 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7257 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7258 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7259 *timestamp = rte_ns_to_timespec(ns);
7265 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7266 struct timespec *timestamp)
7268 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7269 struct ixgbe_adapter *adapter = dev->data->dev_private;
7270 uint32_t tsync_txctl;
7271 uint64_t tx_tstamp_cycles;
7274 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7275 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7278 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7279 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7280 *timestamp = rte_ns_to_timespec(ns);
7286 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7288 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7291 const struct reg_info *reg_group;
7292 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7293 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7295 while ((reg_group = reg_set[g_ind++]))
7296 count += ixgbe_regs_group_count(reg_group);
7302 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7306 const struct reg_info *reg_group;
7308 while ((reg_group = ixgbevf_regs[g_ind++]))
7309 count += ixgbe_regs_group_count(reg_group);
7315 ixgbe_get_regs(struct rte_eth_dev *dev,
7316 struct rte_dev_reg_info *regs)
7318 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7319 uint32_t *data = regs->data;
7322 const struct reg_info *reg_group;
7323 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7324 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7327 regs->length = ixgbe_get_reg_length(dev);
7328 regs->width = sizeof(uint32_t);
7332 /* Support only full register dump */
7333 if ((regs->length == 0) ||
7334 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7335 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7337 while ((reg_group = reg_set[g_ind++]))
7338 count += ixgbe_read_regs_group(dev, &data[count],
7347 ixgbevf_get_regs(struct rte_eth_dev *dev,
7348 struct rte_dev_reg_info *regs)
7350 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7351 uint32_t *data = regs->data;
7354 const struct reg_info *reg_group;
7357 regs->length = ixgbevf_get_reg_length(dev);
7358 regs->width = sizeof(uint32_t);
7362 /* Support only full register dump */
7363 if ((regs->length == 0) ||
7364 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7365 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7367 while ((reg_group = ixgbevf_regs[g_ind++]))
7368 count += ixgbe_read_regs_group(dev, &data[count],
7377 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7379 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7381 /* Return unit is byte count */
7382 return hw->eeprom.word_size * 2;
7386 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7387 struct rte_dev_eeprom_info *in_eeprom)
7389 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7390 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7391 uint16_t *data = in_eeprom->data;
7394 first = in_eeprom->offset >> 1;
7395 length = in_eeprom->length >> 1;
7396 if ((first > hw->eeprom.word_size) ||
7397 ((first + length) > hw->eeprom.word_size))
7400 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7402 return eeprom->ops.read_buffer(hw, first, length, data);
7406 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7407 struct rte_dev_eeprom_info *in_eeprom)
7409 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7410 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7411 uint16_t *data = in_eeprom->data;
7414 first = in_eeprom->offset >> 1;
7415 length = in_eeprom->length >> 1;
7416 if ((first > hw->eeprom.word_size) ||
7417 ((first + length) > hw->eeprom.word_size))
7420 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7422 return eeprom->ops.write_buffer(hw, first, length, data);
7426 ixgbe_get_module_info(struct rte_eth_dev *dev,
7427 struct rte_eth_dev_module_info *modinfo)
7429 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7431 uint8_t sff8472_rev, addr_mode;
7432 bool page_swap = false;
7434 /* Check whether we support SFF-8472 or not */
7435 status = hw->phy.ops.read_i2c_eeprom(hw,
7436 IXGBE_SFF_SFF_8472_COMP,
7441 /* addressing mode is not supported */
7442 status = hw->phy.ops.read_i2c_eeprom(hw,
7443 IXGBE_SFF_SFF_8472_SWAP,
7448 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7450 "Address change required to access page 0xA2, "
7451 "but not supported. Please report the module "
7452 "type to the driver maintainers.");
7456 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7457 /* We have a SFP, but it does not support SFF-8472 */
7458 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7459 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7461 /* We have a SFP which supports a revision of SFF-8472. */
7462 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7463 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7470 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7471 struct rte_dev_eeprom_info *info)
7473 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7474 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7475 uint8_t databyte = 0xFF;
7476 uint8_t *data = info->data;
7479 if (info->length == 0)
7482 for (i = info->offset; i < info->offset + info->length; i++) {
7483 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7484 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7486 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7491 data[i - info->offset] = databyte;
7498 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7500 case ixgbe_mac_X550:
7501 case ixgbe_mac_X550EM_x:
7502 case ixgbe_mac_X550EM_a:
7503 return ETH_RSS_RETA_SIZE_512;
7504 case ixgbe_mac_X550_vf:
7505 case ixgbe_mac_X550EM_x_vf:
7506 case ixgbe_mac_X550EM_a_vf:
7507 return ETH_RSS_RETA_SIZE_64;
7508 case ixgbe_mac_X540_vf:
7509 case ixgbe_mac_82599_vf:
7512 return ETH_RSS_RETA_SIZE_128;
7517 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7519 case ixgbe_mac_X550:
7520 case ixgbe_mac_X550EM_x:
7521 case ixgbe_mac_X550EM_a:
7522 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7523 return IXGBE_RETA(reta_idx >> 2);
7525 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7526 case ixgbe_mac_X550_vf:
7527 case ixgbe_mac_X550EM_x_vf:
7528 case ixgbe_mac_X550EM_a_vf:
7529 return IXGBE_VFRETA(reta_idx >> 2);
7531 return IXGBE_RETA(reta_idx >> 2);
7536 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7538 case ixgbe_mac_X550_vf:
7539 case ixgbe_mac_X550EM_x_vf:
7540 case ixgbe_mac_X550EM_a_vf:
7541 return IXGBE_VFMRQC;
7548 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7550 case ixgbe_mac_X550_vf:
7551 case ixgbe_mac_X550EM_x_vf:
7552 case ixgbe_mac_X550EM_a_vf:
7553 return IXGBE_VFRSSRK(i);
7555 return IXGBE_RSSRK(i);
7560 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7562 case ixgbe_mac_82599_vf:
7563 case ixgbe_mac_X540_vf:
7571 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7572 struct rte_eth_dcb_info *dcb_info)
7574 struct ixgbe_dcb_config *dcb_config =
7575 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7576 struct ixgbe_dcb_tc_config *tc;
7577 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7581 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7582 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7584 dcb_info->nb_tcs = 1;
7586 tc_queue = &dcb_info->tc_queue;
7587 nb_tcs = dcb_info->nb_tcs;
7589 if (dcb_config->vt_mode) { /* vt is enabled*/
7590 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7591 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7592 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7593 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7594 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7595 for (j = 0; j < nb_tcs; j++) {
7596 tc_queue->tc_rxq[0][j].base = j;
7597 tc_queue->tc_rxq[0][j].nb_queue = 1;
7598 tc_queue->tc_txq[0][j].base = j;
7599 tc_queue->tc_txq[0][j].nb_queue = 1;
7602 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7603 for (j = 0; j < nb_tcs; j++) {
7604 tc_queue->tc_rxq[i][j].base =
7606 tc_queue->tc_rxq[i][j].nb_queue = 1;
7607 tc_queue->tc_txq[i][j].base =
7609 tc_queue->tc_txq[i][j].nb_queue = 1;
7613 } else { /* vt is disabled*/
7614 struct rte_eth_dcb_rx_conf *rx_conf =
7615 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7616 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7617 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7618 if (dcb_info->nb_tcs == ETH_4_TCS) {
7619 for (i = 0; i < dcb_info->nb_tcs; i++) {
7620 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7621 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7623 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7624 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7625 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7626 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7627 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7628 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7629 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7630 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7631 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7632 for (i = 0; i < dcb_info->nb_tcs; i++) {
7633 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7634 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7636 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7637 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7638 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7639 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7640 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7641 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7642 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7643 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7644 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7645 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7646 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7647 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7648 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7649 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7650 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7651 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7654 for (i = 0; i < dcb_info->nb_tcs; i++) {
7655 tc = &dcb_config->tc_config[i];
7656 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7661 /* Update e-tag ether type */
7663 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7664 uint16_t ether_type)
7666 uint32_t etag_etype;
7668 if (hw->mac.type != ixgbe_mac_X550 &&
7669 hw->mac.type != ixgbe_mac_X550EM_x &&
7670 hw->mac.type != ixgbe_mac_X550EM_a) {
7674 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7675 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7676 etag_etype |= ether_type;
7677 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7678 IXGBE_WRITE_FLUSH(hw);
7683 /* Config l2 tunnel ether type */
7685 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7686 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7689 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7690 struct ixgbe_l2_tn_info *l2_tn_info =
7691 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7693 if (l2_tunnel == NULL)
7696 switch (l2_tunnel->l2_tunnel_type) {
7697 case RTE_L2_TUNNEL_TYPE_E_TAG:
7698 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7699 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7702 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7710 /* Enable e-tag tunnel */
7712 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7714 uint32_t etag_etype;
7716 if (hw->mac.type != ixgbe_mac_X550 &&
7717 hw->mac.type != ixgbe_mac_X550EM_x &&
7718 hw->mac.type != ixgbe_mac_X550EM_a) {
7722 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7723 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7724 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7725 IXGBE_WRITE_FLUSH(hw);
7730 /* Enable l2 tunnel */
7732 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7733 enum rte_eth_tunnel_type l2_tunnel_type)
7736 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7737 struct ixgbe_l2_tn_info *l2_tn_info =
7738 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7740 switch (l2_tunnel_type) {
7741 case RTE_L2_TUNNEL_TYPE_E_TAG:
7742 l2_tn_info->e_tag_en = TRUE;
7743 ret = ixgbe_e_tag_enable(hw);
7746 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7754 /* Disable e-tag tunnel */
7756 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7758 uint32_t etag_etype;
7760 if (hw->mac.type != ixgbe_mac_X550 &&
7761 hw->mac.type != ixgbe_mac_X550EM_x &&
7762 hw->mac.type != ixgbe_mac_X550EM_a) {
7766 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7767 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7768 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7769 IXGBE_WRITE_FLUSH(hw);
7774 /* Disable l2 tunnel */
7776 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7777 enum rte_eth_tunnel_type l2_tunnel_type)
7780 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7781 struct ixgbe_l2_tn_info *l2_tn_info =
7782 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7784 switch (l2_tunnel_type) {
7785 case RTE_L2_TUNNEL_TYPE_E_TAG:
7786 l2_tn_info->e_tag_en = FALSE;
7787 ret = ixgbe_e_tag_disable(hw);
7790 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7799 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7800 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7803 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7804 uint32_t i, rar_entries;
7805 uint32_t rar_low, rar_high;
7807 if (hw->mac.type != ixgbe_mac_X550 &&
7808 hw->mac.type != ixgbe_mac_X550EM_x &&
7809 hw->mac.type != ixgbe_mac_X550EM_a) {
7813 rar_entries = ixgbe_get_num_rx_addrs(hw);
7815 for (i = 1; i < rar_entries; i++) {
7816 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7817 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7818 if ((rar_high & IXGBE_RAH_AV) &&
7819 (rar_high & IXGBE_RAH_ADTYPE) &&
7820 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7821 l2_tunnel->tunnel_id)) {
7822 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7823 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7825 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7835 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7836 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7839 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7840 uint32_t i, rar_entries;
7841 uint32_t rar_low, rar_high;
7843 if (hw->mac.type != ixgbe_mac_X550 &&
7844 hw->mac.type != ixgbe_mac_X550EM_x &&
7845 hw->mac.type != ixgbe_mac_X550EM_a) {
7849 /* One entry for one tunnel. Try to remove potential existing entry. */
7850 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7852 rar_entries = ixgbe_get_num_rx_addrs(hw);
7854 for (i = 1; i < rar_entries; i++) {
7855 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7856 if (rar_high & IXGBE_RAH_AV) {
7859 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7860 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7861 rar_low = l2_tunnel->tunnel_id;
7863 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7864 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7870 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7871 " Please remove a rule before adding a new one.");
7875 static inline struct ixgbe_l2_tn_filter *
7876 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7877 struct ixgbe_l2_tn_key *key)
7881 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7885 return l2_tn_info->hash_map[ret];
7889 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7890 struct ixgbe_l2_tn_filter *l2_tn_filter)
7894 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7895 &l2_tn_filter->key);
7899 "Failed to insert L2 tunnel filter"
7900 " to hash table %d!",
7905 l2_tn_info->hash_map[ret] = l2_tn_filter;
7907 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7913 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7914 struct ixgbe_l2_tn_key *key)
7917 struct ixgbe_l2_tn_filter *l2_tn_filter;
7919 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7923 "No such L2 tunnel filter to delete %d!",
7928 l2_tn_filter = l2_tn_info->hash_map[ret];
7929 l2_tn_info->hash_map[ret] = NULL;
7931 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7932 rte_free(l2_tn_filter);
7937 /* Add l2 tunnel filter */
7939 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7940 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7944 struct ixgbe_l2_tn_info *l2_tn_info =
7945 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7946 struct ixgbe_l2_tn_key key;
7947 struct ixgbe_l2_tn_filter *node;
7950 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7951 key.tn_id = l2_tunnel->tunnel_id;
7953 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7957 "The L2 tunnel filter already exists!");
7961 node = rte_zmalloc("ixgbe_l2_tn",
7962 sizeof(struct ixgbe_l2_tn_filter),
7967 rte_memcpy(&node->key,
7969 sizeof(struct ixgbe_l2_tn_key));
7970 node->pool = l2_tunnel->pool;
7971 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7978 switch (l2_tunnel->l2_tunnel_type) {
7979 case RTE_L2_TUNNEL_TYPE_E_TAG:
7980 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7983 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7988 if ((!restore) && (ret < 0))
7989 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7994 /* Delete l2 tunnel filter */
7996 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7997 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8000 struct ixgbe_l2_tn_info *l2_tn_info =
8001 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8002 struct ixgbe_l2_tn_key key;
8004 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8005 key.tn_id = l2_tunnel->tunnel_id;
8006 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8010 switch (l2_tunnel->l2_tunnel_type) {
8011 case RTE_L2_TUNNEL_TYPE_E_TAG:
8012 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8015 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8024 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8025 * @dev: pointer to rte_eth_dev structure
8026 * @filter_op:operation will be taken.
8027 * @arg: a pointer to specific structure corresponding to the filter_op
8030 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8031 enum rte_filter_op filter_op,
8036 if (filter_op == RTE_ETH_FILTER_NOP)
8040 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8045 switch (filter_op) {
8046 case RTE_ETH_FILTER_ADD:
8047 ret = ixgbe_dev_l2_tunnel_filter_add
8049 (struct rte_eth_l2_tunnel_conf *)arg,
8052 case RTE_ETH_FILTER_DELETE:
8053 ret = ixgbe_dev_l2_tunnel_filter_del
8055 (struct rte_eth_l2_tunnel_conf *)arg);
8058 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8066 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8070 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8072 if (hw->mac.type != ixgbe_mac_X550 &&
8073 hw->mac.type != ixgbe_mac_X550EM_x &&
8074 hw->mac.type != ixgbe_mac_X550EM_a) {
8078 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8079 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8081 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8082 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8087 /* Enable l2 tunnel forwarding */
8089 ixgbe_dev_l2_tunnel_forwarding_enable
8090 (struct rte_eth_dev *dev,
8091 enum rte_eth_tunnel_type l2_tunnel_type)
8093 struct ixgbe_l2_tn_info *l2_tn_info =
8094 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8097 switch (l2_tunnel_type) {
8098 case RTE_L2_TUNNEL_TYPE_E_TAG:
8099 l2_tn_info->e_tag_fwd_en = TRUE;
8100 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8103 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8111 /* Disable l2 tunnel forwarding */
8113 ixgbe_dev_l2_tunnel_forwarding_disable
8114 (struct rte_eth_dev *dev,
8115 enum rte_eth_tunnel_type l2_tunnel_type)
8117 struct ixgbe_l2_tn_info *l2_tn_info =
8118 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8121 switch (l2_tunnel_type) {
8122 case RTE_L2_TUNNEL_TYPE_E_TAG:
8123 l2_tn_info->e_tag_fwd_en = FALSE;
8124 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8127 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8136 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8137 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8140 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8142 uint32_t vmtir, vmvir;
8143 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8145 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8147 "VF id %u should be less than %u",
8153 if (hw->mac.type != ixgbe_mac_X550 &&
8154 hw->mac.type != ixgbe_mac_X550EM_x &&
8155 hw->mac.type != ixgbe_mac_X550EM_a) {
8160 vmtir = l2_tunnel->tunnel_id;
8164 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8166 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8167 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8169 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8170 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8175 /* Enable l2 tunnel tag insertion */
8177 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8178 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8182 switch (l2_tunnel->l2_tunnel_type) {
8183 case RTE_L2_TUNNEL_TYPE_E_TAG:
8184 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8187 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8195 /* Disable l2 tunnel tag insertion */
8197 ixgbe_dev_l2_tunnel_insertion_disable
8198 (struct rte_eth_dev *dev,
8199 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8203 switch (l2_tunnel->l2_tunnel_type) {
8204 case RTE_L2_TUNNEL_TYPE_E_TAG:
8205 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8208 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8217 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8222 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8224 if (hw->mac.type != ixgbe_mac_X550 &&
8225 hw->mac.type != ixgbe_mac_X550EM_x &&
8226 hw->mac.type != ixgbe_mac_X550EM_a) {
8230 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8232 qde |= IXGBE_QDE_STRIP_TAG;
8234 qde &= ~IXGBE_QDE_STRIP_TAG;
8235 qde &= ~IXGBE_QDE_READ;
8236 qde |= IXGBE_QDE_WRITE;
8237 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8242 /* Enable l2 tunnel tag stripping */
8244 ixgbe_dev_l2_tunnel_stripping_enable
8245 (struct rte_eth_dev *dev,
8246 enum rte_eth_tunnel_type l2_tunnel_type)
8250 switch (l2_tunnel_type) {
8251 case RTE_L2_TUNNEL_TYPE_E_TAG:
8252 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8255 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8263 /* Disable l2 tunnel tag stripping */
8265 ixgbe_dev_l2_tunnel_stripping_disable
8266 (struct rte_eth_dev *dev,
8267 enum rte_eth_tunnel_type l2_tunnel_type)
8271 switch (l2_tunnel_type) {
8272 case RTE_L2_TUNNEL_TYPE_E_TAG:
8273 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8276 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8284 /* Enable/disable l2 tunnel offload functions */
8286 ixgbe_dev_l2_tunnel_offload_set
8287 (struct rte_eth_dev *dev,
8288 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8294 if (l2_tunnel == NULL)
8298 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8300 ret = ixgbe_dev_l2_tunnel_enable(
8302 l2_tunnel->l2_tunnel_type);
8304 ret = ixgbe_dev_l2_tunnel_disable(
8306 l2_tunnel->l2_tunnel_type);
8309 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8311 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8315 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8320 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8322 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8324 l2_tunnel->l2_tunnel_type);
8326 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8328 l2_tunnel->l2_tunnel_type);
8331 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8333 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8335 l2_tunnel->l2_tunnel_type);
8337 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8339 l2_tunnel->l2_tunnel_type);
8346 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8349 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8350 IXGBE_WRITE_FLUSH(hw);
8355 /* There's only one register for VxLAN UDP port.
8356 * So, we cannot add several ports. Will update it.
8359 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8363 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8367 return ixgbe_update_vxlan_port(hw, port);
8370 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8371 * UDP port, it must have a value.
8372 * So, will reset it to the original value 0.
8375 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8380 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8382 if (cur_port != port) {
8383 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8387 return ixgbe_update_vxlan_port(hw, 0);
8390 /* Add UDP tunneling port */
8392 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8393 struct rte_eth_udp_tunnel *udp_tunnel)
8396 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8398 if (hw->mac.type != ixgbe_mac_X550 &&
8399 hw->mac.type != ixgbe_mac_X550EM_x &&
8400 hw->mac.type != ixgbe_mac_X550EM_a) {
8404 if (udp_tunnel == NULL)
8407 switch (udp_tunnel->prot_type) {
8408 case RTE_TUNNEL_TYPE_VXLAN:
8409 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8412 case RTE_TUNNEL_TYPE_GENEVE:
8413 case RTE_TUNNEL_TYPE_TEREDO:
8414 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8419 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8427 /* Remove UDP tunneling port */
8429 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8430 struct rte_eth_udp_tunnel *udp_tunnel)
8433 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8435 if (hw->mac.type != ixgbe_mac_X550 &&
8436 hw->mac.type != ixgbe_mac_X550EM_x &&
8437 hw->mac.type != ixgbe_mac_X550EM_a) {
8441 if (udp_tunnel == NULL)
8444 switch (udp_tunnel->prot_type) {
8445 case RTE_TUNNEL_TYPE_VXLAN:
8446 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8448 case RTE_TUNNEL_TYPE_GENEVE:
8449 case RTE_TUNNEL_TYPE_TEREDO:
8450 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8454 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8463 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8465 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8468 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8472 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8484 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8486 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8489 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8493 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8505 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8507 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8509 int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8511 switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8515 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8527 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8529 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8532 switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8536 case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8547 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8549 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8552 /* peek the message first */
8553 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8555 /* PF reset VF event */
8556 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8557 /* dummy mbx read to ack pf */
8558 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8560 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8566 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8569 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8570 struct ixgbe_interrupt *intr =
8571 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8572 ixgbevf_intr_disable(dev);
8574 /* read-on-clear nic registers here */
8575 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8578 /* only one misc vector supported - mailbox */
8579 eicr &= IXGBE_VTEICR_MASK;
8580 if (eicr == IXGBE_MISC_VEC_ID)
8581 intr->flags |= IXGBE_FLAG_MAILBOX;
8587 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8589 struct ixgbe_interrupt *intr =
8590 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8592 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8593 ixgbevf_mbx_process(dev);
8594 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8597 ixgbevf_intr_enable(dev);
8603 ixgbevf_dev_interrupt_handler(void *param)
8605 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8607 ixgbevf_dev_interrupt_get_status(dev);
8608 ixgbevf_dev_interrupt_action(dev);
8612 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8613 * @hw: pointer to hardware structure
8615 * Stops the transmit data path and waits for the HW to internally empty
8616 * the Tx security block
8618 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8620 #define IXGBE_MAX_SECTX_POLL 40
8625 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8626 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8627 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8628 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8629 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8630 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8632 /* Use interrupt-safe sleep just in case */
8636 /* For informational purposes only */
8637 if (i >= IXGBE_MAX_SECTX_POLL)
8638 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8639 "path fully disabled. Continuing with init.");
8641 return IXGBE_SUCCESS;
8645 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8646 * @hw: pointer to hardware structure
8648 * Enables the transmit data path.
8650 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8654 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8655 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8656 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8657 IXGBE_WRITE_FLUSH(hw);
8659 return IXGBE_SUCCESS;
8662 /* restore n-tuple filter */
8664 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8666 struct ixgbe_filter_info *filter_info =
8667 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8668 struct ixgbe_5tuple_filter *node;
8670 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8671 ixgbe_inject_5tuple_filter(dev, node);
8675 /* restore ethernet type filter */
8677 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8679 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8680 struct ixgbe_filter_info *filter_info =
8681 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8684 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8685 if (filter_info->ethertype_mask & (1 << i)) {
8686 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8687 filter_info->ethertype_filters[i].etqf);
8688 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8689 filter_info->ethertype_filters[i].etqs);
8690 IXGBE_WRITE_FLUSH(hw);
8695 /* restore SYN filter */
8697 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8699 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8700 struct ixgbe_filter_info *filter_info =
8701 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8704 synqf = filter_info->syn_info;
8706 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8707 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8708 IXGBE_WRITE_FLUSH(hw);
8712 /* restore L2 tunnel filter */
8714 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8716 struct ixgbe_l2_tn_info *l2_tn_info =
8717 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8718 struct ixgbe_l2_tn_filter *node;
8719 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8721 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8722 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8723 l2_tn_conf.tunnel_id = node->key.tn_id;
8724 l2_tn_conf.pool = node->pool;
8725 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8729 /* restore rss filter */
8731 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8733 struct ixgbe_filter_info *filter_info =
8734 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8736 if (filter_info->rss_info.conf.queue_num)
8737 ixgbe_config_rss_filter(dev,
8738 &filter_info->rss_info, TRUE);
8742 ixgbe_filter_restore(struct rte_eth_dev *dev)
8744 ixgbe_ntuple_filter_restore(dev);
8745 ixgbe_ethertype_filter_restore(dev);
8746 ixgbe_syn_filter_restore(dev);
8747 ixgbe_fdir_filter_restore(dev);
8748 ixgbe_l2_tn_filter_restore(dev);
8749 ixgbe_rss_filter_restore(dev);
8755 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8757 struct ixgbe_l2_tn_info *l2_tn_info =
8758 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8759 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8761 if (l2_tn_info->e_tag_en)
8762 (void)ixgbe_e_tag_enable(hw);
8764 if (l2_tn_info->e_tag_fwd_en)
8765 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8767 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8770 /* remove all the n-tuple filters */
8772 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8774 struct ixgbe_filter_info *filter_info =
8775 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8776 struct ixgbe_5tuple_filter *p_5tuple;
8778 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8779 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8782 /* remove all the ether type filters */
8784 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8786 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8787 struct ixgbe_filter_info *filter_info =
8788 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8791 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8792 if (filter_info->ethertype_mask & (1 << i) &&
8793 !filter_info->ethertype_filters[i].conf) {
8794 (void)ixgbe_ethertype_filter_remove(filter_info,
8796 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8797 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8798 IXGBE_WRITE_FLUSH(hw);
8803 /* remove the SYN filter */
8805 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8808 struct ixgbe_filter_info *filter_info =
8809 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8811 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8812 filter_info->syn_info = 0;
8814 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8815 IXGBE_WRITE_FLUSH(hw);
8819 /* remove all the L2 tunnel filters */
8821 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8823 struct ixgbe_l2_tn_info *l2_tn_info =
8824 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8825 struct ixgbe_l2_tn_filter *l2_tn_filter;
8826 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8829 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8830 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8831 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8832 l2_tn_conf.pool = l2_tn_filter->pool;
8833 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8842 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8843 struct ixgbe_macsec_setting *macsec_setting)
8845 struct ixgbe_macsec_setting *macsec =
8846 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8848 macsec->encrypt_en = macsec_setting->encrypt_en;
8849 macsec->replayprotect_en = macsec_setting->replayprotect_en;
8853 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8855 struct ixgbe_macsec_setting *macsec =
8856 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8858 macsec->encrypt_en = 0;
8859 macsec->replayprotect_en = 0;
8863 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8864 struct ixgbe_macsec_setting *macsec_setting)
8866 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8868 uint8_t en = macsec_setting->encrypt_en;
8869 uint8_t rp = macsec_setting->replayprotect_en;
8873 * As no ixgbe_disable_sec_rx_path equivalent is
8874 * implemented for tx in the base code, and we are
8875 * not allowed to modify the base code in DPDK, so
8876 * just call the hand-written one directly for now.
8877 * The hardware support has been checked by
8878 * ixgbe_disable_sec_rx_path().
8880 ixgbe_disable_sec_tx_path_generic(hw);
8882 /* Enable Ethernet CRC (required by MACsec offload) */
8883 ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8884 ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8885 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8887 /* Enable the TX and RX crypto engines */
8888 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8889 ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8890 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8892 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8893 ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8894 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8896 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8897 ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8899 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8901 /* Enable SA lookup */
8902 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8903 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8904 ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8905 IXGBE_LSECTXCTRL_AUTH;
8906 ctrl |= IXGBE_LSECTXCTRL_AISCI;
8907 ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8908 ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8909 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8911 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8912 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8913 ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8914 ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8916 ctrl |= IXGBE_LSECRXCTRL_RP;
8918 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8919 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8921 /* Start the data paths */
8922 ixgbe_enable_sec_rx_path(hw);
8925 * As no ixgbe_enable_sec_rx_path equivalent is
8926 * implemented for tx in the base code, and we are
8927 * not allowed to modify the base code in DPDK, so
8928 * just call the hand-written one directly for now.
8930 ixgbe_enable_sec_tx_path_generic(hw);
8934 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8936 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8941 * As no ixgbe_disable_sec_rx_path equivalent is
8942 * implemented for tx in the base code, and we are
8943 * not allowed to modify the base code in DPDK, so
8944 * just call the hand-written one directly for now.
8945 * The hardware support has been checked by
8946 * ixgbe_disable_sec_rx_path().
8948 ixgbe_disable_sec_tx_path_generic(hw);
8950 /* Disable the TX and RX crypto engines */
8951 ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8952 ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8953 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8955 ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8956 ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8957 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8959 /* Disable SA lookup */
8960 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8961 ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8962 ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8963 IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8965 ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8966 ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8967 ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8968 IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8970 /* Start the data paths */
8971 ixgbe_enable_sec_rx_path(hw);
8974 * As no ixgbe_enable_sec_rx_path equivalent is
8975 * implemented for tx in the base code, and we are
8976 * not allowed to modify the base code in DPDK, so
8977 * just call the hand-written one directly for now.
8979 ixgbe_enable_sec_tx_path_generic(hw);
8982 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8983 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8984 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8985 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8986 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8987 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8988 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8989 IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8991 RTE_INIT(ixgbe_init_log)
8993 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8994 if (ixgbe_logtype_init >= 0)
8995 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8996 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8997 if (ixgbe_logtype_driver >= 0)
8998 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8999 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9000 ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9001 if (ixgbe_logtype_rx >= 0)
9002 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9005 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9006 ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9007 if (ixgbe_logtype_tx >= 0)
9008 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9011 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9012 ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9013 if (ixgbe_logtype_tx_free >= 0)
9014 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);