drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 233
 234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 235                         struct rte_ether_addr *mac_addr,
 236                         uint32_t index, uint32_t pool);
 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 239                                            struct rte_ether_addr *mac_addr);
 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 241 static bool is_device_supported(struct rte_eth_dev *dev,
 242                                 struct rte_pci_driver *drv);
 243
 244 /* For Virtual Function support */
 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 248 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 250                                    int wait_to_complete);
 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 277
 278 /* For Eth VMDQ APIs support */
 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 280                 rte_ether_addr * mac_addr, uint8_t on);
 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 283                 struct rte_eth_mirror_conf *mirror_conf,
 284                 uint8_t rule_id, uint8_t on);
 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 286                 uint8_t rule_id);
 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 288                                           uint16_t queue_id);
 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 290                                            uint16_t queue_id);
 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 292                                uint8_t queue, uint8_t msix_vector);
 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 294
 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 296                                 struct rte_ether_addr *mac_addr,
 297                                 uint32_t index, uint32_t pool);
 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 300                                              struct rte_ether_addr *mac_addr);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 311                                 enum rte_filter_op filter_op,
 312                                 void *arg);
 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 314                         struct rte_eth_ntuple_filter *filter);
 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter);
 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 321                      enum rte_filter_type filter_type,
 322                      enum rte_filter_op filter_op,
 323                      void *arg);
 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 325
 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 327                                       struct rte_ether_addr *mc_addr_set,
 328                                       uint32_t nb_mc_addr);
 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                    struct rte_eth_dcb_info *dcb_info);
 331
 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 334                             struct rte_dev_reg_info *regs);
 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340
 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 342                                  struct rte_eth_dev_module_info *modinfo);
 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 344                                    struct rte_dev_eeprom_info *info);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381
 382 /*
 383  * Define VF Stats MACRO for Non "cleared on read" register
 384  */
 385 #define UPDATE_VF_STAT(reg, last, cur)                          \
 386 {                                                               \
 387         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 388         cur += (latest - last) & UINT_MAX;                      \
 389         last = latest;                                          \
 390 }
 391
 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 393 {                                                                \
 394         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 395         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 396         u64 latest = ((new_msb << 32) | new_lsb);                \
 397         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 398         last = latest;                                           \
 399 }
 400
 401 #define IXGBE_SET_HWSTRIP(h, q) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (h)->bitmap[idx] |= 1 << bit;\
 405         } while (0)
 406
 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] &= ~(1 << bit);\
 411         } while (0)
 412
 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (r) = (h)->bitmap[idx] >> bit & 1;\
 417         } while (0)
 418
 419 int ixgbe_logtype_init;
 420 int ixgbe_logtype_driver;
 421
 422 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
 423 int ixgbe_logtype_rx;
 424 #endif
 425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
 426 int ixgbe_logtype_tx;
 427 #endif
 428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 429 int ixgbe_logtype_tx_free;
 430 #endif
 431
 432 /*
 433  * The set of PCI devices this driver supports
 434  */
 435 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .dev_reset            = ixgbe_dev_reset,
 529         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 530         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 531         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 532         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 533         .link_update          = ixgbe_dev_link_update,
 534         .stats_get            = ixgbe_dev_stats_get,
 535         .xstats_get           = ixgbe_dev_xstats_get,
 536         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 537         .stats_reset          = ixgbe_dev_stats_reset,
 538         .xstats_reset         = ixgbe_dev_xstats_reset,
 539         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 540         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 541         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 542         .fw_version_get       = ixgbe_fw_version_get,
 543         .dev_infos_get        = ixgbe_dev_info_get,
 544         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 545         .mtu_set              = ixgbe_dev_mtu_set,
 546         .vlan_filter_set      = ixgbe_vlan_filter_set,
 547         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 548         .vlan_offload_set     = ixgbe_vlan_offload_set,
 549         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 550         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 551         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 552         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 553         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 556         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 557         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 558         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 559         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 560         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 561         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 562         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 563         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 564         .dev_led_on           = ixgbe_dev_led_on,
 565         .dev_led_off          = ixgbe_dev_led_off,
 566         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 567         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 568         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 569         .mac_addr_add         = ixgbe_add_rar,
 570         .mac_addr_remove      = ixgbe_remove_rar,
 571         .mac_addr_set         = ixgbe_set_default_mac_addr,
 572         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 573         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 574         .mirror_rule_set      = ixgbe_mirror_rule_set,
 575         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 576         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 577         .reta_update          = ixgbe_dev_rss_reta_update,
 578         .reta_query           = ixgbe_dev_rss_reta_query,
 579         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 580         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 581         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 582         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 583         .rxq_info_get         = ixgbe_rxq_info_get,
 584         .txq_info_get         = ixgbe_txq_info_get,
 585         .timesync_enable      = ixgbe_timesync_enable,
 586         .timesync_disable     = ixgbe_timesync_disable,
 587         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 588         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 589         .get_reg              = ixgbe_get_regs,
 590         .get_eeprom_length    = ixgbe_get_eeprom_length,
 591         .get_eeprom           = ixgbe_get_eeprom,
 592         .set_eeprom           = ixgbe_set_eeprom,
 593         .get_module_info      = ixgbe_get_module_info,
 594         .get_module_eeprom    = ixgbe_get_module_eeprom,
 595         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 596         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 597         .timesync_read_time   = ixgbe_timesync_read_time,
 598         .timesync_write_time  = ixgbe_timesync_write_time,
 599         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 600         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 601         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 602         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 603         .tm_ops_get           = ixgbe_tm_ops_get,
 604 };
 605
 606 /*
 607  * dev_ops for virtual function, bare necessities for basic vf
 608  * operation have been implemented
 609  */
 610 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 611         .dev_configure        = ixgbevf_dev_configure,
 612         .dev_start            = ixgbevf_dev_start,
 613         .dev_stop             = ixgbevf_dev_stop,
 614         .link_update          = ixgbevf_dev_link_update,
 615         .stats_get            = ixgbevf_dev_stats_get,
 616         .xstats_get           = ixgbevf_dev_xstats_get,
 617         .stats_reset          = ixgbevf_dev_stats_reset,
 618         .xstats_reset         = ixgbevf_dev_stats_reset,
 619         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 620         .dev_close            = ixgbevf_dev_close,
 621         .dev_reset            = ixgbevf_dev_reset,
 622         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 623         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 624         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 625         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 626         .dev_infos_get        = ixgbevf_dev_info_get,
 627         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 628         .mtu_set              = ixgbevf_dev_set_mtu,
 629         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 630         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 631         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 632         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 633         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 634         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 635         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 636         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 637         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 638         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 639         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 640         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 641         .mac_addr_add         = ixgbevf_add_mac_addr,
 642         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 643         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 644         .rxq_info_get         = ixgbe_rxq_info_get,
 645         .txq_info_get         = ixgbe_txq_info_get,
 646         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 647         .get_reg              = ixgbevf_get_regs,
 648         .reta_update          = ixgbe_dev_rss_reta_update,
 649         .reta_query           = ixgbe_dev_rss_reta_query,
 650         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 651         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 652 };
 653
 654 /* store statistics names and its offset in stats structure */
 655 struct rte_ixgbe_xstats_name_off {
 656         char name[RTE_ETH_XSTATS_NAME_SIZE];
 657         unsigned offset;
 658 };
 659
 660 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 661         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 662         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 663         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 664         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 665         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 666         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 667         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 668         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 669         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 670         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 671         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 672         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 673         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 674         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 675         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 676                 prc1023)},
 677         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 678                 prc1522)},
 679         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 680         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 681         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 682         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 683         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 684         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 685         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 686         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 687         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 688         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 689         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 690         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 691         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 692         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 693         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 694         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 695         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 696                 ptc1023)},
 697         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 698                 ptc1522)},
 699         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 700         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 701         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 702         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 703
 704         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirustat_add)},
 706         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirustat_remove)},
 708         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 709                 fdirfstat_fadd)},
 710         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 711                 fdirfstat_fremove)},
 712         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirmatch)},
 714         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 715                 fdirmiss)},
 716
 717         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 718         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 719         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 720                 fclast)},
 721         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 722         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 723         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 724         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 725         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 726                 fcoe_noddp)},
 727         {"rx_fcoe_no_direct_data_placement_ext_buff",
 728                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 729
 730         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxontxc)},
 732         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxonrxc)},
 734         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxofftxc)},
 736         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxoffrxc)},
 738         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 739 };
 740
 741 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 742                            sizeof(rte_ixgbe_stats_strings[0]))
 743
 744 /* MACsec statistics */
 745 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 746         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_untagged)},
 748         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 749                 out_pkts_encrypted)},
 750         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 751                 out_pkts_protected)},
 752         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 753                 out_octets_encrypted)},
 754         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 755                 out_octets_protected)},
 756         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_untagged)},
 758         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_badtag)},
 760         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_nosci)},
 762         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_unknownsci)},
 764         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 765                 in_octets_decrypted)},
 766         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 767                 in_octets_validated)},
 768         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_unchecked)},
 770         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_delayed)},
 772         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_late)},
 774         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_ok)},
 776         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_invalid)},
 778         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_notvalid)},
 780         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_unusedsa)},
 782         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_notusingsa)},
 784 };
 785
 786 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 787                            sizeof(rte_ixgbe_macsec_strings[0]))
 788
 789 /* Per-queue statistics */
 790 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 791         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 792         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 793         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 794         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 795 };
 796
 797 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 798                            sizeof(rte_ixgbe_rxq_strings[0]))
 799 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 800
 801 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 802         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 803         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 804         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 805                 pxon2offc)},
 806 };
 807
 808 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 809                            sizeof(rte_ixgbe_txq_strings[0]))
 810 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 811
 812 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 813         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 814 };
 815
 816 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 817                 sizeof(rte_ixgbevf_stats_strings[0]))
 818
 819 /*
 820  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 821  */
 822 static inline int
 823 ixgbe_is_sfp(struct ixgbe_hw *hw)
 824 {
 825         switch (hw->phy.type) {
 826         case ixgbe_phy_sfp_avago:
 827         case ixgbe_phy_sfp_ftl:
 828         case ixgbe_phy_sfp_intel:
 829         case ixgbe_phy_sfp_unknown:
 830         case ixgbe_phy_sfp_passive_tyco:
 831         case ixgbe_phy_sfp_passive_unknown:
 832                 return 1;
 833         default:
 834                 return 0;
 835         }
 836 }
 837
 838 static inline int32_t
 839 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 840 {
 841         uint32_t ctrl_ext;
 842         int32_t status;
 843
 844         status = ixgbe_reset_hw(hw);
 845
 846         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 847         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 848         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 849         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 850         IXGBE_WRITE_FLUSH(hw);
 851
 852         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 853                 status = IXGBE_SUCCESS;
 854         return status;
 855 }
 856
 857 static inline void
 858 ixgbe_enable_intr(struct rte_eth_dev *dev)
 859 {
 860         struct ixgbe_interrupt *intr =
 861                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 862         struct ixgbe_hw *hw =
 863                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 864
 865         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 866         IXGBE_WRITE_FLUSH(hw);
 867 }
 868
 869 /*
 870  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 871  */
 872 static void
 873 ixgbe_disable_intr(struct ixgbe_hw *hw)
 874 {
 875         PMD_INIT_FUNC_TRACE();
 876
 877         if (hw->mac.type == ixgbe_mac_82598EB) {
 878                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 879         } else {
 880                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 881                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 882                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 883         }
 884         IXGBE_WRITE_FLUSH(hw);
 885 }
 886
 887 /*
 888  * This function resets queue statistics mapping registers.
 889  * From Niantic datasheet, Initialization of Statistics section:
 890  * "...if software requires the queue counters, the RQSMR and TQSM registers
 891  * must be re-programmed following a device reset.
 892  */
 893 static void
 894 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 895 {
 896         uint32_t i;
 897
 898         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 899                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 900                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 901         }
 902 }
 903
 904
 905 static int
 906 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 907                                   uint16_t queue_id,
 908                                   uint8_t stat_idx,
 909                                   uint8_t is_rx)
 910 {
 911 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 912 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 913 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 914
 915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 916         struct ixgbe_stat_mapping_registers *stat_mappings =
 917                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 918         uint32_t qsmr_mask = 0;
 919         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 920         uint32_t q_map;
 921         uint8_t n, offset;
 922
 923         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 924                 (hw->mac.type != ixgbe_mac_X540) &&
 925                 (hw->mac.type != ixgbe_mac_X550) &&
 926                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 927                 (hw->mac.type != ixgbe_mac_X550EM_a))
 928                 return -ENOSYS;
 929
 930         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 931                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 932                      queue_id, stat_idx);
 933
 934         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 935         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 936                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 937                 return -EIO;
 938         }
 939         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 940
 941         /* Now clear any previous stat_idx set */
 942         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 943         if (!is_rx)
 944                 stat_mappings->tqsm[n] &= ~clearing_mask;
 945         else
 946                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 947
 948         q_map = (uint32_t)stat_idx;
 949         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 950         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 951         if (!is_rx)
 952                 stat_mappings->tqsm[n] |= qsmr_mask;
 953         else
 954                 stat_mappings->rqsmr[n] |= qsmr_mask;
 955
 956         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 957                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 958                      queue_id, stat_idx);
 959         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 960                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 961
 962         /* Now write the mapping in the appropriate register */
 963         if (is_rx) {
 964                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 965                              stat_mappings->rqsmr[n], n);
 966                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 967         } else {
 968                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 969                              stat_mappings->tqsm[n], n);
 970                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 971         }
 972         return 0;
 973 }
 974
 975 static void
 976 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 977 {
 978         struct ixgbe_stat_mapping_registers *stat_mappings =
 979                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         int i;
 982
 983         /* write whatever was in stat mapping table to the NIC */
 984         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 985                 /* rx */
 986                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 987
 988                 /* tx */
 989                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 990         }
 991 }
 992
 993 static void
 994 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 995 {
 996         uint8_t i;
 997         struct ixgbe_dcb_tc_config *tc;
 998         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 999
1000         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1001         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1002         for (i = 0; i < dcb_max_tc; i++) {
1003                 tc = &dcb_config->tc_config[i];
1004                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1005                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1006                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1007                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1008                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1009                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1010                 tc->pfc = ixgbe_dcb_pfc_disabled;
1011         }
1012
1013         /* Initialize default user to priority mapping, UPx->TC0 */
1014         tc = &dcb_config->tc_config[0];
1015         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1016         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1017         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1018                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1019                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1020         }
1021         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1022         dcb_config->pfc_mode_enable = false;
1023         dcb_config->vt_mode = true;
1024         dcb_config->round_robin_enable = false;
1025         /* support all DCB capabilities in 82599 */
1026         dcb_config->support.capabilities = 0xFF;
1027
1028         /*we only support 4 Tcs for X540, X550 */
1029         if (hw->mac.type == ixgbe_mac_X540 ||
1030                 hw->mac.type == ixgbe_mac_X550 ||
1031                 hw->mac.type == ixgbe_mac_X550EM_x ||
1032                 hw->mac.type == ixgbe_mac_X550EM_a) {
1033                 dcb_config->num_tcs.pg_tcs = 4;
1034                 dcb_config->num_tcs.pfc_tcs = 4;
1035         }
1036 }
1037
1038 /*
1039  * Ensure that all locks are released before first NVM or PHY access
1040  */
1041 static void
1042 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1043 {
1044         uint16_t mask;
1045
1046         /*
1047          * Phy lock should not fail in this early stage. If this is the case,
1048          * it is due to an improper exit of the application.
1049          * So force the release of the faulty lock. Release of common lock
1050          * is done automatically by swfw_sync function.
1051          */
1052         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1053         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1054                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1055         }
1056         ixgbe_release_swfw_semaphore(hw, mask);
1057
1058         /*
1059          * These ones are more tricky since they are common to all ports; but
1060          * swfw_sync retries last long enough (1s) to be almost sure that if
1061          * lock can not be taken it is due to an improper lock of the
1062          * semaphore.
1063          */
1064         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1065         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1066                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1067         }
1068         ixgbe_release_swfw_semaphore(hw, mask);
1069 }
1070
1071 /*
1072  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1073  * It returns 0 on success.
1074  */
1075 static int
1076 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1077 {
1078         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1079         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1080         struct ixgbe_hw *hw =
1081                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1082         struct ixgbe_vfta *shadow_vfta =
1083                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1084         struct ixgbe_hwstrip *hwstrip =
1085                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1086         struct ixgbe_dcb_config *dcb_config =
1087                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1088         struct ixgbe_filter_info *filter_info =
1089                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1090         struct ixgbe_bw_conf *bw_conf =
1091                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1092         uint32_t ctrl_ext;
1093         uint16_t csum;
1094         int diag, i;
1095
1096         PMD_INIT_FUNC_TRACE();
1097
1098         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1099         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1100         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1101         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1102
1103         /*
1104          * For secondary processes, we don't initialise any further as primary
1105          * has already done this work. Only check we don't need a different
1106          * RX and TX function.
1107          */
1108         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1109                 struct ixgbe_tx_queue *txq;
1110                 /* TX queue function in primary, set by last queue initialized
1111                  * Tx queue may not initialized by primary process
1112                  */
1113                 if (eth_dev->data->tx_queues) {
1114                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1115                         ixgbe_set_tx_function(eth_dev, txq);
1116                 } else {
1117                         /* Use default TX function if we get here */
1118                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1119                                      "Using default TX function.");
1120                 }
1121
1122                 ixgbe_set_rx_function(eth_dev);
1123
1124                 return 0;
1125         }
1126
1127         rte_eth_copy_pci_info(eth_dev, pci_dev);
1128
1129         /* Vendor and Device ID need to be set before init of shared code */
1130         hw->device_id = pci_dev->id.device_id;
1131         hw->vendor_id = pci_dev->id.vendor_id;
1132         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1133         hw->allow_unsupported_sfp = 1;
1134
1135         /* Initialize the shared code (base driver) */
1136 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1137         diag = ixgbe_bypass_init_shared_code(hw);
1138 #else
1139         diag = ixgbe_init_shared_code(hw);
1140 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1141
1142         if (diag != IXGBE_SUCCESS) {
1143                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1144                 return -EIO;
1145         }
1146
1147         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1148                 PMD_INIT_LOG(ERR, "\nERROR: "
1149                         "Firmware recovery mode detected. Limiting functionality.\n"
1150                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1151                         "User Guide for details on firmware recovery mode.");
1152                 return -EIO;
1153         }
1154
1155         /* pick up the PCI bus settings for reporting later */
1156         ixgbe_get_bus_info(hw);
1157
1158         /* Unlock any pending hardware semaphore */
1159         ixgbe_swfw_lock_reset(hw);
1160
1161 #ifdef RTE_LIBRTE_SECURITY
1162         /* Initialize security_ctx only for primary process*/
1163         if (ixgbe_ipsec_ctx_create(eth_dev))
1164                 return -ENOMEM;
1165 #endif
1166
1167         /* Initialize DCB configuration*/
1168         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1169         ixgbe_dcb_init(hw, dcb_config);
1170         /* Get Hardware Flow Control setting */
1171         hw->fc.requested_mode = ixgbe_fc_full;
1172         hw->fc.current_mode = ixgbe_fc_full;
1173         hw->fc.pause_time = IXGBE_FC_PAUSE;
1174         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1175                 hw->fc.low_water[i] = IXGBE_FC_LO;
1176                 hw->fc.high_water[i] = IXGBE_FC_HI;
1177         }
1178         hw->fc.send_xon = 1;
1179
1180         /* Make sure we have a good EEPROM before we read from it */
1181         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1182         if (diag != IXGBE_SUCCESS) {
1183                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1184                 return -EIO;
1185         }
1186
1187 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1188         diag = ixgbe_bypass_init_hw(hw);
1189 #else
1190         diag = ixgbe_init_hw(hw);
1191 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1192
1193         /*
1194          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1195          * is called too soon after the kernel driver unbinding/binding occurs.
1196          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1197          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1198          * also called. See ixgbe_identify_phy_82599(). The reason for the
1199          * failure is not known, and only occuts when virtualisation features
1200          * are disabled in the bios. A delay of 100ms  was found to be enough by
1201          * trial-and-error, and is doubled to be safe.
1202          */
1203         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1204                 rte_delay_ms(200);
1205                 diag = ixgbe_init_hw(hw);
1206         }
1207
1208         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1209                 diag = IXGBE_SUCCESS;
1210
1211         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1212                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1213                              "LOM.  Please be aware there may be issues associated "
1214                              "with your hardware.");
1215                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1216                              "please contact your Intel or hardware representative "
1217                              "who provided you with this hardware.");
1218         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1219                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1220         if (diag) {
1221                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1222                 return -EIO;
1223         }
1224
1225         /* Reset the hw statistics */
1226         ixgbe_dev_stats_reset(eth_dev);
1227
1228         /* disable interrupt */
1229         ixgbe_disable_intr(hw);
1230
1231         /* reset mappings for queue statistics hw counters*/
1232         ixgbe_reset_qstat_mappings(hw);
1233
1234         /* Allocate memory for storing MAC addresses */
1235         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1236                                                hw->mac.num_rar_entries, 0);
1237         if (eth_dev->data->mac_addrs == NULL) {
1238                 PMD_INIT_LOG(ERR,
1239                              "Failed to allocate %u bytes needed to store "
1240                              "MAC addresses",
1241                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1242                 return -ENOMEM;
1243         }
1244         /* Copy the permanent MAC address */
1245         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1246                         &eth_dev->data->mac_addrs[0]);
1247
1248         /* Allocate memory for storing hash filter MAC addresses */
1249         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1250                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1251         if (eth_dev->data->hash_mac_addrs == NULL) {
1252                 PMD_INIT_LOG(ERR,
1253                              "Failed to allocate %d bytes needed to store MAC addresses",
1254                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1255                 return -ENOMEM;
1256         }
1257
1258         /* Pass the information to the rte_eth_dev_close() that it should also
1259          * release the private port resources.
1260          */
1261         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1262
1263         /* initialize the vfta */
1264         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1265
1266         /* initialize the hw strip bitmap*/
1267         memset(hwstrip, 0, sizeof(*hwstrip));
1268
1269         /* initialize PF if max_vfs not zero */
1270         ixgbe_pf_host_init(eth_dev);
1271
1272         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1273         /* let hardware know driver is loaded */
1274         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1275         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1276         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1277         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1278         IXGBE_WRITE_FLUSH(hw);
1279
1280         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1281                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1282                              (int) hw->mac.type, (int) hw->phy.type,
1283                              (int) hw->phy.sfp_type);
1284         else
1285                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1286                              (int) hw->mac.type, (int) hw->phy.type);
1287
1288         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1289                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1290                      pci_dev->id.device_id);
1291
1292         rte_intr_callback_register(intr_handle,
1293                                    ixgbe_dev_interrupt_handler, eth_dev);
1294
1295         /* enable uio/vfio intr/eventfd mapping */
1296         rte_intr_enable(intr_handle);
1297
1298         /* enable support intr */
1299         ixgbe_enable_intr(eth_dev);
1300
1301         /* initialize filter info */
1302         memset(filter_info, 0,
1303                sizeof(struct ixgbe_filter_info));
1304
1305         /* initialize 5tuple filter list */
1306         TAILQ_INIT(&filter_info->fivetuple_list);
1307
1308         /* initialize flow director filter list & hash */
1309         ixgbe_fdir_filter_init(eth_dev);
1310
1311         /* initialize l2 tunnel filter list & hash */
1312         ixgbe_l2_tn_filter_init(eth_dev);
1313
1314         /* initialize flow filter lists */
1315         ixgbe_filterlist_init();
1316
1317         /* initialize bandwidth configuration info */
1318         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1319
1320         /* initialize Traffic Manager configuration */
1321         ixgbe_tm_conf_init(eth_dev);
1322
1323         return 0;
1324 }
1325
1326 static int
1327 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1328 {
1329         PMD_INIT_FUNC_TRACE();
1330
1331         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1332                 return 0;
1333
1334         ixgbe_dev_close(eth_dev);
1335
1336         return 0;
1337 }
1338
1339 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1340 {
1341         struct ixgbe_filter_info *filter_info =
1342                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1343         struct ixgbe_5tuple_filter *p_5tuple;
1344
1345         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1346                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1347                              p_5tuple,
1348                              entries);
1349                 rte_free(p_5tuple);
1350         }
1351         memset(filter_info->fivetuple_mask, 0,
1352                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_hw_fdir_info *fdir_info =
1360                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_fdir_filter *fdir_filter;
1362
1363                 if (fdir_info->hash_map)
1364                 rte_free(fdir_info->hash_map);
1365         if (fdir_info->hash_handle)
1366                 rte_hash_free(fdir_info->hash_handle);
1367
1368         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1369                 TAILQ_REMOVE(&fdir_info->fdir_list,
1370                              fdir_filter,
1371                              entries);
1372                 rte_free(fdir_filter);
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1379 {
1380         struct ixgbe_l2_tn_info *l2_tn_info =
1381                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1382         struct ixgbe_l2_tn_filter *l2_tn_filter;
1383
1384         if (l2_tn_info->hash_map)
1385                 rte_free(l2_tn_info->hash_map);
1386         if (l2_tn_info->hash_handle)
1387                 rte_hash_free(l2_tn_info->hash_handle);
1388
1389         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1390                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1391                              l2_tn_filter,
1392                              entries);
1393                 rte_free(l2_tn_filter);
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1400 {
1401         struct ixgbe_hw_fdir_info *fdir_info =
1402                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1403         char fdir_hash_name[RTE_HASH_NAMESIZE];
1404         struct rte_hash_parameters fdir_hash_params = {
1405                 .name = fdir_hash_name,
1406                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1407                 .key_len = sizeof(union ixgbe_atr_input),
1408                 .hash_func = rte_hash_crc,
1409                 .hash_func_init_val = 0,
1410                 .socket_id = rte_socket_id(),
1411         };
1412
1413         TAILQ_INIT(&fdir_info->fdir_list);
1414         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1415                  "fdir_%s", eth_dev->device->name);
1416         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1417         if (!fdir_info->hash_handle) {
1418                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1419                 return -EINVAL;
1420         }
1421         fdir_info->hash_map = rte_zmalloc("ixgbe",
1422                                           sizeof(struct ixgbe_fdir_filter *) *
1423                                           IXGBE_MAX_FDIR_FILTER_NUM,
1424                                           0);
1425         if (!fdir_info->hash_map) {
1426                 PMD_INIT_LOG(ERR,
1427                              "Failed to allocate memory for fdir hash map!");
1428                 return -ENOMEM;
1429         }
1430         fdir_info->mask_added = FALSE;
1431
1432         return 0;
1433 }
1434
1435 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1436 {
1437         struct ixgbe_l2_tn_info *l2_tn_info =
1438                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1439         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1440         struct rte_hash_parameters l2_tn_hash_params = {
1441                 .name = l2_tn_hash_name,
1442                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1443                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1444                 .hash_func = rte_hash_crc,
1445                 .hash_func_init_val = 0,
1446                 .socket_id = rte_socket_id(),
1447         };
1448
1449         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1450         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1451                  "l2_tn_%s", eth_dev->device->name);
1452         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1453         if (!l2_tn_info->hash_handle) {
1454                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1455                 return -EINVAL;
1456         }
1457         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1458                                    sizeof(struct ixgbe_l2_tn_filter *) *
1459                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1460                                    0);
1461         if (!l2_tn_info->hash_map) {
1462                 PMD_INIT_LOG(ERR,
1463                         "Failed to allocate memory for L2 TN hash map!");
1464                 return -ENOMEM;
1465         }
1466         l2_tn_info->e_tag_en = FALSE;
1467         l2_tn_info->e_tag_fwd_en = FALSE;
1468         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1469
1470         return 0;
1471 }
1472 /*
1473  * Negotiate mailbox API version with the PF.
1474  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1475  * Then we try to negotiate starting with the most recent one.
1476  * If all negotiation attempts fail, then we will proceed with
1477  * the default one (ixgbe_mbox_api_10).
1478  */
1479 static void
1480 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1481 {
1482         int32_t i;
1483
1484         /* start with highest supported, proceed down */
1485         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1486                 ixgbe_mbox_api_13,
1487                 ixgbe_mbox_api_12,
1488                 ixgbe_mbox_api_11,
1489                 ixgbe_mbox_api_10,
1490         };
1491
1492         for (i = 0;
1493                         i != RTE_DIM(sup_ver) &&
1494                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1495                         i++)
1496                 ;
1497 }
1498
1499 static void
1500 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1501 {
1502         uint64_t random;
1503
1504         /* Set Organizationally Unique Identifier (OUI) prefix. */
1505         mac_addr->addr_bytes[0] = 0x00;
1506         mac_addr->addr_bytes[1] = 0x09;
1507         mac_addr->addr_bytes[2] = 0xC0;
1508         /* Force indication of locally assigned MAC address. */
1509         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1510         /* Generate the last 3 bytes of the MAC address with a random number. */
1511         random = rte_rand();
1512         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1513 }
1514
1515 static int
1516 devarg_handle_int(__rte_unused const char *key, const char *value,
1517                   void *extra_args)
1518 {
1519         uint16_t *n = extra_args;
1520
1521         if (value == NULL || extra_args == NULL)
1522                 return -EINVAL;
1523
1524         *n = (uint16_t)strtoul(value, NULL, 0);
1525         if (*n == USHRT_MAX && errno == ERANGE)
1526                 return -1;
1527
1528         return 0;
1529 }
1530
1531 static void
1532 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1533                       struct rte_devargs *devargs)
1534 {
1535         struct rte_kvargs *kvlist;
1536         uint16_t pflink_fullchk;
1537
1538         if (devargs == NULL)
1539                 return;
1540
1541         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1542         if (kvlist == NULL)
1543                 return;
1544
1545         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1546             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1547                                devarg_handle_int, &pflink_fullchk) == 0 &&
1548             pflink_fullchk == 1)
1549                 adapter->pflink_fullchk = 1;
1550
1551         rte_kvargs_free(kvlist);
1552 }
1553
1554 /*
1555  * Virtual Function device init
1556  */
1557 static int
1558 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1559 {
1560         int diag;
1561         uint32_t tc, tcs;
1562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564         struct ixgbe_hw *hw =
1565                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1566         struct ixgbe_vfta *shadow_vfta =
1567                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1568         struct ixgbe_hwstrip *hwstrip =
1569                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1570         struct rte_ether_addr *perm_addr =
1571                 (struct rte_ether_addr *)hw->mac.perm_addr;
1572
1573         PMD_INIT_FUNC_TRACE();
1574
1575         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1576         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1577         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1578
1579         /* for secondary processes, we don't initialise any further as primary
1580          * has already done this work. Only check we don't need a different
1581          * RX function
1582          */
1583         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1584                 struct ixgbe_tx_queue *txq;
1585                 /* TX queue function in primary, set by last queue initialized
1586                  * Tx queue may not initialized by primary process
1587                  */
1588                 if (eth_dev->data->tx_queues) {
1589                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1590                         ixgbe_set_tx_function(eth_dev, txq);
1591                 } else {
1592                         /* Use default TX function if we get here */
1593                         PMD_INIT_LOG(NOTICE,
1594                                      "No TX queues configured yet. Using default TX function.");
1595                 }
1596
1597                 ixgbe_set_rx_function(eth_dev);
1598
1599                 return 0;
1600         }
1601
1602         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1603                               pci_dev->device.devargs);
1604
1605         rte_eth_copy_pci_info(eth_dev, pci_dev);
1606
1607         hw->device_id = pci_dev->id.device_id;
1608         hw->vendor_id = pci_dev->id.vendor_id;
1609         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1610
1611         /* initialize the vfta */
1612         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1613
1614         /* initialize the hw strip bitmap*/
1615         memset(hwstrip, 0, sizeof(*hwstrip));
1616
1617         /* Initialize the shared code (base driver) */
1618         diag = ixgbe_init_shared_code(hw);
1619         if (diag != IXGBE_SUCCESS) {
1620                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1621                 return -EIO;
1622         }
1623
1624         /* init_mailbox_params */
1625         hw->mbx.ops.init_params(hw);
1626
1627         /* Reset the hw statistics */
1628         ixgbevf_dev_stats_reset(eth_dev);
1629
1630         /* Disable the interrupts for VF */
1631         ixgbevf_intr_disable(eth_dev);
1632
1633         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1634         diag = hw->mac.ops.reset_hw(hw);
1635
1636         /*
1637          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1638          * the underlying PF driver has not assigned a MAC address to the VF.
1639          * In this case, assign a random MAC address.
1640          */
1641         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1642                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1643                 /*
1644                  * This error code will be propagated to the app by
1645                  * rte_eth_dev_reset, so use a public error code rather than
1646                  * the internal-only IXGBE_ERR_RESET_FAILED
1647                  */
1648                 return -EAGAIN;
1649         }
1650
1651         /* negotiate mailbox API version to use with the PF. */
1652         ixgbevf_negotiate_api(hw);
1653
1654         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1655         ixgbevf_get_queues(hw, &tcs, &tc);
1656
1657         /* Allocate memory for storing MAC addresses */
1658         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1659                                                hw->mac.num_rar_entries, 0);
1660         if (eth_dev->data->mac_addrs == NULL) {
1661                 PMD_INIT_LOG(ERR,
1662                              "Failed to allocate %u bytes needed to store "
1663                              "MAC addresses",
1664                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1665                 return -ENOMEM;
1666         }
1667
1668         /* Pass the information to the rte_eth_dev_close() that it should also
1669          * release the private port resources.
1670          */
1671         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1672
1673         /* Generate a random MAC address, if none was assigned by PF. */
1674         if (rte_is_zero_ether_addr(perm_addr)) {
1675                 generate_random_mac_addr(perm_addr);
1676                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1677                 if (diag) {
1678                         rte_free(eth_dev->data->mac_addrs);
1679                         eth_dev->data->mac_addrs = NULL;
1680                         return diag;
1681                 }
1682                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1683                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1684                              "%02x:%02x:%02x:%02x:%02x:%02x",
1685                              perm_addr->addr_bytes[0],
1686                              perm_addr->addr_bytes[1],
1687                              perm_addr->addr_bytes[2],
1688                              perm_addr->addr_bytes[3],
1689                              perm_addr->addr_bytes[4],
1690                              perm_addr->addr_bytes[5]);
1691         }
1692
1693         /* Copy the permanent MAC address */
1694         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1695
1696         /* reset the hardware with the new settings */
1697         diag = hw->mac.ops.start_hw(hw);
1698         switch (diag) {
1699         case  0:
1700                 break;
1701
1702         default:
1703                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1704                 return -EIO;
1705         }
1706
1707         rte_intr_callback_register(intr_handle,
1708                                    ixgbevf_dev_interrupt_handler, eth_dev);
1709         rte_intr_enable(intr_handle);
1710         ixgbevf_intr_enable(eth_dev);
1711
1712         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1713                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1714                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1715
1716         return 0;
1717 }
1718
1719 /* Virtual Function device uninit */
1720
1721 static int
1722 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1723 {
1724         PMD_INIT_FUNC_TRACE();
1725
1726         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1727                 return 0;
1728
1729         ixgbevf_dev_close(eth_dev);
1730
1731         return 0;
1732 }
1733
1734 static int
1735 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1736                 struct rte_pci_device *pci_dev)
1737 {
1738         char name[RTE_ETH_NAME_MAX_LEN];
1739         struct rte_eth_dev *pf_ethdev;
1740         struct rte_eth_devargs eth_da;
1741         int i, retval;
1742
1743         if (pci_dev->device.devargs) {
1744                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1745                                 &eth_da);
1746                 if (retval)
1747                         return retval;
1748         } else
1749                 memset(&eth_da, 0, sizeof(eth_da));
1750
1751         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1752                 sizeof(struct ixgbe_adapter),
1753                 eth_dev_pci_specific_init, pci_dev,
1754                 eth_ixgbe_dev_init, NULL);
1755
1756         if (retval || eth_da.nb_representor_ports < 1)
1757                 return retval;
1758
1759         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1760         if (pf_ethdev == NULL)
1761                 return -ENODEV;
1762
1763         /* probe VF representor ports */
1764         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1765                 struct ixgbe_vf_info *vfinfo;
1766                 struct ixgbe_vf_representor representor;
1767
1768                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1769                         pf_ethdev->data->dev_private);
1770                 if (vfinfo == NULL) {
1771                         PMD_DRV_LOG(ERR,
1772                                 "no virtual functions supported by PF");
1773                         break;
1774                 }
1775
1776                 representor.vf_id = eth_da.representor_ports[i];
1777                 representor.switch_domain_id = vfinfo->switch_domain_id;
1778                 representor.pf_ethdev = pf_ethdev;
1779
1780                 /* representor port net_bdf_port */
1781                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1782                         pci_dev->device.name,
1783                         eth_da.representor_ports[i]);
1784
1785                 retval = rte_eth_dev_create(&pci_dev->device, name,
1786                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1787                         ixgbe_vf_representor_init, &representor);
1788
1789                 if (retval)
1790                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1791                                 "representor %s.", name);
1792         }
1793
1794         return 0;
1795 }
1796
1797 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1798 {
1799         struct rte_eth_dev *ethdev;
1800
1801         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1802         if (!ethdev)
1803                 return -ENODEV;
1804
1805         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1806                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1807         else
1808                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1809 }
1810
1811 static struct rte_pci_driver rte_ixgbe_pmd = {
1812         .id_table = pci_id_ixgbe_map,
1813         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1814         .probe = eth_ixgbe_pci_probe,
1815         .remove = eth_ixgbe_pci_remove,
1816 };
1817
1818 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1819         struct rte_pci_device *pci_dev)
1820 {
1821         return rte_eth_dev_pci_generic_probe(pci_dev,
1822                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1823 }
1824
1825 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1826 {
1827         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1828 }
1829
1830 /*
1831  * virtual function driver struct
1832  */
1833 static struct rte_pci_driver rte_ixgbevf_pmd = {
1834         .id_table = pci_id_ixgbevf_map,
1835         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1836         .probe = eth_ixgbevf_pci_probe,
1837         .remove = eth_ixgbevf_pci_remove,
1838 };
1839
1840 static int
1841 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1842 {
1843         struct ixgbe_hw *hw =
1844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct ixgbe_vfta *shadow_vfta =
1846                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1847         uint32_t vfta;
1848         uint32_t vid_idx;
1849         uint32_t vid_bit;
1850
1851         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1852         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1853         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1854         if (on)
1855                 vfta |= vid_bit;
1856         else
1857                 vfta &= ~vid_bit;
1858         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1859
1860         /* update local VFTA copy */
1861         shadow_vfta->vfta[vid_idx] = vfta;
1862
1863         return 0;
1864 }
1865
1866 static void
1867 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1868 {
1869         if (on)
1870                 ixgbe_vlan_hw_strip_enable(dev, queue);
1871         else
1872                 ixgbe_vlan_hw_strip_disable(dev, queue);
1873 }
1874
1875 static int
1876 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1877                     enum rte_vlan_type vlan_type,
1878                     uint16_t tpid)
1879 {
1880         struct ixgbe_hw *hw =
1881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         int ret = 0;
1883         uint32_t reg;
1884         uint32_t qinq;
1885
1886         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887         qinq &= IXGBE_DMATXCTL_GDV;
1888
1889         switch (vlan_type) {
1890         case ETH_VLAN_TYPE_INNER:
1891                 if (qinq) {
1892                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1893                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1894                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1895                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1896                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1897                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1898                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1899                 } else {
1900                         ret = -ENOTSUP;
1901                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1902                                     " by single VLAN");
1903                 }
1904                 break;
1905         case ETH_VLAN_TYPE_OUTER:
1906                 if (qinq) {
1907                         /* Only the high 16-bits is valid */
1908                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1909                                         IXGBE_EXVET_VET_EXT_SHIFT);
1910                 } else {
1911                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1913                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1914                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1915                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1916                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1917                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1918                 }
1919
1920                 break;
1921         default:
1922                 ret = -EINVAL;
1923                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1924                 break;
1925         }
1926
1927         return ret;
1928 }
1929
1930 void
1931 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1932 {
1933         struct ixgbe_hw *hw =
1934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         uint32_t vlnctrl;
1936
1937         PMD_INIT_FUNC_TRACE();
1938
1939         /* Filter Table Disable */
1940         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1941         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1942
1943         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1944 }
1945
1946 void
1947 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1948 {
1949         struct ixgbe_hw *hw =
1950                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct ixgbe_vfta *shadow_vfta =
1952                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1953         uint32_t vlnctrl;
1954         uint16_t i;
1955
1956         PMD_INIT_FUNC_TRACE();
1957
1958         /* Filter Table Enable */
1959         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1960         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1961         vlnctrl |= IXGBE_VLNCTRL_VFE;
1962
1963         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1964
1965         /* write whatever is in local vfta copy */
1966         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1967                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1968 }
1969
1970 static void
1971 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1972 {
1973         struct ixgbe_hwstrip *hwstrip =
1974                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1975         struct ixgbe_rx_queue *rxq;
1976
1977         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1978                 return;
1979
1980         if (on)
1981                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1982         else
1983                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1984
1985         if (queue >= dev->data->nb_rx_queues)
1986                 return;
1987
1988         rxq = dev->data->rx_queues[queue];
1989
1990         if (on) {
1991                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1992                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1993         } else {
1994                 rxq->vlan_flags = PKT_RX_VLAN;
1995                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1996         }
1997 }
1998
1999 static void
2000 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005
2006         PMD_INIT_FUNC_TRACE();
2007
2008         if (hw->mac.type == ixgbe_mac_82598EB) {
2009                 /* No queue level support */
2010                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2011                 return;
2012         }
2013
2014         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2015         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2016         ctrl &= ~IXGBE_RXDCTL_VME;
2017         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018
2019         /* record those setting for HW strip per queue */
2020         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2021 }
2022
2023 static void
2024 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2025 {
2026         struct ixgbe_hw *hw =
2027                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t ctrl;
2029
2030         PMD_INIT_FUNC_TRACE();
2031
2032         if (hw->mac.type == ixgbe_mac_82598EB) {
2033                 /* No queue level supported */
2034                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2035                 return;
2036         }
2037
2038         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2040         ctrl |= IXGBE_RXDCTL_VME;
2041         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2042
2043         /* record those setting for HW strip per queue */
2044         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2045 }
2046
2047 static void
2048 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2049 {
2050         struct ixgbe_hw *hw =
2051                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         uint32_t ctrl;
2053
2054         PMD_INIT_FUNC_TRACE();
2055
2056         /* DMATXCTRL: Geric Double VLAN Disable */
2057         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2058         ctrl &= ~IXGBE_DMATXCTL_GDV;
2059         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2060
2061         /* CTRL_EXT: Global Double VLAN Disable */
2062         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2063         ctrl &= ~IXGBE_EXTENDED_VLAN;
2064         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2065
2066 }
2067
2068 static void
2069 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2070 {
2071         struct ixgbe_hw *hw =
2072                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         uint32_t ctrl;
2074
2075         PMD_INIT_FUNC_TRACE();
2076
2077         /* DMATXCTRL: Geric Double VLAN Enable */
2078         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2079         ctrl |= IXGBE_DMATXCTL_GDV;
2080         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2081
2082         /* CTRL_EXT: Global Double VLAN Enable */
2083         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2084         ctrl |= IXGBE_EXTENDED_VLAN;
2085         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2086
2087         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2088         if (hw->mac.type == ixgbe_mac_X550 ||
2089             hw->mac.type == ixgbe_mac_X550EM_x ||
2090             hw->mac.type == ixgbe_mac_X550EM_a) {
2091                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2092                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2093                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2094         }
2095
2096         /*
2097          * VET EXT field in the EXVET register = 0x8100 by default
2098          * So no need to change. Same to VT field of DMATXCTL register
2099          */
2100 }
2101
2102 void
2103 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2104 {
2105         struct ixgbe_hw *hw =
2106                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2108         uint32_t ctrl;
2109         uint16_t i;
2110         struct ixgbe_rx_queue *rxq;
2111         bool on;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         if (hw->mac.type == ixgbe_mac_82598EB) {
2116                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2117                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2118                         ctrl |= IXGBE_VLNCTRL_VME;
2119                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2120                 } else {
2121                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2122                         ctrl &= ~IXGBE_VLNCTRL_VME;
2123                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2124                 }
2125         } else {
2126                 /*
2127                  * Other 10G NIC, the VLAN strip can be setup
2128                  * per queue in RXDCTL
2129                  */
2130                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2131                         rxq = dev->data->rx_queues[i];
2132                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2133                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2134                                 ctrl |= IXGBE_RXDCTL_VME;
2135                                 on = TRUE;
2136                         } else {
2137                                 ctrl &= ~IXGBE_RXDCTL_VME;
2138                                 on = FALSE;
2139                         }
2140                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2141
2142                         /* record those setting for HW strip per queue */
2143                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2144                 }
2145         }
2146 }
2147
2148 static void
2149 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2150 {
2151         uint16_t i;
2152         struct rte_eth_rxmode *rxmode;
2153         struct ixgbe_rx_queue *rxq;
2154
2155         if (mask & ETH_VLAN_STRIP_MASK) {
2156                 rxmode = &dev->data->dev_conf.rxmode;
2157                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2158                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                                 rxq = dev->data->rx_queues[i];
2160                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2161                         }
2162                 else
2163                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2164                                 rxq = dev->data->rx_queues[i];
2165                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2166                         }
2167         }
2168 }
2169
2170 static int
2171 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2172 {
2173         struct rte_eth_rxmode *rxmode;
2174         rxmode = &dev->data->dev_conf.rxmode;
2175
2176         if (mask & ETH_VLAN_STRIP_MASK) {
2177                 ixgbe_vlan_hw_strip_config(dev);
2178         }
2179
2180         if (mask & ETH_VLAN_FILTER_MASK) {
2181                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2182                         ixgbe_vlan_hw_filter_enable(dev);
2183                 else
2184                         ixgbe_vlan_hw_filter_disable(dev);
2185         }
2186
2187         if (mask & ETH_VLAN_EXTEND_MASK) {
2188                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2189                         ixgbe_vlan_hw_extend_enable(dev);
2190                 else
2191                         ixgbe_vlan_hw_extend_disable(dev);
2192         }
2193
2194         return 0;
2195 }
2196
2197 static int
2198 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2199 {
2200         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2201
2202         ixgbe_vlan_offload_config(dev, mask);
2203
2204         return 0;
2205 }
2206
2207 static void
2208 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw =
2211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2213         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2214
2215         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2216         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2217 }
2218
2219 static int
2220 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2221 {
2222         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2223
2224         switch (nb_rx_q) {
2225         case 1:
2226         case 2:
2227                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2228                 break;
2229         case 4:
2230                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2231                 break;
2232         default:
2233                 return -EINVAL;
2234         }
2235
2236         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2237                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2238         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2239                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2240         return 0;
2241 }
2242
2243 static int
2244 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2245 {
2246         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2249         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2250
2251         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2252                 /* check multi-queue mode */
2253                 switch (dev_conf->rxmode.mq_mode) {
2254                 case ETH_MQ_RX_VMDQ_DCB:
2255                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2256                         break;
2257                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2258                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2259                         PMD_INIT_LOG(ERR, "SRIOV active,"
2260                                         " unsupported mq_mode rx %d.",
2261                                         dev_conf->rxmode.mq_mode);
2262                         return -EINVAL;
2263                 case ETH_MQ_RX_RSS:
2264                 case ETH_MQ_RX_VMDQ_RSS:
2265                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2266                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2267                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2268                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2269                                                 " invalid queue number"
2270                                                 " for VMDQ RSS, allowed"
2271                                                 " value are 1, 2 or 4.");
2272                                         return -EINVAL;
2273                                 }
2274                         break;
2275                 case ETH_MQ_RX_VMDQ_ONLY:
2276                 case ETH_MQ_RX_NONE:
2277                         /* if nothing mq mode configure, use default scheme */
2278                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2279                         break;
2280                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2281                         /* SRIOV only works in VMDq enable mode */
2282                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2283                                         " wrong mq_mode rx %d.",
2284                                         dev_conf->rxmode.mq_mode);
2285                         return -EINVAL;
2286                 }
2287
2288                 switch (dev_conf->txmode.mq_mode) {
2289                 case ETH_MQ_TX_VMDQ_DCB:
2290                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2291                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2292                         break;
2293                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2294                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2295                         break;
2296                 }
2297
2298                 /* check valid queue number */
2299                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2300                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2301                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2302                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2303                                         " must be less than or equal to %d.",
2304                                         nb_rx_q, nb_tx_q,
2305                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2306                         return -EINVAL;
2307                 }
2308         } else {
2309                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2310                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2311                                           " not supported.");
2312                         return -EINVAL;
2313                 }
2314                 /* check configuration for vmdb+dcb mode */
2315                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2316                         const struct rte_eth_vmdq_dcb_conf *conf;
2317
2318                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2319                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2320                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2321                                 return -EINVAL;
2322                         }
2323                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2324                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2325                                conf->nb_queue_pools == ETH_32_POOLS)) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2327                                                 " nb_queue_pools must be %d or %d.",
2328                                                 ETH_16_POOLS, ETH_32_POOLS);
2329                                 return -EINVAL;
2330                         }
2331                 }
2332                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2333                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2334
2335                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2336                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2337                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2338                                 return -EINVAL;
2339                         }
2340                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2341                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2342                                conf->nb_queue_pools == ETH_32_POOLS)) {
2343                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2344                                                 " nb_queue_pools != %d and"
2345                                                 " nb_queue_pools != %d.",
2346                                                 ETH_16_POOLS, ETH_32_POOLS);
2347                                 return -EINVAL;
2348                         }
2349                 }
2350
2351                 /* For DCB mode check our configuration before we go further */
2352                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2353                         const struct rte_eth_dcb_rx_conf *conf;
2354
2355                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2356                         if (!(conf->nb_tcs == ETH_4_TCS ||
2357                                conf->nb_tcs == ETH_8_TCS)) {
2358                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2359                                                 " and nb_tcs != %d.",
2360                                                 ETH_4_TCS, ETH_8_TCS);
2361                                 return -EINVAL;
2362                         }
2363                 }
2364
2365                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2366                         const struct rte_eth_dcb_tx_conf *conf;
2367
2368                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2369                         if (!(conf->nb_tcs == ETH_4_TCS ||
2370                                conf->nb_tcs == ETH_8_TCS)) {
2371                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372                                                 " and nb_tcs != %d.",
2373                                                 ETH_4_TCS, ETH_8_TCS);
2374                                 return -EINVAL;
2375                         }
2376                 }
2377
2378                 /*
2379                  * When DCB/VT is off, maximum number of queues changes,
2380                  * except for 82598EB, which remains constant.
2381                  */
2382                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2383                                 hw->mac.type != ixgbe_mac_82598EB) {
2384                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2385                                 PMD_INIT_LOG(ERR,
2386                                              "Neither VT nor DCB are enabled, "
2387                                              "nb_tx_q > %d.",
2388                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2389                                 return -EINVAL;
2390                         }
2391                 }
2392         }
2393         return 0;
2394 }
2395
2396 static int
2397 ixgbe_dev_configure(struct rte_eth_dev *dev)
2398 {
2399         struct ixgbe_interrupt *intr =
2400                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2401         struct ixgbe_adapter *adapter = dev->data->dev_private;
2402         int ret;
2403
2404         PMD_INIT_FUNC_TRACE();
2405         /* multipe queue mode checking */
2406         ret  = ixgbe_check_mq_mode(dev);
2407         if (ret != 0) {
2408                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2409                             ret);
2410                 return ret;
2411         }
2412
2413         /* set flag to update link status after init */
2414         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2415
2416         /*
2417          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2418          * allocation or vector Rx preconditions we will reset it.
2419          */
2420         adapter->rx_bulk_alloc_allowed = true;
2421         adapter->rx_vec_allowed = true;
2422
2423         return 0;
2424 }
2425
2426 static void
2427 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2428 {
2429         struct ixgbe_hw *hw =
2430                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2431         struct ixgbe_interrupt *intr =
2432                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2433         uint32_t gpie;
2434
2435         /* only set up it on X550EM_X */
2436         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2437                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2438                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2439                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2440                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2441                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2442         }
2443 }
2444
2445 int
2446 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2447                         uint16_t tx_rate, uint64_t q_msk)
2448 {
2449         struct ixgbe_hw *hw;
2450         struct ixgbe_vf_info *vfinfo;
2451         struct rte_eth_link link;
2452         uint8_t  nb_q_per_pool;
2453         uint32_t queue_stride;
2454         uint32_t queue_idx, idx = 0, vf_idx;
2455         uint32_t queue_end;
2456         uint16_t total_rate = 0;
2457         struct rte_pci_device *pci_dev;
2458         int ret;
2459
2460         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2461         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2462         if (ret < 0)
2463                 return ret;
2464
2465         if (vf >= pci_dev->max_vfs)
2466                 return -EINVAL;
2467
2468         if (tx_rate > link.link_speed)
2469                 return -EINVAL;
2470
2471         if (q_msk == 0)
2472                 return 0;
2473
2474         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2476         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2477         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2478         queue_idx = vf * queue_stride;
2479         queue_end = queue_idx + nb_q_per_pool - 1;
2480         if (queue_end >= hw->mac.max_tx_queues)
2481                 return -EINVAL;
2482
2483         if (vfinfo) {
2484                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2485                         if (vf_idx == vf)
2486                                 continue;
2487                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2488                                 idx++)
2489                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2490                 }
2491         } else {
2492                 return -EINVAL;
2493         }
2494
2495         /* Store tx_rate for this vf. */
2496         for (idx = 0; idx < nb_q_per_pool; idx++) {
2497                 if (((uint64_t)0x1 << idx) & q_msk) {
2498                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2499                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2500                         total_rate += tx_rate;
2501                 }
2502         }
2503
2504         if (total_rate > dev->data->dev_link.link_speed) {
2505                 /* Reset stored TX rate of the VF if it causes exceed
2506                  * link speed.
2507                  */
2508                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2509                 return -EINVAL;
2510         }
2511
2512         /* Set RTTBCNRC of each queue/pool for vf X  */
2513         for (; queue_idx <= queue_end; queue_idx++) {
2514                 if (0x1 & q_msk)
2515                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2516                 q_msk = q_msk >> 1;
2517         }
2518
2519         return 0;
2520 }
2521
2522 /*
2523  * Configure device link speed and setup link.
2524  * It returns 0 on success.
2525  */
2526 static int
2527 ixgbe_dev_start(struct rte_eth_dev *dev)
2528 {
2529         struct ixgbe_hw *hw =
2530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         struct ixgbe_vf_info *vfinfo =
2532                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2533         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2534         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2535         uint32_t intr_vector = 0;
2536         int err, link_up = 0, negotiate = 0;
2537         uint32_t speed = 0;
2538         uint32_t allowed_speeds = 0;
2539         int mask = 0;
2540         int status;
2541         uint16_t vf, idx;
2542         uint32_t *link_speeds;
2543         struct ixgbe_tm_conf *tm_conf =
2544                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2545         struct ixgbe_macsec_setting *macsec_ctrl =
2546                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2547
2548         PMD_INIT_FUNC_TRACE();
2549
2550         /* IXGBE devices don't support:
2551         *    - half duplex (checked afterwards for valid speeds)
2552         *    - fixed speed: TODO implement
2553         */
2554         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2555                 PMD_INIT_LOG(ERR,
2556                 "Invalid link_speeds for port %u, fix speed not supported",
2557                                 dev->data->port_id);
2558                 return -EINVAL;
2559         }
2560
2561         /* Stop the link setup handler before resetting the HW. */
2562         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2563
2564         /* disable uio/vfio intr/eventfd mapping */
2565         rte_intr_disable(intr_handle);
2566
2567         /* stop adapter */
2568         hw->adapter_stopped = 0;
2569         ixgbe_stop_adapter(hw);
2570
2571         /* reinitialize adapter
2572          * this calls reset and start
2573          */
2574         status = ixgbe_pf_reset_hw(hw);
2575         if (status != 0)
2576                 return -1;
2577         hw->mac.ops.start_hw(hw);
2578         hw->mac.get_link_status = true;
2579
2580         /* configure PF module if SRIOV enabled */
2581         ixgbe_pf_host_configure(dev);
2582
2583         ixgbe_dev_phy_intr_setup(dev);
2584
2585         /* check and configure queue intr-vector mapping */
2586         if ((rte_intr_cap_multiple(intr_handle) ||
2587              !RTE_ETH_DEV_SRIOV(dev).active) &&
2588             dev->data->dev_conf.intr_conf.rxq != 0) {
2589                 intr_vector = dev->data->nb_rx_queues;
2590                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2591                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2592                                         IXGBE_MAX_INTR_QUEUE_NUM);
2593                         return -ENOTSUP;
2594                 }
2595                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2596                         return -1;
2597         }
2598
2599         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2600                 intr_handle->intr_vec =
2601                         rte_zmalloc("intr_vec",
2602                                     dev->data->nb_rx_queues * sizeof(int), 0);
2603                 if (intr_handle->intr_vec == NULL) {
2604                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2605                                      " intr_vec", dev->data->nb_rx_queues);
2606                         return -ENOMEM;
2607                 }
2608         }
2609
2610         /* confiugre msix for sleep until rx interrupt */
2611         ixgbe_configure_msix(dev);
2612
2613         /* initialize transmission unit */
2614         ixgbe_dev_tx_init(dev);
2615
2616         /* This can fail when allocating mbufs for descriptor rings */
2617         err = ixgbe_dev_rx_init(dev);
2618         if (err) {
2619                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2620                 goto error;
2621         }
2622
2623         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2624                 ETH_VLAN_EXTEND_MASK;
2625         err = ixgbe_vlan_offload_config(dev, mask);
2626         if (err) {
2627                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2628                 goto error;
2629         }
2630
2631         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2632                 /* Enable vlan filtering for VMDq */
2633                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2634         }
2635
2636         /* Configure DCB hw */
2637         ixgbe_configure_dcb(dev);
2638
2639         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2640                 err = ixgbe_fdir_configure(dev);
2641                 if (err)
2642                         goto error;
2643         }
2644
2645         /* Restore vf rate limit */
2646         if (vfinfo != NULL) {
2647                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2648                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2649                                 if (vfinfo[vf].tx_rate[idx] != 0)
2650                                         ixgbe_set_vf_rate_limit(
2651                                                 dev, vf,
2652                                                 vfinfo[vf].tx_rate[idx],
2653                                                 1 << idx);
2654         }
2655
2656         ixgbe_restore_statistics_mapping(dev);
2657
2658         err = ixgbe_dev_rxtx_start(dev);
2659         if (err < 0) {
2660                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2661                 goto error;
2662         }
2663
2664         /* Skip link setup if loopback mode is enabled. */
2665         if (dev->data->dev_conf.lpbk_mode != 0) {
2666                 err = ixgbe_check_supported_loopback_mode(dev);
2667                 if (err < 0) {
2668                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2669                         goto error;
2670                 } else {
2671                         goto skip_link_setup;
2672                 }
2673         }
2674
2675         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2676                 err = hw->mac.ops.setup_sfp(hw);
2677                 if (err)
2678                         goto error;
2679         }
2680
2681         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2682                 /* Turn on the copper */
2683                 ixgbe_set_phy_power(hw, true);
2684         } else {
2685                 /* Turn on the laser */
2686                 ixgbe_enable_tx_laser(hw);
2687         }
2688
2689         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2690         if (err)
2691                 goto error;
2692         dev->data->dev_link.link_status = link_up;
2693
2694         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2695         if (err)
2696                 goto error;
2697
2698         switch (hw->mac.type) {
2699         case ixgbe_mac_X550:
2700         case ixgbe_mac_X550EM_x:
2701         case ixgbe_mac_X550EM_a:
2702                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2703                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2704                         ETH_LINK_SPEED_10G;
2705                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2706                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2707                         allowed_speeds = ETH_LINK_SPEED_10M |
2708                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2709                 break;
2710         default:
2711                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2712                         ETH_LINK_SPEED_10G;
2713         }
2714
2715         link_speeds = &dev->data->dev_conf.link_speeds;
2716         if (*link_speeds & ~allowed_speeds) {
2717                 PMD_INIT_LOG(ERR, "Invalid link setting");
2718                 goto error;
2719         }
2720
2721         speed = 0x0;
2722         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2723                 switch (hw->mac.type) {
2724                 case ixgbe_mac_82598EB:
2725                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2726                         break;
2727                 case ixgbe_mac_82599EB:
2728                 case ixgbe_mac_X540:
2729                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2730                         break;
2731                 case ixgbe_mac_X550:
2732                 case ixgbe_mac_X550EM_x:
2733                 case ixgbe_mac_X550EM_a:
2734                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2735                         break;
2736                 default:
2737                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2738                 }
2739         } else {
2740                 if (*link_speeds & ETH_LINK_SPEED_10G)
2741                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2742                 if (*link_speeds & ETH_LINK_SPEED_5G)
2743                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2744                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2745                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2746                 if (*link_speeds & ETH_LINK_SPEED_1G)
2747                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2748                 if (*link_speeds & ETH_LINK_SPEED_100M)
2749                         speed |= IXGBE_LINK_SPEED_100_FULL;
2750                 if (*link_speeds & ETH_LINK_SPEED_10M)
2751                         speed |= IXGBE_LINK_SPEED_10_FULL;
2752         }
2753
2754         err = ixgbe_setup_link(hw, speed, link_up);
2755         if (err)
2756                 goto error;
2757
2758 skip_link_setup:
2759
2760         if (rte_intr_allow_others(intr_handle)) {
2761                 /* check if lsc interrupt is enabled */
2762                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2763                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2764                 else
2765                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2766                 ixgbe_dev_macsec_interrupt_setup(dev);
2767         } else {
2768                 rte_intr_callback_unregister(intr_handle,
2769                                              ixgbe_dev_interrupt_handler, dev);
2770                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2771                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2772                                      " no intr multiplex");
2773         }
2774
2775         /* check if rxq interrupt is enabled */
2776         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2777             rte_intr_dp_is_en(intr_handle))
2778                 ixgbe_dev_rxq_interrupt_setup(dev);
2779
2780         /* enable uio/vfio intr/eventfd mapping */
2781         rte_intr_enable(intr_handle);
2782
2783         /* resume enabled intr since hw reset */
2784         ixgbe_enable_intr(dev);
2785         ixgbe_l2_tunnel_conf(dev);
2786         ixgbe_filter_restore(dev);
2787
2788         if (tm_conf->root && !tm_conf->committed)
2789                 PMD_DRV_LOG(WARNING,
2790                             "please call hierarchy_commit() "
2791                             "before starting the port");
2792
2793         /*
2794          * Update link status right before return, because it may
2795          * start link configuration process in a separate thread.
2796          */
2797         ixgbe_dev_link_update(dev, 0);
2798
2799         /* setup the macsec ctrl register */
2800         ixgbe_dev_macsec_register_enable(dev, macsec_ctrl);
2801
2802         return 0;
2803
2804 error:
2805         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2806         ixgbe_dev_clear_queues(dev);
2807         return -EIO;
2808 }
2809
2810 /*
2811  * Stop device: disable rx and tx functions to allow for reconfiguring.
2812  */
2813 static void
2814 ixgbe_dev_stop(struct rte_eth_dev *dev)
2815 {
2816         struct rte_eth_link link;
2817         struct ixgbe_adapter *adapter = dev->data->dev_private;
2818         struct ixgbe_hw *hw =
2819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820         struct ixgbe_vf_info *vfinfo =
2821                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2822         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2823         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2824         int vf;
2825         struct ixgbe_tm_conf *tm_conf =
2826                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2827
2828         if (hw->adapter_stopped)
2829                 return;
2830
2831         PMD_INIT_FUNC_TRACE();
2832
2833         /* disable mecsec register */
2834         ixgbe_dev_macsec_register_disable(dev);
2835
2836         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2837
2838         /* disable interrupts */
2839         ixgbe_disable_intr(hw);
2840
2841         /* reset the NIC */
2842         ixgbe_pf_reset_hw(hw);
2843         hw->adapter_stopped = 0;
2844
2845         /* stop adapter */
2846         ixgbe_stop_adapter(hw);
2847
2848         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2849                 vfinfo[vf].clear_to_send = false;
2850
2851         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2852                 /* Turn off the copper */
2853                 ixgbe_set_phy_power(hw, false);
2854         } else {
2855                 /* Turn off the laser */
2856                 ixgbe_disable_tx_laser(hw);
2857         }
2858
2859         ixgbe_dev_clear_queues(dev);
2860
2861         /* Clear stored conf */
2862         dev->data->scattered_rx = 0;
2863         dev->data->lro = 0;
2864
2865         /* Clear recorded link status */
2866         memset(&link, 0, sizeof(link));
2867         rte_eth_linkstatus_set(dev, &link);
2868
2869         if (!rte_intr_allow_others(intr_handle))
2870                 /* resume to the default handler */
2871                 rte_intr_callback_register(intr_handle,
2872                                            ixgbe_dev_interrupt_handler,
2873                                            (void *)dev);
2874
2875         /* Clean datapath event and queue/vec mapping */
2876         rte_intr_efd_disable(intr_handle);
2877         if (intr_handle->intr_vec != NULL) {
2878                 rte_free(intr_handle->intr_vec);
2879                 intr_handle->intr_vec = NULL;
2880         }
2881
2882         /* reset hierarchy commit */
2883         tm_conf->committed = false;
2884
2885         adapter->rss_reta_updated = 0;
2886
2887         hw->adapter_stopped = true;
2888 }
2889
2890 /*
2891  * Set device link up: enable tx.
2892  */
2893 static int
2894 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2895 {
2896         struct ixgbe_hw *hw =
2897                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898         if (hw->mac.type == ixgbe_mac_82599EB) {
2899 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2900                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2901                         /* Not suported in bypass mode */
2902                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2903                                      "by device id 0x%x", hw->device_id);
2904                         return -ENOTSUP;
2905                 }
2906 #endif
2907         }
2908
2909         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2910                 /* Turn on the copper */
2911                 ixgbe_set_phy_power(hw, true);
2912         } else {
2913                 /* Turn on the laser */
2914                 ixgbe_enable_tx_laser(hw);
2915                 ixgbe_dev_link_update(dev, 0);
2916         }
2917
2918         return 0;
2919 }
2920
2921 /*
2922  * Set device link down: disable tx.
2923  */
2924 static int
2925 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2926 {
2927         struct ixgbe_hw *hw =
2928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929         if (hw->mac.type == ixgbe_mac_82599EB) {
2930 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2931                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2932                         /* Not suported in bypass mode */
2933                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2934                                      "by device id 0x%x", hw->device_id);
2935                         return -ENOTSUP;
2936                 }
2937 #endif
2938         }
2939
2940         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2941                 /* Turn off the copper */
2942                 ixgbe_set_phy_power(hw, false);
2943         } else {
2944                 /* Turn off the laser */
2945                 ixgbe_disable_tx_laser(hw);
2946                 ixgbe_dev_link_update(dev, 0);
2947         }
2948
2949         return 0;
2950 }
2951
2952 /*
2953  * Reset and stop device.
2954  */
2955 static void
2956 ixgbe_dev_close(struct rte_eth_dev *dev)
2957 {
2958         struct ixgbe_hw *hw =
2959                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2960         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2961         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2962         int retries = 0;
2963         int ret;
2964
2965         PMD_INIT_FUNC_TRACE();
2966
2967         ixgbe_pf_reset_hw(hw);
2968
2969         ixgbe_dev_stop(dev);
2970
2971         ixgbe_dev_free_queues(dev);
2972
2973         ixgbe_disable_pcie_master(hw);
2974
2975         /* reprogram the RAR[0] in case user changed it. */
2976         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2977
2978         dev->dev_ops = NULL;
2979         dev->rx_pkt_burst = NULL;
2980         dev->tx_pkt_burst = NULL;
2981
2982         /* Unlock any pending hardware semaphore */
2983         ixgbe_swfw_lock_reset(hw);
2984
2985         /* disable uio intr before callback unregister */
2986         rte_intr_disable(intr_handle);
2987
2988         do {
2989                 ret = rte_intr_callback_unregister(intr_handle,
2990                                 ixgbe_dev_interrupt_handler, dev);
2991                 if (ret >= 0 || ret == -ENOENT) {
2992                         break;
2993                 } else if (ret != -EAGAIN) {
2994                         PMD_INIT_LOG(ERR,
2995                                 "intr callback unregister failed: %d",
2996                                 ret);
2997                 }
2998                 rte_delay_ms(100);
2999         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3000
3001         /* cancel the delay handler before remove dev */
3002         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3003
3004         /* uninitialize PF if max_vfs not zero */
3005         ixgbe_pf_host_uninit(dev);
3006
3007         /* remove all the fdir filters & hash */
3008         ixgbe_fdir_filter_uninit(dev);
3009
3010         /* remove all the L2 tunnel filters & hash */
3011         ixgbe_l2_tn_filter_uninit(dev);
3012
3013         /* Remove all ntuple filters of the device */
3014         ixgbe_ntuple_filter_uninit(dev);
3015
3016         /* clear all the filters list */
3017         ixgbe_filterlist_flush();
3018
3019         /* Remove all Traffic Manager configuration */
3020         ixgbe_tm_conf_uninit(dev);
3021
3022 #ifdef RTE_LIBRTE_SECURITY
3023         rte_free(dev->security_ctx);
3024 #endif
3025
3026 }
3027
3028 /*
3029  * Reset PF device.
3030  */
3031 static int
3032 ixgbe_dev_reset(struct rte_eth_dev *dev)
3033 {
3034         int ret;
3035
3036         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3037          * its VF to make them align with it. The detailed notification
3038          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3039          * To avoid unexpected behavior in VF, currently reset of PF with
3040          * SR-IOV activation is not supported. It might be supported later.
3041          */
3042         if (dev->data->sriov.active)
3043                 return -ENOTSUP;
3044
3045         ret = eth_ixgbe_dev_uninit(dev);
3046         if (ret)
3047                 return ret;
3048
3049         ret = eth_ixgbe_dev_init(dev, NULL);
3050
3051         return ret;
3052 }
3053
3054 static void
3055 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3056                            struct ixgbe_hw_stats *hw_stats,
3057                            struct ixgbe_macsec_stats *macsec_stats,
3058                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3059                            uint64_t *total_qprc, uint64_t *total_qprdc)
3060 {
3061         uint32_t bprc, lxon, lxoff, total;
3062         uint32_t delta_gprc = 0;
3063         unsigned i;
3064         /* Workaround for RX byte count not including CRC bytes when CRC
3065          * strip is enabled. CRC bytes are removed from counters when crc_strip
3066          * is disabled.
3067          */
3068         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3069                         IXGBE_HLREG0_RXCRCSTRP);
3070
3071         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3072         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3073         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3074         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3075
3076         for (i = 0; i < 8; i++) {
3077                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3078
3079                 /* global total per queue */
3080                 hw_stats->mpc[i] += mp;
3081                 /* Running comprehensive total for stats display */
3082                 *total_missed_rx += hw_stats->mpc[i];
3083                 if (hw->mac.type == ixgbe_mac_82598EB) {
3084                         hw_stats->rnbc[i] +=
3085                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3086                         hw_stats->pxonrxc[i] +=
3087                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3088                         hw_stats->pxoffrxc[i] +=
3089                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3090                 } else {
3091                         hw_stats->pxonrxc[i] +=
3092                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3093                         hw_stats->pxoffrxc[i] +=
3094                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3095                         hw_stats->pxon2offc[i] +=
3096                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3097                 }
3098                 hw_stats->pxontxc[i] +=
3099                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3100                 hw_stats->pxofftxc[i] +=
3101                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3102         }
3103         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3104                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3105                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3106                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3107
3108                 delta_gprc += delta_qprc;
3109
3110                 hw_stats->qprc[i] += delta_qprc;
3111                 hw_stats->qptc[i] += delta_qptc;
3112
3113                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3114                 hw_stats->qbrc[i] +=
3115                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3116                 if (crc_strip == 0)
3117                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3118
3119                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3120                 hw_stats->qbtc[i] +=
3121                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3122
3123                 hw_stats->qprdc[i] += delta_qprdc;
3124                 *total_qprdc += hw_stats->qprdc[i];
3125
3126                 *total_qprc += hw_stats->qprc[i];
3127                 *total_qbrc += hw_stats->qbrc[i];
3128         }
3129         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3130         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3131         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3132
3133         /*
3134          * An errata states that gprc actually counts good + missed packets:
3135          * Workaround to set gprc to summated queue packet receives
3136          */
3137         hw_stats->gprc = *total_qprc;
3138
3139         if (hw->mac.type != ixgbe_mac_82598EB) {
3140                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3141                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3142                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3143                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3144                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3145                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3146                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3147                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3148         } else {
3149                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3150                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3151                 /* 82598 only has a counter in the high register */
3152                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3153                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3154                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3155         }
3156         uint64_t old_tpr = hw_stats->tpr;
3157
3158         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3159         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3160
3161         if (crc_strip == 0)
3162                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3163
3164         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3165         hw_stats->gptc += delta_gptc;
3166         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3167         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3168
3169         /*
3170          * Workaround: mprc hardware is incorrectly counting
3171          * broadcasts, so for now we subtract those.
3172          */
3173         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3174         hw_stats->bprc += bprc;
3175         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3176         if (hw->mac.type == ixgbe_mac_82598EB)
3177                 hw_stats->mprc -= bprc;
3178
3179         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3180         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3181         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3182         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3183         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3184         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3185
3186         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3187         hw_stats->lxontxc += lxon;
3188         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3189         hw_stats->lxofftxc += lxoff;
3190         total = lxon + lxoff;
3191
3192         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3193         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3194         hw_stats->gptc -= total;
3195         hw_stats->mptc -= total;
3196         hw_stats->ptc64 -= total;
3197         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3198
3199         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3200         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3201         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3202         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3203         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3204         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3205         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3206         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3207         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3208         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3209         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3210         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3211         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3212         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3213         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3214         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3215         /* Only read FCOE on 82599 */
3216         if (hw->mac.type != ixgbe_mac_82598EB) {
3217                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3218                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3219                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3220                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3221                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3222         }
3223
3224         /* Flow Director Stats registers */
3225         if (hw->mac.type != ixgbe_mac_82598EB) {
3226                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3227                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3228                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3229                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3230                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3231                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3232                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3233                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3234                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3235                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3236         }
3237         /* MACsec Stats registers */
3238         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3239         macsec_stats->out_pkts_encrypted +=
3240                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3241         macsec_stats->out_pkts_protected +=
3242                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3243         macsec_stats->out_octets_encrypted +=
3244                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3245         macsec_stats->out_octets_protected +=
3246                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3247         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3248         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3249         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3250         macsec_stats->in_pkts_unknownsci +=
3251                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3252         macsec_stats->in_octets_decrypted +=
3253                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3254         macsec_stats->in_octets_validated +=
3255                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3256         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3257         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3258         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3259         for (i = 0; i < 2; i++) {
3260                 macsec_stats->in_pkts_ok +=
3261                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3262                 macsec_stats->in_pkts_invalid +=
3263                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3264                 macsec_stats->in_pkts_notvalid +=
3265                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3266         }
3267         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3268         macsec_stats->in_pkts_notusingsa +=
3269                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3270 }
3271
3272 /*
3273  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3274  */
3275 static int
3276 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3277 {
3278         struct ixgbe_hw *hw =
3279                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3280         struct ixgbe_hw_stats *hw_stats =
3281                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3282         struct ixgbe_macsec_stats *macsec_stats =
3283                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3284                                 dev->data->dev_private);
3285         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3286         unsigned i;
3287
3288         total_missed_rx = 0;
3289         total_qbrc = 0;
3290         total_qprc = 0;
3291         total_qprdc = 0;
3292
3293         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3294                         &total_qbrc, &total_qprc, &total_qprdc);
3295
3296         if (stats == NULL)
3297                 return -EINVAL;
3298
3299         /* Fill out the rte_eth_stats statistics structure */
3300         stats->ipackets = total_qprc;
3301         stats->ibytes = total_qbrc;
3302         stats->opackets = hw_stats->gptc;
3303         stats->obytes = hw_stats->gotc;
3304
3305         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3306                 stats->q_ipackets[i] = hw_stats->qprc[i];
3307                 stats->q_opackets[i] = hw_stats->qptc[i];
3308                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3309                 stats->q_obytes[i] = hw_stats->qbtc[i];
3310                 stats->q_errors[i] = hw_stats->qprdc[i];
3311         }
3312
3313         /* Rx Errors */
3314         stats->imissed  = total_missed_rx;
3315         stats->ierrors  = hw_stats->crcerrs +
3316                           hw_stats->mspdc +
3317                           hw_stats->rlec +
3318                           hw_stats->ruc +
3319                           hw_stats->roc +
3320                           hw_stats->illerrc +
3321                           hw_stats->errbc +
3322                           hw_stats->rfc +
3323                           hw_stats->fccrc +
3324                           hw_stats->fclast;
3325
3326         /* Tx Errors */
3327         stats->oerrors  = 0;
3328         return 0;
3329 }
3330
3331 static int
3332 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3333 {
3334         struct ixgbe_hw_stats *stats =
3335                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3336
3337         /* HW registers are cleared on read */
3338         ixgbe_dev_stats_get(dev, NULL);
3339
3340         /* Reset software totals */
3341         memset(stats, 0, sizeof(*stats));
3342
3343         return 0;
3344 }
3345
3346 /* This function calculates the number of xstats based on the current config */
3347 static unsigned
3348 ixgbe_xstats_calc_num(void) {
3349         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3350                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3351                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3352 }
3353
3354 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3355         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3356 {
3357         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3358         unsigned stat, i, count;
3359
3360         if (xstats_names != NULL) {
3361                 count = 0;
3362
3363                 /* Note: limit >= cnt_stats checked upstream
3364                  * in rte_eth_xstats_names()
3365                  */
3366
3367                 /* Extended stats from ixgbe_hw_stats */
3368                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3369                         strlcpy(xstats_names[count].name,
3370                                 rte_ixgbe_stats_strings[i].name,
3371                                 sizeof(xstats_names[count].name));
3372                         count++;
3373                 }
3374
3375                 /* MACsec Stats */
3376                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3377                         strlcpy(xstats_names[count].name,
3378                                 rte_ixgbe_macsec_strings[i].name,
3379                                 sizeof(xstats_names[count].name));
3380                         count++;
3381                 }
3382
3383                 /* RX Priority Stats */
3384                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3385                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3386                                 snprintf(xstats_names[count].name,
3387                                         sizeof(xstats_names[count].name),
3388                                         "rx_priority%u_%s", i,
3389                                         rte_ixgbe_rxq_strings[stat].name);
3390                                 count++;
3391                         }
3392                 }
3393
3394                 /* TX Priority Stats */
3395                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3396                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3397                                 snprintf(xstats_names[count].name,
3398                                         sizeof(xstats_names[count].name),
3399                                         "tx_priority%u_%s", i,
3400                                         rte_ixgbe_txq_strings[stat].name);
3401                                 count++;
3402                         }
3403                 }
3404         }
3405         return cnt_stats;
3406 }
3407
3408 static int ixgbe_dev_xstats_get_names_by_id(
3409         struct rte_eth_dev *dev,
3410         struct rte_eth_xstat_name *xstats_names,
3411         const uint64_t *ids,
3412         unsigned int limit)
3413 {
3414         if (!ids) {
3415                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3416                 unsigned int stat, i, count;
3417
3418                 if (xstats_names != NULL) {
3419                         count = 0;
3420
3421                         /* Note: limit >= cnt_stats checked upstream
3422                          * in rte_eth_xstats_names()
3423                          */
3424
3425                         /* Extended stats from ixgbe_hw_stats */
3426                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3427                                 strlcpy(xstats_names[count].name,
3428                                         rte_ixgbe_stats_strings[i].name,
3429                                         sizeof(xstats_names[count].name));
3430                                 count++;
3431                         }
3432
3433                         /* MACsec Stats */
3434                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3435                                 strlcpy(xstats_names[count].name,
3436                                         rte_ixgbe_macsec_strings[i].name,
3437                                         sizeof(xstats_names[count].name));
3438                                 count++;
3439                         }
3440
3441                         /* RX Priority Stats */
3442                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3443                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3444                                         snprintf(xstats_names[count].name,
3445                                             sizeof(xstats_names[count].name),
3446                                             "rx_priority%u_%s", i,
3447                                             rte_ixgbe_rxq_strings[stat].name);
3448                                         count++;
3449                                 }
3450                         }
3451
3452                         /* TX Priority Stats */
3453                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3454                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3455                                         snprintf(xstats_names[count].name,
3456                                             sizeof(xstats_names[count].name),
3457                                             "tx_priority%u_%s", i,
3458                                             rte_ixgbe_txq_strings[stat].name);
3459                                         count++;
3460                                 }
3461                         }
3462                 }
3463                 return cnt_stats;
3464         }
3465
3466         uint16_t i;
3467         uint16_t size = ixgbe_xstats_calc_num();
3468         struct rte_eth_xstat_name xstats_names_copy[size];
3469
3470         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3471                         size);
3472
3473         for (i = 0; i < limit; i++) {
3474                 if (ids[i] >= size) {
3475                         PMD_INIT_LOG(ERR, "id value isn't valid");
3476                         return -1;
3477                 }
3478                 strcpy(xstats_names[i].name,
3479                                 xstats_names_copy[ids[i]].name);
3480         }
3481         return limit;
3482 }
3483
3484 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3485         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3486 {
3487         unsigned i;
3488
3489         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3490                 return -ENOMEM;
3491
3492         if (xstats_names != NULL)
3493                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3494                         strlcpy(xstats_names[i].name,
3495                                 rte_ixgbevf_stats_strings[i].name,
3496                                 sizeof(xstats_names[i].name));
3497         return IXGBEVF_NB_XSTATS;
3498 }
3499
3500 static int
3501 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3502                                          unsigned n)
3503 {
3504         struct ixgbe_hw *hw =
3505                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3506         struct ixgbe_hw_stats *hw_stats =
3507                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3508         struct ixgbe_macsec_stats *macsec_stats =
3509                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3510                                 dev->data->dev_private);
3511         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3512         unsigned i, stat, count = 0;
3513
3514         count = ixgbe_xstats_calc_num();
3515
3516         if (n < count)
3517                 return count;
3518
3519         total_missed_rx = 0;
3520         total_qbrc = 0;
3521         total_qprc = 0;
3522         total_qprdc = 0;
3523
3524         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3525                         &total_qbrc, &total_qprc, &total_qprdc);
3526
3527         /* If this is a reset xstats is NULL, and we have cleared the
3528          * registers by reading them.
3529          */
3530         if (!xstats)
3531                 return 0;
3532
3533         /* Extended stats from ixgbe_hw_stats */
3534         count = 0;
3535         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3536                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3537                                 rte_ixgbe_stats_strings[i].offset);
3538                 xstats[count].id = count;
3539                 count++;
3540         }
3541
3542         /* MACsec Stats */
3543         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3544                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3545                                 rte_ixgbe_macsec_strings[i].offset);
3546                 xstats[count].id = count;
3547                 count++;
3548         }
3549
3550         /* RX Priority Stats */
3551         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3552                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3553                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3554                                         rte_ixgbe_rxq_strings[stat].offset +
3555                                         (sizeof(uint64_t) * i));
3556                         xstats[count].id = count;
3557                         count++;
3558                 }
3559         }
3560
3561         /* TX Priority Stats */
3562         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3563                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3564                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3565                                         rte_ixgbe_txq_strings[stat].offset +
3566                                         (sizeof(uint64_t) * i));
3567                         xstats[count].id = count;
3568                         count++;
3569                 }
3570         }
3571         return count;
3572 }
3573
3574 static int
3575 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3576                 uint64_t *values, unsigned int n)
3577 {
3578         if (!ids) {
3579                 struct ixgbe_hw *hw =
3580                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581                 struct ixgbe_hw_stats *hw_stats =
3582                                 IXGBE_DEV_PRIVATE_TO_STATS(
3583                                                 dev->data->dev_private);
3584                 struct ixgbe_macsec_stats *macsec_stats =
3585                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3586                                         dev->data->dev_private);
3587                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3588                 unsigned int i, stat, count = 0;
3589
3590                 count = ixgbe_xstats_calc_num();
3591
3592                 if (!ids && n < count)
3593                         return count;
3594
3595                 total_missed_rx = 0;
3596                 total_qbrc = 0;
3597                 total_qprc = 0;
3598                 total_qprdc = 0;
3599
3600                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3601                                 &total_missed_rx, &total_qbrc, &total_qprc,
3602                                 &total_qprdc);
3603
3604                 /* If this is a reset xstats is NULL, and we have cleared the
3605                  * registers by reading them.
3606                  */
3607                 if (!ids && !values)
3608                         return 0;
3609
3610                 /* Extended stats from ixgbe_hw_stats */
3611                 count = 0;
3612                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3613                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3614                                         rte_ixgbe_stats_strings[i].offset);
3615                         count++;
3616                 }
3617
3618                 /* MACsec Stats */
3619                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3620                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3621                                         rte_ixgbe_macsec_strings[i].offset);
3622                         count++;
3623                 }
3624
3625                 /* RX Priority Stats */
3626                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3627                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3628                                 values[count] =
3629                                         *(uint64_t *)(((char *)hw_stats) +
3630                                         rte_ixgbe_rxq_strings[stat].offset +
3631                                         (sizeof(uint64_t) * i));
3632                                 count++;
3633                         }
3634                 }
3635
3636                 /* TX Priority Stats */
3637                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3638                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3639                                 values[count] =
3640                                         *(uint64_t *)(((char *)hw_stats) +
3641                                         rte_ixgbe_txq_strings[stat].offset +
3642                                         (sizeof(uint64_t) * i));
3643                                 count++;
3644                         }
3645                 }
3646                 return count;
3647         }
3648
3649         uint16_t i;
3650         uint16_t size = ixgbe_xstats_calc_num();
3651         uint64_t values_copy[size];
3652
3653         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3654
3655         for (i = 0; i < n; i++) {
3656                 if (ids[i] >= size) {
3657                         PMD_INIT_LOG(ERR, "id value isn't valid");
3658                         return -1;
3659                 }
3660                 values[i] = values_copy[ids[i]];
3661         }
3662         return n;
3663 }
3664
3665 static int
3666 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3667 {
3668         struct ixgbe_hw_stats *stats =
3669                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3670         struct ixgbe_macsec_stats *macsec_stats =
3671                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3672                                 dev->data->dev_private);
3673
3674         unsigned count = ixgbe_xstats_calc_num();
3675
3676         /* HW registers are cleared on read */
3677         ixgbe_dev_xstats_get(dev, NULL, count);
3678
3679         /* Reset software totals */
3680         memset(stats, 0, sizeof(*stats));
3681         memset(macsec_stats, 0, sizeof(*macsec_stats));
3682
3683         return 0;
3684 }
3685
3686 static void
3687 ixgbevf_update_stats(struct rte_eth_dev *dev)
3688 {
3689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3690         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3691                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3692
3693         /* Good Rx packet, include VF loopback */
3694         UPDATE_VF_STAT(IXGBE_VFGPRC,
3695             hw_stats->last_vfgprc, hw_stats->vfgprc);
3696
3697         /* Good Rx octets, include VF loopback */
3698         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3699             hw_stats->last_vfgorc, hw_stats->vfgorc);
3700
3701         /* Good Tx packet, include VF loopback */
3702         UPDATE_VF_STAT(IXGBE_VFGPTC,
3703             hw_stats->last_vfgptc, hw_stats->vfgptc);
3704
3705         /* Good Tx octets, include VF loopback */
3706         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3707             hw_stats->last_vfgotc, hw_stats->vfgotc);
3708
3709         /* Rx Multicst Packet */
3710         UPDATE_VF_STAT(IXGBE_VFMPRC,
3711             hw_stats->last_vfmprc, hw_stats->vfmprc);
3712 }
3713
3714 static int
3715 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3716                        unsigned n)
3717 {
3718         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3719                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3720         unsigned i;
3721
3722         if (n < IXGBEVF_NB_XSTATS)
3723                 return IXGBEVF_NB_XSTATS;
3724
3725         ixgbevf_update_stats(dev);
3726
3727         if (!xstats)
3728                 return 0;
3729
3730         /* Extended stats */
3731         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3732                 xstats[i].id = i;
3733                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3734                         rte_ixgbevf_stats_strings[i].offset);
3735         }
3736
3737         return IXGBEVF_NB_XSTATS;
3738 }
3739
3740 static int
3741 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3742 {
3743         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3744                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3745
3746         ixgbevf_update_stats(dev);
3747
3748         if (stats == NULL)
3749                 return -EINVAL;
3750
3751         stats->ipackets = hw_stats->vfgprc;
3752         stats->ibytes = hw_stats->vfgorc;
3753         stats->opackets = hw_stats->vfgptc;
3754         stats->obytes = hw_stats->vfgotc;
3755         return 0;
3756 }
3757
3758 static int
3759 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3760 {
3761         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3762                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3763
3764         /* Sync HW register to the last stats */
3765         ixgbevf_dev_stats_get(dev, NULL);
3766
3767         /* reset HW current stats*/
3768         hw_stats->vfgprc = 0;
3769         hw_stats->vfgorc = 0;
3770         hw_stats->vfgptc = 0;
3771         hw_stats->vfgotc = 0;
3772
3773         return 0;
3774 }
3775
3776 static int
3777 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3778 {
3779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3780         u16 eeprom_verh, eeprom_verl;
3781         u32 etrack_id;
3782         int ret;
3783
3784         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3785         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3786
3787         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3788         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3789
3790         ret += 1; /* add the size of '\0' */
3791         if (fw_size < (u32)ret)
3792                 return ret;
3793         else
3794                 return 0;
3795 }
3796
3797 static int
3798 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3799 {
3800         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3803
3804         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3805         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3806         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3807                 /*
3808                  * When DCB/VT is off, maximum number of queues changes,
3809                  * except for 82598EB, which remains constant.
3810                  */
3811                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3812                                 hw->mac.type != ixgbe_mac_82598EB)
3813                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3814         }
3815         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3816         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3817         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3818         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3819         dev_info->max_vfs = pci_dev->max_vfs;
3820         if (hw->mac.type == ixgbe_mac_82598EB)
3821                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3822         else
3823                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3824         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3825         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3826         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3827         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3828         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3829                                      dev_info->rx_queue_offload_capa);
3830         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3831         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3832
3833         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3834                 .rx_thresh = {
3835                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3836                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3837                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3838                 },
3839                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3840                 .rx_drop_en = 0,
3841                 .offloads = 0,
3842         };
3843
3844         dev_info->default_txconf = (struct rte_eth_txconf) {
3845                 .tx_thresh = {
3846                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3847                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3848                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3849                 },
3850                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3851                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3852                 .offloads = 0,
3853         };
3854
3855         dev_info->rx_desc_lim = rx_desc_lim;
3856         dev_info->tx_desc_lim = tx_desc_lim;
3857
3858         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3859         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3860         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3861
3862         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3863         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3864                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3865                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3866                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3867
3868         if (hw->mac.type == ixgbe_mac_X540 ||
3869             hw->mac.type == ixgbe_mac_X540_vf ||
3870             hw->mac.type == ixgbe_mac_X550 ||
3871             hw->mac.type == ixgbe_mac_X550_vf) {
3872                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3873         }
3874         if (hw->mac.type == ixgbe_mac_X550) {
3875                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3876                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3877         }
3878
3879         /* Driver-preferred Rx/Tx parameters */
3880         dev_info->default_rxportconf.burst_size = 32;
3881         dev_info->default_txportconf.burst_size = 32;
3882         dev_info->default_rxportconf.nb_queues = 1;
3883         dev_info->default_txportconf.nb_queues = 1;
3884         dev_info->default_rxportconf.ring_size = 256;
3885         dev_info->default_txportconf.ring_size = 256;
3886
3887         return 0;
3888 }
3889
3890 static const uint32_t *
3891 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3892 {
3893         static const uint32_t ptypes[] = {
3894                 /* For non-vec functions,
3895                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3896                  * for vec functions,
3897                  * refers to _recv_raw_pkts_vec().
3898                  */
3899                 RTE_PTYPE_L2_ETHER,
3900                 RTE_PTYPE_L3_IPV4,
3901                 RTE_PTYPE_L3_IPV4_EXT,
3902                 RTE_PTYPE_L3_IPV6,
3903                 RTE_PTYPE_L3_IPV6_EXT,
3904                 RTE_PTYPE_L4_SCTP,
3905                 RTE_PTYPE_L4_TCP,
3906                 RTE_PTYPE_L4_UDP,
3907                 RTE_PTYPE_TUNNEL_IP,
3908                 RTE_PTYPE_INNER_L3_IPV6,
3909                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3910                 RTE_PTYPE_INNER_L4_TCP,
3911                 RTE_PTYPE_INNER_L4_UDP,
3912                 RTE_PTYPE_UNKNOWN
3913         };
3914
3915         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3916             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3917             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3918             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3919                 return ptypes;
3920
3921 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3922         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3923             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3924                 return ptypes;
3925 #endif
3926         return NULL;
3927 }
3928
3929 static int
3930 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3931                      struct rte_eth_dev_info *dev_info)
3932 {
3933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935
3936         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3937         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3938         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3939         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3940         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3941         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3942         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3943         dev_info->max_vfs = pci_dev->max_vfs;
3944         if (hw->mac.type == ixgbe_mac_82598EB)
3945                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3946         else
3947                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3948         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3949         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3950                                      dev_info->rx_queue_offload_capa);
3951         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3952         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3953         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3954         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3955         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3956
3957         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3958                 .rx_thresh = {
3959                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3960                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3961                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3962                 },
3963                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3964                 .rx_drop_en = 0,
3965                 .offloads = 0,
3966         };
3967
3968         dev_info->default_txconf = (struct rte_eth_txconf) {
3969                 .tx_thresh = {
3970                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3971                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3972                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3973                 },
3974                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3975                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3976                 .offloads = 0,
3977         };
3978
3979         dev_info->rx_desc_lim = rx_desc_lim;
3980         dev_info->tx_desc_lim = tx_desc_lim;
3981
3982         return 0;
3983 }
3984
3985 static int
3986 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3987                    int *link_up, int wait_to_complete)
3988 {
3989         struct ixgbe_adapter *adapter = container_of(hw,
3990                                                      struct ixgbe_adapter, hw);
3991         struct ixgbe_mbx_info *mbx = &hw->mbx;
3992         struct ixgbe_mac_info *mac = &hw->mac;
3993         uint32_t links_reg, in_msg;
3994         int ret_val = 0;
3995
3996         /* If we were hit with a reset drop the link */
3997         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3998                 mac->get_link_status = true;
3999
4000         if (!mac->get_link_status)
4001                 goto out;
4002
4003         /* if link status is down no point in checking to see if pf is up */
4004         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4005         if (!(links_reg & IXGBE_LINKS_UP))
4006                 goto out;
4007
4008         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4009          * before the link status is correct
4010          */
4011         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4012                 int i;
4013
4014                 for (i = 0; i < 5; i++) {
4015                         rte_delay_us(100);
4016                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4017
4018                         if (!(links_reg & IXGBE_LINKS_UP))
4019                                 goto out;
4020                 }
4021         }
4022
4023         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4024         case IXGBE_LINKS_SPEED_10G_82599:
4025                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4026                 if (hw->mac.type >= ixgbe_mac_X550) {
4027                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4028                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4029                 }
4030                 break;
4031         case IXGBE_LINKS_SPEED_1G_82599:
4032                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4033                 break;
4034         case IXGBE_LINKS_SPEED_100_82599:
4035                 *speed = IXGBE_LINK_SPEED_100_FULL;
4036                 if (hw->mac.type == ixgbe_mac_X550) {
4037                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4038                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4039                 }
4040                 break;
4041         case IXGBE_LINKS_SPEED_10_X550EM_A:
4042                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4043                 /* Since Reserved in older MAC's */
4044                 if (hw->mac.type >= ixgbe_mac_X550)
4045                         *speed = IXGBE_LINK_SPEED_10_FULL;
4046                 break;
4047         default:
4048                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4049         }
4050
4051         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4052                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4053                         mac->get_link_status = true;
4054                 else
4055                         mac->get_link_status = false;
4056
4057                 goto out;
4058         }
4059
4060         /* if the read failed it could just be a mailbox collision, best wait
4061          * until we are called again and don't report an error
4062          */
4063         if (mbx->ops.read(hw, &in_msg, 1, 0))
4064                 goto out;
4065
4066         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4067                 /* msg is not CTS and is NACK we must have lost CTS status */
4068                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4069                         mac->get_link_status = false;
4070                 goto out;
4071         }
4072
4073         /* the pf is talking, if we timed out in the past we reinit */
4074         if (!mbx->timeout) {
4075                 ret_val = -1;
4076                 goto out;
4077         }
4078
4079         /* if we passed all the tests above then the link is up and we no
4080          * longer need to check for link
4081          */
4082         mac->get_link_status = false;
4083
4084 out:
4085         *link_up = !mac->get_link_status;
4086         return ret_val;
4087 }
4088
4089 static void
4090 ixgbe_dev_setup_link_alarm_handler(void *param)
4091 {
4092         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4094         struct ixgbe_interrupt *intr =
4095                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4096         u32 speed;
4097         bool autoneg = false;
4098
4099         speed = hw->phy.autoneg_advertised;
4100         if (!speed)
4101                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4102
4103         ixgbe_setup_link(hw, speed, true);
4104
4105         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4106 }
4107
4108 /* return 0 means link status changed, -1 means not changed */
4109 int
4110 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4111                             int wait_to_complete, int vf)
4112 {
4113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         struct rte_eth_link link;
4115         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4116         struct ixgbe_interrupt *intr =
4117                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4118         int link_up;
4119         int diag;
4120         int wait = 1;
4121         u32 esdp_reg;
4122
4123         memset(&link, 0, sizeof(link));
4124         link.link_status = ETH_LINK_DOWN;
4125         link.link_speed = ETH_SPEED_NUM_NONE;
4126         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4127         link.link_autoneg = ETH_LINK_AUTONEG;
4128
4129         hw->mac.get_link_status = true;
4130
4131         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4132                 return rte_eth_linkstatus_set(dev, &link);
4133
4134         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4135         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4136                 wait = 0;
4137
4138         if (vf)
4139                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4140         else
4141                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4142
4143         if (diag != 0) {
4144                 link.link_speed = ETH_SPEED_NUM_100M;
4145                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4146                 return rte_eth_linkstatus_set(dev, &link);
4147         }
4148
4149         esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4150         if ((esdp_reg & IXGBE_ESDP_SDP3))
4151                 link_up = 0;
4152
4153         if (link_up == 0) {
4154                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4155                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4156                         rte_eal_alarm_set(10,
4157                                 ixgbe_dev_setup_link_alarm_handler, dev);
4158                 }
4159                 return rte_eth_linkstatus_set(dev, &link);
4160         }
4161
4162         link.link_status = ETH_LINK_UP;
4163         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4164
4165         switch (link_speed) {
4166         default:
4167         case IXGBE_LINK_SPEED_UNKNOWN:
4168                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4169                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4170                         link.link_speed = ETH_SPEED_NUM_10M;
4171                 else
4172                         link.link_speed = ETH_SPEED_NUM_100M;
4173                 break;
4174
4175         case IXGBE_LINK_SPEED_100_FULL:
4176                 link.link_speed = ETH_SPEED_NUM_100M;
4177                 break;
4178
4179         case IXGBE_LINK_SPEED_1GB_FULL:
4180                 link.link_speed = ETH_SPEED_NUM_1G;
4181                 break;
4182
4183         case IXGBE_LINK_SPEED_2_5GB_FULL:
4184                 link.link_speed = ETH_SPEED_NUM_2_5G;
4185                 break;
4186
4187         case IXGBE_LINK_SPEED_5GB_FULL:
4188                 link.link_speed = ETH_SPEED_NUM_5G;
4189                 break;
4190
4191         case IXGBE_LINK_SPEED_10GB_FULL:
4192                 link.link_speed = ETH_SPEED_NUM_10G;
4193                 break;
4194         }
4195
4196         return rte_eth_linkstatus_set(dev, &link);
4197 }
4198
4199 static int
4200 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4201 {
4202         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4203 }
4204
4205 static int
4206 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4207 {
4208         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4209 }
4210
4211 static int
4212 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4213 {
4214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4215         uint32_t fctrl;
4216
4217         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4218         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4219         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4220
4221         return 0;
4222 }
4223
4224 static int
4225 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4226 {
4227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4228         uint32_t fctrl;
4229
4230         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4231         fctrl &= (~IXGBE_FCTRL_UPE);
4232         if (dev->data->all_multicast == 1)
4233                 fctrl |= IXGBE_FCTRL_MPE;
4234         else
4235                 fctrl &= (~IXGBE_FCTRL_MPE);
4236         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4237
4238         return 0;
4239 }
4240
4241 static int
4242 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4243 {
4244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4245         uint32_t fctrl;
4246
4247         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4248         fctrl |= IXGBE_FCTRL_MPE;
4249         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4250
4251         return 0;
4252 }
4253
4254 static int
4255 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4256 {
4257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4258         uint32_t fctrl;
4259
4260         if (dev->data->promiscuous == 1)
4261                 return 0; /* must remain in all_multicast mode */
4262
4263         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4264         fctrl &= (~IXGBE_FCTRL_MPE);
4265         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4266
4267         return 0;
4268 }
4269
4270 /**
4271  * It clears the interrupt causes and enables the interrupt.
4272  * It will be called once only during nic initialized.
4273  *
4274  * @param dev
4275  *  Pointer to struct rte_eth_dev.
4276  * @param on
4277  *  Enable or Disable.
4278  *
4279  * @return
4280  *  - On success, zero.
4281  *  - On failure, a negative value.
4282  */
4283 static int
4284 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4285 {
4286         struct ixgbe_interrupt *intr =
4287                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4288
4289         ixgbe_dev_link_status_print(dev);
4290         if (on)
4291                 intr->mask |= IXGBE_EICR_LSC;
4292         else
4293                 intr->mask &= ~IXGBE_EICR_LSC;
4294
4295         return 0;
4296 }
4297
4298 /**
4299  * It clears the interrupt causes and enables the interrupt.
4300  * It will be called once only during nic initialized.
4301  *
4302  * @param dev
4303  *  Pointer to struct rte_eth_dev.
4304  *
4305  * @return
4306  *  - On success, zero.
4307  *  - On failure, a negative value.
4308  */
4309 static int
4310 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4311 {
4312         struct ixgbe_interrupt *intr =
4313                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4314
4315         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4316
4317         return 0;
4318 }
4319
4320 /**
4321  * It clears the interrupt causes and enables the interrupt.
4322  * It will be called once only during nic initialized.
4323  *
4324  * @param dev
4325  *  Pointer to struct rte_eth_dev.
4326  *
4327  * @return
4328  *  - On success, zero.
4329  *  - On failure, a negative value.
4330  */
4331 static int
4332 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4333 {
4334         struct ixgbe_interrupt *intr =
4335                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4336
4337         intr->mask |= IXGBE_EICR_LINKSEC;
4338
4339         return 0;
4340 }
4341
4342 /*
4343  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4344  *
4345  * @param dev
4346  *  Pointer to struct rte_eth_dev.
4347  *
4348  * @return
4349  *  - On success, zero.
4350  *  - On failure, a negative value.
4351  */
4352 static int
4353 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4354 {
4355         uint32_t eicr;
4356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357         struct ixgbe_interrupt *intr =
4358                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4359
4360         /* clear all cause mask */
4361         ixgbe_disable_intr(hw);
4362
4363         /* read-on-clear nic registers here */
4364         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4365         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4366
4367         intr->flags = 0;
4368
4369         /* set flag for async link update */
4370         if (eicr & IXGBE_EICR_LSC)
4371                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4372
4373         if (eicr & IXGBE_EICR_MAILBOX)
4374                 intr->flags |= IXGBE_FLAG_MAILBOX;
4375
4376         if (eicr & IXGBE_EICR_LINKSEC)
4377                 intr->flags |= IXGBE_FLAG_MACSEC;
4378
4379         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4380             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4381             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4382                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4383
4384         return 0;
4385 }
4386
4387 /**
4388  * It gets and then prints the link status.
4389  *
4390  * @param dev
4391  *  Pointer to struct rte_eth_dev.
4392  *
4393  * @return
4394  *  - On success, zero.
4395  *  - On failure, a negative value.
4396  */
4397 static void
4398 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4399 {
4400         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4401         struct rte_eth_link link;
4402
4403         rte_eth_linkstatus_get(dev, &link);
4404
4405         if (link.link_status) {
4406                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4407                                         (int)(dev->data->port_id),
4408                                         (unsigned)link.link_speed,
4409                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4410                                         "full-duplex" : "half-duplex");
4411         } else {
4412                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4413                                 (int)(dev->data->port_id));
4414         }
4415         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4416                                 pci_dev->addr.domain,
4417                                 pci_dev->addr.bus,
4418                                 pci_dev->addr.devid,
4419                                 pci_dev->addr.function);
4420 }
4421
4422 /*
4423  * It executes link_update after knowing an interrupt occurred.
4424  *
4425  * @param dev
4426  *  Pointer to struct rte_eth_dev.
4427  *
4428  * @return
4429  *  - On success, zero.
4430  *  - On failure, a negative value.
4431  */
4432 static int
4433 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4434 {
4435         struct ixgbe_interrupt *intr =
4436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4437         int64_t timeout;
4438         struct ixgbe_hw *hw =
4439                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4440
4441         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4442
4443         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4444                 ixgbe_pf_mbx_process(dev);
4445                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4446         }
4447
4448         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4449                 ixgbe_handle_lasi(hw);
4450                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4451         }
4452
4453         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4454                 struct rte_eth_link link;
4455
4456                 /* get the link status before link update, for predicting later */
4457                 rte_eth_linkstatus_get(dev, &link);
4458
4459                 ixgbe_dev_link_update(dev, 0);
4460
4461                 /* likely to up */
4462                 if (!link.link_status)
4463                         /* handle it 1 sec later, wait it being stable */
4464                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4465                 /* likely to down */
4466                 else
4467                         /* handle it 4 sec later, wait it being stable */
4468                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4469
4470                 ixgbe_dev_link_status_print(dev);
4471                 if (rte_eal_alarm_set(timeout * 1000,
4472                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4473                         PMD_DRV_LOG(ERR, "Error setting alarm");
4474                 else {
4475                         /* remember original mask */
4476                         intr->mask_original = intr->mask;
4477                         /* only disable lsc interrupt */
4478                         intr->mask &= ~IXGBE_EIMS_LSC;
4479                 }
4480         }
4481
4482         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4483         ixgbe_enable_intr(dev);
4484
4485         return 0;
4486 }
4487
4488 /**
4489  * Interrupt handler which shall be registered for alarm callback for delayed
4490  * handling specific interrupt to wait for the stable nic state. As the
4491  * NIC interrupt state is not stable for ixgbe after link is just down,
4492  * it needs to wait 4 seconds to get the stable status.
4493  *
4494  * @param handle
4495  *  Pointer to interrupt handle.
4496  * @param param
4497  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4498  *
4499  * @return
4500  *  void
4501  */
4502 static void
4503 ixgbe_dev_interrupt_delayed_handler(void *param)
4504 {
4505         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4506         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4507         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4508         struct ixgbe_interrupt *intr =
4509                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4510         struct ixgbe_hw *hw =
4511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4512         uint32_t eicr;
4513
4514         ixgbe_disable_intr(hw);
4515
4516         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4517         if (eicr & IXGBE_EICR_MAILBOX)
4518                 ixgbe_pf_mbx_process(dev);
4519
4520         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4521                 ixgbe_handle_lasi(hw);
4522                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4523         }
4524
4525         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4526                 ixgbe_dev_link_update(dev, 0);
4527                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4528                 ixgbe_dev_link_status_print(dev);
4529                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4530                                               NULL);
4531         }
4532
4533         if (intr->flags & IXGBE_FLAG_MACSEC) {
4534                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4535                                               NULL);
4536                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4537         }
4538
4539         /* restore original mask */
4540         intr->mask = intr->mask_original;
4541         intr->mask_original = 0;
4542
4543         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4544         ixgbe_enable_intr(dev);
4545         rte_intr_ack(intr_handle);
4546 }
4547
4548 /**
4549  * Interrupt handler triggered by NIC  for handling
4550  * specific interrupt.
4551  *
4552  * @param handle
4553  *  Pointer to interrupt handle.
4554  * @param param
4555  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4556  *
4557  * @return
4558  *  void
4559  */
4560 static void
4561 ixgbe_dev_interrupt_handler(void *param)
4562 {
4563         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4564
4565         ixgbe_dev_interrupt_get_status(dev);
4566         ixgbe_dev_interrupt_action(dev);
4567 }
4568
4569 static int
4570 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4571 {
4572         struct ixgbe_hw *hw;
4573
4574         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4575         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4576 }
4577
4578 static int
4579 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4580 {
4581         struct ixgbe_hw *hw;
4582
4583         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4584         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4585 }
4586
4587 static int
4588 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4589 {
4590         struct ixgbe_hw *hw;
4591         uint32_t mflcn_reg;
4592         uint32_t fccfg_reg;
4593         int rx_pause;
4594         int tx_pause;
4595
4596         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4597
4598         fc_conf->pause_time = hw->fc.pause_time;
4599         fc_conf->high_water = hw->fc.high_water[0];
4600         fc_conf->low_water = hw->fc.low_water[0];
4601         fc_conf->send_xon = hw->fc.send_xon;
4602         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4603
4604         /*
4605          * Return rx_pause status according to actual setting of
4606          * MFLCN register.
4607          */
4608         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4609         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4610                 rx_pause = 1;
4611         else
4612                 rx_pause = 0;
4613
4614         /*
4615          * Return tx_pause status according to actual setting of
4616          * FCCFG register.
4617          */
4618         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4619         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4620                 tx_pause = 1;
4621         else
4622                 tx_pause = 0;
4623
4624         if (rx_pause && tx_pause)
4625                 fc_conf->mode = RTE_FC_FULL;
4626         else if (rx_pause)
4627                 fc_conf->mode = RTE_FC_RX_PAUSE;
4628         else if (tx_pause)
4629                 fc_conf->mode = RTE_FC_TX_PAUSE;
4630         else
4631                 fc_conf->mode = RTE_FC_NONE;
4632
4633         return 0;
4634 }
4635
4636 static int
4637 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4638 {
4639         struct ixgbe_hw *hw;
4640         int err;
4641         uint32_t rx_buf_size;
4642         uint32_t max_high_water;
4643         uint32_t mflcn;
4644         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4645                 ixgbe_fc_none,
4646                 ixgbe_fc_rx_pause,
4647                 ixgbe_fc_tx_pause,
4648                 ixgbe_fc_full
4649         };
4650
4651         PMD_INIT_FUNC_TRACE();
4652
4653         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4654         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4655         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4656
4657         /*
4658          * At least reserve one Ethernet frame for watermark
4659          * high_water/low_water in kilo bytes for ixgbe
4660          */
4661         max_high_water = (rx_buf_size -
4662                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4663         if ((fc_conf->high_water > max_high_water) ||
4664                 (fc_conf->high_water < fc_conf->low_water)) {
4665                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4666                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4667                 return -EINVAL;
4668         }
4669
4670         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4671         hw->fc.pause_time     = fc_conf->pause_time;
4672         hw->fc.high_water[0]  = fc_conf->high_water;
4673         hw->fc.low_water[0]   = fc_conf->low_water;
4674         hw->fc.send_xon       = fc_conf->send_xon;
4675         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4676
4677         err = ixgbe_fc_enable(hw);
4678
4679         /* Not negotiated is not an error case */
4680         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4681
4682                 /* check if we want to forward MAC frames - driver doesn't have native
4683                  * capability to do that, so we'll write the registers ourselves */
4684
4685                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4686
4687                 /* set or clear MFLCN.PMCF bit depending on configuration */
4688                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4689                         mflcn |= IXGBE_MFLCN_PMCF;
4690                 else
4691                         mflcn &= ~IXGBE_MFLCN_PMCF;
4692
4693                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4694                 IXGBE_WRITE_FLUSH(hw);
4695
4696                 return 0;
4697         }
4698
4699         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4700         return -EIO;
4701 }
4702
4703 /**
4704  *  ixgbe_pfc_enable_generic - Enable flow control
4705  *  @hw: pointer to hardware structure
4706  *  @tc_num: traffic class number
4707  *  Enable flow control according to the current settings.
4708  */
4709 static int
4710 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4711 {
4712         int ret_val = 0;
4713         uint32_t mflcn_reg, fccfg_reg;
4714         uint32_t reg;
4715         uint32_t fcrtl, fcrth;
4716         uint8_t i;
4717         uint8_t nb_rx_en;
4718
4719         /* Validate the water mark configuration */
4720         if (!hw->fc.pause_time) {
4721                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4722                 goto out;
4723         }
4724
4725         /* Low water mark of zero causes XOFF floods */
4726         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4727                  /* High/Low water can not be 0 */
4728                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4729                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4730                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4731                         goto out;
4732                 }
4733
4734                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4735                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4736                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4737                         goto out;
4738                 }
4739         }
4740         /* Negotiate the fc mode to use */
4741         ixgbe_fc_autoneg(hw);
4742
4743         /* Disable any previous flow control settings */
4744         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4745         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4746
4747         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4748         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4749
4750         switch (hw->fc.current_mode) {
4751         case ixgbe_fc_none:
4752                 /*
4753                  * If the count of enabled RX Priority Flow control >1,
4754                  * and the TX pause can not be disabled
4755                  */
4756                 nb_rx_en = 0;
4757                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4758                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4759                         if (reg & IXGBE_FCRTH_FCEN)
4760                                 nb_rx_en++;
4761                 }
4762                 if (nb_rx_en > 1)
4763                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4764                 break;
4765         case ixgbe_fc_rx_pause:
4766                 /*
4767                  * Rx Flow control is enabled and Tx Flow control is
4768                  * disabled by software override. Since there really
4769                  * isn't a way to advertise that we are capable of RX
4770                  * Pause ONLY, we will advertise that we support both
4771                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4772                  * disable the adapter's ability to send PAUSE frames.
4773                  */
4774                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4775                 /*
4776                  * If the count of enabled RX Priority Flow control >1,
4777                  * and the TX pause can not be disabled
4778                  */
4779                 nb_rx_en = 0;
4780                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4781                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4782                         if (reg & IXGBE_FCRTH_FCEN)
4783                                 nb_rx_en++;
4784                 }
4785                 if (nb_rx_en > 1)
4786                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4787                 break;
4788         case ixgbe_fc_tx_pause:
4789                 /*
4790                  * Tx Flow control is enabled, and Rx Flow control is
4791                  * disabled by software override.
4792                  */
4793                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4794                 break;
4795         case ixgbe_fc_full:
4796                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4797                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4798                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4799                 break;
4800         default:
4801                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4802                 ret_val = IXGBE_ERR_CONFIG;
4803                 goto out;
4804         }
4805
4806         /* Set 802.3x based flow control settings. */
4807         mflcn_reg |= IXGBE_MFLCN_DPF;
4808         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4809         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4810
4811         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4812         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4813                 hw->fc.high_water[tc_num]) {
4814                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4815                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4816                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4817         } else {
4818                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4819                 /*
4820                  * In order to prevent Tx hangs when the internal Tx
4821                  * switch is enabled we must set the high water mark
4822                  * to the maximum FCRTH value.  This allows the Tx
4823                  * switch to function even under heavy Rx workloads.
4824                  */
4825                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4826         }
4827         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4828
4829         /* Configure pause time (2 TCs per register) */
4830         reg = hw->fc.pause_time * 0x00010001;
4831         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4832                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4833
4834         /* Configure flow control refresh threshold value */
4835         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4836
4837 out:
4838         return ret_val;
4839 }
4840
4841 static int
4842 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4843 {
4844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4846
4847         if (hw->mac.type != ixgbe_mac_82598EB) {
4848                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4849         }
4850         return ret_val;
4851 }
4852
4853 static int
4854 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4855 {
4856         int err;
4857         uint32_t rx_buf_size;
4858         uint32_t max_high_water;
4859         uint8_t tc_num;
4860         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4861         struct ixgbe_hw *hw =
4862                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4863         struct ixgbe_dcb_config *dcb_config =
4864                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4865
4866         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4867                 ixgbe_fc_none,
4868                 ixgbe_fc_rx_pause,
4869                 ixgbe_fc_tx_pause,
4870                 ixgbe_fc_full
4871         };
4872
4873         PMD_INIT_FUNC_TRACE();
4874
4875         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4876         tc_num = map[pfc_conf->priority];
4877         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4878         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4879         /*
4880          * At least reserve one Ethernet frame for watermark
4881          * high_water/low_water in kilo bytes for ixgbe
4882          */
4883         max_high_water = (rx_buf_size -
4884                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4885         if ((pfc_conf->fc.high_water > max_high_water) ||
4886             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4887                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4888                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4889                 return -EINVAL;
4890         }
4891
4892         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4893         hw->fc.pause_time = pfc_conf->fc.pause_time;
4894         hw->fc.send_xon = pfc_conf->fc.send_xon;
4895         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4896         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4897
4898         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4899
4900         /* Not negotiated is not an error case */
4901         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4902                 return 0;
4903
4904         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4905         return -EIO;
4906 }
4907
4908 static int
4909 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4910                           struct rte_eth_rss_reta_entry64 *reta_conf,
4911                           uint16_t reta_size)
4912 {
4913         uint16_t i, sp_reta_size;
4914         uint8_t j, mask;
4915         uint32_t reta, r;
4916         uint16_t idx, shift;
4917         struct ixgbe_adapter *adapter = dev->data->dev_private;
4918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4919         uint32_t reta_reg;
4920
4921         PMD_INIT_FUNC_TRACE();
4922
4923         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4924                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4925                         "NIC.");
4926                 return -ENOTSUP;
4927         }
4928
4929         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4930         if (reta_size != sp_reta_size) {
4931                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4932                         "(%d) doesn't match the number hardware can supported "
4933                         "(%d)", reta_size, sp_reta_size);
4934                 return -EINVAL;
4935         }
4936
4937         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4938                 idx = i / RTE_RETA_GROUP_SIZE;
4939                 shift = i % RTE_RETA_GROUP_SIZE;
4940                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4941                                                 IXGBE_4_BIT_MASK);
4942                 if (!mask)
4943                         continue;
4944                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4945                 if (mask == IXGBE_4_BIT_MASK)
4946                         r = 0;
4947                 else
4948                         r = IXGBE_READ_REG(hw, reta_reg);
4949                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4950                         if (mask & (0x1 << j))
4951                                 reta |= reta_conf[idx].reta[shift + j] <<
4952                                                         (CHAR_BIT * j);
4953                         else
4954                                 reta |= r & (IXGBE_8_BIT_MASK <<
4955                                                 (CHAR_BIT * j));
4956                 }
4957                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4958         }
4959         adapter->rss_reta_updated = 1;
4960
4961         return 0;
4962 }
4963
4964 static int
4965 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4966                          struct rte_eth_rss_reta_entry64 *reta_conf,
4967                          uint16_t reta_size)
4968 {
4969         uint16_t i, sp_reta_size;
4970         uint8_t j, mask;
4971         uint32_t reta;
4972         uint16_t idx, shift;
4973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4974         uint32_t reta_reg;
4975
4976         PMD_INIT_FUNC_TRACE();
4977         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4978         if (reta_size != sp_reta_size) {
4979                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4980                         "(%d) doesn't match the number hardware can supported "
4981                         "(%d)", reta_size, sp_reta_size);
4982                 return -EINVAL;
4983         }
4984
4985         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4986                 idx = i / RTE_RETA_GROUP_SIZE;
4987                 shift = i % RTE_RETA_GROUP_SIZE;
4988                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4989                                                 IXGBE_4_BIT_MASK);
4990                 if (!mask)
4991                         continue;
4992
4993                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4994                 reta = IXGBE_READ_REG(hw, reta_reg);
4995                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4996                         if (mask & (0x1 << j))
4997                                 reta_conf[idx].reta[shift + j] =
4998                                         ((reta >> (CHAR_BIT * j)) &
4999                                                 IXGBE_8_BIT_MASK);
5000                 }
5001         }
5002
5003         return 0;
5004 }
5005
5006 static int
5007 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5008                                 uint32_t index, uint32_t pool)
5009 {
5010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5011         uint32_t enable_addr = 1;
5012
5013         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5014                              pool, enable_addr);
5015 }
5016
5017 static void
5018 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5019 {
5020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5021
5022         ixgbe_clear_rar(hw, index);
5023 }
5024
5025 static int
5026 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5027 {
5028         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5029
5030         ixgbe_remove_rar(dev, 0);
5031         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5032
5033         return 0;
5034 }
5035
5036 static bool
5037 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5038 {
5039         if (strcmp(dev->device->driver->name, drv->driver.name))
5040                 return false;
5041
5042         return true;
5043 }
5044
5045 bool
5046 is_ixgbe_supported(struct rte_eth_dev *dev)
5047 {
5048         return is_device_supported(dev, &rte_ixgbe_pmd);
5049 }
5050
5051 static int
5052 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5053 {
5054         uint32_t hlreg0;
5055         uint32_t maxfrs;
5056         struct ixgbe_hw *hw;
5057         struct rte_eth_dev_info dev_info;
5058         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5059         struct rte_eth_dev_data *dev_data = dev->data;
5060         int ret;
5061
5062         ret = ixgbe_dev_info_get(dev, &dev_info);
5063         if (ret != 0)
5064                 return ret;
5065
5066         /* check that mtu is within the allowed range */
5067         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5068                 return -EINVAL;
5069
5070         /* If device is started, refuse mtu that requires the support of
5071          * scattered packets when this feature has not been enabled before.
5072          */
5073         if (dev_data->dev_started && !dev_data->scattered_rx &&
5074             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5075              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5076                 PMD_INIT_LOG(ERR, "Stop port first.");
5077                 return -EINVAL;
5078         }
5079
5080         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5081         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5082
5083         /* switch to jumbo mode if needed */
5084         if (frame_size > RTE_ETHER_MAX_LEN) {
5085                 dev->data->dev_conf.rxmode.offloads |=
5086                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5087                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5088         } else {
5089                 dev->data->dev_conf.rxmode.offloads &=
5090                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5091                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5092         }
5093         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5094
5095         /* update max frame size */
5096         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5097
5098         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5099         maxfrs &= 0x0000FFFF;
5100         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5101         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5102
5103         return 0;
5104 }
5105
5106 /*
5107  * Virtual Function operations
5108  */
5109 static void
5110 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5111 {
5112         struct ixgbe_interrupt *intr =
5113                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5114         struct ixgbe_hw *hw =
5115                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5116
5117         PMD_INIT_FUNC_TRACE();
5118
5119         /* Clear interrupt mask to stop from interrupts being generated */
5120         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5121
5122         IXGBE_WRITE_FLUSH(hw);
5123
5124         /* Clear mask value. */
5125         intr->mask = 0;
5126 }
5127
5128 static void
5129 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5130 {
5131         struct ixgbe_interrupt *intr =
5132                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5133         struct ixgbe_hw *hw =
5134                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5135
5136         PMD_INIT_FUNC_TRACE();
5137
5138         /* VF enable interrupt autoclean */
5139         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5140         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5141         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5142
5143         IXGBE_WRITE_FLUSH(hw);
5144
5145         /* Save IXGBE_VTEIMS value to mask. */
5146         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5147 }
5148
5149 static int
5150 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5151 {
5152         struct rte_eth_conf *conf = &dev->data->dev_conf;
5153         struct ixgbe_adapter *adapter = dev->data->dev_private;
5154
5155         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5156                      dev->data->port_id);
5157
5158         /*
5159          * VF has no ability to enable/disable HW CRC
5160          * Keep the persistent behavior the same as Host PF
5161          */
5162 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5163         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5164                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5165                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5166         }
5167 #else
5168         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5169                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5170                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5171         }
5172 #endif
5173
5174         /*
5175          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5176          * allocation or vector Rx preconditions we will reset it.
5177          */
5178         adapter->rx_bulk_alloc_allowed = true;
5179         adapter->rx_vec_allowed = true;
5180
5181         return 0;
5182 }
5183
5184 static int
5185 ixgbevf_dev_start(struct rte_eth_dev *dev)
5186 {
5187         struct ixgbe_hw *hw =
5188                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5189         uint32_t intr_vector = 0;
5190         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5191         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5192
5193         int err, mask = 0;
5194
5195         PMD_INIT_FUNC_TRACE();
5196
5197         /* Stop the link setup handler before resetting the HW. */
5198         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5199
5200         err = hw->mac.ops.reset_hw(hw);
5201         if (err) {
5202                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5203                 return err;
5204         }
5205         hw->mac.get_link_status = true;
5206
5207         /* negotiate mailbox API version to use with the PF. */
5208         ixgbevf_negotiate_api(hw);
5209
5210         ixgbevf_dev_tx_init(dev);
5211
5212         /* This can fail when allocating mbufs for descriptor rings */
5213         err = ixgbevf_dev_rx_init(dev);
5214         if (err) {
5215                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5216                 ixgbe_dev_clear_queues(dev);
5217                 return err;
5218         }
5219
5220         /* Set vfta */
5221         ixgbevf_set_vfta_all(dev, 1);
5222
5223         /* Set HW strip */
5224         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5225                 ETH_VLAN_EXTEND_MASK;
5226         err = ixgbevf_vlan_offload_config(dev, mask);
5227         if (err) {
5228                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5229                 ixgbe_dev_clear_queues(dev);
5230                 return err;
5231         }
5232
5233         ixgbevf_dev_rxtx_start(dev);
5234
5235         /* check and configure queue intr-vector mapping */
5236         if (rte_intr_cap_multiple(intr_handle) &&
5237             dev->data->dev_conf.intr_conf.rxq) {
5238                 /* According to datasheet, only vector 0/1/2 can be used,
5239                  * now only one vector is used for Rx queue
5240                  */
5241                 intr_vector = 1;
5242                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5243                         return -1;
5244         }
5245
5246         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5247                 intr_handle->intr_vec =
5248                         rte_zmalloc("intr_vec",
5249                                     dev->data->nb_rx_queues * sizeof(int), 0);
5250                 if (intr_handle->intr_vec == NULL) {
5251                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5252                                      " intr_vec", dev->data->nb_rx_queues);
5253                         return -ENOMEM;
5254                 }
5255         }
5256         ixgbevf_configure_msix(dev);
5257
5258         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5259          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5260          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5261          * is not cleared, it will fail when following rte_intr_enable( ) tries
5262          * to map Rx queue interrupt to other VFIO vectors.
5263          * So clear uio/vfio intr/evevnfd first to avoid failure.
5264          */
5265         rte_intr_disable(intr_handle);
5266
5267         rte_intr_enable(intr_handle);
5268
5269         /* Re-enable interrupt for VF */
5270         ixgbevf_intr_enable(dev);
5271
5272         /*
5273          * Update link status right before return, because it may
5274          * start link configuration process in a separate thread.
5275          */
5276         ixgbevf_dev_link_update(dev, 0);
5277
5278         hw->adapter_stopped = false;
5279
5280         return 0;
5281 }
5282
5283 static void
5284 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5285 {
5286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5287         struct ixgbe_adapter *adapter = dev->data->dev_private;
5288         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5289         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5290
5291         if (hw->adapter_stopped)
5292                 return;
5293
5294         PMD_INIT_FUNC_TRACE();
5295
5296         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5297
5298         ixgbevf_intr_disable(dev);
5299
5300         hw->adapter_stopped = 1;
5301         ixgbe_stop_adapter(hw);
5302
5303         /*
5304           * Clear what we set, but we still keep shadow_vfta to
5305           * restore after device starts
5306           */
5307         ixgbevf_set_vfta_all(dev, 0);
5308
5309         /* Clear stored conf */
5310         dev->data->scattered_rx = 0;
5311
5312         ixgbe_dev_clear_queues(dev);
5313
5314         /* Clean datapath event and queue/vec mapping */
5315         rte_intr_efd_disable(intr_handle);
5316         if (intr_handle->intr_vec != NULL) {
5317                 rte_free(intr_handle->intr_vec);
5318                 intr_handle->intr_vec = NULL;
5319         }
5320
5321         adapter->rss_reta_updated = 0;
5322 }
5323
5324 static void
5325 ixgbevf_dev_close(struct rte_eth_dev *dev)
5326 {
5327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5328         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5329         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5330
5331         PMD_INIT_FUNC_TRACE();
5332
5333         ixgbe_reset_hw(hw);
5334
5335         ixgbevf_dev_stop(dev);
5336
5337         ixgbe_dev_free_queues(dev);
5338
5339         /**
5340          * Remove the VF MAC address ro ensure
5341          * that the VF traffic goes to the PF
5342          * after stop, close and detach of the VF
5343          **/
5344         ixgbevf_remove_mac_addr(dev, 0);
5345
5346         dev->dev_ops = NULL;
5347         dev->rx_pkt_burst = NULL;
5348         dev->tx_pkt_burst = NULL;
5349
5350         rte_intr_disable(intr_handle);
5351         rte_intr_callback_unregister(intr_handle,
5352                                      ixgbevf_dev_interrupt_handler, dev);
5353 }
5354
5355 /*
5356  * Reset VF device
5357  */
5358 static int
5359 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5360 {
5361         int ret;
5362
5363         ret = eth_ixgbevf_dev_uninit(dev);
5364         if (ret)
5365                 return ret;
5366
5367         ret = eth_ixgbevf_dev_init(dev);
5368
5369         return ret;
5370 }
5371
5372 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5373 {
5374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5375         struct ixgbe_vfta *shadow_vfta =
5376                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5377         int i = 0, j = 0, vfta = 0, mask = 1;
5378
5379         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5380                 vfta = shadow_vfta->vfta[i];
5381                 if (vfta) {
5382                         mask = 1;
5383                         for (j = 0; j < 32; j++) {
5384                                 if (vfta & mask)
5385                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5386                                                        on, false);
5387                                 mask <<= 1;
5388                         }
5389                 }
5390         }
5391
5392 }
5393
5394 static int
5395 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5396 {
5397         struct ixgbe_hw *hw =
5398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5399         struct ixgbe_vfta *shadow_vfta =
5400                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5401         uint32_t vid_idx = 0;
5402         uint32_t vid_bit = 0;
5403         int ret = 0;
5404
5405         PMD_INIT_FUNC_TRACE();
5406
5407         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5408         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5409         if (ret) {
5410                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5411                 return ret;
5412         }
5413         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5414         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5415
5416         /* Save what we set and retore it after device reset */
5417         if (on)
5418                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5419         else
5420                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5421
5422         return 0;
5423 }
5424
5425 static void
5426 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5427 {
5428         struct ixgbe_hw *hw =
5429                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5430         uint32_t ctrl;
5431
5432         PMD_INIT_FUNC_TRACE();
5433
5434         if (queue >= hw->mac.max_rx_queues)
5435                 return;
5436
5437         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5438         if (on)
5439                 ctrl |= IXGBE_RXDCTL_VME;
5440         else
5441                 ctrl &= ~IXGBE_RXDCTL_VME;
5442         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5443
5444         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5445 }
5446
5447 static int
5448 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5449 {
5450         struct ixgbe_rx_queue *rxq;
5451         uint16_t i;
5452         int on = 0;
5453
5454         /* VF function only support hw strip feature, others are not support */
5455         if (mask & ETH_VLAN_STRIP_MASK) {
5456                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5457                         rxq = dev->data->rx_queues[i];
5458                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5459                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5460                 }
5461         }
5462
5463         return 0;
5464 }
5465
5466 static int
5467 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5468 {
5469         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5470
5471         ixgbevf_vlan_offload_config(dev, mask);
5472
5473         return 0;
5474 }
5475
5476 int
5477 ixgbe_vt_check(struct ixgbe_hw *hw)
5478 {
5479         uint32_t reg_val;
5480
5481         /* if Virtualization Technology is enabled */
5482         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5483         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5484                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5485                 return -1;
5486         }
5487
5488         return 0;
5489 }
5490
5491 static uint32_t
5492 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5493 {
5494         uint32_t vector = 0;
5495
5496         switch (hw->mac.mc_filter_type) {
5497         case 0:   /* use bits [47:36] of the address */
5498                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5499                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5500                 break;
5501         case 1:   /* use bits [46:35] of the address */
5502                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5503                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5504                 break;
5505         case 2:   /* use bits [45:34] of the address */
5506                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5507                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5508                 break;
5509         case 3:   /* use bits [43:32] of the address */
5510                 vector = ((uc_addr->addr_bytes[4]) |
5511                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5512                 break;
5513         default:  /* Invalid mc_filter_type */
5514                 break;
5515         }
5516
5517         /* vector can only be 12-bits or boundary will be exceeded */
5518         vector &= 0xFFF;
5519         return vector;
5520 }
5521
5522 static int
5523 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5524                         struct rte_ether_addr *mac_addr, uint8_t on)
5525 {
5526         uint32_t vector;
5527         uint32_t uta_idx;
5528         uint32_t reg_val;
5529         uint32_t uta_shift;
5530         uint32_t rc;
5531         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5532         const uint32_t ixgbe_uta_bit_shift = 5;
5533         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5534         const uint32_t bit1 = 0x1;
5535
5536         struct ixgbe_hw *hw =
5537                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5538         struct ixgbe_uta_info *uta_info =
5539                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5540
5541         /* The UTA table only exists on 82599 hardware and newer */
5542         if (hw->mac.type < ixgbe_mac_82599EB)
5543                 return -ENOTSUP;
5544
5545         vector = ixgbe_uta_vector(hw, mac_addr);
5546         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5547         uta_shift = vector & ixgbe_uta_bit_mask;
5548
5549         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5550         if (rc == on)
5551                 return 0;
5552
5553         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5554         if (on) {
5555                 uta_info->uta_in_use++;
5556                 reg_val |= (bit1 << uta_shift);
5557                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5558         } else {
5559                 uta_info->uta_in_use--;
5560                 reg_val &= ~(bit1 << uta_shift);
5561                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5562         }
5563
5564         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5565
5566         if (uta_info->uta_in_use > 0)
5567                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5568                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5569         else
5570                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5571
5572         return 0;
5573 }
5574
5575 static int
5576 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5577 {
5578         int i;
5579         struct ixgbe_hw *hw =
5580                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5581         struct ixgbe_uta_info *uta_info =
5582                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5583
5584         /* The UTA table only exists on 82599 hardware and newer */
5585         if (hw->mac.type < ixgbe_mac_82599EB)
5586                 return -ENOTSUP;
5587
5588         if (on) {
5589                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5590                         uta_info->uta_shadow[i] = ~0;
5591                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5592                 }
5593         } else {
5594                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5595                         uta_info->uta_shadow[i] = 0;
5596                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5597                 }
5598         }
5599         return 0;
5600
5601 }
5602
5603 uint32_t
5604 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5605 {
5606         uint32_t new_val = orig_val;
5607
5608         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5609                 new_val |= IXGBE_VMOLR_AUPE;
5610         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5611                 new_val |= IXGBE_VMOLR_ROMPE;
5612         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5613                 new_val |= IXGBE_VMOLR_ROPE;
5614         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5615                 new_val |= IXGBE_VMOLR_BAM;
5616         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5617                 new_val |= IXGBE_VMOLR_MPE;
5618
5619         return new_val;
5620 }
5621
5622 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5623 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5624 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5625 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5626 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5627         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5628         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5629
5630 static int
5631 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5632                       struct rte_eth_mirror_conf *mirror_conf,
5633                       uint8_t rule_id, uint8_t on)
5634 {
5635         uint32_t mr_ctl, vlvf;
5636         uint32_t mp_lsb = 0;
5637         uint32_t mv_msb = 0;
5638         uint32_t mv_lsb = 0;
5639         uint32_t mp_msb = 0;
5640         uint8_t i = 0;
5641         int reg_index = 0;
5642         uint64_t vlan_mask = 0;
5643
5644         const uint8_t pool_mask_offset = 32;
5645         const uint8_t vlan_mask_offset = 32;
5646         const uint8_t dst_pool_offset = 8;
5647         const uint8_t rule_mr_offset  = 4;
5648         const uint8_t mirror_rule_mask = 0x0F;
5649
5650         struct ixgbe_mirror_info *mr_info =
5651                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5652         struct ixgbe_hw *hw =
5653                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5654         uint8_t mirror_type = 0;
5655
5656         if (ixgbe_vt_check(hw) < 0)
5657                 return -ENOTSUP;
5658
5659         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5660                 return -EINVAL;
5661
5662         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5663                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5664                             mirror_conf->rule_type);
5665                 return -EINVAL;
5666         }
5667
5668         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5669                 mirror_type |= IXGBE_MRCTL_VLME;
5670                 /* Check if vlan id is valid and find conresponding VLAN ID
5671                  * index in VLVF
5672                  */
5673                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5674                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5675                                 /* search vlan id related pool vlan filter
5676                                  * index
5677                                  */
5678                                 reg_index = ixgbe_find_vlvf_slot(
5679                                                 hw,
5680                                                 mirror_conf->vlan.vlan_id[i],
5681                                                 false);
5682                                 if (reg_index < 0)
5683                                         return -EINVAL;
5684                                 vlvf = IXGBE_READ_REG(hw,
5685                                                       IXGBE_VLVF(reg_index));
5686                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5687                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5688                                       mirror_conf->vlan.vlan_id[i]))
5689                                         vlan_mask |= (1ULL << reg_index);
5690                                 else
5691                                         return -EINVAL;
5692                         }
5693                 }
5694
5695                 if (on) {
5696                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5697                         mv_msb = vlan_mask >> vlan_mask_offset;
5698
5699                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5700                                                 mirror_conf->vlan.vlan_mask;
5701                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5702                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5703                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5704                                                 mirror_conf->vlan.vlan_id[i];
5705                         }
5706                 } else {
5707                         mv_lsb = 0;
5708                         mv_msb = 0;
5709                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5710                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5711                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5712                 }
5713         }
5714
5715         /**
5716          * if enable pool mirror, write related pool mask register,if disable
5717          * pool mirror, clear PFMRVM register
5718          */
5719         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5720                 mirror_type |= IXGBE_MRCTL_VPME;
5721                 if (on) {
5722                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5723                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5724                         mr_info->mr_conf[rule_id].pool_mask =
5725                                         mirror_conf->pool_mask;
5726
5727                 } else {
5728                         mp_lsb = 0;
5729                         mp_msb = 0;
5730                         mr_info->mr_conf[rule_id].pool_mask = 0;
5731                 }
5732         }
5733         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5734                 mirror_type |= IXGBE_MRCTL_UPME;
5735         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5736                 mirror_type |= IXGBE_MRCTL_DPME;
5737
5738         /* read  mirror control register and recalculate it */
5739         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5740
5741         if (on) {
5742                 mr_ctl |= mirror_type;
5743                 mr_ctl &= mirror_rule_mask;
5744                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5745         } else {
5746                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5747         }
5748
5749         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5750         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5751
5752         /* write mirrror control  register */
5753         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5754
5755         /* write pool mirrror control  register */
5756         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5757                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5758                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5759                                 mp_msb);
5760         }
5761         /* write VLAN mirrror control  register */
5762         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5763                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5764                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5765                                 mv_msb);
5766         }
5767
5768         return 0;
5769 }
5770
5771 static int
5772 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5773 {
5774         int mr_ctl = 0;
5775         uint32_t lsb_val = 0;
5776         uint32_t msb_val = 0;
5777         const uint8_t rule_mr_offset = 4;
5778
5779         struct ixgbe_hw *hw =
5780                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5781         struct ixgbe_mirror_info *mr_info =
5782                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5783
5784         if (ixgbe_vt_check(hw) < 0)
5785                 return -ENOTSUP;
5786
5787         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5788                 return -EINVAL;
5789
5790         memset(&mr_info->mr_conf[rule_id], 0,
5791                sizeof(struct rte_eth_mirror_conf));
5792
5793         /* clear PFVMCTL register */
5794         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5795
5796         /* clear pool mask register */
5797         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5798         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5799
5800         /* clear vlan mask register */
5801         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5802         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5803
5804         return 0;
5805 }
5806
5807 static int
5808 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5809 {
5810         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5811         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5812         struct ixgbe_interrupt *intr =
5813                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5814         struct ixgbe_hw *hw =
5815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5816         uint32_t vec = IXGBE_MISC_VEC_ID;
5817
5818         if (rte_intr_allow_others(intr_handle))
5819                 vec = IXGBE_RX_VEC_START;
5820         intr->mask |= (1 << vec);
5821         RTE_SET_USED(queue_id);
5822         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5823
5824         rte_intr_ack(intr_handle);
5825
5826         return 0;
5827 }
5828
5829 static int
5830 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5831 {
5832         struct ixgbe_interrupt *intr =
5833                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5834         struct ixgbe_hw *hw =
5835                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5836         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5837         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5838         uint32_t vec = IXGBE_MISC_VEC_ID;
5839
5840         if (rte_intr_allow_others(intr_handle))
5841                 vec = IXGBE_RX_VEC_START;
5842         intr->mask &= ~(1 << vec);
5843         RTE_SET_USED(queue_id);
5844         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5845
5846         return 0;
5847 }
5848
5849 static int
5850 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5851 {
5852         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5853         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5854         uint32_t mask;
5855         struct ixgbe_hw *hw =
5856                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5857         struct ixgbe_interrupt *intr =
5858                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5859
5860         if (queue_id < 16) {
5861                 ixgbe_disable_intr(hw);
5862                 intr->mask |= (1 << queue_id);
5863                 ixgbe_enable_intr(dev);
5864         } else if (queue_id < 32) {
5865                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5866                 mask &= (1 << queue_id);
5867                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5868         } else if (queue_id < 64) {
5869                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5870                 mask &= (1 << (queue_id - 32));
5871                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5872         }
5873         rte_intr_ack(intr_handle);
5874
5875         return 0;
5876 }
5877
5878 static int
5879 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5880 {
5881         uint32_t mask;
5882         struct ixgbe_hw *hw =
5883                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5884         struct ixgbe_interrupt *intr =
5885                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5886
5887         if (queue_id < 16) {
5888                 ixgbe_disable_intr(hw);
5889                 intr->mask &= ~(1 << queue_id);
5890                 ixgbe_enable_intr(dev);
5891         } else if (queue_id < 32) {
5892                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5893                 mask &= ~(1 << queue_id);
5894                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5895         } else if (queue_id < 64) {
5896                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5897                 mask &= ~(1 << (queue_id - 32));
5898                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5899         }
5900
5901         return 0;
5902 }
5903
5904 static void
5905 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5906                      uint8_t queue, uint8_t msix_vector)
5907 {
5908         uint32_t tmp, idx;
5909
5910         if (direction == -1) {
5911                 /* other causes */
5912                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5913                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5914                 tmp &= ~0xFF;
5915                 tmp |= msix_vector;
5916                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5917         } else {
5918                 /* rx or tx cause */
5919                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5920                 idx = ((16 * (queue & 1)) + (8 * direction));
5921                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5922                 tmp &= ~(0xFF << idx);
5923                 tmp |= (msix_vector << idx);
5924                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5925         }
5926 }
5927
5928 /**
5929  * set the IVAR registers, mapping interrupt causes to vectors
5930  * @param hw
5931  *  pointer to ixgbe_hw struct
5932  * @direction
5933  *  0 for Rx, 1 for Tx, -1 for other causes
5934  * @queue
5935  *  queue to map the corresponding interrupt to
5936  * @msix_vector
5937  *  the vector to map to the corresponding queue
5938  */
5939 static void
5940 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5941                    uint8_t queue, uint8_t msix_vector)
5942 {
5943         uint32_t tmp, idx;
5944
5945         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5946         if (hw->mac.type == ixgbe_mac_82598EB) {
5947                 if (direction == -1)
5948                         direction = 0;
5949                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5950                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5951                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5952                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5953                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5954         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5955                         (hw->mac.type == ixgbe_mac_X540) ||
5956                         (hw->mac.type == ixgbe_mac_X550) ||
5957                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5958                 if (direction == -1) {
5959                         /* other causes */
5960                         idx = ((queue & 1) * 8);
5961                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5962                         tmp &= ~(0xFF << idx);
5963                         tmp |= (msix_vector << idx);
5964                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5965                 } else {
5966                         /* rx or tx causes */
5967                         idx = ((16 * (queue & 1)) + (8 * direction));
5968                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5969                         tmp &= ~(0xFF << idx);
5970                         tmp |= (msix_vector << idx);
5971                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5972                 }
5973         }
5974 }
5975
5976 static void
5977 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5978 {
5979         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5980         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5981         struct ixgbe_hw *hw =
5982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5983         uint32_t q_idx;
5984         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5985         uint32_t base = IXGBE_MISC_VEC_ID;
5986
5987         /* Configure VF other cause ivar */
5988         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5989
5990         /* won't configure msix register if no mapping is done
5991          * between intr vector and event fd.
5992          */
5993         if (!rte_intr_dp_is_en(intr_handle))
5994                 return;
5995
5996         if (rte_intr_allow_others(intr_handle)) {
5997                 base = IXGBE_RX_VEC_START;
5998                 vector_idx = IXGBE_RX_VEC_START;
5999         }
6000
6001         /* Configure all RX queues of VF */
6002         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6003                 /* Force all queue use vector 0,
6004                  * as IXGBE_VF_MAXMSIVECOTR = 1
6005                  */
6006                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6007                 intr_handle->intr_vec[q_idx] = vector_idx;
6008                 if (vector_idx < base + intr_handle->nb_efd - 1)
6009                         vector_idx++;
6010         }
6011
6012         /* As RX queue setting above show, all queues use the vector 0.
6013          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6014          */
6015         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6016                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6017                         | IXGBE_EITR_CNT_WDIS);
6018 }
6019
6020 /**
6021  * Sets up the hardware to properly generate MSI-X interrupts
6022  * @hw
6023  *  board private structure
6024  */
6025 static void
6026 ixgbe_configure_msix(struct rte_eth_dev *dev)
6027 {
6028         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6029         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6030         struct ixgbe_hw *hw =
6031                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6032         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6033         uint32_t vec = IXGBE_MISC_VEC_ID;
6034         uint32_t mask;
6035         uint32_t gpie;
6036
6037         /* won't configure msix register if no mapping is done
6038          * between intr vector and event fd
6039          * but if misx has been enabled already, need to configure
6040          * auto clean, auto mask and throttling.
6041          */
6042         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6043         if (!rte_intr_dp_is_en(intr_handle) &&
6044             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6045                 return;
6046
6047         if (rte_intr_allow_others(intr_handle))
6048                 vec = base = IXGBE_RX_VEC_START;
6049
6050         /* setup GPIE for MSI-x mode */
6051         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6052         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6053                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6054         /* auto clearing and auto setting corresponding bits in EIMS
6055          * when MSI-X interrupt is triggered
6056          */
6057         if (hw->mac.type == ixgbe_mac_82598EB) {
6058                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6059         } else {
6060                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6061                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6062         }
6063         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6064
6065         /* Populate the IVAR table and set the ITR values to the
6066          * corresponding register.
6067          */
6068         if (rte_intr_dp_is_en(intr_handle)) {
6069                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6070                         queue_id++) {
6071                         /* by default, 1:1 mapping */
6072                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6073                         intr_handle->intr_vec[queue_id] = vec;
6074                         if (vec < base + intr_handle->nb_efd - 1)
6075                                 vec++;
6076                 }
6077
6078                 switch (hw->mac.type) {
6079                 case ixgbe_mac_82598EB:
6080                         ixgbe_set_ivar_map(hw, -1,
6081                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6082                                            IXGBE_MISC_VEC_ID);
6083                         break;
6084                 case ixgbe_mac_82599EB:
6085                 case ixgbe_mac_X540:
6086                 case ixgbe_mac_X550:
6087                 case ixgbe_mac_X550EM_x:
6088                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6089                         break;
6090                 default:
6091                         break;
6092                 }
6093         }
6094         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6095                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6096                         | IXGBE_EITR_CNT_WDIS);
6097
6098         /* set up to autoclear timer, and the vectors */
6099         mask = IXGBE_EIMS_ENABLE_MASK;
6100         mask &= ~(IXGBE_EIMS_OTHER |
6101                   IXGBE_EIMS_MAILBOX |
6102                   IXGBE_EIMS_LSC);
6103
6104         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6105 }
6106
6107 int
6108 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6109                            uint16_t queue_idx, uint16_t tx_rate)
6110 {
6111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6112         struct rte_eth_rxmode *rxmode;
6113         uint32_t rf_dec, rf_int;
6114         uint32_t bcnrc_val;
6115         uint16_t link_speed = dev->data->dev_link.link_speed;
6116
6117         if (queue_idx >= hw->mac.max_tx_queues)
6118                 return -EINVAL;
6119
6120         if (tx_rate != 0) {
6121                 /* Calculate the rate factor values to set */
6122                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6123                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6124                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6125
6126                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6127                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6128                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6129                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6130         } else {
6131                 bcnrc_val = 0;
6132         }
6133
6134         rxmode = &dev->data->dev_conf.rxmode;
6135         /*
6136          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6137          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6138          * set as 0x4.
6139          */
6140         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6141             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6142                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6143                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6144         else
6145                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6146                         IXGBE_MMW_SIZE_DEFAULT);
6147
6148         /* Set RTTBCNRC of queue X */
6149         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6150         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6151         IXGBE_WRITE_FLUSH(hw);
6152
6153         return 0;
6154 }
6155
6156 static int
6157 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6158                      __attribute__((unused)) uint32_t index,
6159                      __attribute__((unused)) uint32_t pool)
6160 {
6161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6162         int diag;
6163
6164         /*
6165          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6166          * operation. Trap this case to avoid exhausting the [very limited]
6167          * set of PF resources used to store VF MAC addresses.
6168          */
6169         if (memcmp(hw->mac.perm_addr, mac_addr,
6170                         sizeof(struct rte_ether_addr)) == 0)
6171                 return -1;
6172         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6173         if (diag != 0)
6174                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6175                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6176                             mac_addr->addr_bytes[0],
6177                             mac_addr->addr_bytes[1],
6178                             mac_addr->addr_bytes[2],
6179                             mac_addr->addr_bytes[3],
6180                             mac_addr->addr_bytes[4],
6181                             mac_addr->addr_bytes[5],
6182                             diag);
6183         return diag;
6184 }
6185
6186 static void
6187 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6188 {
6189         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6190         struct rte_ether_addr *perm_addr =
6191                 (struct rte_ether_addr *)hw->mac.perm_addr;
6192         struct rte_ether_addr *mac_addr;
6193         uint32_t i;
6194         int diag;
6195
6196         /*
6197          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6198          * not support the deletion of a given MAC address.
6199          * Instead, it imposes to delete all MAC addresses, then to add again
6200          * all MAC addresses with the exception of the one to be deleted.
6201          */
6202         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6203
6204         /*
6205          * Add again all MAC addresses, with the exception of the deleted one
6206          * and of the permanent MAC address.
6207          */
6208         for (i = 0, mac_addr = dev->data->mac_addrs;
6209              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6210                 /* Skip the deleted MAC address */
6211                 if (i == index)
6212                         continue;
6213                 /* Skip NULL MAC addresses */
6214                 if (rte_is_zero_ether_addr(mac_addr))
6215                         continue;
6216                 /* Skip the permanent MAC address */
6217                 if (memcmp(perm_addr, mac_addr,
6218                                 sizeof(struct rte_ether_addr)) == 0)
6219                         continue;
6220                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6221                 if (diag != 0)
6222                         PMD_DRV_LOG(ERR,
6223                                     "Adding again MAC address "
6224                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6225                                     "diag=%d",
6226                                     mac_addr->addr_bytes[0],
6227                                     mac_addr->addr_bytes[1],
6228                                     mac_addr->addr_bytes[2],
6229                                     mac_addr->addr_bytes[3],
6230                                     mac_addr->addr_bytes[4],
6231                                     mac_addr->addr_bytes[5],
6232                                     diag);
6233         }
6234 }
6235
6236 static int
6237 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6238                         struct rte_ether_addr *addr)
6239 {
6240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6241
6242         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6243
6244         return 0;
6245 }
6246
6247 int
6248 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6249                         struct rte_eth_syn_filter *filter,
6250                         bool add)
6251 {
6252         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6253         struct ixgbe_filter_info *filter_info =
6254                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6255         uint32_t syn_info;
6256         uint32_t synqf;
6257
6258         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6259                 return -EINVAL;
6260
6261         syn_info = filter_info->syn_info;
6262
6263         if (add) {
6264                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6265                         return -EINVAL;
6266                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6267                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6268
6269                 if (filter->hig_pri)
6270                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6271                 else
6272                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6273         } else {
6274                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6275                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6276                         return -ENOENT;
6277                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6278         }
6279
6280         filter_info->syn_info = synqf;
6281         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6282         IXGBE_WRITE_FLUSH(hw);
6283         return 0;
6284 }
6285
6286 static int
6287 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6288                         struct rte_eth_syn_filter *filter)
6289 {
6290         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6291         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6292
6293         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6294                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6295                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6296                 return 0;
6297         }
6298         return -ENOENT;
6299 }
6300
6301 static int
6302 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6303                         enum rte_filter_op filter_op,
6304                         void *arg)
6305 {
6306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6307         int ret;
6308
6309         MAC_TYPE_FILTER_SUP(hw->mac.type);
6310
6311         if (filter_op == RTE_ETH_FILTER_NOP)
6312                 return 0;
6313
6314         if (arg == NULL) {
6315                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6316                             filter_op);
6317                 return -EINVAL;
6318         }
6319
6320         switch (filter_op) {
6321         case RTE_ETH_FILTER_ADD:
6322                 ret = ixgbe_syn_filter_set(dev,
6323                                 (struct rte_eth_syn_filter *)arg,
6324                                 TRUE);
6325                 break;
6326         case RTE_ETH_FILTER_DELETE:
6327                 ret = ixgbe_syn_filter_set(dev,
6328                                 (struct rte_eth_syn_filter *)arg,
6329                                 FALSE);
6330                 break;
6331         case RTE_ETH_FILTER_GET:
6332                 ret = ixgbe_syn_filter_get(dev,
6333                                 (struct rte_eth_syn_filter *)arg);
6334                 break;
6335         default:
6336                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6337                 ret = -EINVAL;
6338                 break;
6339         }
6340
6341         return ret;
6342 }
6343
6344
6345 static inline enum ixgbe_5tuple_protocol
6346 convert_protocol_type(uint8_t protocol_value)
6347 {
6348         if (protocol_value == IPPROTO_TCP)
6349                 return IXGBE_FILTER_PROTOCOL_TCP;
6350         else if (protocol_value == IPPROTO_UDP)
6351                 return IXGBE_FILTER_PROTOCOL_UDP;
6352         else if (protocol_value == IPPROTO_SCTP)
6353                 return IXGBE_FILTER_PROTOCOL_SCTP;
6354         else
6355                 return IXGBE_FILTER_PROTOCOL_NONE;
6356 }
6357
6358 /* inject a 5-tuple filter to HW */
6359 static inline void
6360 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6361                            struct ixgbe_5tuple_filter *filter)
6362 {
6363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6364         int i;
6365         uint32_t ftqf, sdpqf;
6366         uint32_t l34timir = 0;
6367         uint8_t mask = 0xff;
6368
6369         i = filter->index;
6370
6371         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6372                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6373         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6374
6375         ftqf = (uint32_t)(filter->filter_info.proto &
6376                 IXGBE_FTQF_PROTOCOL_MASK);
6377         ftqf |= (uint32_t)((filter->filter_info.priority &
6378                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6379         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6380                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6381         if (filter->filter_info.dst_ip_mask == 0)
6382                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6383         if (filter->filter_info.src_port_mask == 0)
6384                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6385         if (filter->filter_info.dst_port_mask == 0)
6386                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6387         if (filter->filter_info.proto_mask == 0)
6388                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6389         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6390         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6391         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6392
6393         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6394         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6395         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6396         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6397
6398         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6399         l34timir |= (uint32_t)(filter->queue <<
6400                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6401         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6402 }
6403
6404 /*
6405  * add a 5tuple filter
6406  *
6407  * @param
6408  * dev: Pointer to struct rte_eth_dev.
6409  * index: the index the filter allocates.
6410  * filter: ponter to the filter that will be added.
6411  * rx_queue: the queue id the filter assigned to.
6412  *
6413  * @return
6414  *    - On success, zero.
6415  *    - On failure, a negative value.
6416  */
6417 static int
6418 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6419                         struct ixgbe_5tuple_filter *filter)
6420 {
6421         struct ixgbe_filter_info *filter_info =
6422                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6423         int i, idx, shift;
6424
6425         /*
6426          * look for an unused 5tuple filter index,
6427          * and insert the filter to list.
6428          */
6429         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6430                 idx = i / (sizeof(uint32_t) * NBBY);
6431                 shift = i % (sizeof(uint32_t) * NBBY);
6432                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6433                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6434                         filter->index = i;
6435                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6436                                           filter,
6437                                           entries);
6438                         break;
6439                 }
6440         }
6441         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6442                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6443                 return -ENOSYS;
6444         }
6445
6446         ixgbe_inject_5tuple_filter(dev, filter);
6447
6448         return 0;
6449 }
6450
6451 /*
6452  * remove a 5tuple filter
6453  *
6454  * @param
6455  * dev: Pointer to struct rte_eth_dev.
6456  * filter: the pointer of the filter will be removed.
6457  */
6458 static void
6459 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6460                         struct ixgbe_5tuple_filter *filter)
6461 {
6462         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6463         struct ixgbe_filter_info *filter_info =
6464                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6465         uint16_t index = filter->index;
6466
6467         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6468                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6469         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6470         rte_free(filter);
6471
6472         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6473         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6474         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6475         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6476         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6477 }
6478
6479 static int
6480 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6481 {
6482         struct ixgbe_hw *hw;
6483         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6484         struct rte_eth_dev_data *dev_data = dev->data;
6485
6486         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6487
6488         if (mtu < RTE_ETHER_MIN_MTU ||
6489                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6490                 return -EINVAL;
6491
6492         /* If device is started, refuse mtu that requires the support of
6493          * scattered packets when this feature has not been enabled before.
6494          */
6495         if (dev_data->dev_started && !dev_data->scattered_rx &&
6496             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6497              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6498                 PMD_INIT_LOG(ERR, "Stop port first.");
6499                 return -EINVAL;
6500         }
6501
6502         /*
6503          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6504          * request of the version 2.0 of the mailbox API.
6505          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6506          * of the mailbox API.
6507          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6508          * prior to 3.11.33 which contains the following change:
6509          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6510          */
6511         ixgbevf_rlpml_set_vf(hw, max_frame);
6512
6513         /* update max frame size */
6514         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6515         return 0;
6516 }
6517
6518 static inline struct ixgbe_5tuple_filter *
6519 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6520                         struct ixgbe_5tuple_filter_info *key)
6521 {
6522         struct ixgbe_5tuple_filter *it;
6523
6524         TAILQ_FOREACH(it, filter_list, entries) {
6525                 if (memcmp(key, &it->filter_info,
6526                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6527                         return it;
6528                 }
6529         }
6530         return NULL;
6531 }
6532
6533 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6534 static inline int
6535 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6536                         struct ixgbe_5tuple_filter_info *filter_info)
6537 {
6538         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6539                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6540                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6541                 return -EINVAL;
6542
6543         switch (filter->dst_ip_mask) {
6544         case UINT32_MAX:
6545                 filter_info->dst_ip_mask = 0;
6546                 filter_info->dst_ip = filter->dst_ip;
6547                 break;
6548         case 0:
6549                 filter_info->dst_ip_mask = 1;
6550                 break;
6551         default:
6552                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6553                 return -EINVAL;
6554         }
6555
6556         switch (filter->src_ip_mask) {
6557         case UINT32_MAX:
6558                 filter_info->src_ip_mask = 0;
6559                 filter_info->src_ip = filter->src_ip;
6560                 break;
6561         case 0:
6562                 filter_info->src_ip_mask = 1;
6563                 break;
6564         default:
6565                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6566                 return -EINVAL;
6567         }
6568
6569         switch (filter->dst_port_mask) {
6570         case UINT16_MAX:
6571                 filter_info->dst_port_mask = 0;
6572                 filter_info->dst_port = filter->dst_port;
6573                 break;
6574         case 0:
6575                 filter_info->dst_port_mask = 1;
6576                 break;
6577         default:
6578                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6579                 return -EINVAL;
6580         }
6581
6582         switch (filter->src_port_mask) {
6583         case UINT16_MAX:
6584                 filter_info->src_port_mask = 0;
6585                 filter_info->src_port = filter->src_port;
6586                 break;
6587         case 0:
6588                 filter_info->src_port_mask = 1;
6589                 break;
6590         default:
6591                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6592                 return -EINVAL;
6593         }
6594
6595         switch (filter->proto_mask) {
6596         case UINT8_MAX:
6597                 filter_info->proto_mask = 0;
6598                 filter_info->proto =
6599                         convert_protocol_type(filter->proto);
6600                 break;
6601         case 0:
6602                 filter_info->proto_mask = 1;
6603                 break;
6604         default:
6605                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6606                 return -EINVAL;
6607         }
6608
6609         filter_info->priority = (uint8_t)filter->priority;
6610         return 0;
6611 }
6612
6613 /*
6614  * add or delete a ntuple filter
6615  *
6616  * @param
6617  * dev: Pointer to struct rte_eth_dev.
6618  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6619  * add: if true, add filter, if false, remove filter
6620  *
6621  * @return
6622  *    - On success, zero.
6623  *    - On failure, a negative value.
6624  */
6625 int
6626 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6627                         struct rte_eth_ntuple_filter *ntuple_filter,
6628                         bool add)
6629 {
6630         struct ixgbe_filter_info *filter_info =
6631                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6632         struct ixgbe_5tuple_filter_info filter_5tuple;
6633         struct ixgbe_5tuple_filter *filter;
6634         int ret;
6635
6636         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6637                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6638                 return -EINVAL;
6639         }
6640
6641         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6642         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6643         if (ret < 0)
6644                 return ret;
6645
6646         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6647                                          &filter_5tuple);
6648         if (filter != NULL && add) {
6649                 PMD_DRV_LOG(ERR, "filter exists.");
6650                 return -EEXIST;
6651         }
6652         if (filter == NULL && !add) {
6653                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6654                 return -ENOENT;
6655         }
6656
6657         if (add) {
6658                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6659                                 sizeof(struct ixgbe_5tuple_filter), 0);
6660                 if (filter == NULL)
6661                         return -ENOMEM;
6662                 rte_memcpy(&filter->filter_info,
6663                                  &filter_5tuple,
6664                                  sizeof(struct ixgbe_5tuple_filter_info));
6665                 filter->queue = ntuple_filter->queue;
6666                 ret = ixgbe_add_5tuple_filter(dev, filter);
6667                 if (ret < 0) {
6668                         rte_free(filter);
6669                         return ret;
6670                 }
6671         } else
6672                 ixgbe_remove_5tuple_filter(dev, filter);
6673
6674         return 0;
6675 }
6676
6677 /*
6678  * get a ntuple filter
6679  *
6680  * @param
6681  * dev: Pointer to struct rte_eth_dev.
6682  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6683  *
6684  * @return
6685  *    - On success, zero.
6686  *    - On failure, a negative value.
6687  */
6688 static int
6689 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6690                         struct rte_eth_ntuple_filter *ntuple_filter)
6691 {
6692         struct ixgbe_filter_info *filter_info =
6693                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6694         struct ixgbe_5tuple_filter_info filter_5tuple;
6695         struct ixgbe_5tuple_filter *filter;
6696         int ret;
6697
6698         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6699                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6700                 return -EINVAL;
6701         }
6702
6703         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6704         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6705         if (ret < 0)
6706                 return ret;
6707
6708         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6709                                          &filter_5tuple);
6710         if (filter == NULL) {
6711                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6712                 return -ENOENT;
6713         }
6714         ntuple_filter->queue = filter->queue;
6715         return 0;
6716 }
6717
6718 /*
6719  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6720  * @dev: pointer to rte_eth_dev structure
6721  * @filter_op:operation will be taken.
6722  * @arg: a pointer to specific structure corresponding to the filter_op
6723  *
6724  * @return
6725  *    - On success, zero.
6726  *    - On failure, a negative value.
6727  */
6728 static int
6729 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6730                                 enum rte_filter_op filter_op,
6731                                 void *arg)
6732 {
6733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6734         int ret;
6735
6736         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6737
6738         if (filter_op == RTE_ETH_FILTER_NOP)
6739                 return 0;
6740
6741         if (arg == NULL) {
6742                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6743                             filter_op);
6744                 return -EINVAL;
6745         }
6746
6747         switch (filter_op) {
6748         case RTE_ETH_FILTER_ADD:
6749                 ret = ixgbe_add_del_ntuple_filter(dev,
6750                         (struct rte_eth_ntuple_filter *)arg,
6751                         TRUE);
6752                 break;
6753         case RTE_ETH_FILTER_DELETE:
6754                 ret = ixgbe_add_del_ntuple_filter(dev,
6755                         (struct rte_eth_ntuple_filter *)arg,
6756                         FALSE);
6757                 break;
6758         case RTE_ETH_FILTER_GET:
6759                 ret = ixgbe_get_ntuple_filter(dev,
6760                         (struct rte_eth_ntuple_filter *)arg);
6761                 break;
6762         default:
6763                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6764                 ret = -EINVAL;
6765                 break;
6766         }
6767         return ret;
6768 }
6769
6770 int
6771 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6772                         struct rte_eth_ethertype_filter *filter,
6773                         bool add)
6774 {
6775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6776         struct ixgbe_filter_info *filter_info =
6777                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6778         uint32_t etqf = 0;
6779         uint32_t etqs = 0;
6780         int ret;
6781         struct ixgbe_ethertype_filter ethertype_filter;
6782
6783         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6784                 return -EINVAL;
6785
6786         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6787                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6788                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6789                         " ethertype filter.", filter->ether_type);
6790                 return -EINVAL;
6791         }
6792
6793         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6794                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6795                 return -EINVAL;
6796         }
6797         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6798                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6799                 return -EINVAL;
6800         }
6801
6802         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6803         if (ret >= 0 && add) {
6804                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6805                             filter->ether_type);
6806                 return -EEXIST;
6807         }
6808         if (ret < 0 && !add) {
6809                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6810                             filter->ether_type);
6811                 return -ENOENT;
6812         }
6813
6814         if (add) {
6815                 etqf = IXGBE_ETQF_FILTER_EN;
6816                 etqf |= (uint32_t)filter->ether_type;
6817                 etqs |= (uint32_t)((filter->queue <<
6818                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6819                                     IXGBE_ETQS_RX_QUEUE);
6820                 etqs |= IXGBE_ETQS_QUEUE_EN;
6821
6822                 ethertype_filter.ethertype = filter->ether_type;
6823                 ethertype_filter.etqf = etqf;
6824                 ethertype_filter.etqs = etqs;
6825                 ethertype_filter.conf = FALSE;
6826                 ret = ixgbe_ethertype_filter_insert(filter_info,
6827                                                     &ethertype_filter);
6828                 if (ret < 0) {
6829                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6830                         return -ENOSPC;
6831                 }
6832         } else {
6833                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6834                 if (ret < 0)
6835                         return -ENOSYS;
6836         }
6837         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6838         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6839         IXGBE_WRITE_FLUSH(hw);
6840
6841         return 0;
6842 }
6843
6844 static int
6845 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6846                         struct rte_eth_ethertype_filter *filter)
6847 {
6848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6849         struct ixgbe_filter_info *filter_info =
6850                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6851         uint32_t etqf, etqs;
6852         int ret;
6853
6854         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6855         if (ret < 0) {
6856                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6857                             filter->ether_type);
6858                 return -ENOENT;
6859         }
6860
6861         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6862         if (etqf & IXGBE_ETQF_FILTER_EN) {
6863                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6864                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6865                 filter->flags = 0;
6866                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6867                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6868                 return 0;
6869         }
6870         return -ENOENT;
6871 }
6872
6873 /*
6874  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6875  * @dev: pointer to rte_eth_dev structure
6876  * @filter_op:operation will be taken.
6877  * @arg: a pointer to specific structure corresponding to the filter_op
6878  */
6879 static int
6880 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6881                                 enum rte_filter_op filter_op,
6882                                 void *arg)
6883 {
6884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6885         int ret;
6886
6887         MAC_TYPE_FILTER_SUP(hw->mac.type);
6888
6889         if (filter_op == RTE_ETH_FILTER_NOP)
6890                 return 0;
6891
6892         if (arg == NULL) {
6893                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6894                             filter_op);
6895                 return -EINVAL;
6896         }
6897
6898         switch (filter_op) {
6899         case RTE_ETH_FILTER_ADD:
6900                 ret = ixgbe_add_del_ethertype_filter(dev,
6901                         (struct rte_eth_ethertype_filter *)arg,
6902                         TRUE);
6903                 break;
6904         case RTE_ETH_FILTER_DELETE:
6905                 ret = ixgbe_add_del_ethertype_filter(dev,
6906                         (struct rte_eth_ethertype_filter *)arg,
6907                         FALSE);
6908                 break;
6909         case RTE_ETH_FILTER_GET:
6910                 ret = ixgbe_get_ethertype_filter(dev,
6911                         (struct rte_eth_ethertype_filter *)arg);
6912                 break;
6913         default:
6914                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6915                 ret = -EINVAL;
6916                 break;
6917         }
6918         return ret;
6919 }
6920
6921 static int
6922 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6923                      enum rte_filter_type filter_type,
6924                      enum rte_filter_op filter_op,
6925                      void *arg)
6926 {
6927         int ret = 0;
6928
6929         switch (filter_type) {
6930         case RTE_ETH_FILTER_NTUPLE:
6931                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6932                 break;
6933         case RTE_ETH_FILTER_ETHERTYPE:
6934                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6935                 break;
6936         case RTE_ETH_FILTER_SYN:
6937                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6938                 break;
6939         case RTE_ETH_FILTER_FDIR:
6940                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6941                 break;
6942         case RTE_ETH_FILTER_L2_TUNNEL:
6943                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6944                 break;
6945         case RTE_ETH_FILTER_GENERIC:
6946                 if (filter_op != RTE_ETH_FILTER_GET)
6947                         return -EINVAL;
6948                 *(const void **)arg = &ixgbe_flow_ops;
6949                 break;
6950         default:
6951                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6952                                                         filter_type);
6953                 ret = -EINVAL;
6954                 break;
6955         }
6956
6957         return ret;
6958 }
6959
6960 static u8 *
6961 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6962                         u8 **mc_addr_ptr, u32 *vmdq)
6963 {
6964         u8 *mc_addr;
6965
6966         *vmdq = 0;
6967         mc_addr = *mc_addr_ptr;
6968         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6969         return mc_addr;
6970 }
6971
6972 static int
6973 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6974                           struct rte_ether_addr *mc_addr_set,
6975                           uint32_t nb_mc_addr)
6976 {
6977         struct ixgbe_hw *hw;
6978         u8 *mc_addr_list;
6979
6980         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981         mc_addr_list = (u8 *)mc_addr_set;
6982         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6983                                          ixgbe_dev_addr_list_itr, TRUE);
6984 }
6985
6986 static uint64_t
6987 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6988 {
6989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6990         uint64_t systime_cycles;
6991
6992         switch (hw->mac.type) {
6993         case ixgbe_mac_X550:
6994         case ixgbe_mac_X550EM_x:
6995         case ixgbe_mac_X550EM_a:
6996                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6997                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6998                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6999                                 * NSEC_PER_SEC;
7000                 break;
7001         default:
7002                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7003                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7004                                 << 32;
7005         }
7006
7007         return systime_cycles;
7008 }
7009
7010 static uint64_t
7011 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7012 {
7013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7014         uint64_t rx_tstamp_cycles;
7015
7016         switch (hw->mac.type) {
7017         case ixgbe_mac_X550:
7018         case ixgbe_mac_X550EM_x:
7019         case ixgbe_mac_X550EM_a:
7020                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7021                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7022                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7023                                 * NSEC_PER_SEC;
7024                 break;
7025         default:
7026                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7027                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7028                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7029                                 << 32;
7030         }
7031
7032         return rx_tstamp_cycles;
7033 }
7034
7035 static uint64_t
7036 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7037 {
7038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7039         uint64_t tx_tstamp_cycles;
7040
7041         switch (hw->mac.type) {
7042         case ixgbe_mac_X550:
7043         case ixgbe_mac_X550EM_x:
7044         case ixgbe_mac_X550EM_a:
7045                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7046                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7047                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7048                                 * NSEC_PER_SEC;
7049                 break;
7050         default:
7051                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7052                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7053                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7054                                 << 32;
7055         }
7056
7057         return tx_tstamp_cycles;
7058 }
7059
7060 static void
7061 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7062 {
7063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7064         struct ixgbe_adapter *adapter = dev->data->dev_private;
7065         struct rte_eth_link link;
7066         uint32_t incval = 0;
7067         uint32_t shift = 0;
7068
7069         /* Get current link speed. */
7070         ixgbe_dev_link_update(dev, 1);
7071         rte_eth_linkstatus_get(dev, &link);
7072
7073         switch (link.link_speed) {
7074         case ETH_SPEED_NUM_100M:
7075                 incval = IXGBE_INCVAL_100;
7076                 shift = IXGBE_INCVAL_SHIFT_100;
7077                 break;
7078         case ETH_SPEED_NUM_1G:
7079                 incval = IXGBE_INCVAL_1GB;
7080                 shift = IXGBE_INCVAL_SHIFT_1GB;
7081                 break;
7082         case ETH_SPEED_NUM_10G:
7083         default:
7084                 incval = IXGBE_INCVAL_10GB;
7085                 shift = IXGBE_INCVAL_SHIFT_10GB;
7086                 break;
7087         }
7088
7089         switch (hw->mac.type) {
7090         case ixgbe_mac_X550:
7091         case ixgbe_mac_X550EM_x:
7092         case ixgbe_mac_X550EM_a:
7093                 /* Independent of link speed. */
7094                 incval = 1;
7095                 /* Cycles read will be interpreted as ns. */
7096                 shift = 0;
7097                 /* Fall-through */
7098         case ixgbe_mac_X540:
7099                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7100                 break;
7101         case ixgbe_mac_82599EB:
7102                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7103                 shift -= IXGBE_INCVAL_SHIFT_82599;
7104                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7105                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7106                 break;
7107         default:
7108                 /* Not supported. */
7109                 return;
7110         }
7111
7112         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7113         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7114         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7115
7116         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7117         adapter->systime_tc.cc_shift = shift;
7118         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7119
7120         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7121         adapter->rx_tstamp_tc.cc_shift = shift;
7122         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7123
7124         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7125         adapter->tx_tstamp_tc.cc_shift = shift;
7126         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7127 }
7128
7129 static int
7130 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7131 {
7132         struct ixgbe_adapter *adapter = dev->data->dev_private;
7133
7134         adapter->systime_tc.nsec += delta;
7135         adapter->rx_tstamp_tc.nsec += delta;
7136         adapter->tx_tstamp_tc.nsec += delta;
7137
7138         return 0;
7139 }
7140
7141 static int
7142 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7143 {
7144         uint64_t ns;
7145         struct ixgbe_adapter *adapter = dev->data->dev_private;
7146
7147         ns = rte_timespec_to_ns(ts);
7148         /* Set the timecounters to a new value. */
7149         adapter->systime_tc.nsec = ns;
7150         adapter->rx_tstamp_tc.nsec = ns;
7151         adapter->tx_tstamp_tc.nsec = ns;
7152
7153         return 0;
7154 }
7155
7156 static int
7157 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7158 {
7159         uint64_t ns, systime_cycles;
7160         struct ixgbe_adapter *adapter = dev->data->dev_private;
7161
7162         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7163         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7164         *ts = rte_ns_to_timespec(ns);
7165
7166         return 0;
7167 }
7168
7169 static int
7170 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7171 {
7172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7173         uint32_t tsync_ctl;
7174         uint32_t tsauxc;
7175
7176         /* Stop the timesync system time. */
7177         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7178         /* Reset the timesync system time value. */
7179         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7180         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7181
7182         /* Enable system time for platforms where it isn't on by default. */
7183         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7184         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7185         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7186
7187         ixgbe_start_timecounters(dev);
7188
7189         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7190         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7191                         (RTE_ETHER_TYPE_1588 |
7192                          IXGBE_ETQF_FILTER_EN |
7193                          IXGBE_ETQF_1588));
7194
7195         /* Enable timestamping of received PTP packets. */
7196         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7197         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7198         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7199
7200         /* Enable timestamping of transmitted PTP packets. */
7201         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7202         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7203         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7204
7205         IXGBE_WRITE_FLUSH(hw);
7206
7207         return 0;
7208 }
7209
7210 static int
7211 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7212 {
7213         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7214         uint32_t tsync_ctl;
7215
7216         /* Disable timestamping of transmitted PTP packets. */
7217         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7218         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7219         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7220
7221         /* Disable timestamping of received PTP packets. */
7222         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7223         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7224         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7225
7226         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7227         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7228
7229         /* Stop incrementating the System Time registers. */
7230         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7231
7232         return 0;
7233 }
7234
7235 static int
7236 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7237                                  struct timespec *timestamp,
7238                                  uint32_t flags __rte_unused)
7239 {
7240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7241         struct ixgbe_adapter *adapter = dev->data->dev_private;
7242         uint32_t tsync_rxctl;
7243         uint64_t rx_tstamp_cycles;
7244         uint64_t ns;
7245
7246         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7247         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7248                 return -EINVAL;
7249
7250         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7251         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7252         *timestamp = rte_ns_to_timespec(ns);
7253
7254         return  0;
7255 }
7256
7257 static int
7258 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7259                                  struct timespec *timestamp)
7260 {
7261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7262         struct ixgbe_adapter *adapter = dev->data->dev_private;
7263         uint32_t tsync_txctl;
7264         uint64_t tx_tstamp_cycles;
7265         uint64_t ns;
7266
7267         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7268         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7269                 return -EINVAL;
7270
7271         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7272         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7273         *timestamp = rte_ns_to_timespec(ns);
7274
7275         return 0;
7276 }
7277
7278 static int
7279 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7280 {
7281         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7282         int count = 0;
7283         int g_ind = 0;
7284         const struct reg_info *reg_group;
7285         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7286                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7287
7288         while ((reg_group = reg_set[g_ind++]))
7289                 count += ixgbe_regs_group_count(reg_group);
7290
7291         return count;
7292 }
7293
7294 static int
7295 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7296 {
7297         int count = 0;
7298         int g_ind = 0;
7299         const struct reg_info *reg_group;
7300
7301         while ((reg_group = ixgbevf_regs[g_ind++]))
7302                 count += ixgbe_regs_group_count(reg_group);
7303
7304         return count;
7305 }
7306
7307 static int
7308 ixgbe_get_regs(struct rte_eth_dev *dev,
7309               struct rte_dev_reg_info *regs)
7310 {
7311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7312         uint32_t *data = regs->data;
7313         int g_ind = 0;
7314         int count = 0;
7315         const struct reg_info *reg_group;
7316         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7317                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7318
7319         if (data == NULL) {
7320                 regs->length = ixgbe_get_reg_length(dev);
7321                 regs->width = sizeof(uint32_t);
7322                 return 0;
7323         }
7324
7325         /* Support only full register dump */
7326         if ((regs->length == 0) ||
7327             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7328                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7329                         hw->device_id;
7330                 while ((reg_group = reg_set[g_ind++]))
7331                         count += ixgbe_read_regs_group(dev, &data[count],
7332                                 reg_group);
7333                 return 0;
7334         }
7335
7336         return -ENOTSUP;
7337 }
7338
7339 static int
7340 ixgbevf_get_regs(struct rte_eth_dev *dev,
7341                 struct rte_dev_reg_info *regs)
7342 {
7343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7344         uint32_t *data = regs->data;
7345         int g_ind = 0;
7346         int count = 0;
7347         const struct reg_info *reg_group;
7348
7349         if (data == NULL) {
7350                 regs->length = ixgbevf_get_reg_length(dev);
7351                 regs->width = sizeof(uint32_t);
7352                 return 0;
7353         }
7354
7355         /* Support only full register dump */
7356         if ((regs->length == 0) ||
7357             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7358                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7359                         hw->device_id;
7360                 while ((reg_group = ixgbevf_regs[g_ind++]))
7361                         count += ixgbe_read_regs_group(dev, &data[count],
7362                                                       reg_group);
7363                 return 0;
7364         }
7365
7366         return -ENOTSUP;
7367 }
7368
7369 static int
7370 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7371 {
7372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7373
7374         /* Return unit is byte count */
7375         return hw->eeprom.word_size * 2;
7376 }
7377
7378 static int
7379 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7380                 struct rte_dev_eeprom_info *in_eeprom)
7381 {
7382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7383         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7384         uint16_t *data = in_eeprom->data;
7385         int first, length;
7386
7387         first = in_eeprom->offset >> 1;
7388         length = in_eeprom->length >> 1;
7389         if ((first > hw->eeprom.word_size) ||
7390             ((first + length) > hw->eeprom.word_size))
7391                 return -EINVAL;
7392
7393         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7394
7395         return eeprom->ops.read_buffer(hw, first, length, data);
7396 }
7397
7398 static int
7399 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7400                 struct rte_dev_eeprom_info *in_eeprom)
7401 {
7402         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7403         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7404         uint16_t *data = in_eeprom->data;
7405         int first, length;
7406
7407         first = in_eeprom->offset >> 1;
7408         length = in_eeprom->length >> 1;
7409         if ((first > hw->eeprom.word_size) ||
7410             ((first + length) > hw->eeprom.word_size))
7411                 return -EINVAL;
7412
7413         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7414
7415         return eeprom->ops.write_buffer(hw,  first, length, data);
7416 }
7417
7418 static int
7419 ixgbe_get_module_info(struct rte_eth_dev *dev,
7420                       struct rte_eth_dev_module_info *modinfo)
7421 {
7422         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7423         uint32_t status;
7424         uint8_t sff8472_rev, addr_mode;
7425         bool page_swap = false;
7426
7427         /* Check whether we support SFF-8472 or not */
7428         status = hw->phy.ops.read_i2c_eeprom(hw,
7429                                              IXGBE_SFF_SFF_8472_COMP,
7430                                              &sff8472_rev);
7431         if (status != 0)
7432                 return -EIO;
7433
7434         /* addressing mode is not supported */
7435         status = hw->phy.ops.read_i2c_eeprom(hw,
7436                                              IXGBE_SFF_SFF_8472_SWAP,
7437                                              &addr_mode);
7438         if (status != 0)
7439                 return -EIO;
7440
7441         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7442                 PMD_DRV_LOG(ERR,
7443                             "Address change required to access page 0xA2, "
7444                             "but not supported. Please report the module "
7445                             "type to the driver maintainers.");
7446                 page_swap = true;
7447         }
7448
7449         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7450                 /* We have a SFP, but it does not support SFF-8472 */
7451                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7452                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7453         } else {
7454                 /* We have a SFP which supports a revision of SFF-8472. */
7455                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7456                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7457         }
7458
7459         return 0;
7460 }
7461
7462 static int
7463 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7464                         struct rte_dev_eeprom_info *info)
7465 {
7466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7467         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7468         uint8_t databyte = 0xFF;
7469         uint8_t *data = info->data;
7470         uint32_t i = 0;
7471
7472         if (info->length == 0)
7473                 return -EINVAL;
7474
7475         for (i = info->offset; i < info->offset + info->length; i++) {
7476                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7477                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7478                 else
7479                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7480
7481                 if (status != 0)
7482                         return -EIO;
7483
7484                 data[i - info->offset] = databyte;
7485         }
7486
7487         return 0;
7488 }
7489
7490 uint16_t
7491 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7492         switch (mac_type) {
7493         case ixgbe_mac_X550:
7494         case ixgbe_mac_X550EM_x:
7495         case ixgbe_mac_X550EM_a:
7496                 return ETH_RSS_RETA_SIZE_512;
7497         case ixgbe_mac_X550_vf:
7498         case ixgbe_mac_X550EM_x_vf:
7499         case ixgbe_mac_X550EM_a_vf:
7500                 return ETH_RSS_RETA_SIZE_64;
7501         case ixgbe_mac_X540_vf:
7502         case ixgbe_mac_82599_vf:
7503                 return 0;
7504         default:
7505                 return ETH_RSS_RETA_SIZE_128;
7506         }
7507 }
7508
7509 uint32_t
7510 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7511         switch (mac_type) {
7512         case ixgbe_mac_X550:
7513         case ixgbe_mac_X550EM_x:
7514         case ixgbe_mac_X550EM_a:
7515                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7516                         return IXGBE_RETA(reta_idx >> 2);
7517                 else
7518                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7519         case ixgbe_mac_X550_vf:
7520         case ixgbe_mac_X550EM_x_vf:
7521         case ixgbe_mac_X550EM_a_vf:
7522                 return IXGBE_VFRETA(reta_idx >> 2);
7523         default:
7524                 return IXGBE_RETA(reta_idx >> 2);
7525         }
7526 }
7527
7528 uint32_t
7529 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7530         switch (mac_type) {
7531         case ixgbe_mac_X550_vf:
7532         case ixgbe_mac_X550EM_x_vf:
7533         case ixgbe_mac_X550EM_a_vf:
7534                 return IXGBE_VFMRQC;
7535         default:
7536                 return IXGBE_MRQC;
7537         }
7538 }
7539
7540 uint32_t
7541 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7542         switch (mac_type) {
7543         case ixgbe_mac_X550_vf:
7544         case ixgbe_mac_X550EM_x_vf:
7545         case ixgbe_mac_X550EM_a_vf:
7546                 return IXGBE_VFRSSRK(i);
7547         default:
7548                 return IXGBE_RSSRK(i);
7549         }
7550 }
7551
7552 bool
7553 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7554         switch (mac_type) {
7555         case ixgbe_mac_82599_vf:
7556         case ixgbe_mac_X540_vf:
7557                 return 0;
7558         default:
7559                 return 1;
7560         }
7561 }
7562
7563 static int
7564 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7565                         struct rte_eth_dcb_info *dcb_info)
7566 {
7567         struct ixgbe_dcb_config *dcb_config =
7568                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7569         struct ixgbe_dcb_tc_config *tc;
7570         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7571         uint8_t nb_tcs;
7572         uint8_t i, j;
7573
7574         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7575                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7576         else
7577                 dcb_info->nb_tcs = 1;
7578
7579         tc_queue = &dcb_info->tc_queue;
7580         nb_tcs = dcb_info->nb_tcs;
7581
7582         if (dcb_config->vt_mode) { /* vt is enabled*/
7583                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7584                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7585                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7586                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7587                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7588                         for (j = 0; j < nb_tcs; j++) {
7589                                 tc_queue->tc_rxq[0][j].base = j;
7590                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7591                                 tc_queue->tc_txq[0][j].base = j;
7592                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7593                         }
7594                 } else {
7595                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7596                                 for (j = 0; j < nb_tcs; j++) {
7597                                         tc_queue->tc_rxq[i][j].base =
7598                                                 i * nb_tcs + j;
7599                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7600                                         tc_queue->tc_txq[i][j].base =
7601                                                 i * nb_tcs + j;
7602                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7603                                 }
7604                         }
7605                 }
7606         } else { /* vt is disabled*/
7607                 struct rte_eth_dcb_rx_conf *rx_conf =
7608                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7609                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7610                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7611                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7612                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7613                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7614                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7615                         }
7616                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7617                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7618                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7619                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7620                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7621                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7622                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7623                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7624                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7625                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7626                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7627                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7628                         }
7629                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7630                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7631                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7632                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7633                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7634                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7635                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7636                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7637                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7638                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7639                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7640                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7641                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7642                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7643                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7644                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7645                 }
7646         }
7647         for (i = 0; i < dcb_info->nb_tcs; i++) {
7648                 tc = &dcb_config->tc_config[i];
7649                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7650         }
7651         return 0;
7652 }
7653
7654 /* Update e-tag ether type */
7655 static int
7656 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7657                             uint16_t ether_type)
7658 {
7659         uint32_t etag_etype;
7660
7661         if (hw->mac.type != ixgbe_mac_X550 &&
7662             hw->mac.type != ixgbe_mac_X550EM_x &&
7663             hw->mac.type != ixgbe_mac_X550EM_a) {
7664                 return -ENOTSUP;
7665         }
7666
7667         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7668         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7669         etag_etype |= ether_type;
7670         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7671         IXGBE_WRITE_FLUSH(hw);
7672
7673         return 0;
7674 }
7675
7676 /* Config l2 tunnel ether type */
7677 static int
7678 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7679                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7680 {
7681         int ret = 0;
7682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7683         struct ixgbe_l2_tn_info *l2_tn_info =
7684                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7685
7686         if (l2_tunnel == NULL)
7687                 return -EINVAL;
7688
7689         switch (l2_tunnel->l2_tunnel_type) {
7690         case RTE_L2_TUNNEL_TYPE_E_TAG:
7691                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7692                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7693                 break;
7694         default:
7695                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7696                 ret = -EINVAL;
7697                 break;
7698         }
7699
7700         return ret;
7701 }
7702
7703 /* Enable e-tag tunnel */
7704 static int
7705 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7706 {
7707         uint32_t etag_etype;
7708
7709         if (hw->mac.type != ixgbe_mac_X550 &&
7710             hw->mac.type != ixgbe_mac_X550EM_x &&
7711             hw->mac.type != ixgbe_mac_X550EM_a) {
7712                 return -ENOTSUP;
7713         }
7714
7715         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7716         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7717         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7718         IXGBE_WRITE_FLUSH(hw);
7719
7720         return 0;
7721 }
7722
7723 /* Enable l2 tunnel */
7724 static int
7725 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7726                            enum rte_eth_tunnel_type l2_tunnel_type)
7727 {
7728         int ret = 0;
7729         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7730         struct ixgbe_l2_tn_info *l2_tn_info =
7731                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7732
7733         switch (l2_tunnel_type) {
7734         case RTE_L2_TUNNEL_TYPE_E_TAG:
7735                 l2_tn_info->e_tag_en = TRUE;
7736                 ret = ixgbe_e_tag_enable(hw);
7737                 break;
7738         default:
7739                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7740                 ret = -EINVAL;
7741                 break;
7742         }
7743
7744         return ret;
7745 }
7746
7747 /* Disable e-tag tunnel */
7748 static int
7749 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7750 {
7751         uint32_t etag_etype;
7752
7753         if (hw->mac.type != ixgbe_mac_X550 &&
7754             hw->mac.type != ixgbe_mac_X550EM_x &&
7755             hw->mac.type != ixgbe_mac_X550EM_a) {
7756                 return -ENOTSUP;
7757         }
7758
7759         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7760         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7761         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7762         IXGBE_WRITE_FLUSH(hw);
7763
7764         return 0;
7765 }
7766
7767 /* Disable l2 tunnel */
7768 static int
7769 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7770                             enum rte_eth_tunnel_type l2_tunnel_type)
7771 {
7772         int ret = 0;
7773         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7774         struct ixgbe_l2_tn_info *l2_tn_info =
7775                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7776
7777         switch (l2_tunnel_type) {
7778         case RTE_L2_TUNNEL_TYPE_E_TAG:
7779                 l2_tn_info->e_tag_en = FALSE;
7780                 ret = ixgbe_e_tag_disable(hw);
7781                 break;
7782         default:
7783                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7784                 ret = -EINVAL;
7785                 break;
7786         }
7787
7788         return ret;
7789 }
7790
7791 static int
7792 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7793                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7794 {
7795         int ret = 0;
7796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7797         uint32_t i, rar_entries;
7798         uint32_t rar_low, rar_high;
7799
7800         if (hw->mac.type != ixgbe_mac_X550 &&
7801             hw->mac.type != ixgbe_mac_X550EM_x &&
7802             hw->mac.type != ixgbe_mac_X550EM_a) {
7803                 return -ENOTSUP;
7804         }
7805
7806         rar_entries = ixgbe_get_num_rx_addrs(hw);
7807
7808         for (i = 1; i < rar_entries; i++) {
7809                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7810                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7811                 if ((rar_high & IXGBE_RAH_AV) &&
7812                     (rar_high & IXGBE_RAH_ADTYPE) &&
7813                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7814                      l2_tunnel->tunnel_id)) {
7815                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7816                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7817
7818                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7819
7820                         return ret;
7821                 }
7822         }
7823
7824         return ret;
7825 }
7826
7827 static int
7828 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7829                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7830 {
7831         int ret = 0;
7832         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7833         uint32_t i, rar_entries;
7834         uint32_t rar_low, rar_high;
7835
7836         if (hw->mac.type != ixgbe_mac_X550 &&
7837             hw->mac.type != ixgbe_mac_X550EM_x &&
7838             hw->mac.type != ixgbe_mac_X550EM_a) {
7839                 return -ENOTSUP;
7840         }
7841
7842         /* One entry for one tunnel. Try to remove potential existing entry. */
7843         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7844
7845         rar_entries = ixgbe_get_num_rx_addrs(hw);
7846
7847         for (i = 1; i < rar_entries; i++) {
7848                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7849                 if (rar_high & IXGBE_RAH_AV) {
7850                         continue;
7851                 } else {
7852                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7853                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7854                         rar_low = l2_tunnel->tunnel_id;
7855
7856                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7857                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7858
7859                         return ret;
7860                 }
7861         }
7862
7863         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7864                      " Please remove a rule before adding a new one.");
7865         return -EINVAL;
7866 }
7867
7868 static inline struct ixgbe_l2_tn_filter *
7869 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7870                           struct ixgbe_l2_tn_key *key)
7871 {
7872         int ret;
7873
7874         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7875         if (ret < 0)
7876                 return NULL;
7877
7878         return l2_tn_info->hash_map[ret];
7879 }
7880
7881 static inline int
7882 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7883                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7884 {
7885         int ret;
7886
7887         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7888                                &l2_tn_filter->key);
7889
7890         if (ret < 0) {
7891                 PMD_DRV_LOG(ERR,
7892                             "Failed to insert L2 tunnel filter"
7893                             " to hash table %d!",
7894                             ret);
7895                 return ret;
7896         }
7897
7898         l2_tn_info->hash_map[ret] = l2_tn_filter;
7899
7900         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7901
7902         return 0;
7903 }
7904
7905 static inline int
7906 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7907                           struct ixgbe_l2_tn_key *key)
7908 {
7909         int ret;
7910         struct ixgbe_l2_tn_filter *l2_tn_filter;
7911
7912         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7913
7914         if (ret < 0) {
7915                 PMD_DRV_LOG(ERR,
7916                             "No such L2 tunnel filter to delete %d!",
7917                             ret);
7918                 return ret;
7919         }
7920
7921         l2_tn_filter = l2_tn_info->hash_map[ret];
7922         l2_tn_info->hash_map[ret] = NULL;
7923
7924         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7925         rte_free(l2_tn_filter);
7926
7927         return 0;
7928 }
7929
7930 /* Add l2 tunnel filter */
7931 int
7932 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7933                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7934                                bool restore)
7935 {
7936         int ret;
7937         struct ixgbe_l2_tn_info *l2_tn_info =
7938                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7939         struct ixgbe_l2_tn_key key;
7940         struct ixgbe_l2_tn_filter *node;
7941
7942         if (!restore) {
7943                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7944                 key.tn_id = l2_tunnel->tunnel_id;
7945
7946                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7947
7948                 if (node) {
7949                         PMD_DRV_LOG(ERR,
7950                                     "The L2 tunnel filter already exists!");
7951                         return -EINVAL;
7952                 }
7953
7954                 node = rte_zmalloc("ixgbe_l2_tn",
7955                                    sizeof(struct ixgbe_l2_tn_filter),
7956                                    0);
7957                 if (!node)
7958                         return -ENOMEM;
7959
7960                 rte_memcpy(&node->key,
7961                                  &key,
7962                                  sizeof(struct ixgbe_l2_tn_key));
7963                 node->pool = l2_tunnel->pool;
7964                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7965                 if (ret < 0) {
7966                         rte_free(node);
7967                         return ret;
7968                 }
7969         }
7970
7971         switch (l2_tunnel->l2_tunnel_type) {
7972         case RTE_L2_TUNNEL_TYPE_E_TAG:
7973                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7974                 break;
7975         default:
7976                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7977                 ret = -EINVAL;
7978                 break;
7979         }
7980
7981         if ((!restore) && (ret < 0))
7982                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7983
7984         return ret;
7985 }
7986
7987 /* Delete l2 tunnel filter */
7988 int
7989 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7990                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7991 {
7992         int ret;
7993         struct ixgbe_l2_tn_info *l2_tn_info =
7994                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7995         struct ixgbe_l2_tn_key key;
7996
7997         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7998         key.tn_id = l2_tunnel->tunnel_id;
7999         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8000         if (ret < 0)
8001                 return ret;
8002
8003         switch (l2_tunnel->l2_tunnel_type) {
8004         case RTE_L2_TUNNEL_TYPE_E_TAG:
8005                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8006                 break;
8007         default:
8008                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8009                 ret = -EINVAL;
8010                 break;
8011         }
8012
8013         return ret;
8014 }
8015
8016 /**
8017  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8018  * @dev: pointer to rte_eth_dev structure
8019  * @filter_op:operation will be taken.
8020  * @arg: a pointer to specific structure corresponding to the filter_op
8021  */
8022 static int
8023 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8024                                   enum rte_filter_op filter_op,
8025                                   void *arg)
8026 {
8027         int ret;
8028
8029         if (filter_op == RTE_ETH_FILTER_NOP)
8030                 return 0;
8031
8032         if (arg == NULL) {
8033                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8034                             filter_op);
8035                 return -EINVAL;
8036         }
8037
8038         switch (filter_op) {
8039         case RTE_ETH_FILTER_ADD:
8040                 ret = ixgbe_dev_l2_tunnel_filter_add
8041                         (dev,
8042                          (struct rte_eth_l2_tunnel_conf *)arg,
8043                          FALSE);
8044                 break;
8045         case RTE_ETH_FILTER_DELETE:
8046                 ret = ixgbe_dev_l2_tunnel_filter_del
8047                         (dev,
8048                          (struct rte_eth_l2_tunnel_conf *)arg);
8049                 break;
8050         default:
8051                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8052                 ret = -EINVAL;
8053                 break;
8054         }
8055         return ret;
8056 }
8057
8058 static int
8059 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8060 {
8061         int ret = 0;
8062         uint32_t ctrl;
8063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8064
8065         if (hw->mac.type != ixgbe_mac_X550 &&
8066             hw->mac.type != ixgbe_mac_X550EM_x &&
8067             hw->mac.type != ixgbe_mac_X550EM_a) {
8068                 return -ENOTSUP;
8069         }
8070
8071         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8072         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8073         if (en)
8074                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8075         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8076
8077         return ret;
8078 }
8079
8080 /* Enable l2 tunnel forwarding */
8081 static int
8082 ixgbe_dev_l2_tunnel_forwarding_enable
8083         (struct rte_eth_dev *dev,
8084          enum rte_eth_tunnel_type l2_tunnel_type)
8085 {
8086         struct ixgbe_l2_tn_info *l2_tn_info =
8087                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8088         int ret = 0;
8089
8090         switch (l2_tunnel_type) {
8091         case RTE_L2_TUNNEL_TYPE_E_TAG:
8092                 l2_tn_info->e_tag_fwd_en = TRUE;
8093                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8094                 break;
8095         default:
8096                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8097                 ret = -EINVAL;
8098                 break;
8099         }
8100
8101         return ret;
8102 }
8103
8104 /* Disable l2 tunnel forwarding */
8105 static int
8106 ixgbe_dev_l2_tunnel_forwarding_disable
8107         (struct rte_eth_dev *dev,
8108          enum rte_eth_tunnel_type l2_tunnel_type)
8109 {
8110         struct ixgbe_l2_tn_info *l2_tn_info =
8111                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8112         int ret = 0;
8113
8114         switch (l2_tunnel_type) {
8115         case RTE_L2_TUNNEL_TYPE_E_TAG:
8116                 l2_tn_info->e_tag_fwd_en = FALSE;
8117                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8118                 break;
8119         default:
8120                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8121                 ret = -EINVAL;
8122                 break;
8123         }
8124
8125         return ret;
8126 }
8127
8128 static int
8129 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8130                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8131                              bool en)
8132 {
8133         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8134         int ret = 0;
8135         uint32_t vmtir, vmvir;
8136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8137
8138         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8139                 PMD_DRV_LOG(ERR,
8140                             "VF id %u should be less than %u",
8141                             l2_tunnel->vf_id,
8142                             pci_dev->max_vfs);
8143                 return -EINVAL;
8144         }
8145
8146         if (hw->mac.type != ixgbe_mac_X550 &&
8147             hw->mac.type != ixgbe_mac_X550EM_x &&
8148             hw->mac.type != ixgbe_mac_X550EM_a) {
8149                 return -ENOTSUP;
8150         }
8151
8152         if (en)
8153                 vmtir = l2_tunnel->tunnel_id;
8154         else
8155                 vmtir = 0;
8156
8157         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8158
8159         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8160         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8161         if (en)
8162                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8163         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8164
8165         return ret;
8166 }
8167
8168 /* Enable l2 tunnel tag insertion */
8169 static int
8170 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8171                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8172 {
8173         int ret = 0;
8174
8175         switch (l2_tunnel->l2_tunnel_type) {
8176         case RTE_L2_TUNNEL_TYPE_E_TAG:
8177                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8178                 break;
8179         default:
8180                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8181                 ret = -EINVAL;
8182                 break;
8183         }
8184
8185         return ret;
8186 }
8187
8188 /* Disable l2 tunnel tag insertion */
8189 static int
8190 ixgbe_dev_l2_tunnel_insertion_disable
8191         (struct rte_eth_dev *dev,
8192          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8193 {
8194         int ret = 0;
8195
8196         switch (l2_tunnel->l2_tunnel_type) {
8197         case RTE_L2_TUNNEL_TYPE_E_TAG:
8198                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8199                 break;
8200         default:
8201                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8202                 ret = -EINVAL;
8203                 break;
8204         }
8205
8206         return ret;
8207 }
8208
8209 static int
8210 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8211                              bool en)
8212 {
8213         int ret = 0;
8214         uint32_t qde;
8215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8216
8217         if (hw->mac.type != ixgbe_mac_X550 &&
8218             hw->mac.type != ixgbe_mac_X550EM_x &&
8219             hw->mac.type != ixgbe_mac_X550EM_a) {
8220                 return -ENOTSUP;
8221         }
8222
8223         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8224         if (en)
8225                 qde |= IXGBE_QDE_STRIP_TAG;
8226         else
8227                 qde &= ~IXGBE_QDE_STRIP_TAG;
8228         qde &= ~IXGBE_QDE_READ;
8229         qde |= IXGBE_QDE_WRITE;
8230         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8231
8232         return ret;
8233 }
8234
8235 /* Enable l2 tunnel tag stripping */
8236 static int
8237 ixgbe_dev_l2_tunnel_stripping_enable
8238         (struct rte_eth_dev *dev,
8239          enum rte_eth_tunnel_type l2_tunnel_type)
8240 {
8241         int ret = 0;
8242
8243         switch (l2_tunnel_type) {
8244         case RTE_L2_TUNNEL_TYPE_E_TAG:
8245                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8246                 break;
8247         default:
8248                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8249                 ret = -EINVAL;
8250                 break;
8251         }
8252
8253         return ret;
8254 }
8255
8256 /* Disable l2 tunnel tag stripping */
8257 static int
8258 ixgbe_dev_l2_tunnel_stripping_disable
8259         (struct rte_eth_dev *dev,
8260          enum rte_eth_tunnel_type l2_tunnel_type)
8261 {
8262         int ret = 0;
8263
8264         switch (l2_tunnel_type) {
8265         case RTE_L2_TUNNEL_TYPE_E_TAG:
8266                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8267                 break;
8268         default:
8269                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8270                 ret = -EINVAL;
8271                 break;
8272         }
8273
8274         return ret;
8275 }
8276
8277 /* Enable/disable l2 tunnel offload functions */
8278 static int
8279 ixgbe_dev_l2_tunnel_offload_set
8280         (struct rte_eth_dev *dev,
8281          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8282          uint32_t mask,
8283          uint8_t en)
8284 {
8285         int ret = 0;
8286
8287         if (l2_tunnel == NULL)
8288                 return -EINVAL;
8289
8290         ret = -EINVAL;
8291         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8292                 if (en)
8293                         ret = ixgbe_dev_l2_tunnel_enable(
8294                                 dev,
8295                                 l2_tunnel->l2_tunnel_type);
8296                 else
8297                         ret = ixgbe_dev_l2_tunnel_disable(
8298                                 dev,
8299                                 l2_tunnel->l2_tunnel_type);
8300         }
8301
8302         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8303                 if (en)
8304                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8305                                 dev,
8306                                 l2_tunnel);
8307                 else
8308                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8309                                 dev,
8310                                 l2_tunnel);
8311         }
8312
8313         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8314                 if (en)
8315                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8316                                 dev,
8317                                 l2_tunnel->l2_tunnel_type);
8318                 else
8319                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8320                                 dev,
8321                                 l2_tunnel->l2_tunnel_type);
8322         }
8323
8324         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8325                 if (en)
8326                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8327                                 dev,
8328                                 l2_tunnel->l2_tunnel_type);
8329                 else
8330                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8331                                 dev,
8332                                 l2_tunnel->l2_tunnel_type);
8333         }
8334
8335         return ret;
8336 }
8337
8338 static int
8339 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8340                         uint16_t port)
8341 {
8342         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8343         IXGBE_WRITE_FLUSH(hw);
8344
8345         return 0;
8346 }
8347
8348 /* There's only one register for VxLAN UDP port.
8349  * So, we cannot add several ports. Will update it.
8350  */
8351 static int
8352 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8353                      uint16_t port)
8354 {
8355         if (port == 0) {
8356                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8357                 return -EINVAL;
8358         }
8359
8360         return ixgbe_update_vxlan_port(hw, port);
8361 }
8362
8363 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8364  * UDP port, it must have a value.
8365  * So, will reset it to the original value 0.
8366  */
8367 static int
8368 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8369                      uint16_t port)
8370 {
8371         uint16_t cur_port;
8372
8373         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8374
8375         if (cur_port != port) {
8376                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8377                 return -EINVAL;
8378         }
8379
8380         return ixgbe_update_vxlan_port(hw, 0);
8381 }
8382
8383 /* Add UDP tunneling port */
8384 static int
8385 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8386                               struct rte_eth_udp_tunnel *udp_tunnel)
8387 {
8388         int ret = 0;
8389         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8390
8391         if (hw->mac.type != ixgbe_mac_X550 &&
8392             hw->mac.type != ixgbe_mac_X550EM_x &&
8393             hw->mac.type != ixgbe_mac_X550EM_a) {
8394                 return -ENOTSUP;
8395         }
8396
8397         if (udp_tunnel == NULL)
8398                 return -EINVAL;
8399
8400         switch (udp_tunnel->prot_type) {
8401         case RTE_TUNNEL_TYPE_VXLAN:
8402                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8403                 break;
8404
8405         case RTE_TUNNEL_TYPE_GENEVE:
8406         case RTE_TUNNEL_TYPE_TEREDO:
8407                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8408                 ret = -EINVAL;
8409                 break;
8410
8411         default:
8412                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8413                 ret = -EINVAL;
8414                 break;
8415         }
8416
8417         return ret;
8418 }
8419
8420 /* Remove UDP tunneling port */
8421 static int
8422 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8423                               struct rte_eth_udp_tunnel *udp_tunnel)
8424 {
8425         int ret = 0;
8426         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8427
8428         if (hw->mac.type != ixgbe_mac_X550 &&
8429             hw->mac.type != ixgbe_mac_X550EM_x &&
8430             hw->mac.type != ixgbe_mac_X550EM_a) {
8431                 return -ENOTSUP;
8432         }
8433
8434         if (udp_tunnel == NULL)
8435                 return -EINVAL;
8436
8437         switch (udp_tunnel->prot_type) {
8438         case RTE_TUNNEL_TYPE_VXLAN:
8439                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8440                 break;
8441         case RTE_TUNNEL_TYPE_GENEVE:
8442         case RTE_TUNNEL_TYPE_TEREDO:
8443                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8444                 ret = -EINVAL;
8445                 break;
8446         default:
8447                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8448                 ret = -EINVAL;
8449                 break;
8450         }
8451
8452         return ret;
8453 }
8454
8455 static int
8456 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8457 {
8458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8459         int ret;
8460
8461         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8462         case IXGBE_SUCCESS:
8463                 ret = 0;
8464                 break;
8465         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8466                 ret = -ENOTSUP;
8467                 break;
8468         default:
8469                 ret = -EAGAIN;
8470                 break;
8471         }
8472
8473         return ret;
8474 }
8475
8476 static int
8477 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8478 {
8479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8480         int ret;
8481
8482         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8483         case IXGBE_SUCCESS:
8484                 ret = 0;
8485                 break;
8486         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8487                 ret = -ENOTSUP;
8488                 break;
8489         default:
8490                 ret = -EAGAIN;
8491                 break;
8492         }
8493
8494         return ret;
8495 }
8496
8497 static int
8498 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8499 {
8500         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8501         int ret;
8502         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8503
8504         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8505         case IXGBE_SUCCESS:
8506                 ret = 0;
8507                 break;
8508         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8509                 ret = -ENOTSUP;
8510                 break;
8511         default:
8512                 ret = -EAGAIN;
8513                 break;
8514         }
8515
8516         return ret;
8517 }
8518
8519 static int
8520 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8521 {
8522         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8523         int ret;
8524
8525         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8526         case IXGBE_SUCCESS:
8527                 ret = 0;
8528                 break;
8529         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8530                 ret = -ENOTSUP;
8531                 break;
8532         default:
8533                 ret = -EAGAIN;
8534                 break;
8535         }
8536
8537         return ret;
8538 }
8539
8540 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8541 {
8542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8543         u32 in_msg = 0;
8544
8545         /* peek the message first */
8546         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8547
8548         /* PF reset VF event */
8549         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8550                 /* dummy mbx read to ack pf */
8551                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8552                         return;
8553                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8554                                               NULL);
8555         }
8556 }
8557
8558 static int
8559 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8560 {
8561         uint32_t eicr;
8562         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8563         struct ixgbe_interrupt *intr =
8564                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8565         ixgbevf_intr_disable(dev);
8566
8567         /* read-on-clear nic registers here */
8568         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8569         intr->flags = 0;
8570
8571         /* only one misc vector supported - mailbox */
8572         eicr &= IXGBE_VTEICR_MASK;
8573         if (eicr == IXGBE_MISC_VEC_ID)
8574                 intr->flags |= IXGBE_FLAG_MAILBOX;
8575
8576         return 0;
8577 }
8578
8579 static int
8580 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8581 {
8582         struct ixgbe_interrupt *intr =
8583                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8584
8585         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8586                 ixgbevf_mbx_process(dev);
8587                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8588         }
8589
8590         ixgbevf_intr_enable(dev);
8591
8592         return 0;
8593 }
8594
8595 static void
8596 ixgbevf_dev_interrupt_handler(void *param)
8597 {
8598         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8599
8600         ixgbevf_dev_interrupt_get_status(dev);
8601         ixgbevf_dev_interrupt_action(dev);
8602 }
8603
8604 /**
8605  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8606  *  @hw: pointer to hardware structure
8607  *
8608  *  Stops the transmit data path and waits for the HW to internally empty
8609  *  the Tx security block
8610  **/
8611 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8612 {
8613 #define IXGBE_MAX_SECTX_POLL 40
8614
8615         int i;
8616         int sectxreg;
8617
8618         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8619         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8620         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8621         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8622                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8623                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8624                         break;
8625                 /* Use interrupt-safe sleep just in case */
8626                 usec_delay(1000);
8627         }
8628
8629         /* For informational purposes only */
8630         if (i >= IXGBE_MAX_SECTX_POLL)
8631                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8632                          "path fully disabled.  Continuing with init.");
8633
8634         return IXGBE_SUCCESS;
8635 }
8636
8637 /**
8638  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8639  *  @hw: pointer to hardware structure
8640  *
8641  *  Enables the transmit data path.
8642  **/
8643 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8644 {
8645         uint32_t sectxreg;
8646
8647         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8648         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8649         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8650         IXGBE_WRITE_FLUSH(hw);
8651
8652         return IXGBE_SUCCESS;
8653 }
8654
8655 /* restore n-tuple filter */
8656 static inline void
8657 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8658 {
8659         struct ixgbe_filter_info *filter_info =
8660                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8661         struct ixgbe_5tuple_filter *node;
8662
8663         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8664                 ixgbe_inject_5tuple_filter(dev, node);
8665         }
8666 }
8667
8668 /* restore ethernet type filter */
8669 static inline void
8670 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8671 {
8672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8673         struct ixgbe_filter_info *filter_info =
8674                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8675         int i;
8676
8677         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8678                 if (filter_info->ethertype_mask & (1 << i)) {
8679                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8680                                         filter_info->ethertype_filters[i].etqf);
8681                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8682                                         filter_info->ethertype_filters[i].etqs);
8683                         IXGBE_WRITE_FLUSH(hw);
8684                 }
8685         }
8686 }
8687
8688 /* restore SYN filter */
8689 static inline void
8690 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8691 {
8692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8693         struct ixgbe_filter_info *filter_info =
8694                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8695         uint32_t synqf;
8696
8697         synqf = filter_info->syn_info;
8698
8699         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8700                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8701                 IXGBE_WRITE_FLUSH(hw);
8702         }
8703 }
8704
8705 /* restore L2 tunnel filter */
8706 static inline void
8707 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8708 {
8709         struct ixgbe_l2_tn_info *l2_tn_info =
8710                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8711         struct ixgbe_l2_tn_filter *node;
8712         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8713
8714         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8715                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8716                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8717                 l2_tn_conf.pool           = node->pool;
8718                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8719         }
8720 }
8721
8722 /* restore rss filter */
8723 static inline void
8724 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8725 {
8726         struct ixgbe_filter_info *filter_info =
8727                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8728
8729         if (filter_info->rss_info.conf.queue_num)
8730                 ixgbe_config_rss_filter(dev,
8731                         &filter_info->rss_info, TRUE);
8732 }
8733
8734 static int
8735 ixgbe_filter_restore(struct rte_eth_dev *dev)
8736 {
8737         ixgbe_ntuple_filter_restore(dev);
8738         ixgbe_ethertype_filter_restore(dev);
8739         ixgbe_syn_filter_restore(dev);
8740         ixgbe_fdir_filter_restore(dev);
8741         ixgbe_l2_tn_filter_restore(dev);
8742         ixgbe_rss_filter_restore(dev);
8743
8744         return 0;
8745 }
8746
8747 static void
8748 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8749 {
8750         struct ixgbe_l2_tn_info *l2_tn_info =
8751                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8753
8754         if (l2_tn_info->e_tag_en)
8755                 (void)ixgbe_e_tag_enable(hw);
8756
8757         if (l2_tn_info->e_tag_fwd_en)
8758                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8759
8760         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8761 }
8762
8763 /* remove all the n-tuple filters */
8764 void
8765 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8766 {
8767         struct ixgbe_filter_info *filter_info =
8768                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8769         struct ixgbe_5tuple_filter *p_5tuple;
8770
8771         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8772                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8773 }
8774
8775 /* remove all the ether type filters */
8776 void
8777 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8778 {
8779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8780         struct ixgbe_filter_info *filter_info =
8781                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8782         int i;
8783
8784         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8785                 if (filter_info->ethertype_mask & (1 << i) &&
8786                     !filter_info->ethertype_filters[i].conf) {
8787                         (void)ixgbe_ethertype_filter_remove(filter_info,
8788                                                             (uint8_t)i);
8789                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8790                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8791                         IXGBE_WRITE_FLUSH(hw);
8792                 }
8793         }
8794 }
8795
8796 /* remove the SYN filter */
8797 void
8798 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8799 {
8800         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8801         struct ixgbe_filter_info *filter_info =
8802                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8803
8804         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8805                 filter_info->syn_info = 0;
8806
8807                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8808                 IXGBE_WRITE_FLUSH(hw);
8809         }
8810 }
8811
8812 /* remove all the L2 tunnel filters */
8813 int
8814 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8815 {
8816         struct ixgbe_l2_tn_info *l2_tn_info =
8817                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8818         struct ixgbe_l2_tn_filter *l2_tn_filter;
8819         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8820         int ret = 0;
8821
8822         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8823                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8824                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8825                 l2_tn_conf.pool           = l2_tn_filter->pool;
8826                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8827                 if (ret < 0)
8828                         return ret;
8829         }
8830
8831         return 0;
8832 }
8833
8834 void
8835 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8836                                 struct ixgbe_macsec_setting *macsec_setting)
8837 {
8838         struct ixgbe_macsec_setting *macsec =
8839                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8840
8841         macsec->encrypt_en = macsec_setting->encrypt_en;
8842         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8843 }
8844
8845 void
8846 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8847 {
8848         struct ixgbe_macsec_setting *macsec =
8849                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8850
8851         macsec->encrypt_en = 0;
8852         macsec->replayprotect_en = 0;
8853 }
8854
8855 void
8856 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8857                                 struct ixgbe_macsec_setting *macsec_setting)
8858 {
8859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8860         uint32_t ctrl;
8861         uint8_t en = macsec_setting->encrypt_en;
8862         uint8_t rp = macsec_setting->replayprotect_en;
8863
8864         /**
8865          * Workaround:
8866          * As no ixgbe_disable_sec_rx_path equivalent is
8867          * implemented for tx in the base code, and we are
8868          * not allowed to modify the base code in DPDK, so
8869          * just call the hand-written one directly for now.
8870          * The hardware support has been checked by
8871          * ixgbe_disable_sec_rx_path().
8872          */
8873         ixgbe_disable_sec_tx_path_generic(hw);
8874
8875         /* Enable Ethernet CRC (required by MACsec offload) */
8876         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8877         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8878         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8879
8880         /* Enable the TX and RX crypto engines */
8881         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8882         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8883         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8884
8885         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8886         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8887         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8888
8889         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8890         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8891         ctrl |= 0x3;
8892         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8893
8894         /* Enable SA lookup */
8895         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8896         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8897         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8898                      IXGBE_LSECTXCTRL_AUTH;
8899         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8900         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8901         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8902         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8903
8904         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8905         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8906         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8907         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8908         if (rp)
8909                 ctrl |= IXGBE_LSECRXCTRL_RP;
8910         else
8911                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8912         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8913
8914         /* Start the data paths */
8915         ixgbe_enable_sec_rx_path(hw);
8916         /**
8917          * Workaround:
8918          * As no ixgbe_enable_sec_rx_path equivalent is
8919          * implemented for tx in the base code, and we are
8920          * not allowed to modify the base code in DPDK, so
8921          * just call the hand-written one directly for now.
8922          */
8923         ixgbe_enable_sec_tx_path_generic(hw);
8924 }
8925
8926 void
8927 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8928 {
8929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8930         uint32_t ctrl;
8931
8932         /**
8933          * Workaround:
8934          * As no ixgbe_disable_sec_rx_path equivalent is
8935          * implemented for tx in the base code, and we are
8936          * not allowed to modify the base code in DPDK, so
8937          * just call the hand-written one directly for now.
8938          * The hardware support has been checked by
8939          * ixgbe_disable_sec_rx_path().
8940          */
8941         ixgbe_disable_sec_tx_path_generic(hw);
8942
8943         /* Disable the TX and RX crypto engines */
8944         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8945         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8946         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8947
8948         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8949         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8950         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8951
8952         /* Disable SA lookup */
8953         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8954         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8955         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8956         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8957
8958         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8959         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8960         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8961         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8962
8963         /* Start the data paths */
8964         ixgbe_enable_sec_rx_path(hw);
8965         /**
8966          * Workaround:
8967          * As no ixgbe_enable_sec_rx_path equivalent is
8968          * implemented for tx in the base code, and we are
8969          * not allowed to modify the base code in DPDK, so
8970          * just call the hand-written one directly for now.
8971          */
8972         ixgbe_enable_sec_tx_path_generic(hw);
8973 }
8974
8975 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8976 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8977 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8978 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8979 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8980 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8981 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8982                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8983
8984 RTE_INIT(ixgbe_init_log)
8985 {
8986         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8987         if (ixgbe_logtype_init >= 0)
8988                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8989         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8990         if (ixgbe_logtype_driver >= 0)
8991                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8992 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8993         ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
8994         if (ixgbe_logtype_rx >= 0)
8995                 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
8996 #endif
8997
8998 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8999         ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9000         if (ixgbe_logtype_tx >= 0)
9001                 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9002 #endif
9003
9004 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9005         ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9006         if (ixgbe_logtype_tx_free >= 0)
9007                 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);
9008 #endif
9009 }