drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 221 static void ixgbe_dev_interrupt_handler(void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 224
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                             uint16_t queue_id);
 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                              uint16_t queue_id);
 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                  uint8_t queue, uint8_t msix_vector);
 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 266 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 267
 268 /* For Eth VMDQ APIs support */
 269 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 270                 ether_addr * mac_addr, uint8_t on);
 271 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 272 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 273                 struct rte_eth_mirror_conf *mirror_conf,
 274                 uint8_t rule_id, uint8_t on);
 275 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 276                 uint8_t rule_id);
 277 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 278                                           uint16_t queue_id);
 279 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 280                                            uint16_t queue_id);
 281 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 282                                uint8_t queue, uint8_t msix_vector);
 283 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 284
 285 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 286                                 struct ether_addr *mac_addr,
 287                                 uint32_t index, uint32_t pool);
 288 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 289 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 290                                              struct ether_addr *mac_addr);
 291 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 292                         struct rte_eth_syn_filter *filter);
 293 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 294                         enum rte_filter_op filter_op,
 295                         void *arg);
 296 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 301                                 enum rte_filter_op filter_op,
 302                                 void *arg);
 303 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 304                         struct rte_eth_ntuple_filter *filter);
 305 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ethertype_filter *filter);
 310 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 311                      enum rte_filter_type filter_type,
 312                      enum rte_filter_op filter_op,
 313                      void *arg);
 314 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 315
 316 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 317                                       struct ether_addr *mc_addr_set,
 318                                       uint32_t nb_mc_addr);
 319 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 320                                    struct rte_eth_dcb_info *dcb_info);
 321
 322 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 324                             struct rte_dev_reg_info *regs);
 325 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 326 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 329                                 struct rte_dev_eeprom_info *eeprom);
 330
 331 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 332                                  struct rte_eth_dev_module_info *modinfo);
 333 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 334                                    struct rte_dev_eeprom_info *info);
 335
 336 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 337 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 338                                 struct rte_dev_reg_info *regs);
 339
 340 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 341 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 342 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp,
 344                                             uint32_t flags);
 345 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 346                                             struct timespec *timestamp);
 347 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 348 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 349                                    struct timespec *timestamp);
 350 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 351                                    const struct timespec *timestamp);
 352 static void ixgbevf_dev_interrupt_handler(void *param);
 353
 354 static int ixgbe_dev_l2_tunnel_eth_type_conf
 355         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 356 static int ixgbe_dev_l2_tunnel_offload_set
 357         (struct rte_eth_dev *dev,
 358          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 359          uint32_t mask,
 360          uint8_t en);
 361 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 362                                              enum rte_filter_op filter_op,
 363                                              void *arg);
 364
 365 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 366                                          struct rte_eth_udp_tunnel *udp_tunnel);
 367 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 370 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 371
 372 /*
 373  * Define VF Stats MACRO for Non "cleared on read" register
 374  */
 375 #define UPDATE_VF_STAT(reg, last, cur)                          \
 376 {                                                               \
 377         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 378         cur += (latest - last) & UINT_MAX;                      \
 379         last = latest;                                          \
 380 }
 381
 382 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 383 {                                                                \
 384         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 385         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 386         u64 latest = ((new_msb << 32) | new_lsb);                \
 387         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 388         last = latest;                                           \
 389 }
 390
 391 #define IXGBE_SET_HWSTRIP(h, q) do {\
 392                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] |= 1 << bit;\
 395         } while (0)
 396
 397 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 398                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 400                 (h)->bitmap[idx] &= ~(1 << bit);\
 401         } while (0)
 402
 403 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 404                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 406                 (r) = (h)->bitmap[idx] >> bit & 1;\
 407         } while (0)
 408
 409 int ixgbe_logtype_init;
 410 int ixgbe_logtype_driver;
 411
 412 /*
 413  * The set of PCI devices this driver supports
 414  */
 415 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 463 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 465 #endif
 466         { .vendor_id = 0, /* sentinel */ },
 467 };
 468
 469 /*
 470  * The set of PCI devices this driver supports (for 82599 VF)
 471  */
 472 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 483         { .vendor_id = 0, /* sentinel */ },
 484 };
 485
 486 static const struct rte_eth_desc_lim rx_desc_lim = {
 487         .nb_max = IXGBE_MAX_RING_DESC,
 488         .nb_min = IXGBE_MIN_RING_DESC,
 489         .nb_align = IXGBE_RXD_ALIGN,
 490 };
 491
 492 static const struct rte_eth_desc_lim tx_desc_lim = {
 493         .nb_max = IXGBE_MAX_RING_DESC,
 494         .nb_min = IXGBE_MIN_RING_DESC,
 495         .nb_align = IXGBE_TXD_ALIGN,
 496         .nb_seg_max = IXGBE_TX_MAX_SEG,
 497         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 498 };
 499
 500 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 501         .dev_configure        = ixgbe_dev_configure,
 502         .dev_start            = ixgbe_dev_start,
 503         .dev_stop             = ixgbe_dev_stop,
 504         .dev_set_link_up    = ixgbe_dev_set_link_up,
 505         .dev_set_link_down  = ixgbe_dev_set_link_down,
 506         .dev_close            = ixgbe_dev_close,
 507         .dev_reset            = ixgbe_dev_reset,
 508         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 509         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 510         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 511         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 512         .link_update          = ixgbe_dev_link_update,
 513         .stats_get            = ixgbe_dev_stats_get,
 514         .xstats_get           = ixgbe_dev_xstats_get,
 515         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 516         .stats_reset          = ixgbe_dev_stats_reset,
 517         .xstats_reset         = ixgbe_dev_xstats_reset,
 518         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 519         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 520         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 521         .fw_version_get       = ixgbe_fw_version_get,
 522         .dev_infos_get        = ixgbe_dev_info_get,
 523         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 524         .mtu_set              = ixgbe_dev_mtu_set,
 525         .vlan_filter_set      = ixgbe_vlan_filter_set,
 526         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 527         .vlan_offload_set     = ixgbe_vlan_offload_set,
 528         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 529         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 530         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 531         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 532         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 533         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 534         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 535         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 536         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 537         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 538         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 539         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 540         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 541         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 542         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 543         .dev_led_on           = ixgbe_dev_led_on,
 544         .dev_led_off          = ixgbe_dev_led_off,
 545         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 546         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 547         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 548         .mac_addr_add         = ixgbe_add_rar,
 549         .mac_addr_remove      = ixgbe_remove_rar,
 550         .mac_addr_set         = ixgbe_set_default_mac_addr,
 551         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 552         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 553         .mirror_rule_set      = ixgbe_mirror_rule_set,
 554         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 555         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 556         .reta_update          = ixgbe_dev_rss_reta_update,
 557         .reta_query           = ixgbe_dev_rss_reta_query,
 558         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 559         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 560         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 561         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 562         .rxq_info_get         = ixgbe_rxq_info_get,
 563         .txq_info_get         = ixgbe_txq_info_get,
 564         .timesync_enable      = ixgbe_timesync_enable,
 565         .timesync_disable     = ixgbe_timesync_disable,
 566         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 567         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 568         .get_reg              = ixgbe_get_regs,
 569         .get_eeprom_length    = ixgbe_get_eeprom_length,
 570         .get_eeprom           = ixgbe_get_eeprom,
 571         .set_eeprom           = ixgbe_set_eeprom,
 572         .get_module_info      = ixgbe_get_module_info,
 573         .get_module_eeprom    = ixgbe_get_module_eeprom,
 574         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 575         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 576         .timesync_read_time   = ixgbe_timesync_read_time,
 577         .timesync_write_time  = ixgbe_timesync_write_time,
 578         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 579         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 580         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 581         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 582         .tm_ops_get           = ixgbe_tm_ops_get,
 583 };
 584
 585 /*
 586  * dev_ops for virtual function, bare necessities for basic vf
 587  * operation have been implemented
 588  */
 589 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 590         .dev_configure        = ixgbevf_dev_configure,
 591         .dev_start            = ixgbevf_dev_start,
 592         .dev_stop             = ixgbevf_dev_stop,
 593         .link_update          = ixgbevf_dev_link_update,
 594         .stats_get            = ixgbevf_dev_stats_get,
 595         .xstats_get           = ixgbevf_dev_xstats_get,
 596         .stats_reset          = ixgbevf_dev_stats_reset,
 597         .xstats_reset         = ixgbevf_dev_stats_reset,
 598         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 599         .dev_close            = ixgbevf_dev_close,
 600         .dev_reset            = ixgbevf_dev_reset,
 601         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 602         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 603         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 604         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 605         .dev_infos_get        = ixgbevf_dev_info_get,
 606         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 607         .mtu_set              = ixgbevf_dev_set_mtu,
 608         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 609         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 610         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 611         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 612         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 613         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 614         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 615         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 616         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 617         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 618         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 619         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 620         .mac_addr_add         = ixgbevf_add_mac_addr,
 621         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 622         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 623         .rxq_info_get         = ixgbe_rxq_info_get,
 624         .txq_info_get         = ixgbe_txq_info_get,
 625         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 626         .get_reg              = ixgbevf_get_regs,
 627         .reta_update          = ixgbe_dev_rss_reta_update,
 628         .reta_query           = ixgbe_dev_rss_reta_query,
 629         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 630         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 631 };
 632
 633 /* store statistics names and its offset in stats structure */
 634 struct rte_ixgbe_xstats_name_off {
 635         char name[RTE_ETH_XSTATS_NAME_SIZE];
 636         unsigned offset;
 637 };
 638
 639 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 640         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 641         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 642         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 643         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 644         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 645         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 646         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 647         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 648         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 649         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 650         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 651         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 652         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 653         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 654         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 655                 prc1023)},
 656         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 657                 prc1522)},
 658         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 659         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 660         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 661         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 662         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 663         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 664         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 665         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 666         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 667         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 668         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 669         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 670         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 671         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 672         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 673         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 674         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 675                 ptc1023)},
 676         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 677                 ptc1522)},
 678         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 679         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 680         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 681         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 682
 683         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 684                 fdirustat_add)},
 685         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 686                 fdirustat_remove)},
 687         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 688                 fdirfstat_fadd)},
 689         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 690                 fdirfstat_fremove)},
 691         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirmatch)},
 693         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 694                 fdirmiss)},
 695
 696         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 697         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 698         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 699                 fclast)},
 700         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 701         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 702         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 703         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 704         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 705                 fcoe_noddp)},
 706         {"rx_fcoe_no_direct_data_placement_ext_buff",
 707                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 708
 709         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxontxc)},
 711         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxonrxc)},
 713         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 714                 lxofftxc)},
 715         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxoffrxc)},
 717         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 718 };
 719
 720 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 721                            sizeof(rte_ixgbe_stats_strings[0]))
 722
 723 /* MACsec statistics */
 724 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 725         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_untagged)},
 727         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_pkts_encrypted)},
 729         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_pkts_protected)},
 731         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 732                 out_octets_encrypted)},
 733         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 734                 out_octets_protected)},
 735         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_untagged)},
 737         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_badtag)},
 739         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_nosci)},
 741         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_unknownsci)},
 743         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 744                 in_octets_decrypted)},
 745         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 746                 in_octets_validated)},
 747         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_unchecked)},
 749         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_delayed)},
 751         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_late)},
 753         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_ok)},
 755         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_invalid)},
 757         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notvalid)},
 759         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_unusedsa)},
 761         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_notusingsa)},
 763 };
 764
 765 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 766                            sizeof(rte_ixgbe_macsec_strings[0]))
 767
 768 /* Per-queue statistics */
 769 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 770         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 771         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 772         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 773         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 774 };
 775
 776 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 777                            sizeof(rte_ixgbe_rxq_strings[0]))
 778 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 779
 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 781         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 782         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 783         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 784                 pxon2offc)},
 785 };
 786
 787 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 788                            sizeof(rte_ixgbe_txq_strings[0]))
 789 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 790
 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 792         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 793 };
 794
 795 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 796                 sizeof(rte_ixgbevf_stats_strings[0]))
 797
 798 /*
 799  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 800  */
 801 static inline int
 802 ixgbe_is_sfp(struct ixgbe_hw *hw)
 803 {
 804         switch (hw->phy.type) {
 805         case ixgbe_phy_sfp_avago:
 806         case ixgbe_phy_sfp_ftl:
 807         case ixgbe_phy_sfp_intel:
 808         case ixgbe_phy_sfp_unknown:
 809         case ixgbe_phy_sfp_passive_tyco:
 810         case ixgbe_phy_sfp_passive_unknown:
 811                 return 1;
 812         default:
 813                 return 0;
 814         }
 815 }
 816
 817 static inline int32_t
 818 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 819 {
 820         uint32_t ctrl_ext;
 821         int32_t status;
 822
 823         status = ixgbe_reset_hw(hw);
 824
 825         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 826         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 827         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 828         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 829         IXGBE_WRITE_FLUSH(hw);
 830
 831         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 832                 status = IXGBE_SUCCESS;
 833         return status;
 834 }
 835
 836 static inline void
 837 ixgbe_enable_intr(struct rte_eth_dev *dev)
 838 {
 839         struct ixgbe_interrupt *intr =
 840                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 841         struct ixgbe_hw *hw =
 842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 843
 844         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 845         IXGBE_WRITE_FLUSH(hw);
 846 }
 847
 848 /*
 849  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 850  */
 851 static void
 852 ixgbe_disable_intr(struct ixgbe_hw *hw)
 853 {
 854         PMD_INIT_FUNC_TRACE();
 855
 856         if (hw->mac.type == ixgbe_mac_82598EB) {
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 858         } else {
 859                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 860                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 862         }
 863         IXGBE_WRITE_FLUSH(hw);
 864 }
 865
 866 /*
 867  * This function resets queue statistics mapping registers.
 868  * From Niantic datasheet, Initialization of Statistics section:
 869  * "...if software requires the queue counters, the RQSMR and TQSM registers
 870  * must be re-programmed following a device reset.
 871  */
 872 static void
 873 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 874 {
 875         uint32_t i;
 876
 877         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 878                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 879                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 880         }
 881 }
 882
 883
 884 static int
 885 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 886                                   uint16_t queue_id,
 887                                   uint8_t stat_idx,
 888                                   uint8_t is_rx)
 889 {
 890 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 891 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 892 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 893
 894         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 895         struct ixgbe_stat_mapping_registers *stat_mappings =
 896                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 897         uint32_t qsmr_mask = 0;
 898         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 899         uint32_t q_map;
 900         uint8_t n, offset;
 901
 902         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 903                 (hw->mac.type != ixgbe_mac_X540) &&
 904                 (hw->mac.type != ixgbe_mac_X550) &&
 905                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 906                 (hw->mac.type != ixgbe_mac_X550EM_a))
 907                 return -ENOSYS;
 908
 909         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 910                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 911                      queue_id, stat_idx);
 912
 913         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 914         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 915                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 916                 return -EIO;
 917         }
 918         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 919
 920         /* Now clear any previous stat_idx set */
 921         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 922         if (!is_rx)
 923                 stat_mappings->tqsm[n] &= ~clearing_mask;
 924         else
 925                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 926
 927         q_map = (uint32_t)stat_idx;
 928         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 929         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 930         if (!is_rx)
 931                 stat_mappings->tqsm[n] |= qsmr_mask;
 932         else
 933                 stat_mappings->rqsmr[n] |= qsmr_mask;
 934
 935         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 936                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 937                      queue_id, stat_idx);
 938         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 939                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 940
 941         /* Now write the mapping in the appropriate register */
 942         if (is_rx) {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 944                              stat_mappings->rqsmr[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 946         } else {
 947                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 948                              stat_mappings->tqsm[n], n);
 949                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 950         }
 951         return 0;
 952 }
 953
 954 static void
 955 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 956 {
 957         struct ixgbe_stat_mapping_registers *stat_mappings =
 958                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 960         int i;
 961
 962         /* write whatever was in stat mapping table to the NIC */
 963         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 964                 /* rx */
 965                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 966
 967                 /* tx */
 968                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 969         }
 970 }
 971
 972 static void
 973 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 974 {
 975         uint8_t i;
 976         struct ixgbe_dcb_tc_config *tc;
 977         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 978
 979         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 980         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 981         for (i = 0; i < dcb_max_tc; i++) {
 982                 tc = &dcb_config->tc_config[i];
 983                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 984                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 985                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 986                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 987                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 988                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 989                 tc->pfc = ixgbe_dcb_pfc_disabled;
 990         }
 991
 992         /* Initialize default user to priority mapping, UPx->TC0 */
 993         tc = &dcb_config->tc_config[0];
 994         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 995         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 996         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 997                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 998                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 999         }
1000         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1001         dcb_config->pfc_mode_enable = false;
1002         dcb_config->vt_mode = true;
1003         dcb_config->round_robin_enable = false;
1004         /* support all DCB capabilities in 82599 */
1005         dcb_config->support.capabilities = 0xFF;
1006
1007         /*we only support 4 Tcs for X540, X550 */
1008         if (hw->mac.type == ixgbe_mac_X540 ||
1009                 hw->mac.type == ixgbe_mac_X550 ||
1010                 hw->mac.type == ixgbe_mac_X550EM_x ||
1011                 hw->mac.type == ixgbe_mac_X550EM_a) {
1012                 dcb_config->num_tcs.pg_tcs = 4;
1013                 dcb_config->num_tcs.pfc_tcs = 4;
1014         }
1015 }
1016
1017 /*
1018  * Ensure that all locks are released before first NVM or PHY access
1019  */
1020 static void
1021 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1022 {
1023         uint16_t mask;
1024
1025         /*
1026          * Phy lock should not fail in this early stage. If this is the case,
1027          * it is due to an improper exit of the application.
1028          * So force the release of the faulty lock. Release of common lock
1029          * is done automatically by swfw_sync function.
1030          */
1031         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1032         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1033                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1034         }
1035         ixgbe_release_swfw_semaphore(hw, mask);
1036
1037         /*
1038          * These ones are more tricky since they are common to all ports; but
1039          * swfw_sync retries last long enough (1s) to be almost sure that if
1040          * lock can not be taken it is due to an improper lock of the
1041          * semaphore.
1042          */
1043         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1044         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1045                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1046         }
1047         ixgbe_release_swfw_semaphore(hw, mask);
1048 }
1049
1050 /*
1051  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1052  * It returns 0 on success.
1053  */
1054 static int
1055 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1056 {
1057         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1058         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1059         struct ixgbe_hw *hw =
1060                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1061         struct ixgbe_vfta *shadow_vfta =
1062                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1063         struct ixgbe_hwstrip *hwstrip =
1064                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1065         struct ixgbe_dcb_config *dcb_config =
1066                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1067         struct ixgbe_filter_info *filter_info =
1068                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1069         struct ixgbe_bw_conf *bw_conf =
1070                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1071         uint32_t ctrl_ext;
1072         uint16_t csum;
1073         int diag, i;
1074
1075         PMD_INIT_FUNC_TRACE();
1076
1077         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1078         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1079         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1080         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1081
1082         /*
1083          * For secondary processes, we don't initialise any further as primary
1084          * has already done this work. Only check we don't need a different
1085          * RX and TX function.
1086          */
1087         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1088                 struct ixgbe_tx_queue *txq;
1089                 /* TX queue function in primary, set by last queue initialized
1090                  * Tx queue may not initialized by primary process
1091                  */
1092                 if (eth_dev->data->tx_queues) {
1093                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1094                         ixgbe_set_tx_function(eth_dev, txq);
1095                 } else {
1096                         /* Use default TX function if we get here */
1097                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1098                                      "Using default TX function.");
1099                 }
1100
1101                 ixgbe_set_rx_function(eth_dev);
1102
1103                 return 0;
1104         }
1105
1106         rte_eth_copy_pci_info(eth_dev, pci_dev);
1107
1108         /* Vendor and Device ID need to be set before init of shared code */
1109         hw->device_id = pci_dev->id.device_id;
1110         hw->vendor_id = pci_dev->id.vendor_id;
1111         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1112         hw->allow_unsupported_sfp = 1;
1113
1114         /* Initialize the shared code (base driver) */
1115 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1116         diag = ixgbe_bypass_init_shared_code(hw);
1117 #else
1118         diag = ixgbe_init_shared_code(hw);
1119 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1120
1121         if (diag != IXGBE_SUCCESS) {
1122                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1123                 return -EIO;
1124         }
1125
1126         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1127                 PMD_INIT_LOG(ERR, "\nERROR: "
1128                         "Firmware recovery mode detected. Limiting functionality.\n"
1129                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1130                         "User Guide for details on firmware recovery mode.");
1131                 return -EIO;
1132         }
1133
1134         /* pick up the PCI bus settings for reporting later */
1135         ixgbe_get_bus_info(hw);
1136
1137         /* Unlock any pending hardware semaphore */
1138         ixgbe_swfw_lock_reset(hw);
1139
1140 #ifdef RTE_LIBRTE_SECURITY
1141         /* Initialize security_ctx only for primary process*/
1142         if (ixgbe_ipsec_ctx_create(eth_dev))
1143                 return -ENOMEM;
1144 #endif
1145
1146         /* Initialize DCB configuration*/
1147         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1148         ixgbe_dcb_init(hw, dcb_config);
1149         /* Get Hardware Flow Control setting */
1150         hw->fc.requested_mode = ixgbe_fc_full;
1151         hw->fc.current_mode = ixgbe_fc_full;
1152         hw->fc.pause_time = IXGBE_FC_PAUSE;
1153         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1154                 hw->fc.low_water[i] = IXGBE_FC_LO;
1155                 hw->fc.high_water[i] = IXGBE_FC_HI;
1156         }
1157         hw->fc.send_xon = 1;
1158
1159         /* Make sure we have a good EEPROM before we read from it */
1160         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1161         if (diag != IXGBE_SUCCESS) {
1162                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1163                 return -EIO;
1164         }
1165
1166 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1167         diag = ixgbe_bypass_init_hw(hw);
1168 #else
1169         diag = ixgbe_init_hw(hw);
1170 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1171
1172         /*
1173          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1174          * is called too soon after the kernel driver unbinding/binding occurs.
1175          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1176          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1177          * also called. See ixgbe_identify_phy_82599(). The reason for the
1178          * failure is not known, and only occuts when virtualisation features
1179          * are disabled in the bios. A delay of 100ms  was found to be enough by
1180          * trial-and-error, and is doubled to be safe.
1181          */
1182         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1183                 rte_delay_ms(200);
1184                 diag = ixgbe_init_hw(hw);
1185         }
1186
1187         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1188                 diag = IXGBE_SUCCESS;
1189
1190         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1191                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1192                              "LOM.  Please be aware there may be issues associated "
1193                              "with your hardware.");
1194                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1195                              "please contact your Intel or hardware representative "
1196                              "who provided you with this hardware.");
1197         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1198                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1199         if (diag) {
1200                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1201                 return -EIO;
1202         }
1203
1204         /* Reset the hw statistics */
1205         ixgbe_dev_stats_reset(eth_dev);
1206
1207         /* disable interrupt */
1208         ixgbe_disable_intr(hw);
1209
1210         /* reset mappings for queue statistics hw counters*/
1211         ixgbe_reset_qstat_mappings(hw);
1212
1213         /* Allocate memory for storing MAC addresses */
1214         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1215                                                hw->mac.num_rar_entries, 0);
1216         if (eth_dev->data->mac_addrs == NULL) {
1217                 PMD_INIT_LOG(ERR,
1218                              "Failed to allocate %u bytes needed to store "
1219                              "MAC addresses",
1220                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1221                 return -ENOMEM;
1222         }
1223         /* Copy the permanent MAC address */
1224         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1225                         &eth_dev->data->mac_addrs[0]);
1226
1227         /* Allocate memory for storing hash filter MAC addresses */
1228         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1229                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1230         if (eth_dev->data->hash_mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %d bytes needed to store MAC addresses",
1233                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1234                 return -ENOMEM;
1235         }
1236
1237         /* initialize the vfta */
1238         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1239
1240         /* initialize the hw strip bitmap*/
1241         memset(hwstrip, 0, sizeof(*hwstrip));
1242
1243         /* initialize PF if max_vfs not zero */
1244         ixgbe_pf_host_init(eth_dev);
1245
1246         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1247         /* let hardware know driver is loaded */
1248         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1249         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1250         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1251         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1252         IXGBE_WRITE_FLUSH(hw);
1253
1254         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1255                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1256                              (int) hw->mac.type, (int) hw->phy.type,
1257                              (int) hw->phy.sfp_type);
1258         else
1259                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1260                              (int) hw->mac.type, (int) hw->phy.type);
1261
1262         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1263                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1264                      pci_dev->id.device_id);
1265
1266         rte_intr_callback_register(intr_handle,
1267                                    ixgbe_dev_interrupt_handler, eth_dev);
1268
1269         /* enable uio/vfio intr/eventfd mapping */
1270         rte_intr_enable(intr_handle);
1271
1272         /* enable support intr */
1273         ixgbe_enable_intr(eth_dev);
1274
1275         /* initialize filter info */
1276         memset(filter_info, 0,
1277                sizeof(struct ixgbe_filter_info));
1278
1279         /* initialize 5tuple filter list */
1280         TAILQ_INIT(&filter_info->fivetuple_list);
1281
1282         /* initialize flow director filter list & hash */
1283         ixgbe_fdir_filter_init(eth_dev);
1284
1285         /* initialize l2 tunnel filter list & hash */
1286         ixgbe_l2_tn_filter_init(eth_dev);
1287
1288         /* initialize flow filter lists */
1289         ixgbe_filterlist_init();
1290
1291         /* initialize bandwidth configuration info */
1292         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1293
1294         /* initialize Traffic Manager configuration */
1295         ixgbe_tm_conf_init(eth_dev);
1296
1297         return 0;
1298 }
1299
1300 static int
1301 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1302 {
1303         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1304         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1305         struct ixgbe_hw *hw;
1306         int retries = 0;
1307         int ret;
1308
1309         PMD_INIT_FUNC_TRACE();
1310
1311         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1312                 return 0;
1313
1314         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1315
1316         if (hw->adapter_stopped == 0)
1317                 ixgbe_dev_close(eth_dev);
1318
1319         eth_dev->dev_ops = NULL;
1320         eth_dev->rx_pkt_burst = NULL;
1321         eth_dev->tx_pkt_burst = NULL;
1322
1323         /* Unlock any pending hardware semaphore */
1324         ixgbe_swfw_lock_reset(hw);
1325
1326         /* disable uio intr before callback unregister */
1327         rte_intr_disable(intr_handle);
1328
1329         do {
1330                 ret = rte_intr_callback_unregister(intr_handle,
1331                                 ixgbe_dev_interrupt_handler, eth_dev);
1332                 if (ret >= 0) {
1333                         break;
1334                 } else if (ret != -EAGAIN) {
1335                         PMD_INIT_LOG(ERR,
1336                                 "intr callback unregister failed: %d",
1337                                 ret);
1338                         return ret;
1339                 }
1340                 rte_delay_ms(100);
1341         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1342
1343         /* cancel the delay handler before remove dev */
1344         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1345
1346         /* uninitialize PF if max_vfs not zero */
1347         ixgbe_pf_host_uninit(eth_dev);
1348
1349         /* remove all the fdir filters & hash */
1350         ixgbe_fdir_filter_uninit(eth_dev);
1351
1352         /* remove all the L2 tunnel filters & hash */
1353         ixgbe_l2_tn_filter_uninit(eth_dev);
1354
1355         /* Remove all ntuple filters of the device */
1356         ixgbe_ntuple_filter_uninit(eth_dev);
1357
1358         /* clear all the filters list */
1359         ixgbe_filterlist_flush();
1360
1361         /* Remove all Traffic Manager configuration */
1362         ixgbe_tm_conf_uninit(eth_dev);
1363
1364 #ifdef RTE_LIBRTE_SECURITY
1365         rte_free(eth_dev->security_ctx);
1366 #endif
1367
1368         return 0;
1369 }
1370
1371 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1372 {
1373         struct ixgbe_filter_info *filter_info =
1374                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1375         struct ixgbe_5tuple_filter *p_5tuple;
1376
1377         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1378                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1379                              p_5tuple,
1380                              entries);
1381                 rte_free(p_5tuple);
1382         }
1383         memset(filter_info->fivetuple_mask, 0,
1384                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1385
1386         return 0;
1387 }
1388
1389 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1390 {
1391         struct ixgbe_hw_fdir_info *fdir_info =
1392                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1393         struct ixgbe_fdir_filter *fdir_filter;
1394
1395                 if (fdir_info->hash_map)
1396                 rte_free(fdir_info->hash_map);
1397         if (fdir_info->hash_handle)
1398                 rte_hash_free(fdir_info->hash_handle);
1399
1400         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1401                 TAILQ_REMOVE(&fdir_info->fdir_list,
1402                              fdir_filter,
1403                              entries);
1404                 rte_free(fdir_filter);
1405         }
1406
1407         return 0;
1408 }
1409
1410 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1411 {
1412         struct ixgbe_l2_tn_info *l2_tn_info =
1413                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1414         struct ixgbe_l2_tn_filter *l2_tn_filter;
1415
1416         if (l2_tn_info->hash_map)
1417                 rte_free(l2_tn_info->hash_map);
1418         if (l2_tn_info->hash_handle)
1419                 rte_hash_free(l2_tn_info->hash_handle);
1420
1421         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1422                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1423                              l2_tn_filter,
1424                              entries);
1425                 rte_free(l2_tn_filter);
1426         }
1427
1428         return 0;
1429 }
1430
1431 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1432 {
1433         struct ixgbe_hw_fdir_info *fdir_info =
1434                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1435         char fdir_hash_name[RTE_HASH_NAMESIZE];
1436         struct rte_hash_parameters fdir_hash_params = {
1437                 .name = fdir_hash_name,
1438                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1439                 .key_len = sizeof(union ixgbe_atr_input),
1440                 .hash_func = rte_hash_crc,
1441                 .hash_func_init_val = 0,
1442                 .socket_id = rte_socket_id(),
1443         };
1444
1445         TAILQ_INIT(&fdir_info->fdir_list);
1446         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1447                  "fdir_%s", eth_dev->device->name);
1448         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1449         if (!fdir_info->hash_handle) {
1450                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1451                 return -EINVAL;
1452         }
1453         fdir_info->hash_map = rte_zmalloc("ixgbe",
1454                                           sizeof(struct ixgbe_fdir_filter *) *
1455                                           IXGBE_MAX_FDIR_FILTER_NUM,
1456                                           0);
1457         if (!fdir_info->hash_map) {
1458                 PMD_INIT_LOG(ERR,
1459                              "Failed to allocate memory for fdir hash map!");
1460                 return -ENOMEM;
1461         }
1462         fdir_info->mask_added = FALSE;
1463
1464         return 0;
1465 }
1466
1467 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1468 {
1469         struct ixgbe_l2_tn_info *l2_tn_info =
1470                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1471         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1472         struct rte_hash_parameters l2_tn_hash_params = {
1473                 .name = l2_tn_hash_name,
1474                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1475                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1476                 .hash_func = rte_hash_crc,
1477                 .hash_func_init_val = 0,
1478                 .socket_id = rte_socket_id(),
1479         };
1480
1481         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1482         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1483                  "l2_tn_%s", eth_dev->device->name);
1484         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1485         if (!l2_tn_info->hash_handle) {
1486                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1487                 return -EINVAL;
1488         }
1489         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1490                                    sizeof(struct ixgbe_l2_tn_filter *) *
1491                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1492                                    0);
1493         if (!l2_tn_info->hash_map) {
1494                 PMD_INIT_LOG(ERR,
1495                         "Failed to allocate memory for L2 TN hash map!");
1496                 return -ENOMEM;
1497         }
1498         l2_tn_info->e_tag_en = FALSE;
1499         l2_tn_info->e_tag_fwd_en = FALSE;
1500         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1501
1502         return 0;
1503 }
1504 /*
1505  * Negotiate mailbox API version with the PF.
1506  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1507  * Then we try to negotiate starting with the most recent one.
1508  * If all negotiation attempts fail, then we will proceed with
1509  * the default one (ixgbe_mbox_api_10).
1510  */
1511 static void
1512 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1513 {
1514         int32_t i;
1515
1516         /* start with highest supported, proceed down */
1517         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1518                 ixgbe_mbox_api_12,
1519                 ixgbe_mbox_api_11,
1520                 ixgbe_mbox_api_10,
1521         };
1522
1523         for (i = 0;
1524                         i != RTE_DIM(sup_ver) &&
1525                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1526                         i++)
1527                 ;
1528 }
1529
1530 static void
1531 generate_random_mac_addr(struct ether_addr *mac_addr)
1532 {
1533         uint64_t random;
1534
1535         /* Set Organizationally Unique Identifier (OUI) prefix. */
1536         mac_addr->addr_bytes[0] = 0x00;
1537         mac_addr->addr_bytes[1] = 0x09;
1538         mac_addr->addr_bytes[2] = 0xC0;
1539         /* Force indication of locally assigned MAC address. */
1540         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1541         /* Generate the last 3 bytes of the MAC address with a random number. */
1542         random = rte_rand();
1543         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1544 }
1545
1546 /*
1547  * Virtual Function device init
1548  */
1549 static int
1550 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1551 {
1552         int diag;
1553         uint32_t tc, tcs;
1554         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1555         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1556         struct ixgbe_hw *hw =
1557                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1558         struct ixgbe_vfta *shadow_vfta =
1559                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1560         struct ixgbe_hwstrip *hwstrip =
1561                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1562         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1563
1564         PMD_INIT_FUNC_TRACE();
1565
1566         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1567         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1568         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1569
1570         /* for secondary processes, we don't initialise any further as primary
1571          * has already done this work. Only check we don't need a different
1572          * RX function
1573          */
1574         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1575                 struct ixgbe_tx_queue *txq;
1576                 /* TX queue function in primary, set by last queue initialized
1577                  * Tx queue may not initialized by primary process
1578                  */
1579                 if (eth_dev->data->tx_queues) {
1580                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1581                         ixgbe_set_tx_function(eth_dev, txq);
1582                 } else {
1583                         /* Use default TX function if we get here */
1584                         PMD_INIT_LOG(NOTICE,
1585                                      "No TX queues configured yet. Using default TX function.");
1586                 }
1587
1588                 ixgbe_set_rx_function(eth_dev);
1589
1590                 return 0;
1591         }
1592
1593         rte_eth_copy_pci_info(eth_dev, pci_dev);
1594
1595         hw->device_id = pci_dev->id.device_id;
1596         hw->vendor_id = pci_dev->id.vendor_id;
1597         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1598
1599         /* initialize the vfta */
1600         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1601
1602         /* initialize the hw strip bitmap*/
1603         memset(hwstrip, 0, sizeof(*hwstrip));
1604
1605         /* Initialize the shared code (base driver) */
1606         diag = ixgbe_init_shared_code(hw);
1607         if (diag != IXGBE_SUCCESS) {
1608                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1609                 return -EIO;
1610         }
1611
1612         /* init_mailbox_params */
1613         hw->mbx.ops.init_params(hw);
1614
1615         /* Reset the hw statistics */
1616         ixgbevf_dev_stats_reset(eth_dev);
1617
1618         /* Disable the interrupts for VF */
1619         ixgbevf_intr_disable(eth_dev);
1620
1621         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1622         diag = hw->mac.ops.reset_hw(hw);
1623
1624         /*
1625          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1626          * the underlying PF driver has not assigned a MAC address to the VF.
1627          * In this case, assign a random MAC address.
1628          */
1629         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1630                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1631                 /*
1632                  * This error code will be propagated to the app by
1633                  * rte_eth_dev_reset, so use a public error code rather than
1634                  * the internal-only IXGBE_ERR_RESET_FAILED
1635                  */
1636                 return -EAGAIN;
1637         }
1638
1639         /* negotiate mailbox API version to use with the PF. */
1640         ixgbevf_negotiate_api(hw);
1641
1642         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1643         ixgbevf_get_queues(hw, &tcs, &tc);
1644
1645         /* Allocate memory for storing MAC addresses */
1646         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1647                                                hw->mac.num_rar_entries, 0);
1648         if (eth_dev->data->mac_addrs == NULL) {
1649                 PMD_INIT_LOG(ERR,
1650                              "Failed to allocate %u bytes needed to store "
1651                              "MAC addresses",
1652                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1653                 return -ENOMEM;
1654         }
1655
1656         /* Generate a random MAC address, if none was assigned by PF. */
1657         if (is_zero_ether_addr(perm_addr)) {
1658                 generate_random_mac_addr(perm_addr);
1659                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1660                 if (diag) {
1661                         rte_free(eth_dev->data->mac_addrs);
1662                         eth_dev->data->mac_addrs = NULL;
1663                         return diag;
1664                 }
1665                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1666                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1667                              "%02x:%02x:%02x:%02x:%02x:%02x",
1668                              perm_addr->addr_bytes[0],
1669                              perm_addr->addr_bytes[1],
1670                              perm_addr->addr_bytes[2],
1671                              perm_addr->addr_bytes[3],
1672                              perm_addr->addr_bytes[4],
1673                              perm_addr->addr_bytes[5]);
1674         }
1675
1676         /* Copy the permanent MAC address */
1677         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1678
1679         /* reset the hardware with the new settings */
1680         diag = hw->mac.ops.start_hw(hw);
1681         switch (diag) {
1682         case  0:
1683                 break;
1684
1685         default:
1686                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1687                 return -EIO;
1688         }
1689
1690         rte_intr_callback_register(intr_handle,
1691                                    ixgbevf_dev_interrupt_handler, eth_dev);
1692         rte_intr_enable(intr_handle);
1693         ixgbevf_intr_enable(eth_dev);
1694
1695         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1696                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1697                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1698
1699         return 0;
1700 }
1701
1702 /* Virtual Function device uninit */
1703
1704 static int
1705 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1706 {
1707         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1708         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1709         struct ixgbe_hw *hw;
1710
1711         PMD_INIT_FUNC_TRACE();
1712
1713         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1714                 return 0;
1715
1716         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1717
1718         if (hw->adapter_stopped == 0)
1719                 ixgbevf_dev_close(eth_dev);
1720
1721         eth_dev->dev_ops = NULL;
1722         eth_dev->rx_pkt_burst = NULL;
1723         eth_dev->tx_pkt_burst = NULL;
1724
1725         /* Disable the interrupts for VF */
1726         ixgbevf_intr_disable(eth_dev);
1727
1728         rte_intr_disable(intr_handle);
1729         rte_intr_callback_unregister(intr_handle,
1730                                      ixgbevf_dev_interrupt_handler, eth_dev);
1731
1732         return 0;
1733 }
1734
1735 static int
1736 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1737                 struct rte_pci_device *pci_dev)
1738 {
1739         char name[RTE_ETH_NAME_MAX_LEN];
1740         struct rte_eth_dev *pf_ethdev;
1741         struct rte_eth_devargs eth_da;
1742         int i, retval;
1743
1744         if (pci_dev->device.devargs) {
1745                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1746                                 &eth_da);
1747                 if (retval)
1748                         return retval;
1749         } else
1750                 memset(&eth_da, 0, sizeof(eth_da));
1751
1752         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1753                 sizeof(struct ixgbe_adapter),
1754                 eth_dev_pci_specific_init, pci_dev,
1755                 eth_ixgbe_dev_init, NULL);
1756
1757         if (retval || eth_da.nb_representor_ports < 1)
1758                 return retval;
1759
1760         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1761         if (pf_ethdev == NULL)
1762                 return -ENODEV;
1763
1764         /* probe VF representor ports */
1765         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1766                 struct ixgbe_vf_info *vfinfo;
1767                 struct ixgbe_vf_representor representor;
1768
1769                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1770                         pf_ethdev->data->dev_private);
1771                 if (vfinfo == NULL) {
1772                         PMD_DRV_LOG(ERR,
1773                                 "no virtual functions supported by PF");
1774                         break;
1775                 }
1776
1777                 representor.vf_id = eth_da.representor_ports[i];
1778                 representor.switch_domain_id = vfinfo->switch_domain_id;
1779                 representor.pf_ethdev = pf_ethdev;
1780
1781                 /* representor port net_bdf_port */
1782                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1783                         pci_dev->device.name,
1784                         eth_da.representor_ports[i]);
1785
1786                 retval = rte_eth_dev_create(&pci_dev->device, name,
1787                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1788                         ixgbe_vf_representor_init, &representor);
1789
1790                 if (retval)
1791                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1792                                 "representor %s.", name);
1793         }
1794
1795         return 0;
1796 }
1797
1798 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1799 {
1800         struct rte_eth_dev *ethdev;
1801
1802         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1803         if (!ethdev)
1804                 return -ENODEV;
1805
1806         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1807                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1808         else
1809                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1810 }
1811
1812 static struct rte_pci_driver rte_ixgbe_pmd = {
1813         .id_table = pci_id_ixgbe_map,
1814         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1815                      RTE_PCI_DRV_IOVA_AS_VA,
1816         .probe = eth_ixgbe_pci_probe,
1817         .remove = eth_ixgbe_pci_remove,
1818 };
1819
1820 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1821         struct rte_pci_device *pci_dev)
1822 {
1823         return rte_eth_dev_pci_generic_probe(pci_dev,
1824                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1825 }
1826
1827 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1828 {
1829         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1830 }
1831
1832 /*
1833  * virtual function driver struct
1834  */
1835 static struct rte_pci_driver rte_ixgbevf_pmd = {
1836         .id_table = pci_id_ixgbevf_map,
1837         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1838         .probe = eth_ixgbevf_pci_probe,
1839         .remove = eth_ixgbevf_pci_remove,
1840 };
1841
1842 static int
1843 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1844 {
1845         struct ixgbe_hw *hw =
1846                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847         struct ixgbe_vfta *shadow_vfta =
1848                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1849         uint32_t vfta;
1850         uint32_t vid_idx;
1851         uint32_t vid_bit;
1852
1853         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1854         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1855         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1856         if (on)
1857                 vfta |= vid_bit;
1858         else
1859                 vfta &= ~vid_bit;
1860         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1861
1862         /* update local VFTA copy */
1863         shadow_vfta->vfta[vid_idx] = vfta;
1864
1865         return 0;
1866 }
1867
1868 static void
1869 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1870 {
1871         if (on)
1872                 ixgbe_vlan_hw_strip_enable(dev, queue);
1873         else
1874                 ixgbe_vlan_hw_strip_disable(dev, queue);
1875 }
1876
1877 static int
1878 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1879                     enum rte_vlan_type vlan_type,
1880                     uint16_t tpid)
1881 {
1882         struct ixgbe_hw *hw =
1883                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884         int ret = 0;
1885         uint32_t reg;
1886         uint32_t qinq;
1887
1888         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1889         qinq &= IXGBE_DMATXCTL_GDV;
1890
1891         switch (vlan_type) {
1892         case ETH_VLAN_TYPE_INNER:
1893                 if (qinq) {
1894                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1895                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1896                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1897                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1898                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1899                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1900                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1901                 } else {
1902                         ret = -ENOTSUP;
1903                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1904                                     " by single VLAN");
1905                 }
1906                 break;
1907         case ETH_VLAN_TYPE_OUTER:
1908                 if (qinq) {
1909                         /* Only the high 16-bits is valid */
1910                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1911                                         IXGBE_EXVET_VET_EXT_SHIFT);
1912                 } else {
1913                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1914                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1915                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1916                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1917                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1918                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1919                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1920                 }
1921
1922                 break;
1923         default:
1924                 ret = -EINVAL;
1925                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1926                 break;
1927         }
1928
1929         return ret;
1930 }
1931
1932 void
1933 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1934 {
1935         struct ixgbe_hw *hw =
1936                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1937         uint32_t vlnctrl;
1938
1939         PMD_INIT_FUNC_TRACE();
1940
1941         /* Filter Table Disable */
1942         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1943         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1944
1945         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1946 }
1947
1948 void
1949 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1950 {
1951         struct ixgbe_hw *hw =
1952                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         struct ixgbe_vfta *shadow_vfta =
1954                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1955         uint32_t vlnctrl;
1956         uint16_t i;
1957
1958         PMD_INIT_FUNC_TRACE();
1959
1960         /* Filter Table Enable */
1961         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1962         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1963         vlnctrl |= IXGBE_VLNCTRL_VFE;
1964
1965         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1966
1967         /* write whatever is in local vfta copy */
1968         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1969                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1970 }
1971
1972 static void
1973 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1974 {
1975         struct ixgbe_hwstrip *hwstrip =
1976                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1977         struct ixgbe_rx_queue *rxq;
1978
1979         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1980                 return;
1981
1982         if (on)
1983                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1984         else
1985                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1986
1987         if (queue >= dev->data->nb_rx_queues)
1988                 return;
1989
1990         rxq = dev->data->rx_queues[queue];
1991
1992         if (on) {
1993                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1994                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1995         } else {
1996                 rxq->vlan_flags = PKT_RX_VLAN;
1997                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1998         }
1999 }
2000
2001 static void
2002 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2003 {
2004         struct ixgbe_hw *hw =
2005                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         uint32_t ctrl;
2007
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (hw->mac.type == ixgbe_mac_82598EB) {
2011                 /* No queue level support */
2012                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2013                 return;
2014         }
2015
2016         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2017         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2018         ctrl &= ~IXGBE_RXDCTL_VME;
2019         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2020
2021         /* record those setting for HW strip per queue */
2022         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2023 }
2024
2025 static void
2026 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2027 {
2028         struct ixgbe_hw *hw =
2029                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         uint32_t ctrl;
2031
2032         PMD_INIT_FUNC_TRACE();
2033
2034         if (hw->mac.type == ixgbe_mac_82598EB) {
2035                 /* No queue level supported */
2036                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2037                 return;
2038         }
2039
2040         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2042         ctrl |= IXGBE_RXDCTL_VME;
2043         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2044
2045         /* record those setting for HW strip per queue */
2046         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2047 }
2048
2049 static void
2050 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2051 {
2052         struct ixgbe_hw *hw =
2053                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         uint32_t ctrl;
2055
2056         PMD_INIT_FUNC_TRACE();
2057
2058         /* DMATXCTRL: Geric Double VLAN Disable */
2059         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2060         ctrl &= ~IXGBE_DMATXCTL_GDV;
2061         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2062
2063         /* CTRL_EXT: Global Double VLAN Disable */
2064         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2065         ctrl &= ~IXGBE_EXTENDED_VLAN;
2066         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2067
2068 }
2069
2070 static void
2071 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2072 {
2073         struct ixgbe_hw *hw =
2074                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2075         uint32_t ctrl;
2076
2077         PMD_INIT_FUNC_TRACE();
2078
2079         /* DMATXCTRL: Geric Double VLAN Enable */
2080         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2081         ctrl |= IXGBE_DMATXCTL_GDV;
2082         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2083
2084         /* CTRL_EXT: Global Double VLAN Enable */
2085         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2086         ctrl |= IXGBE_EXTENDED_VLAN;
2087         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2088
2089         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2090         if (hw->mac.type == ixgbe_mac_X550 ||
2091             hw->mac.type == ixgbe_mac_X550EM_x ||
2092             hw->mac.type == ixgbe_mac_X550EM_a) {
2093                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2094                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2095                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2096         }
2097
2098         /*
2099          * VET EXT field in the EXVET register = 0x8100 by default
2100          * So no need to change. Same to VT field of DMATXCTL register
2101          */
2102 }
2103
2104 void
2105 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2106 {
2107         struct ixgbe_hw *hw =
2108                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2110         uint32_t ctrl;
2111         uint16_t i;
2112         struct ixgbe_rx_queue *rxq;
2113         bool on;
2114
2115         PMD_INIT_FUNC_TRACE();
2116
2117         if (hw->mac.type == ixgbe_mac_82598EB) {
2118                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2119                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2120                         ctrl |= IXGBE_VLNCTRL_VME;
2121                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2122                 } else {
2123                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2124                         ctrl &= ~IXGBE_VLNCTRL_VME;
2125                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2126                 }
2127         } else {
2128                 /*
2129                  * Other 10G NIC, the VLAN strip can be setup
2130                  * per queue in RXDCTL
2131                  */
2132                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2133                         rxq = dev->data->rx_queues[i];
2134                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2135                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2136                                 ctrl |= IXGBE_RXDCTL_VME;
2137                                 on = TRUE;
2138                         } else {
2139                                 ctrl &= ~IXGBE_RXDCTL_VME;
2140                                 on = FALSE;
2141                         }
2142                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2143
2144                         /* record those setting for HW strip per queue */
2145                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2146                 }
2147         }
2148 }
2149
2150 static void
2151 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2152 {
2153         uint16_t i;
2154         struct rte_eth_rxmode *rxmode;
2155         struct ixgbe_rx_queue *rxq;
2156
2157         if (mask & ETH_VLAN_STRIP_MASK) {
2158                 rxmode = &dev->data->dev_conf.rxmode;
2159                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2160                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2161                                 rxq = dev->data->rx_queues[i];
2162                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2163                         }
2164                 else
2165                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2166                                 rxq = dev->data->rx_queues[i];
2167                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2168                         }
2169         }
2170 }
2171
2172 static int
2173 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2174 {
2175         struct rte_eth_rxmode *rxmode;
2176         rxmode = &dev->data->dev_conf.rxmode;
2177
2178         if (mask & ETH_VLAN_STRIP_MASK) {
2179                 ixgbe_vlan_hw_strip_config(dev);
2180         }
2181
2182         if (mask & ETH_VLAN_FILTER_MASK) {
2183                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2184                         ixgbe_vlan_hw_filter_enable(dev);
2185                 else
2186                         ixgbe_vlan_hw_filter_disable(dev);
2187         }
2188
2189         if (mask & ETH_VLAN_EXTEND_MASK) {
2190                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2191                         ixgbe_vlan_hw_extend_enable(dev);
2192                 else
2193                         ixgbe_vlan_hw_extend_disable(dev);
2194         }
2195
2196         return 0;
2197 }
2198
2199 static int
2200 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2201 {
2202         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2203
2204         ixgbe_vlan_offload_config(dev, mask);
2205
2206         return 0;
2207 }
2208
2209 static void
2210 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2211 {
2212         struct ixgbe_hw *hw =
2213                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2214         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2215         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2216
2217         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2218         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2219 }
2220
2221 static int
2222 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2223 {
2224         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2225
2226         switch (nb_rx_q) {
2227         case 1:
2228         case 2:
2229                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2230                 break;
2231         case 4:
2232                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2233                 break;
2234         default:
2235                 return -EINVAL;
2236         }
2237
2238         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2239                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2240         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2241                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2242         return 0;
2243 }
2244
2245 static int
2246 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2247 {
2248         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2249         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2251         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2252
2253         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2254                 /* check multi-queue mode */
2255                 switch (dev_conf->rxmode.mq_mode) {
2256                 case ETH_MQ_RX_VMDQ_DCB:
2257                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2258                         break;
2259                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2260                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2261                         PMD_INIT_LOG(ERR, "SRIOV active,"
2262                                         " unsupported mq_mode rx %d.",
2263                                         dev_conf->rxmode.mq_mode);
2264                         return -EINVAL;
2265                 case ETH_MQ_RX_RSS:
2266                 case ETH_MQ_RX_VMDQ_RSS:
2267                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2268                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2269                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2270                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2271                                                 " invalid queue number"
2272                                                 " for VMDQ RSS, allowed"
2273                                                 " value are 1, 2 or 4.");
2274                                         return -EINVAL;
2275                                 }
2276                         break;
2277                 case ETH_MQ_RX_VMDQ_ONLY:
2278                 case ETH_MQ_RX_NONE:
2279                         /* if nothing mq mode configure, use default scheme */
2280                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2281                         break;
2282                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2283                         /* SRIOV only works in VMDq enable mode */
2284                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2285                                         " wrong mq_mode rx %d.",
2286                                         dev_conf->rxmode.mq_mode);
2287                         return -EINVAL;
2288                 }
2289
2290                 switch (dev_conf->txmode.mq_mode) {
2291                 case ETH_MQ_TX_VMDQ_DCB:
2292                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2293                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2294                         break;
2295                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2296                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2297                         break;
2298                 }
2299
2300                 /* check valid queue number */
2301                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2302                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2303                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2304                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2305                                         " must be less than or equal to %d.",
2306                                         nb_rx_q, nb_tx_q,
2307                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2308                         return -EINVAL;
2309                 }
2310         } else {
2311                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2312                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2313                                           " not supported.");
2314                         return -EINVAL;
2315                 }
2316                 /* check configuration for vmdb+dcb mode */
2317                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2318                         const struct rte_eth_vmdq_dcb_conf *conf;
2319
2320                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2321                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2322                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2323                                 return -EINVAL;
2324                         }
2325                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2326                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2327                                conf->nb_queue_pools == ETH_32_POOLS)) {
2328                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2329                                                 " nb_queue_pools must be %d or %d.",
2330                                                 ETH_16_POOLS, ETH_32_POOLS);
2331                                 return -EINVAL;
2332                         }
2333                 }
2334                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2335                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2336
2337                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2338                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2339                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2340                                 return -EINVAL;
2341                         }
2342                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2343                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2344                                conf->nb_queue_pools == ETH_32_POOLS)) {
2345                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2346                                                 " nb_queue_pools != %d and"
2347                                                 " nb_queue_pools != %d.",
2348                                                 ETH_16_POOLS, ETH_32_POOLS);
2349                                 return -EINVAL;
2350                         }
2351                 }
2352
2353                 /* For DCB mode check our configuration before we go further */
2354                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2355                         const struct rte_eth_dcb_rx_conf *conf;
2356
2357                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2358                         if (!(conf->nb_tcs == ETH_4_TCS ||
2359                                conf->nb_tcs == ETH_8_TCS)) {
2360                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2361                                                 " and nb_tcs != %d.",
2362                                                 ETH_4_TCS, ETH_8_TCS);
2363                                 return -EINVAL;
2364                         }
2365                 }
2366
2367                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2368                         const struct rte_eth_dcb_tx_conf *conf;
2369
2370                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2371                         if (!(conf->nb_tcs == ETH_4_TCS ||
2372                                conf->nb_tcs == ETH_8_TCS)) {
2373                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2374                                                 " and nb_tcs != %d.",
2375                                                 ETH_4_TCS, ETH_8_TCS);
2376                                 return -EINVAL;
2377                         }
2378                 }
2379
2380                 /*
2381                  * When DCB/VT is off, maximum number of queues changes,
2382                  * except for 82598EB, which remains constant.
2383                  */
2384                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2385                                 hw->mac.type != ixgbe_mac_82598EB) {
2386                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2387                                 PMD_INIT_LOG(ERR,
2388                                              "Neither VT nor DCB are enabled, "
2389                                              "nb_tx_q > %d.",
2390                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2391                                 return -EINVAL;
2392                         }
2393                 }
2394         }
2395         return 0;
2396 }
2397
2398 static int
2399 ixgbe_dev_configure(struct rte_eth_dev *dev)
2400 {
2401         struct ixgbe_interrupt *intr =
2402                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2403         struct ixgbe_adapter *adapter =
2404                 (struct ixgbe_adapter *)dev->data->dev_private;
2405         int ret;
2406
2407         PMD_INIT_FUNC_TRACE();
2408         /* multipe queue mode checking */
2409         ret  = ixgbe_check_mq_mode(dev);
2410         if (ret != 0) {
2411                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2412                             ret);
2413                 return ret;
2414         }
2415
2416         /* set flag to update link status after init */
2417         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2418
2419         /*
2420          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2421          * allocation or vector Rx preconditions we will reset it.
2422          */
2423         adapter->rx_bulk_alloc_allowed = true;
2424         adapter->rx_vec_allowed = true;
2425
2426         return 0;
2427 }
2428
2429 static void
2430 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2431 {
2432         struct ixgbe_hw *hw =
2433                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434         struct ixgbe_interrupt *intr =
2435                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2436         uint32_t gpie;
2437
2438         /* only set up it on X550EM_X */
2439         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2440                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2441                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2442                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2443                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2444                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2445         }
2446 }
2447
2448 int
2449 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2450                         uint16_t tx_rate, uint64_t q_msk)
2451 {
2452         struct ixgbe_hw *hw;
2453         struct ixgbe_vf_info *vfinfo;
2454         struct rte_eth_link link;
2455         uint8_t  nb_q_per_pool;
2456         uint32_t queue_stride;
2457         uint32_t queue_idx, idx = 0, vf_idx;
2458         uint32_t queue_end;
2459         uint16_t total_rate = 0;
2460         struct rte_pci_device *pci_dev;
2461
2462         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2463         rte_eth_link_get_nowait(dev->data->port_id, &link);
2464
2465         if (vf >= pci_dev->max_vfs)
2466                 return -EINVAL;
2467
2468         if (tx_rate > link.link_speed)
2469                 return -EINVAL;
2470
2471         if (q_msk == 0)
2472                 return 0;
2473
2474         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2475         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2476         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2477         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2478         queue_idx = vf * queue_stride;
2479         queue_end = queue_idx + nb_q_per_pool - 1;
2480         if (queue_end >= hw->mac.max_tx_queues)
2481                 return -EINVAL;
2482
2483         if (vfinfo) {
2484                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2485                         if (vf_idx == vf)
2486                                 continue;
2487                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2488                                 idx++)
2489                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2490                 }
2491         } else {
2492                 return -EINVAL;
2493         }
2494
2495         /* Store tx_rate for this vf. */
2496         for (idx = 0; idx < nb_q_per_pool; idx++) {
2497                 if (((uint64_t)0x1 << idx) & q_msk) {
2498                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2499                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2500                         total_rate += tx_rate;
2501                 }
2502         }
2503
2504         if (total_rate > dev->data->dev_link.link_speed) {
2505                 /* Reset stored TX rate of the VF if it causes exceed
2506                  * link speed.
2507                  */
2508                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2509                 return -EINVAL;
2510         }
2511
2512         /* Set RTTBCNRC of each queue/pool for vf X  */
2513         for (; queue_idx <= queue_end; queue_idx++) {
2514                 if (0x1 & q_msk)
2515                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2516                 q_msk = q_msk >> 1;
2517         }
2518
2519         return 0;
2520 }
2521
2522 /*
2523  * Configure device link speed and setup link.
2524  * It returns 0 on success.
2525  */
2526 static int
2527 ixgbe_dev_start(struct rte_eth_dev *dev)
2528 {
2529         struct ixgbe_hw *hw =
2530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         struct ixgbe_vf_info *vfinfo =
2532                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2533         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2534         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2535         uint32_t intr_vector = 0;
2536         int err, link_up = 0, negotiate = 0;
2537         uint32_t speed = 0;
2538         uint32_t allowed_speeds = 0;
2539         int mask = 0;
2540         int status;
2541         uint16_t vf, idx;
2542         uint32_t *link_speeds;
2543         struct ixgbe_tm_conf *tm_conf =
2544                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2545
2546         PMD_INIT_FUNC_TRACE();
2547
2548         /* IXGBE devices don't support:
2549         *    - half duplex (checked afterwards for valid speeds)
2550         *    - fixed speed: TODO implement
2551         */
2552         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2553                 PMD_INIT_LOG(ERR,
2554                 "Invalid link_speeds for port %u, fix speed not supported",
2555                                 dev->data->port_id);
2556                 return -EINVAL;
2557         }
2558
2559         /* Stop the link setup handler before resetting the HW. */
2560         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2561
2562         /* disable uio/vfio intr/eventfd mapping */
2563         rte_intr_disable(intr_handle);
2564
2565         /* stop adapter */
2566         hw->adapter_stopped = 0;
2567         ixgbe_stop_adapter(hw);
2568
2569         /* reinitialize adapter
2570          * this calls reset and start
2571          */
2572         status = ixgbe_pf_reset_hw(hw);
2573         if (status != 0)
2574                 return -1;
2575         hw->mac.ops.start_hw(hw);
2576         hw->mac.get_link_status = true;
2577
2578         /* configure PF module if SRIOV enabled */
2579         ixgbe_pf_host_configure(dev);
2580
2581         ixgbe_dev_phy_intr_setup(dev);
2582
2583         /* check and configure queue intr-vector mapping */
2584         if ((rte_intr_cap_multiple(intr_handle) ||
2585              !RTE_ETH_DEV_SRIOV(dev).active) &&
2586             dev->data->dev_conf.intr_conf.rxq != 0) {
2587                 intr_vector = dev->data->nb_rx_queues;
2588                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2589                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2590                                         IXGBE_MAX_INTR_QUEUE_NUM);
2591                         return -ENOTSUP;
2592                 }
2593                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2594                         return -1;
2595         }
2596
2597         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2598                 intr_handle->intr_vec =
2599                         rte_zmalloc("intr_vec",
2600                                     dev->data->nb_rx_queues * sizeof(int), 0);
2601                 if (intr_handle->intr_vec == NULL) {
2602                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2603                                      " intr_vec", dev->data->nb_rx_queues);
2604                         return -ENOMEM;
2605                 }
2606         }
2607
2608         /* confiugre msix for sleep until rx interrupt */
2609         ixgbe_configure_msix(dev);
2610
2611         /* initialize transmission unit */
2612         ixgbe_dev_tx_init(dev);
2613
2614         /* This can fail when allocating mbufs for descriptor rings */
2615         err = ixgbe_dev_rx_init(dev);
2616         if (err) {
2617                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2618                 goto error;
2619         }
2620
2621         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2622                 ETH_VLAN_EXTEND_MASK;
2623         err = ixgbe_vlan_offload_config(dev, mask);
2624         if (err) {
2625                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2626                 goto error;
2627         }
2628
2629         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2630                 /* Enable vlan filtering for VMDq */
2631                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2632         }
2633
2634         /* Configure DCB hw */
2635         ixgbe_configure_dcb(dev);
2636
2637         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2638                 err = ixgbe_fdir_configure(dev);
2639                 if (err)
2640                         goto error;
2641         }
2642
2643         /* Restore vf rate limit */
2644         if (vfinfo != NULL) {
2645                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2646                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2647                                 if (vfinfo[vf].tx_rate[idx] != 0)
2648                                         ixgbe_set_vf_rate_limit(
2649                                                 dev, vf,
2650                                                 vfinfo[vf].tx_rate[idx],
2651                                                 1 << idx);
2652         }
2653
2654         ixgbe_restore_statistics_mapping(dev);
2655
2656         err = ixgbe_dev_rxtx_start(dev);
2657         if (err < 0) {
2658                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2659                 goto error;
2660         }
2661
2662         /* Skip link setup if loopback mode is enabled. */
2663         if (dev->data->dev_conf.lpbk_mode != 0) {
2664                 err = ixgbe_check_supported_loopback_mode(dev);
2665                 if (err < 0) {
2666                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2667                         goto error;
2668                 } else {
2669                         goto skip_link_setup;
2670                 }
2671         }
2672
2673         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2674                 err = hw->mac.ops.setup_sfp(hw);
2675                 if (err)
2676                         goto error;
2677         }
2678
2679         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2680                 /* Turn on the copper */
2681                 ixgbe_set_phy_power(hw, true);
2682         } else {
2683                 /* Turn on the laser */
2684                 ixgbe_enable_tx_laser(hw);
2685         }
2686
2687         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2688         if (err)
2689                 goto error;
2690         dev->data->dev_link.link_status = link_up;
2691
2692         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2693         if (err)
2694                 goto error;
2695
2696         switch (hw->mac.type) {
2697         case ixgbe_mac_X550:
2698         case ixgbe_mac_X550EM_x:
2699         case ixgbe_mac_X550EM_a:
2700                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2701                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2702                         ETH_LINK_SPEED_10G;
2703                 break;
2704         default:
2705                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2706                         ETH_LINK_SPEED_10G;
2707         }
2708
2709         link_speeds = &dev->data->dev_conf.link_speeds;
2710         if (*link_speeds & ~allowed_speeds) {
2711                 PMD_INIT_LOG(ERR, "Invalid link setting");
2712                 goto error;
2713         }
2714
2715         speed = 0x0;
2716         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2717                 switch (hw->mac.type) {
2718                 case ixgbe_mac_82598EB:
2719                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2720                         break;
2721                 case ixgbe_mac_82599EB:
2722                 case ixgbe_mac_X540:
2723                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2724                         break;
2725                 case ixgbe_mac_X550:
2726                 case ixgbe_mac_X550EM_x:
2727                 case ixgbe_mac_X550EM_a:
2728                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2729                         break;
2730                 default:
2731                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2732                 }
2733         } else {
2734                 if (*link_speeds & ETH_LINK_SPEED_10G)
2735                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2736                 if (*link_speeds & ETH_LINK_SPEED_5G)
2737                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2738                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2739                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2740                 if (*link_speeds & ETH_LINK_SPEED_1G)
2741                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2742                 if (*link_speeds & ETH_LINK_SPEED_100M)
2743                         speed |= IXGBE_LINK_SPEED_100_FULL;
2744         }
2745
2746         err = ixgbe_setup_link(hw, speed, link_up);
2747         if (err)
2748                 goto error;
2749
2750 skip_link_setup:
2751
2752         if (rte_intr_allow_others(intr_handle)) {
2753                 /* check if lsc interrupt is enabled */
2754                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2755                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2756                 else
2757                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2758                 ixgbe_dev_macsec_interrupt_setup(dev);
2759         } else {
2760                 rte_intr_callback_unregister(intr_handle,
2761                                              ixgbe_dev_interrupt_handler, dev);
2762                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2763                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2764                                      " no intr multiplex");
2765         }
2766
2767         /* check if rxq interrupt is enabled */
2768         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2769             rte_intr_dp_is_en(intr_handle))
2770                 ixgbe_dev_rxq_interrupt_setup(dev);
2771
2772         /* enable uio/vfio intr/eventfd mapping */
2773         rte_intr_enable(intr_handle);
2774
2775         /* resume enabled intr since hw reset */
2776         ixgbe_enable_intr(dev);
2777         ixgbe_l2_tunnel_conf(dev);
2778         ixgbe_filter_restore(dev);
2779
2780         if (tm_conf->root && !tm_conf->committed)
2781                 PMD_DRV_LOG(WARNING,
2782                             "please call hierarchy_commit() "
2783                             "before starting the port");
2784
2785         /*
2786          * Update link status right before return, because it may
2787          * start link configuration process in a separate thread.
2788          */
2789         ixgbe_dev_link_update(dev, 0);
2790
2791         return 0;
2792
2793 error:
2794         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2795         ixgbe_dev_clear_queues(dev);
2796         return -EIO;
2797 }
2798
2799 /*
2800  * Stop device: disable rx and tx functions to allow for reconfiguring.
2801  */
2802 static void
2803 ixgbe_dev_stop(struct rte_eth_dev *dev)
2804 {
2805         struct rte_eth_link link;
2806         struct ixgbe_adapter *adapter =
2807                 (struct ixgbe_adapter *)dev->data->dev_private;
2808         struct ixgbe_hw *hw =
2809                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810         struct ixgbe_vf_info *vfinfo =
2811                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2812         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2813         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2814         int vf;
2815         struct ixgbe_tm_conf *tm_conf =
2816                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2817
2818         PMD_INIT_FUNC_TRACE();
2819
2820         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2821
2822         /* disable interrupts */
2823         ixgbe_disable_intr(hw);
2824
2825         /* reset the NIC */
2826         ixgbe_pf_reset_hw(hw);
2827         hw->adapter_stopped = 0;
2828
2829         /* stop adapter */
2830         ixgbe_stop_adapter(hw);
2831
2832         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2833                 vfinfo[vf].clear_to_send = false;
2834
2835         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2836                 /* Turn off the copper */
2837                 ixgbe_set_phy_power(hw, false);
2838         } else {
2839                 /* Turn off the laser */
2840                 ixgbe_disable_tx_laser(hw);
2841         }
2842
2843         ixgbe_dev_clear_queues(dev);
2844
2845         /* Clear stored conf */
2846         dev->data->scattered_rx = 0;
2847         dev->data->lro = 0;
2848
2849         /* Clear recorded link status */
2850         memset(&link, 0, sizeof(link));
2851         rte_eth_linkstatus_set(dev, &link);
2852
2853         if (!rte_intr_allow_others(intr_handle))
2854                 /* resume to the default handler */
2855                 rte_intr_callback_register(intr_handle,
2856                                            ixgbe_dev_interrupt_handler,
2857                                            (void *)dev);
2858
2859         /* Clean datapath event and queue/vec mapping */
2860         rte_intr_efd_disable(intr_handle);
2861         if (intr_handle->intr_vec != NULL) {
2862                 rte_free(intr_handle->intr_vec);
2863                 intr_handle->intr_vec = NULL;
2864         }
2865
2866         /* reset hierarchy commit */
2867         tm_conf->committed = false;
2868
2869         adapter->rss_reta_updated = 0;
2870 }
2871
2872 /*
2873  * Set device link up: enable tx.
2874  */
2875 static int
2876 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2877 {
2878         struct ixgbe_hw *hw =
2879                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2880         if (hw->mac.type == ixgbe_mac_82599EB) {
2881 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2882                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2883                         /* Not suported in bypass mode */
2884                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2885                                      "by device id 0x%x", hw->device_id);
2886                         return -ENOTSUP;
2887                 }
2888 #endif
2889         }
2890
2891         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2892                 /* Turn on the copper */
2893                 ixgbe_set_phy_power(hw, true);
2894         } else {
2895                 /* Turn on the laser */
2896                 ixgbe_enable_tx_laser(hw);
2897         }
2898
2899         return 0;
2900 }
2901
2902 /*
2903  * Set device link down: disable tx.
2904  */
2905 static int
2906 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2907 {
2908         struct ixgbe_hw *hw =
2909                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910         if (hw->mac.type == ixgbe_mac_82599EB) {
2911 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2912                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2913                         /* Not suported in bypass mode */
2914                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2915                                      "by device id 0x%x", hw->device_id);
2916                         return -ENOTSUP;
2917                 }
2918 #endif
2919         }
2920
2921         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2922                 /* Turn off the copper */
2923                 ixgbe_set_phy_power(hw, false);
2924         } else {
2925                 /* Turn off the laser */
2926                 ixgbe_disable_tx_laser(hw);
2927         }
2928
2929         return 0;
2930 }
2931
2932 /*
2933  * Reset and stop device.
2934  */
2935 static void
2936 ixgbe_dev_close(struct rte_eth_dev *dev)
2937 {
2938         struct ixgbe_hw *hw =
2939                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2940
2941         PMD_INIT_FUNC_TRACE();
2942
2943         ixgbe_pf_reset_hw(hw);
2944
2945         ixgbe_dev_stop(dev);
2946         hw->adapter_stopped = 1;
2947
2948         ixgbe_dev_free_queues(dev);
2949
2950         ixgbe_disable_pcie_master(hw);
2951
2952         /* reprogram the RAR[0] in case user changed it. */
2953         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2954 }
2955
2956 /*
2957  * Reset PF device.
2958  */
2959 static int
2960 ixgbe_dev_reset(struct rte_eth_dev *dev)
2961 {
2962         int ret;
2963
2964         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2965          * its VF to make them align with it. The detailed notification
2966          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2967          * To avoid unexpected behavior in VF, currently reset of PF with
2968          * SR-IOV activation is not supported. It might be supported later.
2969          */
2970         if (dev->data->sriov.active)
2971                 return -ENOTSUP;
2972
2973         ret = eth_ixgbe_dev_uninit(dev);
2974         if (ret)
2975                 return ret;
2976
2977         ret = eth_ixgbe_dev_init(dev, NULL);
2978
2979         return ret;
2980 }
2981
2982 static void
2983 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2984                            struct ixgbe_hw_stats *hw_stats,
2985                            struct ixgbe_macsec_stats *macsec_stats,
2986                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2987                            uint64_t *total_qprc, uint64_t *total_qprdc)
2988 {
2989         uint32_t bprc, lxon, lxoff, total;
2990         uint32_t delta_gprc = 0;
2991         unsigned i;
2992         /* Workaround for RX byte count not including CRC bytes when CRC
2993          * strip is enabled. CRC bytes are removed from counters when crc_strip
2994          * is disabled.
2995          */
2996         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2997                         IXGBE_HLREG0_RXCRCSTRP);
2998
2999         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3000         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3001         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3002         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3003
3004         for (i = 0; i < 8; i++) {
3005                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3006
3007                 /* global total per queue */
3008                 hw_stats->mpc[i] += mp;
3009                 /* Running comprehensive total for stats display */
3010                 *total_missed_rx += hw_stats->mpc[i];
3011                 if (hw->mac.type == ixgbe_mac_82598EB) {
3012                         hw_stats->rnbc[i] +=
3013                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3014                         hw_stats->pxonrxc[i] +=
3015                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3016                         hw_stats->pxoffrxc[i] +=
3017                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3018                 } else {
3019                         hw_stats->pxonrxc[i] +=
3020                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3021                         hw_stats->pxoffrxc[i] +=
3022                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3023                         hw_stats->pxon2offc[i] +=
3024                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3025                 }
3026                 hw_stats->pxontxc[i] +=
3027                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3028                 hw_stats->pxofftxc[i] +=
3029                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3030         }
3031         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3032                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3033                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3034                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3035
3036                 delta_gprc += delta_qprc;
3037
3038                 hw_stats->qprc[i] += delta_qprc;
3039                 hw_stats->qptc[i] += delta_qptc;
3040
3041                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3042                 hw_stats->qbrc[i] +=
3043                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3044                 if (crc_strip == 0)
3045                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3046
3047                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3048                 hw_stats->qbtc[i] +=
3049                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3050
3051                 hw_stats->qprdc[i] += delta_qprdc;
3052                 *total_qprdc += hw_stats->qprdc[i];
3053
3054                 *total_qprc += hw_stats->qprc[i];
3055                 *total_qbrc += hw_stats->qbrc[i];
3056         }
3057         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3058         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3059         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3060
3061         /*
3062          * An errata states that gprc actually counts good + missed packets:
3063          * Workaround to set gprc to summated queue packet receives
3064          */
3065         hw_stats->gprc = *total_qprc;
3066
3067         if (hw->mac.type != ixgbe_mac_82598EB) {
3068                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3069                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3070                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3071                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3072                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3073                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3074                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3075                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3076         } else {
3077                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3078                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3079                 /* 82598 only has a counter in the high register */
3080                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3081                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3082                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3083         }
3084         uint64_t old_tpr = hw_stats->tpr;
3085
3086         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3087         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3088
3089         if (crc_strip == 0)
3090                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3091
3092         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3093         hw_stats->gptc += delta_gptc;
3094         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3095         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3096
3097         /*
3098          * Workaround: mprc hardware is incorrectly counting
3099          * broadcasts, so for now we subtract those.
3100          */
3101         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3102         hw_stats->bprc += bprc;
3103         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3104         if (hw->mac.type == ixgbe_mac_82598EB)
3105                 hw_stats->mprc -= bprc;
3106
3107         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3108         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3109         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3110         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3111         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3112         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3113
3114         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3115         hw_stats->lxontxc += lxon;
3116         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3117         hw_stats->lxofftxc += lxoff;
3118         total = lxon + lxoff;
3119
3120         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3121         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3122         hw_stats->gptc -= total;
3123         hw_stats->mptc -= total;
3124         hw_stats->ptc64 -= total;
3125         hw_stats->gotc -= total * ETHER_MIN_LEN;
3126
3127         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3128         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3129         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3130         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3131         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3132         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3133         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3134         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3135         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3136         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3137         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3138         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3139         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3140         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3141         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3142         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3143         /* Only read FCOE on 82599 */
3144         if (hw->mac.type != ixgbe_mac_82598EB) {
3145                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3146                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3147                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3148                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3149                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3150         }
3151
3152         /* Flow Director Stats registers */
3153         if (hw->mac.type != ixgbe_mac_82598EB) {
3154                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3155                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3156                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3157                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3158                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3159                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3160                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3161                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3162                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3163                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3164         }
3165         /* MACsec Stats registers */
3166         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3167         macsec_stats->out_pkts_encrypted +=
3168                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3169         macsec_stats->out_pkts_protected +=
3170                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3171         macsec_stats->out_octets_encrypted +=
3172                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3173         macsec_stats->out_octets_protected +=
3174                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3175         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3176         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3177         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3178         macsec_stats->in_pkts_unknownsci +=
3179                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3180         macsec_stats->in_octets_decrypted +=
3181                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3182         macsec_stats->in_octets_validated +=
3183                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3184         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3185         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3186         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3187         for (i = 0; i < 2; i++) {
3188                 macsec_stats->in_pkts_ok +=
3189                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3190                 macsec_stats->in_pkts_invalid +=
3191                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3192                 macsec_stats->in_pkts_notvalid +=
3193                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3194         }
3195         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3196         macsec_stats->in_pkts_notusingsa +=
3197                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3198 }
3199
3200 /*
3201  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3202  */
3203 static int
3204 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3205 {
3206         struct ixgbe_hw *hw =
3207                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3208         struct ixgbe_hw_stats *hw_stats =
3209                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3210         struct ixgbe_macsec_stats *macsec_stats =
3211                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3212                                 dev->data->dev_private);
3213         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3214         unsigned i;
3215
3216         total_missed_rx = 0;
3217         total_qbrc = 0;
3218         total_qprc = 0;
3219         total_qprdc = 0;
3220
3221         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3222                         &total_qbrc, &total_qprc, &total_qprdc);
3223
3224         if (stats == NULL)
3225                 return -EINVAL;
3226
3227         /* Fill out the rte_eth_stats statistics structure */
3228         stats->ipackets = total_qprc;
3229         stats->ibytes = total_qbrc;
3230         stats->opackets = hw_stats->gptc;
3231         stats->obytes = hw_stats->gotc;
3232
3233         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3234                 stats->q_ipackets[i] = hw_stats->qprc[i];
3235                 stats->q_opackets[i] = hw_stats->qptc[i];
3236                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3237                 stats->q_obytes[i] = hw_stats->qbtc[i];
3238                 stats->q_errors[i] = hw_stats->qprdc[i];
3239         }
3240
3241         /* Rx Errors */
3242         stats->imissed  = total_missed_rx;
3243         stats->ierrors  = hw_stats->crcerrs +
3244                           hw_stats->mspdc +
3245                           hw_stats->rlec +
3246                           hw_stats->ruc +
3247                           hw_stats->roc +
3248                           hw_stats->illerrc +
3249                           hw_stats->errbc +
3250                           hw_stats->rfc +
3251                           hw_stats->fccrc +
3252                           hw_stats->fclast;
3253
3254         /* Tx Errors */
3255         stats->oerrors  = 0;
3256         return 0;
3257 }
3258
3259 static void
3260 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3261 {
3262         struct ixgbe_hw_stats *stats =
3263                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3264
3265         /* HW registers are cleared on read */
3266         ixgbe_dev_stats_get(dev, NULL);
3267
3268         /* Reset software totals */
3269         memset(stats, 0, sizeof(*stats));
3270 }
3271
3272 /* This function calculates the number of xstats based on the current config */
3273 static unsigned
3274 ixgbe_xstats_calc_num(void) {
3275         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3276                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3277                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3278 }
3279
3280 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3281         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3282 {
3283         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3284         unsigned stat, i, count;
3285
3286         if (xstats_names != NULL) {
3287                 count = 0;
3288
3289                 /* Note: limit >= cnt_stats checked upstream
3290                  * in rte_eth_xstats_names()
3291                  */
3292
3293                 /* Extended stats from ixgbe_hw_stats */
3294                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3295                         snprintf(xstats_names[count].name,
3296                                 sizeof(xstats_names[count].name),
3297                                 "%s",
3298                                 rte_ixgbe_stats_strings[i].name);
3299                         count++;
3300                 }
3301
3302                 /* MACsec Stats */
3303                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3304                         snprintf(xstats_names[count].name,
3305                                 sizeof(xstats_names[count].name),
3306                                 "%s",
3307                                 rte_ixgbe_macsec_strings[i].name);
3308                         count++;
3309                 }
3310
3311                 /* RX Priority Stats */
3312                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3313                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3314                                 snprintf(xstats_names[count].name,
3315                                         sizeof(xstats_names[count].name),
3316                                         "rx_priority%u_%s", i,
3317                                         rte_ixgbe_rxq_strings[stat].name);
3318                                 count++;
3319                         }
3320                 }
3321
3322                 /* TX Priority Stats */
3323                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3324                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3325                                 snprintf(xstats_names[count].name,
3326                                         sizeof(xstats_names[count].name),
3327                                         "tx_priority%u_%s", i,
3328                                         rte_ixgbe_txq_strings[stat].name);
3329                                 count++;
3330                         }
3331                 }
3332         }
3333         return cnt_stats;
3334 }
3335
3336 static int ixgbe_dev_xstats_get_names_by_id(
3337         struct rte_eth_dev *dev,
3338         struct rte_eth_xstat_name *xstats_names,
3339         const uint64_t *ids,
3340         unsigned int limit)
3341 {
3342         if (!ids) {
3343                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3344                 unsigned int stat, i, count;
3345
3346                 if (xstats_names != NULL) {
3347                         count = 0;
3348
3349                         /* Note: limit >= cnt_stats checked upstream
3350                          * in rte_eth_xstats_names()
3351                          */
3352
3353                         /* Extended stats from ixgbe_hw_stats */
3354                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3355                                 snprintf(xstats_names[count].name,
3356                                         sizeof(xstats_names[count].name),
3357                                         "%s",
3358                                         rte_ixgbe_stats_strings[i].name);
3359                                 count++;
3360                         }
3361
3362                         /* MACsec Stats */
3363                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3364                                 snprintf(xstats_names[count].name,
3365                                         sizeof(xstats_names[count].name),
3366                                         "%s",
3367                                         rte_ixgbe_macsec_strings[i].name);
3368                                 count++;
3369                         }
3370
3371                         /* RX Priority Stats */
3372                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3373                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3374                                         snprintf(xstats_names[count].name,
3375                                             sizeof(xstats_names[count].name),
3376                                             "rx_priority%u_%s", i,
3377                                             rte_ixgbe_rxq_strings[stat].name);
3378                                         count++;
3379                                 }
3380                         }
3381
3382                         /* TX Priority Stats */
3383                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3384                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3385                                         snprintf(xstats_names[count].name,
3386                                             sizeof(xstats_names[count].name),
3387                                             "tx_priority%u_%s", i,
3388                                             rte_ixgbe_txq_strings[stat].name);
3389                                         count++;
3390                                 }
3391                         }
3392                 }
3393                 return cnt_stats;
3394         }
3395
3396         uint16_t i;
3397         uint16_t size = ixgbe_xstats_calc_num();
3398         struct rte_eth_xstat_name xstats_names_copy[size];
3399
3400         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3401                         size);
3402
3403         for (i = 0; i < limit; i++) {
3404                 if (ids[i] >= size) {
3405                         PMD_INIT_LOG(ERR, "id value isn't valid");
3406                         return -1;
3407                 }
3408                 strcpy(xstats_names[i].name,
3409                                 xstats_names_copy[ids[i]].name);
3410         }
3411         return limit;
3412 }
3413
3414 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3415         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3416 {
3417         unsigned i;
3418
3419         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3420                 return -ENOMEM;
3421
3422         if (xstats_names != NULL)
3423                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3424                         snprintf(xstats_names[i].name,
3425                                 sizeof(xstats_names[i].name),
3426                                 "%s", rte_ixgbevf_stats_strings[i].name);
3427         return IXGBEVF_NB_XSTATS;
3428 }
3429
3430 static int
3431 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3432                                          unsigned n)
3433 {
3434         struct ixgbe_hw *hw =
3435                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3436         struct ixgbe_hw_stats *hw_stats =
3437                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3438         struct ixgbe_macsec_stats *macsec_stats =
3439                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3440                                 dev->data->dev_private);
3441         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3442         unsigned i, stat, count = 0;
3443
3444         count = ixgbe_xstats_calc_num();
3445
3446         if (n < count)
3447                 return count;
3448
3449         total_missed_rx = 0;
3450         total_qbrc = 0;
3451         total_qprc = 0;
3452         total_qprdc = 0;
3453
3454         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3455                         &total_qbrc, &total_qprc, &total_qprdc);
3456
3457         /* If this is a reset xstats is NULL, and we have cleared the
3458          * registers by reading them.
3459          */
3460         if (!xstats)
3461                 return 0;
3462
3463         /* Extended stats from ixgbe_hw_stats */
3464         count = 0;
3465         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3466                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3467                                 rte_ixgbe_stats_strings[i].offset);
3468                 xstats[count].id = count;
3469                 count++;
3470         }
3471
3472         /* MACsec Stats */
3473         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3474                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3475                                 rte_ixgbe_macsec_strings[i].offset);
3476                 xstats[count].id = count;
3477                 count++;
3478         }
3479
3480         /* RX Priority Stats */
3481         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3482                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3483                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3484                                         rte_ixgbe_rxq_strings[stat].offset +
3485                                         (sizeof(uint64_t) * i));
3486                         xstats[count].id = count;
3487                         count++;
3488                 }
3489         }
3490
3491         /* TX Priority Stats */
3492         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3493                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3494                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3495                                         rte_ixgbe_txq_strings[stat].offset +
3496                                         (sizeof(uint64_t) * i));
3497                         xstats[count].id = count;
3498                         count++;
3499                 }
3500         }
3501         return count;
3502 }
3503
3504 static int
3505 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3506                 uint64_t *values, unsigned int n)
3507 {
3508         if (!ids) {
3509                 struct ixgbe_hw *hw =
3510                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3511                 struct ixgbe_hw_stats *hw_stats =
3512                                 IXGBE_DEV_PRIVATE_TO_STATS(
3513                                                 dev->data->dev_private);
3514                 struct ixgbe_macsec_stats *macsec_stats =
3515                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3516                                         dev->data->dev_private);
3517                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3518                 unsigned int i, stat, count = 0;
3519
3520                 count = ixgbe_xstats_calc_num();
3521
3522                 if (!ids && n < count)
3523                         return count;
3524
3525                 total_missed_rx = 0;
3526                 total_qbrc = 0;
3527                 total_qprc = 0;
3528                 total_qprdc = 0;
3529
3530                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3531                                 &total_missed_rx, &total_qbrc, &total_qprc,
3532                                 &total_qprdc);
3533
3534                 /* If this is a reset xstats is NULL, and we have cleared the
3535                  * registers by reading them.
3536                  */
3537                 if (!ids && !values)
3538                         return 0;
3539
3540                 /* Extended stats from ixgbe_hw_stats */
3541                 count = 0;
3542                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3543                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3544                                         rte_ixgbe_stats_strings[i].offset);
3545                         count++;
3546                 }
3547
3548                 /* MACsec Stats */
3549                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3550                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3551                                         rte_ixgbe_macsec_strings[i].offset);
3552                         count++;
3553                 }
3554
3555                 /* RX Priority Stats */
3556                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3557                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3558                                 values[count] =
3559                                         *(uint64_t *)(((char *)hw_stats) +
3560                                         rte_ixgbe_rxq_strings[stat].offset +
3561                                         (sizeof(uint64_t) * i));
3562                                 count++;
3563                         }
3564                 }
3565
3566                 /* TX Priority Stats */
3567                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3568                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3569                                 values[count] =
3570                                         *(uint64_t *)(((char *)hw_stats) +
3571                                         rte_ixgbe_txq_strings[stat].offset +
3572                                         (sizeof(uint64_t) * i));
3573                                 count++;
3574                         }
3575                 }
3576                 return count;
3577         }
3578
3579         uint16_t i;
3580         uint16_t size = ixgbe_xstats_calc_num();
3581         uint64_t values_copy[size];
3582
3583         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3584
3585         for (i = 0; i < n; i++) {
3586                 if (ids[i] >= size) {
3587                         PMD_INIT_LOG(ERR, "id value isn't valid");
3588                         return -1;
3589                 }
3590                 values[i] = values_copy[ids[i]];
3591         }
3592         return n;
3593 }
3594
3595 static void
3596 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3597 {
3598         struct ixgbe_hw_stats *stats =
3599                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3600         struct ixgbe_macsec_stats *macsec_stats =
3601                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3602                                 dev->data->dev_private);
3603
3604         unsigned count = ixgbe_xstats_calc_num();
3605
3606         /* HW registers are cleared on read */
3607         ixgbe_dev_xstats_get(dev, NULL, count);
3608
3609         /* Reset software totals */
3610         memset(stats, 0, sizeof(*stats));
3611         memset(macsec_stats, 0, sizeof(*macsec_stats));
3612 }
3613
3614 static void
3615 ixgbevf_update_stats(struct rte_eth_dev *dev)
3616 {
3617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3619                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3620
3621         /* Good Rx packet, include VF loopback */
3622         UPDATE_VF_STAT(IXGBE_VFGPRC,
3623             hw_stats->last_vfgprc, hw_stats->vfgprc);
3624
3625         /* Good Rx octets, include VF loopback */
3626         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3627             hw_stats->last_vfgorc, hw_stats->vfgorc);
3628
3629         /* Good Tx packet, include VF loopback */
3630         UPDATE_VF_STAT(IXGBE_VFGPTC,
3631             hw_stats->last_vfgptc, hw_stats->vfgptc);
3632
3633         /* Good Tx octets, include VF loopback */
3634         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3635             hw_stats->last_vfgotc, hw_stats->vfgotc);
3636
3637         /* Rx Multicst Packet */
3638         UPDATE_VF_STAT(IXGBE_VFMPRC,
3639             hw_stats->last_vfmprc, hw_stats->vfmprc);
3640 }
3641
3642 static int
3643 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3644                        unsigned n)
3645 {
3646         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3647                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3648         unsigned i;
3649
3650         if (n < IXGBEVF_NB_XSTATS)
3651                 return IXGBEVF_NB_XSTATS;
3652
3653         ixgbevf_update_stats(dev);
3654
3655         if (!xstats)
3656                 return 0;
3657
3658         /* Extended stats */
3659         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3660                 xstats[i].id = i;
3661                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3662                         rte_ixgbevf_stats_strings[i].offset);
3663         }
3664
3665         return IXGBEVF_NB_XSTATS;
3666 }
3667
3668 static int
3669 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3670 {
3671         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3672                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3673
3674         ixgbevf_update_stats(dev);
3675
3676         if (stats == NULL)
3677                 return -EINVAL;
3678
3679         stats->ipackets = hw_stats->vfgprc;
3680         stats->ibytes = hw_stats->vfgorc;
3681         stats->opackets = hw_stats->vfgptc;
3682         stats->obytes = hw_stats->vfgotc;
3683         return 0;
3684 }
3685
3686 static void
3687 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3688 {
3689         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3690                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3691
3692         /* Sync HW register to the last stats */
3693         ixgbevf_dev_stats_get(dev, NULL);
3694
3695         /* reset HW current stats*/
3696         hw_stats->vfgprc = 0;
3697         hw_stats->vfgorc = 0;
3698         hw_stats->vfgptc = 0;
3699         hw_stats->vfgotc = 0;
3700 }
3701
3702 static int
3703 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3704 {
3705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706         u16 eeprom_verh, eeprom_verl;
3707         u32 etrack_id;
3708         int ret;
3709
3710         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3711         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3712
3713         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3714         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3715
3716         ret += 1; /* add the size of '\0' */
3717         if (fw_size < (u32)ret)
3718                 return ret;
3719         else
3720                 return 0;
3721 }
3722
3723 static void
3724 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3725 {
3726         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3728         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3729
3730         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3731         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3732         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3733                 /*
3734                  * When DCB/VT is off, maximum number of queues changes,
3735                  * except for 82598EB, which remains constant.
3736                  */
3737                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3738                                 hw->mac.type != ixgbe_mac_82598EB)
3739                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3740         }
3741         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3742         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3743         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3744         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3745         dev_info->max_vfs = pci_dev->max_vfs;
3746         if (hw->mac.type == ixgbe_mac_82598EB)
3747                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3748         else
3749                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3750         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3751         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3752         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3753                                      dev_info->rx_queue_offload_capa);
3754         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3755         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3756
3757         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3758                 .rx_thresh = {
3759                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3760                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3761                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3762                 },
3763                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3764                 .rx_drop_en = 0,
3765                 .offloads = 0,
3766         };
3767
3768         dev_info->default_txconf = (struct rte_eth_txconf) {
3769                 .tx_thresh = {
3770                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3771                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3772                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3773                 },
3774                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3775                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3776                 .offloads = 0,
3777         };
3778
3779         dev_info->rx_desc_lim = rx_desc_lim;
3780         dev_info->tx_desc_lim = tx_desc_lim;
3781
3782         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3783         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3784         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3785
3786         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3787         if (hw->mac.type == ixgbe_mac_X540 ||
3788             hw->mac.type == ixgbe_mac_X540_vf ||
3789             hw->mac.type == ixgbe_mac_X550 ||
3790             hw->mac.type == ixgbe_mac_X550_vf) {
3791                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3792         }
3793         if (hw->mac.type == ixgbe_mac_X550) {
3794                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3795                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3796         }
3797
3798         /* Driver-preferred Rx/Tx parameters */
3799         dev_info->default_rxportconf.burst_size = 32;
3800         dev_info->default_txportconf.burst_size = 32;
3801         dev_info->default_rxportconf.nb_queues = 1;
3802         dev_info->default_txportconf.nb_queues = 1;
3803         dev_info->default_rxportconf.ring_size = 256;
3804         dev_info->default_txportconf.ring_size = 256;
3805 }
3806
3807 static const uint32_t *
3808 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3809 {
3810         static const uint32_t ptypes[] = {
3811                 /* For non-vec functions,
3812                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3813                  * for vec functions,
3814                  * refers to _recv_raw_pkts_vec().
3815                  */
3816                 RTE_PTYPE_L2_ETHER,
3817                 RTE_PTYPE_L3_IPV4,
3818                 RTE_PTYPE_L3_IPV4_EXT,
3819                 RTE_PTYPE_L3_IPV6,
3820                 RTE_PTYPE_L3_IPV6_EXT,
3821                 RTE_PTYPE_L4_SCTP,
3822                 RTE_PTYPE_L4_TCP,
3823                 RTE_PTYPE_L4_UDP,
3824                 RTE_PTYPE_TUNNEL_IP,
3825                 RTE_PTYPE_INNER_L3_IPV6,
3826                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3827                 RTE_PTYPE_INNER_L4_TCP,
3828                 RTE_PTYPE_INNER_L4_UDP,
3829                 RTE_PTYPE_UNKNOWN
3830         };
3831
3832         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3833             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3834             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3835             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3836                 return ptypes;
3837
3838 #if defined(RTE_ARCH_X86)
3839         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3840             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3841                 return ptypes;
3842 #endif
3843         return NULL;
3844 }
3845
3846 static void
3847 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3848                      struct rte_eth_dev_info *dev_info)
3849 {
3850         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3852
3853         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3854         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3855         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3856         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3857         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3858         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3859         dev_info->max_vfs = pci_dev->max_vfs;
3860         if (hw->mac.type == ixgbe_mac_82598EB)
3861                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3862         else
3863                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3864         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3865         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3866                                      dev_info->rx_queue_offload_capa);
3867         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3868         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3869
3870         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3871                 .rx_thresh = {
3872                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3873                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3874                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3875                 },
3876                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3877                 .rx_drop_en = 0,
3878                 .offloads = 0,
3879         };
3880
3881         dev_info->default_txconf = (struct rte_eth_txconf) {
3882                 .tx_thresh = {
3883                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3884                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3885                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3886                 },
3887                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3888                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3889                 .offloads = 0,
3890         };
3891
3892         dev_info->rx_desc_lim = rx_desc_lim;
3893         dev_info->tx_desc_lim = tx_desc_lim;
3894 }
3895
3896 static int
3897 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3898                    int *link_up, int wait_to_complete)
3899 {
3900         struct ixgbe_mbx_info *mbx = &hw->mbx;
3901         struct ixgbe_mac_info *mac = &hw->mac;
3902         uint32_t links_reg, in_msg;
3903         int ret_val = 0;
3904
3905         /* If we were hit with a reset drop the link */
3906         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3907                 mac->get_link_status = true;
3908
3909         if (!mac->get_link_status)
3910                 goto out;
3911
3912         /* if link status is down no point in checking to see if pf is up */
3913         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3914         if (!(links_reg & IXGBE_LINKS_UP))
3915                 goto out;
3916
3917         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3918          * before the link status is correct
3919          */
3920         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3921                 int i;
3922
3923                 for (i = 0; i < 5; i++) {
3924                         rte_delay_us(100);
3925                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3926
3927                         if (!(links_reg & IXGBE_LINKS_UP))
3928                                 goto out;
3929                 }
3930         }
3931
3932         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3933         case IXGBE_LINKS_SPEED_10G_82599:
3934                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3935                 if (hw->mac.type >= ixgbe_mac_X550) {
3936                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3937                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3938                 }
3939                 break;
3940         case IXGBE_LINKS_SPEED_1G_82599:
3941                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3942                 break;
3943         case IXGBE_LINKS_SPEED_100_82599:
3944                 *speed = IXGBE_LINK_SPEED_100_FULL;
3945                 if (hw->mac.type == ixgbe_mac_X550) {
3946                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3947                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3948                 }
3949                 break;
3950         case IXGBE_LINKS_SPEED_10_X550EM_A:
3951                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3952                 /* Since Reserved in older MAC's */
3953                 if (hw->mac.type >= ixgbe_mac_X550)
3954                         *speed = IXGBE_LINK_SPEED_10_FULL;
3955                 break;
3956         default:
3957                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3958         }
3959
3960         /* if the read failed it could just be a mailbox collision, best wait
3961          * until we are called again and don't report an error
3962          */
3963         if (mbx->ops.read(hw, &in_msg, 1, 0))
3964                 goto out;
3965
3966         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3967                 /* msg is not CTS and is NACK we must have lost CTS status */
3968                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3969                         mac->get_link_status = false;
3970                 goto out;
3971         }
3972
3973         /* the pf is talking, if we timed out in the past we reinit */
3974         if (!mbx->timeout) {
3975                 ret_val = -1;
3976                 goto out;
3977         }
3978
3979         /* if we passed all the tests above then the link is up and we no
3980          * longer need to check for link
3981          */
3982         mac->get_link_status = false;
3983
3984 out:
3985         *link_up = !mac->get_link_status;
3986         return ret_val;
3987 }
3988
3989 static void
3990 ixgbe_dev_setup_link_alarm_handler(void *param)
3991 {
3992         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3994         struct ixgbe_interrupt *intr =
3995                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3996         u32 speed;
3997         bool autoneg = false;
3998
3999         speed = hw->phy.autoneg_advertised;
4000         if (!speed)
4001                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4002
4003         ixgbe_setup_link(hw, speed, true);
4004
4005         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4006 }
4007
4008 /* return 0 means link status changed, -1 means not changed */
4009 int
4010 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4011                             int wait_to_complete, int vf)
4012 {
4013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4014         struct rte_eth_link link;
4015         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4016         struct ixgbe_interrupt *intr =
4017                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4018         int link_up;
4019         int diag;
4020         int wait = 1;
4021
4022         memset(&link, 0, sizeof(link));
4023         link.link_status = ETH_LINK_DOWN;
4024         link.link_speed = ETH_SPEED_NUM_NONE;
4025         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4026         link.link_autoneg = ETH_LINK_AUTONEG;
4027
4028         hw->mac.get_link_status = true;
4029
4030         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4031                 return rte_eth_linkstatus_set(dev, &link);
4032
4033         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4034         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4035                 wait = 0;
4036
4037         if (vf)
4038                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4039         else
4040                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4041
4042         if (diag != 0) {
4043                 link.link_speed = ETH_SPEED_NUM_100M;
4044                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4045                 return rte_eth_linkstatus_set(dev, &link);
4046         }
4047
4048         if (link_up == 0) {
4049                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4050                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4051                         rte_eal_alarm_set(10,
4052                                 ixgbe_dev_setup_link_alarm_handler, dev);
4053                 }
4054                 return rte_eth_linkstatus_set(dev, &link);
4055         }
4056
4057         link.link_status = ETH_LINK_UP;
4058         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4059
4060         switch (link_speed) {
4061         default:
4062         case IXGBE_LINK_SPEED_UNKNOWN:
4063                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4064                 link.link_speed = ETH_SPEED_NUM_100M;
4065                 break;
4066
4067         case IXGBE_LINK_SPEED_100_FULL:
4068                 link.link_speed = ETH_SPEED_NUM_100M;
4069                 break;
4070
4071         case IXGBE_LINK_SPEED_1GB_FULL:
4072                 link.link_speed = ETH_SPEED_NUM_1G;
4073                 break;
4074
4075         case IXGBE_LINK_SPEED_2_5GB_FULL:
4076                 link.link_speed = ETH_SPEED_NUM_2_5G;
4077                 break;
4078
4079         case IXGBE_LINK_SPEED_5GB_FULL:
4080                 link.link_speed = ETH_SPEED_NUM_5G;
4081                 break;
4082
4083         case IXGBE_LINK_SPEED_10GB_FULL:
4084                 link.link_speed = ETH_SPEED_NUM_10G;
4085                 break;
4086         }
4087
4088         return rte_eth_linkstatus_set(dev, &link);
4089 }
4090
4091 static int
4092 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4093 {
4094         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4095 }
4096
4097 static int
4098 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4099 {
4100         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4101 }
4102
4103 static void
4104 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4105 {
4106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4107         uint32_t fctrl;
4108
4109         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4110         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4111         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4112 }
4113
4114 static void
4115 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4116 {
4117         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4118         uint32_t fctrl;
4119
4120         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4121         fctrl &= (~IXGBE_FCTRL_UPE);
4122         if (dev->data->all_multicast == 1)
4123                 fctrl |= IXGBE_FCTRL_MPE;
4124         else
4125                 fctrl &= (~IXGBE_FCTRL_MPE);
4126         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4127 }
4128
4129 static void
4130 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4131 {
4132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4133         uint32_t fctrl;
4134
4135         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4136         fctrl |= IXGBE_FCTRL_MPE;
4137         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4138 }
4139
4140 static void
4141 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4142 {
4143         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4144         uint32_t fctrl;
4145
4146         if (dev->data->promiscuous == 1)
4147                 return; /* must remain in all_multicast mode */
4148
4149         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4150         fctrl &= (~IXGBE_FCTRL_MPE);
4151         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4152 }
4153
4154 /**
4155  * It clears the interrupt causes and enables the interrupt.
4156  * It will be called once only during nic initialized.
4157  *
4158  * @param dev
4159  *  Pointer to struct rte_eth_dev.
4160  * @param on
4161  *  Enable or Disable.
4162  *
4163  * @return
4164  *  - On success, zero.
4165  *  - On failure, a negative value.
4166  */
4167 static int
4168 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4169 {
4170         struct ixgbe_interrupt *intr =
4171                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4172
4173         ixgbe_dev_link_status_print(dev);
4174         if (on)
4175                 intr->mask |= IXGBE_EICR_LSC;
4176         else
4177                 intr->mask &= ~IXGBE_EICR_LSC;
4178
4179         return 0;
4180 }
4181
4182 /**
4183  * It clears the interrupt causes and enables the interrupt.
4184  * It will be called once only during nic initialized.
4185  *
4186  * @param dev
4187  *  Pointer to struct rte_eth_dev.
4188  *
4189  * @return
4190  *  - On success, zero.
4191  *  - On failure, a negative value.
4192  */
4193 static int
4194 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4195 {
4196         struct ixgbe_interrupt *intr =
4197                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4198
4199         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4200
4201         return 0;
4202 }
4203
4204 /**
4205  * It clears the interrupt causes and enables the interrupt.
4206  * It will be called once only during nic initialized.
4207  *
4208  * @param dev
4209  *  Pointer to struct rte_eth_dev.
4210  *
4211  * @return
4212  *  - On success, zero.
4213  *  - On failure, a negative value.
4214  */
4215 static int
4216 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4217 {
4218         struct ixgbe_interrupt *intr =
4219                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4220
4221         intr->mask |= IXGBE_EICR_LINKSEC;
4222
4223         return 0;
4224 }
4225
4226 /*
4227  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4228  *
4229  * @param dev
4230  *  Pointer to struct rte_eth_dev.
4231  *
4232  * @return
4233  *  - On success, zero.
4234  *  - On failure, a negative value.
4235  */
4236 static int
4237 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4238 {
4239         uint32_t eicr;
4240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4241         struct ixgbe_interrupt *intr =
4242                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4243
4244         /* clear all cause mask */
4245         ixgbe_disable_intr(hw);
4246
4247         /* read-on-clear nic registers here */
4248         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4249         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4250
4251         intr->flags = 0;
4252
4253         /* set flag for async link update */
4254         if (eicr & IXGBE_EICR_LSC)
4255                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4256
4257         if (eicr & IXGBE_EICR_MAILBOX)
4258                 intr->flags |= IXGBE_FLAG_MAILBOX;
4259
4260         if (eicr & IXGBE_EICR_LINKSEC)
4261                 intr->flags |= IXGBE_FLAG_MACSEC;
4262
4263         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4264             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4265             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4266                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4267
4268         return 0;
4269 }
4270
4271 /**
4272  * It gets and then prints the link status.
4273  *
4274  * @param dev
4275  *  Pointer to struct rte_eth_dev.
4276  *
4277  * @return
4278  *  - On success, zero.
4279  *  - On failure, a negative value.
4280  */
4281 static void
4282 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4283 {
4284         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4285         struct rte_eth_link link;
4286
4287         rte_eth_linkstatus_get(dev, &link);
4288
4289         if (link.link_status) {
4290                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4291                                         (int)(dev->data->port_id),
4292                                         (unsigned)link.link_speed,
4293                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4294                                         "full-duplex" : "half-duplex");
4295         } else {
4296                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4297                                 (int)(dev->data->port_id));
4298         }
4299         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4300                                 pci_dev->addr.domain,
4301                                 pci_dev->addr.bus,
4302                                 pci_dev->addr.devid,
4303                                 pci_dev->addr.function);
4304 }
4305
4306 /*
4307  * It executes link_update after knowing an interrupt occurred.
4308  *
4309  * @param dev
4310  *  Pointer to struct rte_eth_dev.
4311  *
4312  * @return
4313  *  - On success, zero.
4314  *  - On failure, a negative value.
4315  */
4316 static int
4317 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4318 {
4319         struct ixgbe_interrupt *intr =
4320                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4321         int64_t timeout;
4322         struct ixgbe_hw *hw =
4323                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324
4325         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4326
4327         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4328                 ixgbe_pf_mbx_process(dev);
4329                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4330         }
4331
4332         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4333                 ixgbe_handle_lasi(hw);
4334                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4335         }
4336
4337         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4338                 struct rte_eth_link link;
4339
4340                 /* get the link status before link update, for predicting later */
4341                 rte_eth_linkstatus_get(dev, &link);
4342
4343                 ixgbe_dev_link_update(dev, 0);
4344
4345                 /* likely to up */
4346                 if (!link.link_status)
4347                         /* handle it 1 sec later, wait it being stable */
4348                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4349                 /* likely to down */
4350                 else
4351                         /* handle it 4 sec later, wait it being stable */
4352                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4353
4354                 ixgbe_dev_link_status_print(dev);
4355                 if (rte_eal_alarm_set(timeout * 1000,
4356                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4357                         PMD_DRV_LOG(ERR, "Error setting alarm");
4358                 else {
4359                         /* remember original mask */
4360                         intr->mask_original = intr->mask;
4361                         /* only disable lsc interrupt */
4362                         intr->mask &= ~IXGBE_EIMS_LSC;
4363                 }
4364         }
4365
4366         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4367         ixgbe_enable_intr(dev);
4368
4369         return 0;
4370 }
4371
4372 /**
4373  * Interrupt handler which shall be registered for alarm callback for delayed
4374  * handling specific interrupt to wait for the stable nic state. As the
4375  * NIC interrupt state is not stable for ixgbe after link is just down,
4376  * it needs to wait 4 seconds to get the stable status.
4377  *
4378  * @param handle
4379  *  Pointer to interrupt handle.
4380  * @param param
4381  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4382  *
4383  * @return
4384  *  void
4385  */
4386 static void
4387 ixgbe_dev_interrupt_delayed_handler(void *param)
4388 {
4389         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4390         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4391         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4392         struct ixgbe_interrupt *intr =
4393                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4394         struct ixgbe_hw *hw =
4395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4396         uint32_t eicr;
4397
4398         ixgbe_disable_intr(hw);
4399
4400         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4401         if (eicr & IXGBE_EICR_MAILBOX)
4402                 ixgbe_pf_mbx_process(dev);
4403
4404         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4405                 ixgbe_handle_lasi(hw);
4406                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4407         }
4408
4409         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4410                 ixgbe_dev_link_update(dev, 0);
4411                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4412                 ixgbe_dev_link_status_print(dev);
4413                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4414                                               NULL);
4415         }
4416
4417         if (intr->flags & IXGBE_FLAG_MACSEC) {
4418                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4419                                               NULL);
4420                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4421         }
4422
4423         /* restore original mask */
4424         intr->mask = intr->mask_original;
4425         intr->mask_original = 0;
4426
4427         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4428         ixgbe_enable_intr(dev);
4429         rte_intr_enable(intr_handle);
4430 }
4431
4432 /**
4433  * Interrupt handler triggered by NIC  for handling
4434  * specific interrupt.
4435  *
4436  * @param handle
4437  *  Pointer to interrupt handle.
4438  * @param param
4439  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4440  *
4441  * @return
4442  *  void
4443  */
4444 static void
4445 ixgbe_dev_interrupt_handler(void *param)
4446 {
4447         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4448
4449         ixgbe_dev_interrupt_get_status(dev);
4450         ixgbe_dev_interrupt_action(dev);
4451 }
4452
4453 static int
4454 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4455 {
4456         struct ixgbe_hw *hw;
4457
4458         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4459         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4460 }
4461
4462 static int
4463 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4464 {
4465         struct ixgbe_hw *hw;
4466
4467         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4468         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4469 }
4470
4471 static int
4472 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4473 {
4474         struct ixgbe_hw *hw;
4475         uint32_t mflcn_reg;
4476         uint32_t fccfg_reg;
4477         int rx_pause;
4478         int tx_pause;
4479
4480         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481
4482         fc_conf->pause_time = hw->fc.pause_time;
4483         fc_conf->high_water = hw->fc.high_water[0];
4484         fc_conf->low_water = hw->fc.low_water[0];
4485         fc_conf->send_xon = hw->fc.send_xon;
4486         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4487
4488         /*
4489          * Return rx_pause status according to actual setting of
4490          * MFLCN register.
4491          */
4492         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4493         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4494                 rx_pause = 1;
4495         else
4496                 rx_pause = 0;
4497
4498         /*
4499          * Return tx_pause status according to actual setting of
4500          * FCCFG register.
4501          */
4502         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4503         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4504                 tx_pause = 1;
4505         else
4506                 tx_pause = 0;
4507
4508         if (rx_pause && tx_pause)
4509                 fc_conf->mode = RTE_FC_FULL;
4510         else if (rx_pause)
4511                 fc_conf->mode = RTE_FC_RX_PAUSE;
4512         else if (tx_pause)
4513                 fc_conf->mode = RTE_FC_TX_PAUSE;
4514         else
4515                 fc_conf->mode = RTE_FC_NONE;
4516
4517         return 0;
4518 }
4519
4520 static int
4521 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4522 {
4523         struct ixgbe_hw *hw;
4524         int err;
4525         uint32_t rx_buf_size;
4526         uint32_t max_high_water;
4527         uint32_t mflcn;
4528         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4529                 ixgbe_fc_none,
4530                 ixgbe_fc_rx_pause,
4531                 ixgbe_fc_tx_pause,
4532                 ixgbe_fc_full
4533         };
4534
4535         PMD_INIT_FUNC_TRACE();
4536
4537         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4538         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4539         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4540
4541         /*
4542          * At least reserve one Ethernet frame for watermark
4543          * high_water/low_water in kilo bytes for ixgbe
4544          */
4545         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4546         if ((fc_conf->high_water > max_high_water) ||
4547                 (fc_conf->high_water < fc_conf->low_water)) {
4548                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4549                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4550                 return -EINVAL;
4551         }
4552
4553         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4554         hw->fc.pause_time     = fc_conf->pause_time;
4555         hw->fc.high_water[0]  = fc_conf->high_water;
4556         hw->fc.low_water[0]   = fc_conf->low_water;
4557         hw->fc.send_xon       = fc_conf->send_xon;
4558         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4559
4560         err = ixgbe_fc_enable(hw);
4561
4562         /* Not negotiated is not an error case */
4563         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4564
4565                 /* check if we want to forward MAC frames - driver doesn't have native
4566                  * capability to do that, so we'll write the registers ourselves */
4567
4568                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4569
4570                 /* set or clear MFLCN.PMCF bit depending on configuration */
4571                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4572                         mflcn |= IXGBE_MFLCN_PMCF;
4573                 else
4574                         mflcn &= ~IXGBE_MFLCN_PMCF;
4575
4576                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4577                 IXGBE_WRITE_FLUSH(hw);
4578
4579                 return 0;
4580         }
4581
4582         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4583         return -EIO;
4584 }
4585
4586 /**
4587  *  ixgbe_pfc_enable_generic - Enable flow control
4588  *  @hw: pointer to hardware structure
4589  *  @tc_num: traffic class number
4590  *  Enable flow control according to the current settings.
4591  */
4592 static int
4593 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4594 {
4595         int ret_val = 0;
4596         uint32_t mflcn_reg, fccfg_reg;
4597         uint32_t reg;
4598         uint32_t fcrtl, fcrth;
4599         uint8_t i;
4600         uint8_t nb_rx_en;
4601
4602         /* Validate the water mark configuration */
4603         if (!hw->fc.pause_time) {
4604                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4605                 goto out;
4606         }
4607
4608         /* Low water mark of zero causes XOFF floods */
4609         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4610                  /* High/Low water can not be 0 */
4611                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4612                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4613                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4614                         goto out;
4615                 }
4616
4617                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4618                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4619                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4620                         goto out;
4621                 }
4622         }
4623         /* Negotiate the fc mode to use */
4624         ixgbe_fc_autoneg(hw);
4625
4626         /* Disable any previous flow control settings */
4627         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4628         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4629
4630         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4631         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4632
4633         switch (hw->fc.current_mode) {
4634         case ixgbe_fc_none:
4635                 /*
4636                  * If the count of enabled RX Priority Flow control >1,
4637                  * and the TX pause can not be disabled
4638                  */
4639                 nb_rx_en = 0;
4640                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4641                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4642                         if (reg & IXGBE_FCRTH_FCEN)
4643                                 nb_rx_en++;
4644                 }
4645                 if (nb_rx_en > 1)
4646                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4647                 break;
4648         case ixgbe_fc_rx_pause:
4649                 /*
4650                  * Rx Flow control is enabled and Tx Flow control is
4651                  * disabled by software override. Since there really
4652                  * isn't a way to advertise that we are capable of RX
4653                  * Pause ONLY, we will advertise that we support both
4654                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4655                  * disable the adapter's ability to send PAUSE frames.
4656                  */
4657                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4658                 /*
4659                  * If the count of enabled RX Priority Flow control >1,
4660                  * and the TX pause can not be disabled
4661                  */
4662                 nb_rx_en = 0;
4663                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4664                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4665                         if (reg & IXGBE_FCRTH_FCEN)
4666                                 nb_rx_en++;
4667                 }
4668                 if (nb_rx_en > 1)
4669                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4670                 break;
4671         case ixgbe_fc_tx_pause:
4672                 /*
4673                  * Tx Flow control is enabled, and Rx Flow control is
4674                  * disabled by software override.
4675                  */
4676                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4677                 break;
4678         case ixgbe_fc_full:
4679                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4680                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4681                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4682                 break;
4683         default:
4684                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4685                 ret_val = IXGBE_ERR_CONFIG;
4686                 goto out;
4687         }
4688
4689         /* Set 802.3x based flow control settings. */
4690         mflcn_reg |= IXGBE_MFLCN_DPF;
4691         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4692         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4693
4694         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4695         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4696                 hw->fc.high_water[tc_num]) {
4697                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4698                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4699                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4700         } else {
4701                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4702                 /*
4703                  * In order to prevent Tx hangs when the internal Tx
4704                  * switch is enabled we must set the high water mark
4705                  * to the maximum FCRTH value.  This allows the Tx
4706                  * switch to function even under heavy Rx workloads.
4707                  */
4708                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4709         }
4710         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4711
4712         /* Configure pause time (2 TCs per register) */
4713         reg = hw->fc.pause_time * 0x00010001;
4714         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4715                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4716
4717         /* Configure flow control refresh threshold value */
4718         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4719
4720 out:
4721         return ret_val;
4722 }
4723
4724 static int
4725 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4726 {
4727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4728         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4729
4730         if (hw->mac.type != ixgbe_mac_82598EB) {
4731                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4732         }
4733         return ret_val;
4734 }
4735
4736 static int
4737 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4738 {
4739         int err;
4740         uint32_t rx_buf_size;
4741         uint32_t max_high_water;
4742         uint8_t tc_num;
4743         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4744         struct ixgbe_hw *hw =
4745                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746         struct ixgbe_dcb_config *dcb_config =
4747                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4748
4749         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4750                 ixgbe_fc_none,
4751                 ixgbe_fc_rx_pause,
4752                 ixgbe_fc_tx_pause,
4753                 ixgbe_fc_full
4754         };
4755
4756         PMD_INIT_FUNC_TRACE();
4757
4758         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4759         tc_num = map[pfc_conf->priority];
4760         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4761         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4762         /*
4763          * At least reserve one Ethernet frame for watermark
4764          * high_water/low_water in kilo bytes for ixgbe
4765          */
4766         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4767         if ((pfc_conf->fc.high_water > max_high_water) ||
4768             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4769                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4770                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4771                 return -EINVAL;
4772         }
4773
4774         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4775         hw->fc.pause_time = pfc_conf->fc.pause_time;
4776         hw->fc.send_xon = pfc_conf->fc.send_xon;
4777         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4778         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4779
4780         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4781
4782         /* Not negotiated is not an error case */
4783         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4784                 return 0;
4785
4786         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4787         return -EIO;
4788 }
4789
4790 static int
4791 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4792                           struct rte_eth_rss_reta_entry64 *reta_conf,
4793                           uint16_t reta_size)
4794 {
4795         uint16_t i, sp_reta_size;
4796         uint8_t j, mask;
4797         uint32_t reta, r;
4798         uint16_t idx, shift;
4799         struct ixgbe_adapter *adapter =
4800                 (struct ixgbe_adapter *)dev->data->dev_private;
4801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4802         uint32_t reta_reg;
4803
4804         PMD_INIT_FUNC_TRACE();
4805
4806         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4807                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4808                         "NIC.");
4809                 return -ENOTSUP;
4810         }
4811
4812         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4813         if (reta_size != sp_reta_size) {
4814                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4815                         "(%d) doesn't match the number hardware can supported "
4816                         "(%d)", reta_size, sp_reta_size);
4817                 return -EINVAL;
4818         }
4819
4820         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4821                 idx = i / RTE_RETA_GROUP_SIZE;
4822                 shift = i % RTE_RETA_GROUP_SIZE;
4823                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4824                                                 IXGBE_4_BIT_MASK);
4825                 if (!mask)
4826                         continue;
4827                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4828                 if (mask == IXGBE_4_BIT_MASK)
4829                         r = 0;
4830                 else
4831                         r = IXGBE_READ_REG(hw, reta_reg);
4832                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4833                         if (mask & (0x1 << j))
4834                                 reta |= reta_conf[idx].reta[shift + j] <<
4835                                                         (CHAR_BIT * j);
4836                         else
4837                                 reta |= r & (IXGBE_8_BIT_MASK <<
4838                                                 (CHAR_BIT * j));
4839                 }
4840                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4841         }
4842         adapter->rss_reta_updated = 1;
4843
4844         return 0;
4845 }
4846
4847 static int
4848 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4849                          struct rte_eth_rss_reta_entry64 *reta_conf,
4850                          uint16_t reta_size)
4851 {
4852         uint16_t i, sp_reta_size;
4853         uint8_t j, mask;
4854         uint32_t reta;
4855         uint16_t idx, shift;
4856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4857         uint32_t reta_reg;
4858
4859         PMD_INIT_FUNC_TRACE();
4860         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4861         if (reta_size != sp_reta_size) {
4862                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4863                         "(%d) doesn't match the number hardware can supported "
4864                         "(%d)", reta_size, sp_reta_size);
4865                 return -EINVAL;
4866         }
4867
4868         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4869                 idx = i / RTE_RETA_GROUP_SIZE;
4870                 shift = i % RTE_RETA_GROUP_SIZE;
4871                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4872                                                 IXGBE_4_BIT_MASK);
4873                 if (!mask)
4874                         continue;
4875
4876                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4877                 reta = IXGBE_READ_REG(hw, reta_reg);
4878                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4879                         if (mask & (0x1 << j))
4880                                 reta_conf[idx].reta[shift + j] =
4881                                         ((reta >> (CHAR_BIT * j)) &
4882                                                 IXGBE_8_BIT_MASK);
4883                 }
4884         }
4885
4886         return 0;
4887 }
4888
4889 static int
4890 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4891                                 uint32_t index, uint32_t pool)
4892 {
4893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894         uint32_t enable_addr = 1;
4895
4896         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4897                              pool, enable_addr);
4898 }
4899
4900 static void
4901 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4902 {
4903         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904
4905         ixgbe_clear_rar(hw, index);
4906 }
4907
4908 static int
4909 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4910 {
4911         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4912
4913         ixgbe_remove_rar(dev, 0);
4914         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4915
4916         return 0;
4917 }
4918
4919 static bool
4920 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4921 {
4922         if (strcmp(dev->device->driver->name, drv->driver.name))
4923                 return false;
4924
4925         return true;
4926 }
4927
4928 bool
4929 is_ixgbe_supported(struct rte_eth_dev *dev)
4930 {
4931         return is_device_supported(dev, &rte_ixgbe_pmd);
4932 }
4933
4934 static int
4935 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4936 {
4937         uint32_t hlreg0;
4938         uint32_t maxfrs;
4939         struct ixgbe_hw *hw;
4940         struct rte_eth_dev_info dev_info;
4941         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4942         struct rte_eth_dev_data *dev_data = dev->data;
4943
4944         ixgbe_dev_info_get(dev, &dev_info);
4945
4946         /* check that mtu is within the allowed range */
4947         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4948                 return -EINVAL;
4949
4950         /* If device is started, refuse mtu that requires the support of
4951          * scattered packets when this feature has not been enabled before.
4952          */
4953         if (dev_data->dev_started && !dev_data->scattered_rx &&
4954             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4955              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4956                 PMD_INIT_LOG(ERR, "Stop port first.");
4957                 return -EINVAL;
4958         }
4959
4960         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4961         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4962
4963         /* switch to jumbo mode if needed */
4964         if (frame_size > ETHER_MAX_LEN) {
4965                 dev->data->dev_conf.rxmode.offloads |=
4966                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4967                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4968         } else {
4969                 dev->data->dev_conf.rxmode.offloads &=
4970                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4971                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4972         }
4973         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4974
4975         /* update max frame size */
4976         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4977
4978         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4979         maxfrs &= 0x0000FFFF;
4980         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4981         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4982
4983         return 0;
4984 }
4985
4986 /*
4987  * Virtual Function operations
4988  */
4989 static void
4990 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4991 {
4992         struct ixgbe_interrupt *intr =
4993                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4994         struct ixgbe_hw *hw =
4995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996
4997         PMD_INIT_FUNC_TRACE();
4998
4999         /* Clear interrupt mask to stop from interrupts being generated */
5000         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5001
5002         IXGBE_WRITE_FLUSH(hw);
5003
5004         /* Clear mask value. */
5005         intr->mask = 0;
5006 }
5007
5008 static void
5009 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5010 {
5011         struct ixgbe_interrupt *intr =
5012                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5013         struct ixgbe_hw *hw =
5014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5015
5016         PMD_INIT_FUNC_TRACE();
5017
5018         /* VF enable interrupt autoclean */
5019         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5020         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5021         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5022
5023         IXGBE_WRITE_FLUSH(hw);
5024
5025         /* Save IXGBE_VTEIMS value to mask. */
5026         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5027 }
5028
5029 static int
5030 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5031 {
5032         struct rte_eth_conf *conf = &dev->data->dev_conf;
5033         struct ixgbe_adapter *adapter =
5034                         (struct ixgbe_adapter *)dev->data->dev_private;
5035
5036         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5037                      dev->data->port_id);
5038
5039         /*
5040          * VF has no ability to enable/disable HW CRC
5041          * Keep the persistent behavior the same as Host PF
5042          */
5043 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5044         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5045                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5046                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5047         }
5048 #else
5049         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5050                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5051                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5052         }
5053 #endif
5054
5055         /*
5056          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5057          * allocation or vector Rx preconditions we will reset it.
5058          */
5059         adapter->rx_bulk_alloc_allowed = true;
5060         adapter->rx_vec_allowed = true;
5061
5062         return 0;
5063 }
5064
5065 static int
5066 ixgbevf_dev_start(struct rte_eth_dev *dev)
5067 {
5068         struct ixgbe_hw *hw =
5069                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5070         uint32_t intr_vector = 0;
5071         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5072         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5073
5074         int err, mask = 0;
5075
5076         PMD_INIT_FUNC_TRACE();
5077
5078         /* Stop the link setup handler before resetting the HW. */
5079         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5080
5081         err = hw->mac.ops.reset_hw(hw);
5082         if (err) {
5083                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5084                 return err;
5085         }
5086         hw->mac.get_link_status = true;
5087
5088         /* negotiate mailbox API version to use with the PF. */
5089         ixgbevf_negotiate_api(hw);
5090
5091         ixgbevf_dev_tx_init(dev);
5092
5093         /* This can fail when allocating mbufs for descriptor rings */
5094         err = ixgbevf_dev_rx_init(dev);
5095         if (err) {
5096                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5097                 ixgbe_dev_clear_queues(dev);
5098                 return err;
5099         }
5100
5101         /* Set vfta */
5102         ixgbevf_set_vfta_all(dev, 1);
5103
5104         /* Set HW strip */
5105         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5106                 ETH_VLAN_EXTEND_MASK;
5107         err = ixgbevf_vlan_offload_config(dev, mask);
5108         if (err) {
5109                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5110                 ixgbe_dev_clear_queues(dev);
5111                 return err;
5112         }
5113
5114         ixgbevf_dev_rxtx_start(dev);
5115
5116         /* check and configure queue intr-vector mapping */
5117         if (rte_intr_cap_multiple(intr_handle) &&
5118             dev->data->dev_conf.intr_conf.rxq) {
5119                 /* According to datasheet, only vector 0/1/2 can be used,
5120                  * now only one vector is used for Rx queue
5121                  */
5122                 intr_vector = 1;
5123                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5124                         return -1;
5125         }
5126
5127         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5128                 intr_handle->intr_vec =
5129                         rte_zmalloc("intr_vec",
5130                                     dev->data->nb_rx_queues * sizeof(int), 0);
5131                 if (intr_handle->intr_vec == NULL) {
5132                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5133                                      " intr_vec", dev->data->nb_rx_queues);
5134                         return -ENOMEM;
5135                 }
5136         }
5137         ixgbevf_configure_msix(dev);
5138
5139         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5140          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5141          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5142          * is not cleared, it will fail when following rte_intr_enable( ) tries
5143          * to map Rx queue interrupt to other VFIO vectors.
5144          * So clear uio/vfio intr/evevnfd first to avoid failure.
5145          */
5146         rte_intr_disable(intr_handle);
5147
5148         rte_intr_enable(intr_handle);
5149
5150         /* Re-enable interrupt for VF */
5151         ixgbevf_intr_enable(dev);
5152
5153         /*
5154          * Update link status right before return, because it may
5155          * start link configuration process in a separate thread.
5156          */
5157         ixgbevf_dev_link_update(dev, 0);
5158
5159         return 0;
5160 }
5161
5162 static void
5163 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5164 {
5165         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5166         struct ixgbe_adapter *adapter =
5167                 (struct ixgbe_adapter *)dev->data->dev_private;
5168         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5169         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5170
5171         PMD_INIT_FUNC_TRACE();
5172
5173         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5174
5175         ixgbevf_intr_disable(dev);
5176
5177         hw->adapter_stopped = 1;
5178         ixgbe_stop_adapter(hw);
5179
5180         /*
5181           * Clear what we set, but we still keep shadow_vfta to
5182           * restore after device starts
5183           */
5184         ixgbevf_set_vfta_all(dev, 0);
5185
5186         /* Clear stored conf */
5187         dev->data->scattered_rx = 0;
5188
5189         ixgbe_dev_clear_queues(dev);
5190
5191         /* Clean datapath event and queue/vec mapping */
5192         rte_intr_efd_disable(intr_handle);
5193         if (intr_handle->intr_vec != NULL) {
5194                 rte_free(intr_handle->intr_vec);
5195                 intr_handle->intr_vec = NULL;
5196         }
5197
5198         adapter->rss_reta_updated = 0;
5199 }
5200
5201 static void
5202 ixgbevf_dev_close(struct rte_eth_dev *dev)
5203 {
5204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5205
5206         PMD_INIT_FUNC_TRACE();
5207
5208         ixgbe_reset_hw(hw);
5209
5210         ixgbevf_dev_stop(dev);
5211
5212         ixgbe_dev_free_queues(dev);
5213
5214         /**
5215          * Remove the VF MAC address ro ensure
5216          * that the VF traffic goes to the PF
5217          * after stop, close and detach of the VF
5218          **/
5219         ixgbevf_remove_mac_addr(dev, 0);
5220 }
5221
5222 /*
5223  * Reset VF device
5224  */
5225 static int
5226 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5227 {
5228         int ret;
5229
5230         ret = eth_ixgbevf_dev_uninit(dev);
5231         if (ret)
5232                 return ret;
5233
5234         ret = eth_ixgbevf_dev_init(dev);
5235
5236         return ret;
5237 }
5238
5239 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5240 {
5241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5242         struct ixgbe_vfta *shadow_vfta =
5243                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5244         int i = 0, j = 0, vfta = 0, mask = 1;
5245
5246         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5247                 vfta = shadow_vfta->vfta[i];
5248                 if (vfta) {
5249                         mask = 1;
5250                         for (j = 0; j < 32; j++) {
5251                                 if (vfta & mask)
5252                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5253                                                        on, false);
5254                                 mask <<= 1;
5255                         }
5256                 }
5257         }
5258
5259 }
5260
5261 static int
5262 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5263 {
5264         struct ixgbe_hw *hw =
5265                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5266         struct ixgbe_vfta *shadow_vfta =
5267                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5268         uint32_t vid_idx = 0;
5269         uint32_t vid_bit = 0;
5270         int ret = 0;
5271
5272         PMD_INIT_FUNC_TRACE();
5273
5274         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5275         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5276         if (ret) {
5277                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5278                 return ret;
5279         }
5280         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5281         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5282
5283         /* Save what we set and retore it after device reset */
5284         if (on)
5285                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5286         else
5287                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5288
5289         return 0;
5290 }
5291
5292 static void
5293 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5294 {
5295         struct ixgbe_hw *hw =
5296                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5297         uint32_t ctrl;
5298
5299         PMD_INIT_FUNC_TRACE();
5300
5301         if (queue >= hw->mac.max_rx_queues)
5302                 return;
5303
5304         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5305         if (on)
5306                 ctrl |= IXGBE_RXDCTL_VME;
5307         else
5308                 ctrl &= ~IXGBE_RXDCTL_VME;
5309         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5310
5311         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5312 }
5313
5314 static int
5315 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5316 {
5317         struct ixgbe_rx_queue *rxq;
5318         uint16_t i;
5319         int on = 0;
5320
5321         /* VF function only support hw strip feature, others are not support */
5322         if (mask & ETH_VLAN_STRIP_MASK) {
5323                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5324                         rxq = dev->data->rx_queues[i];
5325                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5326                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5327                 }
5328         }
5329
5330         return 0;
5331 }
5332
5333 static int
5334 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5335 {
5336         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5337
5338         ixgbevf_vlan_offload_config(dev, mask);
5339
5340         return 0;
5341 }
5342
5343 int
5344 ixgbe_vt_check(struct ixgbe_hw *hw)
5345 {
5346         uint32_t reg_val;
5347
5348         /* if Virtualization Technology is enabled */
5349         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5350         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5351                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5352                 return -1;
5353         }
5354
5355         return 0;
5356 }
5357
5358 static uint32_t
5359 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5360 {
5361         uint32_t vector = 0;
5362
5363         switch (hw->mac.mc_filter_type) {
5364         case 0:   /* use bits [47:36] of the address */
5365                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5366                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5367                 break;
5368         case 1:   /* use bits [46:35] of the address */
5369                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5370                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5371                 break;
5372         case 2:   /* use bits [45:34] of the address */
5373                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5374                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5375                 break;
5376         case 3:   /* use bits [43:32] of the address */
5377                 vector = ((uc_addr->addr_bytes[4]) |
5378                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5379                 break;
5380         default:  /* Invalid mc_filter_type */
5381                 break;
5382         }
5383
5384         /* vector can only be 12-bits or boundary will be exceeded */
5385         vector &= 0xFFF;
5386         return vector;
5387 }
5388
5389 static int
5390 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5391                         uint8_t on)
5392 {
5393         uint32_t vector;
5394         uint32_t uta_idx;
5395         uint32_t reg_val;
5396         uint32_t uta_shift;
5397         uint32_t rc;
5398         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5399         const uint32_t ixgbe_uta_bit_shift = 5;
5400         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5401         const uint32_t bit1 = 0x1;
5402
5403         struct ixgbe_hw *hw =
5404                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5405         struct ixgbe_uta_info *uta_info =
5406                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5407
5408         /* The UTA table only exists on 82599 hardware and newer */
5409         if (hw->mac.type < ixgbe_mac_82599EB)
5410                 return -ENOTSUP;
5411
5412         vector = ixgbe_uta_vector(hw, mac_addr);
5413         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5414         uta_shift = vector & ixgbe_uta_bit_mask;
5415
5416         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5417         if (rc == on)
5418                 return 0;
5419
5420         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5421         if (on) {
5422                 uta_info->uta_in_use++;
5423                 reg_val |= (bit1 << uta_shift);
5424                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5425         } else {
5426                 uta_info->uta_in_use--;
5427                 reg_val &= ~(bit1 << uta_shift);
5428                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5429         }
5430
5431         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5432
5433         if (uta_info->uta_in_use > 0)
5434                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5435                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5436         else
5437                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5438
5439         return 0;
5440 }
5441
5442 static int
5443 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5444 {
5445         int i;
5446         struct ixgbe_hw *hw =
5447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5448         struct ixgbe_uta_info *uta_info =
5449                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5450
5451         /* The UTA table only exists on 82599 hardware and newer */
5452         if (hw->mac.type < ixgbe_mac_82599EB)
5453                 return -ENOTSUP;
5454
5455         if (on) {
5456                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5457                         uta_info->uta_shadow[i] = ~0;
5458                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5459                 }
5460         } else {
5461                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5462                         uta_info->uta_shadow[i] = 0;
5463                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5464                 }
5465         }
5466         return 0;
5467
5468 }
5469
5470 uint32_t
5471 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5472 {
5473         uint32_t new_val = orig_val;
5474
5475         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5476                 new_val |= IXGBE_VMOLR_AUPE;
5477         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5478                 new_val |= IXGBE_VMOLR_ROMPE;
5479         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5480                 new_val |= IXGBE_VMOLR_ROPE;
5481         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5482                 new_val |= IXGBE_VMOLR_BAM;
5483         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5484                 new_val |= IXGBE_VMOLR_MPE;
5485
5486         return new_val;
5487 }
5488
5489 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5490 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5491 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5492 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5493 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5494         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5495         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5496
5497 static int
5498 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5499                       struct rte_eth_mirror_conf *mirror_conf,
5500                       uint8_t rule_id, uint8_t on)
5501 {
5502         uint32_t mr_ctl, vlvf;
5503         uint32_t mp_lsb = 0;
5504         uint32_t mv_msb = 0;
5505         uint32_t mv_lsb = 0;
5506         uint32_t mp_msb = 0;
5507         uint8_t i = 0;
5508         int reg_index = 0;
5509         uint64_t vlan_mask = 0;
5510
5511         const uint8_t pool_mask_offset = 32;
5512         const uint8_t vlan_mask_offset = 32;
5513         const uint8_t dst_pool_offset = 8;
5514         const uint8_t rule_mr_offset  = 4;
5515         const uint8_t mirror_rule_mask = 0x0F;
5516
5517         struct ixgbe_mirror_info *mr_info =
5518                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5519         struct ixgbe_hw *hw =
5520                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5521         uint8_t mirror_type = 0;
5522
5523         if (ixgbe_vt_check(hw) < 0)
5524                 return -ENOTSUP;
5525
5526         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5527                 return -EINVAL;
5528
5529         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5530                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5531                             mirror_conf->rule_type);
5532                 return -EINVAL;
5533         }
5534
5535         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5536                 mirror_type |= IXGBE_MRCTL_VLME;
5537                 /* Check if vlan id is valid and find conresponding VLAN ID
5538                  * index in VLVF
5539                  */
5540                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5541                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5542                                 /* search vlan id related pool vlan filter
5543                                  * index
5544                                  */
5545                                 reg_index = ixgbe_find_vlvf_slot(
5546                                                 hw,
5547                                                 mirror_conf->vlan.vlan_id[i],
5548                                                 false);
5549                                 if (reg_index < 0)
5550                                         return -EINVAL;
5551                                 vlvf = IXGBE_READ_REG(hw,
5552                                                       IXGBE_VLVF(reg_index));
5553                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5554                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5555                                       mirror_conf->vlan.vlan_id[i]))
5556                                         vlan_mask |= (1ULL << reg_index);
5557                                 else
5558                                         return -EINVAL;
5559                         }
5560                 }
5561
5562                 if (on) {
5563                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5564                         mv_msb = vlan_mask >> vlan_mask_offset;
5565
5566                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5567                                                 mirror_conf->vlan.vlan_mask;
5568                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5569                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5570                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5571                                                 mirror_conf->vlan.vlan_id[i];
5572                         }
5573                 } else {
5574                         mv_lsb = 0;
5575                         mv_msb = 0;
5576                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5577                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5578                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5579                 }
5580         }
5581
5582         /**
5583          * if enable pool mirror, write related pool mask register,if disable
5584          * pool mirror, clear PFMRVM register
5585          */
5586         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5587                 mirror_type |= IXGBE_MRCTL_VPME;
5588                 if (on) {
5589                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5590                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5591                         mr_info->mr_conf[rule_id].pool_mask =
5592                                         mirror_conf->pool_mask;
5593
5594                 } else {
5595                         mp_lsb = 0;
5596                         mp_msb = 0;
5597                         mr_info->mr_conf[rule_id].pool_mask = 0;
5598                 }
5599         }
5600         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5601                 mirror_type |= IXGBE_MRCTL_UPME;
5602         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5603                 mirror_type |= IXGBE_MRCTL_DPME;
5604
5605         /* read  mirror control register and recalculate it */
5606         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5607
5608         if (on) {
5609                 mr_ctl |= mirror_type;
5610                 mr_ctl &= mirror_rule_mask;
5611                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5612         } else {
5613                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5614         }
5615
5616         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5617         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5618
5619         /* write mirrror control  register */
5620         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5621
5622         /* write pool mirrror control  register */
5623         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5624                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5625                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5626                                 mp_msb);
5627         }
5628         /* write VLAN mirrror control  register */
5629         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5630                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5631                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5632                                 mv_msb);
5633         }
5634
5635         return 0;
5636 }
5637
5638 static int
5639 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5640 {
5641         int mr_ctl = 0;
5642         uint32_t lsb_val = 0;
5643         uint32_t msb_val = 0;
5644         const uint8_t rule_mr_offset = 4;
5645
5646         struct ixgbe_hw *hw =
5647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5648         struct ixgbe_mirror_info *mr_info =
5649                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5650
5651         if (ixgbe_vt_check(hw) < 0)
5652                 return -ENOTSUP;
5653
5654         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5655                 return -EINVAL;
5656
5657         memset(&mr_info->mr_conf[rule_id], 0,
5658                sizeof(struct rte_eth_mirror_conf));
5659
5660         /* clear PFVMCTL register */
5661         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5662
5663         /* clear pool mask register */
5664         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5665         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5666
5667         /* clear vlan mask register */
5668         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5669         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5670
5671         return 0;
5672 }
5673
5674 static int
5675 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5676 {
5677         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5678         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5679         struct ixgbe_interrupt *intr =
5680                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5681         struct ixgbe_hw *hw =
5682                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5683         uint32_t vec = IXGBE_MISC_VEC_ID;
5684
5685         if (rte_intr_allow_others(intr_handle))
5686                 vec = IXGBE_RX_VEC_START;
5687         intr->mask |= (1 << vec);
5688         RTE_SET_USED(queue_id);
5689         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5690
5691         rte_intr_enable(intr_handle);
5692
5693         return 0;
5694 }
5695
5696 static int
5697 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5698 {
5699         struct ixgbe_interrupt *intr =
5700                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5701         struct ixgbe_hw *hw =
5702                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5703         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5704         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5705         uint32_t vec = IXGBE_MISC_VEC_ID;
5706
5707         if (rte_intr_allow_others(intr_handle))
5708                 vec = IXGBE_RX_VEC_START;
5709         intr->mask &= ~(1 << vec);
5710         RTE_SET_USED(queue_id);
5711         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5712
5713         return 0;
5714 }
5715
5716 static int
5717 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5718 {
5719         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5720         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5721         uint32_t mask;
5722         struct ixgbe_hw *hw =
5723                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5724         struct ixgbe_interrupt *intr =
5725                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5726
5727         if (queue_id < 16) {
5728                 ixgbe_disable_intr(hw);
5729                 intr->mask |= (1 << queue_id);
5730                 ixgbe_enable_intr(dev);
5731         } else if (queue_id < 32) {
5732                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5733                 mask &= (1 << queue_id);
5734                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5735         } else if (queue_id < 64) {
5736                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5737                 mask &= (1 << (queue_id - 32));
5738                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5739         }
5740         rte_intr_enable(intr_handle);
5741
5742         return 0;
5743 }
5744
5745 static int
5746 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5747 {
5748         uint32_t mask;
5749         struct ixgbe_hw *hw =
5750                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5751         struct ixgbe_interrupt *intr =
5752                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5753
5754         if (queue_id < 16) {
5755                 ixgbe_disable_intr(hw);
5756                 intr->mask &= ~(1 << queue_id);
5757                 ixgbe_enable_intr(dev);
5758         } else if (queue_id < 32) {
5759                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5760                 mask &= ~(1 << queue_id);
5761                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5762         } else if (queue_id < 64) {
5763                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5764                 mask &= ~(1 << (queue_id - 32));
5765                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5766         }
5767
5768         return 0;
5769 }
5770
5771 static void
5772 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5773                      uint8_t queue, uint8_t msix_vector)
5774 {
5775         uint32_t tmp, idx;
5776
5777         if (direction == -1) {
5778                 /* other causes */
5779                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5780                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5781                 tmp &= ~0xFF;
5782                 tmp |= msix_vector;
5783                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5784         } else {
5785                 /* rx or tx cause */
5786                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5787                 idx = ((16 * (queue & 1)) + (8 * direction));
5788                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5789                 tmp &= ~(0xFF << idx);
5790                 tmp |= (msix_vector << idx);
5791                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5792         }
5793 }
5794
5795 /**
5796  * set the IVAR registers, mapping interrupt causes to vectors
5797  * @param hw
5798  *  pointer to ixgbe_hw struct
5799  * @direction
5800  *  0 for Rx, 1 for Tx, -1 for other causes
5801  * @queue
5802  *  queue to map the corresponding interrupt to
5803  * @msix_vector
5804  *  the vector to map to the corresponding queue
5805  */
5806 static void
5807 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5808                    uint8_t queue, uint8_t msix_vector)
5809 {
5810         uint32_t tmp, idx;
5811
5812         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5813         if (hw->mac.type == ixgbe_mac_82598EB) {
5814                 if (direction == -1)
5815                         direction = 0;
5816                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5817                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5818                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5819                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5820                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5821         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5822                         (hw->mac.type == ixgbe_mac_X540) ||
5823                         (hw->mac.type == ixgbe_mac_X550)) {
5824                 if (direction == -1) {
5825                         /* other causes */
5826                         idx = ((queue & 1) * 8);
5827                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5828                         tmp &= ~(0xFF << idx);
5829                         tmp |= (msix_vector << idx);
5830                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5831                 } else {
5832                         /* rx or tx causes */
5833                         idx = ((16 * (queue & 1)) + (8 * direction));
5834                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5835                         tmp &= ~(0xFF << idx);
5836                         tmp |= (msix_vector << idx);
5837                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5838                 }
5839         }
5840 }
5841
5842 static void
5843 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5844 {
5845         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5846         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5847         struct ixgbe_hw *hw =
5848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5849         uint32_t q_idx;
5850         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5851         uint32_t base = IXGBE_MISC_VEC_ID;
5852
5853         /* Configure VF other cause ivar */
5854         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5855
5856         /* won't configure msix register if no mapping is done
5857          * between intr vector and event fd.
5858          */
5859         if (!rte_intr_dp_is_en(intr_handle))
5860                 return;
5861
5862         if (rte_intr_allow_others(intr_handle)) {
5863                 base = IXGBE_RX_VEC_START;
5864                 vector_idx = IXGBE_RX_VEC_START;
5865         }
5866
5867         /* Configure all RX queues of VF */
5868         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5869                 /* Force all queue use vector 0,
5870                  * as IXGBE_VF_MAXMSIVECOTR = 1
5871                  */
5872                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5873                 intr_handle->intr_vec[q_idx] = vector_idx;
5874                 if (vector_idx < base + intr_handle->nb_efd - 1)
5875                         vector_idx++;
5876         }
5877
5878         /* As RX queue setting above show, all queues use the vector 0.
5879          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5880          */
5881         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5882                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5883                         | IXGBE_EITR_CNT_WDIS);
5884 }
5885
5886 /**
5887  * Sets up the hardware to properly generate MSI-X interrupts
5888  * @hw
5889  *  board private structure
5890  */
5891 static void
5892 ixgbe_configure_msix(struct rte_eth_dev *dev)
5893 {
5894         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5895         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5896         struct ixgbe_hw *hw =
5897                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5898         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5899         uint32_t vec = IXGBE_MISC_VEC_ID;
5900         uint32_t mask;
5901         uint32_t gpie;
5902
5903         /* won't configure msix register if no mapping is done
5904          * between intr vector and event fd
5905          * but if misx has been enabled already, need to configure
5906          * auto clean, auto mask and throttling.
5907          */
5908         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5909         if (!rte_intr_dp_is_en(intr_handle) &&
5910             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5911                 return;
5912
5913         if (rte_intr_allow_others(intr_handle))
5914                 vec = base = IXGBE_RX_VEC_START;
5915
5916         /* setup GPIE for MSI-x mode */
5917         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5918         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5919                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5920         /* auto clearing and auto setting corresponding bits in EIMS
5921          * when MSI-X interrupt is triggered
5922          */
5923         if (hw->mac.type == ixgbe_mac_82598EB) {
5924                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5925         } else {
5926                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5927                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5928         }
5929         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5930
5931         /* Populate the IVAR table and set the ITR values to the
5932          * corresponding register.
5933          */
5934         if (rte_intr_dp_is_en(intr_handle)) {
5935                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5936                         queue_id++) {
5937                         /* by default, 1:1 mapping */
5938                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5939                         intr_handle->intr_vec[queue_id] = vec;
5940                         if (vec < base + intr_handle->nb_efd - 1)
5941                                 vec++;
5942                 }
5943
5944                 switch (hw->mac.type) {
5945                 case ixgbe_mac_82598EB:
5946                         ixgbe_set_ivar_map(hw, -1,
5947                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5948                                            IXGBE_MISC_VEC_ID);
5949                         break;
5950                 case ixgbe_mac_82599EB:
5951                 case ixgbe_mac_X540:
5952                 case ixgbe_mac_X550:
5953                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5954                         break;
5955                 default:
5956                         break;
5957                 }
5958         }
5959         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5960                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5961                         | IXGBE_EITR_CNT_WDIS);
5962
5963         /* set up to autoclear timer, and the vectors */
5964         mask = IXGBE_EIMS_ENABLE_MASK;
5965         mask &= ~(IXGBE_EIMS_OTHER |
5966                   IXGBE_EIMS_MAILBOX |
5967                   IXGBE_EIMS_LSC);
5968
5969         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5970 }
5971
5972 int
5973 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5974                            uint16_t queue_idx, uint16_t tx_rate)
5975 {
5976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5977         struct rte_eth_rxmode *rxmode;
5978         uint32_t rf_dec, rf_int;
5979         uint32_t bcnrc_val;
5980         uint16_t link_speed = dev->data->dev_link.link_speed;
5981
5982         if (queue_idx >= hw->mac.max_tx_queues)
5983                 return -EINVAL;
5984
5985         if (tx_rate != 0) {
5986                 /* Calculate the rate factor values to set */
5987                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5988                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5989                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5990
5991                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5992                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5993                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5994                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5995         } else {
5996                 bcnrc_val = 0;
5997         }
5998
5999         rxmode = &dev->data->dev_conf.rxmode;
6000         /*
6001          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6002          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6003          * set as 0x4.
6004          */
6005         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6006             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6007                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6008                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6009         else
6010                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6011                         IXGBE_MMW_SIZE_DEFAULT);
6012
6013         /* Set RTTBCNRC of queue X */
6014         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6015         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6016         IXGBE_WRITE_FLUSH(hw);
6017
6018         return 0;
6019 }
6020
6021 static int
6022 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
6023                      __attribute__((unused)) uint32_t index,
6024                      __attribute__((unused)) uint32_t pool)
6025 {
6026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6027         int diag;
6028
6029         /*
6030          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6031          * operation. Trap this case to avoid exhausting the [very limited]
6032          * set of PF resources used to store VF MAC addresses.
6033          */
6034         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6035                 return -1;
6036         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6037         if (diag != 0)
6038                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6039                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6040                             mac_addr->addr_bytes[0],
6041                             mac_addr->addr_bytes[1],
6042                             mac_addr->addr_bytes[2],
6043                             mac_addr->addr_bytes[3],
6044                             mac_addr->addr_bytes[4],
6045                             mac_addr->addr_bytes[5],
6046                             diag);
6047         return diag;
6048 }
6049
6050 static void
6051 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6052 {
6053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6054         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6055         struct ether_addr *mac_addr;
6056         uint32_t i;
6057         int diag;
6058
6059         /*
6060          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6061          * not support the deletion of a given MAC address.
6062          * Instead, it imposes to delete all MAC addresses, then to add again
6063          * all MAC addresses with the exception of the one to be deleted.
6064          */
6065         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6066
6067         /*
6068          * Add again all MAC addresses, with the exception of the deleted one
6069          * and of the permanent MAC address.
6070          */
6071         for (i = 0, mac_addr = dev->data->mac_addrs;
6072              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6073                 /* Skip the deleted MAC address */
6074                 if (i == index)
6075                         continue;
6076                 /* Skip NULL MAC addresses */
6077                 if (is_zero_ether_addr(mac_addr))
6078                         continue;
6079                 /* Skip the permanent MAC address */
6080                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6081                         continue;
6082                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6083                 if (diag != 0)
6084                         PMD_DRV_LOG(ERR,
6085                                     "Adding again MAC address "
6086                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6087                                     "diag=%d",
6088                                     mac_addr->addr_bytes[0],
6089                                     mac_addr->addr_bytes[1],
6090                                     mac_addr->addr_bytes[2],
6091                                     mac_addr->addr_bytes[3],
6092                                     mac_addr->addr_bytes[4],
6093                                     mac_addr->addr_bytes[5],
6094                                     diag);
6095         }
6096 }
6097
6098 static int
6099 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6100 {
6101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6102
6103         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6104
6105         return 0;
6106 }
6107
6108 int
6109 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6110                         struct rte_eth_syn_filter *filter,
6111                         bool add)
6112 {
6113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6114         struct ixgbe_filter_info *filter_info =
6115                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6116         uint32_t syn_info;
6117         uint32_t synqf;
6118
6119         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6120                 return -EINVAL;
6121
6122         syn_info = filter_info->syn_info;
6123
6124         if (add) {
6125                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6126                         return -EINVAL;
6127                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6128                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6129
6130                 if (filter->hig_pri)
6131                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6132                 else
6133                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6134         } else {
6135                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6136                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6137                         return -ENOENT;
6138                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6139         }
6140
6141         filter_info->syn_info = synqf;
6142         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6143         IXGBE_WRITE_FLUSH(hw);
6144         return 0;
6145 }
6146
6147 static int
6148 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6149                         struct rte_eth_syn_filter *filter)
6150 {
6151         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6152         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6153
6154         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6155                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6156                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6157                 return 0;
6158         }
6159         return -ENOENT;
6160 }
6161
6162 static int
6163 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6164                         enum rte_filter_op filter_op,
6165                         void *arg)
6166 {
6167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6168         int ret;
6169
6170         MAC_TYPE_FILTER_SUP(hw->mac.type);
6171
6172         if (filter_op == RTE_ETH_FILTER_NOP)
6173                 return 0;
6174
6175         if (arg == NULL) {
6176                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6177                             filter_op);
6178                 return -EINVAL;
6179         }
6180
6181         switch (filter_op) {
6182         case RTE_ETH_FILTER_ADD:
6183                 ret = ixgbe_syn_filter_set(dev,
6184                                 (struct rte_eth_syn_filter *)arg,
6185                                 TRUE);
6186                 break;
6187         case RTE_ETH_FILTER_DELETE:
6188                 ret = ixgbe_syn_filter_set(dev,
6189                                 (struct rte_eth_syn_filter *)arg,
6190                                 FALSE);
6191                 break;
6192         case RTE_ETH_FILTER_GET:
6193                 ret = ixgbe_syn_filter_get(dev,
6194                                 (struct rte_eth_syn_filter *)arg);
6195                 break;
6196         default:
6197                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6198                 ret = -EINVAL;
6199                 break;
6200         }
6201
6202         return ret;
6203 }
6204
6205
6206 static inline enum ixgbe_5tuple_protocol
6207 convert_protocol_type(uint8_t protocol_value)
6208 {
6209         if (protocol_value == IPPROTO_TCP)
6210                 return IXGBE_FILTER_PROTOCOL_TCP;
6211         else if (protocol_value == IPPROTO_UDP)
6212                 return IXGBE_FILTER_PROTOCOL_UDP;
6213         else if (protocol_value == IPPROTO_SCTP)
6214                 return IXGBE_FILTER_PROTOCOL_SCTP;
6215         else
6216                 return IXGBE_FILTER_PROTOCOL_NONE;
6217 }
6218
6219 /* inject a 5-tuple filter to HW */
6220 static inline void
6221 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6222                            struct ixgbe_5tuple_filter *filter)
6223 {
6224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6225         int i;
6226         uint32_t ftqf, sdpqf;
6227         uint32_t l34timir = 0;
6228         uint8_t mask = 0xff;
6229
6230         i = filter->index;
6231
6232         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6233                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6234         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6235
6236         ftqf = (uint32_t)(filter->filter_info.proto &
6237                 IXGBE_FTQF_PROTOCOL_MASK);
6238         ftqf |= (uint32_t)((filter->filter_info.priority &
6239                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6240         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6241                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6242         if (filter->filter_info.dst_ip_mask == 0)
6243                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6244         if (filter->filter_info.src_port_mask == 0)
6245                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6246         if (filter->filter_info.dst_port_mask == 0)
6247                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6248         if (filter->filter_info.proto_mask == 0)
6249                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6250         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6251         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6252         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6253
6254         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6255         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6256         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6257         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6258
6259         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6260         l34timir |= (uint32_t)(filter->queue <<
6261                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6262         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6263 }
6264
6265 /*
6266  * add a 5tuple filter
6267  *
6268  * @param
6269  * dev: Pointer to struct rte_eth_dev.
6270  * index: the index the filter allocates.
6271  * filter: ponter to the filter that will be added.
6272  * rx_queue: the queue id the filter assigned to.
6273  *
6274  * @return
6275  *    - On success, zero.
6276  *    - On failure, a negative value.
6277  */
6278 static int
6279 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6280                         struct ixgbe_5tuple_filter *filter)
6281 {
6282         struct ixgbe_filter_info *filter_info =
6283                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6284         int i, idx, shift;
6285
6286         /*
6287          * look for an unused 5tuple filter index,
6288          * and insert the filter to list.
6289          */
6290         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6291                 idx = i / (sizeof(uint32_t) * NBBY);
6292                 shift = i % (sizeof(uint32_t) * NBBY);
6293                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6294                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6295                         filter->index = i;
6296                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6297                                           filter,
6298                                           entries);
6299                         break;
6300                 }
6301         }
6302         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6303                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6304                 return -ENOSYS;
6305         }
6306
6307         ixgbe_inject_5tuple_filter(dev, filter);
6308
6309         return 0;
6310 }
6311
6312 /*
6313  * remove a 5tuple filter
6314  *
6315  * @param
6316  * dev: Pointer to struct rte_eth_dev.
6317  * filter: the pointer of the filter will be removed.
6318  */
6319 static void
6320 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6321                         struct ixgbe_5tuple_filter *filter)
6322 {
6323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6324         struct ixgbe_filter_info *filter_info =
6325                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6326         uint16_t index = filter->index;
6327
6328         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6329                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6330         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6331         rte_free(filter);
6332
6333         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6334         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6335         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6336         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6337         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6338 }
6339
6340 static int
6341 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6342 {
6343         struct ixgbe_hw *hw;
6344         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6345         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6346
6347         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6348
6349         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6350                 return -EINVAL;
6351
6352         /* refuse mtu that requires the support of scattered packets when this
6353          * feature has not been enabled before.
6354          */
6355         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6356             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6357              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6358                 return -EINVAL;
6359
6360         /*
6361          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6362          * request of the version 2.0 of the mailbox API.
6363          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6364          * of the mailbox API.
6365          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6366          * prior to 3.11.33 which contains the following change:
6367          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6368          */
6369         ixgbevf_rlpml_set_vf(hw, max_frame);
6370
6371         /* update max frame size */
6372         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6373         return 0;
6374 }
6375
6376 static inline struct ixgbe_5tuple_filter *
6377 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6378                         struct ixgbe_5tuple_filter_info *key)
6379 {
6380         struct ixgbe_5tuple_filter *it;
6381
6382         TAILQ_FOREACH(it, filter_list, entries) {
6383                 if (memcmp(key, &it->filter_info,
6384                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6385                         return it;
6386                 }
6387         }
6388         return NULL;
6389 }
6390
6391 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6392 static inline int
6393 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6394                         struct ixgbe_5tuple_filter_info *filter_info)
6395 {
6396         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6397                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6398                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6399                 return -EINVAL;
6400
6401         switch (filter->dst_ip_mask) {
6402         case UINT32_MAX:
6403                 filter_info->dst_ip_mask = 0;
6404                 filter_info->dst_ip = filter->dst_ip;
6405                 break;
6406         case 0:
6407                 filter_info->dst_ip_mask = 1;
6408                 break;
6409         default:
6410                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6411                 return -EINVAL;
6412         }
6413
6414         switch (filter->src_ip_mask) {
6415         case UINT32_MAX:
6416                 filter_info->src_ip_mask = 0;
6417                 filter_info->src_ip = filter->src_ip;
6418                 break;
6419         case 0:
6420                 filter_info->src_ip_mask = 1;
6421                 break;
6422         default:
6423                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6424                 return -EINVAL;
6425         }
6426
6427         switch (filter->dst_port_mask) {
6428         case UINT16_MAX:
6429                 filter_info->dst_port_mask = 0;
6430                 filter_info->dst_port = filter->dst_port;
6431                 break;
6432         case 0:
6433                 filter_info->dst_port_mask = 1;
6434                 break;
6435         default:
6436                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6437                 return -EINVAL;
6438         }
6439
6440         switch (filter->src_port_mask) {
6441         case UINT16_MAX:
6442                 filter_info->src_port_mask = 0;
6443                 filter_info->src_port = filter->src_port;
6444                 break;
6445         case 0:
6446                 filter_info->src_port_mask = 1;
6447                 break;
6448         default:
6449                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6450                 return -EINVAL;
6451         }
6452
6453         switch (filter->proto_mask) {
6454         case UINT8_MAX:
6455                 filter_info->proto_mask = 0;
6456                 filter_info->proto =
6457                         convert_protocol_type(filter->proto);
6458                 break;
6459         case 0:
6460                 filter_info->proto_mask = 1;
6461                 break;
6462         default:
6463                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6464                 return -EINVAL;
6465         }
6466
6467         filter_info->priority = (uint8_t)filter->priority;
6468         return 0;
6469 }
6470
6471 /*
6472  * add or delete a ntuple filter
6473  *
6474  * @param
6475  * dev: Pointer to struct rte_eth_dev.
6476  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6477  * add: if true, add filter, if false, remove filter
6478  *
6479  * @return
6480  *    - On success, zero.
6481  *    - On failure, a negative value.
6482  */
6483 int
6484 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6485                         struct rte_eth_ntuple_filter *ntuple_filter,
6486                         bool add)
6487 {
6488         struct ixgbe_filter_info *filter_info =
6489                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6490         struct ixgbe_5tuple_filter_info filter_5tuple;
6491         struct ixgbe_5tuple_filter *filter;
6492         int ret;
6493
6494         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6495                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6496                 return -EINVAL;
6497         }
6498
6499         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6500         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6501         if (ret < 0)
6502                 return ret;
6503
6504         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6505                                          &filter_5tuple);
6506         if (filter != NULL && add) {
6507                 PMD_DRV_LOG(ERR, "filter exists.");
6508                 return -EEXIST;
6509         }
6510         if (filter == NULL && !add) {
6511                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6512                 return -ENOENT;
6513         }
6514
6515         if (add) {
6516                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6517                                 sizeof(struct ixgbe_5tuple_filter), 0);
6518                 if (filter == NULL)
6519                         return -ENOMEM;
6520                 rte_memcpy(&filter->filter_info,
6521                                  &filter_5tuple,
6522                                  sizeof(struct ixgbe_5tuple_filter_info));
6523                 filter->queue = ntuple_filter->queue;
6524                 ret = ixgbe_add_5tuple_filter(dev, filter);
6525                 if (ret < 0) {
6526                         rte_free(filter);
6527                         return ret;
6528                 }
6529         } else
6530                 ixgbe_remove_5tuple_filter(dev, filter);
6531
6532         return 0;
6533 }
6534
6535 /*
6536  * get a ntuple filter
6537  *
6538  * @param
6539  * dev: Pointer to struct rte_eth_dev.
6540  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6541  *
6542  * @return
6543  *    - On success, zero.
6544  *    - On failure, a negative value.
6545  */
6546 static int
6547 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6548                         struct rte_eth_ntuple_filter *ntuple_filter)
6549 {
6550         struct ixgbe_filter_info *filter_info =
6551                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6552         struct ixgbe_5tuple_filter_info filter_5tuple;
6553         struct ixgbe_5tuple_filter *filter;
6554         int ret;
6555
6556         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6557                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6558                 return -EINVAL;
6559         }
6560
6561         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6562         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6563         if (ret < 0)
6564                 return ret;
6565
6566         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6567                                          &filter_5tuple);
6568         if (filter == NULL) {
6569                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6570                 return -ENOENT;
6571         }
6572         ntuple_filter->queue = filter->queue;
6573         return 0;
6574 }
6575
6576 /*
6577  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6578  * @dev: pointer to rte_eth_dev structure
6579  * @filter_op:operation will be taken.
6580  * @arg: a pointer to specific structure corresponding to the filter_op
6581  *
6582  * @return
6583  *    - On success, zero.
6584  *    - On failure, a negative value.
6585  */
6586 static int
6587 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6588                                 enum rte_filter_op filter_op,
6589                                 void *arg)
6590 {
6591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6592         int ret;
6593
6594         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6595
6596         if (filter_op == RTE_ETH_FILTER_NOP)
6597                 return 0;
6598
6599         if (arg == NULL) {
6600                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6601                             filter_op);
6602                 return -EINVAL;
6603         }
6604
6605         switch (filter_op) {
6606         case RTE_ETH_FILTER_ADD:
6607                 ret = ixgbe_add_del_ntuple_filter(dev,
6608                         (struct rte_eth_ntuple_filter *)arg,
6609                         TRUE);
6610                 break;
6611         case RTE_ETH_FILTER_DELETE:
6612                 ret = ixgbe_add_del_ntuple_filter(dev,
6613                         (struct rte_eth_ntuple_filter *)arg,
6614                         FALSE);
6615                 break;
6616         case RTE_ETH_FILTER_GET:
6617                 ret = ixgbe_get_ntuple_filter(dev,
6618                         (struct rte_eth_ntuple_filter *)arg);
6619                 break;
6620         default:
6621                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6622                 ret = -EINVAL;
6623                 break;
6624         }
6625         return ret;
6626 }
6627
6628 int
6629 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6630                         struct rte_eth_ethertype_filter *filter,
6631                         bool add)
6632 {
6633         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6634         struct ixgbe_filter_info *filter_info =
6635                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6636         uint32_t etqf = 0;
6637         uint32_t etqs = 0;
6638         int ret;
6639         struct ixgbe_ethertype_filter ethertype_filter;
6640
6641         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6642                 return -EINVAL;
6643
6644         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6645                 filter->ether_type == ETHER_TYPE_IPv6) {
6646                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6647                         " ethertype filter.", filter->ether_type);
6648                 return -EINVAL;
6649         }
6650
6651         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6652                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6653                 return -EINVAL;
6654         }
6655         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6656                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6657                 return -EINVAL;
6658         }
6659
6660         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6661         if (ret >= 0 && add) {
6662                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6663                             filter->ether_type);
6664                 return -EEXIST;
6665         }
6666         if (ret < 0 && !add) {
6667                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6668                             filter->ether_type);
6669                 return -ENOENT;
6670         }
6671
6672         if (add) {
6673                 etqf = IXGBE_ETQF_FILTER_EN;
6674                 etqf |= (uint32_t)filter->ether_type;
6675                 etqs |= (uint32_t)((filter->queue <<
6676                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6677                                     IXGBE_ETQS_RX_QUEUE);
6678                 etqs |= IXGBE_ETQS_QUEUE_EN;
6679
6680                 ethertype_filter.ethertype = filter->ether_type;
6681                 ethertype_filter.etqf = etqf;
6682                 ethertype_filter.etqs = etqs;
6683                 ethertype_filter.conf = FALSE;
6684                 ret = ixgbe_ethertype_filter_insert(filter_info,
6685                                                     &ethertype_filter);
6686                 if (ret < 0) {
6687                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6688                         return -ENOSPC;
6689                 }
6690         } else {
6691                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6692                 if (ret < 0)
6693                         return -ENOSYS;
6694         }
6695         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6696         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6697         IXGBE_WRITE_FLUSH(hw);
6698
6699         return 0;
6700 }
6701
6702 static int
6703 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6704                         struct rte_eth_ethertype_filter *filter)
6705 {
6706         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6707         struct ixgbe_filter_info *filter_info =
6708                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6709         uint32_t etqf, etqs;
6710         int ret;
6711
6712         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6713         if (ret < 0) {
6714                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6715                             filter->ether_type);
6716                 return -ENOENT;
6717         }
6718
6719         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6720         if (etqf & IXGBE_ETQF_FILTER_EN) {
6721                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6722                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6723                 filter->flags = 0;
6724                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6725                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6726                 return 0;
6727         }
6728         return -ENOENT;
6729 }
6730
6731 /*
6732  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6733  * @dev: pointer to rte_eth_dev structure
6734  * @filter_op:operation will be taken.
6735  * @arg: a pointer to specific structure corresponding to the filter_op
6736  */
6737 static int
6738 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6739                                 enum rte_filter_op filter_op,
6740                                 void *arg)
6741 {
6742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6743         int ret;
6744
6745         MAC_TYPE_FILTER_SUP(hw->mac.type);
6746
6747         if (filter_op == RTE_ETH_FILTER_NOP)
6748                 return 0;
6749
6750         if (arg == NULL) {
6751                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6752                             filter_op);
6753                 return -EINVAL;
6754         }
6755
6756         switch (filter_op) {
6757         case RTE_ETH_FILTER_ADD:
6758                 ret = ixgbe_add_del_ethertype_filter(dev,
6759                         (struct rte_eth_ethertype_filter *)arg,
6760                         TRUE);
6761                 break;
6762         case RTE_ETH_FILTER_DELETE:
6763                 ret = ixgbe_add_del_ethertype_filter(dev,
6764                         (struct rte_eth_ethertype_filter *)arg,
6765                         FALSE);
6766                 break;
6767         case RTE_ETH_FILTER_GET:
6768                 ret = ixgbe_get_ethertype_filter(dev,
6769                         (struct rte_eth_ethertype_filter *)arg);
6770                 break;
6771         default:
6772                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6773                 ret = -EINVAL;
6774                 break;
6775         }
6776         return ret;
6777 }
6778
6779 static int
6780 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6781                      enum rte_filter_type filter_type,
6782                      enum rte_filter_op filter_op,
6783                      void *arg)
6784 {
6785         int ret = 0;
6786
6787         switch (filter_type) {
6788         case RTE_ETH_FILTER_NTUPLE:
6789                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6790                 break;
6791         case RTE_ETH_FILTER_ETHERTYPE:
6792                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6793                 break;
6794         case RTE_ETH_FILTER_SYN:
6795                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6796                 break;
6797         case RTE_ETH_FILTER_FDIR:
6798                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6799                 break;
6800         case RTE_ETH_FILTER_L2_TUNNEL:
6801                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6802                 break;
6803         case RTE_ETH_FILTER_GENERIC:
6804                 if (filter_op != RTE_ETH_FILTER_GET)
6805                         return -EINVAL;
6806                 *(const void **)arg = &ixgbe_flow_ops;
6807                 break;
6808         default:
6809                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6810                                                         filter_type);
6811                 ret = -EINVAL;
6812                 break;
6813         }
6814
6815         return ret;
6816 }
6817
6818 static u8 *
6819 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6820                         u8 **mc_addr_ptr, u32 *vmdq)
6821 {
6822         u8 *mc_addr;
6823
6824         *vmdq = 0;
6825         mc_addr = *mc_addr_ptr;
6826         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6827         return mc_addr;
6828 }
6829
6830 static int
6831 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6832                           struct ether_addr *mc_addr_set,
6833                           uint32_t nb_mc_addr)
6834 {
6835         struct ixgbe_hw *hw;
6836         u8 *mc_addr_list;
6837
6838         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6839         mc_addr_list = (u8 *)mc_addr_set;
6840         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6841                                          ixgbe_dev_addr_list_itr, TRUE);
6842 }
6843
6844 static uint64_t
6845 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6846 {
6847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6848         uint64_t systime_cycles;
6849
6850         switch (hw->mac.type) {
6851         case ixgbe_mac_X550:
6852         case ixgbe_mac_X550EM_x:
6853         case ixgbe_mac_X550EM_a:
6854                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6855                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6856                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6857                                 * NSEC_PER_SEC;
6858                 break;
6859         default:
6860                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6861                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6862                                 << 32;
6863         }
6864
6865         return systime_cycles;
6866 }
6867
6868 static uint64_t
6869 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6870 {
6871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6872         uint64_t rx_tstamp_cycles;
6873
6874         switch (hw->mac.type) {
6875         case ixgbe_mac_X550:
6876         case ixgbe_mac_X550EM_x:
6877         case ixgbe_mac_X550EM_a:
6878                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6879                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6880                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6881                                 * NSEC_PER_SEC;
6882                 break;
6883         default:
6884                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6885                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6886                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6887                                 << 32;
6888         }
6889
6890         return rx_tstamp_cycles;
6891 }
6892
6893 static uint64_t
6894 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6895 {
6896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897         uint64_t tx_tstamp_cycles;
6898
6899         switch (hw->mac.type) {
6900         case ixgbe_mac_X550:
6901         case ixgbe_mac_X550EM_x:
6902         case ixgbe_mac_X550EM_a:
6903                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6904                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6905                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6906                                 * NSEC_PER_SEC;
6907                 break;
6908         default:
6909                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6910                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6911                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6912                                 << 32;
6913         }
6914
6915         return tx_tstamp_cycles;
6916 }
6917
6918 static void
6919 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6920 {
6921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6922         struct ixgbe_adapter *adapter =
6923                 (struct ixgbe_adapter *)dev->data->dev_private;
6924         struct rte_eth_link link;
6925         uint32_t incval = 0;
6926         uint32_t shift = 0;
6927
6928         /* Get current link speed. */
6929         ixgbe_dev_link_update(dev, 1);
6930         rte_eth_linkstatus_get(dev, &link);
6931
6932         switch (link.link_speed) {
6933         case ETH_SPEED_NUM_100M:
6934                 incval = IXGBE_INCVAL_100;
6935                 shift = IXGBE_INCVAL_SHIFT_100;
6936                 break;
6937         case ETH_SPEED_NUM_1G:
6938                 incval = IXGBE_INCVAL_1GB;
6939                 shift = IXGBE_INCVAL_SHIFT_1GB;
6940                 break;
6941         case ETH_SPEED_NUM_10G:
6942         default:
6943                 incval = IXGBE_INCVAL_10GB;
6944                 shift = IXGBE_INCVAL_SHIFT_10GB;
6945                 break;
6946         }
6947
6948         switch (hw->mac.type) {
6949         case ixgbe_mac_X550:
6950         case ixgbe_mac_X550EM_x:
6951         case ixgbe_mac_X550EM_a:
6952                 /* Independent of link speed. */
6953                 incval = 1;
6954                 /* Cycles read will be interpreted as ns. */
6955                 shift = 0;
6956                 /* Fall-through */
6957         case ixgbe_mac_X540:
6958                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6959                 break;
6960         case ixgbe_mac_82599EB:
6961                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6962                 shift -= IXGBE_INCVAL_SHIFT_82599;
6963                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6964                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6965                 break;
6966         default:
6967                 /* Not supported. */
6968                 return;
6969         }
6970
6971         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6972         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6973         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6974
6975         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6976         adapter->systime_tc.cc_shift = shift;
6977         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6978
6979         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6980         adapter->rx_tstamp_tc.cc_shift = shift;
6981         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6982
6983         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6984         adapter->tx_tstamp_tc.cc_shift = shift;
6985         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6986 }
6987
6988 static int
6989 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6990 {
6991         struct ixgbe_adapter *adapter =
6992                         (struct ixgbe_adapter *)dev->data->dev_private;
6993
6994         adapter->systime_tc.nsec += delta;
6995         adapter->rx_tstamp_tc.nsec += delta;
6996         adapter->tx_tstamp_tc.nsec += delta;
6997
6998         return 0;
6999 }
7000
7001 static int
7002 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7003 {
7004         uint64_t ns;
7005         struct ixgbe_adapter *adapter =
7006                         (struct ixgbe_adapter *)dev->data->dev_private;
7007
7008         ns = rte_timespec_to_ns(ts);
7009         /* Set the timecounters to a new value. */
7010         adapter->systime_tc.nsec = ns;
7011         adapter->rx_tstamp_tc.nsec = ns;
7012         adapter->tx_tstamp_tc.nsec = ns;
7013
7014         return 0;
7015 }
7016
7017 static int
7018 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7019 {
7020         uint64_t ns, systime_cycles;
7021         struct ixgbe_adapter *adapter =
7022                         (struct ixgbe_adapter *)dev->data->dev_private;
7023
7024         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7025         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7026         *ts = rte_ns_to_timespec(ns);
7027
7028         return 0;
7029 }
7030
7031 static int
7032 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7033 {
7034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7035         uint32_t tsync_ctl;
7036         uint32_t tsauxc;
7037
7038         /* Stop the timesync system time. */
7039         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7040         /* Reset the timesync system time value. */
7041         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7042         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7043
7044         /* Enable system time for platforms where it isn't on by default. */
7045         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7046         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7047         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7048
7049         ixgbe_start_timecounters(dev);
7050
7051         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7052         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7053                         (ETHER_TYPE_1588 |
7054                          IXGBE_ETQF_FILTER_EN |
7055                          IXGBE_ETQF_1588));
7056
7057         /* Enable timestamping of received PTP packets. */
7058         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7059         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7060         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7061
7062         /* Enable timestamping of transmitted PTP packets. */
7063         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7064         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7065         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7066
7067         IXGBE_WRITE_FLUSH(hw);
7068
7069         return 0;
7070 }
7071
7072 static int
7073 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7074 {
7075         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7076         uint32_t tsync_ctl;
7077
7078         /* Disable timestamping of transmitted PTP packets. */
7079         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7080         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7081         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7082
7083         /* Disable timestamping of received PTP packets. */
7084         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7085         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7086         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7087
7088         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7089         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7090
7091         /* Stop incrementating the System Time registers. */
7092         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7093
7094         return 0;
7095 }
7096
7097 static int
7098 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7099                                  struct timespec *timestamp,
7100                                  uint32_t flags __rte_unused)
7101 {
7102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7103         struct ixgbe_adapter *adapter =
7104                 (struct ixgbe_adapter *)dev->data->dev_private;
7105         uint32_t tsync_rxctl;
7106         uint64_t rx_tstamp_cycles;
7107         uint64_t ns;
7108
7109         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7110         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7111                 return -EINVAL;
7112
7113         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7114         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7115         *timestamp = rte_ns_to_timespec(ns);
7116
7117         return  0;
7118 }
7119
7120 static int
7121 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7122                                  struct timespec *timestamp)
7123 {
7124         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7125         struct ixgbe_adapter *adapter =
7126                 (struct ixgbe_adapter *)dev->data->dev_private;
7127         uint32_t tsync_txctl;
7128         uint64_t tx_tstamp_cycles;
7129         uint64_t ns;
7130
7131         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7132         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7133                 return -EINVAL;
7134
7135         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7136         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7137         *timestamp = rte_ns_to_timespec(ns);
7138
7139         return 0;
7140 }
7141
7142 static int
7143 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7144 {
7145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7146         int count = 0;
7147         int g_ind = 0;
7148         const struct reg_info *reg_group;
7149         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7150                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7151
7152         while ((reg_group = reg_set[g_ind++]))
7153                 count += ixgbe_regs_group_count(reg_group);
7154
7155         return count;
7156 }
7157
7158 static int
7159 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7160 {
7161         int count = 0;
7162         int g_ind = 0;
7163         const struct reg_info *reg_group;
7164
7165         while ((reg_group = ixgbevf_regs[g_ind++]))
7166                 count += ixgbe_regs_group_count(reg_group);
7167
7168         return count;
7169 }
7170
7171 static int
7172 ixgbe_get_regs(struct rte_eth_dev *dev,
7173               struct rte_dev_reg_info *regs)
7174 {
7175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7176         uint32_t *data = regs->data;
7177         int g_ind = 0;
7178         int count = 0;
7179         const struct reg_info *reg_group;
7180         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7181                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7182
7183         if (data == NULL) {
7184                 regs->length = ixgbe_get_reg_length(dev);
7185                 regs->width = sizeof(uint32_t);
7186                 return 0;
7187         }
7188
7189         /* Support only full register dump */
7190         if ((regs->length == 0) ||
7191             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7192                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7193                         hw->device_id;
7194                 while ((reg_group = reg_set[g_ind++]))
7195                         count += ixgbe_read_regs_group(dev, &data[count],
7196                                 reg_group);
7197                 return 0;
7198         }
7199
7200         return -ENOTSUP;
7201 }
7202
7203 static int
7204 ixgbevf_get_regs(struct rte_eth_dev *dev,
7205                 struct rte_dev_reg_info *regs)
7206 {
7207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7208         uint32_t *data = regs->data;
7209         int g_ind = 0;
7210         int count = 0;
7211         const struct reg_info *reg_group;
7212
7213         if (data == NULL) {
7214                 regs->length = ixgbevf_get_reg_length(dev);
7215                 regs->width = sizeof(uint32_t);
7216                 return 0;
7217         }
7218
7219         /* Support only full register dump */
7220         if ((regs->length == 0) ||
7221             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7222                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7223                         hw->device_id;
7224                 while ((reg_group = ixgbevf_regs[g_ind++]))
7225                         count += ixgbe_read_regs_group(dev, &data[count],
7226                                                       reg_group);
7227                 return 0;
7228         }
7229
7230         return -ENOTSUP;
7231 }
7232
7233 static int
7234 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7235 {
7236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7237
7238         /* Return unit is byte count */
7239         return hw->eeprom.word_size * 2;
7240 }
7241
7242 static int
7243 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7244                 struct rte_dev_eeprom_info *in_eeprom)
7245 {
7246         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7247         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7248         uint16_t *data = in_eeprom->data;
7249         int first, length;
7250
7251         first = in_eeprom->offset >> 1;
7252         length = in_eeprom->length >> 1;
7253         if ((first > hw->eeprom.word_size) ||
7254             ((first + length) > hw->eeprom.word_size))
7255                 return -EINVAL;
7256
7257         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7258
7259         return eeprom->ops.read_buffer(hw, first, length, data);
7260 }
7261
7262 static int
7263 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7264                 struct rte_dev_eeprom_info *in_eeprom)
7265 {
7266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7267         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7268         uint16_t *data = in_eeprom->data;
7269         int first, length;
7270
7271         first = in_eeprom->offset >> 1;
7272         length = in_eeprom->length >> 1;
7273         if ((first > hw->eeprom.word_size) ||
7274             ((first + length) > hw->eeprom.word_size))
7275                 return -EINVAL;
7276
7277         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7278
7279         return eeprom->ops.write_buffer(hw,  first, length, data);
7280 }
7281
7282 static int
7283 ixgbe_get_module_info(struct rte_eth_dev *dev,
7284                       struct rte_eth_dev_module_info *modinfo)
7285 {
7286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7287         uint32_t status;
7288         uint8_t sff8472_rev, addr_mode;
7289         bool page_swap = false;
7290
7291         /* Check whether we support SFF-8472 or not */
7292         status = hw->phy.ops.read_i2c_eeprom(hw,
7293                                              IXGBE_SFF_SFF_8472_COMP,
7294                                              &sff8472_rev);
7295         if (status != 0)
7296                 return -EIO;
7297
7298         /* addressing mode is not supported */
7299         status = hw->phy.ops.read_i2c_eeprom(hw,
7300                                              IXGBE_SFF_SFF_8472_SWAP,
7301                                              &addr_mode);
7302         if (status != 0)
7303                 return -EIO;
7304
7305         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7306                 PMD_DRV_LOG(ERR,
7307                             "Address change required to access page 0xA2, "
7308                             "but not supported. Please report the module "
7309                             "type to the driver maintainers.");
7310                 page_swap = true;
7311         }
7312
7313         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7314                 /* We have a SFP, but it does not support SFF-8472 */
7315                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7316                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7317         } else {
7318                 /* We have a SFP which supports a revision of SFF-8472. */
7319                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7320                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7321         }
7322
7323         return 0;
7324 }
7325
7326 static int
7327 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7328                         struct rte_dev_eeprom_info *info)
7329 {
7330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7331         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7332         uint8_t databyte = 0xFF;
7333         uint8_t *data = info->data;
7334         uint32_t i = 0;
7335
7336         if (info->length == 0)
7337                 return -EINVAL;
7338
7339         for (i = info->offset; i < info->offset + info->length; i++) {
7340                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7341                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7342                 else
7343                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7344
7345                 if (status != 0)
7346                         return -EIO;
7347
7348                 data[i - info->offset] = databyte;
7349         }
7350
7351         return 0;
7352 }
7353
7354 uint16_t
7355 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7356         switch (mac_type) {
7357         case ixgbe_mac_X550:
7358         case ixgbe_mac_X550EM_x:
7359         case ixgbe_mac_X550EM_a:
7360                 return ETH_RSS_RETA_SIZE_512;
7361         case ixgbe_mac_X550_vf:
7362         case ixgbe_mac_X550EM_x_vf:
7363         case ixgbe_mac_X550EM_a_vf:
7364                 return ETH_RSS_RETA_SIZE_64;
7365         default:
7366                 return ETH_RSS_RETA_SIZE_128;
7367         }
7368 }
7369
7370 uint32_t
7371 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7372         switch (mac_type) {
7373         case ixgbe_mac_X550:
7374         case ixgbe_mac_X550EM_x:
7375         case ixgbe_mac_X550EM_a:
7376                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7377                         return IXGBE_RETA(reta_idx >> 2);
7378                 else
7379                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7380         case ixgbe_mac_X550_vf:
7381         case ixgbe_mac_X550EM_x_vf:
7382         case ixgbe_mac_X550EM_a_vf:
7383                 return IXGBE_VFRETA(reta_idx >> 2);
7384         default:
7385                 return IXGBE_RETA(reta_idx >> 2);
7386         }
7387 }
7388
7389 uint32_t
7390 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7391         switch (mac_type) {
7392         case ixgbe_mac_X550_vf:
7393         case ixgbe_mac_X550EM_x_vf:
7394         case ixgbe_mac_X550EM_a_vf:
7395                 return IXGBE_VFMRQC;
7396         default:
7397                 return IXGBE_MRQC;
7398         }
7399 }
7400
7401 uint32_t
7402 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7403         switch (mac_type) {
7404         case ixgbe_mac_X550_vf:
7405         case ixgbe_mac_X550EM_x_vf:
7406         case ixgbe_mac_X550EM_a_vf:
7407                 return IXGBE_VFRSSRK(i);
7408         default:
7409                 return IXGBE_RSSRK(i);
7410         }
7411 }
7412
7413 bool
7414 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7415         switch (mac_type) {
7416         case ixgbe_mac_82599_vf:
7417         case ixgbe_mac_X540_vf:
7418                 return 0;
7419         default:
7420                 return 1;
7421         }
7422 }
7423
7424 static int
7425 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7426                         struct rte_eth_dcb_info *dcb_info)
7427 {
7428         struct ixgbe_dcb_config *dcb_config =
7429                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7430         struct ixgbe_dcb_tc_config *tc;
7431         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7432         uint8_t nb_tcs;
7433         uint8_t i, j;
7434
7435         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7436                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7437         else
7438                 dcb_info->nb_tcs = 1;
7439
7440         tc_queue = &dcb_info->tc_queue;
7441         nb_tcs = dcb_info->nb_tcs;
7442
7443         if (dcb_config->vt_mode) { /* vt is enabled*/
7444                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7445                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7446                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7447                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7448                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7449                         for (j = 0; j < nb_tcs; j++) {
7450                                 tc_queue->tc_rxq[0][j].base = j;
7451                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7452                                 tc_queue->tc_txq[0][j].base = j;
7453                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7454                         }
7455                 } else {
7456                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7457                                 for (j = 0; j < nb_tcs; j++) {
7458                                         tc_queue->tc_rxq[i][j].base =
7459                                                 i * nb_tcs + j;
7460                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7461                                         tc_queue->tc_txq[i][j].base =
7462                                                 i * nb_tcs + j;
7463                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7464                                 }
7465                         }
7466                 }
7467         } else { /* vt is disabled*/
7468                 struct rte_eth_dcb_rx_conf *rx_conf =
7469                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7470                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7471                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7472                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7473                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7474                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7475                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7476                         }
7477                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7478                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7479                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7480                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7481                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7482                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7483                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7484                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7485                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7486                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7487                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7488                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7489                         }
7490                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7491                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7492                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7493                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7494                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7495                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7496                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7497                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7498                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7499                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7500                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7501                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7502                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7503                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7504                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7505                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7506                 }
7507         }
7508         for (i = 0; i < dcb_info->nb_tcs; i++) {
7509                 tc = &dcb_config->tc_config[i];
7510                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7511         }
7512         return 0;
7513 }
7514
7515 /* Update e-tag ether type */
7516 static int
7517 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7518                             uint16_t ether_type)
7519 {
7520         uint32_t etag_etype;
7521
7522         if (hw->mac.type != ixgbe_mac_X550 &&
7523             hw->mac.type != ixgbe_mac_X550EM_x &&
7524             hw->mac.type != ixgbe_mac_X550EM_a) {
7525                 return -ENOTSUP;
7526         }
7527
7528         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7529         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7530         etag_etype |= ether_type;
7531         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7532         IXGBE_WRITE_FLUSH(hw);
7533
7534         return 0;
7535 }
7536
7537 /* Config l2 tunnel ether type */
7538 static int
7539 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7540                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7541 {
7542         int ret = 0;
7543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7544         struct ixgbe_l2_tn_info *l2_tn_info =
7545                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7546
7547         if (l2_tunnel == NULL)
7548                 return -EINVAL;
7549
7550         switch (l2_tunnel->l2_tunnel_type) {
7551         case RTE_L2_TUNNEL_TYPE_E_TAG:
7552                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7553                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7554                 break;
7555         default:
7556                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7557                 ret = -EINVAL;
7558                 break;
7559         }
7560
7561         return ret;
7562 }
7563
7564 /* Enable e-tag tunnel */
7565 static int
7566 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7567 {
7568         uint32_t etag_etype;
7569
7570         if (hw->mac.type != ixgbe_mac_X550 &&
7571             hw->mac.type != ixgbe_mac_X550EM_x &&
7572             hw->mac.type != ixgbe_mac_X550EM_a) {
7573                 return -ENOTSUP;
7574         }
7575
7576         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7577         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7578         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7579         IXGBE_WRITE_FLUSH(hw);
7580
7581         return 0;
7582 }
7583
7584 /* Enable l2 tunnel */
7585 static int
7586 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7587                            enum rte_eth_tunnel_type l2_tunnel_type)
7588 {
7589         int ret = 0;
7590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7591         struct ixgbe_l2_tn_info *l2_tn_info =
7592                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7593
7594         switch (l2_tunnel_type) {
7595         case RTE_L2_TUNNEL_TYPE_E_TAG:
7596                 l2_tn_info->e_tag_en = TRUE;
7597                 ret = ixgbe_e_tag_enable(hw);
7598                 break;
7599         default:
7600                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7601                 ret = -EINVAL;
7602                 break;
7603         }
7604
7605         return ret;
7606 }
7607
7608 /* Disable e-tag tunnel */
7609 static int
7610 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7611 {
7612         uint32_t etag_etype;
7613
7614         if (hw->mac.type != ixgbe_mac_X550 &&
7615             hw->mac.type != ixgbe_mac_X550EM_x &&
7616             hw->mac.type != ixgbe_mac_X550EM_a) {
7617                 return -ENOTSUP;
7618         }
7619
7620         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7621         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7622         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7623         IXGBE_WRITE_FLUSH(hw);
7624
7625         return 0;
7626 }
7627
7628 /* Disable l2 tunnel */
7629 static int
7630 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7631                             enum rte_eth_tunnel_type l2_tunnel_type)
7632 {
7633         int ret = 0;
7634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7635         struct ixgbe_l2_tn_info *l2_tn_info =
7636                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7637
7638         switch (l2_tunnel_type) {
7639         case RTE_L2_TUNNEL_TYPE_E_TAG:
7640                 l2_tn_info->e_tag_en = FALSE;
7641                 ret = ixgbe_e_tag_disable(hw);
7642                 break;
7643         default:
7644                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7645                 ret = -EINVAL;
7646                 break;
7647         }
7648
7649         return ret;
7650 }
7651
7652 static int
7653 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7654                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7655 {
7656         int ret = 0;
7657         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7658         uint32_t i, rar_entries;
7659         uint32_t rar_low, rar_high;
7660
7661         if (hw->mac.type != ixgbe_mac_X550 &&
7662             hw->mac.type != ixgbe_mac_X550EM_x &&
7663             hw->mac.type != ixgbe_mac_X550EM_a) {
7664                 return -ENOTSUP;
7665         }
7666
7667         rar_entries = ixgbe_get_num_rx_addrs(hw);
7668
7669         for (i = 1; i < rar_entries; i++) {
7670                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7671                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7672                 if ((rar_high & IXGBE_RAH_AV) &&
7673                     (rar_high & IXGBE_RAH_ADTYPE) &&
7674                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7675                      l2_tunnel->tunnel_id)) {
7676                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7677                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7678
7679                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7680
7681                         return ret;
7682                 }
7683         }
7684
7685         return ret;
7686 }
7687
7688 static int
7689 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7690                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7691 {
7692         int ret = 0;
7693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7694         uint32_t i, rar_entries;
7695         uint32_t rar_low, rar_high;
7696
7697         if (hw->mac.type != ixgbe_mac_X550 &&
7698             hw->mac.type != ixgbe_mac_X550EM_x &&
7699             hw->mac.type != ixgbe_mac_X550EM_a) {
7700                 return -ENOTSUP;
7701         }
7702
7703         /* One entry for one tunnel. Try to remove potential existing entry. */
7704         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7705
7706         rar_entries = ixgbe_get_num_rx_addrs(hw);
7707
7708         for (i = 1; i < rar_entries; i++) {
7709                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7710                 if (rar_high & IXGBE_RAH_AV) {
7711                         continue;
7712                 } else {
7713                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7714                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7715                         rar_low = l2_tunnel->tunnel_id;
7716
7717                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7718                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7719
7720                         return ret;
7721                 }
7722         }
7723
7724         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7725                      " Please remove a rule before adding a new one.");
7726         return -EINVAL;
7727 }
7728
7729 static inline struct ixgbe_l2_tn_filter *
7730 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7731                           struct ixgbe_l2_tn_key *key)
7732 {
7733         int ret;
7734
7735         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7736         if (ret < 0)
7737                 return NULL;
7738
7739         return l2_tn_info->hash_map[ret];
7740 }
7741
7742 static inline int
7743 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7744                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7745 {
7746         int ret;
7747
7748         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7749                                &l2_tn_filter->key);
7750
7751         if (ret < 0) {
7752                 PMD_DRV_LOG(ERR,
7753                             "Failed to insert L2 tunnel filter"
7754                             " to hash table %d!",
7755                             ret);
7756                 return ret;
7757         }
7758
7759         l2_tn_info->hash_map[ret] = l2_tn_filter;
7760
7761         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7762
7763         return 0;
7764 }
7765
7766 static inline int
7767 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7768                           struct ixgbe_l2_tn_key *key)
7769 {
7770         int ret;
7771         struct ixgbe_l2_tn_filter *l2_tn_filter;
7772
7773         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7774
7775         if (ret < 0) {
7776                 PMD_DRV_LOG(ERR,
7777                             "No such L2 tunnel filter to delete %d!",
7778                             ret);
7779                 return ret;
7780         }
7781
7782         l2_tn_filter = l2_tn_info->hash_map[ret];
7783         l2_tn_info->hash_map[ret] = NULL;
7784
7785         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7786         rte_free(l2_tn_filter);
7787
7788         return 0;
7789 }
7790
7791 /* Add l2 tunnel filter */
7792 int
7793 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7794                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7795                                bool restore)
7796 {
7797         int ret;
7798         struct ixgbe_l2_tn_info *l2_tn_info =
7799                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7800         struct ixgbe_l2_tn_key key;
7801         struct ixgbe_l2_tn_filter *node;
7802
7803         if (!restore) {
7804                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7805                 key.tn_id = l2_tunnel->tunnel_id;
7806
7807                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7808
7809                 if (node) {
7810                         PMD_DRV_LOG(ERR,
7811                                     "The L2 tunnel filter already exists!");
7812                         return -EINVAL;
7813                 }
7814
7815                 node = rte_zmalloc("ixgbe_l2_tn",
7816                                    sizeof(struct ixgbe_l2_tn_filter),
7817                                    0);
7818                 if (!node)
7819                         return -ENOMEM;
7820
7821                 rte_memcpy(&node->key,
7822                                  &key,
7823                                  sizeof(struct ixgbe_l2_tn_key));
7824                 node->pool = l2_tunnel->pool;
7825                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7826                 if (ret < 0) {
7827                         rte_free(node);
7828                         return ret;
7829                 }
7830         }
7831
7832         switch (l2_tunnel->l2_tunnel_type) {
7833         case RTE_L2_TUNNEL_TYPE_E_TAG:
7834                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7835                 break;
7836         default:
7837                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7838                 ret = -EINVAL;
7839                 break;
7840         }
7841
7842         if ((!restore) && (ret < 0))
7843                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7844
7845         return ret;
7846 }
7847
7848 /* Delete l2 tunnel filter */
7849 int
7850 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7851                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7852 {
7853         int ret;
7854         struct ixgbe_l2_tn_info *l2_tn_info =
7855                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7856         struct ixgbe_l2_tn_key key;
7857
7858         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7859         key.tn_id = l2_tunnel->tunnel_id;
7860         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7861         if (ret < 0)
7862                 return ret;
7863
7864         switch (l2_tunnel->l2_tunnel_type) {
7865         case RTE_L2_TUNNEL_TYPE_E_TAG:
7866                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7867                 break;
7868         default:
7869                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7870                 ret = -EINVAL;
7871                 break;
7872         }
7873
7874         return ret;
7875 }
7876
7877 /**
7878  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7879  * @dev: pointer to rte_eth_dev structure
7880  * @filter_op:operation will be taken.
7881  * @arg: a pointer to specific structure corresponding to the filter_op
7882  */
7883 static int
7884 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7885                                   enum rte_filter_op filter_op,
7886                                   void *arg)
7887 {
7888         int ret;
7889
7890         if (filter_op == RTE_ETH_FILTER_NOP)
7891                 return 0;
7892
7893         if (arg == NULL) {
7894                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7895                             filter_op);
7896                 return -EINVAL;
7897         }
7898
7899         switch (filter_op) {
7900         case RTE_ETH_FILTER_ADD:
7901                 ret = ixgbe_dev_l2_tunnel_filter_add
7902                         (dev,
7903                          (struct rte_eth_l2_tunnel_conf *)arg,
7904                          FALSE);
7905                 break;
7906         case RTE_ETH_FILTER_DELETE:
7907                 ret = ixgbe_dev_l2_tunnel_filter_del
7908                         (dev,
7909                          (struct rte_eth_l2_tunnel_conf *)arg);
7910                 break;
7911         default:
7912                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7913                 ret = -EINVAL;
7914                 break;
7915         }
7916         return ret;
7917 }
7918
7919 static int
7920 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7921 {
7922         int ret = 0;
7923         uint32_t ctrl;
7924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7925
7926         if (hw->mac.type != ixgbe_mac_X550 &&
7927             hw->mac.type != ixgbe_mac_X550EM_x &&
7928             hw->mac.type != ixgbe_mac_X550EM_a) {
7929                 return -ENOTSUP;
7930         }
7931
7932         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7933         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7934         if (en)
7935                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7936         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7937
7938         return ret;
7939 }
7940
7941 /* Enable l2 tunnel forwarding */
7942 static int
7943 ixgbe_dev_l2_tunnel_forwarding_enable
7944         (struct rte_eth_dev *dev,
7945          enum rte_eth_tunnel_type l2_tunnel_type)
7946 {
7947         struct ixgbe_l2_tn_info *l2_tn_info =
7948                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7949         int ret = 0;
7950
7951         switch (l2_tunnel_type) {
7952         case RTE_L2_TUNNEL_TYPE_E_TAG:
7953                 l2_tn_info->e_tag_fwd_en = TRUE;
7954                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7955                 break;
7956         default:
7957                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7958                 ret = -EINVAL;
7959                 break;
7960         }
7961
7962         return ret;
7963 }
7964
7965 /* Disable l2 tunnel forwarding */
7966 static int
7967 ixgbe_dev_l2_tunnel_forwarding_disable
7968         (struct rte_eth_dev *dev,
7969          enum rte_eth_tunnel_type l2_tunnel_type)
7970 {
7971         struct ixgbe_l2_tn_info *l2_tn_info =
7972                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7973         int ret = 0;
7974
7975         switch (l2_tunnel_type) {
7976         case RTE_L2_TUNNEL_TYPE_E_TAG:
7977                 l2_tn_info->e_tag_fwd_en = FALSE;
7978                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7979                 break;
7980         default:
7981                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7982                 ret = -EINVAL;
7983                 break;
7984         }
7985
7986         return ret;
7987 }
7988
7989 static int
7990 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7991                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7992                              bool en)
7993 {
7994         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7995         int ret = 0;
7996         uint32_t vmtir, vmvir;
7997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7998
7999         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8000                 PMD_DRV_LOG(ERR,
8001                             "VF id %u should be less than %u",
8002                             l2_tunnel->vf_id,
8003                             pci_dev->max_vfs);
8004                 return -EINVAL;
8005         }
8006
8007         if (hw->mac.type != ixgbe_mac_X550 &&
8008             hw->mac.type != ixgbe_mac_X550EM_x &&
8009             hw->mac.type != ixgbe_mac_X550EM_a) {
8010                 return -ENOTSUP;
8011         }
8012
8013         if (en)
8014                 vmtir = l2_tunnel->tunnel_id;
8015         else
8016                 vmtir = 0;
8017
8018         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8019
8020         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8021         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8022         if (en)
8023                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8024         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8025
8026         return ret;
8027 }
8028
8029 /* Enable l2 tunnel tag insertion */
8030 static int
8031 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8032                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8033 {
8034         int ret = 0;
8035
8036         switch (l2_tunnel->l2_tunnel_type) {
8037         case RTE_L2_TUNNEL_TYPE_E_TAG:
8038                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8039                 break;
8040         default:
8041                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8042                 ret = -EINVAL;
8043                 break;
8044         }
8045
8046         return ret;
8047 }
8048
8049 /* Disable l2 tunnel tag insertion */
8050 static int
8051 ixgbe_dev_l2_tunnel_insertion_disable
8052         (struct rte_eth_dev *dev,
8053          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8054 {
8055         int ret = 0;
8056
8057         switch (l2_tunnel->l2_tunnel_type) {
8058         case RTE_L2_TUNNEL_TYPE_E_TAG:
8059                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8060                 break;
8061         default:
8062                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8063                 ret = -EINVAL;
8064                 break;
8065         }
8066
8067         return ret;
8068 }
8069
8070 static int
8071 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8072                              bool en)
8073 {
8074         int ret = 0;
8075         uint32_t qde;
8076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8077
8078         if (hw->mac.type != ixgbe_mac_X550 &&
8079             hw->mac.type != ixgbe_mac_X550EM_x &&
8080             hw->mac.type != ixgbe_mac_X550EM_a) {
8081                 return -ENOTSUP;
8082         }
8083
8084         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8085         if (en)
8086                 qde |= IXGBE_QDE_STRIP_TAG;
8087         else
8088                 qde &= ~IXGBE_QDE_STRIP_TAG;
8089         qde &= ~IXGBE_QDE_READ;
8090         qde |= IXGBE_QDE_WRITE;
8091         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8092
8093         return ret;
8094 }
8095
8096 /* Enable l2 tunnel tag stripping */
8097 static int
8098 ixgbe_dev_l2_tunnel_stripping_enable
8099         (struct rte_eth_dev *dev,
8100          enum rte_eth_tunnel_type l2_tunnel_type)
8101 {
8102         int ret = 0;
8103
8104         switch (l2_tunnel_type) {
8105         case RTE_L2_TUNNEL_TYPE_E_TAG:
8106                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8107                 break;
8108         default:
8109                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8110                 ret = -EINVAL;
8111                 break;
8112         }
8113
8114         return ret;
8115 }
8116
8117 /* Disable l2 tunnel tag stripping */
8118 static int
8119 ixgbe_dev_l2_tunnel_stripping_disable
8120         (struct rte_eth_dev *dev,
8121          enum rte_eth_tunnel_type l2_tunnel_type)
8122 {
8123         int ret = 0;
8124
8125         switch (l2_tunnel_type) {
8126         case RTE_L2_TUNNEL_TYPE_E_TAG:
8127                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8128                 break;
8129         default:
8130                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8131                 ret = -EINVAL;
8132                 break;
8133         }
8134
8135         return ret;
8136 }
8137
8138 /* Enable/disable l2 tunnel offload functions */
8139 static int
8140 ixgbe_dev_l2_tunnel_offload_set
8141         (struct rte_eth_dev *dev,
8142          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8143          uint32_t mask,
8144          uint8_t en)
8145 {
8146         int ret = 0;
8147
8148         if (l2_tunnel == NULL)
8149                 return -EINVAL;
8150
8151         ret = -EINVAL;
8152         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8153                 if (en)
8154                         ret = ixgbe_dev_l2_tunnel_enable(
8155                                 dev,
8156                                 l2_tunnel->l2_tunnel_type);
8157                 else
8158                         ret = ixgbe_dev_l2_tunnel_disable(
8159                                 dev,
8160                                 l2_tunnel->l2_tunnel_type);
8161         }
8162
8163         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8164                 if (en)
8165                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8166                                 dev,
8167                                 l2_tunnel);
8168                 else
8169                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8170                                 dev,
8171                                 l2_tunnel);
8172         }
8173
8174         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8175                 if (en)
8176                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8177                                 dev,
8178                                 l2_tunnel->l2_tunnel_type);
8179                 else
8180                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8181                                 dev,
8182                                 l2_tunnel->l2_tunnel_type);
8183         }
8184
8185         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8186                 if (en)
8187                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8188                                 dev,
8189                                 l2_tunnel->l2_tunnel_type);
8190                 else
8191                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8192                                 dev,
8193                                 l2_tunnel->l2_tunnel_type);
8194         }
8195
8196         return ret;
8197 }
8198
8199 static int
8200 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8201                         uint16_t port)
8202 {
8203         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8204         IXGBE_WRITE_FLUSH(hw);
8205
8206         return 0;
8207 }
8208
8209 /* There's only one register for VxLAN UDP port.
8210  * So, we cannot add several ports. Will update it.
8211  */
8212 static int
8213 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8214                      uint16_t port)
8215 {
8216         if (port == 0) {
8217                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8218                 return -EINVAL;
8219         }
8220
8221         return ixgbe_update_vxlan_port(hw, port);
8222 }
8223
8224 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8225  * UDP port, it must have a value.
8226  * So, will reset it to the original value 0.
8227  */
8228 static int
8229 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8230                      uint16_t port)
8231 {
8232         uint16_t cur_port;
8233
8234         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8235
8236         if (cur_port != port) {
8237                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8238                 return -EINVAL;
8239         }
8240
8241         return ixgbe_update_vxlan_port(hw, 0);
8242 }
8243
8244 /* Add UDP tunneling port */
8245 static int
8246 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8247                               struct rte_eth_udp_tunnel *udp_tunnel)
8248 {
8249         int ret = 0;
8250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8251
8252         if (hw->mac.type != ixgbe_mac_X550 &&
8253             hw->mac.type != ixgbe_mac_X550EM_x &&
8254             hw->mac.type != ixgbe_mac_X550EM_a) {
8255                 return -ENOTSUP;
8256         }
8257
8258         if (udp_tunnel == NULL)
8259                 return -EINVAL;
8260
8261         switch (udp_tunnel->prot_type) {
8262         case RTE_TUNNEL_TYPE_VXLAN:
8263                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8264                 break;
8265
8266         case RTE_TUNNEL_TYPE_GENEVE:
8267         case RTE_TUNNEL_TYPE_TEREDO:
8268                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8269                 ret = -EINVAL;
8270                 break;
8271
8272         default:
8273                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8274                 ret = -EINVAL;
8275                 break;
8276         }
8277
8278         return ret;
8279 }
8280
8281 /* Remove UDP tunneling port */
8282 static int
8283 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8284                               struct rte_eth_udp_tunnel *udp_tunnel)
8285 {
8286         int ret = 0;
8287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8288
8289         if (hw->mac.type != ixgbe_mac_X550 &&
8290             hw->mac.type != ixgbe_mac_X550EM_x &&
8291             hw->mac.type != ixgbe_mac_X550EM_a) {
8292                 return -ENOTSUP;
8293         }
8294
8295         if (udp_tunnel == NULL)
8296                 return -EINVAL;
8297
8298         switch (udp_tunnel->prot_type) {
8299         case RTE_TUNNEL_TYPE_VXLAN:
8300                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8301                 break;
8302         case RTE_TUNNEL_TYPE_GENEVE:
8303         case RTE_TUNNEL_TYPE_TEREDO:
8304                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8305                 ret = -EINVAL;
8306                 break;
8307         default:
8308                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8309                 ret = -EINVAL;
8310                 break;
8311         }
8312
8313         return ret;
8314 }
8315
8316 static void
8317 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8318 {
8319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8320
8321         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC);
8322 }
8323
8324 static void
8325 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8326 {
8327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8328
8329         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8330 }
8331
8332 static void
8333 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8334 {
8335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8336
8337         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8338 }
8339
8340 static void
8341 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8342 {
8343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8344
8345         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8346 }
8347
8348 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8349 {
8350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8351         u32 in_msg = 0;
8352
8353         /* peek the message first */
8354         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8355
8356         /* PF reset VF event */
8357         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8358                 /* dummy mbx read to ack pf */
8359                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8360                         return;
8361                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8362                                               NULL);
8363         }
8364 }
8365
8366 static int
8367 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8368 {
8369         uint32_t eicr;
8370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8371         struct ixgbe_interrupt *intr =
8372                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8373         ixgbevf_intr_disable(dev);
8374
8375         /* read-on-clear nic registers here */
8376         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8377         intr->flags = 0;
8378
8379         /* only one misc vector supported - mailbox */
8380         eicr &= IXGBE_VTEICR_MASK;
8381         if (eicr == IXGBE_MISC_VEC_ID)
8382                 intr->flags |= IXGBE_FLAG_MAILBOX;
8383
8384         return 0;
8385 }
8386
8387 static int
8388 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8389 {
8390         struct ixgbe_interrupt *intr =
8391                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8392
8393         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8394                 ixgbevf_mbx_process(dev);
8395                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8396         }
8397
8398         ixgbevf_intr_enable(dev);
8399
8400         return 0;
8401 }
8402
8403 static void
8404 ixgbevf_dev_interrupt_handler(void *param)
8405 {
8406         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8407
8408         ixgbevf_dev_interrupt_get_status(dev);
8409         ixgbevf_dev_interrupt_action(dev);
8410 }
8411
8412 /**
8413  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8414  *  @hw: pointer to hardware structure
8415  *
8416  *  Stops the transmit data path and waits for the HW to internally empty
8417  *  the Tx security block
8418  **/
8419 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8420 {
8421 #define IXGBE_MAX_SECTX_POLL 40
8422
8423         int i;
8424         int sectxreg;
8425
8426         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8427         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8428         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8429         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8430                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8431                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8432                         break;
8433                 /* Use interrupt-safe sleep just in case */
8434                 usec_delay(1000);
8435         }
8436
8437         /* For informational purposes only */
8438         if (i >= IXGBE_MAX_SECTX_POLL)
8439                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8440                          "path fully disabled.  Continuing with init.");
8441
8442         return IXGBE_SUCCESS;
8443 }
8444
8445 /**
8446  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8447  *  @hw: pointer to hardware structure
8448  *
8449  *  Enables the transmit data path.
8450  **/
8451 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8452 {
8453         uint32_t sectxreg;
8454
8455         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8456         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8457         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8458         IXGBE_WRITE_FLUSH(hw);
8459
8460         return IXGBE_SUCCESS;
8461 }
8462
8463 /* restore n-tuple filter */
8464 static inline void
8465 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8466 {
8467         struct ixgbe_filter_info *filter_info =
8468                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8469         struct ixgbe_5tuple_filter *node;
8470
8471         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8472                 ixgbe_inject_5tuple_filter(dev, node);
8473         }
8474 }
8475
8476 /* restore ethernet type filter */
8477 static inline void
8478 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8479 {
8480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8481         struct ixgbe_filter_info *filter_info =
8482                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8483         int i;
8484
8485         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8486                 if (filter_info->ethertype_mask & (1 << i)) {
8487                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8488                                         filter_info->ethertype_filters[i].etqf);
8489                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8490                                         filter_info->ethertype_filters[i].etqs);
8491                         IXGBE_WRITE_FLUSH(hw);
8492                 }
8493         }
8494 }
8495
8496 /* restore SYN filter */
8497 static inline void
8498 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8499 {
8500         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8501         struct ixgbe_filter_info *filter_info =
8502                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8503         uint32_t synqf;
8504
8505         synqf = filter_info->syn_info;
8506
8507         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8508                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8509                 IXGBE_WRITE_FLUSH(hw);
8510         }
8511 }
8512
8513 /* restore L2 tunnel filter */
8514 static inline void
8515 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8516 {
8517         struct ixgbe_l2_tn_info *l2_tn_info =
8518                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8519         struct ixgbe_l2_tn_filter *node;
8520         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8521
8522         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8523                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8524                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8525                 l2_tn_conf.pool           = node->pool;
8526                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8527         }
8528 }
8529
8530 /* restore rss filter */
8531 static inline void
8532 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8533 {
8534         struct ixgbe_filter_info *filter_info =
8535                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8536
8537         if (filter_info->rss_info.conf.queue_num)
8538                 ixgbe_config_rss_filter(dev,
8539                         &filter_info->rss_info, TRUE);
8540 }
8541
8542 static int
8543 ixgbe_filter_restore(struct rte_eth_dev *dev)
8544 {
8545         ixgbe_ntuple_filter_restore(dev);
8546         ixgbe_ethertype_filter_restore(dev);
8547         ixgbe_syn_filter_restore(dev);
8548         ixgbe_fdir_filter_restore(dev);
8549         ixgbe_l2_tn_filter_restore(dev);
8550         ixgbe_rss_filter_restore(dev);
8551
8552         return 0;
8553 }
8554
8555 static void
8556 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8557 {
8558         struct ixgbe_l2_tn_info *l2_tn_info =
8559                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8561
8562         if (l2_tn_info->e_tag_en)
8563                 (void)ixgbe_e_tag_enable(hw);
8564
8565         if (l2_tn_info->e_tag_fwd_en)
8566                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8567
8568         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8569 }
8570
8571 /* remove all the n-tuple filters */
8572 void
8573 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8574 {
8575         struct ixgbe_filter_info *filter_info =
8576                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8577         struct ixgbe_5tuple_filter *p_5tuple;
8578
8579         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8580                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8581 }
8582
8583 /* remove all the ether type filters */
8584 void
8585 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8586 {
8587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8588         struct ixgbe_filter_info *filter_info =
8589                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8590         int i;
8591
8592         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8593                 if (filter_info->ethertype_mask & (1 << i) &&
8594                     !filter_info->ethertype_filters[i].conf) {
8595                         (void)ixgbe_ethertype_filter_remove(filter_info,
8596                                                             (uint8_t)i);
8597                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8598                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8599                         IXGBE_WRITE_FLUSH(hw);
8600                 }
8601         }
8602 }
8603
8604 /* remove the SYN filter */
8605 void
8606 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8607 {
8608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8609         struct ixgbe_filter_info *filter_info =
8610                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8611
8612         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8613                 filter_info->syn_info = 0;
8614
8615                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8616                 IXGBE_WRITE_FLUSH(hw);
8617         }
8618 }
8619
8620 /* remove all the L2 tunnel filters */
8621 int
8622 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8623 {
8624         struct ixgbe_l2_tn_info *l2_tn_info =
8625                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8626         struct ixgbe_l2_tn_filter *l2_tn_filter;
8627         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8628         int ret = 0;
8629
8630         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8631                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8632                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8633                 l2_tn_conf.pool           = l2_tn_filter->pool;
8634                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8635                 if (ret < 0)
8636                         return ret;
8637         }
8638
8639         return 0;
8640 }
8641
8642 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8643 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8644 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8645 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8646 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8647 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8648
8649 RTE_INIT(ixgbe_init_log)
8650 {
8651         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8652         if (ixgbe_logtype_init >= 0)
8653                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8654         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8655         if (ixgbe_logtype_driver >= 0)
8656                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8657 }