1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_string_fns.h>
15 #include <rte_byteorder.h>
16 #include <rte_common.h>
17 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
27 #include <rte_alarm.h>
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
31 #include <rte_malloc.h>
32 #include <rte_random.h>
34 #include <rte_hash_crc.h>
35 #ifdef RTE_LIBRTE_SECURITY
36 #include <rte_security_driver.h>
39 #include "ixgbe_logs.h"
40 #include "base/ixgbe_api.h"
41 #include "base/ixgbe_vf.h"
42 #include "base/ixgbe_common.h"
43 #include "ixgbe_ethdev.h"
44 #include "ixgbe_bypass.h"
45 #include "ixgbe_rxtx.h"
46 #include "base/ixgbe_type.h"
47 #include "base/ixgbe_phy.h"
48 #include "ixgbe_regs.h"
51 * High threshold controlling when to start sending XOFF frames. Must be at
52 * least 8 bytes less than receive packet buffer size. This value is in units
55 #define IXGBE_FC_HI 0x80
58 * Low threshold controlling when to start sending XON frames. This value is
59 * in units of 1024 bytes.
61 #define IXGBE_FC_LO 0x40
63 /* Timer value included in XOFF frames. */
64 #define IXGBE_FC_PAUSE 0x680
66 /*Default value of Max Rx Queue*/
67 #define IXGBE_MAX_RX_QUEUE_NUM 128
69 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
70 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
71 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
73 #define IXGBE_MMW_SIZE_DEFAULT 0x4
74 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
75 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
78 * Default values for RX/TX configuration
80 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
81 #define IXGBE_DEFAULT_RX_PTHRESH 8
82 #define IXGBE_DEFAULT_RX_HTHRESH 8
83 #define IXGBE_DEFAULT_RX_WTHRESH 0
85 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
86 #define IXGBE_DEFAULT_TX_PTHRESH 32
87 #define IXGBE_DEFAULT_TX_HTHRESH 0
88 #define IXGBE_DEFAULT_TX_WTHRESH 0
89 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
91 /* Bit shift and mask */
92 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
93 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
94 #define IXGBE_8_BIT_WIDTH CHAR_BIT
95 #define IXGBE_8_BIT_MASK UINT8_MAX
97 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
99 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
101 /* Additional timesync values. */
102 #define NSEC_PER_SEC 1000000000L
103 #define IXGBE_INCVAL_10GB 0x66666666
104 #define IXGBE_INCVAL_1GB 0x40000000
105 #define IXGBE_INCVAL_100 0x50000000
106 #define IXGBE_INCVAL_SHIFT_10GB 28
107 #define IXGBE_INCVAL_SHIFT_1GB 24
108 #define IXGBE_INCVAL_SHIFT_100 21
109 #define IXGBE_INCVAL_SHIFT_82599 7
110 #define IXGBE_INCPER_SHIFT_82599 24
112 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
114 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
115 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
116 #define IXGBE_ETAG_ETYPE 0x00005084
117 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
118 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
119 #define IXGBE_RAH_ADTYPE 0x40000000
120 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
121 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
122 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
123 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
124 #define IXGBE_QDE_STRIP_TAG 0x00000004
125 #define IXGBE_VTEICR_MASK 0x07
127 #define IXGBE_EXVET_VET_EXT_SHIFT 16
128 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
130 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
131 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
133 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
134 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
135 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
137 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
138 static int ixgbe_dev_start(struct rte_eth_dev *dev);
139 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
141 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
142 static void ixgbe_dev_close(struct rte_eth_dev *dev);
143 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
144 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
146 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
147 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
148 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
149 int wait_to_complete);
150 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
151 struct rte_eth_stats *stats);
152 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
153 struct rte_eth_xstat *xstats, unsigned n);
154 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
155 struct rte_eth_xstat *xstats, unsigned n);
157 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
158 uint64_t *values, unsigned int n);
159 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
160 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
161 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
162 struct rte_eth_xstat_name *xstats_names,
164 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
165 struct rte_eth_xstat_name *xstats_names, unsigned limit);
166 static int ixgbe_dev_xstats_get_names_by_id(
167 struct rte_eth_dev *dev,
168 struct rte_eth_xstat_name *xstats_names,
171 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
175 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
177 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
178 struct rte_eth_dev_info *dev_info);
179 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
180 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
181 struct rte_eth_dev_info *dev_info);
182 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
184 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
185 uint16_t vlan_id, int on);
186 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
187 enum rte_vlan_type vlan_type,
189 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
190 uint16_t queue, bool on);
191 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
193 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
195 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
196 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
197 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
198 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
199 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
200 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
202 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
203 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
204 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
205 struct rte_eth_fc_conf *fc_conf);
206 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
207 struct rte_eth_fc_conf *fc_conf);
208 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
209 struct rte_eth_pfc_conf *pfc_conf);
210 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
211 struct rte_eth_rss_reta_entry64 *reta_conf,
213 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
214 struct rte_eth_rss_reta_entry64 *reta_conf,
216 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
217 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
218 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
219 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
220 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
221 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
222 static void ixgbe_dev_interrupt_handler(void *param);
223 static void ixgbe_dev_interrupt_delayed_handler(void *param);
224 static void ixgbe_dev_setup_link_alarm_handler(void *param);
226 static int ixgbe_add_rar(struct rte_eth_dev *dev,
227 struct rte_ether_addr *mac_addr,
228 uint32_t index, uint32_t pool);
229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
230 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
231 struct rte_ether_addr *mac_addr);
232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
233 static bool is_device_supported(struct rte_eth_dev *dev,
234 struct rte_pci_driver *drv);
236 /* For Virtual Function support */
237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
239 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
240 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
242 int wait_to_complete);
243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
245 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
246 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
247 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
249 struct rte_eth_stats *stats);
250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
252 uint16_t vlan_id, int on);
253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
254 uint16_t queue, int on);
255 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
256 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
257 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
258 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
260 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
262 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
263 uint8_t queue, uint8_t msix_vector);
264 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
265 static void ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
266 static void ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
267 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
268 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
270 /* For Eth VMDQ APIs support */
271 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
272 rte_ether_addr * mac_addr, uint8_t on);
273 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
275 struct rte_eth_mirror_conf *mirror_conf,
276 uint8_t rule_id, uint8_t on);
277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
284 uint8_t queue, uint8_t msix_vector);
285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
287 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
288 struct rte_ether_addr *mac_addr,
289 uint32_t index, uint32_t pool);
290 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
291 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
292 struct rte_ether_addr *mac_addr);
293 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
294 struct rte_eth_syn_filter *filter);
295 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
296 enum rte_filter_op filter_op,
298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
299 struct ixgbe_5tuple_filter *filter);
300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
301 struct ixgbe_5tuple_filter *filter);
302 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
303 enum rte_filter_op filter_op,
305 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
306 struct rte_eth_ntuple_filter *filter);
307 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
308 enum rte_filter_op filter_op,
310 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
311 struct rte_eth_ethertype_filter *filter);
312 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
313 enum rte_filter_type filter_type,
314 enum rte_filter_op filter_op,
316 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
318 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
319 struct rte_ether_addr *mc_addr_set,
320 uint32_t nb_mc_addr);
321 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
322 struct rte_eth_dcb_info *dcb_info);
324 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
325 static int ixgbe_get_regs(struct rte_eth_dev *dev,
326 struct rte_dev_reg_info *regs);
327 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
328 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
329 struct rte_dev_eeprom_info *eeprom);
330 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
331 struct rte_dev_eeprom_info *eeprom);
333 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
334 struct rte_eth_dev_module_info *modinfo);
335 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
336 struct rte_dev_eeprom_info *info);
338 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
339 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
340 struct rte_dev_reg_info *regs);
342 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
343 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
344 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
345 struct timespec *timestamp,
347 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
348 struct timespec *timestamp);
349 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
350 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
351 struct timespec *timestamp);
352 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
353 const struct timespec *timestamp);
354 static void ixgbevf_dev_interrupt_handler(void *param);
356 static int ixgbe_dev_l2_tunnel_eth_type_conf
357 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
358 static int ixgbe_dev_l2_tunnel_offload_set
359 (struct rte_eth_dev *dev,
360 struct rte_eth_l2_tunnel_conf *l2_tunnel,
363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
364 enum rte_filter_op filter_op,
367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
368 struct rte_eth_udp_tunnel *udp_tunnel);
369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
370 struct rte_eth_udp_tunnel *udp_tunnel);
371 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
372 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
375 * Define VF Stats MACRO for Non "cleared on read" register
377 #define UPDATE_VF_STAT(reg, last, cur) \
379 uint32_t latest = IXGBE_READ_REG(hw, reg); \
380 cur += (latest - last) & UINT_MAX; \
384 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
386 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
387 u64 new_msb = IXGBE_READ_REG(hw, msb); \
388 u64 latest = ((new_msb << 32) | new_lsb); \
389 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
393 #define IXGBE_SET_HWSTRIP(h, q) do {\
394 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
395 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
396 (h)->bitmap[idx] |= 1 << bit;\
399 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
400 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
401 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
402 (h)->bitmap[idx] &= ~(1 << bit);\
405 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
406 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
407 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
408 (r) = (h)->bitmap[idx] >> bit & 1;\
411 int ixgbe_logtype_init;
412 int ixgbe_logtype_driver;
415 * The set of PCI devices this driver supports
417 static const struct rte_pci_id pci_id_ixgbe_map[] = {
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
466 #ifdef RTE_LIBRTE_IXGBE_BYPASS
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
469 { .vendor_id = 0, /* sentinel */ },
473 * The set of PCI devices this driver supports (for 82599 VF)
475 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
484 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
486 { .vendor_id = 0, /* sentinel */ },
489 static const struct rte_eth_desc_lim rx_desc_lim = {
490 .nb_max = IXGBE_MAX_RING_DESC,
491 .nb_min = IXGBE_MIN_RING_DESC,
492 .nb_align = IXGBE_RXD_ALIGN,
495 static const struct rte_eth_desc_lim tx_desc_lim = {
496 .nb_max = IXGBE_MAX_RING_DESC,
497 .nb_min = IXGBE_MIN_RING_DESC,
498 .nb_align = IXGBE_TXD_ALIGN,
499 .nb_seg_max = IXGBE_TX_MAX_SEG,
500 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
503 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
504 .dev_configure = ixgbe_dev_configure,
505 .dev_start = ixgbe_dev_start,
506 .dev_stop = ixgbe_dev_stop,
507 .dev_set_link_up = ixgbe_dev_set_link_up,
508 .dev_set_link_down = ixgbe_dev_set_link_down,
509 .dev_close = ixgbe_dev_close,
510 .dev_reset = ixgbe_dev_reset,
511 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
512 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
513 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
514 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
515 .link_update = ixgbe_dev_link_update,
516 .stats_get = ixgbe_dev_stats_get,
517 .xstats_get = ixgbe_dev_xstats_get,
518 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
519 .stats_reset = ixgbe_dev_stats_reset,
520 .xstats_reset = ixgbe_dev_xstats_reset,
521 .xstats_get_names = ixgbe_dev_xstats_get_names,
522 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
523 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
524 .fw_version_get = ixgbe_fw_version_get,
525 .dev_infos_get = ixgbe_dev_info_get,
526 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
527 .mtu_set = ixgbe_dev_mtu_set,
528 .vlan_filter_set = ixgbe_vlan_filter_set,
529 .vlan_tpid_set = ixgbe_vlan_tpid_set,
530 .vlan_offload_set = ixgbe_vlan_offload_set,
531 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
532 .rx_queue_start = ixgbe_dev_rx_queue_start,
533 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
534 .tx_queue_start = ixgbe_dev_tx_queue_start,
535 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
536 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
537 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
538 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
539 .rx_queue_release = ixgbe_dev_rx_queue_release,
540 .rx_queue_count = ixgbe_dev_rx_queue_count,
541 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
542 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
543 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
544 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
545 .tx_queue_release = ixgbe_dev_tx_queue_release,
546 .dev_led_on = ixgbe_dev_led_on,
547 .dev_led_off = ixgbe_dev_led_off,
548 .flow_ctrl_get = ixgbe_flow_ctrl_get,
549 .flow_ctrl_set = ixgbe_flow_ctrl_set,
550 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
551 .mac_addr_add = ixgbe_add_rar,
552 .mac_addr_remove = ixgbe_remove_rar,
553 .mac_addr_set = ixgbe_set_default_mac_addr,
554 .uc_hash_table_set = ixgbe_uc_hash_table_set,
555 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
556 .mirror_rule_set = ixgbe_mirror_rule_set,
557 .mirror_rule_reset = ixgbe_mirror_rule_reset,
558 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
559 .reta_update = ixgbe_dev_rss_reta_update,
560 .reta_query = ixgbe_dev_rss_reta_query,
561 .rss_hash_update = ixgbe_dev_rss_hash_update,
562 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
563 .filter_ctrl = ixgbe_dev_filter_ctrl,
564 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
565 .rxq_info_get = ixgbe_rxq_info_get,
566 .txq_info_get = ixgbe_txq_info_get,
567 .timesync_enable = ixgbe_timesync_enable,
568 .timesync_disable = ixgbe_timesync_disable,
569 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
570 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
571 .get_reg = ixgbe_get_regs,
572 .get_eeprom_length = ixgbe_get_eeprom_length,
573 .get_eeprom = ixgbe_get_eeprom,
574 .set_eeprom = ixgbe_set_eeprom,
575 .get_module_info = ixgbe_get_module_info,
576 .get_module_eeprom = ixgbe_get_module_eeprom,
577 .get_dcb_info = ixgbe_dev_get_dcb_info,
578 .timesync_adjust_time = ixgbe_timesync_adjust_time,
579 .timesync_read_time = ixgbe_timesync_read_time,
580 .timesync_write_time = ixgbe_timesync_write_time,
581 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
582 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
583 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
584 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
585 .tm_ops_get = ixgbe_tm_ops_get,
589 * dev_ops for virtual function, bare necessities for basic vf
590 * operation have been implemented
592 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
593 .dev_configure = ixgbevf_dev_configure,
594 .dev_start = ixgbevf_dev_start,
595 .dev_stop = ixgbevf_dev_stop,
596 .link_update = ixgbevf_dev_link_update,
597 .stats_get = ixgbevf_dev_stats_get,
598 .xstats_get = ixgbevf_dev_xstats_get,
599 .stats_reset = ixgbevf_dev_stats_reset,
600 .xstats_reset = ixgbevf_dev_stats_reset,
601 .xstats_get_names = ixgbevf_dev_xstats_get_names,
602 .dev_close = ixgbevf_dev_close,
603 .dev_reset = ixgbevf_dev_reset,
604 .promiscuous_enable = ixgbevf_dev_promiscuous_enable,
605 .promiscuous_disable = ixgbevf_dev_promiscuous_disable,
606 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
607 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
608 .dev_infos_get = ixgbevf_dev_info_get,
609 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
610 .mtu_set = ixgbevf_dev_set_mtu,
611 .vlan_filter_set = ixgbevf_vlan_filter_set,
612 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
613 .vlan_offload_set = ixgbevf_vlan_offload_set,
614 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
615 .rx_queue_release = ixgbe_dev_rx_queue_release,
616 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
617 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
618 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
619 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
620 .tx_queue_release = ixgbe_dev_tx_queue_release,
621 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
622 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
623 .mac_addr_add = ixgbevf_add_mac_addr,
624 .mac_addr_remove = ixgbevf_remove_mac_addr,
625 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
626 .rxq_info_get = ixgbe_rxq_info_get,
627 .txq_info_get = ixgbe_txq_info_get,
628 .mac_addr_set = ixgbevf_set_default_mac_addr,
629 .get_reg = ixgbevf_get_regs,
630 .reta_update = ixgbe_dev_rss_reta_update,
631 .reta_query = ixgbe_dev_rss_reta_query,
632 .rss_hash_update = ixgbe_dev_rss_hash_update,
633 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
636 /* store statistics names and its offset in stats structure */
637 struct rte_ixgbe_xstats_name_off {
638 char name[RTE_ETH_XSTATS_NAME_SIZE];
642 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
643 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
644 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
645 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
646 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
647 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
648 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
649 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
650 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
651 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
652 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
653 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
654 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
655 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
656 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
657 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
659 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
661 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
662 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
663 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
664 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
665 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
666 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
667 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
668 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
669 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
670 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
671 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
672 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
673 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
674 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
675 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
676 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
677 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
679 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
681 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
682 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
683 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
684 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
686 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
688 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
690 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
692 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
694 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
696 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
699 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
700 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
701 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
703 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
704 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
705 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
706 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
707 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
709 {"rx_fcoe_no_direct_data_placement_ext_buff",
710 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
712 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
714 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
716 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
718 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
720 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
723 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
724 sizeof(rte_ixgbe_stats_strings[0]))
726 /* MACsec statistics */
727 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
728 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
730 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
731 out_pkts_encrypted)},
732 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
733 out_pkts_protected)},
734 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
735 out_octets_encrypted)},
736 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
737 out_octets_protected)},
738 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
740 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
742 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
744 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
745 in_pkts_unknownsci)},
746 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
747 in_octets_decrypted)},
748 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
749 in_octets_validated)},
750 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
756 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
758 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
760 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
765 in_pkts_notusingsa)},
768 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
769 sizeof(rte_ixgbe_macsec_strings[0]))
771 /* Per-queue statistics */
772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
773 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
774 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
775 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
776 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
779 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
780 sizeof(rte_ixgbe_rxq_strings[0]))
781 #define IXGBE_NB_RXQ_PRIO_VALUES 8
783 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
784 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
785 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
786 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
790 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
791 sizeof(rte_ixgbe_txq_strings[0]))
792 #define IXGBE_NB_TXQ_PRIO_VALUES 8
794 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
795 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
798 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
799 sizeof(rte_ixgbevf_stats_strings[0]))
802 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
805 ixgbe_is_sfp(struct ixgbe_hw *hw)
807 switch (hw->phy.type) {
808 case ixgbe_phy_sfp_avago:
809 case ixgbe_phy_sfp_ftl:
810 case ixgbe_phy_sfp_intel:
811 case ixgbe_phy_sfp_unknown:
812 case ixgbe_phy_sfp_passive_tyco:
813 case ixgbe_phy_sfp_passive_unknown:
820 static inline int32_t
821 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
826 status = ixgbe_reset_hw(hw);
828 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
829 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
830 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
831 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
832 IXGBE_WRITE_FLUSH(hw);
834 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
835 status = IXGBE_SUCCESS;
840 ixgbe_enable_intr(struct rte_eth_dev *dev)
842 struct ixgbe_interrupt *intr =
843 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
844 struct ixgbe_hw *hw =
845 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
847 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
848 IXGBE_WRITE_FLUSH(hw);
852 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
855 ixgbe_disable_intr(struct ixgbe_hw *hw)
857 PMD_INIT_FUNC_TRACE();
859 if (hw->mac.type == ixgbe_mac_82598EB) {
860 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
862 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
863 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
864 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
866 IXGBE_WRITE_FLUSH(hw);
870 * This function resets queue statistics mapping registers.
871 * From Niantic datasheet, Initialization of Statistics section:
872 * "...if software requires the queue counters, the RQSMR and TQSM registers
873 * must be re-programmed following a device reset.
876 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
880 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
881 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
882 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
888 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
893 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
894 #define NB_QMAP_FIELDS_PER_QSM_REG 4
895 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
898 struct ixgbe_stat_mapping_registers *stat_mappings =
899 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
900 uint32_t qsmr_mask = 0;
901 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
905 if ((hw->mac.type != ixgbe_mac_82599EB) &&
906 (hw->mac.type != ixgbe_mac_X540) &&
907 (hw->mac.type != ixgbe_mac_X550) &&
908 (hw->mac.type != ixgbe_mac_X550EM_x) &&
909 (hw->mac.type != ixgbe_mac_X550EM_a))
912 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
913 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
916 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
917 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
918 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
921 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
923 /* Now clear any previous stat_idx set */
924 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
926 stat_mappings->tqsm[n] &= ~clearing_mask;
928 stat_mappings->rqsmr[n] &= ~clearing_mask;
930 q_map = (uint32_t)stat_idx;
931 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
932 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
934 stat_mappings->tqsm[n] |= qsmr_mask;
936 stat_mappings->rqsmr[n] |= qsmr_mask;
938 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
939 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
941 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
942 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
944 /* Now write the mapping in the appropriate register */
946 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
947 stat_mappings->rqsmr[n], n);
948 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
950 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
951 stat_mappings->tqsm[n], n);
952 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
958 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
960 struct ixgbe_stat_mapping_registers *stat_mappings =
961 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
962 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
965 /* write whatever was in stat mapping table to the NIC */
966 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
968 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
971 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
976 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
979 struct ixgbe_dcb_tc_config *tc;
980 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
982 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
983 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
984 for (i = 0; i < dcb_max_tc; i++) {
985 tc = &dcb_config->tc_config[i];
986 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
987 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
988 (uint8_t)(100/dcb_max_tc + (i & 1));
989 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
990 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
991 (uint8_t)(100/dcb_max_tc + (i & 1));
992 tc->pfc = ixgbe_dcb_pfc_disabled;
995 /* Initialize default user to priority mapping, UPx->TC0 */
996 tc = &dcb_config->tc_config[0];
997 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
998 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
999 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1000 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1001 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1003 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1004 dcb_config->pfc_mode_enable = false;
1005 dcb_config->vt_mode = true;
1006 dcb_config->round_robin_enable = false;
1007 /* support all DCB capabilities in 82599 */
1008 dcb_config->support.capabilities = 0xFF;
1010 /*we only support 4 Tcs for X540, X550 */
1011 if (hw->mac.type == ixgbe_mac_X540 ||
1012 hw->mac.type == ixgbe_mac_X550 ||
1013 hw->mac.type == ixgbe_mac_X550EM_x ||
1014 hw->mac.type == ixgbe_mac_X550EM_a) {
1015 dcb_config->num_tcs.pg_tcs = 4;
1016 dcb_config->num_tcs.pfc_tcs = 4;
1021 * Ensure that all locks are released before first NVM or PHY access
1024 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1029 * Phy lock should not fail in this early stage. If this is the case,
1030 * it is due to an improper exit of the application.
1031 * So force the release of the faulty lock. Release of common lock
1032 * is done automatically by swfw_sync function.
1034 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1035 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1038 ixgbe_release_swfw_semaphore(hw, mask);
1041 * These ones are more tricky since they are common to all ports; but
1042 * swfw_sync retries last long enough (1s) to be almost sure that if
1043 * lock can not be taken it is due to an improper lock of the
1046 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1047 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1048 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1050 ixgbe_release_swfw_semaphore(hw, mask);
1054 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1055 * It returns 0 on success.
1058 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1060 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1061 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1062 struct ixgbe_hw *hw =
1063 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1064 struct ixgbe_vfta *shadow_vfta =
1065 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1066 struct ixgbe_hwstrip *hwstrip =
1067 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1068 struct ixgbe_dcb_config *dcb_config =
1069 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1070 struct ixgbe_filter_info *filter_info =
1071 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1072 struct ixgbe_bw_conf *bw_conf =
1073 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1078 PMD_INIT_FUNC_TRACE();
1080 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1081 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1082 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1083 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1086 * For secondary processes, we don't initialise any further as primary
1087 * has already done this work. Only check we don't need a different
1088 * RX and TX function.
1090 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1091 struct ixgbe_tx_queue *txq;
1092 /* TX queue function in primary, set by last queue initialized
1093 * Tx queue may not initialized by primary process
1095 if (eth_dev->data->tx_queues) {
1096 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1097 ixgbe_set_tx_function(eth_dev, txq);
1099 /* Use default TX function if we get here */
1100 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1101 "Using default TX function.");
1104 ixgbe_set_rx_function(eth_dev);
1109 rte_eth_copy_pci_info(eth_dev, pci_dev);
1111 /* Vendor and Device ID need to be set before init of shared code */
1112 hw->device_id = pci_dev->id.device_id;
1113 hw->vendor_id = pci_dev->id.vendor_id;
1114 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1115 hw->allow_unsupported_sfp = 1;
1117 /* Initialize the shared code (base driver) */
1118 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1119 diag = ixgbe_bypass_init_shared_code(hw);
1121 diag = ixgbe_init_shared_code(hw);
1122 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1124 if (diag != IXGBE_SUCCESS) {
1125 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1129 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1130 PMD_INIT_LOG(ERR, "\nERROR: "
1131 "Firmware recovery mode detected. Limiting functionality.\n"
1132 "Refer to the Intel(R) Ethernet Adapters and Devices "
1133 "User Guide for details on firmware recovery mode.");
1137 /* pick up the PCI bus settings for reporting later */
1138 ixgbe_get_bus_info(hw);
1140 /* Unlock any pending hardware semaphore */
1141 ixgbe_swfw_lock_reset(hw);
1143 #ifdef RTE_LIBRTE_SECURITY
1144 /* Initialize security_ctx only for primary process*/
1145 if (ixgbe_ipsec_ctx_create(eth_dev))
1149 /* Initialize DCB configuration*/
1150 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1151 ixgbe_dcb_init(hw, dcb_config);
1152 /* Get Hardware Flow Control setting */
1153 hw->fc.requested_mode = ixgbe_fc_full;
1154 hw->fc.current_mode = ixgbe_fc_full;
1155 hw->fc.pause_time = IXGBE_FC_PAUSE;
1156 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1157 hw->fc.low_water[i] = IXGBE_FC_LO;
1158 hw->fc.high_water[i] = IXGBE_FC_HI;
1160 hw->fc.send_xon = 1;
1162 /* Make sure we have a good EEPROM before we read from it */
1163 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1164 if (diag != IXGBE_SUCCESS) {
1165 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1169 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1170 diag = ixgbe_bypass_init_hw(hw);
1172 diag = ixgbe_init_hw(hw);
1173 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1176 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1177 * is called too soon after the kernel driver unbinding/binding occurs.
1178 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1179 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1180 * also called. See ixgbe_identify_phy_82599(). The reason for the
1181 * failure is not known, and only occuts when virtualisation features
1182 * are disabled in the bios. A delay of 100ms was found to be enough by
1183 * trial-and-error, and is doubled to be safe.
1185 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1187 diag = ixgbe_init_hw(hw);
1190 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1191 diag = IXGBE_SUCCESS;
1193 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1194 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1195 "LOM. Please be aware there may be issues associated "
1196 "with your hardware.");
1197 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1198 "please contact your Intel or hardware representative "
1199 "who provided you with this hardware.");
1200 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1201 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1203 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1207 /* Reset the hw statistics */
1208 ixgbe_dev_stats_reset(eth_dev);
1210 /* disable interrupt */
1211 ixgbe_disable_intr(hw);
1213 /* reset mappings for queue statistics hw counters*/
1214 ixgbe_reset_qstat_mappings(hw);
1216 /* Allocate memory for storing MAC addresses */
1217 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1218 hw->mac.num_rar_entries, 0);
1219 if (eth_dev->data->mac_addrs == NULL) {
1221 "Failed to allocate %u bytes needed to store "
1223 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1226 /* Copy the permanent MAC address */
1227 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1228 ð_dev->data->mac_addrs[0]);
1230 /* Allocate memory for storing hash filter MAC addresses */
1231 eth_dev->data->hash_mac_addrs = rte_zmalloc(
1232 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1233 if (eth_dev->data->hash_mac_addrs == NULL) {
1235 "Failed to allocate %d bytes needed to store MAC addresses",
1236 RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1240 /* initialize the vfta */
1241 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1243 /* initialize the hw strip bitmap*/
1244 memset(hwstrip, 0, sizeof(*hwstrip));
1246 /* initialize PF if max_vfs not zero */
1247 ixgbe_pf_host_init(eth_dev);
1249 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1250 /* let hardware know driver is loaded */
1251 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1252 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1253 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1254 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1255 IXGBE_WRITE_FLUSH(hw);
1257 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1258 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1259 (int) hw->mac.type, (int) hw->phy.type,
1260 (int) hw->phy.sfp_type);
1262 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1263 (int) hw->mac.type, (int) hw->phy.type);
1265 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1266 eth_dev->data->port_id, pci_dev->id.vendor_id,
1267 pci_dev->id.device_id);
1269 rte_intr_callback_register(intr_handle,
1270 ixgbe_dev_interrupt_handler, eth_dev);
1272 /* enable uio/vfio intr/eventfd mapping */
1273 rte_intr_enable(intr_handle);
1275 /* enable support intr */
1276 ixgbe_enable_intr(eth_dev);
1278 /* initialize filter info */
1279 memset(filter_info, 0,
1280 sizeof(struct ixgbe_filter_info));
1282 /* initialize 5tuple filter list */
1283 TAILQ_INIT(&filter_info->fivetuple_list);
1285 /* initialize flow director filter list & hash */
1286 ixgbe_fdir_filter_init(eth_dev);
1288 /* initialize l2 tunnel filter list & hash */
1289 ixgbe_l2_tn_filter_init(eth_dev);
1291 /* initialize flow filter lists */
1292 ixgbe_filterlist_init();
1294 /* initialize bandwidth configuration info */
1295 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1297 /* initialize Traffic Manager configuration */
1298 ixgbe_tm_conf_init(eth_dev);
1304 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1306 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1307 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1308 struct ixgbe_hw *hw;
1312 PMD_INIT_FUNC_TRACE();
1314 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1317 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1319 if (hw->adapter_stopped == 0)
1320 ixgbe_dev_close(eth_dev);
1322 eth_dev->dev_ops = NULL;
1323 eth_dev->rx_pkt_burst = NULL;
1324 eth_dev->tx_pkt_burst = NULL;
1326 /* Unlock any pending hardware semaphore */
1327 ixgbe_swfw_lock_reset(hw);
1329 /* disable uio intr before callback unregister */
1330 rte_intr_disable(intr_handle);
1333 ret = rte_intr_callback_unregister(intr_handle,
1334 ixgbe_dev_interrupt_handler, eth_dev);
1337 } else if (ret != -EAGAIN) {
1339 "intr callback unregister failed: %d",
1344 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1346 /* cancel the delay handler before remove dev */
1347 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1349 /* cancel the link handler before remove dev */
1350 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev);
1352 /* uninitialize PF if max_vfs not zero */
1353 ixgbe_pf_host_uninit(eth_dev);
1355 /* remove all the fdir filters & hash */
1356 ixgbe_fdir_filter_uninit(eth_dev);
1358 /* remove all the L2 tunnel filters & hash */
1359 ixgbe_l2_tn_filter_uninit(eth_dev);
1361 /* Remove all ntuple filters of the device */
1362 ixgbe_ntuple_filter_uninit(eth_dev);
1364 /* clear all the filters list */
1365 ixgbe_filterlist_flush();
1367 /* Remove all Traffic Manager configuration */
1368 ixgbe_tm_conf_uninit(eth_dev);
1370 #ifdef RTE_LIBRTE_SECURITY
1371 rte_free(eth_dev->security_ctx);
1377 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1379 struct ixgbe_filter_info *filter_info =
1380 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1381 struct ixgbe_5tuple_filter *p_5tuple;
1383 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1384 TAILQ_REMOVE(&filter_info->fivetuple_list,
1389 memset(filter_info->fivetuple_mask, 0,
1390 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1395 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1397 struct ixgbe_hw_fdir_info *fdir_info =
1398 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1399 struct ixgbe_fdir_filter *fdir_filter;
1401 if (fdir_info->hash_map)
1402 rte_free(fdir_info->hash_map);
1403 if (fdir_info->hash_handle)
1404 rte_hash_free(fdir_info->hash_handle);
1406 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1407 TAILQ_REMOVE(&fdir_info->fdir_list,
1410 rte_free(fdir_filter);
1416 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1418 struct ixgbe_l2_tn_info *l2_tn_info =
1419 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1420 struct ixgbe_l2_tn_filter *l2_tn_filter;
1422 if (l2_tn_info->hash_map)
1423 rte_free(l2_tn_info->hash_map);
1424 if (l2_tn_info->hash_handle)
1425 rte_hash_free(l2_tn_info->hash_handle);
1427 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1428 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1431 rte_free(l2_tn_filter);
1437 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1439 struct ixgbe_hw_fdir_info *fdir_info =
1440 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1441 char fdir_hash_name[RTE_HASH_NAMESIZE];
1442 struct rte_hash_parameters fdir_hash_params = {
1443 .name = fdir_hash_name,
1444 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1445 .key_len = sizeof(union ixgbe_atr_input),
1446 .hash_func = rte_hash_crc,
1447 .hash_func_init_val = 0,
1448 .socket_id = rte_socket_id(),
1451 TAILQ_INIT(&fdir_info->fdir_list);
1452 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1453 "fdir_%s", eth_dev->device->name);
1454 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1455 if (!fdir_info->hash_handle) {
1456 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1459 fdir_info->hash_map = rte_zmalloc("ixgbe",
1460 sizeof(struct ixgbe_fdir_filter *) *
1461 IXGBE_MAX_FDIR_FILTER_NUM,
1463 if (!fdir_info->hash_map) {
1465 "Failed to allocate memory for fdir hash map!");
1468 fdir_info->mask_added = FALSE;
1473 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1475 struct ixgbe_l2_tn_info *l2_tn_info =
1476 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1477 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1478 struct rte_hash_parameters l2_tn_hash_params = {
1479 .name = l2_tn_hash_name,
1480 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1481 .key_len = sizeof(struct ixgbe_l2_tn_key),
1482 .hash_func = rte_hash_crc,
1483 .hash_func_init_val = 0,
1484 .socket_id = rte_socket_id(),
1487 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1488 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1489 "l2_tn_%s", eth_dev->device->name);
1490 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1491 if (!l2_tn_info->hash_handle) {
1492 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1495 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1496 sizeof(struct ixgbe_l2_tn_filter *) *
1497 IXGBE_MAX_L2_TN_FILTER_NUM,
1499 if (!l2_tn_info->hash_map) {
1501 "Failed to allocate memory for L2 TN hash map!");
1504 l2_tn_info->e_tag_en = FALSE;
1505 l2_tn_info->e_tag_fwd_en = FALSE;
1506 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1511 * Negotiate mailbox API version with the PF.
1512 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1513 * Then we try to negotiate starting with the most recent one.
1514 * If all negotiation attempts fail, then we will proceed with
1515 * the default one (ixgbe_mbox_api_10).
1518 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1522 /* start with highest supported, proceed down */
1523 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1531 i != RTE_DIM(sup_ver) &&
1532 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1538 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1542 /* Set Organizationally Unique Identifier (OUI) prefix. */
1543 mac_addr->addr_bytes[0] = 0x00;
1544 mac_addr->addr_bytes[1] = 0x09;
1545 mac_addr->addr_bytes[2] = 0xC0;
1546 /* Force indication of locally assigned MAC address. */
1547 mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1548 /* Generate the last 3 bytes of the MAC address with a random number. */
1549 random = rte_rand();
1550 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1554 * Virtual Function device init
1557 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1561 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1562 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1563 struct ixgbe_hw *hw =
1564 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1565 struct ixgbe_vfta *shadow_vfta =
1566 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1567 struct ixgbe_hwstrip *hwstrip =
1568 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1569 struct rte_ether_addr *perm_addr =
1570 (struct rte_ether_addr *)hw->mac.perm_addr;
1572 PMD_INIT_FUNC_TRACE();
1574 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1575 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1576 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1578 /* for secondary processes, we don't initialise any further as primary
1579 * has already done this work. Only check we don't need a different
1582 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1583 struct ixgbe_tx_queue *txq;
1584 /* TX queue function in primary, set by last queue initialized
1585 * Tx queue may not initialized by primary process
1587 if (eth_dev->data->tx_queues) {
1588 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1589 ixgbe_set_tx_function(eth_dev, txq);
1591 /* Use default TX function if we get here */
1592 PMD_INIT_LOG(NOTICE,
1593 "No TX queues configured yet. Using default TX function.");
1596 ixgbe_set_rx_function(eth_dev);
1601 rte_eth_copy_pci_info(eth_dev, pci_dev);
1603 hw->device_id = pci_dev->id.device_id;
1604 hw->vendor_id = pci_dev->id.vendor_id;
1605 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1607 /* initialize the vfta */
1608 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1610 /* initialize the hw strip bitmap*/
1611 memset(hwstrip, 0, sizeof(*hwstrip));
1613 /* Initialize the shared code (base driver) */
1614 diag = ixgbe_init_shared_code(hw);
1615 if (diag != IXGBE_SUCCESS) {
1616 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1620 /* init_mailbox_params */
1621 hw->mbx.ops.init_params(hw);
1623 /* Reset the hw statistics */
1624 ixgbevf_dev_stats_reset(eth_dev);
1626 /* Disable the interrupts for VF */
1627 ixgbevf_intr_disable(eth_dev);
1629 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1630 diag = hw->mac.ops.reset_hw(hw);
1633 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1634 * the underlying PF driver has not assigned a MAC address to the VF.
1635 * In this case, assign a random MAC address.
1637 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1638 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1640 * This error code will be propagated to the app by
1641 * rte_eth_dev_reset, so use a public error code rather than
1642 * the internal-only IXGBE_ERR_RESET_FAILED
1647 /* negotiate mailbox API version to use with the PF. */
1648 ixgbevf_negotiate_api(hw);
1650 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1651 ixgbevf_get_queues(hw, &tcs, &tc);
1653 /* Allocate memory for storing MAC addresses */
1654 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1655 hw->mac.num_rar_entries, 0);
1656 if (eth_dev->data->mac_addrs == NULL) {
1658 "Failed to allocate %u bytes needed to store "
1660 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1664 /* Generate a random MAC address, if none was assigned by PF. */
1665 if (rte_is_zero_ether_addr(perm_addr)) {
1666 generate_random_mac_addr(perm_addr);
1667 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1669 rte_free(eth_dev->data->mac_addrs);
1670 eth_dev->data->mac_addrs = NULL;
1673 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1674 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1675 "%02x:%02x:%02x:%02x:%02x:%02x",
1676 perm_addr->addr_bytes[0],
1677 perm_addr->addr_bytes[1],
1678 perm_addr->addr_bytes[2],
1679 perm_addr->addr_bytes[3],
1680 perm_addr->addr_bytes[4],
1681 perm_addr->addr_bytes[5]);
1684 /* Copy the permanent MAC address */
1685 rte_ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1687 /* reset the hardware with the new settings */
1688 diag = hw->mac.ops.start_hw(hw);
1694 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1698 rte_intr_callback_register(intr_handle,
1699 ixgbevf_dev_interrupt_handler, eth_dev);
1700 rte_intr_enable(intr_handle);
1701 ixgbevf_intr_enable(eth_dev);
1703 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1704 eth_dev->data->port_id, pci_dev->id.vendor_id,
1705 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1710 /* Virtual Function device uninit */
1713 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1716 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1717 struct ixgbe_hw *hw;
1719 PMD_INIT_FUNC_TRACE();
1721 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1724 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1726 if (hw->adapter_stopped == 0)
1727 ixgbevf_dev_close(eth_dev);
1729 eth_dev->dev_ops = NULL;
1730 eth_dev->rx_pkt_burst = NULL;
1731 eth_dev->tx_pkt_burst = NULL;
1733 /* Disable the interrupts for VF */
1734 ixgbevf_intr_disable(eth_dev);
1736 rte_intr_disable(intr_handle);
1737 rte_intr_callback_unregister(intr_handle,
1738 ixgbevf_dev_interrupt_handler, eth_dev);
1744 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1745 struct rte_pci_device *pci_dev)
1747 char name[RTE_ETH_NAME_MAX_LEN];
1748 struct rte_eth_dev *pf_ethdev;
1749 struct rte_eth_devargs eth_da;
1752 if (pci_dev->device.devargs) {
1753 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1758 memset(ð_da, 0, sizeof(eth_da));
1760 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1761 sizeof(struct ixgbe_adapter),
1762 eth_dev_pci_specific_init, pci_dev,
1763 eth_ixgbe_dev_init, NULL);
1765 if (retval || eth_da.nb_representor_ports < 1)
1768 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1769 if (pf_ethdev == NULL)
1772 /* probe VF representor ports */
1773 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1774 struct ixgbe_vf_info *vfinfo;
1775 struct ixgbe_vf_representor representor;
1777 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1778 pf_ethdev->data->dev_private);
1779 if (vfinfo == NULL) {
1781 "no virtual functions supported by PF");
1785 representor.vf_id = eth_da.representor_ports[i];
1786 representor.switch_domain_id = vfinfo->switch_domain_id;
1787 representor.pf_ethdev = pf_ethdev;
1789 /* representor port net_bdf_port */
1790 snprintf(name, sizeof(name), "net_%s_representor_%d",
1791 pci_dev->device.name,
1792 eth_da.representor_ports[i]);
1794 retval = rte_eth_dev_create(&pci_dev->device, name,
1795 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1796 ixgbe_vf_representor_init, &representor);
1799 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1800 "representor %s.", name);
1806 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1808 struct rte_eth_dev *ethdev;
1810 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1814 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1815 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1817 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1820 static struct rte_pci_driver rte_ixgbe_pmd = {
1821 .id_table = pci_id_ixgbe_map,
1822 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1823 RTE_PCI_DRV_IOVA_AS_VA,
1824 .probe = eth_ixgbe_pci_probe,
1825 .remove = eth_ixgbe_pci_remove,
1828 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1829 struct rte_pci_device *pci_dev)
1831 return rte_eth_dev_pci_generic_probe(pci_dev,
1832 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1835 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1837 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1841 * virtual function driver struct
1843 static struct rte_pci_driver rte_ixgbevf_pmd = {
1844 .id_table = pci_id_ixgbevf_map,
1845 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1846 .probe = eth_ixgbevf_pci_probe,
1847 .remove = eth_ixgbevf_pci_remove,
1851 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1853 struct ixgbe_hw *hw =
1854 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855 struct ixgbe_vfta *shadow_vfta =
1856 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1861 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1862 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1863 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1868 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1870 /* update local VFTA copy */
1871 shadow_vfta->vfta[vid_idx] = vfta;
1877 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1880 ixgbe_vlan_hw_strip_enable(dev, queue);
1882 ixgbe_vlan_hw_strip_disable(dev, queue);
1886 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1887 enum rte_vlan_type vlan_type,
1890 struct ixgbe_hw *hw =
1891 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1896 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1897 qinq &= IXGBE_DMATXCTL_GDV;
1899 switch (vlan_type) {
1900 case ETH_VLAN_TYPE_INNER:
1902 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1903 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1904 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1905 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1906 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1907 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1908 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1911 PMD_DRV_LOG(ERR, "Inner type is not supported"
1915 case ETH_VLAN_TYPE_OUTER:
1917 /* Only the high 16-bits is valid */
1918 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1919 IXGBE_EXVET_VET_EXT_SHIFT);
1921 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1922 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1923 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1924 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1925 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1926 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1927 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1933 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1941 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1943 struct ixgbe_hw *hw =
1944 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1947 PMD_INIT_FUNC_TRACE();
1949 /* Filter Table Disable */
1950 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1951 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1953 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1957 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1959 struct ixgbe_hw *hw =
1960 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1961 struct ixgbe_vfta *shadow_vfta =
1962 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1966 PMD_INIT_FUNC_TRACE();
1968 /* Filter Table Enable */
1969 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1970 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1971 vlnctrl |= IXGBE_VLNCTRL_VFE;
1973 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1975 /* write whatever is in local vfta copy */
1976 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1977 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1981 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1983 struct ixgbe_hwstrip *hwstrip =
1984 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1985 struct ixgbe_rx_queue *rxq;
1987 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1991 IXGBE_SET_HWSTRIP(hwstrip, queue);
1993 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1995 if (queue >= dev->data->nb_rx_queues)
1998 rxq = dev->data->rx_queues[queue];
2001 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2002 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2004 rxq->vlan_flags = PKT_RX_VLAN;
2005 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2010 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2012 struct ixgbe_hw *hw =
2013 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2016 PMD_INIT_FUNC_TRACE();
2018 if (hw->mac.type == ixgbe_mac_82598EB) {
2019 /* No queue level support */
2020 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2024 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2025 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2026 ctrl &= ~IXGBE_RXDCTL_VME;
2027 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2029 /* record those setting for HW strip per queue */
2030 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2034 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2036 struct ixgbe_hw *hw =
2037 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040 PMD_INIT_FUNC_TRACE();
2042 if (hw->mac.type == ixgbe_mac_82598EB) {
2043 /* No queue level supported */
2044 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2048 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2049 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2050 ctrl |= IXGBE_RXDCTL_VME;
2051 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2053 /* record those setting for HW strip per queue */
2054 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2058 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2060 struct ixgbe_hw *hw =
2061 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064 PMD_INIT_FUNC_TRACE();
2066 /* DMATXCTRL: Geric Double VLAN Disable */
2067 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2068 ctrl &= ~IXGBE_DMATXCTL_GDV;
2069 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2071 /* CTRL_EXT: Global Double VLAN Disable */
2072 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2073 ctrl &= ~IXGBE_EXTENDED_VLAN;
2074 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2079 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2081 struct ixgbe_hw *hw =
2082 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085 PMD_INIT_FUNC_TRACE();
2087 /* DMATXCTRL: Geric Double VLAN Enable */
2088 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2089 ctrl |= IXGBE_DMATXCTL_GDV;
2090 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2092 /* CTRL_EXT: Global Double VLAN Enable */
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2094 ctrl |= IXGBE_EXTENDED_VLAN;
2095 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2097 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2098 if (hw->mac.type == ixgbe_mac_X550 ||
2099 hw->mac.type == ixgbe_mac_X550EM_x ||
2100 hw->mac.type == ixgbe_mac_X550EM_a) {
2101 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2102 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2103 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2107 * VET EXT field in the EXVET register = 0x8100 by default
2108 * So no need to change. Same to VT field of DMATXCTL register
2113 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2115 struct ixgbe_hw *hw =
2116 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2117 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2120 struct ixgbe_rx_queue *rxq;
2123 PMD_INIT_FUNC_TRACE();
2125 if (hw->mac.type == ixgbe_mac_82598EB) {
2126 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2127 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2128 ctrl |= IXGBE_VLNCTRL_VME;
2129 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2131 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2132 ctrl &= ~IXGBE_VLNCTRL_VME;
2133 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2137 * Other 10G NIC, the VLAN strip can be setup
2138 * per queue in RXDCTL
2140 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2141 rxq = dev->data->rx_queues[i];
2142 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2143 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2144 ctrl |= IXGBE_RXDCTL_VME;
2147 ctrl &= ~IXGBE_RXDCTL_VME;
2150 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2152 /* record those setting for HW strip per queue */
2153 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2159 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2162 struct rte_eth_rxmode *rxmode;
2163 struct ixgbe_rx_queue *rxq;
2165 if (mask & ETH_VLAN_STRIP_MASK) {
2166 rxmode = &dev->data->dev_conf.rxmode;
2167 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2168 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2169 rxq = dev->data->rx_queues[i];
2170 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2173 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2174 rxq = dev->data->rx_queues[i];
2175 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2181 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2183 struct rte_eth_rxmode *rxmode;
2184 rxmode = &dev->data->dev_conf.rxmode;
2186 if (mask & ETH_VLAN_STRIP_MASK) {
2187 ixgbe_vlan_hw_strip_config(dev);
2190 if (mask & ETH_VLAN_FILTER_MASK) {
2191 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2192 ixgbe_vlan_hw_filter_enable(dev);
2194 ixgbe_vlan_hw_filter_disable(dev);
2197 if (mask & ETH_VLAN_EXTEND_MASK) {
2198 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2199 ixgbe_vlan_hw_extend_enable(dev);
2201 ixgbe_vlan_hw_extend_disable(dev);
2208 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2210 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2212 ixgbe_vlan_offload_config(dev, mask);
2218 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2220 struct ixgbe_hw *hw =
2221 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2222 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2223 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2225 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2226 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2230 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2232 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2237 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2240 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2246 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2247 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2248 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2249 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2254 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2256 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2257 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2259 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2261 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2262 /* check multi-queue mode */
2263 switch (dev_conf->rxmode.mq_mode) {
2264 case ETH_MQ_RX_VMDQ_DCB:
2265 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2267 case ETH_MQ_RX_VMDQ_DCB_RSS:
2268 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2269 PMD_INIT_LOG(ERR, "SRIOV active,"
2270 " unsupported mq_mode rx %d.",
2271 dev_conf->rxmode.mq_mode);
2274 case ETH_MQ_RX_VMDQ_RSS:
2275 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2276 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2277 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2278 PMD_INIT_LOG(ERR, "SRIOV is active,"
2279 " invalid queue number"
2280 " for VMDQ RSS, allowed"
2281 " value are 1, 2 or 4.");
2285 case ETH_MQ_RX_VMDQ_ONLY:
2286 case ETH_MQ_RX_NONE:
2287 /* if nothing mq mode configure, use default scheme */
2288 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2290 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2291 /* SRIOV only works in VMDq enable mode */
2292 PMD_INIT_LOG(ERR, "SRIOV is active,"
2293 " wrong mq_mode rx %d.",
2294 dev_conf->rxmode.mq_mode);
2298 switch (dev_conf->txmode.mq_mode) {
2299 case ETH_MQ_TX_VMDQ_DCB:
2300 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2301 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2303 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2304 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2308 /* check valid queue number */
2309 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2310 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2311 PMD_INIT_LOG(ERR, "SRIOV is active,"
2312 " nb_rx_q=%d nb_tx_q=%d queue number"
2313 " must be less than or equal to %d.",
2315 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2319 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2320 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2324 /* check configuration for vmdb+dcb mode */
2325 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2326 const struct rte_eth_vmdq_dcb_conf *conf;
2328 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2329 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2330 IXGBE_VMDQ_DCB_NB_QUEUES);
2333 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2334 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2335 conf->nb_queue_pools == ETH_32_POOLS)) {
2336 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2337 " nb_queue_pools must be %d or %d.",
2338 ETH_16_POOLS, ETH_32_POOLS);
2342 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2343 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2345 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2346 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2347 IXGBE_VMDQ_DCB_NB_QUEUES);
2350 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2351 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2352 conf->nb_queue_pools == ETH_32_POOLS)) {
2353 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2354 " nb_queue_pools != %d and"
2355 " nb_queue_pools != %d.",
2356 ETH_16_POOLS, ETH_32_POOLS);
2361 /* For DCB mode check our configuration before we go further */
2362 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2363 const struct rte_eth_dcb_rx_conf *conf;
2365 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2366 if (!(conf->nb_tcs == ETH_4_TCS ||
2367 conf->nb_tcs == ETH_8_TCS)) {
2368 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2369 " and nb_tcs != %d.",
2370 ETH_4_TCS, ETH_8_TCS);
2375 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2376 const struct rte_eth_dcb_tx_conf *conf;
2378 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2379 if (!(conf->nb_tcs == ETH_4_TCS ||
2380 conf->nb_tcs == ETH_8_TCS)) {
2381 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2382 " and nb_tcs != %d.",
2383 ETH_4_TCS, ETH_8_TCS);
2389 * When DCB/VT is off, maximum number of queues changes,
2390 * except for 82598EB, which remains constant.
2392 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2393 hw->mac.type != ixgbe_mac_82598EB) {
2394 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2396 "Neither VT nor DCB are enabled, "
2398 IXGBE_NONE_MODE_TX_NB_QUEUES);
2407 ixgbe_dev_configure(struct rte_eth_dev *dev)
2409 struct ixgbe_interrupt *intr =
2410 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2411 struct ixgbe_adapter *adapter =
2412 (struct ixgbe_adapter *)dev->data->dev_private;
2415 PMD_INIT_FUNC_TRACE();
2416 /* multipe queue mode checking */
2417 ret = ixgbe_check_mq_mode(dev);
2419 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2424 /* set flag to update link status after init */
2425 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2428 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2429 * allocation or vector Rx preconditions we will reset it.
2431 adapter->rx_bulk_alloc_allowed = true;
2432 adapter->rx_vec_allowed = true;
2438 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2440 struct ixgbe_hw *hw =
2441 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2442 struct ixgbe_interrupt *intr =
2443 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2446 /* only set up it on X550EM_X */
2447 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2448 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2449 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2450 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2451 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2452 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2457 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2458 uint16_t tx_rate, uint64_t q_msk)
2460 struct ixgbe_hw *hw;
2461 struct ixgbe_vf_info *vfinfo;
2462 struct rte_eth_link link;
2463 uint8_t nb_q_per_pool;
2464 uint32_t queue_stride;
2465 uint32_t queue_idx, idx = 0, vf_idx;
2467 uint16_t total_rate = 0;
2468 struct rte_pci_device *pci_dev;
2470 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2471 rte_eth_link_get_nowait(dev->data->port_id, &link);
2473 if (vf >= pci_dev->max_vfs)
2476 if (tx_rate > link.link_speed)
2482 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2483 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2484 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2485 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2486 queue_idx = vf * queue_stride;
2487 queue_end = queue_idx + nb_q_per_pool - 1;
2488 if (queue_end >= hw->mac.max_tx_queues)
2492 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2495 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2497 total_rate += vfinfo[vf_idx].tx_rate[idx];
2503 /* Store tx_rate for this vf. */
2504 for (idx = 0; idx < nb_q_per_pool; idx++) {
2505 if (((uint64_t)0x1 << idx) & q_msk) {
2506 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2507 vfinfo[vf].tx_rate[idx] = tx_rate;
2508 total_rate += tx_rate;
2512 if (total_rate > dev->data->dev_link.link_speed) {
2513 /* Reset stored TX rate of the VF if it causes exceed
2516 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2520 /* Set RTTBCNRC of each queue/pool for vf X */
2521 for (; queue_idx <= queue_end; queue_idx++) {
2523 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2531 * Configure device link speed and setup link.
2532 * It returns 0 on success.
2535 ixgbe_dev_start(struct rte_eth_dev *dev)
2537 struct ixgbe_hw *hw =
2538 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539 struct ixgbe_vf_info *vfinfo =
2540 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2541 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2542 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2543 uint32_t intr_vector = 0;
2544 int err, link_up = 0, negotiate = 0;
2546 uint32_t allowed_speeds = 0;
2550 uint32_t *link_speeds;
2551 struct ixgbe_tm_conf *tm_conf =
2552 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2554 PMD_INIT_FUNC_TRACE();
2556 /* IXGBE devices don't support:
2557 * - half duplex (checked afterwards for valid speeds)
2558 * - fixed speed: TODO implement
2560 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2562 "Invalid link_speeds for port %u, fix speed not supported",
2563 dev->data->port_id);
2567 /* Stop the link setup handler before resetting the HW. */
2568 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2570 /* disable uio/vfio intr/eventfd mapping */
2571 rte_intr_disable(intr_handle);
2574 hw->adapter_stopped = 0;
2575 ixgbe_stop_adapter(hw);
2577 /* reinitialize adapter
2578 * this calls reset and start
2580 status = ixgbe_pf_reset_hw(hw);
2583 hw->mac.ops.start_hw(hw);
2584 hw->mac.get_link_status = true;
2586 /* configure PF module if SRIOV enabled */
2587 ixgbe_pf_host_configure(dev);
2589 ixgbe_dev_phy_intr_setup(dev);
2591 /* check and configure queue intr-vector mapping */
2592 if ((rte_intr_cap_multiple(intr_handle) ||
2593 !RTE_ETH_DEV_SRIOV(dev).active) &&
2594 dev->data->dev_conf.intr_conf.rxq != 0) {
2595 intr_vector = dev->data->nb_rx_queues;
2596 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2597 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2598 IXGBE_MAX_INTR_QUEUE_NUM);
2601 if (rte_intr_efd_enable(intr_handle, intr_vector))
2605 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2606 intr_handle->intr_vec =
2607 rte_zmalloc("intr_vec",
2608 dev->data->nb_rx_queues * sizeof(int), 0);
2609 if (intr_handle->intr_vec == NULL) {
2610 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2611 " intr_vec", dev->data->nb_rx_queues);
2616 /* confiugre msix for sleep until rx interrupt */
2617 ixgbe_configure_msix(dev);
2619 /* initialize transmission unit */
2620 ixgbe_dev_tx_init(dev);
2622 /* This can fail when allocating mbufs for descriptor rings */
2623 err = ixgbe_dev_rx_init(dev);
2625 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2629 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2630 ETH_VLAN_EXTEND_MASK;
2631 err = ixgbe_vlan_offload_config(dev, mask);
2633 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2637 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2638 /* Enable vlan filtering for VMDq */
2639 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2642 /* Configure DCB hw */
2643 ixgbe_configure_dcb(dev);
2645 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2646 err = ixgbe_fdir_configure(dev);
2651 /* Restore vf rate limit */
2652 if (vfinfo != NULL) {
2653 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2654 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2655 if (vfinfo[vf].tx_rate[idx] != 0)
2656 ixgbe_set_vf_rate_limit(
2658 vfinfo[vf].tx_rate[idx],
2662 ixgbe_restore_statistics_mapping(dev);
2664 err = ixgbe_dev_rxtx_start(dev);
2666 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2670 /* Skip link setup if loopback mode is enabled. */
2671 if (dev->data->dev_conf.lpbk_mode != 0) {
2672 err = ixgbe_check_supported_loopback_mode(dev);
2674 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2677 goto skip_link_setup;
2681 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2682 err = hw->mac.ops.setup_sfp(hw);
2687 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2688 /* Turn on the copper */
2689 ixgbe_set_phy_power(hw, true);
2691 /* Turn on the laser */
2692 ixgbe_enable_tx_laser(hw);
2695 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2698 dev->data->dev_link.link_status = link_up;
2700 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2704 switch (hw->mac.type) {
2705 case ixgbe_mac_X550:
2706 case ixgbe_mac_X550EM_x:
2707 case ixgbe_mac_X550EM_a:
2708 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2709 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2711 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2712 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2713 allowed_speeds = ETH_LINK_SPEED_10M |
2714 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2717 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2721 link_speeds = &dev->data->dev_conf.link_speeds;
2722 if (*link_speeds & ~allowed_speeds) {
2723 PMD_INIT_LOG(ERR, "Invalid link setting");
2728 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2729 switch (hw->mac.type) {
2730 case ixgbe_mac_82598EB:
2731 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2733 case ixgbe_mac_82599EB:
2734 case ixgbe_mac_X540:
2735 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2737 case ixgbe_mac_X550:
2738 case ixgbe_mac_X550EM_x:
2739 case ixgbe_mac_X550EM_a:
2740 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2743 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2746 if (*link_speeds & ETH_LINK_SPEED_10G)
2747 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2748 if (*link_speeds & ETH_LINK_SPEED_5G)
2749 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2750 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2751 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2752 if (*link_speeds & ETH_LINK_SPEED_1G)
2753 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2754 if (*link_speeds & ETH_LINK_SPEED_100M)
2755 speed |= IXGBE_LINK_SPEED_100_FULL;
2756 if (*link_speeds & ETH_LINK_SPEED_10M)
2757 speed |= IXGBE_LINK_SPEED_10_FULL;
2760 err = ixgbe_setup_link(hw, speed, link_up);
2766 if (rte_intr_allow_others(intr_handle)) {
2767 /* check if lsc interrupt is enabled */
2768 if (dev->data->dev_conf.intr_conf.lsc != 0)
2769 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2771 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2772 ixgbe_dev_macsec_interrupt_setup(dev);
2774 rte_intr_callback_unregister(intr_handle,
2775 ixgbe_dev_interrupt_handler, dev);
2776 if (dev->data->dev_conf.intr_conf.lsc != 0)
2777 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2778 " no intr multiplex");
2781 /* check if rxq interrupt is enabled */
2782 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2783 rte_intr_dp_is_en(intr_handle))
2784 ixgbe_dev_rxq_interrupt_setup(dev);
2786 /* enable uio/vfio intr/eventfd mapping */
2787 rte_intr_enable(intr_handle);
2789 /* resume enabled intr since hw reset */
2790 ixgbe_enable_intr(dev);
2791 ixgbe_l2_tunnel_conf(dev);
2792 ixgbe_filter_restore(dev);
2794 if (tm_conf->root && !tm_conf->committed)
2795 PMD_DRV_LOG(WARNING,
2796 "please call hierarchy_commit() "
2797 "before starting the port");
2800 * Update link status right before return, because it may
2801 * start link configuration process in a separate thread.
2803 ixgbe_dev_link_update(dev, 0);
2808 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2809 ixgbe_dev_clear_queues(dev);
2814 * Stop device: disable rx and tx functions to allow for reconfiguring.
2817 ixgbe_dev_stop(struct rte_eth_dev *dev)
2819 struct rte_eth_link link;
2820 struct ixgbe_adapter *adapter =
2821 (struct ixgbe_adapter *)dev->data->dev_private;
2822 struct ixgbe_hw *hw =
2823 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824 struct ixgbe_vf_info *vfinfo =
2825 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2826 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2827 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2829 struct ixgbe_tm_conf *tm_conf =
2830 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2832 PMD_INIT_FUNC_TRACE();
2834 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2836 /* disable interrupts */
2837 ixgbe_disable_intr(hw);
2840 ixgbe_pf_reset_hw(hw);
2841 hw->adapter_stopped = 0;
2844 ixgbe_stop_adapter(hw);
2846 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2847 vfinfo[vf].clear_to_send = false;
2849 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2850 /* Turn off the copper */
2851 ixgbe_set_phy_power(hw, false);
2853 /* Turn off the laser */
2854 ixgbe_disable_tx_laser(hw);
2857 ixgbe_dev_clear_queues(dev);
2859 /* Clear stored conf */
2860 dev->data->scattered_rx = 0;
2863 /* Clear recorded link status */
2864 memset(&link, 0, sizeof(link));
2865 rte_eth_linkstatus_set(dev, &link);
2867 if (!rte_intr_allow_others(intr_handle))
2868 /* resume to the default handler */
2869 rte_intr_callback_register(intr_handle,
2870 ixgbe_dev_interrupt_handler,
2873 /* Clean datapath event and queue/vec mapping */
2874 rte_intr_efd_disable(intr_handle);
2875 if (intr_handle->intr_vec != NULL) {
2876 rte_free(intr_handle->intr_vec);
2877 intr_handle->intr_vec = NULL;
2880 /* reset hierarchy commit */
2881 tm_conf->committed = false;
2883 adapter->rss_reta_updated = 0;
2887 * Set device link up: enable tx.
2890 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2892 struct ixgbe_hw *hw =
2893 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894 if (hw->mac.type == ixgbe_mac_82599EB) {
2895 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2896 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2897 /* Not suported in bypass mode */
2898 PMD_INIT_LOG(ERR, "Set link up is not supported "
2899 "by device id 0x%x", hw->device_id);
2905 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2906 /* Turn on the copper */
2907 ixgbe_set_phy_power(hw, true);
2909 /* Turn on the laser */
2910 ixgbe_enable_tx_laser(hw);
2917 * Set device link down: disable tx.
2920 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2922 struct ixgbe_hw *hw =
2923 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2924 if (hw->mac.type == ixgbe_mac_82599EB) {
2925 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2926 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2927 /* Not suported in bypass mode */
2928 PMD_INIT_LOG(ERR, "Set link down is not supported "
2929 "by device id 0x%x", hw->device_id);
2935 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2936 /* Turn off the copper */
2937 ixgbe_set_phy_power(hw, false);
2939 /* Turn off the laser */
2940 ixgbe_disable_tx_laser(hw);
2947 * Reset and stop device.
2950 ixgbe_dev_close(struct rte_eth_dev *dev)
2952 struct ixgbe_hw *hw =
2953 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955 PMD_INIT_FUNC_TRACE();
2957 ixgbe_pf_reset_hw(hw);
2959 ixgbe_dev_stop(dev);
2960 hw->adapter_stopped = 1;
2962 ixgbe_dev_free_queues(dev);
2964 ixgbe_disable_pcie_master(hw);
2966 /* reprogram the RAR[0] in case user changed it. */
2967 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2974 ixgbe_dev_reset(struct rte_eth_dev *dev)
2978 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2979 * its VF to make them align with it. The detailed notification
2980 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2981 * To avoid unexpected behavior in VF, currently reset of PF with
2982 * SR-IOV activation is not supported. It might be supported later.
2984 if (dev->data->sriov.active)
2987 ret = eth_ixgbe_dev_uninit(dev);
2991 ret = eth_ixgbe_dev_init(dev, NULL);
2997 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2998 struct ixgbe_hw_stats *hw_stats,
2999 struct ixgbe_macsec_stats *macsec_stats,
3000 uint64_t *total_missed_rx, uint64_t *total_qbrc,
3001 uint64_t *total_qprc, uint64_t *total_qprdc)
3003 uint32_t bprc, lxon, lxoff, total;
3004 uint32_t delta_gprc = 0;
3006 /* Workaround for RX byte count not including CRC bytes when CRC
3007 * strip is enabled. CRC bytes are removed from counters when crc_strip
3010 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3011 IXGBE_HLREG0_RXCRCSTRP);
3013 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3014 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3015 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3016 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3018 for (i = 0; i < 8; i++) {
3019 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3021 /* global total per queue */
3022 hw_stats->mpc[i] += mp;
3023 /* Running comprehensive total for stats display */
3024 *total_missed_rx += hw_stats->mpc[i];
3025 if (hw->mac.type == ixgbe_mac_82598EB) {
3026 hw_stats->rnbc[i] +=
3027 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3028 hw_stats->pxonrxc[i] +=
3029 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3030 hw_stats->pxoffrxc[i] +=
3031 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3033 hw_stats->pxonrxc[i] +=
3034 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3035 hw_stats->pxoffrxc[i] +=
3036 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3037 hw_stats->pxon2offc[i] +=
3038 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3040 hw_stats->pxontxc[i] +=
3041 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3042 hw_stats->pxofftxc[i] +=
3043 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3045 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3046 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3047 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3048 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3050 delta_gprc += delta_qprc;
3052 hw_stats->qprc[i] += delta_qprc;
3053 hw_stats->qptc[i] += delta_qptc;
3055 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3056 hw_stats->qbrc[i] +=
3057 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3059 hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3061 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3062 hw_stats->qbtc[i] +=
3063 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3065 hw_stats->qprdc[i] += delta_qprdc;
3066 *total_qprdc += hw_stats->qprdc[i];
3068 *total_qprc += hw_stats->qprc[i];
3069 *total_qbrc += hw_stats->qbrc[i];
3071 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3072 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3073 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3076 * An errata states that gprc actually counts good + missed packets:
3077 * Workaround to set gprc to summated queue packet receives
3079 hw_stats->gprc = *total_qprc;
3081 if (hw->mac.type != ixgbe_mac_82598EB) {
3082 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3083 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3084 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3085 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3086 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3087 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3088 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3089 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3091 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3092 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3093 /* 82598 only has a counter in the high register */
3094 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3095 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3096 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3098 uint64_t old_tpr = hw_stats->tpr;
3100 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3101 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3104 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3106 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3107 hw_stats->gptc += delta_gptc;
3108 hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3109 hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3112 * Workaround: mprc hardware is incorrectly counting
3113 * broadcasts, so for now we subtract those.
3115 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3116 hw_stats->bprc += bprc;
3117 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3118 if (hw->mac.type == ixgbe_mac_82598EB)
3119 hw_stats->mprc -= bprc;
3121 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3122 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3123 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3124 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3125 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3126 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3128 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3129 hw_stats->lxontxc += lxon;
3130 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3131 hw_stats->lxofftxc += lxoff;
3132 total = lxon + lxoff;
3134 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3135 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3136 hw_stats->gptc -= total;
3137 hw_stats->mptc -= total;
3138 hw_stats->ptc64 -= total;
3139 hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3141 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3142 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3143 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3144 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3145 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3146 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3147 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3148 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3149 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3150 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3151 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3152 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3153 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3154 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3155 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3156 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3157 /* Only read FCOE on 82599 */
3158 if (hw->mac.type != ixgbe_mac_82598EB) {
3159 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3160 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3161 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3162 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3163 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3166 /* Flow Director Stats registers */
3167 if (hw->mac.type != ixgbe_mac_82598EB) {
3168 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3169 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3170 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3171 IXGBE_FDIRUSTAT) & 0xFFFF;
3172 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3173 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3174 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3175 IXGBE_FDIRFSTAT) & 0xFFFF;
3176 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3177 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3179 /* MACsec Stats registers */
3180 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3181 macsec_stats->out_pkts_encrypted +=
3182 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3183 macsec_stats->out_pkts_protected +=
3184 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3185 macsec_stats->out_octets_encrypted +=
3186 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3187 macsec_stats->out_octets_protected +=
3188 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3189 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3190 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3191 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3192 macsec_stats->in_pkts_unknownsci +=
3193 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3194 macsec_stats->in_octets_decrypted +=
3195 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3196 macsec_stats->in_octets_validated +=
3197 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3198 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3199 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3200 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3201 for (i = 0; i < 2; i++) {
3202 macsec_stats->in_pkts_ok +=
3203 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3204 macsec_stats->in_pkts_invalid +=
3205 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3206 macsec_stats->in_pkts_notvalid +=
3207 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3209 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3210 macsec_stats->in_pkts_notusingsa +=
3211 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3215 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3218 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3220 struct ixgbe_hw *hw =
3221 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3222 struct ixgbe_hw_stats *hw_stats =
3223 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3224 struct ixgbe_macsec_stats *macsec_stats =
3225 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3226 dev->data->dev_private);
3227 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3230 total_missed_rx = 0;
3235 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3236 &total_qbrc, &total_qprc, &total_qprdc);
3241 /* Fill out the rte_eth_stats statistics structure */
3242 stats->ipackets = total_qprc;
3243 stats->ibytes = total_qbrc;
3244 stats->opackets = hw_stats->gptc;
3245 stats->obytes = hw_stats->gotc;
3247 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3248 stats->q_ipackets[i] = hw_stats->qprc[i];
3249 stats->q_opackets[i] = hw_stats->qptc[i];
3250 stats->q_ibytes[i] = hw_stats->qbrc[i];
3251 stats->q_obytes[i] = hw_stats->qbtc[i];
3252 stats->q_errors[i] = hw_stats->qprdc[i];
3256 stats->imissed = total_missed_rx;
3257 stats->ierrors = hw_stats->crcerrs +
3274 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3276 struct ixgbe_hw_stats *stats =
3277 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3279 /* HW registers are cleared on read */
3280 ixgbe_dev_stats_get(dev, NULL);
3282 /* Reset software totals */
3283 memset(stats, 0, sizeof(*stats));
3286 /* This function calculates the number of xstats based on the current config */
3288 ixgbe_xstats_calc_num(void) {
3289 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3290 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3291 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3294 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3295 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3297 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3298 unsigned stat, i, count;
3300 if (xstats_names != NULL) {
3303 /* Note: limit >= cnt_stats checked upstream
3304 * in rte_eth_xstats_names()
3307 /* Extended stats from ixgbe_hw_stats */
3308 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3309 strlcpy(xstats_names[count].name,
3310 rte_ixgbe_stats_strings[i].name,
3311 sizeof(xstats_names[count].name));
3316 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3317 strlcpy(xstats_names[count].name,
3318 rte_ixgbe_macsec_strings[i].name,
3319 sizeof(xstats_names[count].name));
3323 /* RX Priority Stats */
3324 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3325 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3326 snprintf(xstats_names[count].name,
3327 sizeof(xstats_names[count].name),
3328 "rx_priority%u_%s", i,
3329 rte_ixgbe_rxq_strings[stat].name);
3334 /* TX Priority Stats */
3335 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3336 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3337 snprintf(xstats_names[count].name,
3338 sizeof(xstats_names[count].name),
3339 "tx_priority%u_%s", i,
3340 rte_ixgbe_txq_strings[stat].name);
3348 static int ixgbe_dev_xstats_get_names_by_id(
3349 struct rte_eth_dev *dev,
3350 struct rte_eth_xstat_name *xstats_names,
3351 const uint64_t *ids,
3355 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3356 unsigned int stat, i, count;
3358 if (xstats_names != NULL) {
3361 /* Note: limit >= cnt_stats checked upstream
3362 * in rte_eth_xstats_names()
3365 /* Extended stats from ixgbe_hw_stats */
3366 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3367 strlcpy(xstats_names[count].name,
3368 rte_ixgbe_stats_strings[i].name,
3369 sizeof(xstats_names[count].name));
3374 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3375 strlcpy(xstats_names[count].name,
3376 rte_ixgbe_macsec_strings[i].name,
3377 sizeof(xstats_names[count].name));
3381 /* RX Priority Stats */
3382 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3383 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3384 snprintf(xstats_names[count].name,
3385 sizeof(xstats_names[count].name),
3386 "rx_priority%u_%s", i,
3387 rte_ixgbe_rxq_strings[stat].name);
3392 /* TX Priority Stats */
3393 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3394 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3395 snprintf(xstats_names[count].name,
3396 sizeof(xstats_names[count].name),
3397 "tx_priority%u_%s", i,
3398 rte_ixgbe_txq_strings[stat].name);
3407 uint16_t size = ixgbe_xstats_calc_num();
3408 struct rte_eth_xstat_name xstats_names_copy[size];
3410 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3413 for (i = 0; i < limit; i++) {
3414 if (ids[i] >= size) {
3415 PMD_INIT_LOG(ERR, "id value isn't valid");
3418 strcpy(xstats_names[i].name,
3419 xstats_names_copy[ids[i]].name);
3424 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3425 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3429 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3432 if (xstats_names != NULL)
3433 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3434 strlcpy(xstats_names[i].name,
3435 rte_ixgbevf_stats_strings[i].name,
3436 sizeof(xstats_names[i].name));
3437 return IXGBEVF_NB_XSTATS;
3441 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3444 struct ixgbe_hw *hw =
3445 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3446 struct ixgbe_hw_stats *hw_stats =
3447 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3448 struct ixgbe_macsec_stats *macsec_stats =
3449 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3450 dev->data->dev_private);
3451 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3452 unsigned i, stat, count = 0;
3454 count = ixgbe_xstats_calc_num();
3459 total_missed_rx = 0;
3464 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3465 &total_qbrc, &total_qprc, &total_qprdc);
3467 /* If this is a reset xstats is NULL, and we have cleared the
3468 * registers by reading them.
3473 /* Extended stats from ixgbe_hw_stats */
3475 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3476 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3477 rte_ixgbe_stats_strings[i].offset);
3478 xstats[count].id = count;
3483 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3484 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3485 rte_ixgbe_macsec_strings[i].offset);
3486 xstats[count].id = count;
3490 /* RX Priority Stats */
3491 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3492 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3493 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3494 rte_ixgbe_rxq_strings[stat].offset +
3495 (sizeof(uint64_t) * i));
3496 xstats[count].id = count;
3501 /* TX Priority Stats */
3502 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3503 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3504 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3505 rte_ixgbe_txq_strings[stat].offset +
3506 (sizeof(uint64_t) * i));
3507 xstats[count].id = count;
3515 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3516 uint64_t *values, unsigned int n)
3519 struct ixgbe_hw *hw =
3520 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3521 struct ixgbe_hw_stats *hw_stats =
3522 IXGBE_DEV_PRIVATE_TO_STATS(
3523 dev->data->dev_private);
3524 struct ixgbe_macsec_stats *macsec_stats =
3525 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3526 dev->data->dev_private);
3527 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3528 unsigned int i, stat, count = 0;
3530 count = ixgbe_xstats_calc_num();
3532 if (!ids && n < count)
3535 total_missed_rx = 0;
3540 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3541 &total_missed_rx, &total_qbrc, &total_qprc,
3544 /* If this is a reset xstats is NULL, and we have cleared the
3545 * registers by reading them.
3547 if (!ids && !values)
3550 /* Extended stats from ixgbe_hw_stats */
3552 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3553 values[count] = *(uint64_t *)(((char *)hw_stats) +
3554 rte_ixgbe_stats_strings[i].offset);
3559 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3560 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3561 rte_ixgbe_macsec_strings[i].offset);
3565 /* RX Priority Stats */
3566 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3567 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3569 *(uint64_t *)(((char *)hw_stats) +
3570 rte_ixgbe_rxq_strings[stat].offset +
3571 (sizeof(uint64_t) * i));
3576 /* TX Priority Stats */
3577 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3578 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3580 *(uint64_t *)(((char *)hw_stats) +
3581 rte_ixgbe_txq_strings[stat].offset +
3582 (sizeof(uint64_t) * i));
3590 uint16_t size = ixgbe_xstats_calc_num();
3591 uint64_t values_copy[size];
3593 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3595 for (i = 0; i < n; i++) {
3596 if (ids[i] >= size) {
3597 PMD_INIT_LOG(ERR, "id value isn't valid");
3600 values[i] = values_copy[ids[i]];
3606 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3608 struct ixgbe_hw_stats *stats =
3609 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3610 struct ixgbe_macsec_stats *macsec_stats =
3611 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3612 dev->data->dev_private);
3614 unsigned count = ixgbe_xstats_calc_num();
3616 /* HW registers are cleared on read */
3617 ixgbe_dev_xstats_get(dev, NULL, count);
3619 /* Reset software totals */
3620 memset(stats, 0, sizeof(*stats));
3621 memset(macsec_stats, 0, sizeof(*macsec_stats));
3625 ixgbevf_update_stats(struct rte_eth_dev *dev)
3627 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3629 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3631 /* Good Rx packet, include VF loopback */
3632 UPDATE_VF_STAT(IXGBE_VFGPRC,
3633 hw_stats->last_vfgprc, hw_stats->vfgprc);
3635 /* Good Rx octets, include VF loopback */
3636 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3637 hw_stats->last_vfgorc, hw_stats->vfgorc);
3639 /* Good Tx packet, include VF loopback */
3640 UPDATE_VF_STAT(IXGBE_VFGPTC,
3641 hw_stats->last_vfgptc, hw_stats->vfgptc);
3643 /* Good Tx octets, include VF loopback */
3644 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3645 hw_stats->last_vfgotc, hw_stats->vfgotc);
3647 /* Rx Multicst Packet */
3648 UPDATE_VF_STAT(IXGBE_VFMPRC,
3649 hw_stats->last_vfmprc, hw_stats->vfmprc);
3653 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3656 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3657 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3660 if (n < IXGBEVF_NB_XSTATS)
3661 return IXGBEVF_NB_XSTATS;
3663 ixgbevf_update_stats(dev);
3668 /* Extended stats */
3669 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3671 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3672 rte_ixgbevf_stats_strings[i].offset);
3675 return IXGBEVF_NB_XSTATS;
3679 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3681 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3682 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3684 ixgbevf_update_stats(dev);
3689 stats->ipackets = hw_stats->vfgprc;
3690 stats->ibytes = hw_stats->vfgorc;
3691 stats->opackets = hw_stats->vfgptc;
3692 stats->obytes = hw_stats->vfgotc;
3697 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3699 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3700 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3702 /* Sync HW register to the last stats */
3703 ixgbevf_dev_stats_get(dev, NULL);
3705 /* reset HW current stats*/
3706 hw_stats->vfgprc = 0;
3707 hw_stats->vfgorc = 0;
3708 hw_stats->vfgptc = 0;
3709 hw_stats->vfgotc = 0;
3713 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3715 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716 u16 eeprom_verh, eeprom_verl;
3720 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3721 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3723 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3724 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3726 ret += 1; /* add the size of '\0' */
3727 if (fw_size < (u32)ret)
3734 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3736 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3737 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3738 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3740 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3741 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3742 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3744 * When DCB/VT is off, maximum number of queues changes,
3745 * except for 82598EB, which remains constant.
3747 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3748 hw->mac.type != ixgbe_mac_82598EB)
3749 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3751 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3752 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3753 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3754 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3755 dev_info->max_vfs = pci_dev->max_vfs;
3756 if (hw->mac.type == ixgbe_mac_82598EB)
3757 dev_info->max_vmdq_pools = ETH_16_POOLS;
3759 dev_info->max_vmdq_pools = ETH_64_POOLS;
3760 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3761 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3762 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3763 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3764 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3765 dev_info->rx_queue_offload_capa);
3766 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3767 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3769 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3771 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3772 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3773 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3775 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3780 dev_info->default_txconf = (struct rte_eth_txconf) {
3782 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3783 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3784 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3786 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3787 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3791 dev_info->rx_desc_lim = rx_desc_lim;
3792 dev_info->tx_desc_lim = tx_desc_lim;
3794 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3795 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3796 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3798 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3799 if (hw->mac.type == ixgbe_mac_X540 ||
3800 hw->mac.type == ixgbe_mac_X540_vf ||
3801 hw->mac.type == ixgbe_mac_X550 ||
3802 hw->mac.type == ixgbe_mac_X550_vf) {
3803 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3805 if (hw->mac.type == ixgbe_mac_X550) {
3806 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3807 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3810 /* Driver-preferred Rx/Tx parameters */
3811 dev_info->default_rxportconf.burst_size = 32;
3812 dev_info->default_txportconf.burst_size = 32;
3813 dev_info->default_rxportconf.nb_queues = 1;
3814 dev_info->default_txportconf.nb_queues = 1;
3815 dev_info->default_rxportconf.ring_size = 256;
3816 dev_info->default_txportconf.ring_size = 256;
3819 static const uint32_t *
3820 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3822 static const uint32_t ptypes[] = {
3823 /* For non-vec functions,
3824 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3825 * for vec functions,
3826 * refers to _recv_raw_pkts_vec().
3830 RTE_PTYPE_L3_IPV4_EXT,
3832 RTE_PTYPE_L3_IPV6_EXT,
3836 RTE_PTYPE_TUNNEL_IP,
3837 RTE_PTYPE_INNER_L3_IPV6,
3838 RTE_PTYPE_INNER_L3_IPV6_EXT,
3839 RTE_PTYPE_INNER_L4_TCP,
3840 RTE_PTYPE_INNER_L4_UDP,
3844 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3845 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3846 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3847 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3850 #if defined(RTE_ARCH_X86)
3851 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3852 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3859 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3860 struct rte_eth_dev_info *dev_info)
3862 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3863 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3865 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3866 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3867 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3868 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3869 dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3870 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3871 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3872 dev_info->max_vfs = pci_dev->max_vfs;
3873 if (hw->mac.type == ixgbe_mac_82598EB)
3874 dev_info->max_vmdq_pools = ETH_16_POOLS;
3876 dev_info->max_vmdq_pools = ETH_64_POOLS;
3877 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3878 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3879 dev_info->rx_queue_offload_capa);
3880 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3881 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3883 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3885 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3886 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3887 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3889 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3894 dev_info->default_txconf = (struct rte_eth_txconf) {
3896 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3897 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3898 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3900 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3901 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3905 dev_info->rx_desc_lim = rx_desc_lim;
3906 dev_info->tx_desc_lim = tx_desc_lim;
3910 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3911 int *link_up, int wait_to_complete)
3913 struct ixgbe_mbx_info *mbx = &hw->mbx;
3914 struct ixgbe_mac_info *mac = &hw->mac;
3915 uint32_t links_reg, in_msg;
3918 /* If we were hit with a reset drop the link */
3919 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3920 mac->get_link_status = true;
3922 if (!mac->get_link_status)
3925 /* if link status is down no point in checking to see if pf is up */
3926 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3927 if (!(links_reg & IXGBE_LINKS_UP))
3930 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3931 * before the link status is correct
3933 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3936 for (i = 0; i < 5; i++) {
3938 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3940 if (!(links_reg & IXGBE_LINKS_UP))
3945 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3946 case IXGBE_LINKS_SPEED_10G_82599:
3947 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3948 if (hw->mac.type >= ixgbe_mac_X550) {
3949 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3950 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3953 case IXGBE_LINKS_SPEED_1G_82599:
3954 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3956 case IXGBE_LINKS_SPEED_100_82599:
3957 *speed = IXGBE_LINK_SPEED_100_FULL;
3958 if (hw->mac.type == ixgbe_mac_X550) {
3959 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3960 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3963 case IXGBE_LINKS_SPEED_10_X550EM_A:
3964 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3965 /* Since Reserved in older MAC's */
3966 if (hw->mac.type >= ixgbe_mac_X550)
3967 *speed = IXGBE_LINK_SPEED_10_FULL;
3970 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3973 /* if the read failed it could just be a mailbox collision, best wait
3974 * until we are called again and don't report an error
3976 if (mbx->ops.read(hw, &in_msg, 1, 0))
3979 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3980 /* msg is not CTS and is NACK we must have lost CTS status */
3981 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3982 mac->get_link_status = false;
3986 /* the pf is talking, if we timed out in the past we reinit */
3987 if (!mbx->timeout) {
3992 /* if we passed all the tests above then the link is up and we no
3993 * longer need to check for link
3995 mac->get_link_status = false;
3998 *link_up = !mac->get_link_status;
4003 ixgbe_dev_setup_link_alarm_handler(void *param)
4005 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4007 struct ixgbe_interrupt *intr =
4008 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4010 bool autoneg = false;
4012 speed = hw->phy.autoneg_advertised;
4014 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4016 ixgbe_setup_link(hw, speed, true);
4018 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4021 /* return 0 means link status changed, -1 means not changed */
4023 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4024 int wait_to_complete, int vf)
4026 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4027 struct rte_eth_link link;
4028 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4029 struct ixgbe_interrupt *intr =
4030 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4035 memset(&link, 0, sizeof(link));
4036 link.link_status = ETH_LINK_DOWN;
4037 link.link_speed = ETH_SPEED_NUM_NONE;
4038 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4039 link.link_autoneg = ETH_LINK_AUTONEG;
4041 hw->mac.get_link_status = true;
4043 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4044 return rte_eth_linkstatus_set(dev, &link);
4046 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4047 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4051 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4053 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4056 link.link_speed = ETH_SPEED_NUM_100M;
4057 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4058 return rte_eth_linkstatus_set(dev, &link);
4062 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4063 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4064 rte_eal_alarm_set(10,
4065 ixgbe_dev_setup_link_alarm_handler, dev);
4067 return rte_eth_linkstatus_set(dev, &link);
4070 link.link_status = ETH_LINK_UP;
4071 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4073 switch (link_speed) {
4075 case IXGBE_LINK_SPEED_UNKNOWN:
4076 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4077 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4078 link.link_speed = ETH_SPEED_NUM_10M;
4080 link.link_speed = ETH_SPEED_NUM_100M;
4081 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4084 case IXGBE_LINK_SPEED_100_FULL:
4085 link.link_speed = ETH_SPEED_NUM_100M;
4088 case IXGBE_LINK_SPEED_1GB_FULL:
4089 link.link_speed = ETH_SPEED_NUM_1G;
4092 case IXGBE_LINK_SPEED_2_5GB_FULL:
4093 link.link_speed = ETH_SPEED_NUM_2_5G;
4096 case IXGBE_LINK_SPEED_5GB_FULL:
4097 link.link_speed = ETH_SPEED_NUM_5G;
4100 case IXGBE_LINK_SPEED_10GB_FULL:
4101 link.link_speed = ETH_SPEED_NUM_10G;
4105 return rte_eth_linkstatus_set(dev, &link);
4109 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4111 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4115 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4117 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4121 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4123 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4127 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4128 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4132 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4134 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4137 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4138 fctrl &= (~IXGBE_FCTRL_UPE);
4139 if (dev->data->all_multicast == 1)
4140 fctrl |= IXGBE_FCTRL_MPE;
4142 fctrl &= (~IXGBE_FCTRL_MPE);
4143 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4147 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4149 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4152 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4153 fctrl |= IXGBE_FCTRL_MPE;
4154 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4158 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4163 if (dev->data->promiscuous == 1)
4164 return; /* must remain in all_multicast mode */
4166 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4167 fctrl &= (~IXGBE_FCTRL_MPE);
4168 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4172 * It clears the interrupt causes and enables the interrupt.
4173 * It will be called once only during nic initialized.
4176 * Pointer to struct rte_eth_dev.
4178 * Enable or Disable.
4181 * - On success, zero.
4182 * - On failure, a negative value.
4185 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4187 struct ixgbe_interrupt *intr =
4188 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4190 ixgbe_dev_link_status_print(dev);
4192 intr->mask |= IXGBE_EICR_LSC;
4194 intr->mask &= ~IXGBE_EICR_LSC;
4200 * It clears the interrupt causes and enables the interrupt.
4201 * It will be called once only during nic initialized.
4204 * Pointer to struct rte_eth_dev.
4207 * - On success, zero.
4208 * - On failure, a negative value.
4211 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4213 struct ixgbe_interrupt *intr =
4214 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4216 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4222 * It clears the interrupt causes and enables the interrupt.
4223 * It will be called once only during nic initialized.
4226 * Pointer to struct rte_eth_dev.
4229 * - On success, zero.
4230 * - On failure, a negative value.
4233 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4235 struct ixgbe_interrupt *intr =
4236 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4238 intr->mask |= IXGBE_EICR_LINKSEC;
4244 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4247 * Pointer to struct rte_eth_dev.
4250 * - On success, zero.
4251 * - On failure, a negative value.
4254 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4257 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4258 struct ixgbe_interrupt *intr =
4259 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4261 /* clear all cause mask */
4262 ixgbe_disable_intr(hw);
4264 /* read-on-clear nic registers here */
4265 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4266 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4270 /* set flag for async link update */
4271 if (eicr & IXGBE_EICR_LSC)
4272 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4274 if (eicr & IXGBE_EICR_MAILBOX)
4275 intr->flags |= IXGBE_FLAG_MAILBOX;
4277 if (eicr & IXGBE_EICR_LINKSEC)
4278 intr->flags |= IXGBE_FLAG_MACSEC;
4280 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4281 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4282 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4283 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4289 * It gets and then prints the link status.
4292 * Pointer to struct rte_eth_dev.
4295 * - On success, zero.
4296 * - On failure, a negative value.
4299 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4301 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4302 struct rte_eth_link link;
4304 rte_eth_linkstatus_get(dev, &link);
4306 if (link.link_status) {
4307 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4308 (int)(dev->data->port_id),
4309 (unsigned)link.link_speed,
4310 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4311 "full-duplex" : "half-duplex");
4313 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4314 (int)(dev->data->port_id));
4316 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4317 pci_dev->addr.domain,
4319 pci_dev->addr.devid,
4320 pci_dev->addr.function);
4324 * It executes link_update after knowing an interrupt occurred.
4327 * Pointer to struct rte_eth_dev.
4330 * - On success, zero.
4331 * - On failure, a negative value.
4334 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4336 struct ixgbe_interrupt *intr =
4337 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4339 struct ixgbe_hw *hw =
4340 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4342 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4344 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4345 ixgbe_pf_mbx_process(dev);
4346 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4349 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4350 ixgbe_handle_lasi(hw);
4351 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4354 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4355 struct rte_eth_link link;
4357 /* get the link status before link update, for predicting later */
4358 rte_eth_linkstatus_get(dev, &link);
4360 ixgbe_dev_link_update(dev, 0);
4363 if (!link.link_status)
4364 /* handle it 1 sec later, wait it being stable */
4365 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4366 /* likely to down */
4368 /* handle it 4 sec later, wait it being stable */
4369 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4371 ixgbe_dev_link_status_print(dev);
4372 if (rte_eal_alarm_set(timeout * 1000,
4373 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4374 PMD_DRV_LOG(ERR, "Error setting alarm");
4376 /* remember original mask */
4377 intr->mask_original = intr->mask;
4378 /* only disable lsc interrupt */
4379 intr->mask &= ~IXGBE_EIMS_LSC;
4383 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4384 ixgbe_enable_intr(dev);
4390 * Interrupt handler which shall be registered for alarm callback for delayed
4391 * handling specific interrupt to wait for the stable nic state. As the
4392 * NIC interrupt state is not stable for ixgbe after link is just down,
4393 * it needs to wait 4 seconds to get the stable status.
4396 * Pointer to interrupt handle.
4398 * The address of parameter (struct rte_eth_dev *) regsitered before.
4404 ixgbe_dev_interrupt_delayed_handler(void *param)
4406 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4407 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4408 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4409 struct ixgbe_interrupt *intr =
4410 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4411 struct ixgbe_hw *hw =
4412 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415 ixgbe_disable_intr(hw);
4417 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4418 if (eicr & IXGBE_EICR_MAILBOX)
4419 ixgbe_pf_mbx_process(dev);
4421 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4422 ixgbe_handle_lasi(hw);
4423 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4426 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4427 ixgbe_dev_link_update(dev, 0);
4428 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4429 ixgbe_dev_link_status_print(dev);
4430 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4434 if (intr->flags & IXGBE_FLAG_MACSEC) {
4435 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4437 intr->flags &= ~IXGBE_FLAG_MACSEC;
4440 /* restore original mask */
4441 intr->mask = intr->mask_original;
4442 intr->mask_original = 0;
4444 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4445 ixgbe_enable_intr(dev);
4446 rte_intr_enable(intr_handle);
4450 * Interrupt handler triggered by NIC for handling
4451 * specific interrupt.
4454 * Pointer to interrupt handle.
4456 * The address of parameter (struct rte_eth_dev *) regsitered before.
4462 ixgbe_dev_interrupt_handler(void *param)
4464 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4466 ixgbe_dev_interrupt_get_status(dev);
4467 ixgbe_dev_interrupt_action(dev);
4471 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4473 struct ixgbe_hw *hw;
4475 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4476 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4480 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4482 struct ixgbe_hw *hw;
4484 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4485 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4489 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4491 struct ixgbe_hw *hw;
4497 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4499 fc_conf->pause_time = hw->fc.pause_time;
4500 fc_conf->high_water = hw->fc.high_water[0];
4501 fc_conf->low_water = hw->fc.low_water[0];
4502 fc_conf->send_xon = hw->fc.send_xon;
4503 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4506 * Return rx_pause status according to actual setting of
4509 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4510 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4516 * Return tx_pause status according to actual setting of
4519 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4520 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4525 if (rx_pause && tx_pause)
4526 fc_conf->mode = RTE_FC_FULL;
4528 fc_conf->mode = RTE_FC_RX_PAUSE;
4530 fc_conf->mode = RTE_FC_TX_PAUSE;
4532 fc_conf->mode = RTE_FC_NONE;
4538 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4540 struct ixgbe_hw *hw;
4542 uint32_t rx_buf_size;
4543 uint32_t max_high_water;
4545 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4552 PMD_INIT_FUNC_TRACE();
4554 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4555 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4556 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4559 * At least reserve one Ethernet frame for watermark
4560 * high_water/low_water in kilo bytes for ixgbe
4562 max_high_water = (rx_buf_size -
4563 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4564 if ((fc_conf->high_water > max_high_water) ||
4565 (fc_conf->high_water < fc_conf->low_water)) {
4566 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4567 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4571 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4572 hw->fc.pause_time = fc_conf->pause_time;
4573 hw->fc.high_water[0] = fc_conf->high_water;
4574 hw->fc.low_water[0] = fc_conf->low_water;
4575 hw->fc.send_xon = fc_conf->send_xon;
4576 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4578 err = ixgbe_fc_enable(hw);
4580 /* Not negotiated is not an error case */
4581 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4583 /* check if we want to forward MAC frames - driver doesn't have native
4584 * capability to do that, so we'll write the registers ourselves */
4586 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4588 /* set or clear MFLCN.PMCF bit depending on configuration */
4589 if (fc_conf->mac_ctrl_frame_fwd != 0)
4590 mflcn |= IXGBE_MFLCN_PMCF;
4592 mflcn &= ~IXGBE_MFLCN_PMCF;
4594 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4595 IXGBE_WRITE_FLUSH(hw);
4600 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4605 * ixgbe_pfc_enable_generic - Enable flow control
4606 * @hw: pointer to hardware structure
4607 * @tc_num: traffic class number
4608 * Enable flow control according to the current settings.
4611 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4614 uint32_t mflcn_reg, fccfg_reg;
4616 uint32_t fcrtl, fcrth;
4620 /* Validate the water mark configuration */
4621 if (!hw->fc.pause_time) {
4622 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4626 /* Low water mark of zero causes XOFF floods */
4627 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4628 /* High/Low water can not be 0 */
4629 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4630 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4631 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4635 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4636 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4637 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4641 /* Negotiate the fc mode to use */
4642 ixgbe_fc_autoneg(hw);
4644 /* Disable any previous flow control settings */
4645 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4646 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4648 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4649 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4651 switch (hw->fc.current_mode) {
4654 * If the count of enabled RX Priority Flow control >1,
4655 * and the TX pause can not be disabled
4658 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4659 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4660 if (reg & IXGBE_FCRTH_FCEN)
4664 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4666 case ixgbe_fc_rx_pause:
4668 * Rx Flow control is enabled and Tx Flow control is
4669 * disabled by software override. Since there really
4670 * isn't a way to advertise that we are capable of RX
4671 * Pause ONLY, we will advertise that we support both
4672 * symmetric and asymmetric Rx PAUSE. Later, we will
4673 * disable the adapter's ability to send PAUSE frames.
4675 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4677 * If the count of enabled RX Priority Flow control >1,
4678 * and the TX pause can not be disabled
4681 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4682 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4683 if (reg & IXGBE_FCRTH_FCEN)
4687 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4689 case ixgbe_fc_tx_pause:
4691 * Tx Flow control is enabled, and Rx Flow control is
4692 * disabled by software override.
4694 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4697 /* Flow control (both Rx and Tx) is enabled by SW override. */
4698 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4699 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4702 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4703 ret_val = IXGBE_ERR_CONFIG;
4707 /* Set 802.3x based flow control settings. */
4708 mflcn_reg |= IXGBE_MFLCN_DPF;
4709 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4710 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4712 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4713 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4714 hw->fc.high_water[tc_num]) {
4715 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4716 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4717 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4719 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4721 * In order to prevent Tx hangs when the internal Tx
4722 * switch is enabled we must set the high water mark
4723 * to the maximum FCRTH value. This allows the Tx
4724 * switch to function even under heavy Rx workloads.
4726 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4728 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4730 /* Configure pause time (2 TCs per register) */
4731 reg = hw->fc.pause_time * 0x00010001;
4732 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4733 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4735 /* Configure flow control refresh threshold value */
4736 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4743 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4745 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4746 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4748 if (hw->mac.type != ixgbe_mac_82598EB) {
4749 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4755 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4758 uint32_t rx_buf_size;
4759 uint32_t max_high_water;
4761 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4762 struct ixgbe_hw *hw =
4763 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4764 struct ixgbe_dcb_config *dcb_config =
4765 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4767 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4774 PMD_INIT_FUNC_TRACE();
4776 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4777 tc_num = map[pfc_conf->priority];
4778 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4779 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4781 * At least reserve one Ethernet frame for watermark
4782 * high_water/low_water in kilo bytes for ixgbe
4784 max_high_water = (rx_buf_size -
4785 RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4786 if ((pfc_conf->fc.high_water > max_high_water) ||
4787 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4788 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4789 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4793 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4794 hw->fc.pause_time = pfc_conf->fc.pause_time;
4795 hw->fc.send_xon = pfc_conf->fc.send_xon;
4796 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4797 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4799 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4801 /* Not negotiated is not an error case */
4802 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4805 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4810 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4811 struct rte_eth_rss_reta_entry64 *reta_conf,
4814 uint16_t i, sp_reta_size;
4817 uint16_t idx, shift;
4818 struct ixgbe_adapter *adapter =
4819 (struct ixgbe_adapter *)dev->data->dev_private;
4820 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4823 PMD_INIT_FUNC_TRACE();
4825 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4826 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4831 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4832 if (reta_size != sp_reta_size) {
4833 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4834 "(%d) doesn't match the number hardware can supported "
4835 "(%d)", reta_size, sp_reta_size);
4839 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4840 idx = i / RTE_RETA_GROUP_SIZE;
4841 shift = i % RTE_RETA_GROUP_SIZE;
4842 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4846 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4847 if (mask == IXGBE_4_BIT_MASK)
4850 r = IXGBE_READ_REG(hw, reta_reg);
4851 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4852 if (mask & (0x1 << j))
4853 reta |= reta_conf[idx].reta[shift + j] <<
4856 reta |= r & (IXGBE_8_BIT_MASK <<
4859 IXGBE_WRITE_REG(hw, reta_reg, reta);
4861 adapter->rss_reta_updated = 1;
4867 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4868 struct rte_eth_rss_reta_entry64 *reta_conf,
4871 uint16_t i, sp_reta_size;
4874 uint16_t idx, shift;
4875 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4878 PMD_INIT_FUNC_TRACE();
4879 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4880 if (reta_size != sp_reta_size) {
4881 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4882 "(%d) doesn't match the number hardware can supported "
4883 "(%d)", reta_size, sp_reta_size);
4887 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4888 idx = i / RTE_RETA_GROUP_SIZE;
4889 shift = i % RTE_RETA_GROUP_SIZE;
4890 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4895 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4896 reta = IXGBE_READ_REG(hw, reta_reg);
4897 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4898 if (mask & (0x1 << j))
4899 reta_conf[idx].reta[shift + j] =
4900 ((reta >> (CHAR_BIT * j)) &
4909 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
4910 uint32_t index, uint32_t pool)
4912 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913 uint32_t enable_addr = 1;
4915 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4920 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4924 ixgbe_clear_rar(hw, index);
4928 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
4930 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4932 ixgbe_remove_rar(dev, 0);
4933 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4939 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4941 if (strcmp(dev->device->driver->name, drv->driver.name))
4948 is_ixgbe_supported(struct rte_eth_dev *dev)
4950 return is_device_supported(dev, &rte_ixgbe_pmd);
4954 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4958 struct ixgbe_hw *hw;
4959 struct rte_eth_dev_info dev_info;
4960 uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
4961 struct rte_eth_dev_data *dev_data = dev->data;
4963 ixgbe_dev_info_get(dev, &dev_info);
4965 /* check that mtu is within the allowed range */
4966 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
4969 /* If device is started, refuse mtu that requires the support of
4970 * scattered packets when this feature has not been enabled before.
4972 if (dev_data->dev_started && !dev_data->scattered_rx &&
4973 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4974 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4975 PMD_INIT_LOG(ERR, "Stop port first.");
4979 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4980 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4982 /* switch to jumbo mode if needed */
4983 if (frame_size > RTE_ETHER_MAX_LEN) {
4984 dev->data->dev_conf.rxmode.offloads |=
4985 DEV_RX_OFFLOAD_JUMBO_FRAME;
4986 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4988 dev->data->dev_conf.rxmode.offloads &=
4989 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4990 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4992 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4994 /* update max frame size */
4995 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4997 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4998 maxfrs &= 0x0000FFFF;
4999 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5000 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5006 * Virtual Function operations
5009 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5011 struct ixgbe_interrupt *intr =
5012 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5013 struct ixgbe_hw *hw =
5014 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5016 PMD_INIT_FUNC_TRACE();
5018 /* Clear interrupt mask to stop from interrupts being generated */
5019 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5021 IXGBE_WRITE_FLUSH(hw);
5023 /* Clear mask value. */
5028 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5030 struct ixgbe_interrupt *intr =
5031 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5032 struct ixgbe_hw *hw =
5033 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035 PMD_INIT_FUNC_TRACE();
5037 /* VF enable interrupt autoclean */
5038 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5039 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5040 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5042 IXGBE_WRITE_FLUSH(hw);
5044 /* Save IXGBE_VTEIMS value to mask. */
5045 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5049 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5051 struct rte_eth_conf *conf = &dev->data->dev_conf;
5052 struct ixgbe_adapter *adapter =
5053 (struct ixgbe_adapter *)dev->data->dev_private;
5055 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5056 dev->data->port_id);
5059 * VF has no ability to enable/disable HW CRC
5060 * Keep the persistent behavior the same as Host PF
5062 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5063 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5064 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5065 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5068 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5069 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5070 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5075 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5076 * allocation or vector Rx preconditions we will reset it.
5078 adapter->rx_bulk_alloc_allowed = true;
5079 adapter->rx_vec_allowed = true;
5085 ixgbevf_dev_start(struct rte_eth_dev *dev)
5087 struct ixgbe_hw *hw =
5088 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5089 uint32_t intr_vector = 0;
5090 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5091 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5095 PMD_INIT_FUNC_TRACE();
5097 /* Stop the link setup handler before resetting the HW. */
5098 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5100 err = hw->mac.ops.reset_hw(hw);
5102 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5105 hw->mac.get_link_status = true;
5107 /* negotiate mailbox API version to use with the PF. */
5108 ixgbevf_negotiate_api(hw);
5110 ixgbevf_dev_tx_init(dev);
5112 /* This can fail when allocating mbufs for descriptor rings */
5113 err = ixgbevf_dev_rx_init(dev);
5115 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5116 ixgbe_dev_clear_queues(dev);
5121 ixgbevf_set_vfta_all(dev, 1);
5124 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5125 ETH_VLAN_EXTEND_MASK;
5126 err = ixgbevf_vlan_offload_config(dev, mask);
5128 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5129 ixgbe_dev_clear_queues(dev);
5133 ixgbevf_dev_rxtx_start(dev);
5135 /* check and configure queue intr-vector mapping */
5136 if (rte_intr_cap_multiple(intr_handle) &&
5137 dev->data->dev_conf.intr_conf.rxq) {
5138 /* According to datasheet, only vector 0/1/2 can be used,
5139 * now only one vector is used for Rx queue
5142 if (rte_intr_efd_enable(intr_handle, intr_vector))
5146 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5147 intr_handle->intr_vec =
5148 rte_zmalloc("intr_vec",
5149 dev->data->nb_rx_queues * sizeof(int), 0);
5150 if (intr_handle->intr_vec == NULL) {
5151 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5152 " intr_vec", dev->data->nb_rx_queues);
5156 ixgbevf_configure_msix(dev);
5158 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5159 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5160 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5161 * is not cleared, it will fail when following rte_intr_enable( ) tries
5162 * to map Rx queue interrupt to other VFIO vectors.
5163 * So clear uio/vfio intr/evevnfd first to avoid failure.
5165 rte_intr_disable(intr_handle);
5167 rte_intr_enable(intr_handle);
5169 /* Re-enable interrupt for VF */
5170 ixgbevf_intr_enable(dev);
5173 * Update link status right before return, because it may
5174 * start link configuration process in a separate thread.
5176 ixgbevf_dev_link_update(dev, 0);
5182 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5184 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5185 struct ixgbe_adapter *adapter =
5186 (struct ixgbe_adapter *)dev->data->dev_private;
5187 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5188 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5190 PMD_INIT_FUNC_TRACE();
5192 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5194 ixgbevf_intr_disable(dev);
5196 hw->adapter_stopped = 1;
5197 ixgbe_stop_adapter(hw);
5200 * Clear what we set, but we still keep shadow_vfta to
5201 * restore after device starts
5203 ixgbevf_set_vfta_all(dev, 0);
5205 /* Clear stored conf */
5206 dev->data->scattered_rx = 0;
5208 ixgbe_dev_clear_queues(dev);
5210 /* Clean datapath event and queue/vec mapping */
5211 rte_intr_efd_disable(intr_handle);
5212 if (intr_handle->intr_vec != NULL) {
5213 rte_free(intr_handle->intr_vec);
5214 intr_handle->intr_vec = NULL;
5217 adapter->rss_reta_updated = 0;
5221 ixgbevf_dev_close(struct rte_eth_dev *dev)
5223 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225 PMD_INIT_FUNC_TRACE();
5229 ixgbevf_dev_stop(dev);
5231 ixgbe_dev_free_queues(dev);
5234 * Remove the VF MAC address ro ensure
5235 * that the VF traffic goes to the PF
5236 * after stop, close and detach of the VF
5238 ixgbevf_remove_mac_addr(dev, 0);
5245 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5249 ret = eth_ixgbevf_dev_uninit(dev);
5253 ret = eth_ixgbevf_dev_init(dev);
5258 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5260 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5261 struct ixgbe_vfta *shadow_vfta =
5262 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5263 int i = 0, j = 0, vfta = 0, mask = 1;
5265 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5266 vfta = shadow_vfta->vfta[i];
5269 for (j = 0; j < 32; j++) {
5271 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5281 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5283 struct ixgbe_hw *hw =
5284 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5285 struct ixgbe_vfta *shadow_vfta =
5286 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5287 uint32_t vid_idx = 0;
5288 uint32_t vid_bit = 0;
5291 PMD_INIT_FUNC_TRACE();
5293 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5294 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5296 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5299 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5300 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5302 /* Save what we set and retore it after device reset */
5304 shadow_vfta->vfta[vid_idx] |= vid_bit;
5306 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5312 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5314 struct ixgbe_hw *hw =
5315 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5318 PMD_INIT_FUNC_TRACE();
5320 if (queue >= hw->mac.max_rx_queues)
5323 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5325 ctrl |= IXGBE_RXDCTL_VME;
5327 ctrl &= ~IXGBE_RXDCTL_VME;
5328 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5330 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5334 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5336 struct ixgbe_rx_queue *rxq;
5340 /* VF function only support hw strip feature, others are not support */
5341 if (mask & ETH_VLAN_STRIP_MASK) {
5342 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5343 rxq = dev->data->rx_queues[i];
5344 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5345 ixgbevf_vlan_strip_queue_set(dev, i, on);
5353 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5355 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5357 ixgbevf_vlan_offload_config(dev, mask);
5363 ixgbe_vt_check(struct ixgbe_hw *hw)
5367 /* if Virtualization Technology is enabled */
5368 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5369 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5370 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5378 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5380 uint32_t vector = 0;
5382 switch (hw->mac.mc_filter_type) {
5383 case 0: /* use bits [47:36] of the address */
5384 vector = ((uc_addr->addr_bytes[4] >> 4) |
5385 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5387 case 1: /* use bits [46:35] of the address */
5388 vector = ((uc_addr->addr_bytes[4] >> 3) |
5389 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5391 case 2: /* use bits [45:34] of the address */
5392 vector = ((uc_addr->addr_bytes[4] >> 2) |
5393 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5395 case 3: /* use bits [43:32] of the address */
5396 vector = ((uc_addr->addr_bytes[4]) |
5397 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5399 default: /* Invalid mc_filter_type */
5403 /* vector can only be 12-bits or boundary will be exceeded */
5409 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5410 struct rte_ether_addr *mac_addr, uint8_t on)
5417 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5418 const uint32_t ixgbe_uta_bit_shift = 5;
5419 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5420 const uint32_t bit1 = 0x1;
5422 struct ixgbe_hw *hw =
5423 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5424 struct ixgbe_uta_info *uta_info =
5425 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5427 /* The UTA table only exists on 82599 hardware and newer */
5428 if (hw->mac.type < ixgbe_mac_82599EB)
5431 vector = ixgbe_uta_vector(hw, mac_addr);
5432 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5433 uta_shift = vector & ixgbe_uta_bit_mask;
5435 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5439 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5441 uta_info->uta_in_use++;
5442 reg_val |= (bit1 << uta_shift);
5443 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5445 uta_info->uta_in_use--;
5446 reg_val &= ~(bit1 << uta_shift);
5447 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5450 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5452 if (uta_info->uta_in_use > 0)
5453 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5454 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5456 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5462 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5465 struct ixgbe_hw *hw =
5466 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5467 struct ixgbe_uta_info *uta_info =
5468 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5470 /* The UTA table only exists on 82599 hardware and newer */
5471 if (hw->mac.type < ixgbe_mac_82599EB)
5475 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5476 uta_info->uta_shadow[i] = ~0;
5477 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5480 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5481 uta_info->uta_shadow[i] = 0;
5482 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5490 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5492 uint32_t new_val = orig_val;
5494 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5495 new_val |= IXGBE_VMOLR_AUPE;
5496 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5497 new_val |= IXGBE_VMOLR_ROMPE;
5498 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5499 new_val |= IXGBE_VMOLR_ROPE;
5500 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5501 new_val |= IXGBE_VMOLR_BAM;
5502 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5503 new_val |= IXGBE_VMOLR_MPE;
5508 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5509 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5510 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5511 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5512 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5513 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5514 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5517 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5518 struct rte_eth_mirror_conf *mirror_conf,
5519 uint8_t rule_id, uint8_t on)
5521 uint32_t mr_ctl, vlvf;
5522 uint32_t mp_lsb = 0;
5523 uint32_t mv_msb = 0;
5524 uint32_t mv_lsb = 0;
5525 uint32_t mp_msb = 0;
5528 uint64_t vlan_mask = 0;
5530 const uint8_t pool_mask_offset = 32;
5531 const uint8_t vlan_mask_offset = 32;
5532 const uint8_t dst_pool_offset = 8;
5533 const uint8_t rule_mr_offset = 4;
5534 const uint8_t mirror_rule_mask = 0x0F;
5536 struct ixgbe_mirror_info *mr_info =
5537 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5538 struct ixgbe_hw *hw =
5539 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5540 uint8_t mirror_type = 0;
5542 if (ixgbe_vt_check(hw) < 0)
5545 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5548 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5549 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5550 mirror_conf->rule_type);
5554 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5555 mirror_type |= IXGBE_MRCTL_VLME;
5556 /* Check if vlan id is valid and find conresponding VLAN ID
5559 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5560 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5561 /* search vlan id related pool vlan filter
5564 reg_index = ixgbe_find_vlvf_slot(
5566 mirror_conf->vlan.vlan_id[i],
5570 vlvf = IXGBE_READ_REG(hw,
5571 IXGBE_VLVF(reg_index));
5572 if ((vlvf & IXGBE_VLVF_VIEN) &&
5573 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5574 mirror_conf->vlan.vlan_id[i]))
5575 vlan_mask |= (1ULL << reg_index);
5582 mv_lsb = vlan_mask & 0xFFFFFFFF;
5583 mv_msb = vlan_mask >> vlan_mask_offset;
5585 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5586 mirror_conf->vlan.vlan_mask;
5587 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5588 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5589 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5590 mirror_conf->vlan.vlan_id[i];
5595 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5596 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5597 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5602 * if enable pool mirror, write related pool mask register,if disable
5603 * pool mirror, clear PFMRVM register
5605 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5606 mirror_type |= IXGBE_MRCTL_VPME;
5608 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5609 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5610 mr_info->mr_conf[rule_id].pool_mask =
5611 mirror_conf->pool_mask;
5616 mr_info->mr_conf[rule_id].pool_mask = 0;
5619 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5620 mirror_type |= IXGBE_MRCTL_UPME;
5621 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5622 mirror_type |= IXGBE_MRCTL_DPME;
5624 /* read mirror control register and recalculate it */
5625 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5628 mr_ctl |= mirror_type;
5629 mr_ctl &= mirror_rule_mask;
5630 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5632 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5635 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5636 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5638 /* write mirrror control register */
5639 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5641 /* write pool mirrror control register */
5642 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5643 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5644 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5647 /* write VLAN mirrror control register */
5648 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5649 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5650 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5658 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5661 uint32_t lsb_val = 0;
5662 uint32_t msb_val = 0;
5663 const uint8_t rule_mr_offset = 4;
5665 struct ixgbe_hw *hw =
5666 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5667 struct ixgbe_mirror_info *mr_info =
5668 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5670 if (ixgbe_vt_check(hw) < 0)
5673 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5676 memset(&mr_info->mr_conf[rule_id], 0,
5677 sizeof(struct rte_eth_mirror_conf));
5679 /* clear PFVMCTL register */
5680 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5682 /* clear pool mask register */
5683 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5684 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5686 /* clear vlan mask register */
5687 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5688 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5694 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5696 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5697 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5698 struct ixgbe_interrupt *intr =
5699 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5700 struct ixgbe_hw *hw =
5701 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5702 uint32_t vec = IXGBE_MISC_VEC_ID;
5704 if (rte_intr_allow_others(intr_handle))
5705 vec = IXGBE_RX_VEC_START;
5706 intr->mask |= (1 << vec);
5707 RTE_SET_USED(queue_id);
5708 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5710 rte_intr_enable(intr_handle);
5716 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5718 struct ixgbe_interrupt *intr =
5719 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5720 struct ixgbe_hw *hw =
5721 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5722 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5723 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5724 uint32_t vec = IXGBE_MISC_VEC_ID;
5726 if (rte_intr_allow_others(intr_handle))
5727 vec = IXGBE_RX_VEC_START;
5728 intr->mask &= ~(1 << vec);
5729 RTE_SET_USED(queue_id);
5730 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5736 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5738 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5739 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5741 struct ixgbe_hw *hw =
5742 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5743 struct ixgbe_interrupt *intr =
5744 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5746 if (queue_id < 16) {
5747 ixgbe_disable_intr(hw);
5748 intr->mask |= (1 << queue_id);
5749 ixgbe_enable_intr(dev);
5750 } else if (queue_id < 32) {
5751 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5752 mask &= (1 << queue_id);
5753 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5754 } else if (queue_id < 64) {
5755 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5756 mask &= (1 << (queue_id - 32));
5757 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5759 rte_intr_enable(intr_handle);
5765 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5768 struct ixgbe_hw *hw =
5769 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5770 struct ixgbe_interrupt *intr =
5771 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5773 if (queue_id < 16) {
5774 ixgbe_disable_intr(hw);
5775 intr->mask &= ~(1 << queue_id);
5776 ixgbe_enable_intr(dev);
5777 } else if (queue_id < 32) {
5778 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5779 mask &= ~(1 << queue_id);
5780 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5781 } else if (queue_id < 64) {
5782 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5783 mask &= ~(1 << (queue_id - 32));
5784 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5791 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5792 uint8_t queue, uint8_t msix_vector)
5796 if (direction == -1) {
5798 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5799 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5802 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5804 /* rx or tx cause */
5805 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5806 idx = ((16 * (queue & 1)) + (8 * direction));
5807 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5808 tmp &= ~(0xFF << idx);
5809 tmp |= (msix_vector << idx);
5810 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5815 * set the IVAR registers, mapping interrupt causes to vectors
5817 * pointer to ixgbe_hw struct
5819 * 0 for Rx, 1 for Tx, -1 for other causes
5821 * queue to map the corresponding interrupt to
5823 * the vector to map to the corresponding queue
5826 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5827 uint8_t queue, uint8_t msix_vector)
5831 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5832 if (hw->mac.type == ixgbe_mac_82598EB) {
5833 if (direction == -1)
5835 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5836 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5837 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5838 tmp |= (msix_vector << (8 * (queue & 0x3)));
5839 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5840 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5841 (hw->mac.type == ixgbe_mac_X540) ||
5842 (hw->mac.type == ixgbe_mac_X550)) {
5843 if (direction == -1) {
5845 idx = ((queue & 1) * 8);
5846 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5847 tmp &= ~(0xFF << idx);
5848 tmp |= (msix_vector << idx);
5849 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5851 /* rx or tx causes */
5852 idx = ((16 * (queue & 1)) + (8 * direction));
5853 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5854 tmp &= ~(0xFF << idx);
5855 tmp |= (msix_vector << idx);
5856 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5862 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5864 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5865 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5866 struct ixgbe_hw *hw =
5867 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5869 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5870 uint32_t base = IXGBE_MISC_VEC_ID;
5872 /* Configure VF other cause ivar */
5873 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5875 /* won't configure msix register if no mapping is done
5876 * between intr vector and event fd.
5878 if (!rte_intr_dp_is_en(intr_handle))
5881 if (rte_intr_allow_others(intr_handle)) {
5882 base = IXGBE_RX_VEC_START;
5883 vector_idx = IXGBE_RX_VEC_START;
5886 /* Configure all RX queues of VF */
5887 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5888 /* Force all queue use vector 0,
5889 * as IXGBE_VF_MAXMSIVECOTR = 1
5891 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5892 intr_handle->intr_vec[q_idx] = vector_idx;
5893 if (vector_idx < base + intr_handle->nb_efd - 1)
5897 /* As RX queue setting above show, all queues use the vector 0.
5898 * Set only the ITR value of IXGBE_MISC_VEC_ID.
5900 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5901 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5902 | IXGBE_EITR_CNT_WDIS);
5906 * Sets up the hardware to properly generate MSI-X interrupts
5908 * board private structure
5911 ixgbe_configure_msix(struct rte_eth_dev *dev)
5913 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5914 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5915 struct ixgbe_hw *hw =
5916 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5917 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5918 uint32_t vec = IXGBE_MISC_VEC_ID;
5922 /* won't configure msix register if no mapping is done
5923 * between intr vector and event fd
5924 * but if misx has been enabled already, need to configure
5925 * auto clean, auto mask and throttling.
5927 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5928 if (!rte_intr_dp_is_en(intr_handle) &&
5929 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5932 if (rte_intr_allow_others(intr_handle))
5933 vec = base = IXGBE_RX_VEC_START;
5935 /* setup GPIE for MSI-x mode */
5936 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5937 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5938 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5939 /* auto clearing and auto setting corresponding bits in EIMS
5940 * when MSI-X interrupt is triggered
5942 if (hw->mac.type == ixgbe_mac_82598EB) {
5943 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5945 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5946 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5948 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5950 /* Populate the IVAR table and set the ITR values to the
5951 * corresponding register.
5953 if (rte_intr_dp_is_en(intr_handle)) {
5954 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5956 /* by default, 1:1 mapping */
5957 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5958 intr_handle->intr_vec[queue_id] = vec;
5959 if (vec < base + intr_handle->nb_efd - 1)
5963 switch (hw->mac.type) {
5964 case ixgbe_mac_82598EB:
5965 ixgbe_set_ivar_map(hw, -1,
5966 IXGBE_IVAR_OTHER_CAUSES_INDEX,
5969 case ixgbe_mac_82599EB:
5970 case ixgbe_mac_X540:
5971 case ixgbe_mac_X550:
5972 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5978 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5979 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5980 | IXGBE_EITR_CNT_WDIS);
5982 /* set up to autoclear timer, and the vectors */
5983 mask = IXGBE_EIMS_ENABLE_MASK;
5984 mask &= ~(IXGBE_EIMS_OTHER |
5985 IXGBE_EIMS_MAILBOX |
5988 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5992 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5993 uint16_t queue_idx, uint16_t tx_rate)
5995 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996 struct rte_eth_rxmode *rxmode;
5997 uint32_t rf_dec, rf_int;
5999 uint16_t link_speed = dev->data->dev_link.link_speed;
6001 if (queue_idx >= hw->mac.max_tx_queues)
6005 /* Calculate the rate factor values to set */
6006 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6007 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6008 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6010 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6011 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6012 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6013 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6018 rxmode = &dev->data->dev_conf.rxmode;
6020 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6021 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6024 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6025 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6026 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6027 IXGBE_MMW_SIZE_JUMBO_FRAME);
6029 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6030 IXGBE_MMW_SIZE_DEFAULT);
6032 /* Set RTTBCNRC of queue X */
6033 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6034 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6035 IXGBE_WRITE_FLUSH(hw);
6041 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6042 __attribute__((unused)) uint32_t index,
6043 __attribute__((unused)) uint32_t pool)
6045 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6049 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6050 * operation. Trap this case to avoid exhausting the [very limited]
6051 * set of PF resources used to store VF MAC addresses.
6053 if (memcmp(hw->mac.perm_addr, mac_addr,
6054 sizeof(struct rte_ether_addr)) == 0)
6056 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6058 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6059 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6060 mac_addr->addr_bytes[0],
6061 mac_addr->addr_bytes[1],
6062 mac_addr->addr_bytes[2],
6063 mac_addr->addr_bytes[3],
6064 mac_addr->addr_bytes[4],
6065 mac_addr->addr_bytes[5],
6071 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6074 struct rte_ether_addr *perm_addr =
6075 (struct rte_ether_addr *)hw->mac.perm_addr;
6076 struct rte_ether_addr *mac_addr;
6081 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6082 * not support the deletion of a given MAC address.
6083 * Instead, it imposes to delete all MAC addresses, then to add again
6084 * all MAC addresses with the exception of the one to be deleted.
6086 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6089 * Add again all MAC addresses, with the exception of the deleted one
6090 * and of the permanent MAC address.
6092 for (i = 0, mac_addr = dev->data->mac_addrs;
6093 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6094 /* Skip the deleted MAC address */
6097 /* Skip NULL MAC addresses */
6098 if (rte_is_zero_ether_addr(mac_addr))
6100 /* Skip the permanent MAC address */
6101 if (memcmp(perm_addr, mac_addr,
6102 sizeof(struct rte_ether_addr)) == 0)
6104 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6107 "Adding again MAC address "
6108 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6110 mac_addr->addr_bytes[0],
6111 mac_addr->addr_bytes[1],
6112 mac_addr->addr_bytes[2],
6113 mac_addr->addr_bytes[3],
6114 mac_addr->addr_bytes[4],
6115 mac_addr->addr_bytes[5],
6121 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6122 struct rte_ether_addr *addr)
6124 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6126 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6132 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6133 struct rte_eth_syn_filter *filter,
6136 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6137 struct ixgbe_filter_info *filter_info =
6138 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6142 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6145 syn_info = filter_info->syn_info;
6148 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6150 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6151 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6153 if (filter->hig_pri)
6154 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6156 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6158 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6159 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6161 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6164 filter_info->syn_info = synqf;
6165 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6166 IXGBE_WRITE_FLUSH(hw);
6171 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6172 struct rte_eth_syn_filter *filter)
6174 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6175 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6177 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6178 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6179 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6186 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6187 enum rte_filter_op filter_op,
6190 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6193 MAC_TYPE_FILTER_SUP(hw->mac.type);
6195 if (filter_op == RTE_ETH_FILTER_NOP)
6199 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6204 switch (filter_op) {
6205 case RTE_ETH_FILTER_ADD:
6206 ret = ixgbe_syn_filter_set(dev,
6207 (struct rte_eth_syn_filter *)arg,
6210 case RTE_ETH_FILTER_DELETE:
6211 ret = ixgbe_syn_filter_set(dev,
6212 (struct rte_eth_syn_filter *)arg,
6215 case RTE_ETH_FILTER_GET:
6216 ret = ixgbe_syn_filter_get(dev,
6217 (struct rte_eth_syn_filter *)arg);
6220 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6229 static inline enum ixgbe_5tuple_protocol
6230 convert_protocol_type(uint8_t protocol_value)
6232 if (protocol_value == IPPROTO_TCP)
6233 return IXGBE_FILTER_PROTOCOL_TCP;
6234 else if (protocol_value == IPPROTO_UDP)
6235 return IXGBE_FILTER_PROTOCOL_UDP;
6236 else if (protocol_value == IPPROTO_SCTP)
6237 return IXGBE_FILTER_PROTOCOL_SCTP;
6239 return IXGBE_FILTER_PROTOCOL_NONE;
6242 /* inject a 5-tuple filter to HW */
6244 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6245 struct ixgbe_5tuple_filter *filter)
6247 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6249 uint32_t ftqf, sdpqf;
6250 uint32_t l34timir = 0;
6251 uint8_t mask = 0xff;
6255 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6256 IXGBE_SDPQF_DSTPORT_SHIFT);
6257 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6259 ftqf = (uint32_t)(filter->filter_info.proto &
6260 IXGBE_FTQF_PROTOCOL_MASK);
6261 ftqf |= (uint32_t)((filter->filter_info.priority &
6262 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6263 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6264 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6265 if (filter->filter_info.dst_ip_mask == 0)
6266 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6267 if (filter->filter_info.src_port_mask == 0)
6268 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6269 if (filter->filter_info.dst_port_mask == 0)
6270 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6271 if (filter->filter_info.proto_mask == 0)
6272 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6273 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6274 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6275 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6277 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6278 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6279 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6280 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6282 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6283 l34timir |= (uint32_t)(filter->queue <<
6284 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6285 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6289 * add a 5tuple filter
6292 * dev: Pointer to struct rte_eth_dev.
6293 * index: the index the filter allocates.
6294 * filter: ponter to the filter that will be added.
6295 * rx_queue: the queue id the filter assigned to.
6298 * - On success, zero.
6299 * - On failure, a negative value.
6302 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6303 struct ixgbe_5tuple_filter *filter)
6305 struct ixgbe_filter_info *filter_info =
6306 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6310 * look for an unused 5tuple filter index,
6311 * and insert the filter to list.
6313 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6314 idx = i / (sizeof(uint32_t) * NBBY);
6315 shift = i % (sizeof(uint32_t) * NBBY);
6316 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6317 filter_info->fivetuple_mask[idx] |= 1 << shift;
6319 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6325 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6326 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6330 ixgbe_inject_5tuple_filter(dev, filter);
6336 * remove a 5tuple filter
6339 * dev: Pointer to struct rte_eth_dev.
6340 * filter: the pointer of the filter will be removed.
6343 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6344 struct ixgbe_5tuple_filter *filter)
6346 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6347 struct ixgbe_filter_info *filter_info =
6348 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6349 uint16_t index = filter->index;
6351 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6352 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6353 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6356 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6357 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6358 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6359 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6360 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6364 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6366 struct ixgbe_hw *hw;
6367 uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6368 struct rte_eth_dev_data *dev_data = dev->data;
6370 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6372 if (mtu < RTE_ETHER_MIN_MTU ||
6373 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6376 /* If device is started, refuse mtu that requires the support of
6377 * scattered packets when this feature has not been enabled before.
6379 if (dev_data->dev_started && !dev_data->scattered_rx &&
6380 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6381 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6382 PMD_INIT_LOG(ERR, "Stop port first.");
6387 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6388 * request of the version 2.0 of the mailbox API.
6389 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6390 * of the mailbox API.
6391 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6392 * prior to 3.11.33 which contains the following change:
6393 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6395 ixgbevf_rlpml_set_vf(hw, max_frame);
6397 /* update max frame size */
6398 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6402 static inline struct ixgbe_5tuple_filter *
6403 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6404 struct ixgbe_5tuple_filter_info *key)
6406 struct ixgbe_5tuple_filter *it;
6408 TAILQ_FOREACH(it, filter_list, entries) {
6409 if (memcmp(key, &it->filter_info,
6410 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6417 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6419 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6420 struct ixgbe_5tuple_filter_info *filter_info)
6422 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6423 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6424 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6427 switch (filter->dst_ip_mask) {
6429 filter_info->dst_ip_mask = 0;
6430 filter_info->dst_ip = filter->dst_ip;
6433 filter_info->dst_ip_mask = 1;
6436 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6440 switch (filter->src_ip_mask) {
6442 filter_info->src_ip_mask = 0;
6443 filter_info->src_ip = filter->src_ip;
6446 filter_info->src_ip_mask = 1;
6449 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6453 switch (filter->dst_port_mask) {
6455 filter_info->dst_port_mask = 0;
6456 filter_info->dst_port = filter->dst_port;
6459 filter_info->dst_port_mask = 1;
6462 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6466 switch (filter->src_port_mask) {
6468 filter_info->src_port_mask = 0;
6469 filter_info->src_port = filter->src_port;
6472 filter_info->src_port_mask = 1;
6475 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6479 switch (filter->proto_mask) {
6481 filter_info->proto_mask = 0;
6482 filter_info->proto =
6483 convert_protocol_type(filter->proto);
6486 filter_info->proto_mask = 1;
6489 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6493 filter_info->priority = (uint8_t)filter->priority;
6498 * add or delete a ntuple filter
6501 * dev: Pointer to struct rte_eth_dev.
6502 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6503 * add: if true, add filter, if false, remove filter
6506 * - On success, zero.
6507 * - On failure, a negative value.
6510 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6511 struct rte_eth_ntuple_filter *ntuple_filter,
6514 struct ixgbe_filter_info *filter_info =
6515 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6516 struct ixgbe_5tuple_filter_info filter_5tuple;
6517 struct ixgbe_5tuple_filter *filter;
6520 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6521 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6525 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6526 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6530 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6532 if (filter != NULL && add) {
6533 PMD_DRV_LOG(ERR, "filter exists.");
6536 if (filter == NULL && !add) {
6537 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6542 filter = rte_zmalloc("ixgbe_5tuple_filter",
6543 sizeof(struct ixgbe_5tuple_filter), 0);
6546 rte_memcpy(&filter->filter_info,
6548 sizeof(struct ixgbe_5tuple_filter_info));
6549 filter->queue = ntuple_filter->queue;
6550 ret = ixgbe_add_5tuple_filter(dev, filter);
6556 ixgbe_remove_5tuple_filter(dev, filter);
6562 * get a ntuple filter
6565 * dev: Pointer to struct rte_eth_dev.
6566 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6569 * - On success, zero.
6570 * - On failure, a negative value.
6573 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6574 struct rte_eth_ntuple_filter *ntuple_filter)
6576 struct ixgbe_filter_info *filter_info =
6577 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6578 struct ixgbe_5tuple_filter_info filter_5tuple;
6579 struct ixgbe_5tuple_filter *filter;
6582 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6583 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6587 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6588 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6592 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6594 if (filter == NULL) {
6595 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6598 ntuple_filter->queue = filter->queue;
6603 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6604 * @dev: pointer to rte_eth_dev structure
6605 * @filter_op:operation will be taken.
6606 * @arg: a pointer to specific structure corresponding to the filter_op
6609 * - On success, zero.
6610 * - On failure, a negative value.
6613 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6614 enum rte_filter_op filter_op,
6617 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6620 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6622 if (filter_op == RTE_ETH_FILTER_NOP)
6626 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6631 switch (filter_op) {
6632 case RTE_ETH_FILTER_ADD:
6633 ret = ixgbe_add_del_ntuple_filter(dev,
6634 (struct rte_eth_ntuple_filter *)arg,
6637 case RTE_ETH_FILTER_DELETE:
6638 ret = ixgbe_add_del_ntuple_filter(dev,
6639 (struct rte_eth_ntuple_filter *)arg,
6642 case RTE_ETH_FILTER_GET:
6643 ret = ixgbe_get_ntuple_filter(dev,
6644 (struct rte_eth_ntuple_filter *)arg);
6647 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6655 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6656 struct rte_eth_ethertype_filter *filter,
6659 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6660 struct ixgbe_filter_info *filter_info =
6661 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6665 struct ixgbe_ethertype_filter ethertype_filter;
6667 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6670 if (filter->ether_type == RTE_ETHER_TYPE_IPv4 ||
6671 filter->ether_type == RTE_ETHER_TYPE_IPv6) {
6672 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6673 " ethertype filter.", filter->ether_type);
6677 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6678 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6681 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6682 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6686 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6687 if (ret >= 0 && add) {
6688 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6689 filter->ether_type);
6692 if (ret < 0 && !add) {
6693 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6694 filter->ether_type);
6699 etqf = IXGBE_ETQF_FILTER_EN;
6700 etqf |= (uint32_t)filter->ether_type;
6701 etqs |= (uint32_t)((filter->queue <<
6702 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6703 IXGBE_ETQS_RX_QUEUE);
6704 etqs |= IXGBE_ETQS_QUEUE_EN;
6706 ethertype_filter.ethertype = filter->ether_type;
6707 ethertype_filter.etqf = etqf;
6708 ethertype_filter.etqs = etqs;
6709 ethertype_filter.conf = FALSE;
6710 ret = ixgbe_ethertype_filter_insert(filter_info,
6713 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6717 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6721 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6722 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6723 IXGBE_WRITE_FLUSH(hw);
6729 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6730 struct rte_eth_ethertype_filter *filter)
6732 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6733 struct ixgbe_filter_info *filter_info =
6734 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6735 uint32_t etqf, etqs;
6738 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6740 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6741 filter->ether_type);
6745 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6746 if (etqf & IXGBE_ETQF_FILTER_EN) {
6747 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6748 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6750 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6751 IXGBE_ETQS_RX_QUEUE_SHIFT;
6758 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6759 * @dev: pointer to rte_eth_dev structure
6760 * @filter_op:operation will be taken.
6761 * @arg: a pointer to specific structure corresponding to the filter_op
6764 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6765 enum rte_filter_op filter_op,
6768 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6771 MAC_TYPE_FILTER_SUP(hw->mac.type);
6773 if (filter_op == RTE_ETH_FILTER_NOP)
6777 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6782 switch (filter_op) {
6783 case RTE_ETH_FILTER_ADD:
6784 ret = ixgbe_add_del_ethertype_filter(dev,
6785 (struct rte_eth_ethertype_filter *)arg,
6788 case RTE_ETH_FILTER_DELETE:
6789 ret = ixgbe_add_del_ethertype_filter(dev,
6790 (struct rte_eth_ethertype_filter *)arg,
6793 case RTE_ETH_FILTER_GET:
6794 ret = ixgbe_get_ethertype_filter(dev,
6795 (struct rte_eth_ethertype_filter *)arg);
6798 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6806 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6807 enum rte_filter_type filter_type,
6808 enum rte_filter_op filter_op,
6813 switch (filter_type) {
6814 case RTE_ETH_FILTER_NTUPLE:
6815 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6817 case RTE_ETH_FILTER_ETHERTYPE:
6818 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6820 case RTE_ETH_FILTER_SYN:
6821 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6823 case RTE_ETH_FILTER_FDIR:
6824 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6826 case RTE_ETH_FILTER_L2_TUNNEL:
6827 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6829 case RTE_ETH_FILTER_GENERIC:
6830 if (filter_op != RTE_ETH_FILTER_GET)
6832 *(const void **)arg = &ixgbe_flow_ops;
6835 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6845 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6846 u8 **mc_addr_ptr, u32 *vmdq)
6851 mc_addr = *mc_addr_ptr;
6852 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6857 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6858 struct rte_ether_addr *mc_addr_set,
6859 uint32_t nb_mc_addr)
6861 struct ixgbe_hw *hw;
6864 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6865 mc_addr_list = (u8 *)mc_addr_set;
6866 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6867 ixgbe_dev_addr_list_itr, TRUE);
6871 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6873 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6874 uint64_t systime_cycles;
6876 switch (hw->mac.type) {
6877 case ixgbe_mac_X550:
6878 case ixgbe_mac_X550EM_x:
6879 case ixgbe_mac_X550EM_a:
6880 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6881 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6882 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6886 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6887 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6891 return systime_cycles;
6895 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6898 uint64_t rx_tstamp_cycles;
6900 switch (hw->mac.type) {
6901 case ixgbe_mac_X550:
6902 case ixgbe_mac_X550EM_x:
6903 case ixgbe_mac_X550EM_a:
6904 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6905 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6906 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6910 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6911 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6912 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6916 return rx_tstamp_cycles;
6920 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6922 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6923 uint64_t tx_tstamp_cycles;
6925 switch (hw->mac.type) {
6926 case ixgbe_mac_X550:
6927 case ixgbe_mac_X550EM_x:
6928 case ixgbe_mac_X550EM_a:
6929 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6930 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6931 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6935 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6936 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6937 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6941 return tx_tstamp_cycles;
6945 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6947 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6948 struct ixgbe_adapter *adapter =
6949 (struct ixgbe_adapter *)dev->data->dev_private;
6950 struct rte_eth_link link;
6951 uint32_t incval = 0;
6954 /* Get current link speed. */
6955 ixgbe_dev_link_update(dev, 1);
6956 rte_eth_linkstatus_get(dev, &link);
6958 switch (link.link_speed) {
6959 case ETH_SPEED_NUM_100M:
6960 incval = IXGBE_INCVAL_100;
6961 shift = IXGBE_INCVAL_SHIFT_100;
6963 case ETH_SPEED_NUM_1G:
6964 incval = IXGBE_INCVAL_1GB;
6965 shift = IXGBE_INCVAL_SHIFT_1GB;
6967 case ETH_SPEED_NUM_10G:
6969 incval = IXGBE_INCVAL_10GB;
6970 shift = IXGBE_INCVAL_SHIFT_10GB;
6974 switch (hw->mac.type) {
6975 case ixgbe_mac_X550:
6976 case ixgbe_mac_X550EM_x:
6977 case ixgbe_mac_X550EM_a:
6978 /* Independent of link speed. */
6980 /* Cycles read will be interpreted as ns. */
6983 case ixgbe_mac_X540:
6984 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6986 case ixgbe_mac_82599EB:
6987 incval >>= IXGBE_INCVAL_SHIFT_82599;
6988 shift -= IXGBE_INCVAL_SHIFT_82599;
6989 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6990 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6993 /* Not supported. */
6997 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6998 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6999 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7001 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7002 adapter->systime_tc.cc_shift = shift;
7003 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7005 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7006 adapter->rx_tstamp_tc.cc_shift = shift;
7007 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7009 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7010 adapter->tx_tstamp_tc.cc_shift = shift;
7011 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7015 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7017 struct ixgbe_adapter *adapter =
7018 (struct ixgbe_adapter *)dev->data->dev_private;
7020 adapter->systime_tc.nsec += delta;
7021 adapter->rx_tstamp_tc.nsec += delta;
7022 adapter->tx_tstamp_tc.nsec += delta;
7028 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7031 struct ixgbe_adapter *adapter =
7032 (struct ixgbe_adapter *)dev->data->dev_private;
7034 ns = rte_timespec_to_ns(ts);
7035 /* Set the timecounters to a new value. */
7036 adapter->systime_tc.nsec = ns;
7037 adapter->rx_tstamp_tc.nsec = ns;
7038 adapter->tx_tstamp_tc.nsec = ns;
7044 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7046 uint64_t ns, systime_cycles;
7047 struct ixgbe_adapter *adapter =
7048 (struct ixgbe_adapter *)dev->data->dev_private;
7050 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7051 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7052 *ts = rte_ns_to_timespec(ns);
7058 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7060 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7064 /* Stop the timesync system time. */
7065 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7066 /* Reset the timesync system time value. */
7067 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7068 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7070 /* Enable system time for platforms where it isn't on by default. */
7071 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7072 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7073 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7075 ixgbe_start_timecounters(dev);
7077 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7078 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7079 (RTE_ETHER_TYPE_1588 |
7080 IXGBE_ETQF_FILTER_EN |
7083 /* Enable timestamping of received PTP packets. */
7084 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7085 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7086 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7088 /* Enable timestamping of transmitted PTP packets. */
7089 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7090 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7091 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7093 IXGBE_WRITE_FLUSH(hw);
7099 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7101 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7104 /* Disable timestamping of transmitted PTP packets. */
7105 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7106 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7107 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7109 /* Disable timestamping of received PTP packets. */
7110 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7111 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7112 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7114 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7115 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7117 /* Stop incrementating the System Time registers. */
7118 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7124 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7125 struct timespec *timestamp,
7126 uint32_t flags __rte_unused)
7128 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7129 struct ixgbe_adapter *adapter =
7130 (struct ixgbe_adapter *)dev->data->dev_private;
7131 uint32_t tsync_rxctl;
7132 uint64_t rx_tstamp_cycles;
7135 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7136 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7139 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7140 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7141 *timestamp = rte_ns_to_timespec(ns);
7147 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7148 struct timespec *timestamp)
7150 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151 struct ixgbe_adapter *adapter =
7152 (struct ixgbe_adapter *)dev->data->dev_private;
7153 uint32_t tsync_txctl;
7154 uint64_t tx_tstamp_cycles;
7157 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7158 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7161 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7162 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7163 *timestamp = rte_ns_to_timespec(ns);
7169 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7174 const struct reg_info *reg_group;
7175 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7176 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7178 while ((reg_group = reg_set[g_ind++]))
7179 count += ixgbe_regs_group_count(reg_group);
7185 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7189 const struct reg_info *reg_group;
7191 while ((reg_group = ixgbevf_regs[g_ind++]))
7192 count += ixgbe_regs_group_count(reg_group);
7198 ixgbe_get_regs(struct rte_eth_dev *dev,
7199 struct rte_dev_reg_info *regs)
7201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7202 uint32_t *data = regs->data;
7205 const struct reg_info *reg_group;
7206 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7207 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7210 regs->length = ixgbe_get_reg_length(dev);
7211 regs->width = sizeof(uint32_t);
7215 /* Support only full register dump */
7216 if ((regs->length == 0) ||
7217 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7218 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7220 while ((reg_group = reg_set[g_ind++]))
7221 count += ixgbe_read_regs_group(dev, &data[count],
7230 ixgbevf_get_regs(struct rte_eth_dev *dev,
7231 struct rte_dev_reg_info *regs)
7233 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7234 uint32_t *data = regs->data;
7237 const struct reg_info *reg_group;
7240 regs->length = ixgbevf_get_reg_length(dev);
7241 regs->width = sizeof(uint32_t);
7245 /* Support only full register dump */
7246 if ((regs->length == 0) ||
7247 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7248 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7250 while ((reg_group = ixgbevf_regs[g_ind++]))
7251 count += ixgbe_read_regs_group(dev, &data[count],
7260 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7262 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7264 /* Return unit is byte count */
7265 return hw->eeprom.word_size * 2;
7269 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7270 struct rte_dev_eeprom_info *in_eeprom)
7272 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7273 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7274 uint16_t *data = in_eeprom->data;
7277 first = in_eeprom->offset >> 1;
7278 length = in_eeprom->length >> 1;
7279 if ((first > hw->eeprom.word_size) ||
7280 ((first + length) > hw->eeprom.word_size))
7283 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7285 return eeprom->ops.read_buffer(hw, first, length, data);
7289 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7290 struct rte_dev_eeprom_info *in_eeprom)
7292 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7293 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7294 uint16_t *data = in_eeprom->data;
7297 first = in_eeprom->offset >> 1;
7298 length = in_eeprom->length >> 1;
7299 if ((first > hw->eeprom.word_size) ||
7300 ((first + length) > hw->eeprom.word_size))
7303 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7305 return eeprom->ops.write_buffer(hw, first, length, data);
7309 ixgbe_get_module_info(struct rte_eth_dev *dev,
7310 struct rte_eth_dev_module_info *modinfo)
7312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7314 uint8_t sff8472_rev, addr_mode;
7315 bool page_swap = false;
7317 /* Check whether we support SFF-8472 or not */
7318 status = hw->phy.ops.read_i2c_eeprom(hw,
7319 IXGBE_SFF_SFF_8472_COMP,
7324 /* addressing mode is not supported */
7325 status = hw->phy.ops.read_i2c_eeprom(hw,
7326 IXGBE_SFF_SFF_8472_SWAP,
7331 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7333 "Address change required to access page 0xA2, "
7334 "but not supported. Please report the module "
7335 "type to the driver maintainers.");
7339 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7340 /* We have a SFP, but it does not support SFF-8472 */
7341 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7342 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7344 /* We have a SFP which supports a revision of SFF-8472. */
7345 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7346 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7353 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7354 struct rte_dev_eeprom_info *info)
7356 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7357 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7358 uint8_t databyte = 0xFF;
7359 uint8_t *data = info->data;
7362 if (info->length == 0)
7365 for (i = info->offset; i < info->offset + info->length; i++) {
7366 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7367 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7369 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7374 data[i - info->offset] = databyte;
7381 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7383 case ixgbe_mac_X550:
7384 case ixgbe_mac_X550EM_x:
7385 case ixgbe_mac_X550EM_a:
7386 return ETH_RSS_RETA_SIZE_512;
7387 case ixgbe_mac_X550_vf:
7388 case ixgbe_mac_X550EM_x_vf:
7389 case ixgbe_mac_X550EM_a_vf:
7390 return ETH_RSS_RETA_SIZE_64;
7392 return ETH_RSS_RETA_SIZE_128;
7397 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7399 case ixgbe_mac_X550:
7400 case ixgbe_mac_X550EM_x:
7401 case ixgbe_mac_X550EM_a:
7402 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7403 return IXGBE_RETA(reta_idx >> 2);
7405 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7406 case ixgbe_mac_X550_vf:
7407 case ixgbe_mac_X550EM_x_vf:
7408 case ixgbe_mac_X550EM_a_vf:
7409 return IXGBE_VFRETA(reta_idx >> 2);
7411 return IXGBE_RETA(reta_idx >> 2);
7416 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7418 case ixgbe_mac_X550_vf:
7419 case ixgbe_mac_X550EM_x_vf:
7420 case ixgbe_mac_X550EM_a_vf:
7421 return IXGBE_VFMRQC;
7428 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7430 case ixgbe_mac_X550_vf:
7431 case ixgbe_mac_X550EM_x_vf:
7432 case ixgbe_mac_X550EM_a_vf:
7433 return IXGBE_VFRSSRK(i);
7435 return IXGBE_RSSRK(i);
7440 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7442 case ixgbe_mac_82599_vf:
7443 case ixgbe_mac_X540_vf:
7451 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7452 struct rte_eth_dcb_info *dcb_info)
7454 struct ixgbe_dcb_config *dcb_config =
7455 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7456 struct ixgbe_dcb_tc_config *tc;
7457 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7461 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7462 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7464 dcb_info->nb_tcs = 1;
7466 tc_queue = &dcb_info->tc_queue;
7467 nb_tcs = dcb_info->nb_tcs;
7469 if (dcb_config->vt_mode) { /* vt is enabled*/
7470 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7471 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7472 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7473 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7474 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7475 for (j = 0; j < nb_tcs; j++) {
7476 tc_queue->tc_rxq[0][j].base = j;
7477 tc_queue->tc_rxq[0][j].nb_queue = 1;
7478 tc_queue->tc_txq[0][j].base = j;
7479 tc_queue->tc_txq[0][j].nb_queue = 1;
7482 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7483 for (j = 0; j < nb_tcs; j++) {
7484 tc_queue->tc_rxq[i][j].base =
7486 tc_queue->tc_rxq[i][j].nb_queue = 1;
7487 tc_queue->tc_txq[i][j].base =
7489 tc_queue->tc_txq[i][j].nb_queue = 1;
7493 } else { /* vt is disabled*/
7494 struct rte_eth_dcb_rx_conf *rx_conf =
7495 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7496 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7497 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7498 if (dcb_info->nb_tcs == ETH_4_TCS) {
7499 for (i = 0; i < dcb_info->nb_tcs; i++) {
7500 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7501 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7503 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7504 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7505 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7506 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7507 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7508 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7509 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7510 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7511 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7512 for (i = 0; i < dcb_info->nb_tcs; i++) {
7513 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7514 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7516 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7517 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7518 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7519 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7520 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7521 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7522 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7523 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7524 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7525 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7526 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7527 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7528 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7529 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7530 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7531 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7534 for (i = 0; i < dcb_info->nb_tcs; i++) {
7535 tc = &dcb_config->tc_config[i];
7536 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7541 /* Update e-tag ether type */
7543 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7544 uint16_t ether_type)
7546 uint32_t etag_etype;
7548 if (hw->mac.type != ixgbe_mac_X550 &&
7549 hw->mac.type != ixgbe_mac_X550EM_x &&
7550 hw->mac.type != ixgbe_mac_X550EM_a) {
7554 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7555 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7556 etag_etype |= ether_type;
7557 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7558 IXGBE_WRITE_FLUSH(hw);
7563 /* Config l2 tunnel ether type */
7565 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7566 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7569 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7570 struct ixgbe_l2_tn_info *l2_tn_info =
7571 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7573 if (l2_tunnel == NULL)
7576 switch (l2_tunnel->l2_tunnel_type) {
7577 case RTE_L2_TUNNEL_TYPE_E_TAG:
7578 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7579 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7582 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7590 /* Enable e-tag tunnel */
7592 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7594 uint32_t etag_etype;
7596 if (hw->mac.type != ixgbe_mac_X550 &&
7597 hw->mac.type != ixgbe_mac_X550EM_x &&
7598 hw->mac.type != ixgbe_mac_X550EM_a) {
7602 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7603 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7604 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7605 IXGBE_WRITE_FLUSH(hw);
7610 /* Enable l2 tunnel */
7612 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7613 enum rte_eth_tunnel_type l2_tunnel_type)
7616 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7617 struct ixgbe_l2_tn_info *l2_tn_info =
7618 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7620 switch (l2_tunnel_type) {
7621 case RTE_L2_TUNNEL_TYPE_E_TAG:
7622 l2_tn_info->e_tag_en = TRUE;
7623 ret = ixgbe_e_tag_enable(hw);
7626 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7634 /* Disable e-tag tunnel */
7636 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7638 uint32_t etag_etype;
7640 if (hw->mac.type != ixgbe_mac_X550 &&
7641 hw->mac.type != ixgbe_mac_X550EM_x &&
7642 hw->mac.type != ixgbe_mac_X550EM_a) {
7646 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7647 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7648 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7649 IXGBE_WRITE_FLUSH(hw);
7654 /* Disable l2 tunnel */
7656 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7657 enum rte_eth_tunnel_type l2_tunnel_type)
7660 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7661 struct ixgbe_l2_tn_info *l2_tn_info =
7662 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7664 switch (l2_tunnel_type) {
7665 case RTE_L2_TUNNEL_TYPE_E_TAG:
7666 l2_tn_info->e_tag_en = FALSE;
7667 ret = ixgbe_e_tag_disable(hw);
7670 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7679 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7680 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7683 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7684 uint32_t i, rar_entries;
7685 uint32_t rar_low, rar_high;
7687 if (hw->mac.type != ixgbe_mac_X550 &&
7688 hw->mac.type != ixgbe_mac_X550EM_x &&
7689 hw->mac.type != ixgbe_mac_X550EM_a) {
7693 rar_entries = ixgbe_get_num_rx_addrs(hw);
7695 for (i = 1; i < rar_entries; i++) {
7696 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7697 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7698 if ((rar_high & IXGBE_RAH_AV) &&
7699 (rar_high & IXGBE_RAH_ADTYPE) &&
7700 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7701 l2_tunnel->tunnel_id)) {
7702 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7703 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7705 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7715 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7716 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7719 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7720 uint32_t i, rar_entries;
7721 uint32_t rar_low, rar_high;
7723 if (hw->mac.type != ixgbe_mac_X550 &&
7724 hw->mac.type != ixgbe_mac_X550EM_x &&
7725 hw->mac.type != ixgbe_mac_X550EM_a) {
7729 /* One entry for one tunnel. Try to remove potential existing entry. */
7730 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7732 rar_entries = ixgbe_get_num_rx_addrs(hw);
7734 for (i = 1; i < rar_entries; i++) {
7735 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7736 if (rar_high & IXGBE_RAH_AV) {
7739 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7740 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7741 rar_low = l2_tunnel->tunnel_id;
7743 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7744 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7750 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7751 " Please remove a rule before adding a new one.");
7755 static inline struct ixgbe_l2_tn_filter *
7756 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7757 struct ixgbe_l2_tn_key *key)
7761 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7765 return l2_tn_info->hash_map[ret];
7769 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7770 struct ixgbe_l2_tn_filter *l2_tn_filter)
7774 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7775 &l2_tn_filter->key);
7779 "Failed to insert L2 tunnel filter"
7780 " to hash table %d!",
7785 l2_tn_info->hash_map[ret] = l2_tn_filter;
7787 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7793 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7794 struct ixgbe_l2_tn_key *key)
7797 struct ixgbe_l2_tn_filter *l2_tn_filter;
7799 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7803 "No such L2 tunnel filter to delete %d!",
7808 l2_tn_filter = l2_tn_info->hash_map[ret];
7809 l2_tn_info->hash_map[ret] = NULL;
7811 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7812 rte_free(l2_tn_filter);
7817 /* Add l2 tunnel filter */
7819 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7820 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7824 struct ixgbe_l2_tn_info *l2_tn_info =
7825 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7826 struct ixgbe_l2_tn_key key;
7827 struct ixgbe_l2_tn_filter *node;
7830 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7831 key.tn_id = l2_tunnel->tunnel_id;
7833 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7837 "The L2 tunnel filter already exists!");
7841 node = rte_zmalloc("ixgbe_l2_tn",
7842 sizeof(struct ixgbe_l2_tn_filter),
7847 rte_memcpy(&node->key,
7849 sizeof(struct ixgbe_l2_tn_key));
7850 node->pool = l2_tunnel->pool;
7851 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7858 switch (l2_tunnel->l2_tunnel_type) {
7859 case RTE_L2_TUNNEL_TYPE_E_TAG:
7860 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7863 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7868 if ((!restore) && (ret < 0))
7869 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7874 /* Delete l2 tunnel filter */
7876 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7877 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7880 struct ixgbe_l2_tn_info *l2_tn_info =
7881 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7882 struct ixgbe_l2_tn_key key;
7884 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7885 key.tn_id = l2_tunnel->tunnel_id;
7886 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7890 switch (l2_tunnel->l2_tunnel_type) {
7891 case RTE_L2_TUNNEL_TYPE_E_TAG:
7892 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7895 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7904 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7905 * @dev: pointer to rte_eth_dev structure
7906 * @filter_op:operation will be taken.
7907 * @arg: a pointer to specific structure corresponding to the filter_op
7910 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7911 enum rte_filter_op filter_op,
7916 if (filter_op == RTE_ETH_FILTER_NOP)
7920 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7925 switch (filter_op) {
7926 case RTE_ETH_FILTER_ADD:
7927 ret = ixgbe_dev_l2_tunnel_filter_add
7929 (struct rte_eth_l2_tunnel_conf *)arg,
7932 case RTE_ETH_FILTER_DELETE:
7933 ret = ixgbe_dev_l2_tunnel_filter_del
7935 (struct rte_eth_l2_tunnel_conf *)arg);
7938 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7946 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7952 if (hw->mac.type != ixgbe_mac_X550 &&
7953 hw->mac.type != ixgbe_mac_X550EM_x &&
7954 hw->mac.type != ixgbe_mac_X550EM_a) {
7958 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7959 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7961 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7962 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7967 /* Enable l2 tunnel forwarding */
7969 ixgbe_dev_l2_tunnel_forwarding_enable
7970 (struct rte_eth_dev *dev,
7971 enum rte_eth_tunnel_type l2_tunnel_type)
7973 struct ixgbe_l2_tn_info *l2_tn_info =
7974 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7977 switch (l2_tunnel_type) {
7978 case RTE_L2_TUNNEL_TYPE_E_TAG:
7979 l2_tn_info->e_tag_fwd_en = TRUE;
7980 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7983 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7991 /* Disable l2 tunnel forwarding */
7993 ixgbe_dev_l2_tunnel_forwarding_disable
7994 (struct rte_eth_dev *dev,
7995 enum rte_eth_tunnel_type l2_tunnel_type)
7997 struct ixgbe_l2_tn_info *l2_tn_info =
7998 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8001 switch (l2_tunnel_type) {
8002 case RTE_L2_TUNNEL_TYPE_E_TAG:
8003 l2_tn_info->e_tag_fwd_en = FALSE;
8004 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8007 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8016 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8017 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8020 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8022 uint32_t vmtir, vmvir;
8023 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8025 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8027 "VF id %u should be less than %u",
8033 if (hw->mac.type != ixgbe_mac_X550 &&
8034 hw->mac.type != ixgbe_mac_X550EM_x &&
8035 hw->mac.type != ixgbe_mac_X550EM_a) {
8040 vmtir = l2_tunnel->tunnel_id;
8044 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8046 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8047 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8049 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8050 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8055 /* Enable l2 tunnel tag insertion */
8057 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8058 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8062 switch (l2_tunnel->l2_tunnel_type) {
8063 case RTE_L2_TUNNEL_TYPE_E_TAG:
8064 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8067 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8075 /* Disable l2 tunnel tag insertion */
8077 ixgbe_dev_l2_tunnel_insertion_disable
8078 (struct rte_eth_dev *dev,
8079 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8083 switch (l2_tunnel->l2_tunnel_type) {
8084 case RTE_L2_TUNNEL_TYPE_E_TAG:
8085 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8088 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8097 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8104 if (hw->mac.type != ixgbe_mac_X550 &&
8105 hw->mac.type != ixgbe_mac_X550EM_x &&
8106 hw->mac.type != ixgbe_mac_X550EM_a) {
8110 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8112 qde |= IXGBE_QDE_STRIP_TAG;
8114 qde &= ~IXGBE_QDE_STRIP_TAG;
8115 qde &= ~IXGBE_QDE_READ;
8116 qde |= IXGBE_QDE_WRITE;
8117 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8122 /* Enable l2 tunnel tag stripping */
8124 ixgbe_dev_l2_tunnel_stripping_enable
8125 (struct rte_eth_dev *dev,
8126 enum rte_eth_tunnel_type l2_tunnel_type)
8130 switch (l2_tunnel_type) {
8131 case RTE_L2_TUNNEL_TYPE_E_TAG:
8132 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8135 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8143 /* Disable l2 tunnel tag stripping */
8145 ixgbe_dev_l2_tunnel_stripping_disable
8146 (struct rte_eth_dev *dev,
8147 enum rte_eth_tunnel_type l2_tunnel_type)
8151 switch (l2_tunnel_type) {
8152 case RTE_L2_TUNNEL_TYPE_E_TAG:
8153 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8156 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8164 /* Enable/disable l2 tunnel offload functions */
8166 ixgbe_dev_l2_tunnel_offload_set
8167 (struct rte_eth_dev *dev,
8168 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8174 if (l2_tunnel == NULL)
8178 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8180 ret = ixgbe_dev_l2_tunnel_enable(
8182 l2_tunnel->l2_tunnel_type);
8184 ret = ixgbe_dev_l2_tunnel_disable(
8186 l2_tunnel->l2_tunnel_type);
8189 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8191 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8195 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8200 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8202 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8204 l2_tunnel->l2_tunnel_type);
8206 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8208 l2_tunnel->l2_tunnel_type);
8211 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8213 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8215 l2_tunnel->l2_tunnel_type);
8217 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8219 l2_tunnel->l2_tunnel_type);
8226 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8229 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8230 IXGBE_WRITE_FLUSH(hw);
8235 /* There's only one register for VxLAN UDP port.
8236 * So, we cannot add several ports. Will update it.
8239 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8243 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8247 return ixgbe_update_vxlan_port(hw, port);
8250 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8251 * UDP port, it must have a value.
8252 * So, will reset it to the original value 0.
8255 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8260 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8262 if (cur_port != port) {
8263 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8267 return ixgbe_update_vxlan_port(hw, 0);
8270 /* Add UDP tunneling port */
8272 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8273 struct rte_eth_udp_tunnel *udp_tunnel)
8276 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8278 if (hw->mac.type != ixgbe_mac_X550 &&
8279 hw->mac.type != ixgbe_mac_X550EM_x &&
8280 hw->mac.type != ixgbe_mac_X550EM_a) {
8284 if (udp_tunnel == NULL)
8287 switch (udp_tunnel->prot_type) {
8288 case RTE_TUNNEL_TYPE_VXLAN:
8289 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8292 case RTE_TUNNEL_TYPE_GENEVE:
8293 case RTE_TUNNEL_TYPE_TEREDO:
8294 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8299 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8307 /* Remove UDP tunneling port */
8309 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8310 struct rte_eth_udp_tunnel *udp_tunnel)
8313 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8315 if (hw->mac.type != ixgbe_mac_X550 &&
8316 hw->mac.type != ixgbe_mac_X550EM_x &&
8317 hw->mac.type != ixgbe_mac_X550EM_a) {
8321 if (udp_tunnel == NULL)
8324 switch (udp_tunnel->prot_type) {
8325 case RTE_TUNNEL_TYPE_VXLAN:
8326 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8328 case RTE_TUNNEL_TYPE_GENEVE:
8329 case RTE_TUNNEL_TYPE_TEREDO:
8330 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8334 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8343 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8345 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8347 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC);
8351 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8353 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8355 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8359 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8361 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8363 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8367 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8369 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8371 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8374 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8376 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8379 /* peek the message first */
8380 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8382 /* PF reset VF event */
8383 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8384 /* dummy mbx read to ack pf */
8385 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8387 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8393 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8396 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8397 struct ixgbe_interrupt *intr =
8398 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8399 ixgbevf_intr_disable(dev);
8401 /* read-on-clear nic registers here */
8402 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8405 /* only one misc vector supported - mailbox */
8406 eicr &= IXGBE_VTEICR_MASK;
8407 if (eicr == IXGBE_MISC_VEC_ID)
8408 intr->flags |= IXGBE_FLAG_MAILBOX;
8414 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8416 struct ixgbe_interrupt *intr =
8417 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8419 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8420 ixgbevf_mbx_process(dev);
8421 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8424 ixgbevf_intr_enable(dev);
8430 ixgbevf_dev_interrupt_handler(void *param)
8432 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8434 ixgbevf_dev_interrupt_get_status(dev);
8435 ixgbevf_dev_interrupt_action(dev);
8439 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8440 * @hw: pointer to hardware structure
8442 * Stops the transmit data path and waits for the HW to internally empty
8443 * the Tx security block
8445 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8447 #define IXGBE_MAX_SECTX_POLL 40
8452 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8453 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8454 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8455 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8456 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8457 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8459 /* Use interrupt-safe sleep just in case */
8463 /* For informational purposes only */
8464 if (i >= IXGBE_MAX_SECTX_POLL)
8465 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8466 "path fully disabled. Continuing with init.");
8468 return IXGBE_SUCCESS;
8472 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8473 * @hw: pointer to hardware structure
8475 * Enables the transmit data path.
8477 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8481 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8482 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8483 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8484 IXGBE_WRITE_FLUSH(hw);
8486 return IXGBE_SUCCESS;
8489 /* restore n-tuple filter */
8491 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8493 struct ixgbe_filter_info *filter_info =
8494 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8495 struct ixgbe_5tuple_filter *node;
8497 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8498 ixgbe_inject_5tuple_filter(dev, node);
8502 /* restore ethernet type filter */
8504 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8506 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8507 struct ixgbe_filter_info *filter_info =
8508 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8511 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8512 if (filter_info->ethertype_mask & (1 << i)) {
8513 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8514 filter_info->ethertype_filters[i].etqf);
8515 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8516 filter_info->ethertype_filters[i].etqs);
8517 IXGBE_WRITE_FLUSH(hw);
8522 /* restore SYN filter */
8524 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8526 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8527 struct ixgbe_filter_info *filter_info =
8528 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8531 synqf = filter_info->syn_info;
8533 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8534 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8535 IXGBE_WRITE_FLUSH(hw);
8539 /* restore L2 tunnel filter */
8541 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8543 struct ixgbe_l2_tn_info *l2_tn_info =
8544 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8545 struct ixgbe_l2_tn_filter *node;
8546 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8548 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8549 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8550 l2_tn_conf.tunnel_id = node->key.tn_id;
8551 l2_tn_conf.pool = node->pool;
8552 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8556 /* restore rss filter */
8558 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8560 struct ixgbe_filter_info *filter_info =
8561 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8563 if (filter_info->rss_info.conf.queue_num)
8564 ixgbe_config_rss_filter(dev,
8565 &filter_info->rss_info, TRUE);
8569 ixgbe_filter_restore(struct rte_eth_dev *dev)
8571 ixgbe_ntuple_filter_restore(dev);
8572 ixgbe_ethertype_filter_restore(dev);
8573 ixgbe_syn_filter_restore(dev);
8574 ixgbe_fdir_filter_restore(dev);
8575 ixgbe_l2_tn_filter_restore(dev);
8576 ixgbe_rss_filter_restore(dev);
8582 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8584 struct ixgbe_l2_tn_info *l2_tn_info =
8585 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8588 if (l2_tn_info->e_tag_en)
8589 (void)ixgbe_e_tag_enable(hw);
8591 if (l2_tn_info->e_tag_fwd_en)
8592 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8594 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8597 /* remove all the n-tuple filters */
8599 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8601 struct ixgbe_filter_info *filter_info =
8602 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8603 struct ixgbe_5tuple_filter *p_5tuple;
8605 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8606 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8609 /* remove all the ether type filters */
8611 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8613 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8614 struct ixgbe_filter_info *filter_info =
8615 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8618 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8619 if (filter_info->ethertype_mask & (1 << i) &&
8620 !filter_info->ethertype_filters[i].conf) {
8621 (void)ixgbe_ethertype_filter_remove(filter_info,
8623 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8624 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8625 IXGBE_WRITE_FLUSH(hw);
8630 /* remove the SYN filter */
8632 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8634 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8635 struct ixgbe_filter_info *filter_info =
8636 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8638 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8639 filter_info->syn_info = 0;
8641 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8642 IXGBE_WRITE_FLUSH(hw);
8646 /* remove all the L2 tunnel filters */
8648 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8650 struct ixgbe_l2_tn_info *l2_tn_info =
8651 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8652 struct ixgbe_l2_tn_filter *l2_tn_filter;
8653 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8656 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8657 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8658 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8659 l2_tn_conf.pool = l2_tn_filter->pool;
8660 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8668 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8669 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8670 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8671 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8672 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8673 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8675 RTE_INIT(ixgbe_init_log)
8677 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8678 if (ixgbe_logtype_init >= 0)
8679 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8680 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8681 if (ixgbe_logtype_driver >= 0)
8682 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);