drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define IXGBE_TIMINCA_16NS_SHIFT 24
 130 #define IXGBE_TIMINCA_INCVALUE   16000000
 131 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 132                                   | IXGBE_TIMINCA_INCVALUE)
 133
 134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 147                                 int wait_to_complete);
 148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 149                                 struct rte_eth_stats *stats);
 150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_xstats *xstats, unsigned n);
 152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 153                                   struct rte_eth_xstats *xstats, unsigned n);
 154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 157                                              uint16_t queue_id,
 158                                              uint8_t stat_idx,
 159                                              uint8_t is_rx);
 160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_dev_info *dev_info);
 162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 163                                  struct rte_eth_dev_info *dev_info);
 164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 165
 166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 167                 uint16_t vlan_id, int on);
 168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 170                 uint16_t queue, bool on);
 171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 172                 int on);
 173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 178
 179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 182                                struct rte_eth_fc_conf *fc_conf);
 183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 184                                struct rte_eth_fc_conf *fc_conf);
 185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 186                 struct rte_eth_pfc_conf *pfc_conf);
 187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 188                         struct rte_eth_rss_reta_entry64 *reta_conf,
 189                         uint16_t reta_size);
 190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 191                         struct rte_eth_rss_reta_entry64 *reta_conf,
 192                         uint16_t reta_size);
 193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 199                 void *param);
 200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 202                 uint32_t index, uint32_t pool);
 203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 205                                            struct ether_addr *mac_addr);
 206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 207
 208 /* For Virtual Function support */
 209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 211 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 212 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 213 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 214 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 215 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 216 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 217 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 218                 struct rte_eth_stats *stats);
 219 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 220 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 221                 uint16_t vlan_id, int on);
 222 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 223                 uint16_t queue, int on);
 224 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 225 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 226 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 227                                             uint16_t queue_id);
 228 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 229                                              uint16_t queue_id);
 230 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 231                                  uint8_t queue, uint8_t msix_vector);
 232 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 233
 234 /* For Eth VMDQ APIs support */
 235 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 236                 ether_addr* mac_addr,uint8_t on);
 237 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 238 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 239                 uint16_t rx_mask, uint8_t on);
 240 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 241 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 242 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 243                 uint64_t pool_mask,uint8_t vlan_on);
 244 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 245                 struct rte_eth_mirror_conf *mirror_conf,
 246                 uint8_t rule_id, uint8_t on);
 247 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 248                 uint8_t rule_id);
 249 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 250                                           uint16_t queue_id);
 251 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 252                                            uint16_t queue_id);
 253 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 254                                uint8_t queue, uint8_t msix_vector);
 255 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 256
 257 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 258                 uint16_t queue_idx, uint16_t tx_rate);
 259 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 260                 uint16_t tx_rate, uint64_t q_msk);
 261
 262 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 263                                  struct ether_addr *mac_addr,
 264                                  uint32_t index, uint32_t pool);
 265 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 266 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 267                                              struct ether_addr *mac_addr);
 268 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 269                         struct rte_eth_syn_filter *filter,
 270                         bool add);
 271 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 272                         struct rte_eth_syn_filter *filter);
 273 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 274                         enum rte_filter_op filter_op,
 275                         void *arg);
 276 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 277                         struct ixgbe_5tuple_filter *filter);
 278 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 279                         struct ixgbe_5tuple_filter *filter);
 280 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 281                         struct rte_eth_ntuple_filter *filter,
 282                         bool add);
 283 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 284                                 enum rte_filter_op filter_op,
 285                                 void *arg);
 286 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 287                         struct rte_eth_ntuple_filter *filter);
 288 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 289                         struct rte_eth_ethertype_filter *filter,
 290                         bool add);
 291 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 292                                 enum rte_filter_op filter_op,
 293                                 void *arg);
 294 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 295                         struct rte_eth_ethertype_filter *filter);
 296 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 297                      enum rte_filter_type filter_type,
 298                      enum rte_filter_op filter_op,
 299                      void *arg);
 300 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 301
 302 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 303                                       struct ether_addr *mc_addr_set,
 304                                       uint32_t nb_mc_addr);
 305 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 306                                    struct rte_eth_dcb_info *dcb_info);
 307
 308 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 309 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 310                             struct rte_dev_reg_info *regs);
 311 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 312 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 313                                 struct rte_dev_eeprom_info *eeprom);
 314 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 315                                 struct rte_dev_eeprom_info *eeprom);
 316
 317 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 318 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 319                                 struct rte_dev_reg_info *regs);
 320
 321 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 322 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 323 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 324                                             struct timespec *timestamp,
 325                                             uint32_t flags);
 326 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 327                                             struct timespec *timestamp);
 328
 329 /*
 330  * Define VF Stats MACRO for Non "cleared on read" register
 331  */
 332 #define UPDATE_VF_STAT(reg, last, cur)                          \
 333 {                                                               \
 334         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 335         cur += (latest - last) & UINT_MAX;                      \
 336         last = latest;                                          \
 337 }
 338
 339 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 340 {                                                                \
 341         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 342         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 343         u64 latest = ((new_msb << 32) | new_lsb);                \
 344         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 345         last = latest;                                           \
 346 }
 347
 348 #define IXGBE_SET_HWSTRIP(h, q) do{\
 349                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 350                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 351                 (h)->bitmap[idx] |= 1 << bit;\
 352         }while(0)
 353
 354 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 355                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 356                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 357                 (h)->bitmap[idx] &= ~(1 << bit);\
 358         }while(0)
 359
 360 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 361                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 362                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 363                 (r) = (h)->bitmap[idx] >> bit & 1;\
 364         }while(0)
 365
 366 /*
 367  * The set of PCI devices this driver supports
 368  */
 369 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 370
 371 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 372 #include "rte_pci_dev_ids.h"
 373
 374 { .vendor_id = 0, /* sentinel */ },
 375 };
 376
 377
 378 /*
 379  * The set of PCI devices this driver supports (for 82599 VF)
 380  */
 381 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 382
 383 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 384 #include "rte_pci_dev_ids.h"
 385 { .vendor_id = 0, /* sentinel */ },
 386
 387 };
 388
 389 static const struct rte_eth_desc_lim rx_desc_lim = {
 390         .nb_max = IXGBE_MAX_RING_DESC,
 391         .nb_min = IXGBE_MIN_RING_DESC,
 392         .nb_align = IXGBE_RXD_ALIGN,
 393 };
 394
 395 static const struct rte_eth_desc_lim tx_desc_lim = {
 396         .nb_max = IXGBE_MAX_RING_DESC,
 397         .nb_min = IXGBE_MIN_RING_DESC,
 398         .nb_align = IXGBE_TXD_ALIGN,
 399 };
 400
 401 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 402         .dev_configure        = ixgbe_dev_configure,
 403         .dev_start            = ixgbe_dev_start,
 404         .dev_stop             = ixgbe_dev_stop,
 405         .dev_set_link_up    = ixgbe_dev_set_link_up,
 406         .dev_set_link_down  = ixgbe_dev_set_link_down,
 407         .dev_close            = ixgbe_dev_close,
 408         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 409         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 410         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 411         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 412         .link_update          = ixgbe_dev_link_update,
 413         .stats_get            = ixgbe_dev_stats_get,
 414         .xstats_get           = ixgbe_dev_xstats_get,
 415         .stats_reset          = ixgbe_dev_stats_reset,
 416         .xstats_reset         = ixgbe_dev_xstats_reset,
 417         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 418         .dev_infos_get        = ixgbe_dev_info_get,
 419         .mtu_set              = ixgbe_dev_mtu_set,
 420         .vlan_filter_set      = ixgbe_vlan_filter_set,
 421         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 422         .vlan_offload_set     = ixgbe_vlan_offload_set,
 423         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 424         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 425         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 426         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 427         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 428         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 429         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 430         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 431         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 432         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 433         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 434         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 435         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 436         .dev_led_on           = ixgbe_dev_led_on,
 437         .dev_led_off          = ixgbe_dev_led_off,
 438         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 439         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 440         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 441         .mac_addr_add         = ixgbe_add_rar,
 442         .mac_addr_remove      = ixgbe_remove_rar,
 443         .mac_addr_set         = ixgbe_set_default_mac_addr,
 444         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 445         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 446         .mirror_rule_set      = ixgbe_mirror_rule_set,
 447         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 448         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 449         .set_vf_rx            = ixgbe_set_pool_rx,
 450         .set_vf_tx            = ixgbe_set_pool_tx,
 451         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 452         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 453         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 454         .reta_update          = ixgbe_dev_rss_reta_update,
 455         .reta_query           = ixgbe_dev_rss_reta_query,
 456 #ifdef RTE_NIC_BYPASS
 457         .bypass_init          = ixgbe_bypass_init,
 458         .bypass_state_set     = ixgbe_bypass_state_store,
 459         .bypass_state_show    = ixgbe_bypass_state_show,
 460         .bypass_event_set     = ixgbe_bypass_event_store,
 461         .bypass_event_show    = ixgbe_bypass_event_show,
 462         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 463         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 464         .bypass_ver_show      = ixgbe_bypass_ver_show,
 465         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 466 #endif /* RTE_NIC_BYPASS */
 467         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 468         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 469         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 470         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 471         .rxq_info_get         = ixgbe_rxq_info_get,
 472         .txq_info_get         = ixgbe_txq_info_get,
 473         .timesync_enable      = ixgbe_timesync_enable,
 474         .timesync_disable     = ixgbe_timesync_disable,
 475         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 476         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 477         .get_reg_length       = ixgbe_get_reg_length,
 478         .get_reg              = ixgbe_get_regs,
 479         .get_eeprom_length    = ixgbe_get_eeprom_length,
 480         .get_eeprom           = ixgbe_get_eeprom,
 481         .set_eeprom           = ixgbe_set_eeprom,
 482         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 483 };
 484
 485 /*
 486  * dev_ops for virtual function, bare necessities for basic vf
 487  * operation have been implemented
 488  */
 489 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 490         .dev_configure        = ixgbevf_dev_configure,
 491         .dev_start            = ixgbevf_dev_start,
 492         .dev_stop             = ixgbevf_dev_stop,
 493         .link_update          = ixgbe_dev_link_update,
 494         .stats_get            = ixgbevf_dev_stats_get,
 495         .xstats_get           = ixgbevf_dev_xstats_get,
 496         .stats_reset          = ixgbevf_dev_stats_reset,
 497         .xstats_reset         = ixgbevf_dev_stats_reset,
 498         .dev_close            = ixgbevf_dev_close,
 499         .dev_infos_get        = ixgbevf_dev_info_get,
 500         .mtu_set              = ixgbevf_dev_set_mtu,
 501         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 502         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 503         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 504         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 505         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 506         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 507         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 508         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 509         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 510         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 511         .mac_addr_add         = ixgbevf_add_mac_addr,
 512         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 513         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 514         .rxq_info_get         = ixgbe_rxq_info_get,
 515         .txq_info_get         = ixgbe_txq_info_get,
 516         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 517         .get_reg_length       = ixgbevf_get_reg_length,
 518         .get_reg              = ixgbevf_get_regs,
 519         .reta_update          = ixgbe_dev_rss_reta_update,
 520         .reta_query           = ixgbe_dev_rss_reta_query,
 521         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 522         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 523 };
 524
 525 /* store statistics names and its offset in stats structure */
 526 struct rte_ixgbe_xstats_name_off {
 527         char name[RTE_ETH_XSTATS_NAME_SIZE];
 528         unsigned offset;
 529 };
 530
 531 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 532         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 533         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 534         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 535         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 536         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 537         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 538         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 539         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 540         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 541         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 542         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 543         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 544         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 545         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 546         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 547                 prc1023)},
 548         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 549                 prc1522)},
 550         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 551         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 552         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 553         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 554         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 555         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 556         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 557         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 558         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 559         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 560         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 561         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 562         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 563         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 564         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 565         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 566         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 567                 ptc1023)},
 568         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 569                 ptc1522)},
 570         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 571         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 572         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 573         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 574
 575         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 576                 fdirustat_add)},
 577         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 578                 fdirustat_remove)},
 579         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 580                 fdirfstat_fadd)},
 581         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 582                 fdirfstat_fremove)},
 583         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 584                 fdirmatch)},
 585         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 586                 fdirmiss)},
 587
 588         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 589         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 590         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 591                 fclast)},
 592         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 593         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 594         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 595         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 596         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 597                 fcoe_noddp)},
 598         {"rx_fcoe_no_direct_data_placement_ext_buff",
 599                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 600
 601         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 602                 lxontxc)},
 603         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 604                 lxonrxc)},
 605         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 606                 lxofftxc)},
 607         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 608                 lxoffrxc)},
 609         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 610 };
 611
 612 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 613                            sizeof(rte_ixgbe_stats_strings[0]))
 614
 615 /* Per-queue statistics */
 616 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
 617 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
 618 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
 619
 620 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
 621
 622 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 623         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 624 };
 625
 626 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 627                 sizeof(rte_ixgbevf_stats_strings[0]))
 628
 629 /**
 630  * Atomically reads the link status information from global
 631  * structure rte_eth_dev.
 632  *
 633  * @param dev
 634  *   - Pointer to the structure rte_eth_dev to read from.
 635  *   - Pointer to the buffer to be saved with the link status.
 636  *
 637  * @return
 638  *   - On success, zero.
 639  *   - On failure, negative value.
 640  */
 641 static inline int
 642 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 643                                 struct rte_eth_link *link)
 644 {
 645         struct rte_eth_link *dst = link;
 646         struct rte_eth_link *src = &(dev->data->dev_link);
 647
 648         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 649                                         *(uint64_t *)src) == 0)
 650                 return -1;
 651
 652         return 0;
 653 }
 654
 655 /**
 656  * Atomically writes the link status information into global
 657  * structure rte_eth_dev.
 658  *
 659  * @param dev
 660  *   - Pointer to the structure rte_eth_dev to read from.
 661  *   - Pointer to the buffer to be saved with the link status.
 662  *
 663  * @return
 664  *   - On success, zero.
 665  *   - On failure, negative value.
 666  */
 667 static inline int
 668 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 669                                 struct rte_eth_link *link)
 670 {
 671         struct rte_eth_link *dst = &(dev->data->dev_link);
 672         struct rte_eth_link *src = link;
 673
 674         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 675                                         *(uint64_t *)src) == 0)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 /*
 682  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 683  */
 684 static inline int
 685 ixgbe_is_sfp(struct ixgbe_hw *hw)
 686 {
 687         switch (hw->phy.type) {
 688         case ixgbe_phy_sfp_avago:
 689         case ixgbe_phy_sfp_ftl:
 690         case ixgbe_phy_sfp_intel:
 691         case ixgbe_phy_sfp_unknown:
 692         case ixgbe_phy_sfp_passive_tyco:
 693         case ixgbe_phy_sfp_passive_unknown:
 694                 return 1;
 695         default:
 696                 return 0;
 697         }
 698 }
 699
 700 static inline int32_t
 701 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 702 {
 703         uint32_t ctrl_ext;
 704         int32_t status;
 705
 706         status = ixgbe_reset_hw(hw);
 707
 708         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 709         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 710         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 711         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 712         IXGBE_WRITE_FLUSH(hw);
 713
 714         return status;
 715 }
 716
 717 static inline void
 718 ixgbe_enable_intr(struct rte_eth_dev *dev)
 719 {
 720         struct ixgbe_interrupt *intr =
 721                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 722         struct ixgbe_hw *hw =
 723                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 724
 725         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 726         IXGBE_WRITE_FLUSH(hw);
 727 }
 728
 729 /*
 730  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 731  */
 732 static void
 733 ixgbe_disable_intr(struct ixgbe_hw *hw)
 734 {
 735         PMD_INIT_FUNC_TRACE();
 736
 737         if (hw->mac.type == ixgbe_mac_82598EB) {
 738                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 739         } else {
 740                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 741                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 742                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 743         }
 744         IXGBE_WRITE_FLUSH(hw);
 745 }
 746
 747 /*
 748  * This function resets queue statistics mapping registers.
 749  * From Niantic datasheet, Initialization of Statistics section:
 750  * "...if software requires the queue counters, the RQSMR and TQSM registers
 751  * must be re-programmed following a device reset.
 752  */
 753 static void
 754 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 755 {
 756         uint32_t i;
 757
 758         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 759                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 760                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 761         }
 762 }
 763
 764
 765 static int
 766 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 767                                   uint16_t queue_id,
 768                                   uint8_t stat_idx,
 769                                   uint8_t is_rx)
 770 {
 771 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 772 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 773 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 774
 775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 776         struct ixgbe_stat_mapping_registers *stat_mappings =
 777                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 778         uint32_t qsmr_mask = 0;
 779         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 780         uint32_t q_map;
 781         uint8_t n, offset;
 782
 783         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 784                 (hw->mac.type != ixgbe_mac_X540) &&
 785                 (hw->mac.type != ixgbe_mac_X550) &&
 786                 (hw->mac.type != ixgbe_mac_X550EM_x))
 787                 return -ENOSYS;
 788
 789         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 790                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 791                      queue_id, stat_idx);
 792
 793         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 794         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 795                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 796                 return -EIO;
 797         }
 798         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 799
 800         /* Now clear any previous stat_idx set */
 801         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 802         if (!is_rx)
 803                 stat_mappings->tqsm[n] &= ~clearing_mask;
 804         else
 805                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 806
 807         q_map = (uint32_t)stat_idx;
 808         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 809         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 810         if (!is_rx)
 811                 stat_mappings->tqsm[n] |= qsmr_mask;
 812         else
 813                 stat_mappings->rqsmr[n] |= qsmr_mask;
 814
 815         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 816                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 817                      queue_id, stat_idx);
 818         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 819                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 820
 821         /* Now write the mapping in the appropriate register */
 822         if (is_rx) {
 823                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 824                              stat_mappings->rqsmr[n], n);
 825                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 826         }
 827         else {
 828                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 829                              stat_mappings->tqsm[n], n);
 830                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 831         }
 832         return 0;
 833 }
 834
 835 static void
 836 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 837 {
 838         struct ixgbe_stat_mapping_registers *stat_mappings =
 839                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 840         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 841         int i;
 842
 843         /* write whatever was in stat mapping table to the NIC */
 844         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 845                 /* rx */
 846                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 847
 848                 /* tx */
 849                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 850         }
 851 }
 852
 853 static void
 854 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 855 {
 856         uint8_t i;
 857         struct ixgbe_dcb_tc_config *tc;
 858         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 859
 860         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 861         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 862         for (i = 0; i < dcb_max_tc; i++) {
 863                 tc = &dcb_config->tc_config[i];
 864                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 865                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 866                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 867                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 868                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 869                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 870                 tc->pfc = ixgbe_dcb_pfc_disabled;
 871         }
 872
 873         /* Initialize default user to priority mapping, UPx->TC0 */
 874         tc = &dcb_config->tc_config[0];
 875         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 876         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 877         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 878                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 879                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 880         }
 881         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 882         dcb_config->pfc_mode_enable = false;
 883         dcb_config->vt_mode = true;
 884         dcb_config->round_robin_enable = false;
 885         /* support all DCB capabilities in 82599 */
 886         dcb_config->support.capabilities = 0xFF;
 887
 888         /*we only support 4 Tcs for X540, X550 */
 889         if (hw->mac.type == ixgbe_mac_X540 ||
 890                 hw->mac.type == ixgbe_mac_X550 ||
 891                 hw->mac.type == ixgbe_mac_X550EM_x) {
 892                 dcb_config->num_tcs.pg_tcs = 4;
 893                 dcb_config->num_tcs.pfc_tcs = 4;
 894         }
 895 }
 896
 897 /*
 898  * Ensure that all locks are released before first NVM or PHY access
 899  */
 900 static void
 901 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 902 {
 903         uint16_t mask;
 904
 905         /*
 906          * Phy lock should not fail in this early stage. If this is the case,
 907          * it is due to an improper exit of the application.
 908          * So force the release of the faulty lock. Release of common lock
 909          * is done automatically by swfw_sync function.
 910          */
 911         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 912         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 913                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 914         }
 915         ixgbe_release_swfw_semaphore(hw, mask);
 916
 917         /*
 918          * These ones are more tricky since they are common to all ports; but
 919          * swfw_sync retries last long enough (1s) to be almost sure that if
 920          * lock can not be taken it is due to an improper lock of the
 921          * semaphore.
 922          */
 923         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 924         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 925                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 926         }
 927         ixgbe_release_swfw_semaphore(hw, mask);
 928 }
 929
 930 /*
 931  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 932  * It returns 0 on success.
 933  */
 934 static int
 935 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 936 {
 937         struct rte_pci_device *pci_dev;
 938         struct ixgbe_hw *hw =
 939                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 940         struct ixgbe_vfta * shadow_vfta =
 941                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 942         struct ixgbe_hwstrip *hwstrip =
 943                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 944         struct ixgbe_dcb_config *dcb_config =
 945                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 946         struct ixgbe_filter_info *filter_info =
 947                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 948         uint32_t ctrl_ext;
 949         uint16_t csum;
 950         int diag, i;
 951
 952         PMD_INIT_FUNC_TRACE();
 953
 954         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 955         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 956         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 957
 958         /*
 959          * For secondary processes, we don't initialise any further as primary
 960          * has already done this work. Only check we don't need a different
 961          * RX and TX function.
 962          */
 963         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 964                 struct ixgbe_tx_queue *txq;
 965                 /* TX queue function in primary, set by last queue initialized
 966                  * Tx queue may not initialized by primary process */
 967                 if (eth_dev->data->tx_queues) {
 968                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 969                         ixgbe_set_tx_function(eth_dev, txq);
 970                 } else {
 971                         /* Use default TX function if we get here */
 972                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 973                                              "Using default TX function.");
 974                 }
 975
 976                 ixgbe_set_rx_function(eth_dev);
 977
 978                 return 0;
 979         }
 980         pci_dev = eth_dev->pci_dev;
 981
 982         rte_eth_copy_pci_info(eth_dev, pci_dev);
 983
 984         /* Vendor and Device ID need to be set before init of shared code */
 985         hw->device_id = pci_dev->id.device_id;
 986         hw->vendor_id = pci_dev->id.vendor_id;
 987         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 988         hw->allow_unsupported_sfp = 1;
 989
 990         /* Initialize the shared code (base driver) */
 991 #ifdef RTE_NIC_BYPASS
 992         diag = ixgbe_bypass_init_shared_code(hw);
 993 #else
 994         diag = ixgbe_init_shared_code(hw);
 995 #endif /* RTE_NIC_BYPASS */
 996
 997         if (diag != IXGBE_SUCCESS) {
 998                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 999                 return -EIO;
1000         }
1001
1002         /* pick up the PCI bus settings for reporting later */
1003         ixgbe_get_bus_info(hw);
1004
1005         /* Unlock any pending hardware semaphore */
1006         ixgbe_swfw_lock_reset(hw);
1007
1008         /* Initialize DCB configuration*/
1009         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1010         ixgbe_dcb_init(hw,dcb_config);
1011         /* Get Hardware Flow Control setting */
1012         hw->fc.requested_mode = ixgbe_fc_full;
1013         hw->fc.current_mode = ixgbe_fc_full;
1014         hw->fc.pause_time = IXGBE_FC_PAUSE;
1015         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1016                 hw->fc.low_water[i] = IXGBE_FC_LO;
1017                 hw->fc.high_water[i] = IXGBE_FC_HI;
1018         }
1019         hw->fc.send_xon = 1;
1020
1021         /* Make sure we have a good EEPROM before we read from it */
1022         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1023         if (diag != IXGBE_SUCCESS) {
1024                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1025                 return -EIO;
1026         }
1027
1028 #ifdef RTE_NIC_BYPASS
1029         diag = ixgbe_bypass_init_hw(hw);
1030 #else
1031         diag = ixgbe_init_hw(hw);
1032 #endif /* RTE_NIC_BYPASS */
1033
1034         /*
1035          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1036          * is called too soon after the kernel driver unbinding/binding occurs.
1037          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1038          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1039          * also called. See ixgbe_identify_phy_82599(). The reason for the
1040          * failure is not known, and only occuts when virtualisation features
1041          * are disabled in the bios. A delay of 100ms  was found to be enough by
1042          * trial-and-error, and is doubled to be safe.
1043          */
1044         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1045                 rte_delay_ms(200);
1046                 diag = ixgbe_init_hw(hw);
1047         }
1048
1049         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1050                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1051                     "LOM.  Please be aware there may be issues associated "
1052                     "with your hardware.");
1053                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1054                     "please contact your Intel or hardware representative "
1055                     "who provided you with this hardware.");
1056         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1057                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1058         if (diag) {
1059                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1060                 return -EIO;
1061         }
1062
1063         /* Reset the hw statistics */
1064         ixgbe_dev_stats_reset(eth_dev);
1065
1066         /* disable interrupt */
1067         ixgbe_disable_intr(hw);
1068
1069         /* reset mappings for queue statistics hw counters*/
1070         ixgbe_reset_qstat_mappings(hw);
1071
1072         /* Allocate memory for storing MAC addresses */
1073         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1074                         hw->mac.num_rar_entries, 0);
1075         if (eth_dev->data->mac_addrs == NULL) {
1076                 PMD_INIT_LOG(ERR,
1077                         "Failed to allocate %u bytes needed to store "
1078                         "MAC addresses",
1079                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1080                 return -ENOMEM;
1081         }
1082         /* Copy the permanent MAC address */
1083         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1084                         &eth_dev->data->mac_addrs[0]);
1085
1086         /* Allocate memory for storing hash filter MAC addresses */
1087         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1088                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1089         if (eth_dev->data->hash_mac_addrs == NULL) {
1090                 PMD_INIT_LOG(ERR,
1091                         "Failed to allocate %d bytes needed to store MAC addresses",
1092                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1093                 return -ENOMEM;
1094         }
1095
1096         /* initialize the vfta */
1097         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1098
1099         /* initialize the hw strip bitmap*/
1100         memset(hwstrip, 0, sizeof(*hwstrip));
1101
1102         /* initialize PF if max_vfs not zero */
1103         ixgbe_pf_host_init(eth_dev);
1104
1105         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1106         /* let hardware know driver is loaded */
1107         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1108         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1109         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1110         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1111         IXGBE_WRITE_FLUSH(hw);
1112
1113         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1114                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1115                              (int) hw->mac.type, (int) hw->phy.type,
1116                              (int) hw->phy.sfp_type);
1117         else
1118                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1119                              (int) hw->mac.type, (int) hw->phy.type);
1120
1121         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1122                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1123                         pci_dev->id.device_id);
1124
1125         rte_intr_callback_register(&pci_dev->intr_handle,
1126                                    ixgbe_dev_interrupt_handler,
1127                                    (void *)eth_dev);
1128
1129         /* enable uio/vfio intr/eventfd mapping */
1130         rte_intr_enable(&pci_dev->intr_handle);
1131
1132         /* enable support intr */
1133         ixgbe_enable_intr(eth_dev);
1134
1135         /* initialize 5tuple filter list */
1136         TAILQ_INIT(&filter_info->fivetuple_list);
1137         memset(filter_info->fivetuple_mask, 0,
1138                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1139
1140         return 0;
1141 }
1142
1143 static int
1144 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1145 {
1146         struct rte_pci_device *pci_dev;
1147         struct ixgbe_hw *hw;
1148
1149         PMD_INIT_FUNC_TRACE();
1150
1151         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1152                 return -EPERM;
1153
1154         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1155         pci_dev = eth_dev->pci_dev;
1156
1157         if (hw->adapter_stopped == 0)
1158                 ixgbe_dev_close(eth_dev);
1159
1160         eth_dev->dev_ops = NULL;
1161         eth_dev->rx_pkt_burst = NULL;
1162         eth_dev->tx_pkt_burst = NULL;
1163
1164         /* Unlock any pending hardware semaphore */
1165         ixgbe_swfw_lock_reset(hw);
1166
1167         /* disable uio intr before callback unregister */
1168         rte_intr_disable(&(pci_dev->intr_handle));
1169         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1170                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1171
1172         /* uninitialize PF if max_vfs not zero */
1173         ixgbe_pf_host_uninit(eth_dev);
1174
1175         rte_free(eth_dev->data->mac_addrs);
1176         eth_dev->data->mac_addrs = NULL;
1177
1178         rte_free(eth_dev->data->hash_mac_addrs);
1179         eth_dev->data->hash_mac_addrs = NULL;
1180
1181         return 0;
1182 }
1183
1184 /*
1185  * Negotiate mailbox API version with the PF.
1186  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1187  * Then we try to negotiate starting with the most recent one.
1188  * If all negotiation attempts fail, then we will proceed with
1189  * the default one (ixgbe_mbox_api_10).
1190  */
1191 static void
1192 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1193 {
1194         int32_t i;
1195
1196         /* start with highest supported, proceed down */
1197         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1198                 ixgbe_mbox_api_11,
1199                 ixgbe_mbox_api_10,
1200         };
1201
1202         for (i = 0;
1203                         i != RTE_DIM(sup_ver) &&
1204                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1205                         i++)
1206                 ;
1207 }
1208
1209 static void
1210 generate_random_mac_addr(struct ether_addr *mac_addr)
1211 {
1212         uint64_t random;
1213
1214         /* Set Organizationally Unique Identifier (OUI) prefix. */
1215         mac_addr->addr_bytes[0] = 0x00;
1216         mac_addr->addr_bytes[1] = 0x09;
1217         mac_addr->addr_bytes[2] = 0xC0;
1218         /* Force indication of locally assigned MAC address. */
1219         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1220         /* Generate the last 3 bytes of the MAC address with a random number. */
1221         random = rte_rand();
1222         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1223 }
1224
1225 /*
1226  * Virtual Function device init
1227  */
1228 static int
1229 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1230 {
1231         int diag;
1232         uint32_t tc, tcs;
1233         struct rte_pci_device *pci_dev;
1234         struct ixgbe_hw *hw =
1235                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1236         struct ixgbe_vfta * shadow_vfta =
1237                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1238         struct ixgbe_hwstrip *hwstrip =
1239                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1240         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1241
1242         PMD_INIT_FUNC_TRACE();
1243
1244         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1245         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1246         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1247
1248         /* for secondary processes, we don't initialise any further as primary
1249          * has already done this work. Only check we don't need a different
1250          * RX function */
1251         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1252                 if (eth_dev->data->scattered_rx)
1253                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1254                 return 0;
1255         }
1256
1257         pci_dev = eth_dev->pci_dev;
1258
1259         rte_eth_copy_pci_info(eth_dev, pci_dev);
1260
1261         hw->device_id = pci_dev->id.device_id;
1262         hw->vendor_id = pci_dev->id.vendor_id;
1263         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1264
1265         /* initialize the vfta */
1266         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1267
1268         /* initialize the hw strip bitmap*/
1269         memset(hwstrip, 0, sizeof(*hwstrip));
1270
1271         /* Initialize the shared code (base driver) */
1272         diag = ixgbe_init_shared_code(hw);
1273         if (diag != IXGBE_SUCCESS) {
1274                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1275                 return -EIO;
1276         }
1277
1278         /* init_mailbox_params */
1279         hw->mbx.ops.init_params(hw);
1280
1281         /* Reset the hw statistics */
1282         ixgbevf_dev_stats_reset(eth_dev);
1283
1284         /* Disable the interrupts for VF */
1285         ixgbevf_intr_disable(hw);
1286
1287         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1288         diag = hw->mac.ops.reset_hw(hw);
1289
1290         /*
1291          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1292          * the underlying PF driver has not assigned a MAC address to the VF.
1293          * In this case, assign a random MAC address.
1294          */
1295         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1296                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1297                 return (diag);
1298         }
1299
1300         /* negotiate mailbox API version to use with the PF. */
1301         ixgbevf_negotiate_api(hw);
1302
1303         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1304         ixgbevf_get_queues(hw, &tcs, &tc);
1305
1306         /* Allocate memory for storing MAC addresses */
1307         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1308                         hw->mac.num_rar_entries, 0);
1309         if (eth_dev->data->mac_addrs == NULL) {
1310                 PMD_INIT_LOG(ERR,
1311                         "Failed to allocate %u bytes needed to store "
1312                         "MAC addresses",
1313                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1314                 return -ENOMEM;
1315         }
1316
1317         /* Generate a random MAC address, if none was assigned by PF. */
1318         if (is_zero_ether_addr(perm_addr)) {
1319                 generate_random_mac_addr(perm_addr);
1320                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1321                 if (diag) {
1322                         rte_free(eth_dev->data->mac_addrs);
1323                         eth_dev->data->mac_addrs = NULL;
1324                         return diag;
1325                 }
1326                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1327                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1328                              "%02x:%02x:%02x:%02x:%02x:%02x",
1329                              perm_addr->addr_bytes[0],
1330                              perm_addr->addr_bytes[1],
1331                              perm_addr->addr_bytes[2],
1332                              perm_addr->addr_bytes[3],
1333                              perm_addr->addr_bytes[4],
1334                              perm_addr->addr_bytes[5]);
1335         }
1336
1337         /* Copy the permanent MAC address */
1338         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1339
1340         /* reset the hardware with the new settings */
1341         diag = hw->mac.ops.start_hw(hw);
1342         switch (diag) {
1343                 case  0:
1344                         break;
1345
1346                 default:
1347                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1348                         return (-EIO);
1349         }
1350
1351         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1352                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1353                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1354
1355         return 0;
1356 }
1357
1358 /* Virtual Function device uninit */
1359
1360 static int
1361 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1362 {
1363         struct ixgbe_hw *hw;
1364         unsigned i;
1365
1366         PMD_INIT_FUNC_TRACE();
1367
1368         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1369                 return -EPERM;
1370
1371         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1372
1373         if (hw->adapter_stopped == 0)
1374                 ixgbevf_dev_close(eth_dev);
1375
1376         eth_dev->dev_ops = NULL;
1377         eth_dev->rx_pkt_burst = NULL;
1378         eth_dev->tx_pkt_burst = NULL;
1379
1380         /* Disable the interrupts for VF */
1381         ixgbevf_intr_disable(hw);
1382
1383         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1384                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1385                 eth_dev->data->rx_queues[i] = NULL;
1386         }
1387         eth_dev->data->nb_rx_queues = 0;
1388
1389         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1390                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1391                 eth_dev->data->tx_queues[i] = NULL;
1392         }
1393         eth_dev->data->nb_tx_queues = 0;
1394
1395         rte_free(eth_dev->data->mac_addrs);
1396         eth_dev->data->mac_addrs = NULL;
1397
1398         return 0;
1399 }
1400
1401 static struct eth_driver rte_ixgbe_pmd = {
1402         .pci_drv = {
1403                 .name = "rte_ixgbe_pmd",
1404                 .id_table = pci_id_ixgbe_map,
1405                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1406                         RTE_PCI_DRV_DETACHABLE,
1407         },
1408         .eth_dev_init = eth_ixgbe_dev_init,
1409         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1410         .dev_private_size = sizeof(struct ixgbe_adapter),
1411 };
1412
1413 /*
1414  * virtual function driver struct
1415  */
1416 static struct eth_driver rte_ixgbevf_pmd = {
1417         .pci_drv = {
1418                 .name = "rte_ixgbevf_pmd",
1419                 .id_table = pci_id_ixgbevf_map,
1420                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1421         },
1422         .eth_dev_init = eth_ixgbevf_dev_init,
1423         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1424         .dev_private_size = sizeof(struct ixgbe_adapter),
1425 };
1426
1427 /*
1428  * Driver initialization routine.
1429  * Invoked once at EAL init time.
1430  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1431  */
1432 static int
1433 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1434 {
1435         PMD_INIT_FUNC_TRACE();
1436
1437         rte_eth_driver_register(&rte_ixgbe_pmd);
1438         return 0;
1439 }
1440
1441 /*
1442  * VF Driver initialization routine.
1443  * Invoked one at EAL init time.
1444  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1445  */
1446 static int
1447 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1448 {
1449         PMD_INIT_FUNC_TRACE();
1450
1451         rte_eth_driver_register(&rte_ixgbevf_pmd);
1452         return (0);
1453 }
1454
1455 static int
1456 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1457 {
1458         struct ixgbe_hw *hw =
1459                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1460         struct ixgbe_vfta * shadow_vfta =
1461                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1462         uint32_t vfta;
1463         uint32_t vid_idx;
1464         uint32_t vid_bit;
1465
1466         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1467         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1468         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1469         if (on)
1470                 vfta |= vid_bit;
1471         else
1472                 vfta &= ~vid_bit;
1473         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1474
1475         /* update local VFTA copy */
1476         shadow_vfta->vfta[vid_idx] = vfta;
1477
1478         return 0;
1479 }
1480
1481 static void
1482 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1483 {
1484         if (on)
1485                 ixgbe_vlan_hw_strip_enable(dev, queue);
1486         else
1487                 ixgbe_vlan_hw_strip_disable(dev, queue);
1488 }
1489
1490 static void
1491 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1492 {
1493         struct ixgbe_hw *hw =
1494                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1495
1496         /* Only the high 16-bits is valid */
1497         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1498 }
1499
1500 void
1501 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1502 {
1503         struct ixgbe_hw *hw =
1504                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1505         uint32_t vlnctrl;
1506
1507         PMD_INIT_FUNC_TRACE();
1508
1509         /* Filter Table Disable */
1510         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1511         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1512
1513         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1514 }
1515
1516 void
1517 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1518 {
1519         struct ixgbe_hw *hw =
1520                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521         struct ixgbe_vfta * shadow_vfta =
1522                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1523         uint32_t vlnctrl;
1524         uint16_t i;
1525
1526         PMD_INIT_FUNC_TRACE();
1527
1528         /* Filter Table Enable */
1529         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1530         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1531         vlnctrl |= IXGBE_VLNCTRL_VFE;
1532
1533         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1534
1535         /* write whatever is in local vfta copy */
1536         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1537                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1538 }
1539
1540 static void
1541 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1542 {
1543         struct ixgbe_hwstrip *hwstrip =
1544                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1545
1546         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1547                 return;
1548
1549         if (on)
1550                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1551         else
1552                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1553 }
1554
1555 static void
1556 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1557 {
1558         struct ixgbe_hw *hw =
1559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         uint32_t ctrl;
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         if (hw->mac.type == ixgbe_mac_82598EB) {
1565                 /* No queue level support */
1566                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1567                 return;
1568         }
1569         else {
1570                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1571                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1572                 ctrl &= ~IXGBE_RXDCTL_VME;
1573                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1574         }
1575         /* record those setting for HW strip per queue */
1576         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1577 }
1578
1579 static void
1580 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1581 {
1582         struct ixgbe_hw *hw =
1583                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584         uint32_t ctrl;
1585
1586         PMD_INIT_FUNC_TRACE();
1587
1588         if (hw->mac.type == ixgbe_mac_82598EB) {
1589                 /* No queue level supported */
1590                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1591                 return;
1592         }
1593         else {
1594                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1595                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1596                 ctrl |= IXGBE_RXDCTL_VME;
1597                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1598         }
1599         /* record those setting for HW strip per queue */
1600         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1601 }
1602
1603 void
1604 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1605 {
1606         struct ixgbe_hw *hw =
1607                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1608         uint32_t ctrl;
1609         uint16_t i;
1610
1611         PMD_INIT_FUNC_TRACE();
1612
1613         if (hw->mac.type == ixgbe_mac_82598EB) {
1614                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1615                 ctrl &= ~IXGBE_VLNCTRL_VME;
1616                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1617         }
1618         else {
1619                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1620                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1621                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1622                         ctrl &= ~IXGBE_RXDCTL_VME;
1623                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1624
1625                         /* record those setting for HW strip per queue */
1626                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1627                 }
1628         }
1629 }
1630
1631 void
1632 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1633 {
1634         struct ixgbe_hw *hw =
1635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636         uint32_t ctrl;
1637         uint16_t i;
1638
1639         PMD_INIT_FUNC_TRACE();
1640
1641         if (hw->mac.type == ixgbe_mac_82598EB) {
1642                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1643                 ctrl |= IXGBE_VLNCTRL_VME;
1644                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1645         }
1646         else {
1647                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1648                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1649                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1650                         ctrl |= IXGBE_RXDCTL_VME;
1651                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1652
1653                         /* record those setting for HW strip per queue */
1654                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1655                 }
1656         }
1657 }
1658
1659 static void
1660 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1661 {
1662         struct ixgbe_hw *hw =
1663                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664         uint32_t ctrl;
1665
1666         PMD_INIT_FUNC_TRACE();
1667
1668         /* DMATXCTRL: Geric Double VLAN Disable */
1669         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1670         ctrl &= ~IXGBE_DMATXCTL_GDV;
1671         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1672
1673         /* CTRL_EXT: Global Double VLAN Disable */
1674         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1675         ctrl &= ~IXGBE_EXTENDED_VLAN;
1676         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1677
1678 }
1679
1680 static void
1681 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1682 {
1683         struct ixgbe_hw *hw =
1684                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685         uint32_t ctrl;
1686
1687         PMD_INIT_FUNC_TRACE();
1688
1689         /* DMATXCTRL: Geric Double VLAN Enable */
1690         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1691         ctrl |= IXGBE_DMATXCTL_GDV;
1692         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1693
1694         /* CTRL_EXT: Global Double VLAN Enable */
1695         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1696         ctrl |= IXGBE_EXTENDED_VLAN;
1697         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1698
1699         /*
1700          * VET EXT field in the EXVET register = 0x8100 by default
1701          * So no need to change. Same to VT field of DMATXCTL register
1702          */
1703 }
1704
1705 static void
1706 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1707 {
1708         if(mask & ETH_VLAN_STRIP_MASK){
1709                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1710                         ixgbe_vlan_hw_strip_enable_all(dev);
1711                 else
1712                         ixgbe_vlan_hw_strip_disable_all(dev);
1713         }
1714
1715         if(mask & ETH_VLAN_FILTER_MASK){
1716                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1717                         ixgbe_vlan_hw_filter_enable(dev);
1718                 else
1719                         ixgbe_vlan_hw_filter_disable(dev);
1720         }
1721
1722         if(mask & ETH_VLAN_EXTEND_MASK){
1723                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1724                         ixgbe_vlan_hw_extend_enable(dev);
1725                 else
1726                         ixgbe_vlan_hw_extend_disable(dev);
1727         }
1728 }
1729
1730 static void
1731 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1732 {
1733         struct ixgbe_hw *hw =
1734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1735         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1736         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1737         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1738         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1739 }
1740
1741 static int
1742 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1743 {
1744         switch (nb_rx_q) {
1745         case 1:
1746         case 2:
1747                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1748                 break;
1749         case 4:
1750                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1751                 break;
1752         default:
1753                 return -EINVAL;
1754         }
1755
1756         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1757         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1758
1759         return 0;
1760 }
1761
1762 static int
1763 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1764 {
1765         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1766         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1767         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1768
1769         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1770                 /* check multi-queue mode */
1771                 switch (dev_conf->rxmode.mq_mode) {
1772                 case ETH_MQ_RX_VMDQ_DCB:
1773                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1774                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1775                         PMD_INIT_LOG(ERR, "SRIOV active,"
1776                                         " unsupported mq_mode rx %d.",
1777                                         dev_conf->rxmode.mq_mode);
1778                         return -EINVAL;
1779                 case ETH_MQ_RX_RSS:
1780                 case ETH_MQ_RX_VMDQ_RSS:
1781                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1782                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1783                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1784                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1785                                                 " invalid queue number"
1786                                                 " for VMDQ RSS, allowed"
1787                                                 " value are 1, 2 or 4.");
1788                                         return -EINVAL;
1789                                 }
1790                         break;
1791                 case ETH_MQ_RX_VMDQ_ONLY:
1792                 case ETH_MQ_RX_NONE:
1793                         /* if nothing mq mode configure, use default scheme */
1794                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1795                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1796                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1797                         break;
1798                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1799                         /* SRIOV only works in VMDq enable mode */
1800                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1801                                         " wrong mq_mode rx %d.",
1802                                         dev_conf->rxmode.mq_mode);
1803                         return -EINVAL;
1804                 }
1805
1806                 switch (dev_conf->txmode.mq_mode) {
1807                 case ETH_MQ_TX_VMDQ_DCB:
1808                         /* DCB VMDQ in SRIOV mode, not implement yet */
1809                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1810                                         " unsupported VMDQ mq_mode tx %d.",
1811                                         dev_conf->txmode.mq_mode);
1812                         return -EINVAL;
1813                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1814                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1815                         break;
1816                 }
1817
1818                 /* check valid queue number */
1819                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1820                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1821                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1822                                         " queue number must less equal to %d.",
1823                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1824                         return -EINVAL;
1825                 }
1826         } else {
1827                 /* check configuration for vmdb+dcb mode */
1828                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1829                         const struct rte_eth_vmdq_dcb_conf *conf;
1830
1831                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1832                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1833                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1834                                 return -EINVAL;
1835                         }
1836                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1837                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1838                                conf->nb_queue_pools == ETH_32_POOLS)) {
1839                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1840                                                 " nb_queue_pools must be %d or %d.",
1841                                                 ETH_16_POOLS, ETH_32_POOLS);
1842                                 return -EINVAL;
1843                         }
1844                 }
1845                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1846                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1847
1848                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1849                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1850                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1851                                 return -EINVAL;
1852                         }
1853                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1854                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1855                                conf->nb_queue_pools == ETH_32_POOLS)) {
1856                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1857                                                 " nb_queue_pools != %d and"
1858                                                 " nb_queue_pools != %d.",
1859                                                 ETH_16_POOLS, ETH_32_POOLS);
1860                                 return -EINVAL;
1861                         }
1862                 }
1863
1864                 /* For DCB mode check our configuration before we go further */
1865                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1866                         const struct rte_eth_dcb_rx_conf *conf;
1867
1868                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1869                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1870                                                  IXGBE_DCB_NB_QUEUES);
1871                                 return -EINVAL;
1872                         }
1873                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1874                         if (!(conf->nb_tcs == ETH_4_TCS ||
1875                                conf->nb_tcs == ETH_8_TCS)) {
1876                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1877                                                 " and nb_tcs != %d.",
1878                                                 ETH_4_TCS, ETH_8_TCS);
1879                                 return -EINVAL;
1880                         }
1881                 }
1882
1883                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1884                         const struct rte_eth_dcb_tx_conf *conf;
1885
1886                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1887                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1888                                                  IXGBE_DCB_NB_QUEUES);
1889                                 return -EINVAL;
1890                         }
1891                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1892                         if (!(conf->nb_tcs == ETH_4_TCS ||
1893                                conf->nb_tcs == ETH_8_TCS)) {
1894                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1895                                                 " and nb_tcs != %d.",
1896                                                 ETH_4_TCS, ETH_8_TCS);
1897                                 return -EINVAL;
1898                         }
1899                 }
1900         }
1901         return 0;
1902 }
1903
1904 static int
1905 ixgbe_dev_configure(struct rte_eth_dev *dev)
1906 {
1907         struct ixgbe_interrupt *intr =
1908                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1909         struct ixgbe_adapter *adapter =
1910                 (struct ixgbe_adapter *)dev->data->dev_private;
1911         int ret;
1912
1913         PMD_INIT_FUNC_TRACE();
1914         /* multipe queue mode checking */
1915         ret  = ixgbe_check_mq_mode(dev);
1916         if (ret != 0) {
1917                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1918                             ret);
1919                 return ret;
1920         }
1921
1922         /* set flag to update link status after init */
1923         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1924
1925         /*
1926          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1927          * allocation or vector Rx preconditions we will reset it.
1928          */
1929         adapter->rx_bulk_alloc_allowed = true;
1930         adapter->rx_vec_allowed = true;
1931
1932         return 0;
1933 }
1934
1935 /*
1936  * Configure device link speed and setup link.
1937  * It returns 0 on success.
1938  */
1939 static int
1940 ixgbe_dev_start(struct rte_eth_dev *dev)
1941 {
1942         struct ixgbe_hw *hw =
1943                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944         struct ixgbe_vf_info *vfinfo =
1945                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1946         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1947         uint32_t intr_vector = 0;
1948         int err, link_up = 0, negotiate = 0;
1949         uint32_t speed = 0;
1950         int mask = 0;
1951         int status;
1952         uint16_t vf, idx;
1953
1954         PMD_INIT_FUNC_TRACE();
1955
1956         /* IXGBE devices don't support half duplex */
1957         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1958                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1959                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1960                              dev->data->dev_conf.link_duplex,
1961                              dev->data->port_id);
1962                 return -EINVAL;
1963         }
1964
1965         /* stop adapter */
1966         hw->adapter_stopped = 0;
1967         ixgbe_stop_adapter(hw);
1968
1969         /* reinitialize adapter
1970          * this calls reset and start */
1971         status = ixgbe_pf_reset_hw(hw);
1972         if (status != 0)
1973                 return -1;
1974         hw->mac.ops.start_hw(hw);
1975         hw->mac.get_link_status = true;
1976
1977         /* configure PF module if SRIOV enabled */
1978         ixgbe_pf_host_configure(dev);
1979
1980         /* check and configure queue intr-vector mapping */
1981         if ((rte_intr_cap_multiple(intr_handle) ||
1982              !RTE_ETH_DEV_SRIOV(dev).active) &&
1983             dev->data->dev_conf.intr_conf.rxq != 0) {
1984                 intr_vector = dev->data->nb_rx_queues;
1985                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1986                         return -1;
1987         }
1988
1989         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1990                 intr_handle->intr_vec =
1991                         rte_zmalloc("intr_vec",
1992                                     dev->data->nb_rx_queues * sizeof(int), 0);
1993                 if (intr_handle->intr_vec == NULL) {
1994                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1995                                      " intr_vec\n", dev->data->nb_rx_queues);
1996                         return -ENOMEM;
1997                 }
1998         }
1999
2000         /* confiugre msix for sleep until rx interrupt */
2001         ixgbe_configure_msix(dev);
2002
2003         /* initialize transmission unit */
2004         ixgbe_dev_tx_init(dev);
2005
2006         /* This can fail when allocating mbufs for descriptor rings */
2007         err = ixgbe_dev_rx_init(dev);
2008         if (err) {
2009                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2010                 goto error;
2011         }
2012
2013         err = ixgbe_dev_rxtx_start(dev);
2014         if (err < 0) {
2015                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2016                 goto error;
2017         }
2018
2019         /* Skip link setup if loopback mode is enabled for 82599. */
2020         if (hw->mac.type == ixgbe_mac_82599EB &&
2021                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2022                 goto skip_link_setup;
2023
2024         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2025                 err = hw->mac.ops.setup_sfp(hw);
2026                 if (err)
2027                         goto error;
2028         }
2029
2030         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2031                 /* Turn on the copper */
2032                 ixgbe_set_phy_power(hw, true);
2033         } else {
2034                 /* Turn on the laser */
2035                 ixgbe_enable_tx_laser(hw);
2036         }
2037
2038         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2039         if (err)
2040                 goto error;
2041         dev->data->dev_link.link_status = link_up;
2042
2043         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2044         if (err)
2045                 goto error;
2046
2047         switch(dev->data->dev_conf.link_speed) {
2048         case ETH_LINK_SPEED_AUTONEG:
2049                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2050                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2051                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2052                 break;
2053         case ETH_LINK_SPEED_100:
2054                 /*
2055                  * Invalid for 82598 but error will be detected by
2056                  * ixgbe_setup_link()
2057                  */
2058                 speed = IXGBE_LINK_SPEED_100_FULL;
2059                 break;
2060         case ETH_LINK_SPEED_1000:
2061                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2062                 break;
2063         case ETH_LINK_SPEED_10000:
2064                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2065                 break;
2066         default:
2067                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2068                              dev->data->dev_conf.link_speed,
2069                              dev->data->port_id);
2070                 goto error;
2071         }
2072
2073         err = ixgbe_setup_link(hw, speed, link_up);
2074         if (err)
2075                 goto error;
2076
2077 skip_link_setup:
2078
2079         if (rte_intr_allow_others(intr_handle)) {
2080                 /* check if lsc interrupt is enabled */
2081                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2082                         ixgbe_dev_lsc_interrupt_setup(dev);
2083         } else {
2084                 rte_intr_callback_unregister(intr_handle,
2085                                              ixgbe_dev_interrupt_handler,
2086                                              (void *)dev);
2087                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2088                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2089                                      " no intr multiplex\n");
2090         }
2091
2092         /* check if rxq interrupt is enabled */
2093         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2094             rte_intr_dp_is_en(intr_handle))
2095                 ixgbe_dev_rxq_interrupt_setup(dev);
2096
2097         /* enable uio/vfio intr/eventfd mapping */
2098         rte_intr_enable(intr_handle);
2099
2100         /* resume enabled intr since hw reset */
2101         ixgbe_enable_intr(dev);
2102
2103         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2104                 ETH_VLAN_EXTEND_MASK;
2105         ixgbe_vlan_offload_set(dev, mask);
2106
2107         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2108                 /* Enable vlan filtering for VMDq */
2109                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2110         }
2111
2112         /* Configure DCB hw */
2113         ixgbe_configure_dcb(dev);
2114
2115         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2116                 err = ixgbe_fdir_configure(dev);
2117                 if (err)
2118                         goto error;
2119         }
2120
2121         /* Restore vf rate limit */
2122         if (vfinfo != NULL) {
2123                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2124                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2125                                 if (vfinfo[vf].tx_rate[idx] != 0)
2126                                         ixgbe_set_vf_rate_limit(dev, vf,
2127                                                 vfinfo[vf].tx_rate[idx],
2128                                                 1 << idx);
2129         }
2130
2131         ixgbe_restore_statistics_mapping(dev);
2132
2133         return (0);
2134
2135 error:
2136         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2137         ixgbe_dev_clear_queues(dev);
2138         return -EIO;
2139 }
2140
2141 /*
2142  * Stop device: disable rx and tx functions to allow for reconfiguring.
2143  */
2144 static void
2145 ixgbe_dev_stop(struct rte_eth_dev *dev)
2146 {
2147         struct rte_eth_link link;
2148         struct ixgbe_hw *hw =
2149                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2150         struct ixgbe_vf_info *vfinfo =
2151                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2152         struct ixgbe_filter_info *filter_info =
2153                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2154         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2155         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2156         int vf;
2157
2158         PMD_INIT_FUNC_TRACE();
2159
2160         /* disable interrupts */
2161         ixgbe_disable_intr(hw);
2162
2163         /* disable intr eventfd mapping */
2164         rte_intr_disable(intr_handle);
2165
2166         /* reset the NIC */
2167         ixgbe_pf_reset_hw(hw);
2168         hw->adapter_stopped = 0;
2169
2170         /* stop adapter */
2171         ixgbe_stop_adapter(hw);
2172
2173         for (vf = 0; vfinfo != NULL &&
2174                      vf < dev->pci_dev->max_vfs; vf++)
2175                 vfinfo[vf].clear_to_send = false;
2176
2177         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2178                 /* Turn off the copper */
2179                 ixgbe_set_phy_power(hw, false);
2180         } else {
2181                 /* Turn off the laser */
2182                 ixgbe_disable_tx_laser(hw);
2183         }
2184
2185         ixgbe_dev_clear_queues(dev);
2186
2187         /* Clear stored conf */
2188         dev->data->scattered_rx = 0;
2189         dev->data->lro = 0;
2190
2191         /* Clear recorded link status */
2192         memset(&link, 0, sizeof(link));
2193         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2194
2195         /* Remove all ntuple filters of the device */
2196         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2197              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2198                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2199                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2200                              p_5tuple, entries);
2201                 rte_free(p_5tuple);
2202         }
2203         memset(filter_info->fivetuple_mask, 0,
2204                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2205
2206         if (!rte_intr_allow_others(intr_handle))
2207                 /* resume to the default handler */
2208                 rte_intr_callback_register(intr_handle,
2209                                            ixgbe_dev_interrupt_handler,
2210                                            (void *)dev);
2211
2212         /* Clean datapath event and queue/vec mapping */
2213         rte_intr_efd_disable(intr_handle);
2214         if (intr_handle->intr_vec != NULL) {
2215                 rte_free(intr_handle->intr_vec);
2216                 intr_handle->intr_vec = NULL;
2217         }
2218 }
2219
2220 /*
2221  * Set device link up: enable tx.
2222  */
2223 static int
2224 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2225 {
2226         struct ixgbe_hw *hw =
2227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228         if (hw->mac.type == ixgbe_mac_82599EB) {
2229 #ifdef RTE_NIC_BYPASS
2230                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2231                         /* Not suported in bypass mode */
2232                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2233                                      "by device id 0x%x", hw->device_id);
2234                         return -ENOTSUP;
2235                 }
2236 #endif
2237         }
2238
2239         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2240                 /* Turn on the copper */
2241                 ixgbe_set_phy_power(hw, true);
2242         } else {
2243                 /* Turn on the laser */
2244                 ixgbe_enable_tx_laser(hw);
2245         }
2246
2247         return 0;
2248 }
2249
2250 /*
2251  * Set device link down: disable tx.
2252  */
2253 static int
2254 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2255 {
2256         struct ixgbe_hw *hw =
2257                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258         if (hw->mac.type == ixgbe_mac_82599EB) {
2259 #ifdef RTE_NIC_BYPASS
2260                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2261                         /* Not suported in bypass mode */
2262                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2263                                      "by device id 0x%x", hw->device_id);
2264                         return -ENOTSUP;
2265                 }
2266 #endif
2267         }
2268
2269         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2270                 /* Turn off the copper */
2271                 ixgbe_set_phy_power(hw, false);
2272         } else {
2273                 /* Turn off the laser */
2274                 ixgbe_disable_tx_laser(hw);
2275         }
2276
2277         return 0;
2278 }
2279
2280 /*
2281  * Reest and stop device.
2282  */
2283 static void
2284 ixgbe_dev_close(struct rte_eth_dev *dev)
2285 {
2286         struct ixgbe_hw *hw =
2287                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2288
2289         PMD_INIT_FUNC_TRACE();
2290
2291         ixgbe_pf_reset_hw(hw);
2292
2293         ixgbe_dev_stop(dev);
2294         hw->adapter_stopped = 1;
2295
2296         ixgbe_dev_free_queues(dev);
2297
2298         ixgbe_disable_pcie_master(hw);
2299
2300         /* reprogram the RAR[0] in case user changed it. */
2301         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2302 }
2303
2304 static void
2305 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2306                                                    *hw_stats, uint64_t *total_missed_rx,
2307                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2308                                                    uint64_t *total_qprdc)
2309 {
2310         uint32_t bprc, lxon, lxoff, total;
2311         unsigned i;
2312
2313         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2314         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2315         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2316         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2317
2318         for (i = 0; i < 8; i++) {
2319                 uint32_t mp;
2320                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2321                 /* global total per queue */
2322                 hw_stats->mpc[i] += mp;
2323                 /* Running comprehensive total for stats display */
2324                 *total_missed_rx += hw_stats->mpc[i];
2325                 if (hw->mac.type == ixgbe_mac_82598EB) {
2326                         hw_stats->rnbc[i] +=
2327                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2328                         hw_stats->pxonrxc[i] +=
2329                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2330                         hw_stats->pxoffrxc[i] +=
2331                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2332                 } else {
2333                         hw_stats->pxonrxc[i] +=
2334                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2335                         hw_stats->pxoffrxc[i] +=
2336                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2337                         hw_stats->pxon2offc[i] +=
2338                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2339                 }
2340                 hw_stats->pxontxc[i] +=
2341                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2342                 hw_stats->pxofftxc[i] +=
2343                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2344         }
2345         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2346                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2347                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2348                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2349                 hw_stats->qbrc[i] +=
2350                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2351                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2352                 hw_stats->qbtc[i] +=
2353                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2354                 *total_qprdc += hw_stats->qprdc[i] +=
2355                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2356
2357                 *total_qprc += hw_stats->qprc[i];
2358                 *total_qbrc += hw_stats->qbrc[i];
2359         }
2360         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2361         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2362         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2363
2364         /* Note that gprc counts missed packets */
2365         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2366
2367         if (hw->mac.type != ixgbe_mac_82598EB) {
2368                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2369                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2370                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2371                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2372                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2373                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2374                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2375                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2376         } else {
2377                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2378                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2379                 /* 82598 only has a counter in the high register */
2380                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2381                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2382                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2383         }
2384
2385         /*
2386          * Workaround: mprc hardware is incorrectly counting
2387          * broadcasts, so for now we subtract those.
2388          */
2389         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2390         hw_stats->bprc += bprc;
2391         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2392         if (hw->mac.type == ixgbe_mac_82598EB)
2393                 hw_stats->mprc -= bprc;
2394
2395         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2396         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2397         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2398         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2399         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2400         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2401
2402         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2403         hw_stats->lxontxc += lxon;
2404         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2405         hw_stats->lxofftxc += lxoff;
2406         total = lxon + lxoff;
2407
2408         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2409         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2410         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2411         hw_stats->gptc -= total;
2412         hw_stats->mptc -= total;
2413         hw_stats->ptc64 -= total;
2414         hw_stats->gotc -= total * ETHER_MIN_LEN;
2415
2416         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2417         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2418         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2419         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2420         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2421         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2422         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2423         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2424         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2425         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2426         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2427         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2428         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2429         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2430         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2431         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2432         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2433         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2434         /* Only read FCOE on 82599 */
2435         if (hw->mac.type != ixgbe_mac_82598EB) {
2436                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2437                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2438                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2439                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2440                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2441         }
2442
2443         /* Flow Director Stats registers */
2444         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2445         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2446 }
2447
2448 /*
2449  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2450  */
2451 static void
2452 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2453 {
2454         struct ixgbe_hw *hw =
2455                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2456         struct ixgbe_hw_stats *hw_stats =
2457                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2458         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2459         unsigned i;
2460
2461         total_missed_rx = 0;
2462         total_qbrc = 0;
2463         total_qprc = 0;
2464         total_qprdc = 0;
2465
2466         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2467                         &total_qprc, &total_qprdc);
2468
2469         if (stats == NULL)
2470                 return;
2471
2472         /* Fill out the rte_eth_stats statistics structure */
2473         stats->ipackets = total_qprc;
2474         stats->ibytes = total_qbrc;
2475         stats->opackets = hw_stats->gptc;
2476         stats->obytes = hw_stats->gotc;
2477
2478         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2479                 stats->q_ipackets[i] = hw_stats->qprc[i];
2480                 stats->q_opackets[i] = hw_stats->qptc[i];
2481                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2482                 stats->q_obytes[i] = hw_stats->qbtc[i];
2483                 stats->q_errors[i] = hw_stats->qprdc[i];
2484         }
2485
2486         /* Rx Errors */
2487         stats->ierrors  = hw_stats->crcerrs +
2488                           hw_stats->mspdc +
2489                           hw_stats->rlec +
2490                           hw_stats->ruc +
2491                           hw_stats->roc +
2492                           total_missed_rx +
2493                           hw_stats->illerrc +
2494                           hw_stats->errbc +
2495                           hw_stats->xec +
2496                           hw_stats->rfc +
2497                           hw_stats->fccrc +
2498                           hw_stats->fclast;
2499
2500         /* Tx Errors */
2501         stats->oerrors  = 0;
2502 }
2503
2504 static void
2505 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2506 {
2507         struct ixgbe_hw_stats *stats =
2508                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2509
2510         /* HW registers are cleared on read */
2511         ixgbe_dev_stats_get(dev, NULL);
2512
2513         /* Reset software totals */
2514         memset(stats, 0, sizeof(*stats));
2515 }
2516
2517 static int
2518 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2519                                          unsigned n)
2520 {
2521         struct ixgbe_hw *hw =
2522                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2523         struct ixgbe_hw_stats *hw_stats =
2524                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2525         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2526         unsigned i, count = IXGBE_NB_XSTATS;
2527
2528         if (n < count)
2529                 return count;
2530
2531         total_missed_rx = 0;
2532         total_qbrc = 0;
2533         total_qprc = 0;
2534         total_qprdc = 0;
2535
2536         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2537                                    &total_qprc, &total_qprdc);
2538
2539         /* If this is a reset xstats is NULL, and we have cleared the
2540          * registers by reading them.
2541          */
2542         if (!xstats)
2543                 return 0;
2544
2545         /* Extended stats from ixgbe_hw_stats */
2546         count = 0;
2547         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2548                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2549                          rte_ixgbe_stats_strings[i].name);
2550                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2551                                 rte_ixgbe_stats_strings[i].offset);
2552                 count++;
2553         }
2554
2555         /* Per-Q stats, with 8 queues available */
2556         for (i = 0; i < 8; i++) {
2557                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2558                          "rx_q%u_mbuf_allocation_errors", i);
2559                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2560                                 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2561                 count++;
2562
2563                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2564                          "rx_q%u_missed_packets", i);
2565                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2566                                 offsetof(struct ixgbe_hw_stats, mpc[i]));
2567                 count++;
2568
2569                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2570                          "rx_q%u_xon_priority_packets", i);
2571                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2572                                 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2573                 count++;
2574
2575                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2576                          "tx_q%u_xon_priority_packets", i);
2577                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2578                                 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2579                 count++;
2580
2581                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2582                          "rx_q%u_xoff_priority_packets", i);
2583                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2584                                 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2585                 count++;
2586
2587                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2588                          "tx_q%u_xoff_priority_packets", i);
2589                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2590                                 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2591                 count++;
2592
2593                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2594                          "xx_q%u_xon_to_xoff_priority_packets", i);
2595                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2596                                 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2597                 count++;
2598         }
2599
2600         for (i = 0; i < 16; i++) {
2601                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2602                          "rx_q%u_packets", i);
2603                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2604                                 offsetof(struct ixgbe_hw_stats, qprc[i]));
2605                 count++;
2606
2607                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2608                          "rx_q%u_bytes", i);
2609                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2610                                 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2611                 count++;
2612
2613                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2614                          "tx_q%u_packets", i);
2615                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2616                                 offsetof(struct ixgbe_hw_stats, qptc[i]));
2617                 count++;
2618
2619                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2620                          "tx_q%u_bytes", i);
2621                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2622                                 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2623                 count++;
2624
2625                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2626                          "rx_q%u_dropped", i);
2627                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2628                                 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2629                 count++;
2630         }
2631
2632         return count;
2633 }
2634
2635 static void
2636 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2637 {
2638         struct ixgbe_hw_stats *stats =
2639                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2640
2641         /* HW registers are cleared on read */
2642         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2643
2644         /* Reset software totals */
2645         memset(stats, 0, sizeof(*stats));
2646 }
2647
2648 static void
2649 ixgbevf_update_stats(struct rte_eth_dev *dev)
2650 {
2651         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2652         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2653                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2654
2655         /* Good Rx packet, include VF loopback */
2656         UPDATE_VF_STAT(IXGBE_VFGPRC,
2657             hw_stats->last_vfgprc, hw_stats->vfgprc);
2658
2659         /* Good Rx octets, include VF loopback */
2660         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2661             hw_stats->last_vfgorc, hw_stats->vfgorc);
2662
2663         /* Good Tx packet, include VF loopback */
2664         UPDATE_VF_STAT(IXGBE_VFGPTC,
2665             hw_stats->last_vfgptc, hw_stats->vfgptc);
2666
2667         /* Good Tx octets, include VF loopback */
2668         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2669             hw_stats->last_vfgotc, hw_stats->vfgotc);
2670
2671         /* Rx Multicst Packet */
2672         UPDATE_VF_STAT(IXGBE_VFMPRC,
2673             hw_stats->last_vfmprc, hw_stats->vfmprc);
2674 }
2675
2676 static int
2677 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2678                        unsigned n)
2679 {
2680         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2681                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2682         unsigned i;
2683
2684         if (n < IXGBEVF_NB_XSTATS)
2685                 return IXGBEVF_NB_XSTATS;
2686
2687         ixgbevf_update_stats(dev);
2688
2689         if (!xstats)
2690                 return 0;
2691
2692         /* Extended stats */
2693         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2694                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2695                          "%s", rte_ixgbevf_stats_strings[i].name);
2696                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2697                         rte_ixgbevf_stats_strings[i].offset);
2698         }
2699
2700         return IXGBEVF_NB_XSTATS;
2701 }
2702
2703 static void
2704 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2705 {
2706         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2707                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2708
2709         ixgbevf_update_stats(dev);
2710
2711         if (stats == NULL)
2712                 return;
2713
2714         stats->ipackets = hw_stats->vfgprc;
2715         stats->ibytes = hw_stats->vfgorc;
2716         stats->opackets = hw_stats->vfgptc;
2717         stats->obytes = hw_stats->vfgotc;
2718         stats->imcasts = hw_stats->vfmprc;
2719         /* stats->imcasts should be removed as imcasts is deprecated */
2720 }
2721
2722 static void
2723 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2724 {
2725         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2726                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2727
2728         /* Sync HW register to the last stats */
2729         ixgbevf_dev_stats_get(dev, NULL);
2730
2731         /* reset HW current stats*/
2732         hw_stats->vfgprc = 0;
2733         hw_stats->vfgorc = 0;
2734         hw_stats->vfgptc = 0;
2735         hw_stats->vfgotc = 0;
2736         hw_stats->vfmprc = 0;
2737
2738 }
2739
2740 static void
2741 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2742 {
2743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2744
2745         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2746         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2747         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2748         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2749         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2750         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2751         dev_info->max_vfs = dev->pci_dev->max_vfs;
2752         if (hw->mac.type == ixgbe_mac_82598EB)
2753                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2754         else
2755                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2756         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2757         dev_info->rx_offload_capa =
2758                 DEV_RX_OFFLOAD_VLAN_STRIP |
2759                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2760                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2761                 DEV_RX_OFFLOAD_TCP_CKSUM;
2762
2763         /*
2764          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2765          * mode.
2766          */
2767         if ((hw->mac.type == ixgbe_mac_82599EB ||
2768              hw->mac.type == ixgbe_mac_X540) &&
2769             !RTE_ETH_DEV_SRIOV(dev).active)
2770                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2771
2772         dev_info->tx_offload_capa =
2773                 DEV_TX_OFFLOAD_VLAN_INSERT |
2774                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2775                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2776                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2777                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2778                 DEV_TX_OFFLOAD_TCP_TSO;
2779
2780         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2781                 .rx_thresh = {
2782                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2783                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2784                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2785                 },
2786                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2787                 .rx_drop_en = 0,
2788         };
2789
2790         dev_info->default_txconf = (struct rte_eth_txconf) {
2791                 .tx_thresh = {
2792                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2793                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2794                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2795                 },
2796                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2797                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2798                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2799                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2800         };
2801
2802         dev_info->rx_desc_lim = rx_desc_lim;
2803         dev_info->tx_desc_lim = tx_desc_lim;
2804
2805         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2806         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2807         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2808 }
2809
2810 static void
2811 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2812                      struct rte_eth_dev_info *dev_info)
2813 {
2814         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815
2816         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2817         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2818         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2819         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2820         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2821         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2822         dev_info->max_vfs = dev->pci_dev->max_vfs;
2823         if (hw->mac.type == ixgbe_mac_82598EB)
2824                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2825         else
2826                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2827         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2828                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2829                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2830                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2831         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2832                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2833                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2834                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2835                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2836                                 DEV_TX_OFFLOAD_TCP_TSO;
2837
2838         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2839                 .rx_thresh = {
2840                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2841                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2842                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2843                 },
2844                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2845                 .rx_drop_en = 0,
2846         };
2847
2848         dev_info->default_txconf = (struct rte_eth_txconf) {
2849                 .tx_thresh = {
2850                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2851                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2852                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2853                 },
2854                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2855                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2856                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2857                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2858         };
2859
2860         dev_info->rx_desc_lim = rx_desc_lim;
2861         dev_info->tx_desc_lim = tx_desc_lim;
2862 }
2863
2864 /* return 0 means link status changed, -1 means not changed */
2865 static int
2866 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2867 {
2868         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2869         struct rte_eth_link link, old;
2870         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2871         int link_up;
2872         int diag;
2873
2874         link.link_status = 0;
2875         link.link_speed = 0;
2876         link.link_duplex = 0;
2877         memset(&old, 0, sizeof(old));
2878         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2879
2880         hw->mac.get_link_status = true;
2881
2882         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2883         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2884                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2885         else
2886                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2887
2888         if (diag != 0) {
2889                 link.link_speed = ETH_LINK_SPEED_100;
2890                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2891                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2892                 if (link.link_status == old.link_status)
2893                         return -1;
2894                 return 0;
2895         }
2896
2897         if (link_up == 0) {
2898                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2899                 if (link.link_status == old.link_status)
2900                         return -1;
2901                 return 0;
2902         }
2903         link.link_status = 1;
2904         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2905
2906         switch (link_speed) {
2907         default:
2908         case IXGBE_LINK_SPEED_UNKNOWN:
2909                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2910                 link.link_speed = ETH_LINK_SPEED_100;
2911                 break;
2912
2913         case IXGBE_LINK_SPEED_100_FULL:
2914                 link.link_speed = ETH_LINK_SPEED_100;
2915                 break;
2916
2917         case IXGBE_LINK_SPEED_1GB_FULL:
2918                 link.link_speed = ETH_LINK_SPEED_1000;
2919                 break;
2920
2921         case IXGBE_LINK_SPEED_10GB_FULL:
2922                 link.link_speed = ETH_LINK_SPEED_10000;
2923                 break;
2924         }
2925         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2926
2927         if (link.link_status == old.link_status)
2928                 return -1;
2929
2930         return 0;
2931 }
2932
2933 static void
2934 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2935 {
2936         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2937         uint32_t fctrl;
2938
2939         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2940         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2941         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2942 }
2943
2944 static void
2945 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2946 {
2947         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2948         uint32_t fctrl;
2949
2950         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2951         fctrl &= (~IXGBE_FCTRL_UPE);
2952         if (dev->data->all_multicast == 1)
2953                 fctrl |= IXGBE_FCTRL_MPE;
2954         else
2955                 fctrl &= (~IXGBE_FCTRL_MPE);
2956         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2957 }
2958
2959 static void
2960 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2961 {
2962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963         uint32_t fctrl;
2964
2965         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2966         fctrl |= IXGBE_FCTRL_MPE;
2967         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2968 }
2969
2970 static void
2971 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2972 {
2973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974         uint32_t fctrl;
2975
2976         if (dev->data->promiscuous == 1)
2977                 return; /* must remain in all_multicast mode */
2978
2979         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2980         fctrl &= (~IXGBE_FCTRL_MPE);
2981         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2982 }
2983
2984 /**
2985  * It clears the interrupt causes and enables the interrupt.
2986  * It will be called once only during nic initialized.
2987  *
2988  * @param dev
2989  *  Pointer to struct rte_eth_dev.
2990  *
2991  * @return
2992  *  - On success, zero.
2993  *  - On failure, a negative value.
2994  */
2995 static int
2996 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2997 {
2998         struct ixgbe_interrupt *intr =
2999                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3000
3001         ixgbe_dev_link_status_print(dev);
3002         intr->mask |= IXGBE_EICR_LSC;
3003
3004         return 0;
3005 }
3006
3007 /**
3008  * It clears the interrupt causes and enables the interrupt.
3009  * It will be called once only during nic initialized.
3010  *
3011  * @param dev
3012  *  Pointer to struct rte_eth_dev.
3013  *
3014  * @return
3015  *  - On success, zero.
3016  *  - On failure, a negative value.
3017  */
3018 static int
3019 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3020 {
3021         struct ixgbe_interrupt *intr =
3022                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3023
3024         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3025
3026         return 0;
3027 }
3028
3029 /*
3030  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3031  *
3032  * @param dev
3033  *  Pointer to struct rte_eth_dev.
3034  *
3035  * @return
3036  *  - On success, zero.
3037  *  - On failure, a negative value.
3038  */
3039 static int
3040 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3041 {
3042         uint32_t eicr;
3043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3044         struct ixgbe_interrupt *intr =
3045                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3046
3047         /* clear all cause mask */
3048         ixgbe_disable_intr(hw);
3049
3050         /* read-on-clear nic registers here */
3051         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3052         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3053
3054         intr->flags = 0;
3055
3056         /* set flag for async link update */
3057         if (eicr & IXGBE_EICR_LSC)
3058                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3059
3060         if (eicr & IXGBE_EICR_MAILBOX)
3061                 intr->flags |= IXGBE_FLAG_MAILBOX;
3062
3063         return 0;
3064 }
3065
3066 /**
3067  * It gets and then prints the link status.
3068  *
3069  * @param dev
3070  *  Pointer to struct rte_eth_dev.
3071  *
3072  * @return
3073  *  - On success, zero.
3074  *  - On failure, a negative value.
3075  */
3076 static void
3077 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3078 {
3079         struct rte_eth_link link;
3080
3081         memset(&link, 0, sizeof(link));
3082         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3083         if (link.link_status) {
3084                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3085                                         (int)(dev->data->port_id),
3086                                         (unsigned)link.link_speed,
3087                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3088                                         "full-duplex" : "half-duplex");
3089         } else {
3090                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3091                                 (int)(dev->data->port_id));
3092         }
3093         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3094                                 dev->pci_dev->addr.domain,
3095                                 dev->pci_dev->addr.bus,
3096                                 dev->pci_dev->addr.devid,
3097                                 dev->pci_dev->addr.function);
3098 }
3099
3100 /*
3101  * It executes link_update after knowing an interrupt occurred.
3102  *
3103  * @param dev
3104  *  Pointer to struct rte_eth_dev.
3105  *
3106  * @return
3107  *  - On success, zero.
3108  *  - On failure, a negative value.
3109  */
3110 static int
3111 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3112 {
3113         struct ixgbe_interrupt *intr =
3114                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3115         int64_t timeout;
3116         struct rte_eth_link link;
3117         int intr_enable_delay = false;
3118
3119         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3120
3121         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3122                 ixgbe_pf_mbx_process(dev);
3123                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3124         }
3125
3126         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3127                 /* get the link status before link update, for predicting later */
3128                 memset(&link, 0, sizeof(link));
3129                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3130
3131                 ixgbe_dev_link_update(dev, 0);
3132
3133                 /* likely to up */
3134                 if (!link.link_status)
3135                         /* handle it 1 sec later, wait it being stable */
3136                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3137                 /* likely to down */
3138                 else
3139                         /* handle it 4 sec later, wait it being stable */
3140                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3141
3142                 ixgbe_dev_link_status_print(dev);
3143
3144                 intr_enable_delay = true;
3145         }
3146
3147         if (intr_enable_delay) {
3148                 if (rte_eal_alarm_set(timeout * 1000,
3149                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3150                         PMD_DRV_LOG(ERR, "Error setting alarm");
3151         } else {
3152                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3153                 ixgbe_enable_intr(dev);
3154                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3155         }
3156
3157
3158         return 0;
3159 }
3160
3161 /**
3162  * Interrupt handler which shall be registered for alarm callback for delayed
3163  * handling specific interrupt to wait for the stable nic state. As the
3164  * NIC interrupt state is not stable for ixgbe after link is just down,
3165  * it needs to wait 4 seconds to get the stable status.
3166  *
3167  * @param handle
3168  *  Pointer to interrupt handle.
3169  * @param param
3170  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3171  *
3172  * @return
3173  *  void
3174  */
3175 static void
3176 ixgbe_dev_interrupt_delayed_handler(void *param)
3177 {
3178         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3179         struct ixgbe_interrupt *intr =
3180                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3181         struct ixgbe_hw *hw =
3182                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183         uint32_t eicr;
3184
3185         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3186         if (eicr & IXGBE_EICR_MAILBOX)
3187                 ixgbe_pf_mbx_process(dev);
3188
3189         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3190                 ixgbe_dev_link_update(dev, 0);
3191                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3192                 ixgbe_dev_link_status_print(dev);
3193                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3194         }
3195
3196         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3197         ixgbe_enable_intr(dev);
3198         rte_intr_enable(&(dev->pci_dev->intr_handle));
3199 }
3200
3201 /**
3202  * Interrupt handler triggered by NIC  for handling
3203  * specific interrupt.
3204  *
3205  * @param handle
3206  *  Pointer to interrupt handle.
3207  * @param param
3208  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3209  *
3210  * @return
3211  *  void
3212  */
3213 static void
3214 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3215                             void *param)
3216 {
3217         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3218
3219         ixgbe_dev_interrupt_get_status(dev);
3220         ixgbe_dev_interrupt_action(dev);
3221 }
3222
3223 static int
3224 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3225 {
3226         struct ixgbe_hw *hw;
3227
3228         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3230 }
3231
3232 static int
3233 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3234 {
3235         struct ixgbe_hw *hw;
3236
3237         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3239 }
3240
3241 static int
3242 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3243 {
3244         struct ixgbe_hw *hw;
3245         uint32_t mflcn_reg;
3246         uint32_t fccfg_reg;
3247         int rx_pause;
3248         int tx_pause;
3249
3250         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251
3252         fc_conf->pause_time = hw->fc.pause_time;
3253         fc_conf->high_water = hw->fc.high_water[0];
3254         fc_conf->low_water = hw->fc.low_water[0];
3255         fc_conf->send_xon = hw->fc.send_xon;
3256         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3257
3258         /*
3259          * Return rx_pause status according to actual setting of
3260          * MFLCN register.
3261          */
3262         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3263         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3264                 rx_pause = 1;
3265         else
3266                 rx_pause = 0;
3267
3268         /*
3269          * Return tx_pause status according to actual setting of
3270          * FCCFG register.
3271          */
3272         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3273         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3274                 tx_pause = 1;
3275         else
3276                 tx_pause = 0;
3277
3278         if (rx_pause && tx_pause)
3279                 fc_conf->mode = RTE_FC_FULL;
3280         else if (rx_pause)
3281                 fc_conf->mode = RTE_FC_RX_PAUSE;
3282         else if (tx_pause)
3283                 fc_conf->mode = RTE_FC_TX_PAUSE;
3284         else
3285                 fc_conf->mode = RTE_FC_NONE;
3286
3287         return 0;
3288 }
3289
3290 static int
3291 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3292 {
3293         struct ixgbe_hw *hw;
3294         int err;
3295         uint32_t rx_buf_size;
3296         uint32_t max_high_water;
3297         uint32_t mflcn;
3298         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3299                 ixgbe_fc_none,
3300                 ixgbe_fc_rx_pause,
3301                 ixgbe_fc_tx_pause,
3302                 ixgbe_fc_full
3303         };
3304
3305         PMD_INIT_FUNC_TRACE();
3306
3307         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3309         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3310
3311         /*
3312          * At least reserve one Ethernet frame for watermark
3313          * high_water/low_water in kilo bytes for ixgbe
3314          */
3315         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3316         if ((fc_conf->high_water > max_high_water) ||
3317                 (fc_conf->high_water < fc_conf->low_water)) {
3318                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3319                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3320                 return (-EINVAL);
3321         }
3322
3323         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3324         hw->fc.pause_time     = fc_conf->pause_time;
3325         hw->fc.high_water[0]  = fc_conf->high_water;
3326         hw->fc.low_water[0]   = fc_conf->low_water;
3327         hw->fc.send_xon       = fc_conf->send_xon;
3328         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3329
3330         err = ixgbe_fc_enable(hw);
3331
3332         /* Not negotiated is not an error case */
3333         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3334
3335                 /* check if we want to forward MAC frames - driver doesn't have native
3336                  * capability to do that, so we'll write the registers ourselves */
3337
3338                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3339
3340                 /* set or clear MFLCN.PMCF bit depending on configuration */
3341                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3342                         mflcn |= IXGBE_MFLCN_PMCF;
3343                 else
3344                         mflcn &= ~IXGBE_MFLCN_PMCF;
3345
3346                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3347                 IXGBE_WRITE_FLUSH(hw);
3348
3349                 return 0;
3350         }
3351
3352         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3353         return -EIO;
3354 }
3355
3356 /**
3357  *  ixgbe_pfc_enable_generic - Enable flow control
3358  *  @hw: pointer to hardware structure
3359  *  @tc_num: traffic class number
3360  *  Enable flow control according to the current settings.
3361  */
3362 static int
3363 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3364 {
3365         int ret_val = 0;
3366         uint32_t mflcn_reg, fccfg_reg;
3367         uint32_t reg;
3368         uint32_t fcrtl, fcrth;
3369         uint8_t i;
3370         uint8_t nb_rx_en;
3371
3372         /* Validate the water mark configuration */
3373         if (!hw->fc.pause_time) {
3374                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3375                 goto out;
3376         }
3377
3378         /* Low water mark of zero causes XOFF floods */
3379         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3380                  /* High/Low water can not be 0 */
3381                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3382                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3383                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3384                         goto out;
3385                 }
3386
3387                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3388                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3389                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3390                         goto out;
3391                 }
3392         }
3393         /* Negotiate the fc mode to use */
3394         ixgbe_fc_autoneg(hw);
3395
3396         /* Disable any previous flow control settings */
3397         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3398         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3399
3400         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3401         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3402
3403         switch (hw->fc.current_mode) {
3404         case ixgbe_fc_none:
3405                 /*
3406                  * If the count of enabled RX Priority Flow control >1,
3407                  * and the TX pause can not be disabled
3408                  */
3409                 nb_rx_en = 0;
3410                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3411                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3412                         if (reg & IXGBE_FCRTH_FCEN)
3413                                 nb_rx_en++;
3414                 }
3415                 if (nb_rx_en > 1)
3416                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3417                 break;
3418         case ixgbe_fc_rx_pause:
3419                 /*
3420                  * Rx Flow control is enabled and Tx Flow control is
3421                  * disabled by software override. Since there really
3422                  * isn't a way to advertise that we are capable of RX
3423                  * Pause ONLY, we will advertise that we support both
3424                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3425                  * disable the adapter's ability to send PAUSE frames.
3426                  */
3427                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3428                 /*
3429                  * If the count of enabled RX Priority Flow control >1,
3430                  * and the TX pause can not be disabled
3431                  */
3432                 nb_rx_en = 0;
3433                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3434                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3435                         if (reg & IXGBE_FCRTH_FCEN)
3436                                 nb_rx_en++;
3437                 }
3438                 if (nb_rx_en > 1)
3439                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3440                 break;
3441         case ixgbe_fc_tx_pause:
3442                 /*
3443                  * Tx Flow control is enabled, and Rx Flow control is
3444                  * disabled by software override.
3445                  */
3446                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3447                 break;
3448         case ixgbe_fc_full:
3449                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3450                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3451                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3452                 break;
3453         default:
3454                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3455                 ret_val = IXGBE_ERR_CONFIG;
3456                 goto out;
3457                 break;
3458         }
3459
3460         /* Set 802.3x based flow control settings. */
3461         mflcn_reg |= IXGBE_MFLCN_DPF;
3462         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3463         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3464
3465         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3466         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3467                 hw->fc.high_water[tc_num]) {
3468                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3469                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3470                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3471         } else {
3472                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3473                 /*
3474                  * In order to prevent Tx hangs when the internal Tx
3475                  * switch is enabled we must set the high water mark
3476                  * to the maximum FCRTH value.  This allows the Tx
3477                  * switch to function even under heavy Rx workloads.
3478                  */
3479                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3480         }
3481         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3482
3483         /* Configure pause time (2 TCs per register) */
3484         reg = hw->fc.pause_time * 0x00010001;
3485         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3486                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3487
3488         /* Configure flow control refresh threshold value */
3489         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3490
3491 out:
3492         return ret_val;
3493 }
3494
3495 static int
3496 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3497 {
3498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3499         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3500
3501         if(hw->mac.type != ixgbe_mac_82598EB) {
3502                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3503         }
3504         return ret_val;
3505 }
3506
3507 static int
3508 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3509 {
3510         int err;
3511         uint32_t rx_buf_size;
3512         uint32_t max_high_water;
3513         uint8_t tc_num;
3514         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3515         struct ixgbe_hw *hw =
3516                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3517         struct ixgbe_dcb_config *dcb_config =
3518                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3519
3520         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3521                 ixgbe_fc_none,
3522                 ixgbe_fc_rx_pause,
3523                 ixgbe_fc_tx_pause,
3524                 ixgbe_fc_full
3525         };
3526
3527         PMD_INIT_FUNC_TRACE();
3528
3529         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3530         tc_num = map[pfc_conf->priority];
3531         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3532         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3533         /*
3534          * At least reserve one Ethernet frame for watermark
3535          * high_water/low_water in kilo bytes for ixgbe
3536          */
3537         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3538         if ((pfc_conf->fc.high_water > max_high_water) ||
3539             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3540                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3541                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3542                 return (-EINVAL);
3543         }
3544
3545         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3546         hw->fc.pause_time = pfc_conf->fc.pause_time;
3547         hw->fc.send_xon = pfc_conf->fc.send_xon;
3548         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3549         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3550
3551         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3552
3553         /* Not negotiated is not an error case */
3554         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3555                 return 0;
3556
3557         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3558         return -EIO;
3559 }
3560
3561 static int
3562 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3563                           struct rte_eth_rss_reta_entry64 *reta_conf,
3564                           uint16_t reta_size)
3565 {
3566         uint8_t i, j, mask;
3567         uint32_t reta, r;
3568         uint16_t idx, shift;
3569         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570         uint16_t sp_reta_size;
3571         uint32_t reta_reg;
3572
3573         PMD_INIT_FUNC_TRACE();
3574
3575         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3576                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3577                         "NIC.");
3578                 return -ENOTSUP;
3579         }
3580
3581         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3582         if (reta_size != sp_reta_size) {
3583                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3584                         "(%d) doesn't match the number hardware can supported "
3585                         "(%d)\n", reta_size, sp_reta_size);
3586                 return -EINVAL;
3587         }
3588
3589         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3590                 idx = i / RTE_RETA_GROUP_SIZE;
3591                 shift = i % RTE_RETA_GROUP_SIZE;
3592                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3593                                                 IXGBE_4_BIT_MASK);
3594                 if (!mask)
3595                         continue;
3596                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3597                 if (mask == IXGBE_4_BIT_MASK)
3598                         r = 0;
3599                 else
3600                         r = IXGBE_READ_REG(hw, reta_reg);
3601                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3602                         if (mask & (0x1 << j))
3603                                 reta |= reta_conf[idx].reta[shift + j] <<
3604                                                         (CHAR_BIT * j);
3605                         else
3606                                 reta |= r & (IXGBE_8_BIT_MASK <<
3607                                                 (CHAR_BIT * j));
3608                 }
3609                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3610         }
3611
3612         return 0;
3613 }
3614
3615 static int
3616 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3617                          struct rte_eth_rss_reta_entry64 *reta_conf,
3618                          uint16_t reta_size)
3619 {
3620         uint8_t i, j, mask;
3621         uint32_t reta;
3622         uint16_t idx, shift;
3623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3624         uint16_t sp_reta_size;
3625         uint32_t reta_reg;
3626
3627         PMD_INIT_FUNC_TRACE();
3628         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3629         if (reta_size != sp_reta_size) {
3630                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3631                         "(%d) doesn't match the number hardware can supported "
3632                         "(%d)\n", reta_size, sp_reta_size);
3633                 return -EINVAL;
3634         }
3635
3636         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3637                 idx = i / RTE_RETA_GROUP_SIZE;
3638                 shift = i % RTE_RETA_GROUP_SIZE;
3639                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3640                                                 IXGBE_4_BIT_MASK);
3641                 if (!mask)
3642                         continue;
3643
3644                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3645                 reta = IXGBE_READ_REG(hw, reta_reg);
3646                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3647                         if (mask & (0x1 << j))
3648                                 reta_conf[idx].reta[shift + j] =
3649                                         ((reta >> (CHAR_BIT * j)) &
3650                                                 IXGBE_8_BIT_MASK);
3651                 }
3652         }
3653
3654         return 0;
3655 }
3656
3657 static void
3658 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3659                                 uint32_t index, uint32_t pool)
3660 {
3661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3662         uint32_t enable_addr = 1;
3663
3664         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3665 }
3666
3667 static void
3668 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3669 {
3670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3671
3672         ixgbe_clear_rar(hw, index);
3673 }
3674
3675 static void
3676 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3677 {
3678         ixgbe_remove_rar(dev, 0);
3679
3680         ixgbe_add_rar(dev, addr, 0, 0);
3681 }
3682
3683 static int
3684 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3685 {
3686         uint32_t hlreg0;
3687         uint32_t maxfrs;
3688         struct ixgbe_hw *hw;
3689         struct rte_eth_dev_info dev_info;
3690         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3691
3692         ixgbe_dev_info_get(dev, &dev_info);
3693
3694         /* check that mtu is within the allowed range */
3695         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3696                 return -EINVAL;
3697
3698         /* refuse mtu that requires the support of scattered packets when this
3699          * feature has not been enabled before. */
3700         if (!dev->data->scattered_rx &&
3701             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3702              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3703                 return -EINVAL;
3704
3705         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3707
3708         /* switch to jumbo mode if needed */
3709         if (frame_size > ETHER_MAX_LEN) {
3710                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3711                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3712         } else {
3713                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3714                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3715         }
3716         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3717
3718         /* update max frame size */
3719         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3720
3721         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3722         maxfrs &= 0x0000FFFF;
3723         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3724         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3725
3726         return 0;
3727 }
3728
3729 /*
3730  * Virtual Function operations
3731  */
3732 static void
3733 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3734 {
3735         PMD_INIT_FUNC_TRACE();
3736
3737         /* Clear interrupt mask to stop from interrupts being generated */
3738         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3739
3740         IXGBE_WRITE_FLUSH(hw);
3741 }
3742
3743 static void
3744 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3745 {
3746         PMD_INIT_FUNC_TRACE();
3747
3748         /* VF enable interrupt autoclean */
3749         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3750         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3751         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3752
3753         IXGBE_WRITE_FLUSH(hw);
3754 }
3755
3756 static int
3757 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3758 {
3759         struct rte_eth_conf* conf = &dev->data->dev_conf;
3760         struct ixgbe_adapter *adapter =
3761                         (struct ixgbe_adapter *)dev->data->dev_private;
3762
3763         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3764                      dev->data->port_id);
3765
3766         /*
3767          * VF has no ability to enable/disable HW CRC
3768          * Keep the persistent behavior the same as Host PF
3769          */
3770 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3771         if (!conf->rxmode.hw_strip_crc) {
3772                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3773                 conf->rxmode.hw_strip_crc = 1;
3774         }
3775 #else
3776         if (conf->rxmode.hw_strip_crc) {
3777                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3778                 conf->rxmode.hw_strip_crc = 0;
3779         }
3780 #endif
3781
3782         /*
3783          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3784          * allocation or vector Rx preconditions we will reset it.
3785          */
3786         adapter->rx_bulk_alloc_allowed = true;
3787         adapter->rx_vec_allowed = true;
3788
3789         return 0;
3790 }
3791
3792 static int
3793 ixgbevf_dev_start(struct rte_eth_dev *dev)
3794 {
3795         struct ixgbe_hw *hw =
3796                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3797         uint32_t intr_vector = 0;
3798         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3799
3800         int err, mask = 0;
3801
3802         PMD_INIT_FUNC_TRACE();
3803
3804         hw->mac.ops.reset_hw(hw);
3805         hw->mac.get_link_status = true;
3806
3807         /* negotiate mailbox API version to use with the PF. */
3808         ixgbevf_negotiate_api(hw);
3809
3810         ixgbevf_dev_tx_init(dev);
3811
3812         /* This can fail when allocating mbufs for descriptor rings */
3813         err = ixgbevf_dev_rx_init(dev);
3814         if (err) {
3815                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3816                 ixgbe_dev_clear_queues(dev);
3817                 return err;
3818         }
3819
3820         /* Set vfta */
3821         ixgbevf_set_vfta_all(dev,1);
3822
3823         /* Set HW strip */
3824         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3825                 ETH_VLAN_EXTEND_MASK;
3826         ixgbevf_vlan_offload_set(dev, mask);
3827
3828         ixgbevf_dev_rxtx_start(dev);
3829
3830         /* check and configure queue intr-vector mapping */
3831         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3832                 intr_vector = dev->data->nb_rx_queues;
3833                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3834                         return -1;
3835         }
3836
3837         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3838                 intr_handle->intr_vec =
3839                         rte_zmalloc("intr_vec",
3840                                     dev->data->nb_rx_queues * sizeof(int), 0);
3841                 if (intr_handle->intr_vec == NULL) {
3842                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3843                                      " intr_vec\n", dev->data->nb_rx_queues);
3844                         return -ENOMEM;
3845                 }
3846         }
3847         ixgbevf_configure_msix(dev);
3848
3849         rte_intr_enable(intr_handle);
3850
3851         /* Re-enable interrupt for VF */
3852         ixgbevf_intr_enable(hw);
3853
3854         return 0;
3855 }
3856
3857 static void
3858 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3859 {
3860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3861         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3862
3863         PMD_INIT_FUNC_TRACE();
3864
3865         hw->adapter_stopped = 1;
3866         ixgbe_stop_adapter(hw);
3867
3868         /*
3869           * Clear what we set, but we still keep shadow_vfta to
3870           * restore after device starts
3871           */
3872         ixgbevf_set_vfta_all(dev,0);
3873
3874         /* Clear stored conf */
3875         dev->data->scattered_rx = 0;
3876
3877         ixgbe_dev_clear_queues(dev);
3878
3879         /* disable intr eventfd mapping */
3880         rte_intr_disable(intr_handle);
3881
3882         /* Clean datapath event and queue/vec mapping */
3883         rte_intr_efd_disable(intr_handle);
3884         if (intr_handle->intr_vec != NULL) {
3885                 rte_free(intr_handle->intr_vec);
3886                 intr_handle->intr_vec = NULL;
3887         }
3888 }
3889
3890 static void
3891 ixgbevf_dev_close(struct rte_eth_dev *dev)
3892 {
3893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894
3895         PMD_INIT_FUNC_TRACE();
3896
3897         ixgbe_reset_hw(hw);
3898
3899         ixgbevf_dev_stop(dev);
3900
3901         ixgbe_dev_free_queues(dev);
3902
3903         /* reprogram the RAR[0] in case user changed it. */
3904         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3905 }
3906
3907 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3908 {
3909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3910         struct ixgbe_vfta * shadow_vfta =
3911                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3912         int i = 0, j = 0, vfta = 0, mask = 1;
3913
3914         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3915                 vfta = shadow_vfta->vfta[i];
3916                 if(vfta){
3917                         mask = 1;
3918                         for (j = 0; j < 32; j++){
3919                                 if(vfta & mask)
3920                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3921                                 mask<<=1;
3922                         }
3923                 }
3924         }
3925
3926 }
3927
3928 static int
3929 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3930 {
3931         struct ixgbe_hw *hw =
3932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933         struct ixgbe_vfta * shadow_vfta =
3934                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3935         uint32_t vid_idx = 0;
3936         uint32_t vid_bit = 0;
3937         int ret = 0;
3938
3939         PMD_INIT_FUNC_TRACE();
3940
3941         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3942         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3943         if(ret){
3944                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3945                 return ret;
3946         }
3947         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3948         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3949
3950         /* Save what we set and retore it after device reset */
3951         if (on)
3952                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3953         else
3954                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3955
3956         return 0;
3957 }
3958
3959 static void
3960 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3961 {
3962         struct ixgbe_hw *hw =
3963                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3964         uint32_t ctrl;
3965
3966         PMD_INIT_FUNC_TRACE();
3967
3968         if(queue >= hw->mac.max_rx_queues)
3969                 return;
3970
3971         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3972         if(on)
3973                 ctrl |= IXGBE_RXDCTL_VME;
3974         else
3975                 ctrl &= ~IXGBE_RXDCTL_VME;
3976         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3977
3978         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3979 }
3980
3981 static void
3982 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3983 {
3984         struct ixgbe_hw *hw =
3985                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3986         uint16_t i;
3987         int on = 0;
3988
3989         /* VF function only support hw strip feature, others are not support */
3990         if(mask & ETH_VLAN_STRIP_MASK){
3991                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3992
3993                 for(i=0; i < hw->mac.max_rx_queues; i++)
3994                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3995         }
3996 }
3997
3998 static int
3999 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4000 {
4001         uint32_t reg_val;
4002
4003         /* we only need to do this if VMDq is enabled */
4004         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4005         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4006                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4007                 return (-1);
4008         }
4009
4010         return 0;
4011 }
4012
4013 static uint32_t
4014 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4015 {
4016         uint32_t vector = 0;
4017         switch (hw->mac.mc_filter_type) {
4018         case 0:   /* use bits [47:36] of the address */
4019                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4020                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4021                 break;
4022         case 1:   /* use bits [46:35] of the address */
4023                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4024                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4025                 break;
4026         case 2:   /* use bits [45:34] of the address */
4027                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4028                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4029                 break;
4030         case 3:   /* use bits [43:32] of the address */
4031                 vector = ((uc_addr->addr_bytes[4]) |
4032                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4033                 break;
4034         default:  /* Invalid mc_filter_type */
4035                 break;
4036         }
4037
4038         /* vector can only be 12-bits or boundary will be exceeded */
4039         vector &= 0xFFF;
4040         return vector;
4041 }
4042
4043 static int
4044 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4045                                uint8_t on)
4046 {
4047         uint32_t vector;
4048         uint32_t uta_idx;
4049         uint32_t reg_val;
4050         uint32_t uta_shift;
4051         uint32_t rc;
4052         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4053         const uint32_t ixgbe_uta_bit_shift = 5;
4054         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4055         const uint32_t bit1 = 0x1;
4056
4057         struct ixgbe_hw *hw =
4058                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4059         struct ixgbe_uta_info *uta_info =
4060                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4061
4062         /* The UTA table only exists on 82599 hardware and newer */
4063         if (hw->mac.type < ixgbe_mac_82599EB)
4064                 return (-ENOTSUP);
4065
4066         vector = ixgbe_uta_vector(hw,mac_addr);
4067         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4068         uta_shift = vector & ixgbe_uta_bit_mask;
4069
4070         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4071         if(rc == on)
4072                 return 0;
4073
4074         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4075         if (on) {
4076                 uta_info->uta_in_use++;
4077                 reg_val |= (bit1 << uta_shift);
4078                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4079         } else {
4080                 uta_info->uta_in_use--;
4081                 reg_val &= ~(bit1 << uta_shift);
4082                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4083         }
4084
4085         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4086
4087         if (uta_info->uta_in_use > 0)
4088                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4089                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4090         else
4091                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4092
4093         return 0;
4094 }
4095
4096 static int
4097 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4098 {
4099         int i;
4100         struct ixgbe_hw *hw =
4101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102         struct ixgbe_uta_info *uta_info =
4103                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4104
4105         /* The UTA table only exists on 82599 hardware and newer */
4106         if (hw->mac.type < ixgbe_mac_82599EB)
4107                 return (-ENOTSUP);
4108
4109         if(on) {
4110                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4111                         uta_info->uta_shadow[i] = ~0;
4112                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4113                 }
4114         } else {
4115                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4116                         uta_info->uta_shadow[i] = 0;
4117                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4118                 }
4119         }
4120         return 0;
4121
4122 }
4123
4124 uint32_t
4125 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4126 {
4127         uint32_t new_val = orig_val;
4128
4129         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4130                 new_val |= IXGBE_VMOLR_AUPE;
4131         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4132                 new_val |= IXGBE_VMOLR_ROMPE;
4133         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4134                 new_val |= IXGBE_VMOLR_ROPE;
4135         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4136                 new_val |= IXGBE_VMOLR_BAM;
4137         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4138                 new_val |= IXGBE_VMOLR_MPE;
4139
4140         return new_val;
4141 }
4142
4143 static int
4144 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4145                                uint16_t rx_mask, uint8_t on)
4146 {
4147         int val = 0;
4148
4149         struct ixgbe_hw *hw =
4150                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4151         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4152
4153         if (hw->mac.type == ixgbe_mac_82598EB) {
4154                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4155                              " on 82599 hardware and newer");
4156                 return (-ENOTSUP);
4157         }
4158         if (ixgbe_vmdq_mode_check(hw) < 0)
4159                 return (-ENOTSUP);
4160
4161         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4162
4163         if (on)
4164                 vmolr |= val;
4165         else
4166                 vmolr &= ~val;
4167
4168         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4169
4170         return 0;
4171 }
4172
4173 static int
4174 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4175 {
4176         uint32_t reg,addr;
4177         uint32_t val;
4178         const uint8_t bit1 = 0x1;
4179
4180         struct ixgbe_hw *hw =
4181                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182
4183         if (ixgbe_vmdq_mode_check(hw) < 0)
4184                 return (-ENOTSUP);
4185
4186         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4187         reg = IXGBE_READ_REG(hw, addr);
4188         val = bit1 << pool;
4189
4190         if (on)
4191                 reg |= val;
4192         else
4193                 reg &= ~val;
4194
4195         IXGBE_WRITE_REG(hw, addr,reg);
4196
4197         return 0;
4198 }
4199
4200 static int
4201 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4202 {
4203         uint32_t reg,addr;
4204         uint32_t val;
4205         const uint8_t bit1 = 0x1;
4206
4207         struct ixgbe_hw *hw =
4208                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4209
4210         if (ixgbe_vmdq_mode_check(hw) < 0)
4211                 return (-ENOTSUP);
4212
4213         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4214         reg = IXGBE_READ_REG(hw, addr);
4215         val = bit1 << pool;
4216
4217         if (on)
4218                 reg |= val;
4219         else
4220                 reg &= ~val;
4221
4222         IXGBE_WRITE_REG(hw, addr,reg);
4223
4224         return 0;
4225 }
4226
4227 static int
4228 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4229                         uint64_t pool_mask, uint8_t vlan_on)
4230 {
4231         int ret = 0;
4232         uint16_t pool_idx;
4233         struct ixgbe_hw *hw =
4234                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235
4236         if (ixgbe_vmdq_mode_check(hw) < 0)
4237                 return (-ENOTSUP);
4238         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4239                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4240                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4241                         if (ret < 0)
4242                                 return ret;
4243         }
4244
4245         return ret;
4246 }
4247
4248 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4249 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4250 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4251 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4252 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4253         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4254         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4255
4256 static int
4257 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4258                         struct rte_eth_mirror_conf *mirror_conf,
4259                         uint8_t rule_id, uint8_t on)
4260 {
4261         uint32_t mr_ctl,vlvf;
4262         uint32_t mp_lsb = 0;
4263         uint32_t mv_msb = 0;
4264         uint32_t mv_lsb = 0;
4265         uint32_t mp_msb = 0;
4266         uint8_t i = 0;
4267         int reg_index = 0;
4268         uint64_t vlan_mask = 0;
4269
4270         const uint8_t pool_mask_offset = 32;
4271         const uint8_t vlan_mask_offset = 32;
4272         const uint8_t dst_pool_offset = 8;
4273         const uint8_t rule_mr_offset  = 4;
4274         const uint8_t mirror_rule_mask= 0x0F;
4275
4276         struct ixgbe_mirror_info *mr_info =
4277                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4278         struct ixgbe_hw *hw =
4279                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4280         uint8_t mirror_type = 0;
4281
4282         if (ixgbe_vmdq_mode_check(hw) < 0)
4283                 return -ENOTSUP;
4284
4285         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4286                 return -EINVAL;
4287
4288         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4289                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4290                         mirror_conf->rule_type);
4291                 return -EINVAL;
4292         }
4293
4294         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4295                 mirror_type |= IXGBE_MRCTL_VLME;
4296                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4297                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4298                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4299                                 /* search vlan id related pool vlan filter index */
4300                                 reg_index = ixgbe_find_vlvf_slot(hw,
4301                                                 mirror_conf->vlan.vlan_id[i]);
4302                                 if(reg_index < 0)
4303                                         return -EINVAL;
4304                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4305                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4306                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4307                                       mirror_conf->vlan.vlan_id[i]))
4308                                         vlan_mask |= (1ULL << reg_index);
4309                                 else
4310                                         return -EINVAL;
4311                         }
4312                 }
4313
4314                 if (on) {
4315                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4316                         mv_msb = vlan_mask >> vlan_mask_offset;
4317
4318                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4319                                                 mirror_conf->vlan.vlan_mask;
4320                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4321                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4322                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4323                                                 mirror_conf->vlan.vlan_id[i];
4324                         }
4325                 } else {
4326                         mv_lsb = 0;
4327                         mv_msb = 0;
4328                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4329                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4330                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4331                 }
4332         }
4333
4334         /*
4335          * if enable pool mirror, write related pool mask register,if disable
4336          * pool mirror, clear PFMRVM register
4337          */
4338         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4339                 mirror_type |= IXGBE_MRCTL_VPME;
4340                 if (on) {
4341                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4342                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4343                         mr_info->mr_conf[rule_id].pool_mask =
4344                                         mirror_conf->pool_mask;
4345
4346                 } else {
4347                         mp_lsb = 0;
4348                         mp_msb = 0;
4349                         mr_info->mr_conf[rule_id].pool_mask = 0;
4350                 }
4351         }
4352         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4353                 mirror_type |= IXGBE_MRCTL_UPME;
4354         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4355                 mirror_type |= IXGBE_MRCTL_DPME;
4356
4357         /* read  mirror control register and recalculate it */
4358         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4359
4360         if (on) {
4361                 mr_ctl |= mirror_type;
4362                 mr_ctl &= mirror_rule_mask;
4363                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4364         } else
4365                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4366
4367         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4368         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4369
4370         /* write mirrror control  register */
4371         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4372
4373         /* write pool mirrror control  register */
4374         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4375                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4376                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4377                                 mp_msb);
4378         }
4379         /* write VLAN mirrror control  register */
4380         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4381                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4382                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4383                                 mv_msb);
4384         }
4385
4386         return 0;
4387 }
4388
4389 static int
4390 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4391 {
4392         int mr_ctl = 0;
4393         uint32_t lsb_val = 0;
4394         uint32_t msb_val = 0;
4395         const uint8_t rule_mr_offset = 4;
4396
4397         struct ixgbe_hw *hw =
4398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4399         struct ixgbe_mirror_info *mr_info =
4400                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4401
4402         if (ixgbe_vmdq_mode_check(hw) < 0)
4403                 return (-ENOTSUP);
4404
4405         memset(&mr_info->mr_conf[rule_id], 0,
4406                 sizeof(struct rte_eth_mirror_conf));
4407
4408         /* clear PFVMCTL register */
4409         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4410
4411         /* clear pool mask register */
4412         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4413         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4414
4415         /* clear vlan mask register */
4416         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4417         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4418
4419         return 0;
4420 }
4421
4422 static int
4423 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4424 {
4425         uint32_t mask;
4426         struct ixgbe_hw *hw =
4427                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428
4429         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4430         mask |= (1 << IXGBE_MISC_VEC_ID);
4431         RTE_SET_USED(queue_id);
4432         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4433
4434         rte_intr_enable(&dev->pci_dev->intr_handle);
4435
4436         return 0;
4437 }
4438
4439 static int
4440 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4441 {
4442         uint32_t mask;
4443         struct ixgbe_hw *hw =
4444                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4445
4446         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4447         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4448         RTE_SET_USED(queue_id);
4449         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4450
4451         return 0;
4452 }
4453
4454 static int
4455 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4456 {
4457         uint32_t mask;
4458         struct ixgbe_hw *hw =
4459                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460         struct ixgbe_interrupt *intr =
4461                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4462
4463         if (queue_id < 16) {
4464                 ixgbe_disable_intr(hw);
4465                 intr->mask |= (1 << queue_id);
4466                 ixgbe_enable_intr(dev);
4467         } else if (queue_id < 32) {
4468                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4469                 mask &= (1 << queue_id);
4470                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4471         } else if (queue_id < 64) {
4472                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4473                 mask &= (1 << (queue_id - 32));
4474                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4475         }
4476         rte_intr_enable(&dev->pci_dev->intr_handle);
4477
4478         return 0;
4479 }
4480
4481 static int
4482 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4483 {
4484         uint32_t mask;
4485         struct ixgbe_hw *hw =
4486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487         struct ixgbe_interrupt *intr =
4488                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4489
4490         if (queue_id < 16) {
4491                 ixgbe_disable_intr(hw);
4492                 intr->mask &= ~(1 << queue_id);
4493                 ixgbe_enable_intr(dev);
4494         } else if (queue_id < 32) {
4495                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4496                 mask &= ~(1 << queue_id);
4497                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4498         } else if (queue_id < 64) {
4499                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4500                 mask &= ~(1 << (queue_id - 32));
4501                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4502         }
4503
4504         return 0;
4505 }
4506
4507 static void
4508 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4509                      uint8_t queue, uint8_t msix_vector)
4510 {
4511         uint32_t tmp, idx;
4512
4513         if (direction == -1) {
4514                 /* other causes */
4515                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4516                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4517                 tmp &= ~0xFF;
4518                 tmp |= msix_vector;
4519                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4520         } else {
4521                 /* rx or tx cause */
4522                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4523                 idx = ((16 * (queue & 1)) + (8 * direction));
4524                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4525                 tmp &= ~(0xFF << idx);
4526                 tmp |= (msix_vector << idx);
4527                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4528         }
4529 }
4530
4531 /**
4532  * set the IVAR registers, mapping interrupt causes to vectors
4533  * @param hw
4534  *  pointer to ixgbe_hw struct
4535  * @direction
4536  *  0 for Rx, 1 for Tx, -1 for other causes
4537  * @queue
4538  *  queue to map the corresponding interrupt to
4539  * @msix_vector
4540  *  the vector to map to the corresponding queue
4541  */
4542 static void
4543 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4544                    uint8_t queue, uint8_t msix_vector)
4545 {
4546         uint32_t tmp, idx;
4547
4548         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4549         if (hw->mac.type == ixgbe_mac_82598EB) {
4550                 if (direction == -1)
4551                         direction = 0;
4552                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4553                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4554                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4555                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4556                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4557         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4558                         (hw->mac.type == ixgbe_mac_X540)) {
4559                 if (direction == -1) {
4560                         /* other causes */
4561                         idx = ((queue & 1) * 8);
4562                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4563                         tmp &= ~(0xFF << idx);
4564                         tmp |= (msix_vector << idx);
4565                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4566                 } else {
4567                         /* rx or tx causes */
4568                         idx = ((16 * (queue & 1)) + (8 * direction));
4569                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4570                         tmp &= ~(0xFF << idx);
4571                         tmp |= (msix_vector << idx);
4572                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4573                 }
4574         }
4575 }
4576
4577 static void
4578 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4579 {
4580         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4581         struct ixgbe_hw *hw =
4582                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4583         uint32_t q_idx;
4584         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4585
4586         /* won't configure msix register if no mapping is done
4587          * between intr vector and event fd.
4588          */
4589         if (!rte_intr_dp_is_en(intr_handle))
4590                 return;
4591
4592         /* Configure all RX queues of VF */
4593         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4594                 /* Force all queue use vector 0,
4595                  * as IXGBE_VF_MAXMSIVECOTR = 1
4596                  */
4597                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4598                 intr_handle->intr_vec[q_idx] = vector_idx;
4599         }
4600
4601         /* Configure VF other cause ivar */
4602         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4603 }
4604
4605 /**
4606  * Sets up the hardware to properly generate MSI-X interrupts
4607  * @hw
4608  *  board private structure
4609  */
4610 static void
4611 ixgbe_configure_msix(struct rte_eth_dev *dev)
4612 {
4613         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4614         struct ixgbe_hw *hw =
4615                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4617         uint32_t vec = IXGBE_MISC_VEC_ID;
4618         uint32_t mask;
4619         uint32_t gpie;
4620
4621         /* won't configure msix register if no mapping is done
4622          * between intr vector and event fd
4623          */
4624         if (!rte_intr_dp_is_en(intr_handle))
4625                 return;
4626
4627         if (rte_intr_allow_others(intr_handle))
4628                 vec = base = IXGBE_RX_VEC_START;
4629
4630         /* setup GPIE for MSI-x mode */
4631         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4632         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4633                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4634         /* auto clearing and auto setting corresponding bits in EIMS
4635          * when MSI-X interrupt is triggered
4636          */
4637         if (hw->mac.type == ixgbe_mac_82598EB) {
4638                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4639         } else {
4640                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4641                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4642         }
4643         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4644
4645         /* Populate the IVAR table and set the ITR values to the
4646          * corresponding register.
4647          */
4648         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4649              queue_id++) {
4650                 /* by default, 1:1 mapping */
4651                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4652                 intr_handle->intr_vec[queue_id] = vec;
4653                 if (vec < base + intr_handle->nb_efd - 1)
4654                         vec++;
4655         }
4656
4657         switch (hw->mac.type) {
4658         case ixgbe_mac_82598EB:
4659                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4660                                    IXGBE_MISC_VEC_ID);
4661                 break;
4662         case ixgbe_mac_82599EB:
4663         case ixgbe_mac_X540:
4664                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4665                 break;
4666         default:
4667                 break;
4668         }
4669         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4670                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4671
4672         /* set up to autoclear timer, and the vectors */
4673         mask = IXGBE_EIMS_ENABLE_MASK;
4674         mask &= ~(IXGBE_EIMS_OTHER |
4675                   IXGBE_EIMS_MAILBOX |
4676                   IXGBE_EIMS_LSC);
4677
4678         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4679 }
4680
4681 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4682         uint16_t queue_idx, uint16_t tx_rate)
4683 {
4684         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4685         uint32_t rf_dec, rf_int;
4686         uint32_t bcnrc_val;
4687         uint16_t link_speed = dev->data->dev_link.link_speed;
4688
4689         if (queue_idx >= hw->mac.max_tx_queues)
4690                 return -EINVAL;
4691
4692         if (tx_rate != 0) {
4693                 /* Calculate the rate factor values to set */
4694                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4695                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4696                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4697
4698                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4699                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4700                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4701                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4702         } else {
4703                 bcnrc_val = 0;
4704         }
4705
4706         /*
4707          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4708          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4709          * set as 0x4.
4710          */
4711         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4712                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4713                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4714                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4715                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4716         else
4717                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4718                         IXGBE_MMW_SIZE_DEFAULT);
4719
4720         /* Set RTTBCNRC of queue X */
4721         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4722         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4723         IXGBE_WRITE_FLUSH(hw);
4724
4725         return 0;
4726 }
4727
4728 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4729         uint16_t tx_rate, uint64_t q_msk)
4730 {
4731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4732         struct ixgbe_vf_info *vfinfo =
4733                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4734         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4735         uint32_t queue_stride =
4736                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4737         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4738         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4739         uint16_t total_rate = 0;
4740
4741         if (queue_end >= hw->mac.max_tx_queues)
4742                 return -EINVAL;
4743
4744         if (vfinfo != NULL) {
4745                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4746                         if (vf_idx == vf)
4747                                 continue;
4748                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4749                                 idx++)
4750                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4751                 }
4752         } else
4753                 return -EINVAL;
4754
4755         /* Store tx_rate for this vf. */
4756         for (idx = 0; idx < nb_q_per_pool; idx++) {
4757                 if (((uint64_t)0x1 << idx) & q_msk) {
4758                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4759                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4760                         total_rate += tx_rate;
4761                 }
4762         }
4763
4764         if (total_rate > dev->data->dev_link.link_speed) {
4765                 /*
4766                  * Reset stored TX rate of the VF if it causes exceed
4767                  * link speed.
4768                  */
4769                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4770                 return -EINVAL;
4771         }
4772
4773         /* Set RTTBCNRC of each queue/pool for vf X  */
4774         for (; queue_idx <= queue_end; queue_idx++) {
4775                 if (0x1 & q_msk)
4776                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4777                 q_msk = q_msk >> 1;
4778         }
4779
4780         return 0;
4781 }
4782
4783 static void
4784 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4785                      __attribute__((unused)) uint32_t index,
4786                      __attribute__((unused)) uint32_t pool)
4787 {
4788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789         int diag;
4790
4791         /*
4792          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4793          * operation. Trap this case to avoid exhausting the [very limited]
4794          * set of PF resources used to store VF MAC addresses.
4795          */
4796         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4797                 return;
4798         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4799         if (diag == 0)
4800                 return;
4801         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4802 }
4803
4804 static void
4805 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4806 {
4807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4808         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4809         struct ether_addr *mac_addr;
4810         uint32_t i;
4811         int diag;
4812
4813         /*
4814          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4815          * not support the deletion of a given MAC address.
4816          * Instead, it imposes to delete all MAC addresses, then to add again
4817          * all MAC addresses with the exception of the one to be deleted.
4818          */
4819         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4820
4821         /*
4822          * Add again all MAC addresses, with the exception of the deleted one
4823          * and of the permanent MAC address.
4824          */
4825         for (i = 0, mac_addr = dev->data->mac_addrs;
4826              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4827                 /* Skip the deleted MAC address */
4828                 if (i == index)
4829                         continue;
4830                 /* Skip NULL MAC addresses */
4831                 if (is_zero_ether_addr(mac_addr))
4832                         continue;
4833                 /* Skip the permanent MAC address */
4834                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4835                         continue;
4836                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4837                 if (diag != 0)
4838                         PMD_DRV_LOG(ERR,
4839                                     "Adding again MAC address "
4840                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4841                                     "diag=%d",
4842                                     mac_addr->addr_bytes[0],
4843                                     mac_addr->addr_bytes[1],
4844                                     mac_addr->addr_bytes[2],
4845                                     mac_addr->addr_bytes[3],
4846                                     mac_addr->addr_bytes[4],
4847                                     mac_addr->addr_bytes[5],
4848                                     diag);
4849         }
4850 }
4851
4852 static void
4853 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4854 {
4855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4856
4857         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4858 }
4859
4860 #define MAC_TYPE_FILTER_SUP(type)    do {\
4861         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4862                 (type) != ixgbe_mac_X550)\
4863                 return -ENOTSUP;\
4864 } while (0)
4865
4866 static int
4867 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4868                         struct rte_eth_syn_filter *filter,
4869                         bool add)
4870 {
4871         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4872         uint32_t synqf;
4873
4874         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4875                 return -EINVAL;
4876
4877         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4878
4879         if (add) {
4880                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4881                         return -EINVAL;
4882                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4883                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4884
4885                 if (filter->hig_pri)
4886                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4887                 else
4888                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4889         } else {
4890                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4891                         return -ENOENT;
4892                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4893         }
4894         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4895         IXGBE_WRITE_FLUSH(hw);
4896         return 0;
4897 }
4898
4899 static int
4900 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4901                         struct rte_eth_syn_filter *filter)
4902 {
4903         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4905
4906         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4907                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4908                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4909                 return 0;
4910         }
4911         return -ENOENT;
4912 }
4913
4914 static int
4915 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4916                         enum rte_filter_op filter_op,
4917                         void *arg)
4918 {
4919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4920         int ret;
4921
4922         MAC_TYPE_FILTER_SUP(hw->mac.type);
4923
4924         if (filter_op == RTE_ETH_FILTER_NOP)
4925                 return 0;
4926
4927         if (arg == NULL) {
4928                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4929                             filter_op);
4930                 return -EINVAL;
4931         }
4932
4933         switch (filter_op) {
4934         case RTE_ETH_FILTER_ADD:
4935                 ret = ixgbe_syn_filter_set(dev,
4936                                 (struct rte_eth_syn_filter *)arg,
4937                                 TRUE);
4938                 break;
4939         case RTE_ETH_FILTER_DELETE:
4940                 ret = ixgbe_syn_filter_set(dev,
4941                                 (struct rte_eth_syn_filter *)arg,
4942                                 FALSE);
4943                 break;
4944         case RTE_ETH_FILTER_GET:
4945                 ret = ixgbe_syn_filter_get(dev,
4946                                 (struct rte_eth_syn_filter *)arg);
4947                 break;
4948         default:
4949                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4950                 ret = -EINVAL;
4951                 break;
4952         }
4953
4954         return ret;
4955 }
4956
4957
4958 static inline enum ixgbe_5tuple_protocol
4959 convert_protocol_type(uint8_t protocol_value)
4960 {
4961         if (protocol_value == IPPROTO_TCP)
4962                 return IXGBE_FILTER_PROTOCOL_TCP;
4963         else if (protocol_value == IPPROTO_UDP)
4964                 return IXGBE_FILTER_PROTOCOL_UDP;
4965         else if (protocol_value == IPPROTO_SCTP)
4966                 return IXGBE_FILTER_PROTOCOL_SCTP;
4967         else
4968                 return IXGBE_FILTER_PROTOCOL_NONE;
4969 }
4970
4971 /*
4972  * add a 5tuple filter
4973  *
4974  * @param
4975  * dev: Pointer to struct rte_eth_dev.
4976  * index: the index the filter allocates.
4977  * filter: ponter to the filter that will be added.
4978  * rx_queue: the queue id the filter assigned to.
4979  *
4980  * @return
4981  *    - On success, zero.
4982  *    - On failure, a negative value.
4983  */
4984 static int
4985 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4986                         struct ixgbe_5tuple_filter *filter)
4987 {
4988         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4989         struct ixgbe_filter_info *filter_info =
4990                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4991         int i, idx, shift;
4992         uint32_t ftqf, sdpqf;
4993         uint32_t l34timir = 0;
4994         uint8_t mask = 0xff;
4995
4996         /*
4997          * look for an unused 5tuple filter index,
4998          * and insert the filter to list.
4999          */
5000         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5001                 idx = i / (sizeof(uint32_t) * NBBY);
5002                 shift = i % (sizeof(uint32_t) * NBBY);
5003                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5004                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5005                         filter->index = i;
5006                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5007                                           filter,
5008                                           entries);
5009                         break;
5010                 }
5011         }
5012         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5013                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5014                 return -ENOSYS;
5015         }
5016
5017         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5018                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5019         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5020
5021         ftqf = (uint32_t)(filter->filter_info.proto &
5022                 IXGBE_FTQF_PROTOCOL_MASK);
5023         ftqf |= (uint32_t)((filter->filter_info.priority &
5024                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5025         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5026                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5027         if (filter->filter_info.dst_ip_mask == 0)
5028                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5029         if (filter->filter_info.src_port_mask == 0)
5030                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5031         if (filter->filter_info.dst_port_mask == 0)
5032                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5033         if (filter->filter_info.proto_mask == 0)
5034                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5035         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5036         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5037         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5038
5039         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5040         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5041         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5042         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5043
5044         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5045         l34timir |= (uint32_t)(filter->queue <<
5046                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5047         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5048         return 0;
5049 }
5050
5051 /*
5052  * remove a 5tuple filter
5053  *
5054  * @param
5055  * dev: Pointer to struct rte_eth_dev.
5056  * filter: the pointer of the filter will be removed.
5057  */
5058 static void
5059 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5060                         struct ixgbe_5tuple_filter *filter)
5061 {
5062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063         struct ixgbe_filter_info *filter_info =
5064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5065         uint16_t index = filter->index;
5066
5067         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5068                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5069         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5070         rte_free(filter);
5071
5072         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5073         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5074         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5075         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5076         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5077 }
5078
5079 static int
5080 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5081 {
5082         struct ixgbe_hw *hw;
5083         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5084
5085         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5086
5087         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5088                 return -EINVAL;
5089
5090         /* refuse mtu that requires the support of scattered packets when this
5091          * feature has not been enabled before. */
5092         if (!dev->data->scattered_rx &&
5093             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5094              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5095                 return -EINVAL;
5096
5097         /*
5098          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5099          * request of the version 2.0 of the mailbox API.
5100          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5101          * of the mailbox API.
5102          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5103          * prior to 3.11.33 which contains the following change:
5104          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5105          */
5106         ixgbevf_rlpml_set_vf(hw, max_frame);
5107
5108         /* update max frame size */
5109         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5110         return 0;
5111 }
5112
5113 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5114         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5115                 return -ENOTSUP;\
5116 } while (0)
5117
5118 static inline struct ixgbe_5tuple_filter *
5119 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5120                         struct ixgbe_5tuple_filter_info *key)
5121 {
5122         struct ixgbe_5tuple_filter *it;
5123
5124         TAILQ_FOREACH(it, filter_list, entries) {
5125                 if (memcmp(key, &it->filter_info,
5126                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5127                         return it;
5128                 }
5129         }
5130         return NULL;
5131 }
5132
5133 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5134 static inline int
5135 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5136                         struct ixgbe_5tuple_filter_info *filter_info)
5137 {
5138         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5139                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5140                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5141                 return -EINVAL;
5142
5143         switch (filter->dst_ip_mask) {
5144         case UINT32_MAX:
5145                 filter_info->dst_ip_mask = 0;
5146                 filter_info->dst_ip = filter->dst_ip;
5147                 break;
5148         case 0:
5149                 filter_info->dst_ip_mask = 1;
5150                 break;
5151         default:
5152                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5153                 return -EINVAL;
5154         }
5155
5156         switch (filter->src_ip_mask) {
5157         case UINT32_MAX:
5158                 filter_info->src_ip_mask = 0;
5159                 filter_info->src_ip = filter->src_ip;
5160                 break;
5161         case 0:
5162                 filter_info->src_ip_mask = 1;
5163                 break;
5164         default:
5165                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5166                 return -EINVAL;
5167         }
5168
5169         switch (filter->dst_port_mask) {
5170         case UINT16_MAX:
5171                 filter_info->dst_port_mask = 0;
5172                 filter_info->dst_port = filter->dst_port;
5173                 break;
5174         case 0:
5175                 filter_info->dst_port_mask = 1;
5176                 break;
5177         default:
5178                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5179                 return -EINVAL;
5180         }
5181
5182         switch (filter->src_port_mask) {
5183         case UINT16_MAX:
5184                 filter_info->src_port_mask = 0;
5185                 filter_info->src_port = filter->src_port;
5186                 break;
5187         case 0:
5188                 filter_info->src_port_mask = 1;
5189                 break;
5190         default:
5191                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5192                 return -EINVAL;
5193         }
5194
5195         switch (filter->proto_mask) {
5196         case UINT8_MAX:
5197                 filter_info->proto_mask = 0;
5198                 filter_info->proto =
5199                         convert_protocol_type(filter->proto);
5200                 break;
5201         case 0:
5202                 filter_info->proto_mask = 1;
5203                 break;
5204         default:
5205                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5206                 return -EINVAL;
5207         }
5208
5209         filter_info->priority = (uint8_t)filter->priority;
5210         return 0;
5211 }
5212
5213 /*
5214  * add or delete a ntuple filter
5215  *
5216  * @param
5217  * dev: Pointer to struct rte_eth_dev.
5218  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5219  * add: if true, add filter, if false, remove filter
5220  *
5221  * @return
5222  *    - On success, zero.
5223  *    - On failure, a negative value.
5224  */
5225 static int
5226 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5227                         struct rte_eth_ntuple_filter *ntuple_filter,
5228                         bool add)
5229 {
5230         struct ixgbe_filter_info *filter_info =
5231                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5232         struct ixgbe_5tuple_filter_info filter_5tuple;
5233         struct ixgbe_5tuple_filter *filter;
5234         int ret;
5235
5236         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5237                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5238                 return -EINVAL;
5239         }
5240
5241         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5242         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5243         if (ret < 0)
5244                 return ret;
5245
5246         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5247                                          &filter_5tuple);
5248         if (filter != NULL && add) {
5249                 PMD_DRV_LOG(ERR, "filter exists.");
5250                 return -EEXIST;
5251         }
5252         if (filter == NULL && !add) {
5253                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5254                 return -ENOENT;
5255         }
5256
5257         if (add) {
5258                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5259                                 sizeof(struct ixgbe_5tuple_filter), 0);
5260                 if (filter == NULL)
5261                         return -ENOMEM;
5262                 (void)rte_memcpy(&filter->filter_info,
5263                                  &filter_5tuple,
5264                                  sizeof(struct ixgbe_5tuple_filter_info));
5265                 filter->queue = ntuple_filter->queue;
5266                 ret = ixgbe_add_5tuple_filter(dev, filter);
5267                 if (ret < 0) {
5268                         rte_free(filter);
5269                         return ret;
5270                 }
5271         } else
5272                 ixgbe_remove_5tuple_filter(dev, filter);
5273
5274         return 0;
5275 }
5276
5277 /*
5278  * get a ntuple filter
5279  *
5280  * @param
5281  * dev: Pointer to struct rte_eth_dev.
5282  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5283  *
5284  * @return
5285  *    - On success, zero.
5286  *    - On failure, a negative value.
5287  */
5288 static int
5289 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5290                         struct rte_eth_ntuple_filter *ntuple_filter)
5291 {
5292         struct ixgbe_filter_info *filter_info =
5293                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5294         struct ixgbe_5tuple_filter_info filter_5tuple;
5295         struct ixgbe_5tuple_filter *filter;
5296         int ret;
5297
5298         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5299                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5300                 return -EINVAL;
5301         }
5302
5303         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5304         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5305         if (ret < 0)
5306                 return ret;
5307
5308         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5309                                          &filter_5tuple);
5310         if (filter == NULL) {
5311                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5312                 return -ENOENT;
5313         }
5314         ntuple_filter->queue = filter->queue;
5315         return 0;
5316 }
5317
5318 /*
5319  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5320  * @dev: pointer to rte_eth_dev structure
5321  * @filter_op:operation will be taken.
5322  * @arg: a pointer to specific structure corresponding to the filter_op
5323  *
5324  * @return
5325  *    - On success, zero.
5326  *    - On failure, a negative value.
5327  */
5328 static int
5329 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5330                                 enum rte_filter_op filter_op,
5331                                 void *arg)
5332 {
5333         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5334         int ret;
5335
5336         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5337
5338         if (filter_op == RTE_ETH_FILTER_NOP)
5339                 return 0;
5340
5341         if (arg == NULL) {
5342                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5343                             filter_op);
5344                 return -EINVAL;
5345         }
5346
5347         switch (filter_op) {
5348         case RTE_ETH_FILTER_ADD:
5349                 ret = ixgbe_add_del_ntuple_filter(dev,
5350                         (struct rte_eth_ntuple_filter *)arg,
5351                         TRUE);
5352                 break;
5353         case RTE_ETH_FILTER_DELETE:
5354                 ret = ixgbe_add_del_ntuple_filter(dev,
5355                         (struct rte_eth_ntuple_filter *)arg,
5356                         FALSE);
5357                 break;
5358         case RTE_ETH_FILTER_GET:
5359                 ret = ixgbe_get_ntuple_filter(dev,
5360                         (struct rte_eth_ntuple_filter *)arg);
5361                 break;
5362         default:
5363                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5364                 ret = -EINVAL;
5365                 break;
5366         }
5367         return ret;
5368 }
5369
5370 static inline int
5371 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5372                         uint16_t ethertype)
5373 {
5374         int i;
5375
5376         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5377                 if (filter_info->ethertype_filters[i] == ethertype &&
5378                     (filter_info->ethertype_mask & (1 << i)))
5379                         return i;
5380         }
5381         return -1;
5382 }
5383
5384 static inline int
5385 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5386                         uint16_t ethertype)
5387 {
5388         int i;
5389
5390         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5391                 if (!(filter_info->ethertype_mask & (1 << i))) {
5392                         filter_info->ethertype_mask |= 1 << i;
5393                         filter_info->ethertype_filters[i] = ethertype;
5394                         return i;
5395                 }
5396         }
5397         return -1;
5398 }
5399
5400 static inline int
5401 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5402                         uint8_t idx)
5403 {
5404         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5405                 return -1;
5406         filter_info->ethertype_mask &= ~(1 << idx);
5407         filter_info->ethertype_filters[idx] = 0;
5408         return idx;
5409 }
5410
5411 static int
5412 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5413                         struct rte_eth_ethertype_filter *filter,
5414                         bool add)
5415 {
5416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5417         struct ixgbe_filter_info *filter_info =
5418                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5419         uint32_t etqf = 0;
5420         uint32_t etqs = 0;
5421         int ret;
5422
5423         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5424                 return -EINVAL;
5425
5426         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5427                 filter->ether_type == ETHER_TYPE_IPv6) {
5428                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5429                         " ethertype filter.", filter->ether_type);
5430                 return -EINVAL;
5431         }
5432
5433         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5434                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5435                 return -EINVAL;
5436         }
5437         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5438                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5439                 return -EINVAL;
5440         }
5441
5442         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5443         if (ret >= 0 && add) {
5444                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5445                             filter->ether_type);
5446                 return -EEXIST;
5447         }
5448         if (ret < 0 && !add) {
5449                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5450                             filter->ether_type);
5451                 return -ENOENT;
5452         }
5453
5454         if (add) {
5455                 ret = ixgbe_ethertype_filter_insert(filter_info,
5456                         filter->ether_type);
5457                 if (ret < 0) {
5458                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5459                         return -ENOSYS;
5460                 }
5461                 etqf = IXGBE_ETQF_FILTER_EN;
5462                 etqf |= (uint32_t)filter->ether_type;
5463                 etqs |= (uint32_t)((filter->queue <<
5464                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5465                                     IXGBE_ETQS_RX_QUEUE);
5466                 etqs |= IXGBE_ETQS_QUEUE_EN;
5467         } else {
5468                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5469                 if (ret < 0)
5470                         return -ENOSYS;
5471         }
5472         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5473         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5474         IXGBE_WRITE_FLUSH(hw);
5475
5476         return 0;
5477 }
5478
5479 static int
5480 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5481                         struct rte_eth_ethertype_filter *filter)
5482 {
5483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5484         struct ixgbe_filter_info *filter_info =
5485                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5486         uint32_t etqf, etqs;
5487         int ret;
5488
5489         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5490         if (ret < 0) {
5491                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5492                             filter->ether_type);
5493                 return -ENOENT;
5494         }
5495
5496         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5497         if (etqf & IXGBE_ETQF_FILTER_EN) {
5498                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5499                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5500                 filter->flags = 0;
5501                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5502                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5503                 return 0;
5504         }
5505         return -ENOENT;
5506 }
5507
5508 /*
5509  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5510  * @dev: pointer to rte_eth_dev structure
5511  * @filter_op:operation will be taken.
5512  * @arg: a pointer to specific structure corresponding to the filter_op
5513  */
5514 static int
5515 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5516                                 enum rte_filter_op filter_op,
5517                                 void *arg)
5518 {
5519         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5520         int ret;
5521
5522         MAC_TYPE_FILTER_SUP(hw->mac.type);
5523
5524         if (filter_op == RTE_ETH_FILTER_NOP)
5525                 return 0;
5526
5527         if (arg == NULL) {
5528                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5529                             filter_op);
5530                 return -EINVAL;
5531         }
5532
5533         switch (filter_op) {
5534         case RTE_ETH_FILTER_ADD:
5535                 ret = ixgbe_add_del_ethertype_filter(dev,
5536                         (struct rte_eth_ethertype_filter *)arg,
5537                         TRUE);
5538                 break;
5539         case RTE_ETH_FILTER_DELETE:
5540                 ret = ixgbe_add_del_ethertype_filter(dev,
5541                         (struct rte_eth_ethertype_filter *)arg,
5542                         FALSE);
5543                 break;
5544         case RTE_ETH_FILTER_GET:
5545                 ret = ixgbe_get_ethertype_filter(dev,
5546                         (struct rte_eth_ethertype_filter *)arg);
5547                 break;
5548         default:
5549                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5550                 ret = -EINVAL;
5551                 break;
5552         }
5553         return ret;
5554 }
5555
5556 static int
5557 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5558                      enum rte_filter_type filter_type,
5559                      enum rte_filter_op filter_op,
5560                      void *arg)
5561 {
5562         int ret = -EINVAL;
5563
5564         switch (filter_type) {
5565         case RTE_ETH_FILTER_NTUPLE:
5566                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5567                 break;
5568         case RTE_ETH_FILTER_ETHERTYPE:
5569                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5570                 break;
5571         case RTE_ETH_FILTER_SYN:
5572                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5573                 break;
5574         case RTE_ETH_FILTER_FDIR:
5575                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5576                 break;
5577         default:
5578                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5579                                                         filter_type);
5580                 break;
5581         }
5582
5583         return ret;
5584 }
5585
5586 static u8 *
5587 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5588                         u8 **mc_addr_ptr, u32 *vmdq)
5589 {
5590         u8 *mc_addr;
5591
5592         *vmdq = 0;
5593         mc_addr = *mc_addr_ptr;
5594         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5595         return mc_addr;
5596 }
5597
5598 static int
5599 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5600                           struct ether_addr *mc_addr_set,
5601                           uint32_t nb_mc_addr)
5602 {
5603         struct ixgbe_hw *hw;
5604         u8 *mc_addr_list;
5605
5606         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5607         mc_addr_list = (u8 *)mc_addr_set;
5608         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5609                                          ixgbe_dev_addr_list_itr, TRUE);
5610 }
5611
5612 static int
5613 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5614 {
5615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5616         uint32_t tsync_ctl;
5617         uint32_t tsauxc;
5618
5619         /* Enable system time for platforms where it isn't on by default. */
5620         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5621         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5622         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5623
5624         /* Start incrementing the register used to timestamp PTP packets. */
5625         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5626
5627         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5628         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5629                         (ETHER_TYPE_1588 |
5630                          IXGBE_ETQF_FILTER_EN |
5631                          IXGBE_ETQF_1588));
5632
5633         /* Enable timestamping of received PTP packets. */
5634         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5635         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5636         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5637
5638         /* Enable timestamping of transmitted PTP packets. */
5639         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5640         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5641         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5642
5643         return 0;
5644 }
5645
5646 static int
5647 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5648 {
5649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650         uint32_t tsync_ctl;
5651
5652         /* Disable timestamping of transmitted PTP packets. */
5653         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5654         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5655         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5656
5657         /* Disable timestamping of received PTP packets. */
5658         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5659         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5660         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5661
5662         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5663         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5664
5665         /* Stop incrementating the System Time registers. */
5666         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5667
5668         return 0;
5669 }
5670
5671 static int
5672 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5673                                  struct timespec *timestamp,
5674                                  uint32_t flags __rte_unused)
5675 {
5676         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5677         uint32_t tsync_rxctl;
5678         uint32_t rx_stmpl;
5679         uint32_t rx_stmph;
5680
5681         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5682         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5683                 return -EINVAL;
5684
5685         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5686         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5687
5688         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5689         timestamp->tv_nsec = 0;
5690
5691         return  0;
5692 }
5693
5694 static int
5695 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5696                                  struct timespec *timestamp)
5697 {
5698         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699         uint32_t tsync_txctl;
5700         uint32_t tx_stmpl;
5701         uint32_t tx_stmph;
5702
5703         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5704         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5705                 return -EINVAL;
5706
5707         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5708         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5709
5710         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5711         timestamp->tv_nsec = 0;
5712
5713         return  0;
5714 }
5715
5716 static int
5717 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5718 {
5719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5720         int count = 0;
5721         int g_ind = 0;
5722         const struct reg_info *reg_group;
5723         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5724                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5725
5726         while ((reg_group = reg_set[g_ind++]))
5727                 count += ixgbe_regs_group_count(reg_group);
5728
5729         return count;
5730 }
5731
5732 static int
5733 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5734 {
5735         int count = 0;
5736         int g_ind = 0;
5737         const struct reg_info *reg_group;
5738
5739         while ((reg_group = ixgbevf_regs[g_ind++]))
5740                 count += ixgbe_regs_group_count(reg_group);
5741
5742         return count;
5743 }
5744
5745 static int
5746 ixgbe_get_regs(struct rte_eth_dev *dev,
5747               struct rte_dev_reg_info *regs)
5748 {
5749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750         uint32_t *data = regs->data;
5751         int g_ind = 0;
5752         int count = 0;
5753         const struct reg_info *reg_group;
5754         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5755                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5756
5757         /* Support only full register dump */
5758         if ((regs->length == 0) ||
5759             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5760                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5761                         hw->device_id;
5762                 while ((reg_group = reg_set[g_ind++]))
5763                         count += ixgbe_read_regs_group(dev, &data[count],
5764                                 reg_group);
5765                 return 0;
5766         }
5767
5768         return -ENOTSUP;
5769 }
5770
5771 static int
5772 ixgbevf_get_regs(struct rte_eth_dev *dev,
5773                 struct rte_dev_reg_info *regs)
5774 {
5775         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5776         uint32_t *data = regs->data;
5777         int g_ind = 0;
5778         int count = 0;
5779         const struct reg_info *reg_group;
5780
5781         /* Support only full register dump */
5782         if ((regs->length == 0) ||
5783             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5784                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5785                         hw->device_id;
5786                 while ((reg_group = ixgbevf_regs[g_ind++]))
5787                         count += ixgbe_read_regs_group(dev, &data[count],
5788                                                       reg_group);
5789                 return 0;
5790         }
5791
5792         return -ENOTSUP;
5793 }
5794
5795 static int
5796 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5797 {
5798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5799
5800         /* Return unit is byte count */
5801         return hw->eeprom.word_size * 2;
5802 }
5803
5804 static int
5805 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5806                 struct rte_dev_eeprom_info *in_eeprom)
5807 {
5808         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5809         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5810         uint16_t *data = in_eeprom->data;
5811         int first, length;
5812
5813         first = in_eeprom->offset >> 1;
5814         length = in_eeprom->length >> 1;
5815         if ((first > hw->eeprom.word_size) ||
5816             ((first + length) > hw->eeprom.word_size))
5817                 return -EINVAL;
5818
5819         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5820
5821         return eeprom->ops.read_buffer(hw, first, length, data);
5822 }
5823
5824 static int
5825 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5826                 struct rte_dev_eeprom_info *in_eeprom)
5827 {
5828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5829         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5830         uint16_t *data = in_eeprom->data;
5831         int first, length;
5832
5833         first = in_eeprom->offset >> 1;
5834         length = in_eeprom->length >> 1;
5835         if ((first > hw->eeprom.word_size) ||
5836             ((first + length) > hw->eeprom.word_size))
5837                 return -EINVAL;
5838
5839         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5840
5841         return eeprom->ops.write_buffer(hw,  first, length, data);
5842 }
5843
5844 uint16_t
5845 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5846         switch (mac_type) {
5847         case ixgbe_mac_X550:
5848         case ixgbe_mac_X550EM_x:
5849                 return ETH_RSS_RETA_SIZE_512;
5850         case ixgbe_mac_X550_vf:
5851         case ixgbe_mac_X550EM_x_vf:
5852                 return ETH_RSS_RETA_SIZE_64;
5853         default:
5854                 return ETH_RSS_RETA_SIZE_128;
5855         }
5856 }
5857
5858 uint32_t
5859 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5860         switch (mac_type) {
5861         case ixgbe_mac_X550:
5862         case ixgbe_mac_X550EM_x:
5863                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5864                         return IXGBE_RETA(reta_idx >> 2);
5865                 else
5866                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5867         case ixgbe_mac_X550_vf:
5868         case ixgbe_mac_X550EM_x_vf:
5869                 return IXGBE_VFRETA(reta_idx >> 2);
5870         default:
5871                 return IXGBE_RETA(reta_idx >> 2);
5872         }
5873 }
5874
5875 uint32_t
5876 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5877         switch (mac_type) {
5878         case ixgbe_mac_X550_vf:
5879         case ixgbe_mac_X550EM_x_vf:
5880                 return IXGBE_VFMRQC;
5881         default:
5882                 return IXGBE_MRQC;
5883         }
5884 }
5885
5886 uint32_t
5887 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5888         switch (mac_type) {
5889         case ixgbe_mac_X550_vf:
5890         case ixgbe_mac_X550EM_x_vf:
5891                 return IXGBE_VFRSSRK(i);
5892         default:
5893                 return IXGBE_RSSRK(i);
5894         }
5895 }
5896
5897 bool
5898 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5899         switch (mac_type) {
5900         case ixgbe_mac_82599_vf:
5901         case ixgbe_mac_X540_vf:
5902                 return 0;
5903         default:
5904                 return 1;
5905         }
5906 }
5907
5908 static int
5909 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5910                         struct rte_eth_dcb_info *dcb_info)
5911 {
5912         struct ixgbe_dcb_config *dcb_config =
5913                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5914         struct ixgbe_dcb_tc_config *tc;
5915         uint8_t i, j;
5916
5917         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5918                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5919         else
5920                 dcb_info->nb_tcs = 1;
5921
5922         if (dcb_config->vt_mode) { /* vt is enabled*/
5923                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5924                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5925                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5926                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5927                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5928                         for (j = 0; j < dcb_info->nb_tcs; j++) {
5929                                 dcb_info->tc_queue.tc_rxq[i][j].base =
5930                                                 i * dcb_info->nb_tcs + j;
5931                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5932                                 dcb_info->tc_queue.tc_txq[i][j].base =
5933                                                 i * dcb_info->nb_tcs + j;
5934                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5935                         }
5936                 }
5937         } else { /* vt is disabled*/
5938                 struct rte_eth_dcb_rx_conf *rx_conf =
5939                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5940                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5941                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5942                 if (dcb_info->nb_tcs == ETH_4_TCS) {
5943                         for (i = 0; i < dcb_info->nb_tcs; i++) {
5944                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5945                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5946                         }
5947                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
5948                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
5949                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
5950                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
5951                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
5952                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5953                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5954                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5955                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
5956                         for (i = 0; i < dcb_info->nb_tcs; i++) {
5957                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
5958                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5959                         }
5960                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
5961                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
5962                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
5963                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
5964                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
5965                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
5966                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
5967                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
5968                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
5969                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5970                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5971                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5972                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
5973                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
5974                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
5975                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
5976                 }
5977         }
5978         for (i = 0; i < dcb_info->nb_tcs; i++) {
5979                 tc = &dcb_config->tc_config[i];
5980                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
5981         }
5982         return 0;
5983 }
5984
5985 static struct rte_driver rte_ixgbe_driver = {
5986         .type = PMD_PDEV,
5987         .init = rte_ixgbe_pmd_init,
5988 };
5989
5990 static struct rte_driver rte_ixgbevf_driver = {
5991         .type = PMD_PDEV,
5992         .init = rte_ixgbevf_pmd_init,
5993 };
5994
5995 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5996 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);