drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 233
 234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 235                         struct rte_ether_addr *mac_addr,
 236                         uint32_t index, uint32_t pool);
 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 239                                            struct rte_ether_addr *mac_addr);
 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 241 static bool is_device_supported(struct rte_eth_dev *dev,
 242                                 struct rte_pci_driver *drv);
 243
 244 /* For Virtual Function support */
 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 248 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 250                                    int wait_to_complete);
 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 277
 278 /* For Eth VMDQ APIs support */
 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 280                 rte_ether_addr * mac_addr, uint8_t on);
 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 283                 struct rte_eth_mirror_conf *mirror_conf,
 284                 uint8_t rule_id, uint8_t on);
 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 286                 uint8_t rule_id);
 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 288                                           uint16_t queue_id);
 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 290                                            uint16_t queue_id);
 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 292                                uint8_t queue, uint8_t msix_vector);
 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 294
 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 296                                 struct rte_ether_addr *mac_addr,
 297                                 uint32_t index, uint32_t pool);
 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 300                                              struct rte_ether_addr *mac_addr);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 311                                 enum rte_filter_op filter_op,
 312                                 void *arg);
 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 314                         struct rte_eth_ntuple_filter *filter);
 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter);
 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 321                      enum rte_filter_type filter_type,
 322                      enum rte_filter_op filter_op,
 323                      void *arg);
 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 325
 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 327                                       struct rte_ether_addr *mc_addr_set,
 328                                       uint32_t nb_mc_addr);
 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                    struct rte_eth_dcb_info *dcb_info);
 331
 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 334                             struct rte_dev_reg_info *regs);
 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340
 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 342                                  struct rte_eth_dev_module_info *modinfo);
 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 344                                    struct rte_dev_eeprom_info *info);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 382
 383 /*
 384  * Define VF Stats MACRO for Non "cleared on read" register
 385  */
 386 #define UPDATE_VF_STAT(reg, last, cur)                          \
 387 {                                                               \
 388         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 389         cur += (latest - last) & UINT_MAX;                      \
 390         last = latest;                                          \
 391 }
 392
 393 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 394 {                                                                \
 395         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 396         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 397         u64 latest = ((new_msb << 32) | new_lsb);                \
 398         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 399         last = latest;                                           \
 400 }
 401
 402 #define IXGBE_SET_HWSTRIP(h, q) do {\
 403                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 404                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 405                 (h)->bitmap[idx] |= 1 << bit;\
 406         } while (0)
 407
 408 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 409                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 410                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 411                 (h)->bitmap[idx] &= ~(1 << bit);\
 412         } while (0)
 413
 414 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (r) = (h)->bitmap[idx] >> bit & 1;\
 418         } while (0)
 419
 420 int ixgbe_logtype_init;
 421 int ixgbe_logtype_driver;
 422
 423 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
 424 int ixgbe_logtype_rx;
 425 #endif
 426 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
 427 int ixgbe_logtype_tx;
 428 #endif
 429 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 430 int ixgbe_logtype_tx_free;
 431 #endif
 432
 433 /*
 434  * The set of PCI devices this driver supports
 435  */
 436 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 485 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 487 #endif
 488         { .vendor_id = 0, /* sentinel */ },
 489 };
 490
 491 /*
 492  * The set of PCI devices this driver supports (for 82599 VF)
 493  */
 494 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 505         { .vendor_id = 0, /* sentinel */ },
 506 };
 507
 508 static const struct rte_eth_desc_lim rx_desc_lim = {
 509         .nb_max = IXGBE_MAX_RING_DESC,
 510         .nb_min = IXGBE_MIN_RING_DESC,
 511         .nb_align = IXGBE_RXD_ALIGN,
 512 };
 513
 514 static const struct rte_eth_desc_lim tx_desc_lim = {
 515         .nb_max = IXGBE_MAX_RING_DESC,
 516         .nb_min = IXGBE_MIN_RING_DESC,
 517         .nb_align = IXGBE_TXD_ALIGN,
 518         .nb_seg_max = IXGBE_TX_MAX_SEG,
 519         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 520 };
 521
 522 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 523         .dev_configure        = ixgbe_dev_configure,
 524         .dev_start            = ixgbe_dev_start,
 525         .dev_stop             = ixgbe_dev_stop,
 526         .dev_set_link_up    = ixgbe_dev_set_link_up,
 527         .dev_set_link_down  = ixgbe_dev_set_link_down,
 528         .dev_close            = ixgbe_dev_close,
 529         .dev_reset            = ixgbe_dev_reset,
 530         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 531         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 532         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 533         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 534         .link_update          = ixgbe_dev_link_update,
 535         .stats_get            = ixgbe_dev_stats_get,
 536         .xstats_get           = ixgbe_dev_xstats_get,
 537         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 538         .stats_reset          = ixgbe_dev_stats_reset,
 539         .xstats_reset         = ixgbe_dev_xstats_reset,
 540         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 541         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 542         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 543         .fw_version_get       = ixgbe_fw_version_get,
 544         .dev_infos_get        = ixgbe_dev_info_get,
 545         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 546         .mtu_set              = ixgbe_dev_mtu_set,
 547         .vlan_filter_set      = ixgbe_vlan_filter_set,
 548         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 549         .vlan_offload_set     = ixgbe_vlan_offload_set,
 550         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 551         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 552         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 553         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 554         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 555         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 556         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 557         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 558         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 559         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 560         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 561         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 562         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 563         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 564         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 565         .dev_led_on           = ixgbe_dev_led_on,
 566         .dev_led_off          = ixgbe_dev_led_off,
 567         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 568         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 569         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 570         .mac_addr_add         = ixgbe_add_rar,
 571         .mac_addr_remove      = ixgbe_remove_rar,
 572         .mac_addr_set         = ixgbe_set_default_mac_addr,
 573         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 574         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 575         .mirror_rule_set      = ixgbe_mirror_rule_set,
 576         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 577         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 578         .reta_update          = ixgbe_dev_rss_reta_update,
 579         .reta_query           = ixgbe_dev_rss_reta_query,
 580         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 581         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 582         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 583         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 584         .rxq_info_get         = ixgbe_rxq_info_get,
 585         .txq_info_get         = ixgbe_txq_info_get,
 586         .timesync_enable      = ixgbe_timesync_enable,
 587         .timesync_disable     = ixgbe_timesync_disable,
 588         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 589         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 590         .get_reg              = ixgbe_get_regs,
 591         .get_eeprom_length    = ixgbe_get_eeprom_length,
 592         .get_eeprom           = ixgbe_get_eeprom,
 593         .set_eeprom           = ixgbe_set_eeprom,
 594         .get_module_info      = ixgbe_get_module_info,
 595         .get_module_eeprom    = ixgbe_get_module_eeprom,
 596         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 597         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 598         .timesync_read_time   = ixgbe_timesync_read_time,
 599         .timesync_write_time  = ixgbe_timesync_write_time,
 600         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 601         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 602         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 603         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 604         .tm_ops_get           = ixgbe_tm_ops_get,
 605 };
 606
 607 /*
 608  * dev_ops for virtual function, bare necessities for basic vf
 609  * operation have been implemented
 610  */
 611 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 612         .dev_configure        = ixgbevf_dev_configure,
 613         .dev_start            = ixgbevf_dev_start,
 614         .dev_stop             = ixgbevf_dev_stop,
 615         .link_update          = ixgbevf_dev_link_update,
 616         .stats_get            = ixgbevf_dev_stats_get,
 617         .xstats_get           = ixgbevf_dev_xstats_get,
 618         .stats_reset          = ixgbevf_dev_stats_reset,
 619         .xstats_reset         = ixgbevf_dev_stats_reset,
 620         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 621         .dev_close            = ixgbevf_dev_close,
 622         .dev_reset            = ixgbevf_dev_reset,
 623         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 624         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 625         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 626         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 627         .dev_infos_get        = ixgbevf_dev_info_get,
 628         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 629         .mtu_set              = ixgbevf_dev_set_mtu,
 630         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 631         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 632         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 633         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 634         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 635         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 636         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 637         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 638         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 639         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 640         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 641         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 642         .mac_addr_add         = ixgbevf_add_mac_addr,
 643         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 644         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 645         .rxq_info_get         = ixgbe_rxq_info_get,
 646         .txq_info_get         = ixgbe_txq_info_get,
 647         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 648         .get_reg              = ixgbevf_get_regs,
 649         .reta_update          = ixgbe_dev_rss_reta_update,
 650         .reta_query           = ixgbe_dev_rss_reta_query,
 651         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 652         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 653 };
 654
 655 /* store statistics names and its offset in stats structure */
 656 struct rte_ixgbe_xstats_name_off {
 657         char name[RTE_ETH_XSTATS_NAME_SIZE];
 658         unsigned offset;
 659 };
 660
 661 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 662         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 663         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 664         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 665         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 666         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 667         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 668         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 669         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 670         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 671         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 672         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 673         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 674         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 675         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 676         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 677                 prc1023)},
 678         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 679                 prc1522)},
 680         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 681         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 682         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 683         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 684         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 685         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 686         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 687         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 688         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 689         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 690         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 691         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 692         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 693         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 694         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 695         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 696         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 697                 ptc1023)},
 698         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 699                 ptc1522)},
 700         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 701         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 702         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 703         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 704
 705         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 706                 fdirustat_add)},
 707         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 708                 fdirustat_remove)},
 709         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 710                 fdirfstat_fadd)},
 711         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 712                 fdirfstat_fremove)},
 713         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 714                 fdirmatch)},
 715         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 716                 fdirmiss)},
 717
 718         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 719         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 720         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 721                 fclast)},
 722         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 723         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 724         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 725         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 726         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 727                 fcoe_noddp)},
 728         {"rx_fcoe_no_direct_data_placement_ext_buff",
 729                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 730
 731         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxontxc)},
 733         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxonrxc)},
 735         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxofftxc)},
 737         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxoffrxc)},
 739         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 740 };
 741
 742 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 743                            sizeof(rte_ixgbe_stats_strings[0]))
 744
 745 /* MACsec statistics */
 746 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 747         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 748                 out_pkts_untagged)},
 749         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 750                 out_pkts_encrypted)},
 751         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 752                 out_pkts_protected)},
 753         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 754                 out_octets_encrypted)},
 755         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 756                 out_octets_protected)},
 757         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_untagged)},
 759         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_badtag)},
 761         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_nosci)},
 763         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_unknownsci)},
 765         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 766                 in_octets_decrypted)},
 767         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 768                 in_octets_validated)},
 769         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_unchecked)},
 771         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_delayed)},
 773         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_late)},
 775         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_ok)},
 777         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_invalid)},
 779         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_notvalid)},
 781         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_unusedsa)},
 783         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 784                 in_pkts_notusingsa)},
 785 };
 786
 787 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 788                            sizeof(rte_ixgbe_macsec_strings[0]))
 789
 790 /* Per-queue statistics */
 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 792         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 793         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 794         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 795         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 796 };
 797
 798 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 799                            sizeof(rte_ixgbe_rxq_strings[0]))
 800 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 801
 802 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 803         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 804         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 805         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 806                 pxon2offc)},
 807 };
 808
 809 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 810                            sizeof(rte_ixgbe_txq_strings[0]))
 811 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 812
 813 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 814         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 815 };
 816
 817 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 818                 sizeof(rte_ixgbevf_stats_strings[0]))
 819
 820 /*
 821  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 822  */
 823 static inline int
 824 ixgbe_is_sfp(struct ixgbe_hw *hw)
 825 {
 826         switch (hw->phy.type) {
 827         case ixgbe_phy_sfp_avago:
 828         case ixgbe_phy_sfp_ftl:
 829         case ixgbe_phy_sfp_intel:
 830         case ixgbe_phy_sfp_unknown:
 831         case ixgbe_phy_sfp_passive_tyco:
 832         case ixgbe_phy_sfp_passive_unknown:
 833                 return 1;
 834         default:
 835                 return 0;
 836         }
 837 }
 838
 839 static inline int32_t
 840 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 841 {
 842         uint32_t ctrl_ext;
 843         int32_t status;
 844
 845         status = ixgbe_reset_hw(hw);
 846
 847         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 848         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 849         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 850         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 851         IXGBE_WRITE_FLUSH(hw);
 852
 853         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 854                 status = IXGBE_SUCCESS;
 855         return status;
 856 }
 857
 858 static inline void
 859 ixgbe_enable_intr(struct rte_eth_dev *dev)
 860 {
 861         struct ixgbe_interrupt *intr =
 862                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 863         struct ixgbe_hw *hw =
 864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 865
 866         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 867         IXGBE_WRITE_FLUSH(hw);
 868 }
 869
 870 /*
 871  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 872  */
 873 static void
 874 ixgbe_disable_intr(struct ixgbe_hw *hw)
 875 {
 876         PMD_INIT_FUNC_TRACE();
 877
 878         if (hw->mac.type == ixgbe_mac_82598EB) {
 879                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 880         } else {
 881                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 882                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 883                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 884         }
 885         IXGBE_WRITE_FLUSH(hw);
 886 }
 887
 888 /*
 889  * This function resets queue statistics mapping registers.
 890  * From Niantic datasheet, Initialization of Statistics section:
 891  * "...if software requires the queue counters, the RQSMR and TQSM registers
 892  * must be re-programmed following a device reset.
 893  */
 894 static void
 895 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 896 {
 897         uint32_t i;
 898
 899         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 900                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 901                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 902         }
 903 }
 904
 905
 906 static int
 907 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 908                                   uint16_t queue_id,
 909                                   uint8_t stat_idx,
 910                                   uint8_t is_rx)
 911 {
 912 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 913 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 914 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 915
 916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 917         struct ixgbe_stat_mapping_registers *stat_mappings =
 918                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 919         uint32_t qsmr_mask = 0;
 920         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 921         uint32_t q_map;
 922         uint8_t n, offset;
 923
 924         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 925                 (hw->mac.type != ixgbe_mac_X540) &&
 926                 (hw->mac.type != ixgbe_mac_X550) &&
 927                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 928                 (hw->mac.type != ixgbe_mac_X550EM_a))
 929                 return -ENOSYS;
 930
 931         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934
 935         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 936         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 937                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 938                 return -EIO;
 939         }
 940         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 941
 942         /* Now clear any previous stat_idx set */
 943         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 944         if (!is_rx)
 945                 stat_mappings->tqsm[n] &= ~clearing_mask;
 946         else
 947                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 948
 949         q_map = (uint32_t)stat_idx;
 950         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 951         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 952         if (!is_rx)
 953                 stat_mappings->tqsm[n] |= qsmr_mask;
 954         else
 955                 stat_mappings->rqsmr[n] |= qsmr_mask;
 956
 957         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 958                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 959                      queue_id, stat_idx);
 960         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 961                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 962
 963         /* Now write the mapping in the appropriate register */
 964         if (is_rx) {
 965                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 966                              stat_mappings->rqsmr[n], n);
 967                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 968         } else {
 969                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 970                              stat_mappings->tqsm[n], n);
 971                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 972         }
 973         return 0;
 974 }
 975
 976 static void
 977 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 978 {
 979         struct ixgbe_stat_mapping_registers *stat_mappings =
 980                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 982         int i;
 983
 984         /* write whatever was in stat mapping table to the NIC */
 985         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 986                 /* rx */
 987                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 988
 989                 /* tx */
 990                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 991         }
 992 }
 993
 994 static void
 995 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 996 {
 997         uint8_t i;
 998         struct ixgbe_dcb_tc_config *tc;
 999         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1000
1001         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1002         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1003         for (i = 0; i < dcb_max_tc; i++) {
1004                 tc = &dcb_config->tc_config[i];
1005                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1006                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1007                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1008                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1009                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1010                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1011                 tc->pfc = ixgbe_dcb_pfc_disabled;
1012         }
1013
1014         /* Initialize default user to priority mapping, UPx->TC0 */
1015         tc = &dcb_config->tc_config[0];
1016         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1017         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1018         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1019                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1020                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1021         }
1022         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1023         dcb_config->pfc_mode_enable = false;
1024         dcb_config->vt_mode = true;
1025         dcb_config->round_robin_enable = false;
1026         /* support all DCB capabilities in 82599 */
1027         dcb_config->support.capabilities = 0xFF;
1028
1029         /*we only support 4 Tcs for X540, X550 */
1030         if (hw->mac.type == ixgbe_mac_X540 ||
1031                 hw->mac.type == ixgbe_mac_X550 ||
1032                 hw->mac.type == ixgbe_mac_X550EM_x ||
1033                 hw->mac.type == ixgbe_mac_X550EM_a) {
1034                 dcb_config->num_tcs.pg_tcs = 4;
1035                 dcb_config->num_tcs.pfc_tcs = 4;
1036         }
1037 }
1038
1039 /*
1040  * Ensure that all locks are released before first NVM or PHY access
1041  */
1042 static void
1043 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1044 {
1045         uint16_t mask;
1046
1047         /*
1048          * Phy lock should not fail in this early stage. If this is the case,
1049          * it is due to an improper exit of the application.
1050          * So force the release of the faulty lock. Release of common lock
1051          * is done automatically by swfw_sync function.
1052          */
1053         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1054         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1055                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1056         }
1057         ixgbe_release_swfw_semaphore(hw, mask);
1058
1059         /*
1060          * These ones are more tricky since they are common to all ports; but
1061          * swfw_sync retries last long enough (1s) to be almost sure that if
1062          * lock can not be taken it is due to an improper lock of the
1063          * semaphore.
1064          */
1065         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1066         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1067                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1068         }
1069         ixgbe_release_swfw_semaphore(hw, mask);
1070 }
1071
1072 /*
1073  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1074  * It returns 0 on success.
1075  */
1076 static int
1077 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1078 {
1079         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1080         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1081         struct ixgbe_hw *hw =
1082                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1083         struct ixgbe_vfta *shadow_vfta =
1084                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1085         struct ixgbe_hwstrip *hwstrip =
1086                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1087         struct ixgbe_dcb_config *dcb_config =
1088                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1089         struct ixgbe_filter_info *filter_info =
1090                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1091         struct ixgbe_bw_conf *bw_conf =
1092                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1093         uint32_t ctrl_ext;
1094         uint16_t csum;
1095         int diag, i;
1096
1097         PMD_INIT_FUNC_TRACE();
1098
1099         ixgbe_dev_macsec_setting_reset(eth_dev);
1100
1101         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1102         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1103         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1104         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1105
1106         /*
1107          * For secondary processes, we don't initialise any further as primary
1108          * has already done this work. Only check we don't need a different
1109          * RX and TX function.
1110          */
1111         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1112                 struct ixgbe_tx_queue *txq;
1113                 /* TX queue function in primary, set by last queue initialized
1114                  * Tx queue may not initialized by primary process
1115                  */
1116                 if (eth_dev->data->tx_queues) {
1117                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1118                         ixgbe_set_tx_function(eth_dev, txq);
1119                 } else {
1120                         /* Use default TX function if we get here */
1121                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1122                                      "Using default TX function.");
1123                 }
1124
1125                 ixgbe_set_rx_function(eth_dev);
1126
1127                 return 0;
1128         }
1129
1130         rte_eth_copy_pci_info(eth_dev, pci_dev);
1131
1132         /* Vendor and Device ID need to be set before init of shared code */
1133         hw->device_id = pci_dev->id.device_id;
1134         hw->vendor_id = pci_dev->id.vendor_id;
1135         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1136         hw->allow_unsupported_sfp = 1;
1137
1138         /* Initialize the shared code (base driver) */
1139 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1140         diag = ixgbe_bypass_init_shared_code(hw);
1141 #else
1142         diag = ixgbe_init_shared_code(hw);
1143 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1144
1145         if (diag != IXGBE_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1147                 return -EIO;
1148         }
1149
1150         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1151                 PMD_INIT_LOG(ERR, "\nERROR: "
1152                         "Firmware recovery mode detected. Limiting functionality.\n"
1153                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1154                         "User Guide for details on firmware recovery mode.");
1155                 return -EIO;
1156         }
1157
1158         /* pick up the PCI bus settings for reporting later */
1159         ixgbe_get_bus_info(hw);
1160
1161         /* Unlock any pending hardware semaphore */
1162         ixgbe_swfw_lock_reset(hw);
1163
1164 #ifdef RTE_LIBRTE_SECURITY
1165         /* Initialize security_ctx only for primary process*/
1166         if (ixgbe_ipsec_ctx_create(eth_dev))
1167                 return -ENOMEM;
1168 #endif
1169
1170         /* Initialize DCB configuration*/
1171         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1172         ixgbe_dcb_init(hw, dcb_config);
1173         /* Get Hardware Flow Control setting */
1174         hw->fc.requested_mode = ixgbe_fc_full;
1175         hw->fc.current_mode = ixgbe_fc_full;
1176         hw->fc.pause_time = IXGBE_FC_PAUSE;
1177         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1178                 hw->fc.low_water[i] = IXGBE_FC_LO;
1179                 hw->fc.high_water[i] = IXGBE_FC_HI;
1180         }
1181         hw->fc.send_xon = 1;
1182
1183         /* Make sure we have a good EEPROM before we read from it */
1184         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1185         if (diag != IXGBE_SUCCESS) {
1186                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1187                 return -EIO;
1188         }
1189
1190 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1191         diag = ixgbe_bypass_init_hw(hw);
1192 #else
1193         diag = ixgbe_init_hw(hw);
1194         hw->mac.autotry_restart = false;
1195 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1196
1197         /*
1198          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1199          * is called too soon after the kernel driver unbinding/binding occurs.
1200          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1201          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1202          * also called. See ixgbe_identify_phy_82599(). The reason for the
1203          * failure is not known, and only occuts when virtualisation features
1204          * are disabled in the bios. A delay of 100ms  was found to be enough by
1205          * trial-and-error, and is doubled to be safe.
1206          */
1207         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1208                 rte_delay_ms(200);
1209                 diag = ixgbe_init_hw(hw);
1210         }
1211
1212         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1213                 diag = IXGBE_SUCCESS;
1214
1215         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1216                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1217                              "LOM.  Please be aware there may be issues associated "
1218                              "with your hardware.");
1219                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1220                              "please contact your Intel or hardware representative "
1221                              "who provided you with this hardware.");
1222         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1223                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1224         if (diag) {
1225                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1226                 return -EIO;
1227         }
1228
1229         /* Reset the hw statistics */
1230         ixgbe_dev_stats_reset(eth_dev);
1231
1232         /* disable interrupt */
1233         ixgbe_disable_intr(hw);
1234
1235         /* reset mappings for queue statistics hw counters*/
1236         ixgbe_reset_qstat_mappings(hw);
1237
1238         /* Allocate memory for storing MAC addresses */
1239         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1240                                                hw->mac.num_rar_entries, 0);
1241         if (eth_dev->data->mac_addrs == NULL) {
1242                 PMD_INIT_LOG(ERR,
1243                              "Failed to allocate %u bytes needed to store "
1244                              "MAC addresses",
1245                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1246                 return -ENOMEM;
1247         }
1248         /* Copy the permanent MAC address */
1249         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1250                         &eth_dev->data->mac_addrs[0]);
1251
1252         /* Allocate memory for storing hash filter MAC addresses */
1253         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1254                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1255         if (eth_dev->data->hash_mac_addrs == NULL) {
1256                 PMD_INIT_LOG(ERR,
1257                              "Failed to allocate %d bytes needed to store MAC addresses",
1258                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1259                 return -ENOMEM;
1260         }
1261
1262         /* Pass the information to the rte_eth_dev_close() that it should also
1263          * release the private port resources.
1264          */
1265         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1266
1267         /* initialize the vfta */
1268         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1269
1270         /* initialize the hw strip bitmap*/
1271         memset(hwstrip, 0, sizeof(*hwstrip));
1272
1273         /* initialize PF if max_vfs not zero */
1274         ixgbe_pf_host_init(eth_dev);
1275
1276         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1277         /* let hardware know driver is loaded */
1278         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1279         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1280         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1281         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1282         IXGBE_WRITE_FLUSH(hw);
1283
1284         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1285                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1286                              (int) hw->mac.type, (int) hw->phy.type,
1287                              (int) hw->phy.sfp_type);
1288         else
1289                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1290                              (int) hw->mac.type, (int) hw->phy.type);
1291
1292         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1293                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1294                      pci_dev->id.device_id);
1295
1296         rte_intr_callback_register(intr_handle,
1297                                    ixgbe_dev_interrupt_handler, eth_dev);
1298
1299         /* enable uio/vfio intr/eventfd mapping */
1300         rte_intr_enable(intr_handle);
1301
1302         /* enable support intr */
1303         ixgbe_enable_intr(eth_dev);
1304
1305         ixgbe_dev_set_link_down(eth_dev);
1306
1307         /* initialize filter info */
1308         memset(filter_info, 0,
1309                sizeof(struct ixgbe_filter_info));
1310
1311         /* initialize 5tuple filter list */
1312         TAILQ_INIT(&filter_info->fivetuple_list);
1313
1314         /* initialize flow director filter list & hash */
1315         ixgbe_fdir_filter_init(eth_dev);
1316
1317         /* initialize l2 tunnel filter list & hash */
1318         ixgbe_l2_tn_filter_init(eth_dev);
1319
1320         /* initialize flow filter lists */
1321         ixgbe_filterlist_init();
1322
1323         /* initialize bandwidth configuration info */
1324         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1325
1326         /* initialize Traffic Manager configuration */
1327         ixgbe_tm_conf_init(eth_dev);
1328
1329         return 0;
1330 }
1331
1332 static int
1333 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1334 {
1335         PMD_INIT_FUNC_TRACE();
1336
1337         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1338                 return 0;
1339
1340         ixgbe_dev_close(eth_dev);
1341
1342         return 0;
1343 }
1344
1345 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1346 {
1347         struct ixgbe_filter_info *filter_info =
1348                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1349         struct ixgbe_5tuple_filter *p_5tuple;
1350
1351         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1352                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1353                              p_5tuple,
1354                              entries);
1355                 rte_free(p_5tuple);
1356         }
1357         memset(filter_info->fivetuple_mask, 0,
1358                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1359
1360         return 0;
1361 }
1362
1363 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1364 {
1365         struct ixgbe_hw_fdir_info *fdir_info =
1366                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1367         struct ixgbe_fdir_filter *fdir_filter;
1368
1369                 if (fdir_info->hash_map)
1370                 rte_free(fdir_info->hash_map);
1371         if (fdir_info->hash_handle)
1372                 rte_hash_free(fdir_info->hash_handle);
1373
1374         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1375                 TAILQ_REMOVE(&fdir_info->fdir_list,
1376                              fdir_filter,
1377                              entries);
1378                 rte_free(fdir_filter);
1379         }
1380
1381         return 0;
1382 }
1383
1384 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1385 {
1386         struct ixgbe_l2_tn_info *l2_tn_info =
1387                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1388         struct ixgbe_l2_tn_filter *l2_tn_filter;
1389
1390         if (l2_tn_info->hash_map)
1391                 rte_free(l2_tn_info->hash_map);
1392         if (l2_tn_info->hash_handle)
1393                 rte_hash_free(l2_tn_info->hash_handle);
1394
1395         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1396                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1397                              l2_tn_filter,
1398                              entries);
1399                 rte_free(l2_tn_filter);
1400         }
1401
1402         return 0;
1403 }
1404
1405 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1406 {
1407         struct ixgbe_hw_fdir_info *fdir_info =
1408                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1409         char fdir_hash_name[RTE_HASH_NAMESIZE];
1410         struct rte_hash_parameters fdir_hash_params = {
1411                 .name = fdir_hash_name,
1412                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1413                 .key_len = sizeof(union ixgbe_atr_input),
1414                 .hash_func = rte_hash_crc,
1415                 .hash_func_init_val = 0,
1416                 .socket_id = rte_socket_id(),
1417         };
1418
1419         TAILQ_INIT(&fdir_info->fdir_list);
1420         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1421                  "fdir_%s", eth_dev->device->name);
1422         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1423         if (!fdir_info->hash_handle) {
1424                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1425                 return -EINVAL;
1426         }
1427         fdir_info->hash_map = rte_zmalloc("ixgbe",
1428                                           sizeof(struct ixgbe_fdir_filter *) *
1429                                           IXGBE_MAX_FDIR_FILTER_NUM,
1430                                           0);
1431         if (!fdir_info->hash_map) {
1432                 PMD_INIT_LOG(ERR,
1433                              "Failed to allocate memory for fdir hash map!");
1434                 return -ENOMEM;
1435         }
1436         fdir_info->mask_added = FALSE;
1437
1438         return 0;
1439 }
1440
1441 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1442 {
1443         struct ixgbe_l2_tn_info *l2_tn_info =
1444                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1445         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1446         struct rte_hash_parameters l2_tn_hash_params = {
1447                 .name = l2_tn_hash_name,
1448                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1449                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1450                 .hash_func = rte_hash_crc,
1451                 .hash_func_init_val = 0,
1452                 .socket_id = rte_socket_id(),
1453         };
1454
1455         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1456         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1457                  "l2_tn_%s", eth_dev->device->name);
1458         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1459         if (!l2_tn_info->hash_handle) {
1460                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1461                 return -EINVAL;
1462         }
1463         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1464                                    sizeof(struct ixgbe_l2_tn_filter *) *
1465                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1466                                    0);
1467         if (!l2_tn_info->hash_map) {
1468                 PMD_INIT_LOG(ERR,
1469                         "Failed to allocate memory for L2 TN hash map!");
1470                 return -ENOMEM;
1471         }
1472         l2_tn_info->e_tag_en = FALSE;
1473         l2_tn_info->e_tag_fwd_en = FALSE;
1474         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1475
1476         return 0;
1477 }
1478 /*
1479  * Negotiate mailbox API version with the PF.
1480  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1481  * Then we try to negotiate starting with the most recent one.
1482  * If all negotiation attempts fail, then we will proceed with
1483  * the default one (ixgbe_mbox_api_10).
1484  */
1485 static void
1486 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1487 {
1488         int32_t i;
1489
1490         /* start with highest supported, proceed down */
1491         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1492                 ixgbe_mbox_api_13,
1493                 ixgbe_mbox_api_12,
1494                 ixgbe_mbox_api_11,
1495                 ixgbe_mbox_api_10,
1496         };
1497
1498         for (i = 0;
1499                         i != RTE_DIM(sup_ver) &&
1500                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1501                         i++)
1502                 ;
1503 }
1504
1505 static void
1506 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1507 {
1508         uint64_t random;
1509
1510         /* Set Organizationally Unique Identifier (OUI) prefix. */
1511         mac_addr->addr_bytes[0] = 0x00;
1512         mac_addr->addr_bytes[1] = 0x09;
1513         mac_addr->addr_bytes[2] = 0xC0;
1514         /* Force indication of locally assigned MAC address. */
1515         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1516         /* Generate the last 3 bytes of the MAC address with a random number. */
1517         random = rte_rand();
1518         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1519 }
1520
1521 static int
1522 devarg_handle_int(__rte_unused const char *key, const char *value,
1523                   void *extra_args)
1524 {
1525         uint16_t *n = extra_args;
1526
1527         if (value == NULL || extra_args == NULL)
1528                 return -EINVAL;
1529
1530         *n = (uint16_t)strtoul(value, NULL, 0);
1531         if (*n == USHRT_MAX && errno == ERANGE)
1532                 return -1;
1533
1534         return 0;
1535 }
1536
1537 static void
1538 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1539                       struct rte_devargs *devargs)
1540 {
1541         struct rte_kvargs *kvlist;
1542         uint16_t pflink_fullchk;
1543
1544         if (devargs == NULL)
1545                 return;
1546
1547         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1548         if (kvlist == NULL)
1549                 return;
1550
1551         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1552             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1553                                devarg_handle_int, &pflink_fullchk) == 0 &&
1554             pflink_fullchk == 1)
1555                 adapter->pflink_fullchk = 1;
1556
1557         rte_kvargs_free(kvlist);
1558 }
1559
1560 /*
1561  * Virtual Function device init
1562  */
1563 static int
1564 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1565 {
1566         int diag;
1567         uint32_t tc, tcs;
1568         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1569         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1570         struct ixgbe_hw *hw =
1571                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1572         struct ixgbe_vfta *shadow_vfta =
1573                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1574         struct ixgbe_hwstrip *hwstrip =
1575                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1576         struct rte_ether_addr *perm_addr =
1577                 (struct rte_ether_addr *)hw->mac.perm_addr;
1578
1579         PMD_INIT_FUNC_TRACE();
1580
1581         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1582         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1583         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1584
1585         /* for secondary processes, we don't initialise any further as primary
1586          * has already done this work. Only check we don't need a different
1587          * RX function
1588          */
1589         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1590                 struct ixgbe_tx_queue *txq;
1591                 /* TX queue function in primary, set by last queue initialized
1592                  * Tx queue may not initialized by primary process
1593                  */
1594                 if (eth_dev->data->tx_queues) {
1595                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1596                         ixgbe_set_tx_function(eth_dev, txq);
1597                 } else {
1598                         /* Use default TX function if we get here */
1599                         PMD_INIT_LOG(NOTICE,
1600                                      "No TX queues configured yet. Using default TX function.");
1601                 }
1602
1603                 ixgbe_set_rx_function(eth_dev);
1604
1605                 return 0;
1606         }
1607
1608         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1609                               pci_dev->device.devargs);
1610
1611         rte_eth_copy_pci_info(eth_dev, pci_dev);
1612
1613         hw->device_id = pci_dev->id.device_id;
1614         hw->vendor_id = pci_dev->id.vendor_id;
1615         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1616
1617         /* initialize the vfta */
1618         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1619
1620         /* initialize the hw strip bitmap*/
1621         memset(hwstrip, 0, sizeof(*hwstrip));
1622
1623         /* Initialize the shared code (base driver) */
1624         diag = ixgbe_init_shared_code(hw);
1625         if (diag != IXGBE_SUCCESS) {
1626                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1627                 return -EIO;
1628         }
1629
1630         /* init_mailbox_params */
1631         hw->mbx.ops.init_params(hw);
1632
1633         /* Reset the hw statistics */
1634         ixgbevf_dev_stats_reset(eth_dev);
1635
1636         /* Disable the interrupts for VF */
1637         ixgbevf_intr_disable(eth_dev);
1638
1639         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1640         diag = hw->mac.ops.reset_hw(hw);
1641
1642         /*
1643          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1644          * the underlying PF driver has not assigned a MAC address to the VF.
1645          * In this case, assign a random MAC address.
1646          */
1647         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1648                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1649                 /*
1650                  * This error code will be propagated to the app by
1651                  * rte_eth_dev_reset, so use a public error code rather than
1652                  * the internal-only IXGBE_ERR_RESET_FAILED
1653                  */
1654                 return -EAGAIN;
1655         }
1656
1657         /* negotiate mailbox API version to use with the PF. */
1658         ixgbevf_negotiate_api(hw);
1659
1660         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1661         ixgbevf_get_queues(hw, &tcs, &tc);
1662
1663         /* Allocate memory for storing MAC addresses */
1664         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1665                                                hw->mac.num_rar_entries, 0);
1666         if (eth_dev->data->mac_addrs == NULL) {
1667                 PMD_INIT_LOG(ERR,
1668                              "Failed to allocate %u bytes needed to store "
1669                              "MAC addresses",
1670                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1671                 return -ENOMEM;
1672         }
1673
1674         /* Pass the information to the rte_eth_dev_close() that it should also
1675          * release the private port resources.
1676          */
1677         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1678
1679         /* Generate a random MAC address, if none was assigned by PF. */
1680         if (rte_is_zero_ether_addr(perm_addr)) {
1681                 generate_random_mac_addr(perm_addr);
1682                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1683                 if (diag) {
1684                         rte_free(eth_dev->data->mac_addrs);
1685                         eth_dev->data->mac_addrs = NULL;
1686                         return diag;
1687                 }
1688                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1689                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1690                              "%02x:%02x:%02x:%02x:%02x:%02x",
1691                              perm_addr->addr_bytes[0],
1692                              perm_addr->addr_bytes[1],
1693                              perm_addr->addr_bytes[2],
1694                              perm_addr->addr_bytes[3],
1695                              perm_addr->addr_bytes[4],
1696                              perm_addr->addr_bytes[5]);
1697         }
1698
1699         /* Copy the permanent MAC address */
1700         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1701
1702         /* reset the hardware with the new settings */
1703         diag = hw->mac.ops.start_hw(hw);
1704         switch (diag) {
1705         case  0:
1706                 break;
1707
1708         default:
1709                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1710                 return -EIO;
1711         }
1712
1713         rte_intr_callback_register(intr_handle,
1714                                    ixgbevf_dev_interrupt_handler, eth_dev);
1715         rte_intr_enable(intr_handle);
1716         ixgbevf_intr_enable(eth_dev);
1717
1718         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1719                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1720                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1721
1722         return 0;
1723 }
1724
1725 /* Virtual Function device uninit */
1726
1727 static int
1728 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1729 {
1730         PMD_INIT_FUNC_TRACE();
1731
1732         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1733                 return 0;
1734
1735         ixgbevf_dev_close(eth_dev);
1736
1737         return 0;
1738 }
1739
1740 static int
1741 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1742                 struct rte_pci_device *pci_dev)
1743 {
1744         char name[RTE_ETH_NAME_MAX_LEN];
1745         struct rte_eth_dev *pf_ethdev;
1746         struct rte_eth_devargs eth_da;
1747         int i, retval;
1748
1749         if (pci_dev->device.devargs) {
1750                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1751                                 &eth_da);
1752                 if (retval)
1753                         return retval;
1754         } else
1755                 memset(&eth_da, 0, sizeof(eth_da));
1756
1757         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1758                 sizeof(struct ixgbe_adapter),
1759                 eth_dev_pci_specific_init, pci_dev,
1760                 eth_ixgbe_dev_init, NULL);
1761
1762         if (retval || eth_da.nb_representor_ports < 1)
1763                 return retval;
1764
1765         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1766         if (pf_ethdev == NULL)
1767                 return -ENODEV;
1768
1769         /* probe VF representor ports */
1770         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1771                 struct ixgbe_vf_info *vfinfo;
1772                 struct ixgbe_vf_representor representor;
1773
1774                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1775                         pf_ethdev->data->dev_private);
1776                 if (vfinfo == NULL) {
1777                         PMD_DRV_LOG(ERR,
1778                                 "no virtual functions supported by PF");
1779                         break;
1780                 }
1781
1782                 representor.vf_id = eth_da.representor_ports[i];
1783                 representor.switch_domain_id = vfinfo->switch_domain_id;
1784                 representor.pf_ethdev = pf_ethdev;
1785
1786                 /* representor port net_bdf_port */
1787                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1788                         pci_dev->device.name,
1789                         eth_da.representor_ports[i]);
1790
1791                 retval = rte_eth_dev_create(&pci_dev->device, name,
1792                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1793                         ixgbe_vf_representor_init, &representor);
1794
1795                 if (retval)
1796                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1797                                 "representor %s.", name);
1798         }
1799
1800         return 0;
1801 }
1802
1803 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1804 {
1805         struct rte_eth_dev *ethdev;
1806
1807         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1808         if (!ethdev)
1809                 return 0;
1810
1811         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1812                 return rte_eth_dev_pci_generic_remove(pci_dev,
1813                                         ixgbe_vf_representor_uninit);
1814         else
1815                 return rte_eth_dev_pci_generic_remove(pci_dev,
1816                                                 eth_ixgbe_dev_uninit);
1817 }
1818
1819 static struct rte_pci_driver rte_ixgbe_pmd = {
1820         .id_table = pci_id_ixgbe_map,
1821         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1822         .probe = eth_ixgbe_pci_probe,
1823         .remove = eth_ixgbe_pci_remove,
1824 };
1825
1826 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1827         struct rte_pci_device *pci_dev)
1828 {
1829         return rte_eth_dev_pci_generic_probe(pci_dev,
1830                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1831 }
1832
1833 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1834 {
1835         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1836 }
1837
1838 /*
1839  * virtual function driver struct
1840  */
1841 static struct rte_pci_driver rte_ixgbevf_pmd = {
1842         .id_table = pci_id_ixgbevf_map,
1843         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1844         .probe = eth_ixgbevf_pci_probe,
1845         .remove = eth_ixgbevf_pci_remove,
1846 };
1847
1848 static int
1849 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         struct ixgbe_vfta *shadow_vfta =
1854                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1855         uint32_t vfta;
1856         uint32_t vid_idx;
1857         uint32_t vid_bit;
1858
1859         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1860         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1861         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1862         if (on)
1863                 vfta |= vid_bit;
1864         else
1865                 vfta &= ~vid_bit;
1866         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1867
1868         /* update local VFTA copy */
1869         shadow_vfta->vfta[vid_idx] = vfta;
1870
1871         return 0;
1872 }
1873
1874 static void
1875 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1876 {
1877         if (on)
1878                 ixgbe_vlan_hw_strip_enable(dev, queue);
1879         else
1880                 ixgbe_vlan_hw_strip_disable(dev, queue);
1881 }
1882
1883 static int
1884 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1885                     enum rte_vlan_type vlan_type,
1886                     uint16_t tpid)
1887 {
1888         struct ixgbe_hw *hw =
1889                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         int ret = 0;
1891         uint32_t reg;
1892         uint32_t qinq;
1893
1894         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1895         qinq &= IXGBE_DMATXCTL_GDV;
1896
1897         switch (vlan_type) {
1898         case ETH_VLAN_TYPE_INNER:
1899                 if (qinq) {
1900                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1901                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1902                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1903                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1904                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1905                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1906                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1907                 } else {
1908                         ret = -ENOTSUP;
1909                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1910                                     " by single VLAN");
1911                 }
1912                 break;
1913         case ETH_VLAN_TYPE_OUTER:
1914                 if (qinq) {
1915                         /* Only the high 16-bits is valid */
1916                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1917                                         IXGBE_EXVET_VET_EXT_SHIFT);
1918                 } else {
1919                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1920                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1921                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1922                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1923                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1924                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1925                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1926                 }
1927
1928                 break;
1929         default:
1930                 ret = -EINVAL;
1931                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1932                 break;
1933         }
1934
1935         return ret;
1936 }
1937
1938 void
1939 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1940 {
1941         struct ixgbe_hw *hw =
1942                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         uint32_t vlnctrl;
1944
1945         PMD_INIT_FUNC_TRACE();
1946
1947         /* Filter Table Disable */
1948         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1949         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1950
1951         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1952 }
1953
1954 void
1955 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1956 {
1957         struct ixgbe_hw *hw =
1958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         struct ixgbe_vfta *shadow_vfta =
1960                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1961         uint32_t vlnctrl;
1962         uint16_t i;
1963
1964         PMD_INIT_FUNC_TRACE();
1965
1966         /* Filter Table Enable */
1967         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1968         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1969         vlnctrl |= IXGBE_VLNCTRL_VFE;
1970
1971         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1972
1973         /* write whatever is in local vfta copy */
1974         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1975                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1976 }
1977
1978 static void
1979 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1980 {
1981         struct ixgbe_hwstrip *hwstrip =
1982                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1983         struct ixgbe_rx_queue *rxq;
1984
1985         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1986                 return;
1987
1988         if (on)
1989                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1990         else
1991                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1992
1993         if (queue >= dev->data->nb_rx_queues)
1994                 return;
1995
1996         rxq = dev->data->rx_queues[queue];
1997
1998         if (on) {
1999                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2000                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2001         } else {
2002                 rxq->vlan_flags = PKT_RX_VLAN;
2003                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2004         }
2005 }
2006
2007 static void
2008 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2009 {
2010         struct ixgbe_hw *hw =
2011                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         uint32_t ctrl;
2013
2014         PMD_INIT_FUNC_TRACE();
2015
2016         if (hw->mac.type == ixgbe_mac_82598EB) {
2017                 /* No queue level support */
2018                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2019                 return;
2020         }
2021
2022         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2023         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2024         ctrl &= ~IXGBE_RXDCTL_VME;
2025         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2026
2027         /* record those setting for HW strip per queue */
2028         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2029 }
2030
2031 static void
2032 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2033 {
2034         struct ixgbe_hw *hw =
2035                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2036         uint32_t ctrl;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         if (hw->mac.type == ixgbe_mac_82598EB) {
2041                 /* No queue level supported */
2042                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2043                 return;
2044         }
2045
2046         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2047         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2048         ctrl |= IXGBE_RXDCTL_VME;
2049         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2050
2051         /* record those setting for HW strip per queue */
2052         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2053 }
2054
2055 static void
2056 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2057 {
2058         struct ixgbe_hw *hw =
2059                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060         uint32_t ctrl;
2061
2062         PMD_INIT_FUNC_TRACE();
2063
2064         /* DMATXCTRL: Geric Double VLAN Disable */
2065         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2066         ctrl &= ~IXGBE_DMATXCTL_GDV;
2067         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2068
2069         /* CTRL_EXT: Global Double VLAN Disable */
2070         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2071         ctrl &= ~IXGBE_EXTENDED_VLAN;
2072         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2073
2074 }
2075
2076 static void
2077 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2078 {
2079         struct ixgbe_hw *hw =
2080                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2081         uint32_t ctrl;
2082
2083         PMD_INIT_FUNC_TRACE();
2084
2085         /* DMATXCTRL: Geric Double VLAN Enable */
2086         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2087         ctrl |= IXGBE_DMATXCTL_GDV;
2088         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2089
2090         /* CTRL_EXT: Global Double VLAN Enable */
2091         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2092         ctrl |= IXGBE_EXTENDED_VLAN;
2093         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2094
2095         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2096         if (hw->mac.type == ixgbe_mac_X550 ||
2097             hw->mac.type == ixgbe_mac_X550EM_x ||
2098             hw->mac.type == ixgbe_mac_X550EM_a) {
2099                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2100                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2101                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2102         }
2103
2104         /*
2105          * VET EXT field in the EXVET register = 0x8100 by default
2106          * So no need to change. Same to VT field of DMATXCTL register
2107          */
2108 }
2109
2110 void
2111 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2112 {
2113         struct ixgbe_hw *hw =
2114                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2115         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2116         uint32_t ctrl;
2117         uint16_t i;
2118         struct ixgbe_rx_queue *rxq;
2119         bool on;
2120
2121         PMD_INIT_FUNC_TRACE();
2122
2123         if (hw->mac.type == ixgbe_mac_82598EB) {
2124                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2125                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2126                         ctrl |= IXGBE_VLNCTRL_VME;
2127                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2128                 } else {
2129                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2130                         ctrl &= ~IXGBE_VLNCTRL_VME;
2131                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2132                 }
2133         } else {
2134                 /*
2135                  * Other 10G NIC, the VLAN strip can be setup
2136                  * per queue in RXDCTL
2137                  */
2138                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2139                         rxq = dev->data->rx_queues[i];
2140                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2141                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2142                                 ctrl |= IXGBE_RXDCTL_VME;
2143                                 on = TRUE;
2144                         } else {
2145                                 ctrl &= ~IXGBE_RXDCTL_VME;
2146                                 on = FALSE;
2147                         }
2148                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2149
2150                         /* record those setting for HW strip per queue */
2151                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2152                 }
2153         }
2154 }
2155
2156 static void
2157 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2158 {
2159         uint16_t i;
2160         struct rte_eth_rxmode *rxmode;
2161         struct ixgbe_rx_queue *rxq;
2162
2163         if (mask & ETH_VLAN_STRIP_MASK) {
2164                 rxmode = &dev->data->dev_conf.rxmode;
2165                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2166                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2167                                 rxq = dev->data->rx_queues[i];
2168                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2169                         }
2170                 else
2171                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2172                                 rxq = dev->data->rx_queues[i];
2173                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2174                         }
2175         }
2176 }
2177
2178 static int
2179 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2180 {
2181         struct rte_eth_rxmode *rxmode;
2182         rxmode = &dev->data->dev_conf.rxmode;
2183
2184         if (mask & ETH_VLAN_STRIP_MASK) {
2185                 ixgbe_vlan_hw_strip_config(dev);
2186         }
2187
2188         if (mask & ETH_VLAN_FILTER_MASK) {
2189                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2190                         ixgbe_vlan_hw_filter_enable(dev);
2191                 else
2192                         ixgbe_vlan_hw_filter_disable(dev);
2193         }
2194
2195         if (mask & ETH_VLAN_EXTEND_MASK) {
2196                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2197                         ixgbe_vlan_hw_extend_enable(dev);
2198                 else
2199                         ixgbe_vlan_hw_extend_disable(dev);
2200         }
2201
2202         return 0;
2203 }
2204
2205 static int
2206 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2207 {
2208         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2209
2210         ixgbe_vlan_offload_config(dev, mask);
2211
2212         return 0;
2213 }
2214
2215 static void
2216 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2217 {
2218         struct ixgbe_hw *hw =
2219                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2221         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2222
2223         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2224         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2225 }
2226
2227 static int
2228 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2229 {
2230         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2231
2232         switch (nb_rx_q) {
2233         case 1:
2234         case 2:
2235                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2236                 break;
2237         case 4:
2238                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2239                 break;
2240         default:
2241                 return -EINVAL;
2242         }
2243
2244         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2245                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2246         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2247                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2248         return 0;
2249 }
2250
2251 static int
2252 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2253 {
2254         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2256         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2257         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2258
2259         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2260                 /* check multi-queue mode */
2261                 switch (dev_conf->rxmode.mq_mode) {
2262                 case ETH_MQ_RX_VMDQ_DCB:
2263                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2264                         break;
2265                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2266                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2267                         PMD_INIT_LOG(ERR, "SRIOV active,"
2268                                         " unsupported mq_mode rx %d.",
2269                                         dev_conf->rxmode.mq_mode);
2270                         return -EINVAL;
2271                 case ETH_MQ_RX_RSS:
2272                 case ETH_MQ_RX_VMDQ_RSS:
2273                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2274                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2275                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2276                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2277                                                 " invalid queue number"
2278                                                 " for VMDQ RSS, allowed"
2279                                                 " value are 1, 2 or 4.");
2280                                         return -EINVAL;
2281                                 }
2282                         break;
2283                 case ETH_MQ_RX_VMDQ_ONLY:
2284                 case ETH_MQ_RX_NONE:
2285                         /* if nothing mq mode configure, use default scheme */
2286                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2287                         break;
2288                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2289                         /* SRIOV only works in VMDq enable mode */
2290                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2291                                         " wrong mq_mode rx %d.",
2292                                         dev_conf->rxmode.mq_mode);
2293                         return -EINVAL;
2294                 }
2295
2296                 switch (dev_conf->txmode.mq_mode) {
2297                 case ETH_MQ_TX_VMDQ_DCB:
2298                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2299                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2300                         break;
2301                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2302                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2303                         break;
2304                 }
2305
2306                 /* check valid queue number */
2307                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2308                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2309                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2310                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2311                                         " must be less than or equal to %d.",
2312                                         nb_rx_q, nb_tx_q,
2313                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2314                         return -EINVAL;
2315                 }
2316         } else {
2317                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2318                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2319                                           " not supported.");
2320                         return -EINVAL;
2321                 }
2322                 /* check configuration for vmdb+dcb mode */
2323                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2324                         const struct rte_eth_vmdq_dcb_conf *conf;
2325
2326                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2327                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2328                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2329                                 return -EINVAL;
2330                         }
2331                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2332                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2333                                conf->nb_queue_pools == ETH_32_POOLS)) {
2334                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2335                                                 " nb_queue_pools must be %d or %d.",
2336                                                 ETH_16_POOLS, ETH_32_POOLS);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2341                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2342
2343                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2344                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2345                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2346                                 return -EINVAL;
2347                         }
2348                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2349                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2350                                conf->nb_queue_pools == ETH_32_POOLS)) {
2351                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2352                                                 " nb_queue_pools != %d and"
2353                                                 " nb_queue_pools != %d.",
2354                                                 ETH_16_POOLS, ETH_32_POOLS);
2355                                 return -EINVAL;
2356                         }
2357                 }
2358
2359                 /* For DCB mode check our configuration before we go further */
2360                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2361                         const struct rte_eth_dcb_rx_conf *conf;
2362
2363                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2364                         if (!(conf->nb_tcs == ETH_4_TCS ||
2365                                conf->nb_tcs == ETH_8_TCS)) {
2366                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2367                                                 " and nb_tcs != %d.",
2368                                                 ETH_4_TCS, ETH_8_TCS);
2369                                 return -EINVAL;
2370                         }
2371                 }
2372
2373                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2374                         const struct rte_eth_dcb_tx_conf *conf;
2375
2376                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2377                         if (!(conf->nb_tcs == ETH_4_TCS ||
2378                                conf->nb_tcs == ETH_8_TCS)) {
2379                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2380                                                 " and nb_tcs != %d.",
2381                                                 ETH_4_TCS, ETH_8_TCS);
2382                                 return -EINVAL;
2383                         }
2384                 }
2385
2386                 /*
2387                  * When DCB/VT is off, maximum number of queues changes,
2388                  * except for 82598EB, which remains constant.
2389                  */
2390                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2391                                 hw->mac.type != ixgbe_mac_82598EB) {
2392                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2393                                 PMD_INIT_LOG(ERR,
2394                                              "Neither VT nor DCB are enabled, "
2395                                              "nb_tx_q > %d.",
2396                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2397                                 return -EINVAL;
2398                         }
2399                 }
2400         }
2401         return 0;
2402 }
2403
2404 static int
2405 ixgbe_dev_configure(struct rte_eth_dev *dev)
2406 {
2407         struct ixgbe_interrupt *intr =
2408                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2409         struct ixgbe_adapter *adapter = dev->data->dev_private;
2410         int ret;
2411
2412         PMD_INIT_FUNC_TRACE();
2413
2414         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2415                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2416
2417         /* multipe queue mode checking */
2418         ret  = ixgbe_check_mq_mode(dev);
2419         if (ret != 0) {
2420                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2421                             ret);
2422                 return ret;
2423         }
2424
2425         /* set flag to update link status after init */
2426         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2427
2428         /*
2429          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2430          * allocation or vector Rx preconditions we will reset it.
2431          */
2432         adapter->rx_bulk_alloc_allowed = true;
2433         adapter->rx_vec_allowed = true;
2434
2435         return 0;
2436 }
2437
2438 static void
2439 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2440 {
2441         struct ixgbe_hw *hw =
2442                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2443         struct ixgbe_interrupt *intr =
2444                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2445         uint32_t gpie;
2446
2447         /* only set up it on X550EM_X */
2448         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2449                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2450                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2451                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2452                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2453                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2454         }
2455 }
2456
2457 int
2458 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2459                         uint16_t tx_rate, uint64_t q_msk)
2460 {
2461         struct ixgbe_hw *hw;
2462         struct ixgbe_vf_info *vfinfo;
2463         struct rte_eth_link link;
2464         uint8_t  nb_q_per_pool;
2465         uint32_t queue_stride;
2466         uint32_t queue_idx, idx = 0, vf_idx;
2467         uint32_t queue_end;
2468         uint16_t total_rate = 0;
2469         struct rte_pci_device *pci_dev;
2470         int ret;
2471
2472         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2473         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2474         if (ret < 0)
2475                 return ret;
2476
2477         if (vf >= pci_dev->max_vfs)
2478                 return -EINVAL;
2479
2480         if (tx_rate > link.link_speed)
2481                 return -EINVAL;
2482
2483         if (q_msk == 0)
2484                 return 0;
2485
2486         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2488         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2489         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2490         queue_idx = vf * queue_stride;
2491         queue_end = queue_idx + nb_q_per_pool - 1;
2492         if (queue_end >= hw->mac.max_tx_queues)
2493                 return -EINVAL;
2494
2495         if (vfinfo) {
2496                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2497                         if (vf_idx == vf)
2498                                 continue;
2499                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2500                                 idx++)
2501                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2502                 }
2503         } else {
2504                 return -EINVAL;
2505         }
2506
2507         /* Store tx_rate for this vf. */
2508         for (idx = 0; idx < nb_q_per_pool; idx++) {
2509                 if (((uint64_t)0x1 << idx) & q_msk) {
2510                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2511                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2512                         total_rate += tx_rate;
2513                 }
2514         }
2515
2516         if (total_rate > dev->data->dev_link.link_speed) {
2517                 /* Reset stored TX rate of the VF if it causes exceed
2518                  * link speed.
2519                  */
2520                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2521                 return -EINVAL;
2522         }
2523
2524         /* Set RTTBCNRC of each queue/pool for vf X  */
2525         for (; queue_idx <= queue_end; queue_idx++) {
2526                 if (0x1 & q_msk)
2527                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2528                 q_msk = q_msk >> 1;
2529         }
2530
2531         return 0;
2532 }
2533
2534 /*
2535  * Configure device link speed and setup link.
2536  * It returns 0 on success.
2537  */
2538 static int
2539 ixgbe_dev_start(struct rte_eth_dev *dev)
2540 {
2541         struct ixgbe_hw *hw =
2542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2543         struct ixgbe_vf_info *vfinfo =
2544                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2547         uint32_t intr_vector = 0;
2548         int err, link_up = 0, negotiate = 0;
2549         uint32_t speed = 0;
2550         uint32_t allowed_speeds = 0;
2551         int mask = 0;
2552         int status;
2553         uint16_t vf, idx;
2554         uint32_t *link_speeds;
2555         struct ixgbe_tm_conf *tm_conf =
2556                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2557         struct ixgbe_macsec_setting *macsec_setting =
2558                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2559
2560         PMD_INIT_FUNC_TRACE();
2561
2562         /* Stop the link setup handler before resetting the HW. */
2563         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2564
2565         /* disable uio/vfio intr/eventfd mapping */
2566         rte_intr_disable(intr_handle);
2567
2568         /* stop adapter */
2569         hw->adapter_stopped = 0;
2570         ixgbe_stop_adapter(hw);
2571
2572         /* reinitialize adapter
2573          * this calls reset and start
2574          */
2575         status = ixgbe_pf_reset_hw(hw);
2576         if (status != 0)
2577                 return -1;
2578         hw->mac.ops.start_hw(hw);
2579         hw->mac.get_link_status = true;
2580
2581         /* configure PF module if SRIOV enabled */
2582         ixgbe_pf_host_configure(dev);
2583
2584         ixgbe_dev_phy_intr_setup(dev);
2585
2586         /* check and configure queue intr-vector mapping */
2587         if ((rte_intr_cap_multiple(intr_handle) ||
2588              !RTE_ETH_DEV_SRIOV(dev).active) &&
2589             dev->data->dev_conf.intr_conf.rxq != 0) {
2590                 intr_vector = dev->data->nb_rx_queues;
2591                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2592                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2593                                         IXGBE_MAX_INTR_QUEUE_NUM);
2594                         return -ENOTSUP;
2595                 }
2596                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2597                         return -1;
2598         }
2599
2600         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2601                 intr_handle->intr_vec =
2602                         rte_zmalloc("intr_vec",
2603                                     dev->data->nb_rx_queues * sizeof(int), 0);
2604                 if (intr_handle->intr_vec == NULL) {
2605                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2606                                      " intr_vec", dev->data->nb_rx_queues);
2607                         return -ENOMEM;
2608                 }
2609         }
2610
2611         /* confiugre msix for sleep until rx interrupt */
2612         ixgbe_configure_msix(dev);
2613
2614         /* initialize transmission unit */
2615         ixgbe_dev_tx_init(dev);
2616
2617         /* This can fail when allocating mbufs for descriptor rings */
2618         err = ixgbe_dev_rx_init(dev);
2619         if (err) {
2620                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2621                 goto error;
2622         }
2623
2624         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2625                 ETH_VLAN_EXTEND_MASK;
2626         err = ixgbe_vlan_offload_config(dev, mask);
2627         if (err) {
2628                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2629                 goto error;
2630         }
2631
2632         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2633                 /* Enable vlan filtering for VMDq */
2634                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2635         }
2636
2637         /* Configure DCB hw */
2638         ixgbe_configure_dcb(dev);
2639
2640         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2641                 err = ixgbe_fdir_configure(dev);
2642                 if (err)
2643                         goto error;
2644         }
2645
2646         /* Restore vf rate limit */
2647         if (vfinfo != NULL) {
2648                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2649                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2650                                 if (vfinfo[vf].tx_rate[idx] != 0)
2651                                         ixgbe_set_vf_rate_limit(
2652                                                 dev, vf,
2653                                                 vfinfo[vf].tx_rate[idx],
2654                                                 1 << idx);
2655         }
2656
2657         ixgbe_restore_statistics_mapping(dev);
2658
2659         err = ixgbe_dev_rxtx_start(dev);
2660         if (err < 0) {
2661                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2662                 goto error;
2663         }
2664
2665         /* Skip link setup if loopback mode is enabled. */
2666         if (dev->data->dev_conf.lpbk_mode != 0) {
2667                 err = ixgbe_check_supported_loopback_mode(dev);
2668                 if (err < 0) {
2669                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2670                         goto error;
2671                 } else {
2672                         goto skip_link_setup;
2673                 }
2674         }
2675
2676         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2677                 err = hw->mac.ops.setup_sfp(hw);
2678                 if (err)
2679                         goto error;
2680         }
2681
2682         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2683                 /* Turn on the copper */
2684                 ixgbe_set_phy_power(hw, true);
2685         } else {
2686                 /* Turn on the laser */
2687                 ixgbe_enable_tx_laser(hw);
2688         }
2689
2690         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2691         if (err)
2692                 goto error;
2693         dev->data->dev_link.link_status = link_up;
2694
2695         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2696         if (err)
2697                 goto error;
2698
2699         switch (hw->mac.type) {
2700         case ixgbe_mac_X550:
2701         case ixgbe_mac_X550EM_x:
2702         case ixgbe_mac_X550EM_a:
2703                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2704                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2705                         ETH_LINK_SPEED_10G;
2706                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2707                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2708                         allowed_speeds = ETH_LINK_SPEED_10M |
2709                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2710                 break;
2711         default:
2712                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2713                         ETH_LINK_SPEED_10G;
2714         }
2715
2716         link_speeds = &dev->data->dev_conf.link_speeds;
2717
2718         /* Ignore autoneg flag bit and check the validity of
2719          * link_speed
2720          */
2721         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2722                 PMD_INIT_LOG(ERR, "Invalid link setting");
2723                 goto error;
2724         }
2725
2726         speed = 0x0;
2727         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2728                 switch (hw->mac.type) {
2729                 case ixgbe_mac_82598EB:
2730                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2731                         break;
2732                 case ixgbe_mac_82599EB:
2733                 case ixgbe_mac_X540:
2734                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2735                         break;
2736                 case ixgbe_mac_X550:
2737                 case ixgbe_mac_X550EM_x:
2738                 case ixgbe_mac_X550EM_a:
2739                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2740                         break;
2741                 default:
2742                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2743                 }
2744         } else {
2745                 if (*link_speeds & ETH_LINK_SPEED_10G)
2746                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2747                 if (*link_speeds & ETH_LINK_SPEED_5G)
2748                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2749                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2750                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2751                 if (*link_speeds & ETH_LINK_SPEED_1G)
2752                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2753                 if (*link_speeds & ETH_LINK_SPEED_100M)
2754                         speed |= IXGBE_LINK_SPEED_100_FULL;
2755                 if (*link_speeds & ETH_LINK_SPEED_10M)
2756                         speed |= IXGBE_LINK_SPEED_10_FULL;
2757         }
2758
2759         err = ixgbe_setup_link(hw, speed, link_up);
2760         if (err)
2761                 goto error;
2762
2763 skip_link_setup:
2764
2765         if (rte_intr_allow_others(intr_handle)) {
2766                 /* check if lsc interrupt is enabled */
2767                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2768                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2769                 else
2770                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2771                 ixgbe_dev_macsec_interrupt_setup(dev);
2772         } else {
2773                 rte_intr_callback_unregister(intr_handle,
2774                                              ixgbe_dev_interrupt_handler, dev);
2775                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2776                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2777                                      " no intr multiplex");
2778         }
2779
2780         /* check if rxq interrupt is enabled */
2781         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2782             rte_intr_dp_is_en(intr_handle))
2783                 ixgbe_dev_rxq_interrupt_setup(dev);
2784
2785         /* enable uio/vfio intr/eventfd mapping */
2786         rte_intr_enable(intr_handle);
2787
2788         /* resume enabled intr since hw reset */
2789         ixgbe_enable_intr(dev);
2790         ixgbe_l2_tunnel_conf(dev);
2791         ixgbe_filter_restore(dev);
2792
2793         if (tm_conf->root && !tm_conf->committed)
2794                 PMD_DRV_LOG(WARNING,
2795                             "please call hierarchy_commit() "
2796                             "before starting the port");
2797
2798         /* wait for the controller to acquire link */
2799         err = ixgbe_wait_for_link_up(hw);
2800         if (err)
2801                 goto error;
2802
2803         /*
2804          * Update link status right before return, because it may
2805          * start link configuration process in a separate thread.
2806          */
2807         ixgbe_dev_link_update(dev, 0);
2808
2809         /* setup the macsec setting register */
2810         if (macsec_setting->offload_en)
2811                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2812
2813         return 0;
2814
2815 error:
2816         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2817         ixgbe_dev_clear_queues(dev);
2818         return -EIO;
2819 }
2820
2821 /*
2822  * Stop device: disable rx and tx functions to allow for reconfiguring.
2823  */
2824 static void
2825 ixgbe_dev_stop(struct rte_eth_dev *dev)
2826 {
2827         struct rte_eth_link link;
2828         struct ixgbe_adapter *adapter = dev->data->dev_private;
2829         struct ixgbe_hw *hw =
2830                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831         struct ixgbe_vf_info *vfinfo =
2832                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2833         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2834         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2835         int vf;
2836         struct ixgbe_tm_conf *tm_conf =
2837                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2838
2839         if (hw->adapter_stopped)
2840                 return;
2841
2842         PMD_INIT_FUNC_TRACE();
2843
2844         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2845
2846         /* disable interrupts */
2847         ixgbe_disable_intr(hw);
2848
2849         /* reset the NIC */
2850         ixgbe_pf_reset_hw(hw);
2851         hw->adapter_stopped = 0;
2852
2853         /* stop adapter */
2854         ixgbe_stop_adapter(hw);
2855
2856         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2857                 vfinfo[vf].clear_to_send = false;
2858
2859         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2860                 /* Turn off the copper */
2861                 ixgbe_set_phy_power(hw, false);
2862         } else {
2863                 /* Turn off the laser */
2864                 ixgbe_disable_tx_laser(hw);
2865         }
2866
2867         ixgbe_dev_clear_queues(dev);
2868
2869         /* Clear stored conf */
2870         dev->data->scattered_rx = 0;
2871         dev->data->lro = 0;
2872
2873         /* Clear recorded link status */
2874         memset(&link, 0, sizeof(link));
2875         rte_eth_linkstatus_set(dev, &link);
2876
2877         if (!rte_intr_allow_others(intr_handle))
2878                 /* resume to the default handler */
2879                 rte_intr_callback_register(intr_handle,
2880                                            ixgbe_dev_interrupt_handler,
2881                                            (void *)dev);
2882
2883         /* Clean datapath event and queue/vec mapping */
2884         rte_intr_efd_disable(intr_handle);
2885         if (intr_handle->intr_vec != NULL) {
2886                 rte_free(intr_handle->intr_vec);
2887                 intr_handle->intr_vec = NULL;
2888         }
2889
2890         /* reset hierarchy commit */
2891         tm_conf->committed = false;
2892
2893         adapter->rss_reta_updated = 0;
2894
2895         hw->adapter_stopped = true;
2896 }
2897
2898 /*
2899  * Set device link up: enable tx.
2900  */
2901 static int
2902 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2903 {
2904         struct ixgbe_hw *hw =
2905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2906         if (hw->mac.type == ixgbe_mac_82599EB) {
2907 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2908                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2909                         /* Not suported in bypass mode */
2910                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2911                                      "by device id 0x%x", hw->device_id);
2912                         return -ENOTSUP;
2913                 }
2914 #endif
2915         }
2916
2917         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2918                 /* Turn on the copper */
2919                 ixgbe_set_phy_power(hw, true);
2920         } else {
2921                 /* Turn on the laser */
2922                 ixgbe_enable_tx_laser(hw);
2923                 ixgbe_dev_link_update(dev, 0);
2924         }
2925
2926         return 0;
2927 }
2928
2929 /*
2930  * Set device link down: disable tx.
2931  */
2932 static int
2933 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2934 {
2935         struct ixgbe_hw *hw =
2936                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2937         if (hw->mac.type == ixgbe_mac_82599EB) {
2938 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2939                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2940                         /* Not suported in bypass mode */
2941                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2942                                      "by device id 0x%x", hw->device_id);
2943                         return -ENOTSUP;
2944                 }
2945 #endif
2946         }
2947
2948         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2949                 /* Turn off the copper */
2950                 ixgbe_set_phy_power(hw, false);
2951         } else {
2952                 /* Turn off the laser */
2953                 ixgbe_disable_tx_laser(hw);
2954                 ixgbe_dev_link_update(dev, 0);
2955         }
2956
2957         return 0;
2958 }
2959
2960 /*
2961  * Reset and stop device.
2962  */
2963 static void
2964 ixgbe_dev_close(struct rte_eth_dev *dev)
2965 {
2966         struct ixgbe_hw *hw =
2967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2969         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2970         int retries = 0;
2971         int ret;
2972
2973         PMD_INIT_FUNC_TRACE();
2974
2975         ixgbe_pf_reset_hw(hw);
2976
2977         ixgbe_dev_stop(dev);
2978
2979         ixgbe_dev_free_queues(dev);
2980
2981         ixgbe_disable_pcie_master(hw);
2982
2983         /* reprogram the RAR[0] in case user changed it. */
2984         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2985
2986         dev->dev_ops = NULL;
2987         dev->rx_pkt_burst = NULL;
2988         dev->tx_pkt_burst = NULL;
2989
2990         /* Unlock any pending hardware semaphore */
2991         ixgbe_swfw_lock_reset(hw);
2992
2993         /* disable uio intr before callback unregister */
2994         rte_intr_disable(intr_handle);
2995
2996         do {
2997                 ret = rte_intr_callback_unregister(intr_handle,
2998                                 ixgbe_dev_interrupt_handler, dev);
2999                 if (ret >= 0 || ret == -ENOENT) {
3000                         break;
3001                 } else if (ret != -EAGAIN) {
3002                         PMD_INIT_LOG(ERR,
3003                                 "intr callback unregister failed: %d",
3004                                 ret);
3005                 }
3006                 rte_delay_ms(100);
3007         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3008
3009         /* cancel the delay handler before remove dev */
3010         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3011
3012         /* uninitialize PF if max_vfs not zero */
3013         ixgbe_pf_host_uninit(dev);
3014
3015         /* remove all the fdir filters & hash */
3016         ixgbe_fdir_filter_uninit(dev);
3017
3018         /* remove all the L2 tunnel filters & hash */
3019         ixgbe_l2_tn_filter_uninit(dev);
3020
3021         /* Remove all ntuple filters of the device */
3022         ixgbe_ntuple_filter_uninit(dev);
3023
3024         /* clear all the filters list */
3025         ixgbe_filterlist_flush();
3026
3027         /* Remove all Traffic Manager configuration */
3028         ixgbe_tm_conf_uninit(dev);
3029
3030 #ifdef RTE_LIBRTE_SECURITY
3031         rte_free(dev->security_ctx);
3032 #endif
3033
3034 }
3035
3036 /*
3037  * Reset PF device.
3038  */
3039 static int
3040 ixgbe_dev_reset(struct rte_eth_dev *dev)
3041 {
3042         int ret;
3043
3044         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3045          * its VF to make them align with it. The detailed notification
3046          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3047          * To avoid unexpected behavior in VF, currently reset of PF with
3048          * SR-IOV activation is not supported. It might be supported later.
3049          */
3050         if (dev->data->sriov.active)
3051                 return -ENOTSUP;
3052
3053         ret = eth_ixgbe_dev_uninit(dev);
3054         if (ret)
3055                 return ret;
3056
3057         ret = eth_ixgbe_dev_init(dev, NULL);
3058
3059         return ret;
3060 }
3061
3062 static void
3063 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3064                            struct ixgbe_hw_stats *hw_stats,
3065                            struct ixgbe_macsec_stats *macsec_stats,
3066                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3067                            uint64_t *total_qprc, uint64_t *total_qprdc)
3068 {
3069         uint32_t bprc, lxon, lxoff, total;
3070         uint32_t delta_gprc = 0;
3071         unsigned i;
3072         /* Workaround for RX byte count not including CRC bytes when CRC
3073          * strip is enabled. CRC bytes are removed from counters when crc_strip
3074          * is disabled.
3075          */
3076         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3077                         IXGBE_HLREG0_RXCRCSTRP);
3078
3079         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3080         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3081         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3082         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3083
3084         for (i = 0; i < 8; i++) {
3085                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3086
3087                 /* global total per queue */
3088                 hw_stats->mpc[i] += mp;
3089                 /* Running comprehensive total for stats display */
3090                 *total_missed_rx += hw_stats->mpc[i];
3091                 if (hw->mac.type == ixgbe_mac_82598EB) {
3092                         hw_stats->rnbc[i] +=
3093                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3094                         hw_stats->pxonrxc[i] +=
3095                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3096                         hw_stats->pxoffrxc[i] +=
3097                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3098                 } else {
3099                         hw_stats->pxonrxc[i] +=
3100                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3101                         hw_stats->pxoffrxc[i] +=
3102                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3103                         hw_stats->pxon2offc[i] +=
3104                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3105                 }
3106                 hw_stats->pxontxc[i] +=
3107                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3108                 hw_stats->pxofftxc[i] +=
3109                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3110         }
3111         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3112                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3113                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3114                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3115
3116                 delta_gprc += delta_qprc;
3117
3118                 hw_stats->qprc[i] += delta_qprc;
3119                 hw_stats->qptc[i] += delta_qptc;
3120
3121                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3122                 hw_stats->qbrc[i] +=
3123                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3124                 if (crc_strip == 0)
3125                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3126
3127                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3128                 hw_stats->qbtc[i] +=
3129                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3130
3131                 hw_stats->qprdc[i] += delta_qprdc;
3132                 *total_qprdc += hw_stats->qprdc[i];
3133
3134                 *total_qprc += hw_stats->qprc[i];
3135                 *total_qbrc += hw_stats->qbrc[i];
3136         }
3137         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3138         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3139         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3140
3141         /*
3142          * An errata states that gprc actually counts good + missed packets:
3143          * Workaround to set gprc to summated queue packet receives
3144          */
3145         hw_stats->gprc = *total_qprc;
3146
3147         if (hw->mac.type != ixgbe_mac_82598EB) {
3148                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3149                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3150                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3151                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3152                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3153                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3154                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3155                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3156         } else {
3157                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3158                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3159                 /* 82598 only has a counter in the high register */
3160                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3161                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3162                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3163         }
3164         uint64_t old_tpr = hw_stats->tpr;
3165
3166         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3167         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3168
3169         if (crc_strip == 0)
3170                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3171
3172         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3173         hw_stats->gptc += delta_gptc;
3174         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3175         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3176
3177         /*
3178          * Workaround: mprc hardware is incorrectly counting
3179          * broadcasts, so for now we subtract those.
3180          */
3181         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3182         hw_stats->bprc += bprc;
3183         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3184         if (hw->mac.type == ixgbe_mac_82598EB)
3185                 hw_stats->mprc -= bprc;
3186
3187         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3188         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3189         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3190         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3191         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3192         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3193
3194         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3195         hw_stats->lxontxc += lxon;
3196         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3197         hw_stats->lxofftxc += lxoff;
3198         total = lxon + lxoff;
3199
3200         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3201         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3202         hw_stats->gptc -= total;
3203         hw_stats->mptc -= total;
3204         hw_stats->ptc64 -= total;
3205         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3206
3207         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3208         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3209         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3210         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3211         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3212         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3213         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3214         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3215         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3216         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3217         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3218         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3219         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3220         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3221         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3222         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3223         /* Only read FCOE on 82599 */
3224         if (hw->mac.type != ixgbe_mac_82598EB) {
3225                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3226                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3227                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3228                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3229                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3230         }
3231
3232         /* Flow Director Stats registers */
3233         if (hw->mac.type != ixgbe_mac_82598EB) {
3234                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3235                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3236                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3237                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3238                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3239                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3240                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3241                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3242                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3243                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3244         }
3245         /* MACsec Stats registers */
3246         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3247         macsec_stats->out_pkts_encrypted +=
3248                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3249         macsec_stats->out_pkts_protected +=
3250                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3251         macsec_stats->out_octets_encrypted +=
3252                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3253         macsec_stats->out_octets_protected +=
3254                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3255         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3256         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3257         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3258         macsec_stats->in_pkts_unknownsci +=
3259                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3260         macsec_stats->in_octets_decrypted +=
3261                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3262         macsec_stats->in_octets_validated +=
3263                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3264         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3265         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3266         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3267         for (i = 0; i < 2; i++) {
3268                 macsec_stats->in_pkts_ok +=
3269                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3270                 macsec_stats->in_pkts_invalid +=
3271                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3272                 macsec_stats->in_pkts_notvalid +=
3273                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3274         }
3275         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3276         macsec_stats->in_pkts_notusingsa +=
3277                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3278 }
3279
3280 /*
3281  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3282  */
3283 static int
3284 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3285 {
3286         struct ixgbe_hw *hw =
3287                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         struct ixgbe_hw_stats *hw_stats =
3289                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3290         struct ixgbe_macsec_stats *macsec_stats =
3291                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3292                                 dev->data->dev_private);
3293         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3294         unsigned i;
3295
3296         total_missed_rx = 0;
3297         total_qbrc = 0;
3298         total_qprc = 0;
3299         total_qprdc = 0;
3300
3301         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3302                         &total_qbrc, &total_qprc, &total_qprdc);
3303
3304         if (stats == NULL)
3305                 return -EINVAL;
3306
3307         /* Fill out the rte_eth_stats statistics structure */
3308         stats->ipackets = total_qprc;
3309         stats->ibytes = total_qbrc;
3310         stats->opackets = hw_stats->gptc;
3311         stats->obytes = hw_stats->gotc;
3312
3313         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3314                 stats->q_ipackets[i] = hw_stats->qprc[i];
3315                 stats->q_opackets[i] = hw_stats->qptc[i];
3316                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3317                 stats->q_obytes[i] = hw_stats->qbtc[i];
3318                 stats->q_errors[i] = hw_stats->qprdc[i];
3319         }
3320
3321         /* Rx Errors */
3322         stats->imissed  = total_missed_rx;
3323         stats->ierrors  = hw_stats->crcerrs +
3324                           hw_stats->mspdc +
3325                           hw_stats->rlec +
3326                           hw_stats->ruc +
3327                           hw_stats->roc +
3328                           hw_stats->illerrc +
3329                           hw_stats->errbc +
3330                           hw_stats->rfc +
3331                           hw_stats->fccrc +
3332                           hw_stats->fclast;
3333
3334         /* Tx Errors */
3335         stats->oerrors  = 0;
3336         return 0;
3337 }
3338
3339 static int
3340 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3341 {
3342         struct ixgbe_hw_stats *stats =
3343                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3344
3345         /* HW registers are cleared on read */
3346         ixgbe_dev_stats_get(dev, NULL);
3347
3348         /* Reset software totals */
3349         memset(stats, 0, sizeof(*stats));
3350
3351         return 0;
3352 }
3353
3354 /* This function calculates the number of xstats based on the current config */
3355 static unsigned
3356 ixgbe_xstats_calc_num(void) {
3357         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3358                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3359                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3360 }
3361
3362 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3363         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3364 {
3365         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3366         unsigned stat, i, count;
3367
3368         if (xstats_names != NULL) {
3369                 count = 0;
3370
3371                 /* Note: limit >= cnt_stats checked upstream
3372                  * in rte_eth_xstats_names()
3373                  */
3374
3375                 /* Extended stats from ixgbe_hw_stats */
3376                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3377                         strlcpy(xstats_names[count].name,
3378                                 rte_ixgbe_stats_strings[i].name,
3379                                 sizeof(xstats_names[count].name));
3380                         count++;
3381                 }
3382
3383                 /* MACsec Stats */
3384                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3385                         strlcpy(xstats_names[count].name,
3386                                 rte_ixgbe_macsec_strings[i].name,
3387                                 sizeof(xstats_names[count].name));
3388                         count++;
3389                 }
3390
3391                 /* RX Priority Stats */
3392                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3393                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3394                                 snprintf(xstats_names[count].name,
3395                                         sizeof(xstats_names[count].name),
3396                                         "rx_priority%u_%s", i,
3397                                         rte_ixgbe_rxq_strings[stat].name);
3398                                 count++;
3399                         }
3400                 }
3401
3402                 /* TX Priority Stats */
3403                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3404                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3405                                 snprintf(xstats_names[count].name,
3406                                         sizeof(xstats_names[count].name),
3407                                         "tx_priority%u_%s", i,
3408                                         rte_ixgbe_txq_strings[stat].name);
3409                                 count++;
3410                         }
3411                 }
3412         }
3413         return cnt_stats;
3414 }
3415
3416 static int ixgbe_dev_xstats_get_names_by_id(
3417         struct rte_eth_dev *dev,
3418         struct rte_eth_xstat_name *xstats_names,
3419         const uint64_t *ids,
3420         unsigned int limit)
3421 {
3422         if (!ids) {
3423                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3424                 unsigned int stat, i, count;
3425
3426                 if (xstats_names != NULL) {
3427                         count = 0;
3428
3429                         /* Note: limit >= cnt_stats checked upstream
3430                          * in rte_eth_xstats_names()
3431                          */
3432
3433                         /* Extended stats from ixgbe_hw_stats */
3434                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3435                                 strlcpy(xstats_names[count].name,
3436                                         rte_ixgbe_stats_strings[i].name,
3437                                         sizeof(xstats_names[count].name));
3438                                 count++;
3439                         }
3440
3441                         /* MACsec Stats */
3442                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3443                                 strlcpy(xstats_names[count].name,
3444                                         rte_ixgbe_macsec_strings[i].name,
3445                                         sizeof(xstats_names[count].name));
3446                                 count++;
3447                         }
3448
3449                         /* RX Priority Stats */
3450                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3451                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3452                                         snprintf(xstats_names[count].name,
3453                                             sizeof(xstats_names[count].name),
3454                                             "rx_priority%u_%s", i,
3455                                             rte_ixgbe_rxq_strings[stat].name);
3456                                         count++;
3457                                 }
3458                         }
3459
3460                         /* TX Priority Stats */
3461                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3462                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3463                                         snprintf(xstats_names[count].name,
3464                                             sizeof(xstats_names[count].name),
3465                                             "tx_priority%u_%s", i,
3466                                             rte_ixgbe_txq_strings[stat].name);
3467                                         count++;
3468                                 }
3469                         }
3470                 }
3471                 return cnt_stats;
3472         }
3473
3474         uint16_t i;
3475         uint16_t size = ixgbe_xstats_calc_num();
3476         struct rte_eth_xstat_name xstats_names_copy[size];
3477
3478         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3479                         size);
3480
3481         for (i = 0; i < limit; i++) {
3482                 if (ids[i] >= size) {
3483                         PMD_INIT_LOG(ERR, "id value isn't valid");
3484                         return -1;
3485                 }
3486                 strcpy(xstats_names[i].name,
3487                                 xstats_names_copy[ids[i]].name);
3488         }
3489         return limit;
3490 }
3491
3492 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3493         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3494 {
3495         unsigned i;
3496
3497         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3498                 return -ENOMEM;
3499
3500         if (xstats_names != NULL)
3501                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3502                         strlcpy(xstats_names[i].name,
3503                                 rte_ixgbevf_stats_strings[i].name,
3504                                 sizeof(xstats_names[i].name));
3505         return IXGBEVF_NB_XSTATS;
3506 }
3507
3508 static int
3509 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3510                                          unsigned n)
3511 {
3512         struct ixgbe_hw *hw =
3513                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3514         struct ixgbe_hw_stats *hw_stats =
3515                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3516         struct ixgbe_macsec_stats *macsec_stats =
3517                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3518                                 dev->data->dev_private);
3519         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3520         unsigned i, stat, count = 0;
3521
3522         count = ixgbe_xstats_calc_num();
3523
3524         if (n < count)
3525                 return count;
3526
3527         total_missed_rx = 0;
3528         total_qbrc = 0;
3529         total_qprc = 0;
3530         total_qprdc = 0;
3531
3532         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3533                         &total_qbrc, &total_qprc, &total_qprdc);
3534
3535         /* If this is a reset xstats is NULL, and we have cleared the
3536          * registers by reading them.
3537          */
3538         if (!xstats)
3539                 return 0;
3540
3541         /* Extended stats from ixgbe_hw_stats */
3542         count = 0;
3543         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3544                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3545                                 rte_ixgbe_stats_strings[i].offset);
3546                 xstats[count].id = count;
3547                 count++;
3548         }
3549
3550         /* MACsec Stats */
3551         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3552                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3553                                 rte_ixgbe_macsec_strings[i].offset);
3554                 xstats[count].id = count;
3555                 count++;
3556         }
3557
3558         /* RX Priority Stats */
3559         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3560                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3561                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3562                                         rte_ixgbe_rxq_strings[stat].offset +
3563                                         (sizeof(uint64_t) * i));
3564                         xstats[count].id = count;
3565                         count++;
3566                 }
3567         }
3568
3569         /* TX Priority Stats */
3570         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3571                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3572                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3573                                         rte_ixgbe_txq_strings[stat].offset +
3574                                         (sizeof(uint64_t) * i));
3575                         xstats[count].id = count;
3576                         count++;
3577                 }
3578         }
3579         return count;
3580 }
3581
3582 static int
3583 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3584                 uint64_t *values, unsigned int n)
3585 {
3586         if (!ids) {
3587                 struct ixgbe_hw *hw =
3588                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589                 struct ixgbe_hw_stats *hw_stats =
3590                                 IXGBE_DEV_PRIVATE_TO_STATS(
3591                                                 dev->data->dev_private);
3592                 struct ixgbe_macsec_stats *macsec_stats =
3593                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3594                                         dev->data->dev_private);
3595                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3596                 unsigned int i, stat, count = 0;
3597
3598                 count = ixgbe_xstats_calc_num();
3599
3600                 if (!ids && n < count)
3601                         return count;
3602
3603                 total_missed_rx = 0;
3604                 total_qbrc = 0;
3605                 total_qprc = 0;
3606                 total_qprdc = 0;
3607
3608                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3609                                 &total_missed_rx, &total_qbrc, &total_qprc,
3610                                 &total_qprdc);
3611
3612                 /* If this is a reset xstats is NULL, and we have cleared the
3613                  * registers by reading them.
3614                  */
3615                 if (!ids && !values)
3616                         return 0;
3617
3618                 /* Extended stats from ixgbe_hw_stats */
3619                 count = 0;
3620                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3621                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3622                                         rte_ixgbe_stats_strings[i].offset);
3623                         count++;
3624                 }
3625
3626                 /* MACsec Stats */
3627                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3628                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3629                                         rte_ixgbe_macsec_strings[i].offset);
3630                         count++;
3631                 }
3632
3633                 /* RX Priority Stats */
3634                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3635                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3636                                 values[count] =
3637                                         *(uint64_t *)(((char *)hw_stats) +
3638                                         rte_ixgbe_rxq_strings[stat].offset +
3639                                         (sizeof(uint64_t) * i));
3640                                 count++;
3641                         }
3642                 }
3643
3644                 /* TX Priority Stats */
3645                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3646                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3647                                 values[count] =
3648                                         *(uint64_t *)(((char *)hw_stats) +
3649                                         rte_ixgbe_txq_strings[stat].offset +
3650                                         (sizeof(uint64_t) * i));
3651                                 count++;
3652                         }
3653                 }
3654                 return count;
3655         }
3656
3657         uint16_t i;
3658         uint16_t size = ixgbe_xstats_calc_num();
3659         uint64_t values_copy[size];
3660
3661         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3662
3663         for (i = 0; i < n; i++) {
3664                 if (ids[i] >= size) {
3665                         PMD_INIT_LOG(ERR, "id value isn't valid");
3666                         return -1;
3667                 }
3668                 values[i] = values_copy[ids[i]];
3669         }
3670         return n;
3671 }
3672
3673 static int
3674 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3675 {
3676         struct ixgbe_hw_stats *stats =
3677                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3678         struct ixgbe_macsec_stats *macsec_stats =
3679                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3680                                 dev->data->dev_private);
3681
3682         unsigned count = ixgbe_xstats_calc_num();
3683
3684         /* HW registers are cleared on read */
3685         ixgbe_dev_xstats_get(dev, NULL, count);
3686
3687         /* Reset software totals */
3688         memset(stats, 0, sizeof(*stats));
3689         memset(macsec_stats, 0, sizeof(*macsec_stats));
3690
3691         return 0;
3692 }
3693
3694 static void
3695 ixgbevf_update_stats(struct rte_eth_dev *dev)
3696 {
3697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3698         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3699                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3700
3701         /* Good Rx packet, include VF loopback */
3702         UPDATE_VF_STAT(IXGBE_VFGPRC,
3703             hw_stats->last_vfgprc, hw_stats->vfgprc);
3704
3705         /* Good Rx octets, include VF loopback */
3706         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3707             hw_stats->last_vfgorc, hw_stats->vfgorc);
3708
3709         /* Good Tx packet, include VF loopback */
3710         UPDATE_VF_STAT(IXGBE_VFGPTC,
3711             hw_stats->last_vfgptc, hw_stats->vfgptc);
3712
3713         /* Good Tx octets, include VF loopback */
3714         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3715             hw_stats->last_vfgotc, hw_stats->vfgotc);
3716
3717         /* Rx Multicst Packet */
3718         UPDATE_VF_STAT(IXGBE_VFMPRC,
3719             hw_stats->last_vfmprc, hw_stats->vfmprc);
3720 }
3721
3722 static int
3723 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3724                        unsigned n)
3725 {
3726         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3727                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3728         unsigned i;
3729
3730         if (n < IXGBEVF_NB_XSTATS)
3731                 return IXGBEVF_NB_XSTATS;
3732
3733         ixgbevf_update_stats(dev);
3734
3735         if (!xstats)
3736                 return 0;
3737
3738         /* Extended stats */
3739         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3740                 xstats[i].id = i;
3741                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3742                         rte_ixgbevf_stats_strings[i].offset);
3743         }
3744
3745         return IXGBEVF_NB_XSTATS;
3746 }
3747
3748 static int
3749 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3750 {
3751         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3752                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3753
3754         ixgbevf_update_stats(dev);
3755
3756         if (stats == NULL)
3757                 return -EINVAL;
3758
3759         stats->ipackets = hw_stats->vfgprc;
3760         stats->ibytes = hw_stats->vfgorc;
3761         stats->opackets = hw_stats->vfgptc;
3762         stats->obytes = hw_stats->vfgotc;
3763         return 0;
3764 }
3765
3766 static int
3767 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3768 {
3769         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3770                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3771
3772         /* Sync HW register to the last stats */
3773         ixgbevf_dev_stats_get(dev, NULL);
3774
3775         /* reset HW current stats*/
3776         hw_stats->vfgprc = 0;
3777         hw_stats->vfgorc = 0;
3778         hw_stats->vfgptc = 0;
3779         hw_stats->vfgotc = 0;
3780
3781         return 0;
3782 }
3783
3784 static int
3785 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3786 {
3787         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3788         u16 eeprom_verh, eeprom_verl;
3789         u32 etrack_id;
3790         int ret;
3791
3792         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3793         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3794
3795         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3796         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3797
3798         ret += 1; /* add the size of '\0' */
3799         if (fw_size < (u32)ret)
3800                 return ret;
3801         else
3802                 return 0;
3803 }
3804
3805 static int
3806 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3807 {
3808         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3809         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3810         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3811
3812         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3813         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3814         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3815                 /*
3816                  * When DCB/VT is off, maximum number of queues changes,
3817                  * except for 82598EB, which remains constant.
3818                  */
3819                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3820                                 hw->mac.type != ixgbe_mac_82598EB)
3821                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3822         }
3823         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3824         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3825         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3826         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3827         dev_info->max_vfs = pci_dev->max_vfs;
3828         if (hw->mac.type == ixgbe_mac_82598EB)
3829                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3830         else
3831                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3832         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3833         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3834         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3835         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3836         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3837                                      dev_info->rx_queue_offload_capa);
3838         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3839         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3840
3841         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3842                 .rx_thresh = {
3843                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3844                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3845                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3846                 },
3847                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3848                 .rx_drop_en = 0,
3849                 .offloads = 0,
3850         };
3851
3852         dev_info->default_txconf = (struct rte_eth_txconf) {
3853                 .tx_thresh = {
3854                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3855                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3856                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3857                 },
3858                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3859                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3860                 .offloads = 0,
3861         };
3862
3863         dev_info->rx_desc_lim = rx_desc_lim;
3864         dev_info->tx_desc_lim = tx_desc_lim;
3865
3866         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3867         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3868         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3869
3870         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3871         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3872                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3873                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3874                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3875
3876         if (hw->mac.type == ixgbe_mac_X540 ||
3877             hw->mac.type == ixgbe_mac_X540_vf ||
3878             hw->mac.type == ixgbe_mac_X550 ||
3879             hw->mac.type == ixgbe_mac_X550_vf) {
3880                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3881         }
3882         if (hw->mac.type == ixgbe_mac_X550) {
3883                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3884                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3885         }
3886
3887         /* Driver-preferred Rx/Tx parameters */
3888         dev_info->default_rxportconf.burst_size = 32;
3889         dev_info->default_txportconf.burst_size = 32;
3890         dev_info->default_rxportconf.nb_queues = 1;
3891         dev_info->default_txportconf.nb_queues = 1;
3892         dev_info->default_rxportconf.ring_size = 256;
3893         dev_info->default_txportconf.ring_size = 256;
3894
3895         return 0;
3896 }
3897
3898 static const uint32_t *
3899 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3900 {
3901         static const uint32_t ptypes[] = {
3902                 /* For non-vec functions,
3903                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3904                  * for vec functions,
3905                  * refers to _recv_raw_pkts_vec().
3906                  */
3907                 RTE_PTYPE_L2_ETHER,
3908                 RTE_PTYPE_L3_IPV4,
3909                 RTE_PTYPE_L3_IPV4_EXT,
3910                 RTE_PTYPE_L3_IPV6,
3911                 RTE_PTYPE_L3_IPV6_EXT,
3912                 RTE_PTYPE_L4_SCTP,
3913                 RTE_PTYPE_L4_TCP,
3914                 RTE_PTYPE_L4_UDP,
3915                 RTE_PTYPE_TUNNEL_IP,
3916                 RTE_PTYPE_INNER_L3_IPV6,
3917                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3918                 RTE_PTYPE_INNER_L4_TCP,
3919                 RTE_PTYPE_INNER_L4_UDP,
3920                 RTE_PTYPE_UNKNOWN
3921         };
3922
3923         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3924             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3925             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3926             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3927                 return ptypes;
3928
3929 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3930         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3931             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3932                 return ptypes;
3933 #endif
3934         return NULL;
3935 }
3936
3937 static int
3938 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3939                      struct rte_eth_dev_info *dev_info)
3940 {
3941         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3942         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3943
3944         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3945         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3946         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3947         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3948         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3949         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3950         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3951         dev_info->max_vfs = pci_dev->max_vfs;
3952         if (hw->mac.type == ixgbe_mac_82598EB)
3953                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3954         else
3955                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3956         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3957         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3958                                      dev_info->rx_queue_offload_capa);
3959         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3960         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3961         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3962         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3963         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3964
3965         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3966                 .rx_thresh = {
3967                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3968                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3969                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3970                 },
3971                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3972                 .rx_drop_en = 0,
3973                 .offloads = 0,
3974         };
3975
3976         dev_info->default_txconf = (struct rte_eth_txconf) {
3977                 .tx_thresh = {
3978                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3979                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3980                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3981                 },
3982                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3983                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3984                 .offloads = 0,
3985         };
3986
3987         dev_info->rx_desc_lim = rx_desc_lim;
3988         dev_info->tx_desc_lim = tx_desc_lim;
3989
3990         return 0;
3991 }
3992
3993 static int
3994 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3995                    int *link_up, int wait_to_complete)
3996 {
3997         struct ixgbe_adapter *adapter = container_of(hw,
3998                                                      struct ixgbe_adapter, hw);
3999         struct ixgbe_mbx_info *mbx = &hw->mbx;
4000         struct ixgbe_mac_info *mac = &hw->mac;
4001         uint32_t links_reg, in_msg;
4002         int ret_val = 0;
4003
4004         /* If we were hit with a reset drop the link */
4005         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4006                 mac->get_link_status = true;
4007
4008         if (!mac->get_link_status)
4009                 goto out;
4010
4011         /* if link status is down no point in checking to see if pf is up */
4012         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4013         if (!(links_reg & IXGBE_LINKS_UP))
4014                 goto out;
4015
4016         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4017          * before the link status is correct
4018          */
4019         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4020                 int i;
4021
4022                 for (i = 0; i < 5; i++) {
4023                         rte_delay_us(100);
4024                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4025
4026                         if (!(links_reg & IXGBE_LINKS_UP))
4027                                 goto out;
4028                 }
4029         }
4030
4031         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4032         case IXGBE_LINKS_SPEED_10G_82599:
4033                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4034                 if (hw->mac.type >= ixgbe_mac_X550) {
4035                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4036                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4037                 }
4038                 break;
4039         case IXGBE_LINKS_SPEED_1G_82599:
4040                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4041                 break;
4042         case IXGBE_LINKS_SPEED_100_82599:
4043                 *speed = IXGBE_LINK_SPEED_100_FULL;
4044                 if (hw->mac.type == ixgbe_mac_X550) {
4045                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4046                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4047                 }
4048                 break;
4049         case IXGBE_LINKS_SPEED_10_X550EM_A:
4050                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4051                 /* Since Reserved in older MAC's */
4052                 if (hw->mac.type >= ixgbe_mac_X550)
4053                         *speed = IXGBE_LINK_SPEED_10_FULL;
4054                 break;
4055         default:
4056                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4057         }
4058
4059         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4060                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4061                         mac->get_link_status = true;
4062                 else
4063                         mac->get_link_status = false;
4064
4065                 goto out;
4066         }
4067
4068         /* if the read failed it could just be a mailbox collision, best wait
4069          * until we are called again and don't report an error
4070          */
4071         if (mbx->ops.read(hw, &in_msg, 1, 0))
4072                 goto out;
4073
4074         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4075                 /* msg is not CTS and is NACK we must have lost CTS status */
4076                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4077                         mac->get_link_status = false;
4078                 goto out;
4079         }
4080
4081         /* the pf is talking, if we timed out in the past we reinit */
4082         if (!mbx->timeout) {
4083                 ret_val = -1;
4084                 goto out;
4085         }
4086
4087         /* if we passed all the tests above then the link is up and we no
4088          * longer need to check for link
4089          */
4090         mac->get_link_status = false;
4091
4092 out:
4093         *link_up = !mac->get_link_status;
4094         return ret_val;
4095 }
4096
4097 static void
4098 ixgbe_dev_setup_link_alarm_handler(void *param)
4099 {
4100         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102         struct ixgbe_interrupt *intr =
4103                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4104         u32 speed;
4105         bool autoneg = false;
4106
4107         speed = hw->phy.autoneg_advertised;
4108         if (!speed)
4109                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4110
4111         ixgbe_setup_link(hw, speed, true);
4112
4113         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4114 }
4115
4116 /*
4117  * In freebsd environment, nic_uio drivers do not support interrupts,
4118  * rte_intr_callback_register() will fail to register interrupts.
4119  * We can not make link status to change from down to up by interrupt
4120  * callback. So we need to wait for the controller to acquire link
4121  * when ports start.
4122  * It returns 0 on link up.
4123  */
4124 static int
4125 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4126 {
4127 #ifdef RTE_EXEC_ENV_FREEBSD
4128         const int nb_iter = 25;
4129 #else
4130         const int nb_iter = 0;
4131 #endif
4132         int err, i, link_up = 0;
4133         uint32_t speed = 0;
4134
4135         for (i = 0; i < nb_iter; i++) {
4136                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4137                 if (err)
4138                         return err;
4139                 if (link_up)
4140                         return 0;
4141                 msec_delay(200);
4142         }
4143         return 0;
4144 }
4145
4146 /* return 0 means link status changed, -1 means not changed */
4147 int
4148 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4149                             int wait_to_complete, int vf)
4150 {
4151         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4152         struct rte_eth_link link;
4153         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4154         struct ixgbe_interrupt *intr =
4155                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4156         int link_up;
4157         int diag;
4158         int wait = 1;
4159         u32 esdp_reg;
4160
4161         memset(&link, 0, sizeof(link));
4162         link.link_status = ETH_LINK_DOWN;
4163         link.link_speed = ETH_SPEED_NUM_NONE;
4164         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4165         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4166                         ETH_LINK_SPEED_FIXED);
4167
4168         hw->mac.get_link_status = true;
4169
4170         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4171                 return rte_eth_linkstatus_set(dev, &link);
4172
4173         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4174         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4175                 wait = 0;
4176
4177         if (vf)
4178                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4179         else
4180                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4181
4182         if (diag != 0) {
4183                 link.link_speed = ETH_SPEED_NUM_100M;
4184                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4185                 return rte_eth_linkstatus_set(dev, &link);
4186         }
4187
4188         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4189                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4190                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4191                         link_up = 0;
4192         }
4193
4194         if (link_up == 0) {
4195                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4196                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4197                         rte_eal_alarm_set(10,
4198                                 ixgbe_dev_setup_link_alarm_handler, dev);
4199                 }
4200                 return rte_eth_linkstatus_set(dev, &link);
4201         }
4202
4203         link.link_status = ETH_LINK_UP;
4204         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4205
4206         switch (link_speed) {
4207         default:
4208         case IXGBE_LINK_SPEED_UNKNOWN:
4209                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4210                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4211                         link.link_speed = ETH_SPEED_NUM_10M;
4212                 else
4213                         link.link_speed = ETH_SPEED_NUM_100M;
4214                 break;
4215
4216         case IXGBE_LINK_SPEED_100_FULL:
4217                 link.link_speed = ETH_SPEED_NUM_100M;
4218                 break;
4219
4220         case IXGBE_LINK_SPEED_1GB_FULL:
4221                 link.link_speed = ETH_SPEED_NUM_1G;
4222                 break;
4223
4224         case IXGBE_LINK_SPEED_2_5GB_FULL:
4225                 link.link_speed = ETH_SPEED_NUM_2_5G;
4226                 break;
4227
4228         case IXGBE_LINK_SPEED_5GB_FULL:
4229                 link.link_speed = ETH_SPEED_NUM_5G;
4230                 break;
4231
4232         case IXGBE_LINK_SPEED_10GB_FULL:
4233                 link.link_speed = ETH_SPEED_NUM_10G;
4234                 break;
4235         }
4236
4237         return rte_eth_linkstatus_set(dev, &link);
4238 }
4239
4240 static int
4241 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4242 {
4243         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4244 }
4245
4246 static int
4247 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4248 {
4249         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4250 }
4251
4252 static int
4253 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4254 {
4255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4256         uint32_t fctrl;
4257
4258         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4259         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4260         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4261
4262         return 0;
4263 }
4264
4265 static int
4266 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4267 {
4268         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4269         uint32_t fctrl;
4270
4271         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4272         fctrl &= (~IXGBE_FCTRL_UPE);
4273         if (dev->data->all_multicast == 1)
4274                 fctrl |= IXGBE_FCTRL_MPE;
4275         else
4276                 fctrl &= (~IXGBE_FCTRL_MPE);
4277         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4278
4279         return 0;
4280 }
4281
4282 static int
4283 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4284 {
4285         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4286         uint32_t fctrl;
4287
4288         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4289         fctrl |= IXGBE_FCTRL_MPE;
4290         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4291
4292         return 0;
4293 }
4294
4295 static int
4296 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4297 {
4298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4299         uint32_t fctrl;
4300
4301         if (dev->data->promiscuous == 1)
4302                 return 0; /* must remain in all_multicast mode */
4303
4304         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4305         fctrl &= (~IXGBE_FCTRL_MPE);
4306         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4307
4308         return 0;
4309 }
4310
4311 /**
4312  * It clears the interrupt causes and enables the interrupt.
4313  * It will be called once only during nic initialized.
4314  *
4315  * @param dev
4316  *  Pointer to struct rte_eth_dev.
4317  * @param on
4318  *  Enable or Disable.
4319  *
4320  * @return
4321  *  - On success, zero.
4322  *  - On failure, a negative value.
4323  */
4324 static int
4325 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4326 {
4327         struct ixgbe_interrupt *intr =
4328                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4329
4330         ixgbe_dev_link_status_print(dev);
4331         if (on)
4332                 intr->mask |= IXGBE_EICR_LSC;
4333         else
4334                 intr->mask &= ~IXGBE_EICR_LSC;
4335
4336         return 0;
4337 }
4338
4339 /**
4340  * It clears the interrupt causes and enables the interrupt.
4341  * It will be called once only during nic initialized.
4342  *
4343  * @param dev
4344  *  Pointer to struct rte_eth_dev.
4345  *
4346  * @return
4347  *  - On success, zero.
4348  *  - On failure, a negative value.
4349  */
4350 static int
4351 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4352 {
4353         struct ixgbe_interrupt *intr =
4354                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4355
4356         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4357
4358         return 0;
4359 }
4360
4361 /**
4362  * It clears the interrupt causes and enables the interrupt.
4363  * It will be called once only during nic initialized.
4364  *
4365  * @param dev
4366  *  Pointer to struct rte_eth_dev.
4367  *
4368  * @return
4369  *  - On success, zero.
4370  *  - On failure, a negative value.
4371  */
4372 static int
4373 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4374 {
4375         struct ixgbe_interrupt *intr =
4376                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4377
4378         intr->mask |= IXGBE_EICR_LINKSEC;
4379
4380         return 0;
4381 }
4382
4383 /*
4384  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4385  *
4386  * @param dev
4387  *  Pointer to struct rte_eth_dev.
4388  *
4389  * @return
4390  *  - On success, zero.
4391  *  - On failure, a negative value.
4392  */
4393 static int
4394 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4395 {
4396         uint32_t eicr;
4397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4398         struct ixgbe_interrupt *intr =
4399                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4400
4401         /* clear all cause mask */
4402         ixgbe_disable_intr(hw);
4403
4404         /* read-on-clear nic registers here */
4405         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4406         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4407
4408         intr->flags = 0;
4409
4410         /* set flag for async link update */
4411         if (eicr & IXGBE_EICR_LSC)
4412                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4413
4414         if (eicr & IXGBE_EICR_MAILBOX)
4415                 intr->flags |= IXGBE_FLAG_MAILBOX;
4416
4417         if (eicr & IXGBE_EICR_LINKSEC)
4418                 intr->flags |= IXGBE_FLAG_MACSEC;
4419
4420         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4421             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4422             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4423                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4424
4425         return 0;
4426 }
4427
4428 /**
4429  * It gets and then prints the link status.
4430  *
4431  * @param dev
4432  *  Pointer to struct rte_eth_dev.
4433  *
4434  * @return
4435  *  - On success, zero.
4436  *  - On failure, a negative value.
4437  */
4438 static void
4439 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4440 {
4441         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4442         struct rte_eth_link link;
4443
4444         rte_eth_linkstatus_get(dev, &link);
4445
4446         if (link.link_status) {
4447                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4448                                         (int)(dev->data->port_id),
4449                                         (unsigned)link.link_speed,
4450                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4451                                         "full-duplex" : "half-duplex");
4452         } else {
4453                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4454                                 (int)(dev->data->port_id));
4455         }
4456         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4457                                 pci_dev->addr.domain,
4458                                 pci_dev->addr.bus,
4459                                 pci_dev->addr.devid,
4460                                 pci_dev->addr.function);
4461 }
4462
4463 /*
4464  * It executes link_update after knowing an interrupt occurred.
4465  *
4466  * @param dev
4467  *  Pointer to struct rte_eth_dev.
4468  *
4469  * @return
4470  *  - On success, zero.
4471  *  - On failure, a negative value.
4472  */
4473 static int
4474 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4475 {
4476         struct ixgbe_interrupt *intr =
4477                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4478         int64_t timeout;
4479         struct ixgbe_hw *hw =
4480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481
4482         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4483
4484         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4485                 ixgbe_pf_mbx_process(dev);
4486                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4487         }
4488
4489         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4490                 ixgbe_handle_lasi(hw);
4491                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4492         }
4493
4494         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4495                 struct rte_eth_link link;
4496
4497                 /* get the link status before link update, for predicting later */
4498                 rte_eth_linkstatus_get(dev, &link);
4499
4500                 ixgbe_dev_link_update(dev, 0);
4501
4502                 /* likely to up */
4503                 if (!link.link_status)
4504                         /* handle it 1 sec later, wait it being stable */
4505                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4506                 /* likely to down */
4507                 else
4508                         /* handle it 4 sec later, wait it being stable */
4509                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4510
4511                 ixgbe_dev_link_status_print(dev);
4512                 if (rte_eal_alarm_set(timeout * 1000,
4513                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4514                         PMD_DRV_LOG(ERR, "Error setting alarm");
4515                 else {
4516                         /* remember original mask */
4517                         intr->mask_original = intr->mask;
4518                         /* only disable lsc interrupt */
4519                         intr->mask &= ~IXGBE_EIMS_LSC;
4520                 }
4521         }
4522
4523         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4524         ixgbe_enable_intr(dev);
4525
4526         return 0;
4527 }
4528
4529 /**
4530  * Interrupt handler which shall be registered for alarm callback for delayed
4531  * handling specific interrupt to wait for the stable nic state. As the
4532  * NIC interrupt state is not stable for ixgbe after link is just down,
4533  * it needs to wait 4 seconds to get the stable status.
4534  *
4535  * @param handle
4536  *  Pointer to interrupt handle.
4537  * @param param
4538  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4539  *
4540  * @return
4541  *  void
4542  */
4543 static void
4544 ixgbe_dev_interrupt_delayed_handler(void *param)
4545 {
4546         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4547         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4549         struct ixgbe_interrupt *intr =
4550                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4551         struct ixgbe_hw *hw =
4552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553         uint32_t eicr;
4554
4555         ixgbe_disable_intr(hw);
4556
4557         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4558         if (eicr & IXGBE_EICR_MAILBOX)
4559                 ixgbe_pf_mbx_process(dev);
4560
4561         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4562                 ixgbe_handle_lasi(hw);
4563                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4564         }
4565
4566         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4567                 ixgbe_dev_link_update(dev, 0);
4568                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4569                 ixgbe_dev_link_status_print(dev);
4570                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4571                                               NULL);
4572         }
4573
4574         if (intr->flags & IXGBE_FLAG_MACSEC) {
4575                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4576                                               NULL);
4577                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4578         }
4579
4580         /* restore original mask */
4581         intr->mask = intr->mask_original;
4582         intr->mask_original = 0;
4583
4584         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4585         ixgbe_enable_intr(dev);
4586         rte_intr_ack(intr_handle);
4587 }
4588
4589 /**
4590  * Interrupt handler triggered by NIC  for handling
4591  * specific interrupt.
4592  *
4593  * @param handle
4594  *  Pointer to interrupt handle.
4595  * @param param
4596  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4597  *
4598  * @return
4599  *  void
4600  */
4601 static void
4602 ixgbe_dev_interrupt_handler(void *param)
4603 {
4604         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4605
4606         ixgbe_dev_interrupt_get_status(dev);
4607         ixgbe_dev_interrupt_action(dev);
4608 }
4609
4610 static int
4611 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4612 {
4613         struct ixgbe_hw *hw;
4614
4615         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4617 }
4618
4619 static int
4620 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4621 {
4622         struct ixgbe_hw *hw;
4623
4624         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4625         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4626 }
4627
4628 static int
4629 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4630 {
4631         struct ixgbe_hw *hw;
4632         uint32_t mflcn_reg;
4633         uint32_t fccfg_reg;
4634         int rx_pause;
4635         int tx_pause;
4636
4637         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4638
4639         fc_conf->pause_time = hw->fc.pause_time;
4640         fc_conf->high_water = hw->fc.high_water[0];
4641         fc_conf->low_water = hw->fc.low_water[0];
4642         fc_conf->send_xon = hw->fc.send_xon;
4643         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4644
4645         /*
4646          * Return rx_pause status according to actual setting of
4647          * MFLCN register.
4648          */
4649         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4650         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4651                 rx_pause = 1;
4652         else
4653                 rx_pause = 0;
4654
4655         /*
4656          * Return tx_pause status according to actual setting of
4657          * FCCFG register.
4658          */
4659         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4660         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4661                 tx_pause = 1;
4662         else
4663                 tx_pause = 0;
4664
4665         if (rx_pause && tx_pause)
4666                 fc_conf->mode = RTE_FC_FULL;
4667         else if (rx_pause)
4668                 fc_conf->mode = RTE_FC_RX_PAUSE;
4669         else if (tx_pause)
4670                 fc_conf->mode = RTE_FC_TX_PAUSE;
4671         else
4672                 fc_conf->mode = RTE_FC_NONE;
4673
4674         return 0;
4675 }
4676
4677 static int
4678 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4679 {
4680         struct ixgbe_hw *hw;
4681         int err;
4682         uint32_t rx_buf_size;
4683         uint32_t max_high_water;
4684         uint32_t mflcn;
4685         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4686                 ixgbe_fc_none,
4687                 ixgbe_fc_rx_pause,
4688                 ixgbe_fc_tx_pause,
4689                 ixgbe_fc_full
4690         };
4691
4692         PMD_INIT_FUNC_TRACE();
4693
4694         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4696         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4697
4698         /*
4699          * At least reserve one Ethernet frame for watermark
4700          * high_water/low_water in kilo bytes for ixgbe
4701          */
4702         max_high_water = (rx_buf_size -
4703                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4704         if ((fc_conf->high_water > max_high_water) ||
4705                 (fc_conf->high_water < fc_conf->low_water)) {
4706                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4707                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4708                 return -EINVAL;
4709         }
4710
4711         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4712         hw->fc.pause_time     = fc_conf->pause_time;
4713         hw->fc.high_water[0]  = fc_conf->high_water;
4714         hw->fc.low_water[0]   = fc_conf->low_water;
4715         hw->fc.send_xon       = fc_conf->send_xon;
4716         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4717
4718         err = ixgbe_fc_enable(hw);
4719
4720         /* Not negotiated is not an error case */
4721         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4722
4723                 /* check if we want to forward MAC frames - driver doesn't have native
4724                  * capability to do that, so we'll write the registers ourselves */
4725
4726                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4727
4728                 /* set or clear MFLCN.PMCF bit depending on configuration */
4729                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4730                         mflcn |= IXGBE_MFLCN_PMCF;
4731                 else
4732                         mflcn &= ~IXGBE_MFLCN_PMCF;
4733
4734                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4735                 IXGBE_WRITE_FLUSH(hw);
4736
4737                 return 0;
4738         }
4739
4740         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4741         return -EIO;
4742 }
4743
4744 /**
4745  *  ixgbe_pfc_enable_generic - Enable flow control
4746  *  @hw: pointer to hardware structure
4747  *  @tc_num: traffic class number
4748  *  Enable flow control according to the current settings.
4749  */
4750 static int
4751 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4752 {
4753         int ret_val = 0;
4754         uint32_t mflcn_reg, fccfg_reg;
4755         uint32_t reg;
4756         uint32_t fcrtl, fcrth;
4757         uint8_t i;
4758         uint8_t nb_rx_en;
4759
4760         /* Validate the water mark configuration */
4761         if (!hw->fc.pause_time) {
4762                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4763                 goto out;
4764         }
4765
4766         /* Low water mark of zero causes XOFF floods */
4767         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4768                  /* High/Low water can not be 0 */
4769                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4770                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4771                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4772                         goto out;
4773                 }
4774
4775                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4776                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4777                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4778                         goto out;
4779                 }
4780         }
4781         /* Negotiate the fc mode to use */
4782         ixgbe_fc_autoneg(hw);
4783
4784         /* Disable any previous flow control settings */
4785         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4786         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4787
4788         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4789         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4790
4791         switch (hw->fc.current_mode) {
4792         case ixgbe_fc_none:
4793                 /*
4794                  * If the count of enabled RX Priority Flow control >1,
4795                  * and the TX pause can not be disabled
4796                  */
4797                 nb_rx_en = 0;
4798                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4799                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4800                         if (reg & IXGBE_FCRTH_FCEN)
4801                                 nb_rx_en++;
4802                 }
4803                 if (nb_rx_en > 1)
4804                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4805                 break;
4806         case ixgbe_fc_rx_pause:
4807                 /*
4808                  * Rx Flow control is enabled and Tx Flow control is
4809                  * disabled by software override. Since there really
4810                  * isn't a way to advertise that we are capable of RX
4811                  * Pause ONLY, we will advertise that we support both
4812                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4813                  * disable the adapter's ability to send PAUSE frames.
4814                  */
4815                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4816                 /*
4817                  * If the count of enabled RX Priority Flow control >1,
4818                  * and the TX pause can not be disabled
4819                  */
4820                 nb_rx_en = 0;
4821                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4822                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4823                         if (reg & IXGBE_FCRTH_FCEN)
4824                                 nb_rx_en++;
4825                 }
4826                 if (nb_rx_en > 1)
4827                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4828                 break;
4829         case ixgbe_fc_tx_pause:
4830                 /*
4831                  * Tx Flow control is enabled, and Rx Flow control is
4832                  * disabled by software override.
4833                  */
4834                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4835                 break;
4836         case ixgbe_fc_full:
4837                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4838                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4839                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4840                 break;
4841         default:
4842                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4843                 ret_val = IXGBE_ERR_CONFIG;
4844                 goto out;
4845         }
4846
4847         /* Set 802.3x based flow control settings. */
4848         mflcn_reg |= IXGBE_MFLCN_DPF;
4849         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4850         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4851
4852         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4853         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4854                 hw->fc.high_water[tc_num]) {
4855                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4856                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4857                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4858         } else {
4859                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4860                 /*
4861                  * In order to prevent Tx hangs when the internal Tx
4862                  * switch is enabled we must set the high water mark
4863                  * to the maximum FCRTH value.  This allows the Tx
4864                  * switch to function even under heavy Rx workloads.
4865                  */
4866                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4867         }
4868         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4869
4870         /* Configure pause time (2 TCs per register) */
4871         reg = hw->fc.pause_time * 0x00010001;
4872         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4873                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4874
4875         /* Configure flow control refresh threshold value */
4876         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4877
4878 out:
4879         return ret_val;
4880 }
4881
4882 static int
4883 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4884 {
4885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4887
4888         if (hw->mac.type != ixgbe_mac_82598EB) {
4889                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4890         }
4891         return ret_val;
4892 }
4893
4894 static int
4895 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4896 {
4897         int err;
4898         uint32_t rx_buf_size;
4899         uint32_t max_high_water;
4900         uint8_t tc_num;
4901         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4902         struct ixgbe_hw *hw =
4903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4904         struct ixgbe_dcb_config *dcb_config =
4905                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4906
4907         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4908                 ixgbe_fc_none,
4909                 ixgbe_fc_rx_pause,
4910                 ixgbe_fc_tx_pause,
4911                 ixgbe_fc_full
4912         };
4913
4914         PMD_INIT_FUNC_TRACE();
4915
4916         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4917         tc_num = map[pfc_conf->priority];
4918         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4919         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4920         /*
4921          * At least reserve one Ethernet frame for watermark
4922          * high_water/low_water in kilo bytes for ixgbe
4923          */
4924         max_high_water = (rx_buf_size -
4925                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4926         if ((pfc_conf->fc.high_water > max_high_water) ||
4927             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4928                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4929                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4930                 return -EINVAL;
4931         }
4932
4933         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4934         hw->fc.pause_time = pfc_conf->fc.pause_time;
4935         hw->fc.send_xon = pfc_conf->fc.send_xon;
4936         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4937         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4938
4939         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4940
4941         /* Not negotiated is not an error case */
4942         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4943                 return 0;
4944
4945         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4946         return -EIO;
4947 }
4948
4949 static int
4950 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4951                           struct rte_eth_rss_reta_entry64 *reta_conf,
4952                           uint16_t reta_size)
4953 {
4954         uint16_t i, sp_reta_size;
4955         uint8_t j, mask;
4956         uint32_t reta, r;
4957         uint16_t idx, shift;
4958         struct ixgbe_adapter *adapter = dev->data->dev_private;
4959         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4960         uint32_t reta_reg;
4961
4962         PMD_INIT_FUNC_TRACE();
4963
4964         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4965                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4966                         "NIC.");
4967                 return -ENOTSUP;
4968         }
4969
4970         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4971         if (reta_size != sp_reta_size) {
4972                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4973                         "(%d) doesn't match the number hardware can supported "
4974                         "(%d)", reta_size, sp_reta_size);
4975                 return -EINVAL;
4976         }
4977
4978         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4979                 idx = i / RTE_RETA_GROUP_SIZE;
4980                 shift = i % RTE_RETA_GROUP_SIZE;
4981                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4982                                                 IXGBE_4_BIT_MASK);
4983                 if (!mask)
4984                         continue;
4985                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4986                 if (mask == IXGBE_4_BIT_MASK)
4987                         r = 0;
4988                 else
4989                         r = IXGBE_READ_REG(hw, reta_reg);
4990                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4991                         if (mask & (0x1 << j))
4992                                 reta |= reta_conf[idx].reta[shift + j] <<
4993                                                         (CHAR_BIT * j);
4994                         else
4995                                 reta |= r & (IXGBE_8_BIT_MASK <<
4996                                                 (CHAR_BIT * j));
4997                 }
4998                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4999         }
5000         adapter->rss_reta_updated = 1;
5001
5002         return 0;
5003 }
5004
5005 static int
5006 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5007                          struct rte_eth_rss_reta_entry64 *reta_conf,
5008                          uint16_t reta_size)
5009 {
5010         uint16_t i, sp_reta_size;
5011         uint8_t j, mask;
5012         uint32_t reta;
5013         uint16_t idx, shift;
5014         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5015         uint32_t reta_reg;
5016
5017         PMD_INIT_FUNC_TRACE();
5018         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5019         if (reta_size != sp_reta_size) {
5020                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5021                         "(%d) doesn't match the number hardware can supported "
5022                         "(%d)", reta_size, sp_reta_size);
5023                 return -EINVAL;
5024         }
5025
5026         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5027                 idx = i / RTE_RETA_GROUP_SIZE;
5028                 shift = i % RTE_RETA_GROUP_SIZE;
5029                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5030                                                 IXGBE_4_BIT_MASK);
5031                 if (!mask)
5032                         continue;
5033
5034                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5035                 reta = IXGBE_READ_REG(hw, reta_reg);
5036                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5037                         if (mask & (0x1 << j))
5038                                 reta_conf[idx].reta[shift + j] =
5039                                         ((reta >> (CHAR_BIT * j)) &
5040                                                 IXGBE_8_BIT_MASK);
5041                 }
5042         }
5043
5044         return 0;
5045 }
5046
5047 static int
5048 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5049                                 uint32_t index, uint32_t pool)
5050 {
5051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5052         uint32_t enable_addr = 1;
5053
5054         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5055                              pool, enable_addr);
5056 }
5057
5058 static void
5059 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5060 {
5061         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5062
5063         ixgbe_clear_rar(hw, index);
5064 }
5065
5066 static int
5067 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5068 {
5069         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5070
5071         ixgbe_remove_rar(dev, 0);
5072         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5073
5074         return 0;
5075 }
5076
5077 static bool
5078 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5079 {
5080         if (strcmp(dev->device->driver->name, drv->driver.name))
5081                 return false;
5082
5083         return true;
5084 }
5085
5086 bool
5087 is_ixgbe_supported(struct rte_eth_dev *dev)
5088 {
5089         return is_device_supported(dev, &rte_ixgbe_pmd);
5090 }
5091
5092 static int
5093 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5094 {
5095         uint32_t hlreg0;
5096         uint32_t maxfrs;
5097         struct ixgbe_hw *hw;
5098         struct rte_eth_dev_info dev_info;
5099         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5100         struct rte_eth_dev_data *dev_data = dev->data;
5101         int ret;
5102
5103         ret = ixgbe_dev_info_get(dev, &dev_info);
5104         if (ret != 0)
5105                 return ret;
5106
5107         /* check that mtu is within the allowed range */
5108         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5109                 return -EINVAL;
5110
5111         /* If device is started, refuse mtu that requires the support of
5112          * scattered packets when this feature has not been enabled before.
5113          */
5114         if (dev_data->dev_started && !dev_data->scattered_rx &&
5115             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5116              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5117                 PMD_INIT_LOG(ERR, "Stop port first.");
5118                 return -EINVAL;
5119         }
5120
5121         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5123
5124         /* switch to jumbo mode if needed */
5125         if (frame_size > RTE_ETHER_MAX_LEN) {
5126                 dev->data->dev_conf.rxmode.offloads |=
5127                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5128                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5129         } else {
5130                 dev->data->dev_conf.rxmode.offloads &=
5131                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5132                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5133         }
5134         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5135
5136         /* update max frame size */
5137         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5138
5139         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5140         maxfrs &= 0x0000FFFF;
5141         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5142         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5143
5144         return 0;
5145 }
5146
5147 /*
5148  * Virtual Function operations
5149  */
5150 static void
5151 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5152 {
5153         struct ixgbe_interrupt *intr =
5154                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5155         struct ixgbe_hw *hw =
5156                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5157
5158         PMD_INIT_FUNC_TRACE();
5159
5160         /* Clear interrupt mask to stop from interrupts being generated */
5161         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5162
5163         IXGBE_WRITE_FLUSH(hw);
5164
5165         /* Clear mask value. */
5166         intr->mask = 0;
5167 }
5168
5169 static void
5170 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5171 {
5172         struct ixgbe_interrupt *intr =
5173                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5174         struct ixgbe_hw *hw =
5175                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5176
5177         PMD_INIT_FUNC_TRACE();
5178
5179         /* VF enable interrupt autoclean */
5180         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5181         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5182         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5183
5184         IXGBE_WRITE_FLUSH(hw);
5185
5186         /* Save IXGBE_VTEIMS value to mask. */
5187         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5188 }
5189
5190 static int
5191 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5192 {
5193         struct rte_eth_conf *conf = &dev->data->dev_conf;
5194         struct ixgbe_adapter *adapter = dev->data->dev_private;
5195
5196         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5197                      dev->data->port_id);
5198
5199         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5200                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5201
5202         /*
5203          * VF has no ability to enable/disable HW CRC
5204          * Keep the persistent behavior the same as Host PF
5205          */
5206 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5207         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5208                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5209                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5210         }
5211 #else
5212         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5213                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5214                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5215         }
5216 #endif
5217
5218         /*
5219          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5220          * allocation or vector Rx preconditions we will reset it.
5221          */
5222         adapter->rx_bulk_alloc_allowed = true;
5223         adapter->rx_vec_allowed = true;
5224
5225         return 0;
5226 }
5227
5228 static int
5229 ixgbevf_dev_start(struct rte_eth_dev *dev)
5230 {
5231         struct ixgbe_hw *hw =
5232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5233         uint32_t intr_vector = 0;
5234         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5235         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5236
5237         int err, mask = 0;
5238
5239         PMD_INIT_FUNC_TRACE();
5240
5241         /* Stop the link setup handler before resetting the HW. */
5242         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5243
5244         err = hw->mac.ops.reset_hw(hw);
5245         if (err) {
5246                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5247                 return err;
5248         }
5249         hw->mac.get_link_status = true;
5250
5251         /* negotiate mailbox API version to use with the PF. */
5252         ixgbevf_negotiate_api(hw);
5253
5254         ixgbevf_dev_tx_init(dev);
5255
5256         /* This can fail when allocating mbufs for descriptor rings */
5257         err = ixgbevf_dev_rx_init(dev);
5258         if (err) {
5259                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5260                 ixgbe_dev_clear_queues(dev);
5261                 return err;
5262         }
5263
5264         /* Set vfta */
5265         ixgbevf_set_vfta_all(dev, 1);
5266
5267         /* Set HW strip */
5268         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5269                 ETH_VLAN_EXTEND_MASK;
5270         err = ixgbevf_vlan_offload_config(dev, mask);
5271         if (err) {
5272                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5273                 ixgbe_dev_clear_queues(dev);
5274                 return err;
5275         }
5276
5277         ixgbevf_dev_rxtx_start(dev);
5278
5279         /* check and configure queue intr-vector mapping */
5280         if (rte_intr_cap_multiple(intr_handle) &&
5281             dev->data->dev_conf.intr_conf.rxq) {
5282                 /* According to datasheet, only vector 0/1/2 can be used,
5283                  * now only one vector is used for Rx queue
5284                  */
5285                 intr_vector = 1;
5286                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5287                         return -1;
5288         }
5289
5290         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5291                 intr_handle->intr_vec =
5292                         rte_zmalloc("intr_vec",
5293                                     dev->data->nb_rx_queues * sizeof(int), 0);
5294                 if (intr_handle->intr_vec == NULL) {
5295                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5296                                      " intr_vec", dev->data->nb_rx_queues);
5297                         return -ENOMEM;
5298                 }
5299         }
5300         ixgbevf_configure_msix(dev);
5301
5302         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5303          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5304          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5305          * is not cleared, it will fail when following rte_intr_enable( ) tries
5306          * to map Rx queue interrupt to other VFIO vectors.
5307          * So clear uio/vfio intr/evevnfd first to avoid failure.
5308          */
5309         rte_intr_disable(intr_handle);
5310
5311         rte_intr_enable(intr_handle);
5312
5313         /* Re-enable interrupt for VF */
5314         ixgbevf_intr_enable(dev);
5315
5316         /*
5317          * Update link status right before return, because it may
5318          * start link configuration process in a separate thread.
5319          */
5320         ixgbevf_dev_link_update(dev, 0);
5321
5322         hw->adapter_stopped = false;
5323
5324         return 0;
5325 }
5326
5327 static void
5328 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5329 {
5330         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5331         struct ixgbe_adapter *adapter = dev->data->dev_private;
5332         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5333         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5334
5335         if (hw->adapter_stopped)
5336                 return;
5337
5338         PMD_INIT_FUNC_TRACE();
5339
5340         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5341
5342         ixgbevf_intr_disable(dev);
5343
5344         hw->adapter_stopped = 1;
5345         ixgbe_stop_adapter(hw);
5346
5347         /*
5348           * Clear what we set, but we still keep shadow_vfta to
5349           * restore after device starts
5350           */
5351         ixgbevf_set_vfta_all(dev, 0);
5352
5353         /* Clear stored conf */
5354         dev->data->scattered_rx = 0;
5355
5356         ixgbe_dev_clear_queues(dev);
5357
5358         /* Clean datapath event and queue/vec mapping */
5359         rte_intr_efd_disable(intr_handle);
5360         if (intr_handle->intr_vec != NULL) {
5361                 rte_free(intr_handle->intr_vec);
5362                 intr_handle->intr_vec = NULL;
5363         }
5364
5365         adapter->rss_reta_updated = 0;
5366 }
5367
5368 static void
5369 ixgbevf_dev_close(struct rte_eth_dev *dev)
5370 {
5371         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5372         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5373         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5374
5375         PMD_INIT_FUNC_TRACE();
5376
5377         ixgbe_reset_hw(hw);
5378
5379         ixgbevf_dev_stop(dev);
5380
5381         ixgbe_dev_free_queues(dev);
5382
5383         /**
5384          * Remove the VF MAC address ro ensure
5385          * that the VF traffic goes to the PF
5386          * after stop, close and detach of the VF
5387          **/
5388         ixgbevf_remove_mac_addr(dev, 0);
5389
5390         dev->dev_ops = NULL;
5391         dev->rx_pkt_burst = NULL;
5392         dev->tx_pkt_burst = NULL;
5393
5394         rte_intr_disable(intr_handle);
5395         rte_intr_callback_unregister(intr_handle,
5396                                      ixgbevf_dev_interrupt_handler, dev);
5397 }
5398
5399 /*
5400  * Reset VF device
5401  */
5402 static int
5403 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5404 {
5405         int ret;
5406
5407         ret = eth_ixgbevf_dev_uninit(dev);
5408         if (ret)
5409                 return ret;
5410
5411         ret = eth_ixgbevf_dev_init(dev);
5412
5413         return ret;
5414 }
5415
5416 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5417 {
5418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419         struct ixgbe_vfta *shadow_vfta =
5420                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5421         int i = 0, j = 0, vfta = 0, mask = 1;
5422
5423         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5424                 vfta = shadow_vfta->vfta[i];
5425                 if (vfta) {
5426                         mask = 1;
5427                         for (j = 0; j < 32; j++) {
5428                                 if (vfta & mask)
5429                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5430                                                        on, false);
5431                                 mask <<= 1;
5432                         }
5433                 }
5434         }
5435
5436 }
5437
5438 static int
5439 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5440 {
5441         struct ixgbe_hw *hw =
5442                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5443         struct ixgbe_vfta *shadow_vfta =
5444                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5445         uint32_t vid_idx = 0;
5446         uint32_t vid_bit = 0;
5447         int ret = 0;
5448
5449         PMD_INIT_FUNC_TRACE();
5450
5451         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5452         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5453         if (ret) {
5454                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5455                 return ret;
5456         }
5457         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5458         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5459
5460         /* Save what we set and retore it after device reset */
5461         if (on)
5462                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5463         else
5464                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5465
5466         return 0;
5467 }
5468
5469 static void
5470 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5471 {
5472         struct ixgbe_hw *hw =
5473                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5474         uint32_t ctrl;
5475
5476         PMD_INIT_FUNC_TRACE();
5477
5478         if (queue >= hw->mac.max_rx_queues)
5479                 return;
5480
5481         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5482         if (on)
5483                 ctrl |= IXGBE_RXDCTL_VME;
5484         else
5485                 ctrl &= ~IXGBE_RXDCTL_VME;
5486         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5487
5488         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5489 }
5490
5491 static int
5492 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5493 {
5494         struct ixgbe_rx_queue *rxq;
5495         uint16_t i;
5496         int on = 0;
5497
5498         /* VF function only support hw strip feature, others are not support */
5499         if (mask & ETH_VLAN_STRIP_MASK) {
5500                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5501                         rxq = dev->data->rx_queues[i];
5502                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5503                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5504                 }
5505         }
5506
5507         return 0;
5508 }
5509
5510 static int
5511 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5512 {
5513         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5514
5515         ixgbevf_vlan_offload_config(dev, mask);
5516
5517         return 0;
5518 }
5519
5520 int
5521 ixgbe_vt_check(struct ixgbe_hw *hw)
5522 {
5523         uint32_t reg_val;
5524
5525         /* if Virtualization Technology is enabled */
5526         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5527         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5528                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5529                 return -1;
5530         }
5531
5532         return 0;
5533 }
5534
5535 static uint32_t
5536 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5537 {
5538         uint32_t vector = 0;
5539
5540         switch (hw->mac.mc_filter_type) {
5541         case 0:   /* use bits [47:36] of the address */
5542                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5543                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5544                 break;
5545         case 1:   /* use bits [46:35] of the address */
5546                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5547                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5548                 break;
5549         case 2:   /* use bits [45:34] of the address */
5550                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5551                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5552                 break;
5553         case 3:   /* use bits [43:32] of the address */
5554                 vector = ((uc_addr->addr_bytes[4]) |
5555                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5556                 break;
5557         default:  /* Invalid mc_filter_type */
5558                 break;
5559         }
5560
5561         /* vector can only be 12-bits or boundary will be exceeded */
5562         vector &= 0xFFF;
5563         return vector;
5564 }
5565
5566 static int
5567 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5568                         struct rte_ether_addr *mac_addr, uint8_t on)
5569 {
5570         uint32_t vector;
5571         uint32_t uta_idx;
5572         uint32_t reg_val;
5573         uint32_t uta_shift;
5574         uint32_t rc;
5575         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5576         const uint32_t ixgbe_uta_bit_shift = 5;
5577         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5578         const uint32_t bit1 = 0x1;
5579
5580         struct ixgbe_hw *hw =
5581                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5582         struct ixgbe_uta_info *uta_info =
5583                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5584
5585         /* The UTA table only exists on 82599 hardware and newer */
5586         if (hw->mac.type < ixgbe_mac_82599EB)
5587                 return -ENOTSUP;
5588
5589         vector = ixgbe_uta_vector(hw, mac_addr);
5590         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5591         uta_shift = vector & ixgbe_uta_bit_mask;
5592
5593         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5594         if (rc == on)
5595                 return 0;
5596
5597         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5598         if (on) {
5599                 uta_info->uta_in_use++;
5600                 reg_val |= (bit1 << uta_shift);
5601                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5602         } else {
5603                 uta_info->uta_in_use--;
5604                 reg_val &= ~(bit1 << uta_shift);
5605                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5606         }
5607
5608         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5609
5610         if (uta_info->uta_in_use > 0)
5611                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5612                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5613         else
5614                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5615
5616         return 0;
5617 }
5618
5619 static int
5620 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5621 {
5622         int i;
5623         struct ixgbe_hw *hw =
5624                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5625         struct ixgbe_uta_info *uta_info =
5626                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5627
5628         /* The UTA table only exists on 82599 hardware and newer */
5629         if (hw->mac.type < ixgbe_mac_82599EB)
5630                 return -ENOTSUP;
5631
5632         if (on) {
5633                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5634                         uta_info->uta_shadow[i] = ~0;
5635                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5636                 }
5637         } else {
5638                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5639                         uta_info->uta_shadow[i] = 0;
5640                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5641                 }
5642         }
5643         return 0;
5644
5645 }
5646
5647 uint32_t
5648 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5649 {
5650         uint32_t new_val = orig_val;
5651
5652         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5653                 new_val |= IXGBE_VMOLR_AUPE;
5654         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5655                 new_val |= IXGBE_VMOLR_ROMPE;
5656         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5657                 new_val |= IXGBE_VMOLR_ROPE;
5658         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5659                 new_val |= IXGBE_VMOLR_BAM;
5660         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5661                 new_val |= IXGBE_VMOLR_MPE;
5662
5663         return new_val;
5664 }
5665
5666 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5667 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5668 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5669 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5670 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5671         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5672         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5673
5674 static int
5675 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5676                       struct rte_eth_mirror_conf *mirror_conf,
5677                       uint8_t rule_id, uint8_t on)
5678 {
5679         uint32_t mr_ctl, vlvf;
5680         uint32_t mp_lsb = 0;
5681         uint32_t mv_msb = 0;
5682         uint32_t mv_lsb = 0;
5683         uint32_t mp_msb = 0;
5684         uint8_t i = 0;
5685         int reg_index = 0;
5686         uint64_t vlan_mask = 0;
5687
5688         const uint8_t pool_mask_offset = 32;
5689         const uint8_t vlan_mask_offset = 32;
5690         const uint8_t dst_pool_offset = 8;
5691         const uint8_t rule_mr_offset  = 4;
5692         const uint8_t mirror_rule_mask = 0x0F;
5693
5694         struct ixgbe_mirror_info *mr_info =
5695                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5696         struct ixgbe_hw *hw =
5697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5698         uint8_t mirror_type = 0;
5699
5700         if (ixgbe_vt_check(hw) < 0)
5701                 return -ENOTSUP;
5702
5703         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5704                 return -EINVAL;
5705
5706         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5707                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5708                             mirror_conf->rule_type);
5709                 return -EINVAL;
5710         }
5711
5712         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5713                 mirror_type |= IXGBE_MRCTL_VLME;
5714                 /* Check if vlan id is valid and find conresponding VLAN ID
5715                  * index in VLVF
5716                  */
5717                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5718                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5719                                 /* search vlan id related pool vlan filter
5720                                  * index
5721                                  */
5722                                 reg_index = ixgbe_find_vlvf_slot(
5723                                                 hw,
5724                                                 mirror_conf->vlan.vlan_id[i],
5725                                                 false);
5726                                 if (reg_index < 0)
5727                                         return -EINVAL;
5728                                 vlvf = IXGBE_READ_REG(hw,
5729                                                       IXGBE_VLVF(reg_index));
5730                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5731                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5732                                       mirror_conf->vlan.vlan_id[i]))
5733                                         vlan_mask |= (1ULL << reg_index);
5734                                 else
5735                                         return -EINVAL;
5736                         }
5737                 }
5738
5739                 if (on) {
5740                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5741                         mv_msb = vlan_mask >> vlan_mask_offset;
5742
5743                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5744                                                 mirror_conf->vlan.vlan_mask;
5745                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5746                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5747                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5748                                                 mirror_conf->vlan.vlan_id[i];
5749                         }
5750                 } else {
5751                         mv_lsb = 0;
5752                         mv_msb = 0;
5753                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5754                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5755                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5756                 }
5757         }
5758
5759         /**
5760          * if enable pool mirror, write related pool mask register,if disable
5761          * pool mirror, clear PFMRVM register
5762          */
5763         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5764                 mirror_type |= IXGBE_MRCTL_VPME;
5765                 if (on) {
5766                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5767                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5768                         mr_info->mr_conf[rule_id].pool_mask =
5769                                         mirror_conf->pool_mask;
5770
5771                 } else {
5772                         mp_lsb = 0;
5773                         mp_msb = 0;
5774                         mr_info->mr_conf[rule_id].pool_mask = 0;
5775                 }
5776         }
5777         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5778                 mirror_type |= IXGBE_MRCTL_UPME;
5779         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5780                 mirror_type |= IXGBE_MRCTL_DPME;
5781
5782         /* read  mirror control register and recalculate it */
5783         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5784
5785         if (on) {
5786                 mr_ctl |= mirror_type;
5787                 mr_ctl &= mirror_rule_mask;
5788                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5789         } else {
5790                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5791         }
5792
5793         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5794         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5795
5796         /* write mirrror control  register */
5797         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5798
5799         /* write pool mirrror control  register */
5800         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5801                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5802                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5803                                 mp_msb);
5804         }
5805         /* write VLAN mirrror control  register */
5806         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5807                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5808                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5809                                 mv_msb);
5810         }
5811
5812         return 0;
5813 }
5814
5815 static int
5816 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5817 {
5818         int mr_ctl = 0;
5819         uint32_t lsb_val = 0;
5820         uint32_t msb_val = 0;
5821         const uint8_t rule_mr_offset = 4;
5822
5823         struct ixgbe_hw *hw =
5824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5825         struct ixgbe_mirror_info *mr_info =
5826                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5827
5828         if (ixgbe_vt_check(hw) < 0)
5829                 return -ENOTSUP;
5830
5831         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5832                 return -EINVAL;
5833
5834         memset(&mr_info->mr_conf[rule_id], 0,
5835                sizeof(struct rte_eth_mirror_conf));
5836
5837         /* clear PFVMCTL register */
5838         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5839
5840         /* clear pool mask register */
5841         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5842         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5843
5844         /* clear vlan mask register */
5845         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5846         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5847
5848         return 0;
5849 }
5850
5851 static int
5852 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5853 {
5854         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5855         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5856         struct ixgbe_interrupt *intr =
5857                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5858         struct ixgbe_hw *hw =
5859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5860         uint32_t vec = IXGBE_MISC_VEC_ID;
5861
5862         if (rte_intr_allow_others(intr_handle))
5863                 vec = IXGBE_RX_VEC_START;
5864         intr->mask |= (1 << vec);
5865         RTE_SET_USED(queue_id);
5866         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5867
5868         rte_intr_ack(intr_handle);
5869
5870         return 0;
5871 }
5872
5873 static int
5874 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5875 {
5876         struct ixgbe_interrupt *intr =
5877                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5878         struct ixgbe_hw *hw =
5879                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5880         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5881         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5882         uint32_t vec = IXGBE_MISC_VEC_ID;
5883
5884         if (rte_intr_allow_others(intr_handle))
5885                 vec = IXGBE_RX_VEC_START;
5886         intr->mask &= ~(1 << vec);
5887         RTE_SET_USED(queue_id);
5888         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5889
5890         return 0;
5891 }
5892
5893 static int
5894 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5895 {
5896         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5897         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5898         uint32_t mask;
5899         struct ixgbe_hw *hw =
5900                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5901         struct ixgbe_interrupt *intr =
5902                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5903
5904         if (queue_id < 16) {
5905                 ixgbe_disable_intr(hw);
5906                 intr->mask |= (1 << queue_id);
5907                 ixgbe_enable_intr(dev);
5908         } else if (queue_id < 32) {
5909                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5910                 mask &= (1 << queue_id);
5911                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5912         } else if (queue_id < 64) {
5913                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5914                 mask &= (1 << (queue_id - 32));
5915                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5916         }
5917         rte_intr_ack(intr_handle);
5918
5919         return 0;
5920 }
5921
5922 static int
5923 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5924 {
5925         uint32_t mask;
5926         struct ixgbe_hw *hw =
5927                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5928         struct ixgbe_interrupt *intr =
5929                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5930
5931         if (queue_id < 16) {
5932                 ixgbe_disable_intr(hw);
5933                 intr->mask &= ~(1 << queue_id);
5934                 ixgbe_enable_intr(dev);
5935         } else if (queue_id < 32) {
5936                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5937                 mask &= ~(1 << queue_id);
5938                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5939         } else if (queue_id < 64) {
5940                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5941                 mask &= ~(1 << (queue_id - 32));
5942                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5943         }
5944
5945         return 0;
5946 }
5947
5948 static void
5949 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5950                      uint8_t queue, uint8_t msix_vector)
5951 {
5952         uint32_t tmp, idx;
5953
5954         if (direction == -1) {
5955                 /* other causes */
5956                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5957                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5958                 tmp &= ~0xFF;
5959                 tmp |= msix_vector;
5960                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5961         } else {
5962                 /* rx or tx cause */
5963                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5964                 idx = ((16 * (queue & 1)) + (8 * direction));
5965                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5966                 tmp &= ~(0xFF << idx);
5967                 tmp |= (msix_vector << idx);
5968                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5969         }
5970 }
5971
5972 /**
5973  * set the IVAR registers, mapping interrupt causes to vectors
5974  * @param hw
5975  *  pointer to ixgbe_hw struct
5976  * @direction
5977  *  0 for Rx, 1 for Tx, -1 for other causes
5978  * @queue
5979  *  queue to map the corresponding interrupt to
5980  * @msix_vector
5981  *  the vector to map to the corresponding queue
5982  */
5983 static void
5984 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5985                    uint8_t queue, uint8_t msix_vector)
5986 {
5987         uint32_t tmp, idx;
5988
5989         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5990         if (hw->mac.type == ixgbe_mac_82598EB) {
5991                 if (direction == -1)
5992                         direction = 0;
5993                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5994                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5995                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5996                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5997                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5998         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5999                         (hw->mac.type == ixgbe_mac_X540) ||
6000                         (hw->mac.type == ixgbe_mac_X550) ||
6001                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6002                 if (direction == -1) {
6003                         /* other causes */
6004                         idx = ((queue & 1) * 8);
6005                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6006                         tmp &= ~(0xFF << idx);
6007                         tmp |= (msix_vector << idx);
6008                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6009                 } else {
6010                         /* rx or tx causes */
6011                         idx = ((16 * (queue & 1)) + (8 * direction));
6012                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6013                         tmp &= ~(0xFF << idx);
6014                         tmp |= (msix_vector << idx);
6015                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6016                 }
6017         }
6018 }
6019
6020 static void
6021 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6022 {
6023         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6024         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6025         struct ixgbe_hw *hw =
6026                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6027         uint32_t q_idx;
6028         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6029         uint32_t base = IXGBE_MISC_VEC_ID;
6030
6031         /* Configure VF other cause ivar */
6032         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6033
6034         /* won't configure msix register if no mapping is done
6035          * between intr vector and event fd.
6036          */
6037         if (!rte_intr_dp_is_en(intr_handle))
6038                 return;
6039
6040         if (rte_intr_allow_others(intr_handle)) {
6041                 base = IXGBE_RX_VEC_START;
6042                 vector_idx = IXGBE_RX_VEC_START;
6043         }
6044
6045         /* Configure all RX queues of VF */
6046         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6047                 /* Force all queue use vector 0,
6048                  * as IXGBE_VF_MAXMSIVECOTR = 1
6049                  */
6050                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6051                 intr_handle->intr_vec[q_idx] = vector_idx;
6052                 if (vector_idx < base + intr_handle->nb_efd - 1)
6053                         vector_idx++;
6054         }
6055
6056         /* As RX queue setting above show, all queues use the vector 0.
6057          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6058          */
6059         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6060                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6061                         | IXGBE_EITR_CNT_WDIS);
6062 }
6063
6064 /**
6065  * Sets up the hardware to properly generate MSI-X interrupts
6066  * @hw
6067  *  board private structure
6068  */
6069 static void
6070 ixgbe_configure_msix(struct rte_eth_dev *dev)
6071 {
6072         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6073         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6074         struct ixgbe_hw *hw =
6075                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6076         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6077         uint32_t vec = IXGBE_MISC_VEC_ID;
6078         uint32_t mask;
6079         uint32_t gpie;
6080
6081         /* won't configure msix register if no mapping is done
6082          * between intr vector and event fd
6083          * but if misx has been enabled already, need to configure
6084          * auto clean, auto mask and throttling.
6085          */
6086         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6087         if (!rte_intr_dp_is_en(intr_handle) &&
6088             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6089                 return;
6090
6091         if (rte_intr_allow_others(intr_handle))
6092                 vec = base = IXGBE_RX_VEC_START;
6093
6094         /* setup GPIE for MSI-x mode */
6095         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6096         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6097                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6098         /* auto clearing and auto setting corresponding bits in EIMS
6099          * when MSI-X interrupt is triggered
6100          */
6101         if (hw->mac.type == ixgbe_mac_82598EB) {
6102                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6103         } else {
6104                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6105                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6106         }
6107         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6108
6109         /* Populate the IVAR table and set the ITR values to the
6110          * corresponding register.
6111          */
6112         if (rte_intr_dp_is_en(intr_handle)) {
6113                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6114                         queue_id++) {
6115                         /* by default, 1:1 mapping */
6116                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6117                         intr_handle->intr_vec[queue_id] = vec;
6118                         if (vec < base + intr_handle->nb_efd - 1)
6119                                 vec++;
6120                 }
6121
6122                 switch (hw->mac.type) {
6123                 case ixgbe_mac_82598EB:
6124                         ixgbe_set_ivar_map(hw, -1,
6125                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6126                                            IXGBE_MISC_VEC_ID);
6127                         break;
6128                 case ixgbe_mac_82599EB:
6129                 case ixgbe_mac_X540:
6130                 case ixgbe_mac_X550:
6131                 case ixgbe_mac_X550EM_x:
6132                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6133                         break;
6134                 default:
6135                         break;
6136                 }
6137         }
6138         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6139                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6140                         | IXGBE_EITR_CNT_WDIS);
6141
6142         /* set up to autoclear timer, and the vectors */
6143         mask = IXGBE_EIMS_ENABLE_MASK;
6144         mask &= ~(IXGBE_EIMS_OTHER |
6145                   IXGBE_EIMS_MAILBOX |
6146                   IXGBE_EIMS_LSC);
6147
6148         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6149 }
6150
6151 int
6152 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6153                            uint16_t queue_idx, uint16_t tx_rate)
6154 {
6155         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6156         struct rte_eth_rxmode *rxmode;
6157         uint32_t rf_dec, rf_int;
6158         uint32_t bcnrc_val;
6159         uint16_t link_speed = dev->data->dev_link.link_speed;
6160
6161         if (queue_idx >= hw->mac.max_tx_queues)
6162                 return -EINVAL;
6163
6164         if (tx_rate != 0) {
6165                 /* Calculate the rate factor values to set */
6166                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6167                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6168                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6169
6170                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6171                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6172                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6173                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6174         } else {
6175                 bcnrc_val = 0;
6176         }
6177
6178         rxmode = &dev->data->dev_conf.rxmode;
6179         /*
6180          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6181          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6182          * set as 0x4.
6183          */
6184         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6185             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6186                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6187                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6188         else
6189                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6190                         IXGBE_MMW_SIZE_DEFAULT);
6191
6192         /* Set RTTBCNRC of queue X */
6193         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6194         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6195         IXGBE_WRITE_FLUSH(hw);
6196
6197         return 0;
6198 }
6199
6200 static int
6201 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6202                      __attribute__((unused)) uint32_t index,
6203                      __attribute__((unused)) uint32_t pool)
6204 {
6205         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6206         int diag;
6207
6208         /*
6209          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6210          * operation. Trap this case to avoid exhausting the [very limited]
6211          * set of PF resources used to store VF MAC addresses.
6212          */
6213         if (memcmp(hw->mac.perm_addr, mac_addr,
6214                         sizeof(struct rte_ether_addr)) == 0)
6215                 return -1;
6216         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6217         if (diag != 0)
6218                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6219                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6220                             mac_addr->addr_bytes[0],
6221                             mac_addr->addr_bytes[1],
6222                             mac_addr->addr_bytes[2],
6223                             mac_addr->addr_bytes[3],
6224                             mac_addr->addr_bytes[4],
6225                             mac_addr->addr_bytes[5],
6226                             diag);
6227         return diag;
6228 }
6229
6230 static void
6231 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6232 {
6233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6234         struct rte_ether_addr *perm_addr =
6235                 (struct rte_ether_addr *)hw->mac.perm_addr;
6236         struct rte_ether_addr *mac_addr;
6237         uint32_t i;
6238         int diag;
6239
6240         /*
6241          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6242          * not support the deletion of a given MAC address.
6243          * Instead, it imposes to delete all MAC addresses, then to add again
6244          * all MAC addresses with the exception of the one to be deleted.
6245          */
6246         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6247
6248         /*
6249          * Add again all MAC addresses, with the exception of the deleted one
6250          * and of the permanent MAC address.
6251          */
6252         for (i = 0, mac_addr = dev->data->mac_addrs;
6253              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6254                 /* Skip the deleted MAC address */
6255                 if (i == index)
6256                         continue;
6257                 /* Skip NULL MAC addresses */
6258                 if (rte_is_zero_ether_addr(mac_addr))
6259                         continue;
6260                 /* Skip the permanent MAC address */
6261                 if (memcmp(perm_addr, mac_addr,
6262                                 sizeof(struct rte_ether_addr)) == 0)
6263                         continue;
6264                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6265                 if (diag != 0)
6266                         PMD_DRV_LOG(ERR,
6267                                     "Adding again MAC address "
6268                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6269                                     "diag=%d",
6270                                     mac_addr->addr_bytes[0],
6271                                     mac_addr->addr_bytes[1],
6272                                     mac_addr->addr_bytes[2],
6273                                     mac_addr->addr_bytes[3],
6274                                     mac_addr->addr_bytes[4],
6275                                     mac_addr->addr_bytes[5],
6276                                     diag);
6277         }
6278 }
6279
6280 static int
6281 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6282                         struct rte_ether_addr *addr)
6283 {
6284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6285
6286         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6287
6288         return 0;
6289 }
6290
6291 int
6292 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6293                         struct rte_eth_syn_filter *filter,
6294                         bool add)
6295 {
6296         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6297         struct ixgbe_filter_info *filter_info =
6298                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6299         uint32_t syn_info;
6300         uint32_t synqf;
6301
6302         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6303                 return -EINVAL;
6304
6305         syn_info = filter_info->syn_info;
6306
6307         if (add) {
6308                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6309                         return -EINVAL;
6310                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6311                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6312
6313                 if (filter->hig_pri)
6314                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6315                 else
6316                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6317         } else {
6318                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6319                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6320                         return -ENOENT;
6321                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6322         }
6323
6324         filter_info->syn_info = synqf;
6325         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6326         IXGBE_WRITE_FLUSH(hw);
6327         return 0;
6328 }
6329
6330 static int
6331 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6332                         struct rte_eth_syn_filter *filter)
6333 {
6334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6335         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6336
6337         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6338                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6339                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6340                 return 0;
6341         }
6342         return -ENOENT;
6343 }
6344
6345 static int
6346 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6347                         enum rte_filter_op filter_op,
6348                         void *arg)
6349 {
6350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6351         int ret;
6352
6353         MAC_TYPE_FILTER_SUP(hw->mac.type);
6354
6355         if (filter_op == RTE_ETH_FILTER_NOP)
6356                 return 0;
6357
6358         if (arg == NULL) {
6359                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6360                             filter_op);
6361                 return -EINVAL;
6362         }
6363
6364         switch (filter_op) {
6365         case RTE_ETH_FILTER_ADD:
6366                 ret = ixgbe_syn_filter_set(dev,
6367                                 (struct rte_eth_syn_filter *)arg,
6368                                 TRUE);
6369                 break;
6370         case RTE_ETH_FILTER_DELETE:
6371                 ret = ixgbe_syn_filter_set(dev,
6372                                 (struct rte_eth_syn_filter *)arg,
6373                                 FALSE);
6374                 break;
6375         case RTE_ETH_FILTER_GET:
6376                 ret = ixgbe_syn_filter_get(dev,
6377                                 (struct rte_eth_syn_filter *)arg);
6378                 break;
6379         default:
6380                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6381                 ret = -EINVAL;
6382                 break;
6383         }
6384
6385         return ret;
6386 }
6387
6388
6389 static inline enum ixgbe_5tuple_protocol
6390 convert_protocol_type(uint8_t protocol_value)
6391 {
6392         if (protocol_value == IPPROTO_TCP)
6393                 return IXGBE_FILTER_PROTOCOL_TCP;
6394         else if (protocol_value == IPPROTO_UDP)
6395                 return IXGBE_FILTER_PROTOCOL_UDP;
6396         else if (protocol_value == IPPROTO_SCTP)
6397                 return IXGBE_FILTER_PROTOCOL_SCTP;
6398         else
6399                 return IXGBE_FILTER_PROTOCOL_NONE;
6400 }
6401
6402 /* inject a 5-tuple filter to HW */
6403 static inline void
6404 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6405                            struct ixgbe_5tuple_filter *filter)
6406 {
6407         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6408         int i;
6409         uint32_t ftqf, sdpqf;
6410         uint32_t l34timir = 0;
6411         uint8_t mask = 0xff;
6412
6413         i = filter->index;
6414
6415         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6416                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6417         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6418
6419         ftqf = (uint32_t)(filter->filter_info.proto &
6420                 IXGBE_FTQF_PROTOCOL_MASK);
6421         ftqf |= (uint32_t)((filter->filter_info.priority &
6422                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6423         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6424                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6425         if (filter->filter_info.dst_ip_mask == 0)
6426                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6427         if (filter->filter_info.src_port_mask == 0)
6428                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6429         if (filter->filter_info.dst_port_mask == 0)
6430                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6431         if (filter->filter_info.proto_mask == 0)
6432                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6433         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6434         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6435         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6436
6437         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6438         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6439         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6440         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6441
6442         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6443         l34timir |= (uint32_t)(filter->queue <<
6444                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6445         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6446 }
6447
6448 /*
6449  * add a 5tuple filter
6450  *
6451  * @param
6452  * dev: Pointer to struct rte_eth_dev.
6453  * index: the index the filter allocates.
6454  * filter: ponter to the filter that will be added.
6455  * rx_queue: the queue id the filter assigned to.
6456  *
6457  * @return
6458  *    - On success, zero.
6459  *    - On failure, a negative value.
6460  */
6461 static int
6462 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6463                         struct ixgbe_5tuple_filter *filter)
6464 {
6465         struct ixgbe_filter_info *filter_info =
6466                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6467         int i, idx, shift;
6468
6469         /*
6470          * look for an unused 5tuple filter index,
6471          * and insert the filter to list.
6472          */
6473         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6474                 idx = i / (sizeof(uint32_t) * NBBY);
6475                 shift = i % (sizeof(uint32_t) * NBBY);
6476                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6477                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6478                         filter->index = i;
6479                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6480                                           filter,
6481                                           entries);
6482                         break;
6483                 }
6484         }
6485         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6486                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6487                 return -ENOSYS;
6488         }
6489
6490         ixgbe_inject_5tuple_filter(dev, filter);
6491
6492         return 0;
6493 }
6494
6495 /*
6496  * remove a 5tuple filter
6497  *
6498  * @param
6499  * dev: Pointer to struct rte_eth_dev.
6500  * filter: the pointer of the filter will be removed.
6501  */
6502 static void
6503 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6504                         struct ixgbe_5tuple_filter *filter)
6505 {
6506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6507         struct ixgbe_filter_info *filter_info =
6508                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6509         uint16_t index = filter->index;
6510
6511         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6512                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6513         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6514         rte_free(filter);
6515
6516         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6517         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6518         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6519         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6520         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6521 }
6522
6523 static int
6524 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6525 {
6526         struct ixgbe_hw *hw;
6527         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6528         struct rte_eth_dev_data *dev_data = dev->data;
6529
6530         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6531
6532         if (mtu < RTE_ETHER_MIN_MTU ||
6533                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6534                 return -EINVAL;
6535
6536         /* If device is started, refuse mtu that requires the support of
6537          * scattered packets when this feature has not been enabled before.
6538          */
6539         if (dev_data->dev_started && !dev_data->scattered_rx &&
6540             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6541              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6542                 PMD_INIT_LOG(ERR, "Stop port first.");
6543                 return -EINVAL;
6544         }
6545
6546         /*
6547          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6548          * request of the version 2.0 of the mailbox API.
6549          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6550          * of the mailbox API.
6551          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6552          * prior to 3.11.33 which contains the following change:
6553          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6554          */
6555         ixgbevf_rlpml_set_vf(hw, max_frame);
6556
6557         /* update max frame size */
6558         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6559         return 0;
6560 }
6561
6562 static inline struct ixgbe_5tuple_filter *
6563 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6564                         struct ixgbe_5tuple_filter_info *key)
6565 {
6566         struct ixgbe_5tuple_filter *it;
6567
6568         TAILQ_FOREACH(it, filter_list, entries) {
6569                 if (memcmp(key, &it->filter_info,
6570                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6571                         return it;
6572                 }
6573         }
6574         return NULL;
6575 }
6576
6577 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6578 static inline int
6579 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6580                         struct ixgbe_5tuple_filter_info *filter_info)
6581 {
6582         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6583                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6584                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6585                 return -EINVAL;
6586
6587         switch (filter->dst_ip_mask) {
6588         case UINT32_MAX:
6589                 filter_info->dst_ip_mask = 0;
6590                 filter_info->dst_ip = filter->dst_ip;
6591                 break;
6592         case 0:
6593                 filter_info->dst_ip_mask = 1;
6594                 break;
6595         default:
6596                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6597                 return -EINVAL;
6598         }
6599
6600         switch (filter->src_ip_mask) {
6601         case UINT32_MAX:
6602                 filter_info->src_ip_mask = 0;
6603                 filter_info->src_ip = filter->src_ip;
6604                 break;
6605         case 0:
6606                 filter_info->src_ip_mask = 1;
6607                 break;
6608         default:
6609                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6610                 return -EINVAL;
6611         }
6612
6613         switch (filter->dst_port_mask) {
6614         case UINT16_MAX:
6615                 filter_info->dst_port_mask = 0;
6616                 filter_info->dst_port = filter->dst_port;
6617                 break;
6618         case 0:
6619                 filter_info->dst_port_mask = 1;
6620                 break;
6621         default:
6622                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6623                 return -EINVAL;
6624         }
6625
6626         switch (filter->src_port_mask) {
6627         case UINT16_MAX:
6628                 filter_info->src_port_mask = 0;
6629                 filter_info->src_port = filter->src_port;
6630                 break;
6631         case 0:
6632                 filter_info->src_port_mask = 1;
6633                 break;
6634         default:
6635                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6636                 return -EINVAL;
6637         }
6638
6639         switch (filter->proto_mask) {
6640         case UINT8_MAX:
6641                 filter_info->proto_mask = 0;
6642                 filter_info->proto =
6643                         convert_protocol_type(filter->proto);
6644                 break;
6645         case 0:
6646                 filter_info->proto_mask = 1;
6647                 break;
6648         default:
6649                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6650                 return -EINVAL;
6651         }
6652
6653         filter_info->priority = (uint8_t)filter->priority;
6654         return 0;
6655 }
6656
6657 /*
6658  * add or delete a ntuple filter
6659  *
6660  * @param
6661  * dev: Pointer to struct rte_eth_dev.
6662  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6663  * add: if true, add filter, if false, remove filter
6664  *
6665  * @return
6666  *    - On success, zero.
6667  *    - On failure, a negative value.
6668  */
6669 int
6670 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6671                         struct rte_eth_ntuple_filter *ntuple_filter,
6672                         bool add)
6673 {
6674         struct ixgbe_filter_info *filter_info =
6675                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6676         struct ixgbe_5tuple_filter_info filter_5tuple;
6677         struct ixgbe_5tuple_filter *filter;
6678         int ret;
6679
6680         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6681                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6682                 return -EINVAL;
6683         }
6684
6685         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6686         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6687         if (ret < 0)
6688                 return ret;
6689
6690         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6691                                          &filter_5tuple);
6692         if (filter != NULL && add) {
6693                 PMD_DRV_LOG(ERR, "filter exists.");
6694                 return -EEXIST;
6695         }
6696         if (filter == NULL && !add) {
6697                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6698                 return -ENOENT;
6699         }
6700
6701         if (add) {
6702                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6703                                 sizeof(struct ixgbe_5tuple_filter), 0);
6704                 if (filter == NULL)
6705                         return -ENOMEM;
6706                 rte_memcpy(&filter->filter_info,
6707                                  &filter_5tuple,
6708                                  sizeof(struct ixgbe_5tuple_filter_info));
6709                 filter->queue = ntuple_filter->queue;
6710                 ret = ixgbe_add_5tuple_filter(dev, filter);
6711                 if (ret < 0) {
6712                         rte_free(filter);
6713                         return ret;
6714                 }
6715         } else
6716                 ixgbe_remove_5tuple_filter(dev, filter);
6717
6718         return 0;
6719 }
6720
6721 /*
6722  * get a ntuple filter
6723  *
6724  * @param
6725  * dev: Pointer to struct rte_eth_dev.
6726  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6727  *
6728  * @return
6729  *    - On success, zero.
6730  *    - On failure, a negative value.
6731  */
6732 static int
6733 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6734                         struct rte_eth_ntuple_filter *ntuple_filter)
6735 {
6736         struct ixgbe_filter_info *filter_info =
6737                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6738         struct ixgbe_5tuple_filter_info filter_5tuple;
6739         struct ixgbe_5tuple_filter *filter;
6740         int ret;
6741
6742         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6743                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6744                 return -EINVAL;
6745         }
6746
6747         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6748         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6749         if (ret < 0)
6750                 return ret;
6751
6752         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6753                                          &filter_5tuple);
6754         if (filter == NULL) {
6755                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6756                 return -ENOENT;
6757         }
6758         ntuple_filter->queue = filter->queue;
6759         return 0;
6760 }
6761
6762 /*
6763  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6764  * @dev: pointer to rte_eth_dev structure
6765  * @filter_op:operation will be taken.
6766  * @arg: a pointer to specific structure corresponding to the filter_op
6767  *
6768  * @return
6769  *    - On success, zero.
6770  *    - On failure, a negative value.
6771  */
6772 static int
6773 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6774                                 enum rte_filter_op filter_op,
6775                                 void *arg)
6776 {
6777         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6778         int ret;
6779
6780         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6781
6782         if (filter_op == RTE_ETH_FILTER_NOP)
6783                 return 0;
6784
6785         if (arg == NULL) {
6786                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6787                             filter_op);
6788                 return -EINVAL;
6789         }
6790
6791         switch (filter_op) {
6792         case RTE_ETH_FILTER_ADD:
6793                 ret = ixgbe_add_del_ntuple_filter(dev,
6794                         (struct rte_eth_ntuple_filter *)arg,
6795                         TRUE);
6796                 break;
6797         case RTE_ETH_FILTER_DELETE:
6798                 ret = ixgbe_add_del_ntuple_filter(dev,
6799                         (struct rte_eth_ntuple_filter *)arg,
6800                         FALSE);
6801                 break;
6802         case RTE_ETH_FILTER_GET:
6803                 ret = ixgbe_get_ntuple_filter(dev,
6804                         (struct rte_eth_ntuple_filter *)arg);
6805                 break;
6806         default:
6807                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6808                 ret = -EINVAL;
6809                 break;
6810         }
6811         return ret;
6812 }
6813
6814 int
6815 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6816                         struct rte_eth_ethertype_filter *filter,
6817                         bool add)
6818 {
6819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6820         struct ixgbe_filter_info *filter_info =
6821                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6822         uint32_t etqf = 0;
6823         uint32_t etqs = 0;
6824         int ret;
6825         struct ixgbe_ethertype_filter ethertype_filter;
6826
6827         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6828                 return -EINVAL;
6829
6830         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6831                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6832                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6833                         " ethertype filter.", filter->ether_type);
6834                 return -EINVAL;
6835         }
6836
6837         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6838                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6839                 return -EINVAL;
6840         }
6841         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6842                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6843                 return -EINVAL;
6844         }
6845
6846         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6847         if (ret >= 0 && add) {
6848                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6849                             filter->ether_type);
6850                 return -EEXIST;
6851         }
6852         if (ret < 0 && !add) {
6853                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6854                             filter->ether_type);
6855                 return -ENOENT;
6856         }
6857
6858         if (add) {
6859                 etqf = IXGBE_ETQF_FILTER_EN;
6860                 etqf |= (uint32_t)filter->ether_type;
6861                 etqs |= (uint32_t)((filter->queue <<
6862                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6863                                     IXGBE_ETQS_RX_QUEUE);
6864                 etqs |= IXGBE_ETQS_QUEUE_EN;
6865
6866                 ethertype_filter.ethertype = filter->ether_type;
6867                 ethertype_filter.etqf = etqf;
6868                 ethertype_filter.etqs = etqs;
6869                 ethertype_filter.conf = FALSE;
6870                 ret = ixgbe_ethertype_filter_insert(filter_info,
6871                                                     &ethertype_filter);
6872                 if (ret < 0) {
6873                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6874                         return -ENOSPC;
6875                 }
6876         } else {
6877                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6878                 if (ret < 0)
6879                         return -ENOSYS;
6880         }
6881         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6882         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6883         IXGBE_WRITE_FLUSH(hw);
6884
6885         return 0;
6886 }
6887
6888 static int
6889 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6890                         struct rte_eth_ethertype_filter *filter)
6891 {
6892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893         struct ixgbe_filter_info *filter_info =
6894                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6895         uint32_t etqf, etqs;
6896         int ret;
6897
6898         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6899         if (ret < 0) {
6900                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6901                             filter->ether_type);
6902                 return -ENOENT;
6903         }
6904
6905         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6906         if (etqf & IXGBE_ETQF_FILTER_EN) {
6907                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6908                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6909                 filter->flags = 0;
6910                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6911                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6912                 return 0;
6913         }
6914         return -ENOENT;
6915 }
6916
6917 /*
6918  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6919  * @dev: pointer to rte_eth_dev structure
6920  * @filter_op:operation will be taken.
6921  * @arg: a pointer to specific structure corresponding to the filter_op
6922  */
6923 static int
6924 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6925                                 enum rte_filter_op filter_op,
6926                                 void *arg)
6927 {
6928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6929         int ret;
6930
6931         MAC_TYPE_FILTER_SUP(hw->mac.type);
6932
6933         if (filter_op == RTE_ETH_FILTER_NOP)
6934                 return 0;
6935
6936         if (arg == NULL) {
6937                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6938                             filter_op);
6939                 return -EINVAL;
6940         }
6941
6942         switch (filter_op) {
6943         case RTE_ETH_FILTER_ADD:
6944                 ret = ixgbe_add_del_ethertype_filter(dev,
6945                         (struct rte_eth_ethertype_filter *)arg,
6946                         TRUE);
6947                 break;
6948         case RTE_ETH_FILTER_DELETE:
6949                 ret = ixgbe_add_del_ethertype_filter(dev,
6950                         (struct rte_eth_ethertype_filter *)arg,
6951                         FALSE);
6952                 break;
6953         case RTE_ETH_FILTER_GET:
6954                 ret = ixgbe_get_ethertype_filter(dev,
6955                         (struct rte_eth_ethertype_filter *)arg);
6956                 break;
6957         default:
6958                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6959                 ret = -EINVAL;
6960                 break;
6961         }
6962         return ret;
6963 }
6964
6965 static int
6966 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6967                      enum rte_filter_type filter_type,
6968                      enum rte_filter_op filter_op,
6969                      void *arg)
6970 {
6971         int ret = 0;
6972
6973         switch (filter_type) {
6974         case RTE_ETH_FILTER_NTUPLE:
6975                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6976                 break;
6977         case RTE_ETH_FILTER_ETHERTYPE:
6978                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6979                 break;
6980         case RTE_ETH_FILTER_SYN:
6981                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6982                 break;
6983         case RTE_ETH_FILTER_FDIR:
6984                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6985                 break;
6986         case RTE_ETH_FILTER_L2_TUNNEL:
6987                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6988                 break;
6989         case RTE_ETH_FILTER_GENERIC:
6990                 if (filter_op != RTE_ETH_FILTER_GET)
6991                         return -EINVAL;
6992                 *(const void **)arg = &ixgbe_flow_ops;
6993                 break;
6994         default:
6995                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6996                                                         filter_type);
6997                 ret = -EINVAL;
6998                 break;
6999         }
7000
7001         return ret;
7002 }
7003
7004 static u8 *
7005 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
7006                         u8 **mc_addr_ptr, u32 *vmdq)
7007 {
7008         u8 *mc_addr;
7009
7010         *vmdq = 0;
7011         mc_addr = *mc_addr_ptr;
7012         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7013         return mc_addr;
7014 }
7015
7016 static int
7017 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7018                           struct rte_ether_addr *mc_addr_set,
7019                           uint32_t nb_mc_addr)
7020 {
7021         struct ixgbe_hw *hw;
7022         u8 *mc_addr_list;
7023
7024         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7025         mc_addr_list = (u8 *)mc_addr_set;
7026         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7027                                          ixgbe_dev_addr_list_itr, TRUE);
7028 }
7029
7030 static uint64_t
7031 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7032 {
7033         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7034         uint64_t systime_cycles;
7035
7036         switch (hw->mac.type) {
7037         case ixgbe_mac_X550:
7038         case ixgbe_mac_X550EM_x:
7039         case ixgbe_mac_X550EM_a:
7040                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7041                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7042                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7043                                 * NSEC_PER_SEC;
7044                 break;
7045         default:
7046                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7047                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7048                                 << 32;
7049         }
7050
7051         return systime_cycles;
7052 }
7053
7054 static uint64_t
7055 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7056 {
7057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7058         uint64_t rx_tstamp_cycles;
7059
7060         switch (hw->mac.type) {
7061         case ixgbe_mac_X550:
7062         case ixgbe_mac_X550EM_x:
7063         case ixgbe_mac_X550EM_a:
7064                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7065                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7066                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7067                                 * NSEC_PER_SEC;
7068                 break;
7069         default:
7070                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7071                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7072                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7073                                 << 32;
7074         }
7075
7076         return rx_tstamp_cycles;
7077 }
7078
7079 static uint64_t
7080 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7081 {
7082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7083         uint64_t tx_tstamp_cycles;
7084
7085         switch (hw->mac.type) {
7086         case ixgbe_mac_X550:
7087         case ixgbe_mac_X550EM_x:
7088         case ixgbe_mac_X550EM_a:
7089                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7090                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7091                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7092                                 * NSEC_PER_SEC;
7093                 break;
7094         default:
7095                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7096                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7097                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7098                                 << 32;
7099         }
7100
7101         return tx_tstamp_cycles;
7102 }
7103
7104 static void
7105 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7106 {
7107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7108         struct ixgbe_adapter *adapter = dev->data->dev_private;
7109         struct rte_eth_link link;
7110         uint32_t incval = 0;
7111         uint32_t shift = 0;
7112
7113         /* Get current link speed. */
7114         ixgbe_dev_link_update(dev, 1);
7115         rte_eth_linkstatus_get(dev, &link);
7116
7117         switch (link.link_speed) {
7118         case ETH_SPEED_NUM_100M:
7119                 incval = IXGBE_INCVAL_100;
7120                 shift = IXGBE_INCVAL_SHIFT_100;
7121                 break;
7122         case ETH_SPEED_NUM_1G:
7123                 incval = IXGBE_INCVAL_1GB;
7124                 shift = IXGBE_INCVAL_SHIFT_1GB;
7125                 break;
7126         case ETH_SPEED_NUM_10G:
7127         default:
7128                 incval = IXGBE_INCVAL_10GB;
7129                 shift = IXGBE_INCVAL_SHIFT_10GB;
7130                 break;
7131         }
7132
7133         switch (hw->mac.type) {
7134         case ixgbe_mac_X550:
7135         case ixgbe_mac_X550EM_x:
7136         case ixgbe_mac_X550EM_a:
7137                 /* Independent of link speed. */
7138                 incval = 1;
7139                 /* Cycles read will be interpreted as ns. */
7140                 shift = 0;
7141                 /* Fall-through */
7142         case ixgbe_mac_X540:
7143                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7144                 break;
7145         case ixgbe_mac_82599EB:
7146                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7147                 shift -= IXGBE_INCVAL_SHIFT_82599;
7148                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7149                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7150                 break;
7151         default:
7152                 /* Not supported. */
7153                 return;
7154         }
7155
7156         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7157         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7158         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7159
7160         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7161         adapter->systime_tc.cc_shift = shift;
7162         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7163
7164         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7165         adapter->rx_tstamp_tc.cc_shift = shift;
7166         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7167
7168         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7169         adapter->tx_tstamp_tc.cc_shift = shift;
7170         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7171 }
7172
7173 static int
7174 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7175 {
7176         struct ixgbe_adapter *adapter = dev->data->dev_private;
7177
7178         adapter->systime_tc.nsec += delta;
7179         adapter->rx_tstamp_tc.nsec += delta;
7180         adapter->tx_tstamp_tc.nsec += delta;
7181
7182         return 0;
7183 }
7184
7185 static int
7186 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7187 {
7188         uint64_t ns;
7189         struct ixgbe_adapter *adapter = dev->data->dev_private;
7190
7191         ns = rte_timespec_to_ns(ts);
7192         /* Set the timecounters to a new value. */
7193         adapter->systime_tc.nsec = ns;
7194         adapter->rx_tstamp_tc.nsec = ns;
7195         adapter->tx_tstamp_tc.nsec = ns;
7196
7197         return 0;
7198 }
7199
7200 static int
7201 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7202 {
7203         uint64_t ns, systime_cycles;
7204         struct ixgbe_adapter *adapter = dev->data->dev_private;
7205
7206         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7207         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7208         *ts = rte_ns_to_timespec(ns);
7209
7210         return 0;
7211 }
7212
7213 static int
7214 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7215 {
7216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7217         uint32_t tsync_ctl;
7218         uint32_t tsauxc;
7219
7220         /* Stop the timesync system time. */
7221         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7222         /* Reset the timesync system time value. */
7223         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7224         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7225
7226         /* Enable system time for platforms where it isn't on by default. */
7227         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7228         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7229         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7230
7231         ixgbe_start_timecounters(dev);
7232
7233         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7234         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7235                         (RTE_ETHER_TYPE_1588 |
7236                          IXGBE_ETQF_FILTER_EN |
7237                          IXGBE_ETQF_1588));
7238
7239         /* Enable timestamping of received PTP packets. */
7240         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7241         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7242         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7243
7244         /* Enable timestamping of transmitted PTP packets. */
7245         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7246         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7247         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7248
7249         IXGBE_WRITE_FLUSH(hw);
7250
7251         return 0;
7252 }
7253
7254 static int
7255 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7256 {
7257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7258         uint32_t tsync_ctl;
7259
7260         /* Disable timestamping of transmitted PTP packets. */
7261         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7262         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7263         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7264
7265         /* Disable timestamping of received PTP packets. */
7266         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7267         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7268         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7269
7270         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7271         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7272
7273         /* Stop incrementating the System Time registers. */
7274         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7275
7276         return 0;
7277 }
7278
7279 static int
7280 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7281                                  struct timespec *timestamp,
7282                                  uint32_t flags __rte_unused)
7283 {
7284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7285         struct ixgbe_adapter *adapter = dev->data->dev_private;
7286         uint32_t tsync_rxctl;
7287         uint64_t rx_tstamp_cycles;
7288         uint64_t ns;
7289
7290         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7291         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7292                 return -EINVAL;
7293
7294         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7295         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7296         *timestamp = rte_ns_to_timespec(ns);
7297
7298         return  0;
7299 }
7300
7301 static int
7302 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7303                                  struct timespec *timestamp)
7304 {
7305         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7306         struct ixgbe_adapter *adapter = dev->data->dev_private;
7307         uint32_t tsync_txctl;
7308         uint64_t tx_tstamp_cycles;
7309         uint64_t ns;
7310
7311         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7312         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7313                 return -EINVAL;
7314
7315         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7316         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7317         *timestamp = rte_ns_to_timespec(ns);
7318
7319         return 0;
7320 }
7321
7322 static int
7323 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7324 {
7325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7326         int count = 0;
7327         int g_ind = 0;
7328         const struct reg_info *reg_group;
7329         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7330                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7331
7332         while ((reg_group = reg_set[g_ind++]))
7333                 count += ixgbe_regs_group_count(reg_group);
7334
7335         return count;
7336 }
7337
7338 static int
7339 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7340 {
7341         int count = 0;
7342         int g_ind = 0;
7343         const struct reg_info *reg_group;
7344
7345         while ((reg_group = ixgbevf_regs[g_ind++]))
7346                 count += ixgbe_regs_group_count(reg_group);
7347
7348         return count;
7349 }
7350
7351 static int
7352 ixgbe_get_regs(struct rte_eth_dev *dev,
7353               struct rte_dev_reg_info *regs)
7354 {
7355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7356         uint32_t *data = regs->data;
7357         int g_ind = 0;
7358         int count = 0;
7359         const struct reg_info *reg_group;
7360         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7361                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7362
7363         if (data == NULL) {
7364                 regs->length = ixgbe_get_reg_length(dev);
7365                 regs->width = sizeof(uint32_t);
7366                 return 0;
7367         }
7368
7369         /* Support only full register dump */
7370         if ((regs->length == 0) ||
7371             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7372                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7373                         hw->device_id;
7374                 while ((reg_group = reg_set[g_ind++]))
7375                         count += ixgbe_read_regs_group(dev, &data[count],
7376                                 reg_group);
7377                 return 0;
7378         }
7379
7380         return -ENOTSUP;
7381 }
7382
7383 static int
7384 ixgbevf_get_regs(struct rte_eth_dev *dev,
7385                 struct rte_dev_reg_info *regs)
7386 {
7387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7388         uint32_t *data = regs->data;
7389         int g_ind = 0;
7390         int count = 0;
7391         const struct reg_info *reg_group;
7392
7393         if (data == NULL) {
7394                 regs->length = ixgbevf_get_reg_length(dev);
7395                 regs->width = sizeof(uint32_t);
7396                 return 0;
7397         }
7398
7399         /* Support only full register dump */
7400         if ((regs->length == 0) ||
7401             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7402                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7403                         hw->device_id;
7404                 while ((reg_group = ixgbevf_regs[g_ind++]))
7405                         count += ixgbe_read_regs_group(dev, &data[count],
7406                                                       reg_group);
7407                 return 0;
7408         }
7409
7410         return -ENOTSUP;
7411 }
7412
7413 static int
7414 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7415 {
7416         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7417
7418         /* Return unit is byte count */
7419         return hw->eeprom.word_size * 2;
7420 }
7421
7422 static int
7423 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7424                 struct rte_dev_eeprom_info *in_eeprom)
7425 {
7426         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7427         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7428         uint16_t *data = in_eeprom->data;
7429         int first, length;
7430
7431         first = in_eeprom->offset >> 1;
7432         length = in_eeprom->length >> 1;
7433         if ((first > hw->eeprom.word_size) ||
7434             ((first + length) > hw->eeprom.word_size))
7435                 return -EINVAL;
7436
7437         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7438
7439         return eeprom->ops.read_buffer(hw, first, length, data);
7440 }
7441
7442 static int
7443 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7444                 struct rte_dev_eeprom_info *in_eeprom)
7445 {
7446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7447         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7448         uint16_t *data = in_eeprom->data;
7449         int first, length;
7450
7451         first = in_eeprom->offset >> 1;
7452         length = in_eeprom->length >> 1;
7453         if ((first > hw->eeprom.word_size) ||
7454             ((first + length) > hw->eeprom.word_size))
7455                 return -EINVAL;
7456
7457         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7458
7459         return eeprom->ops.write_buffer(hw,  first, length, data);
7460 }
7461
7462 static int
7463 ixgbe_get_module_info(struct rte_eth_dev *dev,
7464                       struct rte_eth_dev_module_info *modinfo)
7465 {
7466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7467         uint32_t status;
7468         uint8_t sff8472_rev, addr_mode;
7469         bool page_swap = false;
7470
7471         /* Check whether we support SFF-8472 or not */
7472         status = hw->phy.ops.read_i2c_eeprom(hw,
7473                                              IXGBE_SFF_SFF_8472_COMP,
7474                                              &sff8472_rev);
7475         if (status != 0)
7476                 return -EIO;
7477
7478         /* addressing mode is not supported */
7479         status = hw->phy.ops.read_i2c_eeprom(hw,
7480                                              IXGBE_SFF_SFF_8472_SWAP,
7481                                              &addr_mode);
7482         if (status != 0)
7483                 return -EIO;
7484
7485         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7486                 PMD_DRV_LOG(ERR,
7487                             "Address change required to access page 0xA2, "
7488                             "but not supported. Please report the module "
7489                             "type to the driver maintainers.");
7490                 page_swap = true;
7491         }
7492
7493         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7494                 /* We have a SFP, but it does not support SFF-8472 */
7495                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7496                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7497         } else {
7498                 /* We have a SFP which supports a revision of SFF-8472. */
7499                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7500                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7501         }
7502
7503         return 0;
7504 }
7505
7506 static int
7507 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7508                         struct rte_dev_eeprom_info *info)
7509 {
7510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7511         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7512         uint8_t databyte = 0xFF;
7513         uint8_t *data = info->data;
7514         uint32_t i = 0;
7515
7516         if (info->length == 0)
7517                 return -EINVAL;
7518
7519         for (i = info->offset; i < info->offset + info->length; i++) {
7520                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7521                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7522                 else
7523                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7524
7525                 if (status != 0)
7526                         return -EIO;
7527
7528                 data[i - info->offset] = databyte;
7529         }
7530
7531         return 0;
7532 }
7533
7534 uint16_t
7535 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7536         switch (mac_type) {
7537         case ixgbe_mac_X550:
7538         case ixgbe_mac_X550EM_x:
7539         case ixgbe_mac_X550EM_a:
7540                 return ETH_RSS_RETA_SIZE_512;
7541         case ixgbe_mac_X550_vf:
7542         case ixgbe_mac_X550EM_x_vf:
7543         case ixgbe_mac_X550EM_a_vf:
7544                 return ETH_RSS_RETA_SIZE_64;
7545         case ixgbe_mac_X540_vf:
7546         case ixgbe_mac_82599_vf:
7547                 return 0;
7548         default:
7549                 return ETH_RSS_RETA_SIZE_128;
7550         }
7551 }
7552
7553 uint32_t
7554 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7555         switch (mac_type) {
7556         case ixgbe_mac_X550:
7557         case ixgbe_mac_X550EM_x:
7558         case ixgbe_mac_X550EM_a:
7559                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7560                         return IXGBE_RETA(reta_idx >> 2);
7561                 else
7562                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7563         case ixgbe_mac_X550_vf:
7564         case ixgbe_mac_X550EM_x_vf:
7565         case ixgbe_mac_X550EM_a_vf:
7566                 return IXGBE_VFRETA(reta_idx >> 2);
7567         default:
7568                 return IXGBE_RETA(reta_idx >> 2);
7569         }
7570 }
7571
7572 uint32_t
7573 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7574         switch (mac_type) {
7575         case ixgbe_mac_X550_vf:
7576         case ixgbe_mac_X550EM_x_vf:
7577         case ixgbe_mac_X550EM_a_vf:
7578                 return IXGBE_VFMRQC;
7579         default:
7580                 return IXGBE_MRQC;
7581         }
7582 }
7583
7584 uint32_t
7585 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7586         switch (mac_type) {
7587         case ixgbe_mac_X550_vf:
7588         case ixgbe_mac_X550EM_x_vf:
7589         case ixgbe_mac_X550EM_a_vf:
7590                 return IXGBE_VFRSSRK(i);
7591         default:
7592                 return IXGBE_RSSRK(i);
7593         }
7594 }
7595
7596 bool
7597 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7598         switch (mac_type) {
7599         case ixgbe_mac_82599_vf:
7600         case ixgbe_mac_X540_vf:
7601                 return 0;
7602         default:
7603                 return 1;
7604         }
7605 }
7606
7607 static int
7608 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7609                         struct rte_eth_dcb_info *dcb_info)
7610 {
7611         struct ixgbe_dcb_config *dcb_config =
7612                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7613         struct ixgbe_dcb_tc_config *tc;
7614         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7615         uint8_t nb_tcs;
7616         uint8_t i, j;
7617
7618         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7619                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7620         else
7621                 dcb_info->nb_tcs = 1;
7622
7623         tc_queue = &dcb_info->tc_queue;
7624         nb_tcs = dcb_info->nb_tcs;
7625
7626         if (dcb_config->vt_mode) { /* vt is enabled*/
7627                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7628                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7629                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7630                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7631                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7632                         for (j = 0; j < nb_tcs; j++) {
7633                                 tc_queue->tc_rxq[0][j].base = j;
7634                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7635                                 tc_queue->tc_txq[0][j].base = j;
7636                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7637                         }
7638                 } else {
7639                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7640                                 for (j = 0; j < nb_tcs; j++) {
7641                                         tc_queue->tc_rxq[i][j].base =
7642                                                 i * nb_tcs + j;
7643                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7644                                         tc_queue->tc_txq[i][j].base =
7645                                                 i * nb_tcs + j;
7646                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7647                                 }
7648                         }
7649                 }
7650         } else { /* vt is disabled*/
7651                 struct rte_eth_dcb_rx_conf *rx_conf =
7652                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7653                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7654                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7655                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7656                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7657                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7658                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7659                         }
7660                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7661                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7662                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7663                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7664                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7665                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7666                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7667                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7668                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7669                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7670                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7671                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7672                         }
7673                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7674                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7675                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7676                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7677                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7678                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7679                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7680                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7681                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7682                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7683                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7684                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7685                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7686                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7687                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7688                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7689                 }
7690         }
7691         for (i = 0; i < dcb_info->nb_tcs; i++) {
7692                 tc = &dcb_config->tc_config[i];
7693                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7694         }
7695         return 0;
7696 }
7697
7698 /* Update e-tag ether type */
7699 static int
7700 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7701                             uint16_t ether_type)
7702 {
7703         uint32_t etag_etype;
7704
7705         if (hw->mac.type != ixgbe_mac_X550 &&
7706             hw->mac.type != ixgbe_mac_X550EM_x &&
7707             hw->mac.type != ixgbe_mac_X550EM_a) {
7708                 return -ENOTSUP;
7709         }
7710
7711         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7712         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7713         etag_etype |= ether_type;
7714         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7715         IXGBE_WRITE_FLUSH(hw);
7716
7717         return 0;
7718 }
7719
7720 /* Config l2 tunnel ether type */
7721 static int
7722 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7723                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7724 {
7725         int ret = 0;
7726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7727         struct ixgbe_l2_tn_info *l2_tn_info =
7728                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7729
7730         if (l2_tunnel == NULL)
7731                 return -EINVAL;
7732
7733         switch (l2_tunnel->l2_tunnel_type) {
7734         case RTE_L2_TUNNEL_TYPE_E_TAG:
7735                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7736                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7737                 break;
7738         default:
7739                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7740                 ret = -EINVAL;
7741                 break;
7742         }
7743
7744         return ret;
7745 }
7746
7747 /* Enable e-tag tunnel */
7748 static int
7749 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7750 {
7751         uint32_t etag_etype;
7752
7753         if (hw->mac.type != ixgbe_mac_X550 &&
7754             hw->mac.type != ixgbe_mac_X550EM_x &&
7755             hw->mac.type != ixgbe_mac_X550EM_a) {
7756                 return -ENOTSUP;
7757         }
7758
7759         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7760         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7761         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7762         IXGBE_WRITE_FLUSH(hw);
7763
7764         return 0;
7765 }
7766
7767 /* Enable l2 tunnel */
7768 static int
7769 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7770                            enum rte_eth_tunnel_type l2_tunnel_type)
7771 {
7772         int ret = 0;
7773         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7774         struct ixgbe_l2_tn_info *l2_tn_info =
7775                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7776
7777         switch (l2_tunnel_type) {
7778         case RTE_L2_TUNNEL_TYPE_E_TAG:
7779                 l2_tn_info->e_tag_en = TRUE;
7780                 ret = ixgbe_e_tag_enable(hw);
7781                 break;
7782         default:
7783                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7784                 ret = -EINVAL;
7785                 break;
7786         }
7787
7788         return ret;
7789 }
7790
7791 /* Disable e-tag tunnel */
7792 static int
7793 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7794 {
7795         uint32_t etag_etype;
7796
7797         if (hw->mac.type != ixgbe_mac_X550 &&
7798             hw->mac.type != ixgbe_mac_X550EM_x &&
7799             hw->mac.type != ixgbe_mac_X550EM_a) {
7800                 return -ENOTSUP;
7801         }
7802
7803         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7804         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7805         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7806         IXGBE_WRITE_FLUSH(hw);
7807
7808         return 0;
7809 }
7810
7811 /* Disable l2 tunnel */
7812 static int
7813 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7814                             enum rte_eth_tunnel_type l2_tunnel_type)
7815 {
7816         int ret = 0;
7817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7818         struct ixgbe_l2_tn_info *l2_tn_info =
7819                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7820
7821         switch (l2_tunnel_type) {
7822         case RTE_L2_TUNNEL_TYPE_E_TAG:
7823                 l2_tn_info->e_tag_en = FALSE;
7824                 ret = ixgbe_e_tag_disable(hw);
7825                 break;
7826         default:
7827                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7828                 ret = -EINVAL;
7829                 break;
7830         }
7831
7832         return ret;
7833 }
7834
7835 static int
7836 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7837                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7838 {
7839         int ret = 0;
7840         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7841         uint32_t i, rar_entries;
7842         uint32_t rar_low, rar_high;
7843
7844         if (hw->mac.type != ixgbe_mac_X550 &&
7845             hw->mac.type != ixgbe_mac_X550EM_x &&
7846             hw->mac.type != ixgbe_mac_X550EM_a) {
7847                 return -ENOTSUP;
7848         }
7849
7850         rar_entries = ixgbe_get_num_rx_addrs(hw);
7851
7852         for (i = 1; i < rar_entries; i++) {
7853                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7854                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7855                 if ((rar_high & IXGBE_RAH_AV) &&
7856                     (rar_high & IXGBE_RAH_ADTYPE) &&
7857                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7858                      l2_tunnel->tunnel_id)) {
7859                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7860                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7861
7862                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7863
7864                         return ret;
7865                 }
7866         }
7867
7868         return ret;
7869 }
7870
7871 static int
7872 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7873                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7874 {
7875         int ret = 0;
7876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7877         uint32_t i, rar_entries;
7878         uint32_t rar_low, rar_high;
7879
7880         if (hw->mac.type != ixgbe_mac_X550 &&
7881             hw->mac.type != ixgbe_mac_X550EM_x &&
7882             hw->mac.type != ixgbe_mac_X550EM_a) {
7883                 return -ENOTSUP;
7884         }
7885
7886         /* One entry for one tunnel. Try to remove potential existing entry. */
7887         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7888
7889         rar_entries = ixgbe_get_num_rx_addrs(hw);
7890
7891         for (i = 1; i < rar_entries; i++) {
7892                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7893                 if (rar_high & IXGBE_RAH_AV) {
7894                         continue;
7895                 } else {
7896                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7897                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7898                         rar_low = l2_tunnel->tunnel_id;
7899
7900                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7901                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7902
7903                         return ret;
7904                 }
7905         }
7906
7907         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7908                      " Please remove a rule before adding a new one.");
7909         return -EINVAL;
7910 }
7911
7912 static inline struct ixgbe_l2_tn_filter *
7913 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7914                           struct ixgbe_l2_tn_key *key)
7915 {
7916         int ret;
7917
7918         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7919         if (ret < 0)
7920                 return NULL;
7921
7922         return l2_tn_info->hash_map[ret];
7923 }
7924
7925 static inline int
7926 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7927                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7928 {
7929         int ret;
7930
7931         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7932                                &l2_tn_filter->key);
7933
7934         if (ret < 0) {
7935                 PMD_DRV_LOG(ERR,
7936                             "Failed to insert L2 tunnel filter"
7937                             " to hash table %d!",
7938                             ret);
7939                 return ret;
7940         }
7941
7942         l2_tn_info->hash_map[ret] = l2_tn_filter;
7943
7944         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7945
7946         return 0;
7947 }
7948
7949 static inline int
7950 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7951                           struct ixgbe_l2_tn_key *key)
7952 {
7953         int ret;
7954         struct ixgbe_l2_tn_filter *l2_tn_filter;
7955
7956         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7957
7958         if (ret < 0) {
7959                 PMD_DRV_LOG(ERR,
7960                             "No such L2 tunnel filter to delete %d!",
7961                             ret);
7962                 return ret;
7963         }
7964
7965         l2_tn_filter = l2_tn_info->hash_map[ret];
7966         l2_tn_info->hash_map[ret] = NULL;
7967
7968         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7969         rte_free(l2_tn_filter);
7970
7971         return 0;
7972 }
7973
7974 /* Add l2 tunnel filter */
7975 int
7976 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7977                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7978                                bool restore)
7979 {
7980         int ret;
7981         struct ixgbe_l2_tn_info *l2_tn_info =
7982                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7983         struct ixgbe_l2_tn_key key;
7984         struct ixgbe_l2_tn_filter *node;
7985
7986         if (!restore) {
7987                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7988                 key.tn_id = l2_tunnel->tunnel_id;
7989
7990                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7991
7992                 if (node) {
7993                         PMD_DRV_LOG(ERR,
7994                                     "The L2 tunnel filter already exists!");
7995                         return -EINVAL;
7996                 }
7997
7998                 node = rte_zmalloc("ixgbe_l2_tn",
7999                                    sizeof(struct ixgbe_l2_tn_filter),
8000                                    0);
8001                 if (!node)
8002                         return -ENOMEM;
8003
8004                 rte_memcpy(&node->key,
8005                                  &key,
8006                                  sizeof(struct ixgbe_l2_tn_key));
8007                 node->pool = l2_tunnel->pool;
8008                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8009                 if (ret < 0) {
8010                         rte_free(node);
8011                         return ret;
8012                 }
8013         }
8014
8015         switch (l2_tunnel->l2_tunnel_type) {
8016         case RTE_L2_TUNNEL_TYPE_E_TAG:
8017                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8018                 break;
8019         default:
8020                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8021                 ret = -EINVAL;
8022                 break;
8023         }
8024
8025         if ((!restore) && (ret < 0))
8026                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8027
8028         return ret;
8029 }
8030
8031 /* Delete l2 tunnel filter */
8032 int
8033 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8034                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8035 {
8036         int ret;
8037         struct ixgbe_l2_tn_info *l2_tn_info =
8038                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8039         struct ixgbe_l2_tn_key key;
8040
8041         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8042         key.tn_id = l2_tunnel->tunnel_id;
8043         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8044         if (ret < 0)
8045                 return ret;
8046
8047         switch (l2_tunnel->l2_tunnel_type) {
8048         case RTE_L2_TUNNEL_TYPE_E_TAG:
8049                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8050                 break;
8051         default:
8052                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8053                 ret = -EINVAL;
8054                 break;
8055         }
8056
8057         return ret;
8058 }
8059
8060 /**
8061  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8062  * @dev: pointer to rte_eth_dev structure
8063  * @filter_op:operation will be taken.
8064  * @arg: a pointer to specific structure corresponding to the filter_op
8065  */
8066 static int
8067 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8068                                   enum rte_filter_op filter_op,
8069                                   void *arg)
8070 {
8071         int ret;
8072
8073         if (filter_op == RTE_ETH_FILTER_NOP)
8074                 return 0;
8075
8076         if (arg == NULL) {
8077                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8078                             filter_op);
8079                 return -EINVAL;
8080         }
8081
8082         switch (filter_op) {
8083         case RTE_ETH_FILTER_ADD:
8084                 ret = ixgbe_dev_l2_tunnel_filter_add
8085                         (dev,
8086                          (struct rte_eth_l2_tunnel_conf *)arg,
8087                          FALSE);
8088                 break;
8089         case RTE_ETH_FILTER_DELETE:
8090                 ret = ixgbe_dev_l2_tunnel_filter_del
8091                         (dev,
8092                          (struct rte_eth_l2_tunnel_conf *)arg);
8093                 break;
8094         default:
8095                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8096                 ret = -EINVAL;
8097                 break;
8098         }
8099         return ret;
8100 }
8101
8102 static int
8103 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8104 {
8105         int ret = 0;
8106         uint32_t ctrl;
8107         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8108
8109         if (hw->mac.type != ixgbe_mac_X550 &&
8110             hw->mac.type != ixgbe_mac_X550EM_x &&
8111             hw->mac.type != ixgbe_mac_X550EM_a) {
8112                 return -ENOTSUP;
8113         }
8114
8115         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8116         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8117         if (en)
8118                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8119         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8120
8121         return ret;
8122 }
8123
8124 /* Enable l2 tunnel forwarding */
8125 static int
8126 ixgbe_dev_l2_tunnel_forwarding_enable
8127         (struct rte_eth_dev *dev,
8128          enum rte_eth_tunnel_type l2_tunnel_type)
8129 {
8130         struct ixgbe_l2_tn_info *l2_tn_info =
8131                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8132         int ret = 0;
8133
8134         switch (l2_tunnel_type) {
8135         case RTE_L2_TUNNEL_TYPE_E_TAG:
8136                 l2_tn_info->e_tag_fwd_en = TRUE;
8137                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8138                 break;
8139         default:
8140                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8141                 ret = -EINVAL;
8142                 break;
8143         }
8144
8145         return ret;
8146 }
8147
8148 /* Disable l2 tunnel forwarding */
8149 static int
8150 ixgbe_dev_l2_tunnel_forwarding_disable
8151         (struct rte_eth_dev *dev,
8152          enum rte_eth_tunnel_type l2_tunnel_type)
8153 {
8154         struct ixgbe_l2_tn_info *l2_tn_info =
8155                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8156         int ret = 0;
8157
8158         switch (l2_tunnel_type) {
8159         case RTE_L2_TUNNEL_TYPE_E_TAG:
8160                 l2_tn_info->e_tag_fwd_en = FALSE;
8161                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8162                 break;
8163         default:
8164                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8165                 ret = -EINVAL;
8166                 break;
8167         }
8168
8169         return ret;
8170 }
8171
8172 static int
8173 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8174                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8175                              bool en)
8176 {
8177         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8178         int ret = 0;
8179         uint32_t vmtir, vmvir;
8180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8181
8182         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8183                 PMD_DRV_LOG(ERR,
8184                             "VF id %u should be less than %u",
8185                             l2_tunnel->vf_id,
8186                             pci_dev->max_vfs);
8187                 return -EINVAL;
8188         }
8189
8190         if (hw->mac.type != ixgbe_mac_X550 &&
8191             hw->mac.type != ixgbe_mac_X550EM_x &&
8192             hw->mac.type != ixgbe_mac_X550EM_a) {
8193                 return -ENOTSUP;
8194         }
8195
8196         if (en)
8197                 vmtir = l2_tunnel->tunnel_id;
8198         else
8199                 vmtir = 0;
8200
8201         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8202
8203         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8204         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8205         if (en)
8206                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8207         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8208
8209         return ret;
8210 }
8211
8212 /* Enable l2 tunnel tag insertion */
8213 static int
8214 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8215                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8216 {
8217         int ret = 0;
8218
8219         switch (l2_tunnel->l2_tunnel_type) {
8220         case RTE_L2_TUNNEL_TYPE_E_TAG:
8221                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8222                 break;
8223         default:
8224                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8225                 ret = -EINVAL;
8226                 break;
8227         }
8228
8229         return ret;
8230 }
8231
8232 /* Disable l2 tunnel tag insertion */
8233 static int
8234 ixgbe_dev_l2_tunnel_insertion_disable
8235         (struct rte_eth_dev *dev,
8236          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8237 {
8238         int ret = 0;
8239
8240         switch (l2_tunnel->l2_tunnel_type) {
8241         case RTE_L2_TUNNEL_TYPE_E_TAG:
8242                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8243                 break;
8244         default:
8245                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8246                 ret = -EINVAL;
8247                 break;
8248         }
8249
8250         return ret;
8251 }
8252
8253 static int
8254 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8255                              bool en)
8256 {
8257         int ret = 0;
8258         uint32_t qde;
8259         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8260
8261         if (hw->mac.type != ixgbe_mac_X550 &&
8262             hw->mac.type != ixgbe_mac_X550EM_x &&
8263             hw->mac.type != ixgbe_mac_X550EM_a) {
8264                 return -ENOTSUP;
8265         }
8266
8267         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8268         if (en)
8269                 qde |= IXGBE_QDE_STRIP_TAG;
8270         else
8271                 qde &= ~IXGBE_QDE_STRIP_TAG;
8272         qde &= ~IXGBE_QDE_READ;
8273         qde |= IXGBE_QDE_WRITE;
8274         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8275
8276         return ret;
8277 }
8278
8279 /* Enable l2 tunnel tag stripping */
8280 static int
8281 ixgbe_dev_l2_tunnel_stripping_enable
8282         (struct rte_eth_dev *dev,
8283          enum rte_eth_tunnel_type l2_tunnel_type)
8284 {
8285         int ret = 0;
8286
8287         switch (l2_tunnel_type) {
8288         case RTE_L2_TUNNEL_TYPE_E_TAG:
8289                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8290                 break;
8291         default:
8292                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8293                 ret = -EINVAL;
8294                 break;
8295         }
8296
8297         return ret;
8298 }
8299
8300 /* Disable l2 tunnel tag stripping */
8301 static int
8302 ixgbe_dev_l2_tunnel_stripping_disable
8303         (struct rte_eth_dev *dev,
8304          enum rte_eth_tunnel_type l2_tunnel_type)
8305 {
8306         int ret = 0;
8307
8308         switch (l2_tunnel_type) {
8309         case RTE_L2_TUNNEL_TYPE_E_TAG:
8310                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8311                 break;
8312         default:
8313                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8314                 ret = -EINVAL;
8315                 break;
8316         }
8317
8318         return ret;
8319 }
8320
8321 /* Enable/disable l2 tunnel offload functions */
8322 static int
8323 ixgbe_dev_l2_tunnel_offload_set
8324         (struct rte_eth_dev *dev,
8325          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8326          uint32_t mask,
8327          uint8_t en)
8328 {
8329         int ret = 0;
8330
8331         if (l2_tunnel == NULL)
8332                 return -EINVAL;
8333
8334         ret = -EINVAL;
8335         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8336                 if (en)
8337                         ret = ixgbe_dev_l2_tunnel_enable(
8338                                 dev,
8339                                 l2_tunnel->l2_tunnel_type);
8340                 else
8341                         ret = ixgbe_dev_l2_tunnel_disable(
8342                                 dev,
8343                                 l2_tunnel->l2_tunnel_type);
8344         }
8345
8346         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8347                 if (en)
8348                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8349                                 dev,
8350                                 l2_tunnel);
8351                 else
8352                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8353                                 dev,
8354                                 l2_tunnel);
8355         }
8356
8357         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8358                 if (en)
8359                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8360                                 dev,
8361                                 l2_tunnel->l2_tunnel_type);
8362                 else
8363                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8364                                 dev,
8365                                 l2_tunnel->l2_tunnel_type);
8366         }
8367
8368         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8369                 if (en)
8370                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8371                                 dev,
8372                                 l2_tunnel->l2_tunnel_type);
8373                 else
8374                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8375                                 dev,
8376                                 l2_tunnel->l2_tunnel_type);
8377         }
8378
8379         return ret;
8380 }
8381
8382 static int
8383 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8384                         uint16_t port)
8385 {
8386         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8387         IXGBE_WRITE_FLUSH(hw);
8388
8389         return 0;
8390 }
8391
8392 /* There's only one register for VxLAN UDP port.
8393  * So, we cannot add several ports. Will update it.
8394  */
8395 static int
8396 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8397                      uint16_t port)
8398 {
8399         if (port == 0) {
8400                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8401                 return -EINVAL;
8402         }
8403
8404         return ixgbe_update_vxlan_port(hw, port);
8405 }
8406
8407 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8408  * UDP port, it must have a value.
8409  * So, will reset it to the original value 0.
8410  */
8411 static int
8412 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8413                      uint16_t port)
8414 {
8415         uint16_t cur_port;
8416
8417         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8418
8419         if (cur_port != port) {
8420                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8421                 return -EINVAL;
8422         }
8423
8424         return ixgbe_update_vxlan_port(hw, 0);
8425 }
8426
8427 /* Add UDP tunneling port */
8428 static int
8429 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8430                               struct rte_eth_udp_tunnel *udp_tunnel)
8431 {
8432         int ret = 0;
8433         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8434
8435         if (hw->mac.type != ixgbe_mac_X550 &&
8436             hw->mac.type != ixgbe_mac_X550EM_x &&
8437             hw->mac.type != ixgbe_mac_X550EM_a) {
8438                 return -ENOTSUP;
8439         }
8440
8441         if (udp_tunnel == NULL)
8442                 return -EINVAL;
8443
8444         switch (udp_tunnel->prot_type) {
8445         case RTE_TUNNEL_TYPE_VXLAN:
8446                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8447                 break;
8448
8449         case RTE_TUNNEL_TYPE_GENEVE:
8450         case RTE_TUNNEL_TYPE_TEREDO:
8451                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8452                 ret = -EINVAL;
8453                 break;
8454
8455         default:
8456                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8457                 ret = -EINVAL;
8458                 break;
8459         }
8460
8461         return ret;
8462 }
8463
8464 /* Remove UDP tunneling port */
8465 static int
8466 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8467                               struct rte_eth_udp_tunnel *udp_tunnel)
8468 {
8469         int ret = 0;
8470         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8471
8472         if (hw->mac.type != ixgbe_mac_X550 &&
8473             hw->mac.type != ixgbe_mac_X550EM_x &&
8474             hw->mac.type != ixgbe_mac_X550EM_a) {
8475                 return -ENOTSUP;
8476         }
8477
8478         if (udp_tunnel == NULL)
8479                 return -EINVAL;
8480
8481         switch (udp_tunnel->prot_type) {
8482         case RTE_TUNNEL_TYPE_VXLAN:
8483                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8484                 break;
8485         case RTE_TUNNEL_TYPE_GENEVE:
8486         case RTE_TUNNEL_TYPE_TEREDO:
8487                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8488                 ret = -EINVAL;
8489                 break;
8490         default:
8491                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8492                 ret = -EINVAL;
8493                 break;
8494         }
8495
8496         return ret;
8497 }
8498
8499 static int
8500 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8501 {
8502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8503         int ret;
8504
8505         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8506         case IXGBE_SUCCESS:
8507                 ret = 0;
8508                 break;
8509         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8510                 ret = -ENOTSUP;
8511                 break;
8512         default:
8513                 ret = -EAGAIN;
8514                 break;
8515         }
8516
8517         return ret;
8518 }
8519
8520 static int
8521 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8522 {
8523         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8524         int ret;
8525
8526         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8527         case IXGBE_SUCCESS:
8528                 ret = 0;
8529                 break;
8530         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8531                 ret = -ENOTSUP;
8532                 break;
8533         default:
8534                 ret = -EAGAIN;
8535                 break;
8536         }
8537
8538         return ret;
8539 }
8540
8541 static int
8542 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8543 {
8544         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8545         int ret;
8546         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8547
8548         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8549         case IXGBE_SUCCESS:
8550                 ret = 0;
8551                 break;
8552         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8553                 ret = -ENOTSUP;
8554                 break;
8555         default:
8556                 ret = -EAGAIN;
8557                 break;
8558         }
8559
8560         return ret;
8561 }
8562
8563 static int
8564 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8565 {
8566         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8567         int ret;
8568
8569         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8570         case IXGBE_SUCCESS:
8571                 ret = 0;
8572                 break;
8573         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8574                 ret = -ENOTSUP;
8575                 break;
8576         default:
8577                 ret = -EAGAIN;
8578                 break;
8579         }
8580
8581         return ret;
8582 }
8583
8584 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8585 {
8586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8587         u32 in_msg = 0;
8588
8589         /* peek the message first */
8590         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8591
8592         /* PF reset VF event */
8593         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8594                 /* dummy mbx read to ack pf */
8595                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8596                         return;
8597                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8598                                               NULL);
8599         }
8600 }
8601
8602 static int
8603 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8604 {
8605         uint32_t eicr;
8606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8607         struct ixgbe_interrupt *intr =
8608                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8609         ixgbevf_intr_disable(dev);
8610
8611         /* read-on-clear nic registers here */
8612         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8613         intr->flags = 0;
8614
8615         /* only one misc vector supported - mailbox */
8616         eicr &= IXGBE_VTEICR_MASK;
8617         if (eicr == IXGBE_MISC_VEC_ID)
8618                 intr->flags |= IXGBE_FLAG_MAILBOX;
8619
8620         return 0;
8621 }
8622
8623 static int
8624 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8625 {
8626         struct ixgbe_interrupt *intr =
8627                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8628
8629         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8630                 ixgbevf_mbx_process(dev);
8631                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8632         }
8633
8634         ixgbevf_intr_enable(dev);
8635
8636         return 0;
8637 }
8638
8639 static void
8640 ixgbevf_dev_interrupt_handler(void *param)
8641 {
8642         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8643
8644         ixgbevf_dev_interrupt_get_status(dev);
8645         ixgbevf_dev_interrupt_action(dev);
8646 }
8647
8648 /**
8649  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8650  *  @hw: pointer to hardware structure
8651  *
8652  *  Stops the transmit data path and waits for the HW to internally empty
8653  *  the Tx security block
8654  **/
8655 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8656 {
8657 #define IXGBE_MAX_SECTX_POLL 40
8658
8659         int i;
8660         int sectxreg;
8661
8662         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8663         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8664         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8665         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8666                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8667                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8668                         break;
8669                 /* Use interrupt-safe sleep just in case */
8670                 usec_delay(1000);
8671         }
8672
8673         /* For informational purposes only */
8674         if (i >= IXGBE_MAX_SECTX_POLL)
8675                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8676                          "path fully disabled.  Continuing with init.");
8677
8678         return IXGBE_SUCCESS;
8679 }
8680
8681 /**
8682  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8683  *  @hw: pointer to hardware structure
8684  *
8685  *  Enables the transmit data path.
8686  **/
8687 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8688 {
8689         uint32_t sectxreg;
8690
8691         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8692         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8693         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8694         IXGBE_WRITE_FLUSH(hw);
8695
8696         return IXGBE_SUCCESS;
8697 }
8698
8699 /* restore n-tuple filter */
8700 static inline void
8701 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8702 {
8703         struct ixgbe_filter_info *filter_info =
8704                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8705         struct ixgbe_5tuple_filter *node;
8706
8707         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8708                 ixgbe_inject_5tuple_filter(dev, node);
8709         }
8710 }
8711
8712 /* restore ethernet type filter */
8713 static inline void
8714 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8715 {
8716         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8717         struct ixgbe_filter_info *filter_info =
8718                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8719         int i;
8720
8721         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8722                 if (filter_info->ethertype_mask & (1 << i)) {
8723                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8724                                         filter_info->ethertype_filters[i].etqf);
8725                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8726                                         filter_info->ethertype_filters[i].etqs);
8727                         IXGBE_WRITE_FLUSH(hw);
8728                 }
8729         }
8730 }
8731
8732 /* restore SYN filter */
8733 static inline void
8734 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8735 {
8736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8737         struct ixgbe_filter_info *filter_info =
8738                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8739         uint32_t synqf;
8740
8741         synqf = filter_info->syn_info;
8742
8743         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8744                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8745                 IXGBE_WRITE_FLUSH(hw);
8746         }
8747 }
8748
8749 /* restore L2 tunnel filter */
8750 static inline void
8751 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8752 {
8753         struct ixgbe_l2_tn_info *l2_tn_info =
8754                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8755         struct ixgbe_l2_tn_filter *node;
8756         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8757
8758         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8759                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8760                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8761                 l2_tn_conf.pool           = node->pool;
8762                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8763         }
8764 }
8765
8766 /* restore rss filter */
8767 static inline void
8768 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8769 {
8770         struct ixgbe_filter_info *filter_info =
8771                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8772
8773         if (filter_info->rss_info.conf.queue_num)
8774                 ixgbe_config_rss_filter(dev,
8775                         &filter_info->rss_info, TRUE);
8776 }
8777
8778 static int
8779 ixgbe_filter_restore(struct rte_eth_dev *dev)
8780 {
8781         ixgbe_ntuple_filter_restore(dev);
8782         ixgbe_ethertype_filter_restore(dev);
8783         ixgbe_syn_filter_restore(dev);
8784         ixgbe_fdir_filter_restore(dev);
8785         ixgbe_l2_tn_filter_restore(dev);
8786         ixgbe_rss_filter_restore(dev);
8787
8788         return 0;
8789 }
8790
8791 static void
8792 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8793 {
8794         struct ixgbe_l2_tn_info *l2_tn_info =
8795                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8797
8798         if (l2_tn_info->e_tag_en)
8799                 (void)ixgbe_e_tag_enable(hw);
8800
8801         if (l2_tn_info->e_tag_fwd_en)
8802                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8803
8804         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8805 }
8806
8807 /* remove all the n-tuple filters */
8808 void
8809 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8810 {
8811         struct ixgbe_filter_info *filter_info =
8812                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8813         struct ixgbe_5tuple_filter *p_5tuple;
8814
8815         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8816                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8817 }
8818
8819 /* remove all the ether type filters */
8820 void
8821 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8822 {
8823         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8824         struct ixgbe_filter_info *filter_info =
8825                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8826         int i;
8827
8828         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8829                 if (filter_info->ethertype_mask & (1 << i) &&
8830                     !filter_info->ethertype_filters[i].conf) {
8831                         (void)ixgbe_ethertype_filter_remove(filter_info,
8832                                                             (uint8_t)i);
8833                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8834                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8835                         IXGBE_WRITE_FLUSH(hw);
8836                 }
8837         }
8838 }
8839
8840 /* remove the SYN filter */
8841 void
8842 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8843 {
8844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8845         struct ixgbe_filter_info *filter_info =
8846                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8847
8848         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8849                 filter_info->syn_info = 0;
8850
8851                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8852                 IXGBE_WRITE_FLUSH(hw);
8853         }
8854 }
8855
8856 /* remove all the L2 tunnel filters */
8857 int
8858 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8859 {
8860         struct ixgbe_l2_tn_info *l2_tn_info =
8861                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8862         struct ixgbe_l2_tn_filter *l2_tn_filter;
8863         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8864         int ret = 0;
8865
8866         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8867                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8868                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8869                 l2_tn_conf.pool           = l2_tn_filter->pool;
8870                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8871                 if (ret < 0)
8872                         return ret;
8873         }
8874
8875         return 0;
8876 }
8877
8878 void
8879 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8880                                 struct ixgbe_macsec_setting *macsec_setting)
8881 {
8882         struct ixgbe_macsec_setting *macsec =
8883                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8884
8885         macsec->offload_en = macsec_setting->offload_en;
8886         macsec->encrypt_en = macsec_setting->encrypt_en;
8887         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8888 }
8889
8890 void
8891 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8892 {
8893         struct ixgbe_macsec_setting *macsec =
8894                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8895
8896         macsec->offload_en = 0;
8897         macsec->encrypt_en = 0;
8898         macsec->replayprotect_en = 0;
8899 }
8900
8901 void
8902 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8903                                 struct ixgbe_macsec_setting *macsec_setting)
8904 {
8905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8906         uint32_t ctrl;
8907         uint8_t en = macsec_setting->encrypt_en;
8908         uint8_t rp = macsec_setting->replayprotect_en;
8909
8910         /**
8911          * Workaround:
8912          * As no ixgbe_disable_sec_rx_path equivalent is
8913          * implemented for tx in the base code, and we are
8914          * not allowed to modify the base code in DPDK, so
8915          * just call the hand-written one directly for now.
8916          * The hardware support has been checked by
8917          * ixgbe_disable_sec_rx_path().
8918          */
8919         ixgbe_disable_sec_tx_path_generic(hw);
8920
8921         /* Enable Ethernet CRC (required by MACsec offload) */
8922         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8923         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8924         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8925
8926         /* Enable the TX and RX crypto engines */
8927         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8928         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8929         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8930
8931         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8932         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8933         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8934
8935         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8936         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8937         ctrl |= 0x3;
8938         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8939
8940         /* Enable SA lookup */
8941         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8942         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8943         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8944                      IXGBE_LSECTXCTRL_AUTH;
8945         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8946         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8947         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8948         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8949
8950         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8951         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8952         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8953         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8954         if (rp)
8955                 ctrl |= IXGBE_LSECRXCTRL_RP;
8956         else
8957                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8958         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8959
8960         /* Start the data paths */
8961         ixgbe_enable_sec_rx_path(hw);
8962         /**
8963          * Workaround:
8964          * As no ixgbe_enable_sec_rx_path equivalent is
8965          * implemented for tx in the base code, and we are
8966          * not allowed to modify the base code in DPDK, so
8967          * just call the hand-written one directly for now.
8968          */
8969         ixgbe_enable_sec_tx_path_generic(hw);
8970 }
8971
8972 void
8973 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8974 {
8975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8976         uint32_t ctrl;
8977
8978         /**
8979          * Workaround:
8980          * As no ixgbe_disable_sec_rx_path equivalent is
8981          * implemented for tx in the base code, and we are
8982          * not allowed to modify the base code in DPDK, so
8983          * just call the hand-written one directly for now.
8984          * The hardware support has been checked by
8985          * ixgbe_disable_sec_rx_path().
8986          */
8987         ixgbe_disable_sec_tx_path_generic(hw);
8988
8989         /* Disable the TX and RX crypto engines */
8990         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8991         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8992         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8993
8994         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8995         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8996         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8997
8998         /* Disable SA lookup */
8999         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9000         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9001         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9002         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9003
9004         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9005         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9006         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9007         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9008
9009         /* Start the data paths */
9010         ixgbe_enable_sec_rx_path(hw);
9011         /**
9012          * Workaround:
9013          * As no ixgbe_enable_sec_rx_path equivalent is
9014          * implemented for tx in the base code, and we are
9015          * not allowed to modify the base code in DPDK, so
9016          * just call the hand-written one directly for now.
9017          */
9018         ixgbe_enable_sec_tx_path_generic(hw);
9019 }
9020
9021 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9022 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9023 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9024 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9025 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9026 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9027 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9028                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9029
9030 RTE_INIT(ixgbe_init_log)
9031 {
9032         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9033         if (ixgbe_logtype_init >= 0)
9034                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9035         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9036         if (ixgbe_logtype_driver >= 0)
9037                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9038 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9039         ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9040         if (ixgbe_logtype_rx >= 0)
9041                 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9042 #endif
9043
9044 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9045         ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9046         if (ixgbe_logtype_tx >= 0)
9047                 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9048 #endif
9049
9050 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9051         ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9052         if (ixgbe_logtype_tx_free >= 0)
9053                 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);
9054 #endif
9055 }