4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
64 #include <rte_security_driver.h>
66 #include "ixgbe_logs.h"
67 #include "base/ixgbe_api.h"
68 #include "base/ixgbe_vf.h"
69 #include "base/ixgbe_common.h"
70 #include "ixgbe_ethdev.h"
71 #include "ixgbe_bypass.h"
72 #include "ixgbe_rxtx.h"
73 #include "base/ixgbe_type.h"
74 #include "base/ixgbe_phy.h"
75 #include "ixgbe_regs.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 #define IXGBE_EXVET_VET_EXT_SHIFT 16
158 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
167 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
168 static int ixgbe_dev_start(struct rte_eth_dev *dev);
169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
173 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
179 int wait_to_complete);
180 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
181 struct rte_eth_stats *stats);
182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
187 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
188 uint64_t *values, unsigned int n);
189 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
190 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
191 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
192 struct rte_eth_xstat_name *xstats_names,
194 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
195 struct rte_eth_xstat_name *xstats_names, unsigned limit);
196 static int ixgbe_dev_xstats_get_names_by_id(
197 struct rte_eth_dev *dev,
198 struct rte_eth_xstat_name *xstats_names,
201 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
205 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
207 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
208 struct rte_eth_dev_info *dev_info);
209 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
210 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
211 struct rte_eth_dev_info *dev_info);
212 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
214 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
215 uint16_t vlan_id, int on);
216 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
217 enum rte_vlan_type vlan_type,
219 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
220 uint16_t queue, bool on);
221 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
223 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
224 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
226 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
227 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
230 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
231 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
232 struct rte_eth_fc_conf *fc_conf);
233 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
234 struct rte_eth_fc_conf *fc_conf);
235 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
236 struct rte_eth_pfc_conf *pfc_conf);
237 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
238 struct rte_eth_rss_reta_entry64 *reta_conf,
240 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
241 struct rte_eth_rss_reta_entry64 *reta_conf,
243 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
244 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
245 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
248 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
249 struct rte_intr_handle *handle);
250 static void ixgbe_dev_interrupt_handler(void *param);
251 static void ixgbe_dev_interrupt_delayed_handler(void *param);
252 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
253 uint32_t index, uint32_t pool);
254 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
255 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
256 struct ether_addr *mac_addr);
257 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
258 static bool is_device_supported(struct rte_eth_dev *dev,
259 struct rte_pci_driver *drv);
261 /* For Virtual Function support */
262 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
263 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
264 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
265 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
266 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
267 int wait_to_complete);
268 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
269 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
270 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
271 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
272 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
273 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
274 struct rte_eth_stats *stats);
275 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
276 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
277 uint16_t vlan_id, int on);
278 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
279 uint16_t queue, int on);
280 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
282 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
284 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
286 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
287 uint8_t queue, uint8_t msix_vector);
288 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
289 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
290 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
292 /* For Eth VMDQ APIs support */
293 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
294 ether_addr * mac_addr, uint8_t on);
295 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
296 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
297 struct rte_eth_mirror_conf *mirror_conf,
298 uint8_t rule_id, uint8_t on);
299 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
301 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
303 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
305 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
306 uint8_t queue, uint8_t msix_vector);
307 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
309 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
310 struct ether_addr *mac_addr,
311 uint32_t index, uint32_t pool);
312 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
313 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
314 struct ether_addr *mac_addr);
315 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
316 struct rte_eth_syn_filter *filter);
317 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
318 enum rte_filter_op filter_op,
320 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
321 struct ixgbe_5tuple_filter *filter);
322 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
323 struct ixgbe_5tuple_filter *filter);
324 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
328 struct rte_eth_ntuple_filter *filter);
329 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
330 enum rte_filter_op filter_op,
332 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
333 struct rte_eth_ethertype_filter *filter);
334 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
335 enum rte_filter_type filter_type,
336 enum rte_filter_op filter_op,
338 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
340 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
341 struct ether_addr *mc_addr_set,
342 uint32_t nb_mc_addr);
343 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
344 struct rte_eth_dcb_info *dcb_info);
346 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
347 static int ixgbe_get_regs(struct rte_eth_dev *dev,
348 struct rte_dev_reg_info *regs);
349 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
350 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
351 struct rte_dev_eeprom_info *eeprom);
352 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
353 struct rte_dev_eeprom_info *eeprom);
355 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
356 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
357 struct rte_dev_reg_info *regs);
359 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
360 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
361 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
362 struct timespec *timestamp,
364 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
365 struct timespec *timestamp);
366 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
367 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
368 struct timespec *timestamp);
369 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
370 const struct timespec *timestamp);
371 static void ixgbevf_dev_interrupt_handler(void *param);
373 static int ixgbe_dev_l2_tunnel_eth_type_conf
374 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
375 static int ixgbe_dev_l2_tunnel_offload_set
376 (struct rte_eth_dev *dev,
377 struct rte_eth_l2_tunnel_conf *l2_tunnel,
380 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
381 enum rte_filter_op filter_op,
384 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
385 struct rte_eth_udp_tunnel *udp_tunnel);
386 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
387 struct rte_eth_udp_tunnel *udp_tunnel);
388 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
389 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
392 * Define VF Stats MACRO for Non "cleared on read" register
394 #define UPDATE_VF_STAT(reg, last, cur) \
396 uint32_t latest = IXGBE_READ_REG(hw, reg); \
397 cur += (latest - last) & UINT_MAX; \
401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
403 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
404 u64 new_msb = IXGBE_READ_REG(hw, msb); \
405 u64 latest = ((new_msb << 32) | new_lsb); \
406 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
410 #define IXGBE_SET_HWSTRIP(h, q) do {\
411 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
412 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
413 (h)->bitmap[idx] |= 1 << bit;\
416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
417 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
418 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
419 (h)->bitmap[idx] &= ~(1 << bit);\
422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
423 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
424 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
425 (r) = (h)->bitmap[idx] >> bit & 1;\
429 * The set of PCI devices this driver supports
431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
480 #ifdef RTE_LIBRTE_IXGBE_BYPASS
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
483 { .vendor_id = 0, /* sentinel */ },
487 * The set of PCI devices this driver supports (for 82599 VF)
489 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
490 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
491 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
500 { .vendor_id = 0, /* sentinel */ },
503 static const struct rte_eth_desc_lim rx_desc_lim = {
504 .nb_max = IXGBE_MAX_RING_DESC,
505 .nb_min = IXGBE_MIN_RING_DESC,
506 .nb_align = IXGBE_RXD_ALIGN,
509 static const struct rte_eth_desc_lim tx_desc_lim = {
510 .nb_max = IXGBE_MAX_RING_DESC,
511 .nb_min = IXGBE_MIN_RING_DESC,
512 .nb_align = IXGBE_TXD_ALIGN,
513 .nb_seg_max = IXGBE_TX_MAX_SEG,
514 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
517 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
518 .dev_configure = ixgbe_dev_configure,
519 .dev_start = ixgbe_dev_start,
520 .dev_stop = ixgbe_dev_stop,
521 .dev_set_link_up = ixgbe_dev_set_link_up,
522 .dev_set_link_down = ixgbe_dev_set_link_down,
523 .dev_close = ixgbe_dev_close,
524 .dev_reset = ixgbe_dev_reset,
525 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
526 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
527 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
528 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
529 .link_update = ixgbe_dev_link_update,
530 .stats_get = ixgbe_dev_stats_get,
531 .xstats_get = ixgbe_dev_xstats_get,
532 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
533 .stats_reset = ixgbe_dev_stats_reset,
534 .xstats_reset = ixgbe_dev_xstats_reset,
535 .xstats_get_names = ixgbe_dev_xstats_get_names,
536 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
537 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
538 .fw_version_get = ixgbe_fw_version_get,
539 .dev_infos_get = ixgbe_dev_info_get,
540 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
541 .mtu_set = ixgbe_dev_mtu_set,
542 .vlan_filter_set = ixgbe_vlan_filter_set,
543 .vlan_tpid_set = ixgbe_vlan_tpid_set,
544 .vlan_offload_set = ixgbe_vlan_offload_set,
545 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
546 .rx_queue_start = ixgbe_dev_rx_queue_start,
547 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
548 .tx_queue_start = ixgbe_dev_tx_queue_start,
549 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
550 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
551 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
552 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
553 .rx_queue_release = ixgbe_dev_rx_queue_release,
554 .rx_queue_count = ixgbe_dev_rx_queue_count,
555 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
556 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
557 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
558 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
559 .tx_queue_release = ixgbe_dev_tx_queue_release,
560 .dev_led_on = ixgbe_dev_led_on,
561 .dev_led_off = ixgbe_dev_led_off,
562 .flow_ctrl_get = ixgbe_flow_ctrl_get,
563 .flow_ctrl_set = ixgbe_flow_ctrl_set,
564 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
565 .mac_addr_add = ixgbe_add_rar,
566 .mac_addr_remove = ixgbe_remove_rar,
567 .mac_addr_set = ixgbe_set_default_mac_addr,
568 .uc_hash_table_set = ixgbe_uc_hash_table_set,
569 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
570 .mirror_rule_set = ixgbe_mirror_rule_set,
571 .mirror_rule_reset = ixgbe_mirror_rule_reset,
572 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
573 .reta_update = ixgbe_dev_rss_reta_update,
574 .reta_query = ixgbe_dev_rss_reta_query,
575 .rss_hash_update = ixgbe_dev_rss_hash_update,
576 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
577 .filter_ctrl = ixgbe_dev_filter_ctrl,
578 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
579 .rxq_info_get = ixgbe_rxq_info_get,
580 .txq_info_get = ixgbe_txq_info_get,
581 .timesync_enable = ixgbe_timesync_enable,
582 .timesync_disable = ixgbe_timesync_disable,
583 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
584 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
585 .get_reg = ixgbe_get_regs,
586 .get_eeprom_length = ixgbe_get_eeprom_length,
587 .get_eeprom = ixgbe_get_eeprom,
588 .set_eeprom = ixgbe_set_eeprom,
589 .get_dcb_info = ixgbe_dev_get_dcb_info,
590 .timesync_adjust_time = ixgbe_timesync_adjust_time,
591 .timesync_read_time = ixgbe_timesync_read_time,
592 .timesync_write_time = ixgbe_timesync_write_time,
593 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
594 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
595 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
596 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
597 .tm_ops_get = ixgbe_tm_ops_get,
601 * dev_ops for virtual function, bare necessities for basic vf
602 * operation have been implemented
604 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
605 .dev_configure = ixgbevf_dev_configure,
606 .dev_start = ixgbevf_dev_start,
607 .dev_stop = ixgbevf_dev_stop,
608 .link_update = ixgbevf_dev_link_update,
609 .stats_get = ixgbevf_dev_stats_get,
610 .xstats_get = ixgbevf_dev_xstats_get,
611 .stats_reset = ixgbevf_dev_stats_reset,
612 .xstats_reset = ixgbevf_dev_stats_reset,
613 .xstats_get_names = ixgbevf_dev_xstats_get_names,
614 .dev_close = ixgbevf_dev_close,
615 .dev_reset = ixgbevf_dev_reset,
616 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
617 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
618 .dev_infos_get = ixgbevf_dev_info_get,
619 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
620 .mtu_set = ixgbevf_dev_set_mtu,
621 .vlan_filter_set = ixgbevf_vlan_filter_set,
622 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
623 .vlan_offload_set = ixgbevf_vlan_offload_set,
624 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
625 .rx_queue_release = ixgbe_dev_rx_queue_release,
626 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
627 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
628 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
629 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
630 .tx_queue_release = ixgbe_dev_tx_queue_release,
631 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
632 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
633 .mac_addr_add = ixgbevf_add_mac_addr,
634 .mac_addr_remove = ixgbevf_remove_mac_addr,
635 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
636 .rxq_info_get = ixgbe_rxq_info_get,
637 .txq_info_get = ixgbe_txq_info_get,
638 .mac_addr_set = ixgbevf_set_default_mac_addr,
639 .get_reg = ixgbevf_get_regs,
640 .reta_update = ixgbe_dev_rss_reta_update,
641 .reta_query = ixgbe_dev_rss_reta_query,
642 .rss_hash_update = ixgbe_dev_rss_hash_update,
643 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
646 /* store statistics names and its offset in stats structure */
647 struct rte_ixgbe_xstats_name_off {
648 char name[RTE_ETH_XSTATS_NAME_SIZE];
652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
653 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
654 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
655 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
656 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
657 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
658 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
659 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
660 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
661 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
662 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
663 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
664 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
665 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
666 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
667 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
669 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
671 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
672 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
673 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
674 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
675 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
676 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
677 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
678 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
679 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
680 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
681 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
682 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
683 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
684 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
685 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
686 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
687 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
689 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
691 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
692 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
693 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
694 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
696 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
698 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
700 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
702 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
704 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
709 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
710 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
711 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
713 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
714 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
715 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
716 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
717 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
719 {"rx_fcoe_no_direct_data_placement_ext_buff",
720 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
722 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
724 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
726 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
728 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
730 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
734 sizeof(rte_ixgbe_stats_strings[0]))
736 /* MACsec statistics */
737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
738 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
740 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
741 out_pkts_encrypted)},
742 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
743 out_pkts_protected)},
744 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
745 out_octets_encrypted)},
746 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
747 out_octets_protected)},
748 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
750 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
755 in_pkts_unknownsci)},
756 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
757 in_octets_decrypted)},
758 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
759 in_octets_validated)},
760 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
775 in_pkts_notusingsa)},
778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
779 sizeof(rte_ixgbe_macsec_strings[0]))
781 /* Per-queue statistics */
782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
783 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
784 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
785 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
786 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
790 sizeof(rte_ixgbe_rxq_strings[0]))
791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
794 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
795 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
796 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
801 sizeof(rte_ixgbe_txq_strings[0]))
802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
805 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
809 sizeof(rte_ixgbevf_stats_strings[0]))
812 * Atomically reads the link status information from global
813 * structure rte_eth_dev.
816 * - Pointer to the structure rte_eth_dev to read from.
817 * - Pointer to the buffer to be saved with the link status.
820 * - On success, zero.
821 * - On failure, negative value.
824 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
825 struct rte_eth_link *link)
827 struct rte_eth_link *dst = link;
828 struct rte_eth_link *src = &(dev->data->dev_link);
830 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
831 *(uint64_t *)src) == 0)
838 * Atomically writes the link status information into global
839 * structure rte_eth_dev.
842 * - Pointer to the structure rte_eth_dev to read from.
843 * - Pointer to the buffer to be saved with the link status.
846 * - On success, zero.
847 * - On failure, negative value.
850 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
851 struct rte_eth_link *link)
853 struct rte_eth_link *dst = &(dev->data->dev_link);
854 struct rte_eth_link *src = link;
856 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
857 *(uint64_t *)src) == 0)
864 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
867 ixgbe_is_sfp(struct ixgbe_hw *hw)
869 switch (hw->phy.type) {
870 case ixgbe_phy_sfp_avago:
871 case ixgbe_phy_sfp_ftl:
872 case ixgbe_phy_sfp_intel:
873 case ixgbe_phy_sfp_unknown:
874 case ixgbe_phy_sfp_passive_tyco:
875 case ixgbe_phy_sfp_passive_unknown:
882 static inline int32_t
883 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
888 status = ixgbe_reset_hw(hw);
890 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
891 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
892 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
893 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
894 IXGBE_WRITE_FLUSH(hw);
896 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
897 status = IXGBE_SUCCESS;
902 ixgbe_enable_intr(struct rte_eth_dev *dev)
904 struct ixgbe_interrupt *intr =
905 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
906 struct ixgbe_hw *hw =
907 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
909 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
910 IXGBE_WRITE_FLUSH(hw);
914 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
917 ixgbe_disable_intr(struct ixgbe_hw *hw)
919 PMD_INIT_FUNC_TRACE();
921 if (hw->mac.type == ixgbe_mac_82598EB) {
922 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
924 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
926 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
928 IXGBE_WRITE_FLUSH(hw);
932 * This function resets queue statistics mapping registers.
933 * From Niantic datasheet, Initialization of Statistics section:
934 * "...if software requires the queue counters, the RQSMR and TQSM registers
935 * must be re-programmed following a device reset.
938 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
942 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
943 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
944 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
950 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
955 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
956 #define NB_QMAP_FIELDS_PER_QSM_REG 4
957 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
960 struct ixgbe_stat_mapping_registers *stat_mappings =
961 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
962 uint32_t qsmr_mask = 0;
963 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
967 if ((hw->mac.type != ixgbe_mac_82599EB) &&
968 (hw->mac.type != ixgbe_mac_X540) &&
969 (hw->mac.type != ixgbe_mac_X550) &&
970 (hw->mac.type != ixgbe_mac_X550EM_x) &&
971 (hw->mac.type != ixgbe_mac_X550EM_a))
974 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
975 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
978 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
979 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
980 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
983 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
985 /* Now clear any previous stat_idx set */
986 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
988 stat_mappings->tqsm[n] &= ~clearing_mask;
990 stat_mappings->rqsmr[n] &= ~clearing_mask;
992 q_map = (uint32_t)stat_idx;
993 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
994 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
996 stat_mappings->tqsm[n] |= qsmr_mask;
998 stat_mappings->rqsmr[n] |= qsmr_mask;
1000 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1001 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1002 queue_id, stat_idx);
1003 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1004 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1006 /* Now write the mapping in the appropriate register */
1008 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1009 stat_mappings->rqsmr[n], n);
1010 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1012 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1013 stat_mappings->tqsm[n], n);
1014 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1020 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1022 struct ixgbe_stat_mapping_registers *stat_mappings =
1023 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027 /* write whatever was in stat mapping table to the NIC */
1028 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1030 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1033 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1041 struct ixgbe_dcb_tc_config *tc;
1042 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1044 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1045 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1046 for (i = 0; i < dcb_max_tc; i++) {
1047 tc = &dcb_config->tc_config[i];
1048 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1049 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1050 (uint8_t)(100/dcb_max_tc + (i & 1));
1051 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->pfc = ixgbe_dcb_pfc_disabled;
1057 /* Initialize default user to priority mapping, UPx->TC0 */
1058 tc = &dcb_config->tc_config[0];
1059 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1060 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1061 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1062 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1063 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1065 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1066 dcb_config->pfc_mode_enable = false;
1067 dcb_config->vt_mode = true;
1068 dcb_config->round_robin_enable = false;
1069 /* support all DCB capabilities in 82599 */
1070 dcb_config->support.capabilities = 0xFF;
1072 /*we only support 4 Tcs for X540, X550 */
1073 if (hw->mac.type == ixgbe_mac_X540 ||
1074 hw->mac.type == ixgbe_mac_X550 ||
1075 hw->mac.type == ixgbe_mac_X550EM_x ||
1076 hw->mac.type == ixgbe_mac_X550EM_a) {
1077 dcb_config->num_tcs.pg_tcs = 4;
1078 dcb_config->num_tcs.pfc_tcs = 4;
1083 * Ensure that all locks are released before first NVM or PHY access
1086 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 * Phy lock should not fail in this early stage. If this is the case,
1092 * it is due to an improper exit of the application.
1093 * So force the release of the faulty lock. Release of common lock
1094 * is done automatically by swfw_sync function.
1096 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1097 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1098 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1100 ixgbe_release_swfw_semaphore(hw, mask);
1103 * These ones are more tricky since they are common to all ports; but
1104 * swfw_sync retries last long enough (1s) to be almost sure that if
1105 * lock can not be taken it is due to an improper lock of the
1108 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1109 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1112 ixgbe_release_swfw_semaphore(hw, mask);
1116 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1117 * It returns 0 on success.
1120 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1122 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1123 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1124 struct ixgbe_hw *hw =
1125 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1126 struct ixgbe_vfta *shadow_vfta =
1127 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1128 struct ixgbe_hwstrip *hwstrip =
1129 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1130 struct ixgbe_dcb_config *dcb_config =
1131 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1132 struct ixgbe_filter_info *filter_info =
1133 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1134 struct ixgbe_bw_conf *bw_conf =
1135 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1140 PMD_INIT_FUNC_TRACE();
1142 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1143 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1144 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1145 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148 * For secondary processes, we don't initialise any further as primary
1149 * has already done this work. Only check we don't need a different
1150 * RX and TX function.
1152 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1153 struct ixgbe_tx_queue *txq;
1154 /* TX queue function in primary, set by last queue initialized
1155 * Tx queue may not initialized by primary process
1157 if (eth_dev->data->tx_queues) {
1158 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1159 ixgbe_set_tx_function(eth_dev, txq);
1161 /* Use default TX function if we get here */
1162 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1163 "Using default TX function.");
1166 ixgbe_set_rx_function(eth_dev);
1171 /* Initialize security_ctx only for primary process*/
1172 eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1173 if (eth_dev->security_ctx == NULL)
1176 rte_eth_copy_pci_info(eth_dev, pci_dev);
1178 /* Vendor and Device ID need to be set before init of shared code */
1179 hw->device_id = pci_dev->id.device_id;
1180 hw->vendor_id = pci_dev->id.vendor_id;
1181 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1182 hw->allow_unsupported_sfp = 1;
1184 /* Initialize the shared code (base driver) */
1185 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1186 diag = ixgbe_bypass_init_shared_code(hw);
1188 diag = ixgbe_init_shared_code(hw);
1189 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1191 if (diag != IXGBE_SUCCESS) {
1192 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1196 /* pick up the PCI bus settings for reporting later */
1197 ixgbe_get_bus_info(hw);
1199 /* Unlock any pending hardware semaphore */
1200 ixgbe_swfw_lock_reset(hw);
1202 /* Initialize DCB configuration*/
1203 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1204 ixgbe_dcb_init(hw, dcb_config);
1205 /* Get Hardware Flow Control setting */
1206 hw->fc.requested_mode = ixgbe_fc_full;
1207 hw->fc.current_mode = ixgbe_fc_full;
1208 hw->fc.pause_time = IXGBE_FC_PAUSE;
1209 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1210 hw->fc.low_water[i] = IXGBE_FC_LO;
1211 hw->fc.high_water[i] = IXGBE_FC_HI;
1213 hw->fc.send_xon = 1;
1215 /* Make sure we have a good EEPROM before we read from it */
1216 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1217 if (diag != IXGBE_SUCCESS) {
1218 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1222 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1223 diag = ixgbe_bypass_init_hw(hw);
1225 diag = ixgbe_init_hw(hw);
1226 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1229 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1230 * is called too soon after the kernel driver unbinding/binding occurs.
1231 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1232 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1233 * also called. See ixgbe_identify_phy_82599(). The reason for the
1234 * failure is not known, and only occuts when virtualisation features
1235 * are disabled in the bios. A delay of 100ms was found to be enough by
1236 * trial-and-error, and is doubled to be safe.
1238 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1240 diag = ixgbe_init_hw(hw);
1243 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1244 diag = IXGBE_SUCCESS;
1246 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1247 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1248 "LOM. Please be aware there may be issues associated "
1249 "with your hardware.");
1250 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1251 "please contact your Intel or hardware representative "
1252 "who provided you with this hardware.");
1253 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1254 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1256 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1260 /* Reset the hw statistics */
1261 ixgbe_dev_stats_reset(eth_dev);
1263 /* disable interrupt */
1264 ixgbe_disable_intr(hw);
1266 /* reset mappings for queue statistics hw counters*/
1267 ixgbe_reset_qstat_mappings(hw);
1269 /* Allocate memory for storing MAC addresses */
1270 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1271 hw->mac.num_rar_entries, 0);
1272 if (eth_dev->data->mac_addrs == NULL) {
1274 "Failed to allocate %u bytes needed to store "
1276 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1279 /* Copy the permanent MAC address */
1280 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1281 ð_dev->data->mac_addrs[0]);
1283 /* Allocate memory for storing hash filter MAC addresses */
1284 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1285 IXGBE_VMDQ_NUM_UC_MAC, 0);
1286 if (eth_dev->data->hash_mac_addrs == NULL) {
1288 "Failed to allocate %d bytes needed to store MAC addresses",
1289 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1293 /* initialize the vfta */
1294 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1296 /* initialize the hw strip bitmap*/
1297 memset(hwstrip, 0, sizeof(*hwstrip));
1299 /* initialize PF if max_vfs not zero */
1300 ixgbe_pf_host_init(eth_dev);
1302 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1303 /* let hardware know driver is loaded */
1304 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1305 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1306 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1307 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1308 IXGBE_WRITE_FLUSH(hw);
1310 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1311 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1312 (int) hw->mac.type, (int) hw->phy.type,
1313 (int) hw->phy.sfp_type);
1315 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1316 (int) hw->mac.type, (int) hw->phy.type);
1318 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1319 eth_dev->data->port_id, pci_dev->id.vendor_id,
1320 pci_dev->id.device_id);
1322 rte_intr_callback_register(intr_handle,
1323 ixgbe_dev_interrupt_handler, eth_dev);
1325 /* enable uio/vfio intr/eventfd mapping */
1326 rte_intr_enable(intr_handle);
1328 /* enable support intr */
1329 ixgbe_enable_intr(eth_dev);
1331 /* initialize filter info */
1332 memset(filter_info, 0,
1333 sizeof(struct ixgbe_filter_info));
1335 /* initialize 5tuple filter list */
1336 TAILQ_INIT(&filter_info->fivetuple_list);
1338 /* initialize flow director filter list & hash */
1339 ixgbe_fdir_filter_init(eth_dev);
1341 /* initialize l2 tunnel filter list & hash */
1342 ixgbe_l2_tn_filter_init(eth_dev);
1344 /* initialize flow filter lists */
1345 ixgbe_filterlist_init();
1347 /* initialize bandwidth configuration info */
1348 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1350 /* initialize Traffic Manager configuration */
1351 ixgbe_tm_conf_init(eth_dev);
1357 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1359 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1360 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1361 struct ixgbe_hw *hw;
1363 PMD_INIT_FUNC_TRACE();
1365 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1368 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370 if (hw->adapter_stopped == 0)
1371 ixgbe_dev_close(eth_dev);
1373 eth_dev->dev_ops = NULL;
1374 eth_dev->rx_pkt_burst = NULL;
1375 eth_dev->tx_pkt_burst = NULL;
1377 /* Unlock any pending hardware semaphore */
1378 ixgbe_swfw_lock_reset(hw);
1380 /* disable uio intr before callback unregister */
1381 rte_intr_disable(intr_handle);
1382 rte_intr_callback_unregister(intr_handle,
1383 ixgbe_dev_interrupt_handler, eth_dev);
1385 /* uninitialize PF if max_vfs not zero */
1386 ixgbe_pf_host_uninit(eth_dev);
1388 rte_free(eth_dev->data->mac_addrs);
1389 eth_dev->data->mac_addrs = NULL;
1391 rte_free(eth_dev->data->hash_mac_addrs);
1392 eth_dev->data->hash_mac_addrs = NULL;
1394 /* remove all the fdir filters & hash */
1395 ixgbe_fdir_filter_uninit(eth_dev);
1397 /* remove all the L2 tunnel filters & hash */
1398 ixgbe_l2_tn_filter_uninit(eth_dev);
1400 /* Remove all ntuple filters of the device */
1401 ixgbe_ntuple_filter_uninit(eth_dev);
1403 /* clear all the filters list */
1404 ixgbe_filterlist_flush();
1406 /* Remove all Traffic Manager configuration */
1407 ixgbe_tm_conf_uninit(eth_dev);
1409 rte_free(eth_dev->security_ctx);
1414 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1416 struct ixgbe_filter_info *filter_info =
1417 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1418 struct ixgbe_5tuple_filter *p_5tuple;
1420 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1421 TAILQ_REMOVE(&filter_info->fivetuple_list,
1426 memset(filter_info->fivetuple_mask, 0,
1427 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1432 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1434 struct ixgbe_hw_fdir_info *fdir_info =
1435 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1436 struct ixgbe_fdir_filter *fdir_filter;
1438 if (fdir_info->hash_map)
1439 rte_free(fdir_info->hash_map);
1440 if (fdir_info->hash_handle)
1441 rte_hash_free(fdir_info->hash_handle);
1443 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1444 TAILQ_REMOVE(&fdir_info->fdir_list,
1447 rte_free(fdir_filter);
1453 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1455 struct ixgbe_l2_tn_info *l2_tn_info =
1456 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457 struct ixgbe_l2_tn_filter *l2_tn_filter;
1459 if (l2_tn_info->hash_map)
1460 rte_free(l2_tn_info->hash_map);
1461 if (l2_tn_info->hash_handle)
1462 rte_hash_free(l2_tn_info->hash_handle);
1464 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1465 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1468 rte_free(l2_tn_filter);
1474 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1476 struct ixgbe_hw_fdir_info *fdir_info =
1477 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1478 char fdir_hash_name[RTE_HASH_NAMESIZE];
1479 struct rte_hash_parameters fdir_hash_params = {
1480 .name = fdir_hash_name,
1481 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1482 .key_len = sizeof(union ixgbe_atr_input),
1483 .hash_func = rte_hash_crc,
1484 .hash_func_init_val = 0,
1485 .socket_id = rte_socket_id(),
1488 TAILQ_INIT(&fdir_info->fdir_list);
1489 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1490 "fdir_%s", eth_dev->device->name);
1491 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1492 if (!fdir_info->hash_handle) {
1493 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1496 fdir_info->hash_map = rte_zmalloc("ixgbe",
1497 sizeof(struct ixgbe_fdir_filter *) *
1498 IXGBE_MAX_FDIR_FILTER_NUM,
1500 if (!fdir_info->hash_map) {
1502 "Failed to allocate memory for fdir hash map!");
1505 fdir_info->mask_added = FALSE;
1510 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1512 struct ixgbe_l2_tn_info *l2_tn_info =
1513 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1514 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1515 struct rte_hash_parameters l2_tn_hash_params = {
1516 .name = l2_tn_hash_name,
1517 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1518 .key_len = sizeof(struct ixgbe_l2_tn_key),
1519 .hash_func = rte_hash_crc,
1520 .hash_func_init_val = 0,
1521 .socket_id = rte_socket_id(),
1524 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1525 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1526 "l2_tn_%s", eth_dev->device->name);
1527 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1528 if (!l2_tn_info->hash_handle) {
1529 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1532 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1533 sizeof(struct ixgbe_l2_tn_filter *) *
1534 IXGBE_MAX_L2_TN_FILTER_NUM,
1536 if (!l2_tn_info->hash_map) {
1538 "Failed to allocate memory for L2 TN hash map!");
1541 l2_tn_info->e_tag_en = FALSE;
1542 l2_tn_info->e_tag_fwd_en = FALSE;
1543 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1548 * Negotiate mailbox API version with the PF.
1549 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1550 * Then we try to negotiate starting with the most recent one.
1551 * If all negotiation attempts fail, then we will proceed with
1552 * the default one (ixgbe_mbox_api_10).
1555 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1559 /* start with highest supported, proceed down */
1560 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1567 i != RTE_DIM(sup_ver) &&
1568 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1574 generate_random_mac_addr(struct ether_addr *mac_addr)
1578 /* Set Organizationally Unique Identifier (OUI) prefix. */
1579 mac_addr->addr_bytes[0] = 0x00;
1580 mac_addr->addr_bytes[1] = 0x09;
1581 mac_addr->addr_bytes[2] = 0xC0;
1582 /* Force indication of locally assigned MAC address. */
1583 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1584 /* Generate the last 3 bytes of the MAC address with a random number. */
1585 random = rte_rand();
1586 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1590 * Virtual Function device init
1593 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1597 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1598 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1599 struct ixgbe_hw *hw =
1600 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1601 struct ixgbe_vfta *shadow_vfta =
1602 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1603 struct ixgbe_hwstrip *hwstrip =
1604 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1605 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1607 PMD_INIT_FUNC_TRACE();
1609 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1610 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1611 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1613 /* for secondary processes, we don't initialise any further as primary
1614 * has already done this work. Only check we don't need a different
1617 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1618 struct ixgbe_tx_queue *txq;
1619 /* TX queue function in primary, set by last queue initialized
1620 * Tx queue may not initialized by primary process
1622 if (eth_dev->data->tx_queues) {
1623 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1624 ixgbe_set_tx_function(eth_dev, txq);
1626 /* Use default TX function if we get here */
1627 PMD_INIT_LOG(NOTICE,
1628 "No TX queues configured yet. Using default TX function.");
1631 ixgbe_set_rx_function(eth_dev);
1636 rte_eth_copy_pci_info(eth_dev, pci_dev);
1638 hw->device_id = pci_dev->id.device_id;
1639 hw->vendor_id = pci_dev->id.vendor_id;
1640 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1642 /* initialize the vfta */
1643 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1645 /* initialize the hw strip bitmap*/
1646 memset(hwstrip, 0, sizeof(*hwstrip));
1648 /* Initialize the shared code (base driver) */
1649 diag = ixgbe_init_shared_code(hw);
1650 if (diag != IXGBE_SUCCESS) {
1651 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1655 /* init_mailbox_params */
1656 hw->mbx.ops.init_params(hw);
1658 /* Reset the hw statistics */
1659 ixgbevf_dev_stats_reset(eth_dev);
1661 /* Disable the interrupts for VF */
1662 ixgbevf_intr_disable(hw);
1664 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1665 diag = hw->mac.ops.reset_hw(hw);
1668 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1669 * the underlying PF driver has not assigned a MAC address to the VF.
1670 * In this case, assign a random MAC address.
1672 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1673 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1677 /* negotiate mailbox API version to use with the PF. */
1678 ixgbevf_negotiate_api(hw);
1680 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1681 ixgbevf_get_queues(hw, &tcs, &tc);
1683 /* Allocate memory for storing MAC addresses */
1684 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1685 hw->mac.num_rar_entries, 0);
1686 if (eth_dev->data->mac_addrs == NULL) {
1688 "Failed to allocate %u bytes needed to store "
1690 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1694 /* Generate a random MAC address, if none was assigned by PF. */
1695 if (is_zero_ether_addr(perm_addr)) {
1696 generate_random_mac_addr(perm_addr);
1697 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1699 rte_free(eth_dev->data->mac_addrs);
1700 eth_dev->data->mac_addrs = NULL;
1703 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1704 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1705 "%02x:%02x:%02x:%02x:%02x:%02x",
1706 perm_addr->addr_bytes[0],
1707 perm_addr->addr_bytes[1],
1708 perm_addr->addr_bytes[2],
1709 perm_addr->addr_bytes[3],
1710 perm_addr->addr_bytes[4],
1711 perm_addr->addr_bytes[5]);
1714 /* Copy the permanent MAC address */
1715 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1717 /* reset the hardware with the new settings */
1718 diag = hw->mac.ops.start_hw(hw);
1724 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1728 rte_intr_callback_register(intr_handle,
1729 ixgbevf_dev_interrupt_handler, eth_dev);
1730 rte_intr_enable(intr_handle);
1731 ixgbevf_intr_enable(hw);
1733 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1734 eth_dev->data->port_id, pci_dev->id.vendor_id,
1735 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1740 /* Virtual Function device uninit */
1743 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1745 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1746 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1747 struct ixgbe_hw *hw;
1749 PMD_INIT_FUNC_TRACE();
1751 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1754 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1756 if (hw->adapter_stopped == 0)
1757 ixgbevf_dev_close(eth_dev);
1759 eth_dev->dev_ops = NULL;
1760 eth_dev->rx_pkt_burst = NULL;
1761 eth_dev->tx_pkt_burst = NULL;
1763 /* Disable the interrupts for VF */
1764 ixgbevf_intr_disable(hw);
1766 rte_free(eth_dev->data->mac_addrs);
1767 eth_dev->data->mac_addrs = NULL;
1769 rte_intr_disable(intr_handle);
1770 rte_intr_callback_unregister(intr_handle,
1771 ixgbevf_dev_interrupt_handler, eth_dev);
1776 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1777 struct rte_pci_device *pci_dev)
1779 return rte_eth_dev_pci_generic_probe(pci_dev,
1780 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1785 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1788 static struct rte_pci_driver rte_ixgbe_pmd = {
1789 .id_table = pci_id_ixgbe_map,
1790 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1791 RTE_PCI_DRV_IOVA_AS_VA,
1792 .probe = eth_ixgbe_pci_probe,
1793 .remove = eth_ixgbe_pci_remove,
1796 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1797 struct rte_pci_device *pci_dev)
1799 return rte_eth_dev_pci_generic_probe(pci_dev,
1800 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1803 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1805 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1809 * virtual function driver struct
1811 static struct rte_pci_driver rte_ixgbevf_pmd = {
1812 .id_table = pci_id_ixgbevf_map,
1813 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1814 .probe = eth_ixgbevf_pci_probe,
1815 .remove = eth_ixgbevf_pci_remove,
1819 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1821 struct ixgbe_hw *hw =
1822 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823 struct ixgbe_vfta *shadow_vfta =
1824 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1829 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1830 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1831 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1836 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1838 /* update local VFTA copy */
1839 shadow_vfta->vfta[vid_idx] = vfta;
1845 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1848 ixgbe_vlan_hw_strip_enable(dev, queue);
1850 ixgbe_vlan_hw_strip_disable(dev, queue);
1854 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1855 enum rte_vlan_type vlan_type,
1858 struct ixgbe_hw *hw =
1859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1865 qinq &= IXGBE_DMATXCTL_GDV;
1867 switch (vlan_type) {
1868 case ETH_VLAN_TYPE_INNER:
1870 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1871 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1872 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1873 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1875 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1876 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1879 PMD_DRV_LOG(ERR, "Inner type is not supported"
1883 case ETH_VLAN_TYPE_OUTER:
1885 /* Only the high 16-bits is valid */
1886 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1887 IXGBE_EXVET_VET_EXT_SHIFT);
1889 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1890 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1891 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1892 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1893 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1894 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1895 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1901 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1909 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1911 struct ixgbe_hw *hw =
1912 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1915 PMD_INIT_FUNC_TRACE();
1917 /* Filter Table Disable */
1918 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1919 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1921 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1925 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1927 struct ixgbe_hw *hw =
1928 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929 struct ixgbe_vfta *shadow_vfta =
1930 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1934 PMD_INIT_FUNC_TRACE();
1936 /* Filter Table Enable */
1937 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1938 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1939 vlnctrl |= IXGBE_VLNCTRL_VFE;
1941 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1943 /* write whatever is in local vfta copy */
1944 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1945 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1949 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1951 struct ixgbe_hwstrip *hwstrip =
1952 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1953 struct ixgbe_rx_queue *rxq;
1955 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1959 IXGBE_SET_HWSTRIP(hwstrip, queue);
1961 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1963 if (queue >= dev->data->nb_rx_queues)
1966 rxq = dev->data->rx_queues[queue];
1969 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1971 rxq->vlan_flags = PKT_RX_VLAN;
1975 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1977 struct ixgbe_hw *hw =
1978 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1981 PMD_INIT_FUNC_TRACE();
1983 if (hw->mac.type == ixgbe_mac_82598EB) {
1984 /* No queue level support */
1985 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1989 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1990 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1991 ctrl &= ~IXGBE_RXDCTL_VME;
1992 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1994 /* record those setting for HW strip per queue */
1995 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1999 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2001 struct ixgbe_hw *hw =
2002 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2005 PMD_INIT_FUNC_TRACE();
2007 if (hw->mac.type == ixgbe_mac_82598EB) {
2008 /* No queue level supported */
2009 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2013 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2014 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2015 ctrl |= IXGBE_RXDCTL_VME;
2016 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018 /* record those setting for HW strip per queue */
2019 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2023 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2025 struct ixgbe_hw *hw =
2026 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029 struct ixgbe_rx_queue *rxq;
2031 PMD_INIT_FUNC_TRACE();
2033 if (hw->mac.type == ixgbe_mac_82598EB) {
2034 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2035 ctrl &= ~IXGBE_VLNCTRL_VME;
2036 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2038 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2040 rxq = dev->data->rx_queues[i];
2041 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2042 ctrl &= ~IXGBE_RXDCTL_VME;
2043 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2045 /* record those setting for HW strip per queue */
2046 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2052 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2054 struct ixgbe_hw *hw =
2055 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058 struct ixgbe_rx_queue *rxq;
2060 PMD_INIT_FUNC_TRACE();
2062 if (hw->mac.type == ixgbe_mac_82598EB) {
2063 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2064 ctrl |= IXGBE_VLNCTRL_VME;
2065 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2067 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2068 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2069 rxq = dev->data->rx_queues[i];
2070 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2071 ctrl |= IXGBE_RXDCTL_VME;
2072 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2074 /* record those setting for HW strip per queue */
2075 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2081 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2083 struct ixgbe_hw *hw =
2084 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087 PMD_INIT_FUNC_TRACE();
2089 /* DMATXCTRL: Geric Double VLAN Disable */
2090 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2091 ctrl &= ~IXGBE_DMATXCTL_GDV;
2092 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2094 /* CTRL_EXT: Global Double VLAN Disable */
2095 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2096 ctrl &= ~IXGBE_EXTENDED_VLAN;
2097 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2102 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2104 struct ixgbe_hw *hw =
2105 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2108 PMD_INIT_FUNC_TRACE();
2110 /* DMATXCTRL: Geric Double VLAN Enable */
2111 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2112 ctrl |= IXGBE_DMATXCTL_GDV;
2113 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2115 /* CTRL_EXT: Global Double VLAN Enable */
2116 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2117 ctrl |= IXGBE_EXTENDED_VLAN;
2118 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2120 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2121 if (hw->mac.type == ixgbe_mac_X550 ||
2122 hw->mac.type == ixgbe_mac_X550EM_x ||
2123 hw->mac.type == ixgbe_mac_X550EM_a) {
2124 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2125 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2126 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2130 * VET EXT field in the EXVET register = 0x8100 by default
2131 * So no need to change. Same to VT field of DMATXCTL register
2136 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2138 if (mask & ETH_VLAN_STRIP_MASK) {
2139 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2140 ixgbe_vlan_hw_strip_enable_all(dev);
2142 ixgbe_vlan_hw_strip_disable_all(dev);
2145 if (mask & ETH_VLAN_FILTER_MASK) {
2146 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2147 ixgbe_vlan_hw_filter_enable(dev);
2149 ixgbe_vlan_hw_filter_disable(dev);
2152 if (mask & ETH_VLAN_EXTEND_MASK) {
2153 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2154 ixgbe_vlan_hw_extend_enable(dev);
2156 ixgbe_vlan_hw_extend_disable(dev);
2161 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2163 struct ixgbe_hw *hw =
2164 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2166 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2168 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2169 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2173 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2175 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2180 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2183 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2189 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2190 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2196 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2198 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2199 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2201 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2203 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2204 /* check multi-queue mode */
2205 switch (dev_conf->rxmode.mq_mode) {
2206 case ETH_MQ_RX_VMDQ_DCB:
2207 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2209 case ETH_MQ_RX_VMDQ_DCB_RSS:
2210 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2211 PMD_INIT_LOG(ERR, "SRIOV active,"
2212 " unsupported mq_mode rx %d.",
2213 dev_conf->rxmode.mq_mode);
2216 case ETH_MQ_RX_VMDQ_RSS:
2217 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2218 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2219 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2220 PMD_INIT_LOG(ERR, "SRIOV is active,"
2221 " invalid queue number"
2222 " for VMDQ RSS, allowed"
2223 " value are 1, 2 or 4.");
2227 case ETH_MQ_RX_VMDQ_ONLY:
2228 case ETH_MQ_RX_NONE:
2229 /* if nothing mq mode configure, use default scheme */
2230 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2231 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2232 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2234 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2235 /* SRIOV only works in VMDq enable mode */
2236 PMD_INIT_LOG(ERR, "SRIOV is active,"
2237 " wrong mq_mode rx %d.",
2238 dev_conf->rxmode.mq_mode);
2242 switch (dev_conf->txmode.mq_mode) {
2243 case ETH_MQ_TX_VMDQ_DCB:
2244 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2245 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2247 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2248 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2252 /* check valid queue number */
2253 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2254 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2255 PMD_INIT_LOG(ERR, "SRIOV is active,"
2256 " nb_rx_q=%d nb_tx_q=%d queue number"
2257 " must be less than or equal to %d.",
2259 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2263 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2264 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2268 /* check configuration for vmdb+dcb mode */
2269 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2270 const struct rte_eth_vmdq_dcb_conf *conf;
2272 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2273 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2274 IXGBE_VMDQ_DCB_NB_QUEUES);
2277 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2278 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2279 conf->nb_queue_pools == ETH_32_POOLS)) {
2280 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2281 " nb_queue_pools must be %d or %d.",
2282 ETH_16_POOLS, ETH_32_POOLS);
2286 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2287 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2289 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2290 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2291 IXGBE_VMDQ_DCB_NB_QUEUES);
2294 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2295 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2296 conf->nb_queue_pools == ETH_32_POOLS)) {
2297 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2298 " nb_queue_pools != %d and"
2299 " nb_queue_pools != %d.",
2300 ETH_16_POOLS, ETH_32_POOLS);
2305 /* For DCB mode check our configuration before we go further */
2306 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2307 const struct rte_eth_dcb_rx_conf *conf;
2309 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2310 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2311 IXGBE_DCB_NB_QUEUES);
2314 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2315 if (!(conf->nb_tcs == ETH_4_TCS ||
2316 conf->nb_tcs == ETH_8_TCS)) {
2317 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2318 " and nb_tcs != %d.",
2319 ETH_4_TCS, ETH_8_TCS);
2324 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2325 const struct rte_eth_dcb_tx_conf *conf;
2327 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2328 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2329 IXGBE_DCB_NB_QUEUES);
2332 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2333 if (!(conf->nb_tcs == ETH_4_TCS ||
2334 conf->nb_tcs == ETH_8_TCS)) {
2335 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2336 " and nb_tcs != %d.",
2337 ETH_4_TCS, ETH_8_TCS);
2343 * When DCB/VT is off, maximum number of queues changes,
2344 * except for 82598EB, which remains constant.
2346 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2347 hw->mac.type != ixgbe_mac_82598EB) {
2348 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2350 "Neither VT nor DCB are enabled, "
2352 IXGBE_NONE_MODE_TX_NB_QUEUES);
2361 ixgbe_dev_configure(struct rte_eth_dev *dev)
2363 struct ixgbe_interrupt *intr =
2364 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2365 struct ixgbe_adapter *adapter =
2366 (struct ixgbe_adapter *)dev->data->dev_private;
2369 PMD_INIT_FUNC_TRACE();
2370 /* multipe queue mode checking */
2371 ret = ixgbe_check_mq_mode(dev);
2373 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2378 /* set flag to update link status after init */
2379 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2382 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2383 * allocation or vector Rx preconditions we will reset it.
2385 adapter->rx_bulk_alloc_allowed = true;
2386 adapter->rx_vec_allowed = true;
2392 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2394 struct ixgbe_hw *hw =
2395 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396 struct ixgbe_interrupt *intr =
2397 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2400 /* only set up it on X550EM_X */
2401 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2402 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2403 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2404 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2405 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2406 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2411 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2412 uint16_t tx_rate, uint64_t q_msk)
2414 struct ixgbe_hw *hw;
2415 struct ixgbe_vf_info *vfinfo;
2416 struct rte_eth_link link;
2417 uint8_t nb_q_per_pool;
2418 uint32_t queue_stride;
2419 uint32_t queue_idx, idx = 0, vf_idx;
2421 uint16_t total_rate = 0;
2422 struct rte_pci_device *pci_dev;
2424 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2425 rte_eth_link_get_nowait(dev->data->port_id, &link);
2427 if (vf >= pci_dev->max_vfs)
2430 if (tx_rate > link.link_speed)
2436 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2437 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2438 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2439 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2440 queue_idx = vf * queue_stride;
2441 queue_end = queue_idx + nb_q_per_pool - 1;
2442 if (queue_end >= hw->mac.max_tx_queues)
2446 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2449 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2451 total_rate += vfinfo[vf_idx].tx_rate[idx];
2457 /* Store tx_rate for this vf. */
2458 for (idx = 0; idx < nb_q_per_pool; idx++) {
2459 if (((uint64_t)0x1 << idx) & q_msk) {
2460 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2461 vfinfo[vf].tx_rate[idx] = tx_rate;
2462 total_rate += tx_rate;
2466 if (total_rate > dev->data->dev_link.link_speed) {
2467 /* Reset stored TX rate of the VF if it causes exceed
2470 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2474 /* Set RTTBCNRC of each queue/pool for vf X */
2475 for (; queue_idx <= queue_end; queue_idx++) {
2477 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2485 * Configure device link speed and setup link.
2486 * It returns 0 on success.
2489 ixgbe_dev_start(struct rte_eth_dev *dev)
2491 struct ixgbe_hw *hw =
2492 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493 struct ixgbe_vf_info *vfinfo =
2494 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2495 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2496 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2497 uint32_t intr_vector = 0;
2498 int err, link_up = 0, negotiate = 0;
2503 uint32_t *link_speeds;
2504 struct ixgbe_tm_conf *tm_conf =
2505 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2507 PMD_INIT_FUNC_TRACE();
2509 /* IXGBE devices don't support:
2510 * - half duplex (checked afterwards for valid speeds)
2511 * - fixed speed: TODO implement
2513 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2515 "Invalid link_speeds for port %u, fix speed not supported",
2516 dev->data->port_id);
2520 /* disable uio/vfio intr/eventfd mapping */
2521 rte_intr_disable(intr_handle);
2524 hw->adapter_stopped = 0;
2525 ixgbe_stop_adapter(hw);
2527 /* reinitialize adapter
2528 * this calls reset and start
2530 status = ixgbe_pf_reset_hw(hw);
2533 hw->mac.ops.start_hw(hw);
2534 hw->mac.get_link_status = true;
2536 /* configure PF module if SRIOV enabled */
2537 ixgbe_pf_host_configure(dev);
2539 ixgbe_dev_phy_intr_setup(dev);
2541 /* check and configure queue intr-vector mapping */
2542 if ((rte_intr_cap_multiple(intr_handle) ||
2543 !RTE_ETH_DEV_SRIOV(dev).active) &&
2544 dev->data->dev_conf.intr_conf.rxq != 0) {
2545 intr_vector = dev->data->nb_rx_queues;
2546 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2547 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2548 IXGBE_MAX_INTR_QUEUE_NUM);
2551 if (rte_intr_efd_enable(intr_handle, intr_vector))
2555 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2556 intr_handle->intr_vec =
2557 rte_zmalloc("intr_vec",
2558 dev->data->nb_rx_queues * sizeof(int), 0);
2559 if (intr_handle->intr_vec == NULL) {
2560 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2561 " intr_vec", dev->data->nb_rx_queues);
2566 /* confiugre msix for sleep until rx interrupt */
2567 ixgbe_configure_msix(dev);
2569 /* initialize transmission unit */
2570 ixgbe_dev_tx_init(dev);
2572 /* This can fail when allocating mbufs for descriptor rings */
2573 err = ixgbe_dev_rx_init(dev);
2575 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2579 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2580 ETH_VLAN_EXTEND_MASK;
2581 ixgbe_vlan_offload_set(dev, mask);
2583 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2584 /* Enable vlan filtering for VMDq */
2585 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2588 /* Configure DCB hw */
2589 ixgbe_configure_dcb(dev);
2591 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2592 err = ixgbe_fdir_configure(dev);
2597 /* Restore vf rate limit */
2598 if (vfinfo != NULL) {
2599 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2600 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2601 if (vfinfo[vf].tx_rate[idx] != 0)
2602 ixgbe_set_vf_rate_limit(
2604 vfinfo[vf].tx_rate[idx],
2608 ixgbe_restore_statistics_mapping(dev);
2610 err = ixgbe_dev_rxtx_start(dev);
2612 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2616 /* Skip link setup if loopback mode is enabled for 82599. */
2617 if (hw->mac.type == ixgbe_mac_82599EB &&
2618 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2619 goto skip_link_setup;
2621 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2622 err = hw->mac.ops.setup_sfp(hw);
2627 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2628 /* Turn on the copper */
2629 ixgbe_set_phy_power(hw, true);
2631 /* Turn on the laser */
2632 ixgbe_enable_tx_laser(hw);
2635 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2638 dev->data->dev_link.link_status = link_up;
2640 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2644 link_speeds = &dev->data->dev_conf.link_speeds;
2645 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2646 ETH_LINK_SPEED_10G)) {
2647 PMD_INIT_LOG(ERR, "Invalid link setting");
2652 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2653 switch (hw->mac.type) {
2654 case ixgbe_mac_82598EB:
2655 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2657 case ixgbe_mac_82599EB:
2658 case ixgbe_mac_X540:
2659 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2661 case ixgbe_mac_X550:
2662 case ixgbe_mac_X550EM_x:
2663 case ixgbe_mac_X550EM_a:
2664 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2667 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2670 if (*link_speeds & ETH_LINK_SPEED_10G)
2671 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2672 if (*link_speeds & ETH_LINK_SPEED_1G)
2673 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2674 if (*link_speeds & ETH_LINK_SPEED_100M)
2675 speed |= IXGBE_LINK_SPEED_100_FULL;
2678 err = ixgbe_setup_link(hw, speed, link_up);
2684 if (rte_intr_allow_others(intr_handle)) {
2685 /* check if lsc interrupt is enabled */
2686 if (dev->data->dev_conf.intr_conf.lsc != 0)
2687 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2689 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2690 ixgbe_dev_macsec_interrupt_setup(dev);
2692 rte_intr_callback_unregister(intr_handle,
2693 ixgbe_dev_interrupt_handler, dev);
2694 if (dev->data->dev_conf.intr_conf.lsc != 0)
2695 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2696 " no intr multiplex");
2699 /* check if rxq interrupt is enabled */
2700 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2701 rte_intr_dp_is_en(intr_handle))
2702 ixgbe_dev_rxq_interrupt_setup(dev);
2704 /* enable uio/vfio intr/eventfd mapping */
2705 rte_intr_enable(intr_handle);
2707 /* resume enabled intr since hw reset */
2708 ixgbe_enable_intr(dev);
2709 ixgbe_l2_tunnel_conf(dev);
2710 ixgbe_filter_restore(dev);
2712 if (tm_conf->root && !tm_conf->committed)
2713 PMD_DRV_LOG(WARNING,
2714 "please call hierarchy_commit() "
2715 "before starting the port");
2720 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2721 ixgbe_dev_clear_queues(dev);
2726 * Stop device: disable rx and tx functions to allow for reconfiguring.
2729 ixgbe_dev_stop(struct rte_eth_dev *dev)
2731 struct rte_eth_link link;
2732 struct ixgbe_hw *hw =
2733 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734 struct ixgbe_vf_info *vfinfo =
2735 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2736 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2737 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2739 struct ixgbe_tm_conf *tm_conf =
2740 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2742 PMD_INIT_FUNC_TRACE();
2744 /* disable interrupts */
2745 ixgbe_disable_intr(hw);
2748 ixgbe_pf_reset_hw(hw);
2749 hw->adapter_stopped = 0;
2752 ixgbe_stop_adapter(hw);
2754 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2755 vfinfo[vf].clear_to_send = false;
2757 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2758 /* Turn off the copper */
2759 ixgbe_set_phy_power(hw, false);
2761 /* Turn off the laser */
2762 ixgbe_disable_tx_laser(hw);
2765 ixgbe_dev_clear_queues(dev);
2767 /* Clear stored conf */
2768 dev->data->scattered_rx = 0;
2771 /* Clear recorded link status */
2772 memset(&link, 0, sizeof(link));
2773 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2775 if (!rte_intr_allow_others(intr_handle))
2776 /* resume to the default handler */
2777 rte_intr_callback_register(intr_handle,
2778 ixgbe_dev_interrupt_handler,
2781 /* Clean datapath event and queue/vec mapping */
2782 rte_intr_efd_disable(intr_handle);
2783 if (intr_handle->intr_vec != NULL) {
2784 rte_free(intr_handle->intr_vec);
2785 intr_handle->intr_vec = NULL;
2788 /* reset hierarchy commit */
2789 tm_conf->committed = false;
2793 * Set device link up: enable tx.
2796 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2798 struct ixgbe_hw *hw =
2799 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2800 if (hw->mac.type == ixgbe_mac_82599EB) {
2801 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2802 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2803 /* Not suported in bypass mode */
2804 PMD_INIT_LOG(ERR, "Set link up is not supported "
2805 "by device id 0x%x", hw->device_id);
2811 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2812 /* Turn on the copper */
2813 ixgbe_set_phy_power(hw, true);
2815 /* Turn on the laser */
2816 ixgbe_enable_tx_laser(hw);
2823 * Set device link down: disable tx.
2826 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2828 struct ixgbe_hw *hw =
2829 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2830 if (hw->mac.type == ixgbe_mac_82599EB) {
2831 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2832 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2833 /* Not suported in bypass mode */
2834 PMD_INIT_LOG(ERR, "Set link down is not supported "
2835 "by device id 0x%x", hw->device_id);
2841 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2842 /* Turn off the copper */
2843 ixgbe_set_phy_power(hw, false);
2845 /* Turn off the laser */
2846 ixgbe_disable_tx_laser(hw);
2853 * Reset and stop device.
2856 ixgbe_dev_close(struct rte_eth_dev *dev)
2858 struct ixgbe_hw *hw =
2859 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861 PMD_INIT_FUNC_TRACE();
2863 ixgbe_pf_reset_hw(hw);
2865 ixgbe_dev_stop(dev);
2866 hw->adapter_stopped = 1;
2868 ixgbe_dev_free_queues(dev);
2870 ixgbe_disable_pcie_master(hw);
2872 /* reprogram the RAR[0] in case user changed it. */
2873 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2880 ixgbe_dev_reset(struct rte_eth_dev *dev)
2884 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2885 * its VF to make them align with it. The detailed notification
2886 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2887 * To avoid unexpected behavior in VF, currently reset of PF with
2888 * SR-IOV activation is not supported. It might be supported later.
2890 if (dev->data->sriov.active)
2893 ret = eth_ixgbe_dev_uninit(dev);
2897 ret = eth_ixgbe_dev_init(dev);
2903 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2904 struct ixgbe_hw_stats *hw_stats,
2905 struct ixgbe_macsec_stats *macsec_stats,
2906 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2907 uint64_t *total_qprc, uint64_t *total_qprdc)
2909 uint32_t bprc, lxon, lxoff, total;
2910 uint32_t delta_gprc = 0;
2912 /* Workaround for RX byte count not including CRC bytes when CRC
2913 * strip is enabled. CRC bytes are removed from counters when crc_strip
2916 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2917 IXGBE_HLREG0_RXCRCSTRP);
2919 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2920 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2921 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2922 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2924 for (i = 0; i < 8; i++) {
2925 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2927 /* global total per queue */
2928 hw_stats->mpc[i] += mp;
2929 /* Running comprehensive total for stats display */
2930 *total_missed_rx += hw_stats->mpc[i];
2931 if (hw->mac.type == ixgbe_mac_82598EB) {
2932 hw_stats->rnbc[i] +=
2933 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2934 hw_stats->pxonrxc[i] +=
2935 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2936 hw_stats->pxoffrxc[i] +=
2937 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2939 hw_stats->pxonrxc[i] +=
2940 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2941 hw_stats->pxoffrxc[i] +=
2942 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2943 hw_stats->pxon2offc[i] +=
2944 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2946 hw_stats->pxontxc[i] +=
2947 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2948 hw_stats->pxofftxc[i] +=
2949 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2951 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2952 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2953 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2954 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2956 delta_gprc += delta_qprc;
2958 hw_stats->qprc[i] += delta_qprc;
2959 hw_stats->qptc[i] += delta_qptc;
2961 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2962 hw_stats->qbrc[i] +=
2963 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2965 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2967 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2968 hw_stats->qbtc[i] +=
2969 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2971 hw_stats->qprdc[i] += delta_qprdc;
2972 *total_qprdc += hw_stats->qprdc[i];
2974 *total_qprc += hw_stats->qprc[i];
2975 *total_qbrc += hw_stats->qbrc[i];
2977 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2978 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2979 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2982 * An errata states that gprc actually counts good + missed packets:
2983 * Workaround to set gprc to summated queue packet receives
2985 hw_stats->gprc = *total_qprc;
2987 if (hw->mac.type != ixgbe_mac_82598EB) {
2988 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2989 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2990 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2991 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2992 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2993 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2994 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2995 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2997 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2998 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2999 /* 82598 only has a counter in the high register */
3000 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3001 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3002 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3004 uint64_t old_tpr = hw_stats->tpr;
3006 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3007 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3010 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3012 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3013 hw_stats->gptc += delta_gptc;
3014 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3015 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3018 * Workaround: mprc hardware is incorrectly counting
3019 * broadcasts, so for now we subtract those.
3021 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3022 hw_stats->bprc += bprc;
3023 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3024 if (hw->mac.type == ixgbe_mac_82598EB)
3025 hw_stats->mprc -= bprc;
3027 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3028 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3029 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3030 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3031 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3032 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3034 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3035 hw_stats->lxontxc += lxon;
3036 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3037 hw_stats->lxofftxc += lxoff;
3038 total = lxon + lxoff;
3040 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3041 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3042 hw_stats->gptc -= total;
3043 hw_stats->mptc -= total;
3044 hw_stats->ptc64 -= total;
3045 hw_stats->gotc -= total * ETHER_MIN_LEN;
3047 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3048 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3049 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3050 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3051 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3052 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3053 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3054 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3055 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3056 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3057 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3058 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3059 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3060 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3061 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3062 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3063 /* Only read FCOE on 82599 */
3064 if (hw->mac.type != ixgbe_mac_82598EB) {
3065 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3066 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3067 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3068 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3069 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3072 /* Flow Director Stats registers */
3073 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3074 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3076 /* MACsec Stats registers */
3077 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3078 macsec_stats->out_pkts_encrypted +=
3079 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3080 macsec_stats->out_pkts_protected +=
3081 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3082 macsec_stats->out_octets_encrypted +=
3083 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3084 macsec_stats->out_octets_protected +=
3085 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3086 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3087 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3088 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3089 macsec_stats->in_pkts_unknownsci +=
3090 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3091 macsec_stats->in_octets_decrypted +=
3092 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3093 macsec_stats->in_octets_validated +=
3094 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3095 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3096 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3097 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3098 for (i = 0; i < 2; i++) {
3099 macsec_stats->in_pkts_ok +=
3100 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3101 macsec_stats->in_pkts_invalid +=
3102 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3103 macsec_stats->in_pkts_notvalid +=
3104 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3106 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3107 macsec_stats->in_pkts_notusingsa +=
3108 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3112 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3115 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3117 struct ixgbe_hw *hw =
3118 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3119 struct ixgbe_hw_stats *hw_stats =
3120 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3121 struct ixgbe_macsec_stats *macsec_stats =
3122 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3123 dev->data->dev_private);
3124 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3127 total_missed_rx = 0;
3132 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3133 &total_qbrc, &total_qprc, &total_qprdc);
3138 /* Fill out the rte_eth_stats statistics structure */
3139 stats->ipackets = total_qprc;
3140 stats->ibytes = total_qbrc;
3141 stats->opackets = hw_stats->gptc;
3142 stats->obytes = hw_stats->gotc;
3144 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3145 stats->q_ipackets[i] = hw_stats->qprc[i];
3146 stats->q_opackets[i] = hw_stats->qptc[i];
3147 stats->q_ibytes[i] = hw_stats->qbrc[i];
3148 stats->q_obytes[i] = hw_stats->qbtc[i];
3149 stats->q_errors[i] = hw_stats->qprdc[i];
3153 stats->imissed = total_missed_rx;
3154 stats->ierrors = hw_stats->crcerrs +
3171 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3173 struct ixgbe_hw_stats *stats =
3174 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3176 /* HW registers are cleared on read */
3177 ixgbe_dev_stats_get(dev, NULL);
3179 /* Reset software totals */
3180 memset(stats, 0, sizeof(*stats));
3183 /* This function calculates the number of xstats based on the current config */
3185 ixgbe_xstats_calc_num(void) {
3186 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3187 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3188 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3191 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3192 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3194 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3195 unsigned stat, i, count;
3197 if (xstats_names != NULL) {
3200 /* Note: limit >= cnt_stats checked upstream
3201 * in rte_eth_xstats_names()
3204 /* Extended stats from ixgbe_hw_stats */
3205 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3206 snprintf(xstats_names[count].name,
3207 sizeof(xstats_names[count].name),
3209 rte_ixgbe_stats_strings[i].name);
3214 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3215 snprintf(xstats_names[count].name,
3216 sizeof(xstats_names[count].name),
3218 rte_ixgbe_macsec_strings[i].name);
3222 /* RX Priority Stats */
3223 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3224 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3225 snprintf(xstats_names[count].name,
3226 sizeof(xstats_names[count].name),
3227 "rx_priority%u_%s", i,
3228 rte_ixgbe_rxq_strings[stat].name);
3233 /* TX Priority Stats */
3234 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3235 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3236 snprintf(xstats_names[count].name,
3237 sizeof(xstats_names[count].name),
3238 "tx_priority%u_%s", i,
3239 rte_ixgbe_txq_strings[stat].name);
3247 static int ixgbe_dev_xstats_get_names_by_id(
3248 struct rte_eth_dev *dev,
3249 struct rte_eth_xstat_name *xstats_names,
3250 const uint64_t *ids,
3254 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3255 unsigned int stat, i, count;
3257 if (xstats_names != NULL) {
3260 /* Note: limit >= cnt_stats checked upstream
3261 * in rte_eth_xstats_names()
3264 /* Extended stats from ixgbe_hw_stats */
3265 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3266 snprintf(xstats_names[count].name,
3267 sizeof(xstats_names[count].name),
3269 rte_ixgbe_stats_strings[i].name);
3274 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3275 snprintf(xstats_names[count].name,
3276 sizeof(xstats_names[count].name),
3278 rte_ixgbe_macsec_strings[i].name);
3282 /* RX Priority Stats */
3283 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3284 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3285 snprintf(xstats_names[count].name,
3286 sizeof(xstats_names[count].name),
3287 "rx_priority%u_%s", i,
3288 rte_ixgbe_rxq_strings[stat].name);
3293 /* TX Priority Stats */
3294 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3295 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3296 snprintf(xstats_names[count].name,
3297 sizeof(xstats_names[count].name),
3298 "tx_priority%u_%s", i,
3299 rte_ixgbe_txq_strings[stat].name);
3308 uint16_t size = ixgbe_xstats_calc_num();
3309 struct rte_eth_xstat_name xstats_names_copy[size];
3311 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3314 for (i = 0; i < limit; i++) {
3315 if (ids[i] >= size) {
3316 PMD_INIT_LOG(ERR, "id value isn't valid");
3319 strcpy(xstats_names[i].name,
3320 xstats_names_copy[ids[i]].name);
3325 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3326 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3330 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3333 if (xstats_names != NULL)
3334 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3335 snprintf(xstats_names[i].name,
3336 sizeof(xstats_names[i].name),
3337 "%s", rte_ixgbevf_stats_strings[i].name);
3338 return IXGBEVF_NB_XSTATS;
3342 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3345 struct ixgbe_hw *hw =
3346 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3347 struct ixgbe_hw_stats *hw_stats =
3348 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3349 struct ixgbe_macsec_stats *macsec_stats =
3350 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3351 dev->data->dev_private);
3352 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3353 unsigned i, stat, count = 0;
3355 count = ixgbe_xstats_calc_num();
3360 total_missed_rx = 0;
3365 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3366 &total_qbrc, &total_qprc, &total_qprdc);
3368 /* If this is a reset xstats is NULL, and we have cleared the
3369 * registers by reading them.
3374 /* Extended stats from ixgbe_hw_stats */
3376 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3377 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3378 rte_ixgbe_stats_strings[i].offset);
3379 xstats[count].id = count;
3384 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3385 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3386 rte_ixgbe_macsec_strings[i].offset);
3387 xstats[count].id = count;
3391 /* RX Priority Stats */
3392 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3393 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3394 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3395 rte_ixgbe_rxq_strings[stat].offset +
3396 (sizeof(uint64_t) * i));
3397 xstats[count].id = count;
3402 /* TX Priority Stats */
3403 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3404 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3405 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3406 rte_ixgbe_txq_strings[stat].offset +
3407 (sizeof(uint64_t) * i));
3408 xstats[count].id = count;
3416 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3417 uint64_t *values, unsigned int n)
3420 struct ixgbe_hw *hw =
3421 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422 struct ixgbe_hw_stats *hw_stats =
3423 IXGBE_DEV_PRIVATE_TO_STATS(
3424 dev->data->dev_private);
3425 struct ixgbe_macsec_stats *macsec_stats =
3426 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3427 dev->data->dev_private);
3428 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3429 unsigned int i, stat, count = 0;
3431 count = ixgbe_xstats_calc_num();
3433 if (!ids && n < count)
3436 total_missed_rx = 0;
3441 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3442 &total_missed_rx, &total_qbrc, &total_qprc,
3445 /* If this is a reset xstats is NULL, and we have cleared the
3446 * registers by reading them.
3448 if (!ids && !values)
3451 /* Extended stats from ixgbe_hw_stats */
3453 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3454 values[count] = *(uint64_t *)(((char *)hw_stats) +
3455 rte_ixgbe_stats_strings[i].offset);
3460 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3461 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3462 rte_ixgbe_macsec_strings[i].offset);
3466 /* RX Priority Stats */
3467 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3468 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3470 *(uint64_t *)(((char *)hw_stats) +
3471 rte_ixgbe_rxq_strings[stat].offset +
3472 (sizeof(uint64_t) * i));
3477 /* TX Priority Stats */
3478 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3479 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3481 *(uint64_t *)(((char *)hw_stats) +
3482 rte_ixgbe_txq_strings[stat].offset +
3483 (sizeof(uint64_t) * i));
3491 uint16_t size = ixgbe_xstats_calc_num();
3492 uint64_t values_copy[size];
3494 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3496 for (i = 0; i < n; i++) {
3497 if (ids[i] >= size) {
3498 PMD_INIT_LOG(ERR, "id value isn't valid");
3501 values[i] = values_copy[ids[i]];
3507 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3509 struct ixgbe_hw_stats *stats =
3510 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3511 struct ixgbe_macsec_stats *macsec_stats =
3512 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3513 dev->data->dev_private);
3515 unsigned count = ixgbe_xstats_calc_num();
3517 /* HW registers are cleared on read */
3518 ixgbe_dev_xstats_get(dev, NULL, count);
3520 /* Reset software totals */
3521 memset(stats, 0, sizeof(*stats));
3522 memset(macsec_stats, 0, sizeof(*macsec_stats));
3526 ixgbevf_update_stats(struct rte_eth_dev *dev)
3528 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3529 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3530 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3532 /* Good Rx packet, include VF loopback */
3533 UPDATE_VF_STAT(IXGBE_VFGPRC,
3534 hw_stats->last_vfgprc, hw_stats->vfgprc);
3536 /* Good Rx octets, include VF loopback */
3537 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3538 hw_stats->last_vfgorc, hw_stats->vfgorc);
3540 /* Good Tx packet, include VF loopback */
3541 UPDATE_VF_STAT(IXGBE_VFGPTC,
3542 hw_stats->last_vfgptc, hw_stats->vfgptc);
3544 /* Good Tx octets, include VF loopback */
3545 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3546 hw_stats->last_vfgotc, hw_stats->vfgotc);
3548 /* Rx Multicst Packet */
3549 UPDATE_VF_STAT(IXGBE_VFMPRC,
3550 hw_stats->last_vfmprc, hw_stats->vfmprc);
3554 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3557 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3558 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3561 if (n < IXGBEVF_NB_XSTATS)
3562 return IXGBEVF_NB_XSTATS;
3564 ixgbevf_update_stats(dev);
3569 /* Extended stats */
3570 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3572 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3573 rte_ixgbevf_stats_strings[i].offset);
3576 return IXGBEVF_NB_XSTATS;
3580 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3582 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3583 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3585 ixgbevf_update_stats(dev);
3590 stats->ipackets = hw_stats->vfgprc;
3591 stats->ibytes = hw_stats->vfgorc;
3592 stats->opackets = hw_stats->vfgptc;
3593 stats->obytes = hw_stats->vfgotc;
3598 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3600 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3601 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3603 /* Sync HW register to the last stats */
3604 ixgbevf_dev_stats_get(dev, NULL);
3606 /* reset HW current stats*/
3607 hw_stats->vfgprc = 0;
3608 hw_stats->vfgorc = 0;
3609 hw_stats->vfgptc = 0;
3610 hw_stats->vfgotc = 0;
3614 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3616 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617 u16 eeprom_verh, eeprom_verl;
3621 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3622 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3624 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3625 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3627 ret += 1; /* add the size of '\0' */
3628 if (fw_size < (u32)ret)
3635 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3637 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3638 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3639 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3641 dev_info->pci_dev = pci_dev;
3642 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3643 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3644 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3646 * When DCB/VT is off, maximum number of queues changes,
3647 * except for 82598EB, which remains constant.
3649 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3650 hw->mac.type != ixgbe_mac_82598EB)
3651 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3653 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3654 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3655 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3656 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3657 dev_info->max_vfs = pci_dev->max_vfs;
3658 if (hw->mac.type == ixgbe_mac_82598EB)
3659 dev_info->max_vmdq_pools = ETH_16_POOLS;
3661 dev_info->max_vmdq_pools = ETH_64_POOLS;
3662 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3663 dev_info->rx_offload_capa =
3664 DEV_RX_OFFLOAD_VLAN_STRIP |
3665 DEV_RX_OFFLOAD_IPV4_CKSUM |
3666 DEV_RX_OFFLOAD_UDP_CKSUM |
3667 DEV_RX_OFFLOAD_TCP_CKSUM;
3670 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3673 if ((hw->mac.type == ixgbe_mac_82599EB ||
3674 hw->mac.type == ixgbe_mac_X540) &&
3675 !RTE_ETH_DEV_SRIOV(dev).active)
3676 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3678 if (hw->mac.type == ixgbe_mac_82599EB ||
3679 hw->mac.type == ixgbe_mac_X540)
3680 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3682 if (hw->mac.type == ixgbe_mac_X550 ||
3683 hw->mac.type == ixgbe_mac_X550EM_x ||
3684 hw->mac.type == ixgbe_mac_X550EM_a)
3685 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3687 dev_info->tx_offload_capa =
3688 DEV_TX_OFFLOAD_VLAN_INSERT |
3689 DEV_TX_OFFLOAD_IPV4_CKSUM |
3690 DEV_TX_OFFLOAD_UDP_CKSUM |
3691 DEV_TX_OFFLOAD_TCP_CKSUM |
3692 DEV_TX_OFFLOAD_SCTP_CKSUM |
3693 DEV_TX_OFFLOAD_TCP_TSO;
3695 if (hw->mac.type == ixgbe_mac_82599EB ||
3696 hw->mac.type == ixgbe_mac_X540)
3697 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3699 if (hw->mac.type == ixgbe_mac_X550 ||
3700 hw->mac.type == ixgbe_mac_X550EM_x ||
3701 hw->mac.type == ixgbe_mac_X550EM_a)
3702 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3704 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3705 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3707 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3709 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3710 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3711 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3713 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3717 dev_info->default_txconf = (struct rte_eth_txconf) {
3719 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3720 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3721 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3723 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3724 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3725 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3726 ETH_TXQ_FLAGS_NOOFFLOADS,
3729 dev_info->rx_desc_lim = rx_desc_lim;
3730 dev_info->tx_desc_lim = tx_desc_lim;
3732 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3733 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3734 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3736 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3737 if (hw->mac.type == ixgbe_mac_X540 ||
3738 hw->mac.type == ixgbe_mac_X540_vf ||
3739 hw->mac.type == ixgbe_mac_X550 ||
3740 hw->mac.type == ixgbe_mac_X550_vf) {
3741 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3743 if (hw->mac.type == ixgbe_mac_X550) {
3744 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3745 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3749 static const uint32_t *
3750 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3752 static const uint32_t ptypes[] = {
3753 /* For non-vec functions,
3754 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3755 * for vec functions,
3756 * refers to _recv_raw_pkts_vec().
3760 RTE_PTYPE_L3_IPV4_EXT,
3762 RTE_PTYPE_L3_IPV6_EXT,
3766 RTE_PTYPE_TUNNEL_IP,
3767 RTE_PTYPE_INNER_L3_IPV6,
3768 RTE_PTYPE_INNER_L3_IPV6_EXT,
3769 RTE_PTYPE_INNER_L4_TCP,
3770 RTE_PTYPE_INNER_L4_UDP,
3774 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3775 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3776 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3777 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3780 #if defined(RTE_ARCH_X86)
3781 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3782 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3789 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3790 struct rte_eth_dev_info *dev_info)
3792 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3793 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795 dev_info->pci_dev = pci_dev;
3796 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3797 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3798 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3799 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3800 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3801 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3802 dev_info->max_vfs = pci_dev->max_vfs;
3803 if (hw->mac.type == ixgbe_mac_82598EB)
3804 dev_info->max_vmdq_pools = ETH_16_POOLS;
3806 dev_info->max_vmdq_pools = ETH_64_POOLS;
3807 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3808 DEV_RX_OFFLOAD_IPV4_CKSUM |
3809 DEV_RX_OFFLOAD_UDP_CKSUM |
3810 DEV_RX_OFFLOAD_TCP_CKSUM;
3811 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3812 DEV_TX_OFFLOAD_IPV4_CKSUM |
3813 DEV_TX_OFFLOAD_UDP_CKSUM |
3814 DEV_TX_OFFLOAD_TCP_CKSUM |
3815 DEV_TX_OFFLOAD_SCTP_CKSUM |
3816 DEV_TX_OFFLOAD_TCP_TSO;
3818 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3820 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3821 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3822 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3824 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3828 dev_info->default_txconf = (struct rte_eth_txconf) {
3830 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3831 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3832 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3834 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3835 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3836 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3837 ETH_TXQ_FLAGS_NOOFFLOADS,
3840 dev_info->rx_desc_lim = rx_desc_lim;
3841 dev_info->tx_desc_lim = tx_desc_lim;
3845 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3846 int *link_up, int wait_to_complete)
3849 * for a quick link status checking, wait_to_compelet == 0,
3850 * skip PF link status checking
3852 bool no_pflink_check = wait_to_complete == 0;
3853 struct ixgbe_mbx_info *mbx = &hw->mbx;
3854 struct ixgbe_mac_info *mac = &hw->mac;
3855 uint32_t links_reg, in_msg;
3858 /* If we were hit with a reset drop the link */
3859 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3860 mac->get_link_status = true;
3862 if (!mac->get_link_status)
3865 /* if link status is down no point in checking to see if pf is up */
3866 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3867 if (!(links_reg & IXGBE_LINKS_UP))
3870 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3871 * before the link status is correct
3873 if (mac->type == ixgbe_mac_82599_vf) {
3876 for (i = 0; i < 5; i++) {
3878 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3880 if (!(links_reg & IXGBE_LINKS_UP))
3885 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3886 case IXGBE_LINKS_SPEED_10G_82599:
3887 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3888 if (hw->mac.type >= ixgbe_mac_X550) {
3889 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3890 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3893 case IXGBE_LINKS_SPEED_1G_82599:
3894 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3896 case IXGBE_LINKS_SPEED_100_82599:
3897 *speed = IXGBE_LINK_SPEED_100_FULL;
3898 if (hw->mac.type == ixgbe_mac_X550) {
3899 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3900 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3903 case IXGBE_LINKS_SPEED_10_X550EM_A:
3904 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3905 /* Since Reserved in older MAC's */
3906 if (hw->mac.type >= ixgbe_mac_X550)
3907 *speed = IXGBE_LINK_SPEED_10_FULL;
3910 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3913 if (no_pflink_check) {
3914 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3915 mac->get_link_status = true;
3917 mac->get_link_status = false;
3921 /* if the read failed it could just be a mailbox collision, best wait
3922 * until we are called again and don't report an error
3924 if (mbx->ops.read(hw, &in_msg, 1, 0))
3927 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3928 /* msg is not CTS and is NACK we must have lost CTS status */
3929 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3934 /* the pf is talking, if we timed out in the past we reinit */
3935 if (!mbx->timeout) {
3940 /* if we passed all the tests above then the link is up and we no
3941 * longer need to check for link
3943 mac->get_link_status = false;
3946 *link_up = !mac->get_link_status;
3950 /* return 0 means link status changed, -1 means not changed */
3952 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3953 int wait_to_complete, int vf)
3955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3956 struct rte_eth_link link, old;
3957 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3958 struct ixgbe_interrupt *intr =
3959 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3964 bool autoneg = false;
3966 link.link_status = ETH_LINK_DOWN;
3967 link.link_speed = 0;
3968 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3969 link.link_autoneg = ETH_LINK_AUTONEG;
3970 memset(&old, 0, sizeof(old));
3971 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3973 hw->mac.get_link_status = true;
3975 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3976 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3977 speed = hw->phy.autoneg_advertised;
3979 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3980 ixgbe_setup_link(hw, speed, true);
3983 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3984 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3988 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3990 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3993 link.link_speed = ETH_SPEED_NUM_100M;
3994 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3995 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3996 if (link.link_status == old.link_status)
4002 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4003 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4004 if (link.link_status == old.link_status)
4008 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4009 link.link_status = ETH_LINK_UP;
4010 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4012 switch (link_speed) {
4014 case IXGBE_LINK_SPEED_UNKNOWN:
4015 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4016 link.link_speed = ETH_SPEED_NUM_100M;
4019 case IXGBE_LINK_SPEED_100_FULL:
4020 link.link_speed = ETH_SPEED_NUM_100M;
4023 case IXGBE_LINK_SPEED_1GB_FULL:
4024 link.link_speed = ETH_SPEED_NUM_1G;
4027 case IXGBE_LINK_SPEED_2_5GB_FULL:
4028 link.link_speed = ETH_SPEED_NUM_2_5G;
4031 case IXGBE_LINK_SPEED_5GB_FULL:
4032 link.link_speed = ETH_SPEED_NUM_5G;
4035 case IXGBE_LINK_SPEED_10GB_FULL:
4036 link.link_speed = ETH_SPEED_NUM_10G;
4039 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4041 if (link.link_status == old.link_status)
4048 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4050 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4054 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4056 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4060 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4062 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4065 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4066 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4067 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4071 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4076 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4077 fctrl &= (~IXGBE_FCTRL_UPE);
4078 if (dev->data->all_multicast == 1)
4079 fctrl |= IXGBE_FCTRL_MPE;
4081 fctrl &= (~IXGBE_FCTRL_MPE);
4082 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4086 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4088 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4091 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4092 fctrl |= IXGBE_FCTRL_MPE;
4093 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4097 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4099 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102 if (dev->data->promiscuous == 1)
4103 return; /* must remain in all_multicast mode */
4105 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4106 fctrl &= (~IXGBE_FCTRL_MPE);
4107 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4111 * It clears the interrupt causes and enables the interrupt.
4112 * It will be called once only during nic initialized.
4115 * Pointer to struct rte_eth_dev.
4117 * Enable or Disable.
4120 * - On success, zero.
4121 * - On failure, a negative value.
4124 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4126 struct ixgbe_interrupt *intr =
4127 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4129 ixgbe_dev_link_status_print(dev);
4131 intr->mask |= IXGBE_EICR_LSC;
4133 intr->mask &= ~IXGBE_EICR_LSC;
4139 * It clears the interrupt causes and enables the interrupt.
4140 * It will be called once only during nic initialized.
4143 * Pointer to struct rte_eth_dev.
4146 * - On success, zero.
4147 * - On failure, a negative value.
4150 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4152 struct ixgbe_interrupt *intr =
4153 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4155 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4161 * It clears the interrupt causes and enables the interrupt.
4162 * It will be called once only during nic initialized.
4165 * Pointer to struct rte_eth_dev.
4168 * - On success, zero.
4169 * - On failure, a negative value.
4172 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4174 struct ixgbe_interrupt *intr =
4175 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4177 intr->mask |= IXGBE_EICR_LINKSEC;
4183 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4186 * Pointer to struct rte_eth_dev.
4189 * - On success, zero.
4190 * - On failure, a negative value.
4193 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4196 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4197 struct ixgbe_interrupt *intr =
4198 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4200 /* clear all cause mask */
4201 ixgbe_disable_intr(hw);
4203 /* read-on-clear nic registers here */
4204 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4205 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4209 /* set flag for async link update */
4210 if (eicr & IXGBE_EICR_LSC)
4211 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4213 if (eicr & IXGBE_EICR_MAILBOX)
4214 intr->flags |= IXGBE_FLAG_MAILBOX;
4216 if (eicr & IXGBE_EICR_LINKSEC)
4217 intr->flags |= IXGBE_FLAG_MACSEC;
4219 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4220 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4221 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4222 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4228 * It gets and then prints the link status.
4231 * Pointer to struct rte_eth_dev.
4234 * - On success, zero.
4235 * - On failure, a negative value.
4238 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4240 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4241 struct rte_eth_link link;
4243 memset(&link, 0, sizeof(link));
4244 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4245 if (link.link_status) {
4246 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4247 (int)(dev->data->port_id),
4248 (unsigned)link.link_speed,
4249 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4250 "full-duplex" : "half-duplex");
4252 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4253 (int)(dev->data->port_id));
4255 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4256 pci_dev->addr.domain,
4258 pci_dev->addr.devid,
4259 pci_dev->addr.function);
4263 * It executes link_update after knowing an interrupt occurred.
4266 * Pointer to struct rte_eth_dev.
4269 * - On success, zero.
4270 * - On failure, a negative value.
4273 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4274 struct rte_intr_handle *intr_handle)
4276 struct ixgbe_interrupt *intr =
4277 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4279 struct rte_eth_link link;
4280 struct ixgbe_hw *hw =
4281 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4283 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4285 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4286 ixgbe_pf_mbx_process(dev);
4287 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4290 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4291 ixgbe_handle_lasi(hw);
4292 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4295 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4296 /* get the link status before link update, for predicting later */
4297 memset(&link, 0, sizeof(link));
4298 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4300 ixgbe_dev_link_update(dev, 0);
4303 if (!link.link_status)
4304 /* handle it 1 sec later, wait it being stable */
4305 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4306 /* likely to down */
4308 /* handle it 4 sec later, wait it being stable */
4309 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4311 ixgbe_dev_link_status_print(dev);
4312 if (rte_eal_alarm_set(timeout * 1000,
4313 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4314 PMD_DRV_LOG(ERR, "Error setting alarm");
4316 /* remember original mask */
4317 intr->mask_original = intr->mask;
4318 /* only disable lsc interrupt */
4319 intr->mask &= ~IXGBE_EIMS_LSC;
4323 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4324 ixgbe_enable_intr(dev);
4325 rte_intr_enable(intr_handle);
4331 * Interrupt handler which shall be registered for alarm callback for delayed
4332 * handling specific interrupt to wait for the stable nic state. As the
4333 * NIC interrupt state is not stable for ixgbe after link is just down,
4334 * it needs to wait 4 seconds to get the stable status.
4337 * Pointer to interrupt handle.
4339 * The address of parameter (struct rte_eth_dev *) regsitered before.
4345 ixgbe_dev_interrupt_delayed_handler(void *param)
4347 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4348 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4349 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4350 struct ixgbe_interrupt *intr =
4351 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4352 struct ixgbe_hw *hw =
4353 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356 ixgbe_disable_intr(hw);
4358 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4359 if (eicr & IXGBE_EICR_MAILBOX)
4360 ixgbe_pf_mbx_process(dev);
4362 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4363 ixgbe_handle_lasi(hw);
4364 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4367 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4368 ixgbe_dev_link_update(dev, 0);
4369 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4370 ixgbe_dev_link_status_print(dev);
4371 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4375 if (intr->flags & IXGBE_FLAG_MACSEC) {
4376 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4378 intr->flags &= ~IXGBE_FLAG_MACSEC;
4381 /* restore original mask */
4382 intr->mask = intr->mask_original;
4383 intr->mask_original = 0;
4385 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4386 ixgbe_enable_intr(dev);
4387 rte_intr_enable(intr_handle);
4391 * Interrupt handler triggered by NIC for handling
4392 * specific interrupt.
4395 * Pointer to interrupt handle.
4397 * The address of parameter (struct rte_eth_dev *) regsitered before.
4403 ixgbe_dev_interrupt_handler(void *param)
4405 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4407 ixgbe_dev_interrupt_get_status(dev);
4408 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4412 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4414 struct ixgbe_hw *hw;
4416 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4421 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4423 struct ixgbe_hw *hw;
4425 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4430 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4432 struct ixgbe_hw *hw;
4438 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4440 fc_conf->pause_time = hw->fc.pause_time;
4441 fc_conf->high_water = hw->fc.high_water[0];
4442 fc_conf->low_water = hw->fc.low_water[0];
4443 fc_conf->send_xon = hw->fc.send_xon;
4444 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4447 * Return rx_pause status according to actual setting of
4450 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4451 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4457 * Return tx_pause status according to actual setting of
4460 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4461 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4466 if (rx_pause && tx_pause)
4467 fc_conf->mode = RTE_FC_FULL;
4469 fc_conf->mode = RTE_FC_RX_PAUSE;
4471 fc_conf->mode = RTE_FC_TX_PAUSE;
4473 fc_conf->mode = RTE_FC_NONE;
4479 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4481 struct ixgbe_hw *hw;
4483 uint32_t rx_buf_size;
4484 uint32_t max_high_water;
4486 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4493 PMD_INIT_FUNC_TRACE();
4495 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4497 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4500 * At least reserve one Ethernet frame for watermark
4501 * high_water/low_water in kilo bytes for ixgbe
4503 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4504 if ((fc_conf->high_water > max_high_water) ||
4505 (fc_conf->high_water < fc_conf->low_water)) {
4506 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4507 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4511 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4512 hw->fc.pause_time = fc_conf->pause_time;
4513 hw->fc.high_water[0] = fc_conf->high_water;
4514 hw->fc.low_water[0] = fc_conf->low_water;
4515 hw->fc.send_xon = fc_conf->send_xon;
4516 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4518 err = ixgbe_fc_enable(hw);
4520 /* Not negotiated is not an error case */
4521 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4523 /* check if we want to forward MAC frames - driver doesn't have native
4524 * capability to do that, so we'll write the registers ourselves */
4526 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4528 /* set or clear MFLCN.PMCF bit depending on configuration */
4529 if (fc_conf->mac_ctrl_frame_fwd != 0)
4530 mflcn |= IXGBE_MFLCN_PMCF;
4532 mflcn &= ~IXGBE_MFLCN_PMCF;
4534 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4535 IXGBE_WRITE_FLUSH(hw);
4540 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4545 * ixgbe_pfc_enable_generic - Enable flow control
4546 * @hw: pointer to hardware structure
4547 * @tc_num: traffic class number
4548 * Enable flow control according to the current settings.
4551 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4554 uint32_t mflcn_reg, fccfg_reg;
4556 uint32_t fcrtl, fcrth;
4560 /* Validate the water mark configuration */
4561 if (!hw->fc.pause_time) {
4562 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4566 /* Low water mark of zero causes XOFF floods */
4567 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4568 /* High/Low water can not be 0 */
4569 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4570 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4571 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4575 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4576 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4577 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4581 /* Negotiate the fc mode to use */
4582 ixgbe_fc_autoneg(hw);
4584 /* Disable any previous flow control settings */
4585 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4586 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4588 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4589 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4591 switch (hw->fc.current_mode) {
4594 * If the count of enabled RX Priority Flow control >1,
4595 * and the TX pause can not be disabled
4598 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4599 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4600 if (reg & IXGBE_FCRTH_FCEN)
4604 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4606 case ixgbe_fc_rx_pause:
4608 * Rx Flow control is enabled and Tx Flow control is
4609 * disabled by software override. Since there really
4610 * isn't a way to advertise that we are capable of RX
4611 * Pause ONLY, we will advertise that we support both
4612 * symmetric and asymmetric Rx PAUSE. Later, we will
4613 * disable the adapter's ability to send PAUSE frames.
4615 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4617 * If the count of enabled RX Priority Flow control >1,
4618 * and the TX pause can not be disabled
4621 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4622 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4623 if (reg & IXGBE_FCRTH_FCEN)
4627 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4629 case ixgbe_fc_tx_pause:
4631 * Tx Flow control is enabled, and Rx Flow control is
4632 * disabled by software override.
4634 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4637 /* Flow control (both Rx and Tx) is enabled by SW override. */
4638 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4639 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4642 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4643 ret_val = IXGBE_ERR_CONFIG;
4647 /* Set 802.3x based flow control settings. */
4648 mflcn_reg |= IXGBE_MFLCN_DPF;
4649 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4650 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4652 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4653 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4654 hw->fc.high_water[tc_num]) {
4655 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4656 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4657 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4659 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4661 * In order to prevent Tx hangs when the internal Tx
4662 * switch is enabled we must set the high water mark
4663 * to the maximum FCRTH value. This allows the Tx
4664 * switch to function even under heavy Rx workloads.
4666 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4668 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4670 /* Configure pause time (2 TCs per register) */
4671 reg = hw->fc.pause_time * 0x00010001;
4672 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4673 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4675 /* Configure flow control refresh threshold value */
4676 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4683 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4685 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4686 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4688 if (hw->mac.type != ixgbe_mac_82598EB) {
4689 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4695 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4698 uint32_t rx_buf_size;
4699 uint32_t max_high_water;
4701 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4702 struct ixgbe_hw *hw =
4703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704 struct ixgbe_dcb_config *dcb_config =
4705 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4707 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4714 PMD_INIT_FUNC_TRACE();
4716 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4717 tc_num = map[pfc_conf->priority];
4718 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4719 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4721 * At least reserve one Ethernet frame for watermark
4722 * high_water/low_water in kilo bytes for ixgbe
4724 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4725 if ((pfc_conf->fc.high_water > max_high_water) ||
4726 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4727 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4728 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4732 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4733 hw->fc.pause_time = pfc_conf->fc.pause_time;
4734 hw->fc.send_xon = pfc_conf->fc.send_xon;
4735 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4736 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4738 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4740 /* Not negotiated is not an error case */
4741 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4744 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4749 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4750 struct rte_eth_rss_reta_entry64 *reta_conf,
4753 uint16_t i, sp_reta_size;
4756 uint16_t idx, shift;
4757 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4760 PMD_INIT_FUNC_TRACE();
4762 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4763 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4768 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4769 if (reta_size != sp_reta_size) {
4770 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4771 "(%d) doesn't match the number hardware can supported "
4772 "(%d)", reta_size, sp_reta_size);
4776 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4777 idx = i / RTE_RETA_GROUP_SIZE;
4778 shift = i % RTE_RETA_GROUP_SIZE;
4779 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4783 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4784 if (mask == IXGBE_4_BIT_MASK)
4787 r = IXGBE_READ_REG(hw, reta_reg);
4788 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4789 if (mask & (0x1 << j))
4790 reta |= reta_conf[idx].reta[shift + j] <<
4793 reta |= r & (IXGBE_8_BIT_MASK <<
4796 IXGBE_WRITE_REG(hw, reta_reg, reta);
4803 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4804 struct rte_eth_rss_reta_entry64 *reta_conf,
4807 uint16_t i, sp_reta_size;
4810 uint16_t idx, shift;
4811 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814 PMD_INIT_FUNC_TRACE();
4815 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4816 if (reta_size != sp_reta_size) {
4817 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4818 "(%d) doesn't match the number hardware can supported "
4819 "(%d)", reta_size, sp_reta_size);
4823 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4824 idx = i / RTE_RETA_GROUP_SIZE;
4825 shift = i % RTE_RETA_GROUP_SIZE;
4826 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4831 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4832 reta = IXGBE_READ_REG(hw, reta_reg);
4833 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4834 if (mask & (0x1 << j))
4835 reta_conf[idx].reta[shift + j] =
4836 ((reta >> (CHAR_BIT * j)) &
4845 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4846 uint32_t index, uint32_t pool)
4848 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4849 uint32_t enable_addr = 1;
4851 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4856 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860 ixgbe_clear_rar(hw, index);
4864 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4866 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4868 ixgbe_remove_rar(dev, 0);
4870 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4874 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4876 if (strcmp(dev->device->driver->name, drv->driver.name))
4883 is_ixgbe_supported(struct rte_eth_dev *dev)
4885 return is_device_supported(dev, &rte_ixgbe_pmd);
4889 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4893 struct ixgbe_hw *hw;
4894 struct rte_eth_dev_info dev_info;
4895 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4896 struct rte_eth_dev_data *dev_data = dev->data;
4898 ixgbe_dev_info_get(dev, &dev_info);
4900 /* check that mtu is within the allowed range */
4901 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4904 /* If device is started, refuse mtu that requires the support of
4905 * scattered packets when this feature has not been enabled before.
4907 if (dev_data->dev_started && !dev_data->scattered_rx &&
4908 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4909 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4910 PMD_INIT_LOG(ERR, "Stop port first.");
4914 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4915 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4917 /* switch to jumbo mode if needed */
4918 if (frame_size > ETHER_MAX_LEN) {
4919 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4920 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4922 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4923 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4925 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4927 /* update max frame size */
4928 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4930 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4931 maxfrs &= 0x0000FFFF;
4932 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4933 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4939 * Virtual Function operations
4942 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4944 PMD_INIT_FUNC_TRACE();
4946 /* Clear interrupt mask to stop from interrupts being generated */
4947 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4949 IXGBE_WRITE_FLUSH(hw);
4953 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4955 PMD_INIT_FUNC_TRACE();
4957 /* VF enable interrupt autoclean */
4958 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4959 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4960 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4962 IXGBE_WRITE_FLUSH(hw);
4966 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4968 struct rte_eth_conf *conf = &dev->data->dev_conf;
4969 struct ixgbe_adapter *adapter =
4970 (struct ixgbe_adapter *)dev->data->dev_private;
4972 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4973 dev->data->port_id);
4976 * VF has no ability to enable/disable HW CRC
4977 * Keep the persistent behavior the same as Host PF
4979 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4980 if (!conf->rxmode.hw_strip_crc) {
4981 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4982 conf->rxmode.hw_strip_crc = 1;
4985 if (conf->rxmode.hw_strip_crc) {
4986 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4987 conf->rxmode.hw_strip_crc = 0;
4992 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4993 * allocation or vector Rx preconditions we will reset it.
4995 adapter->rx_bulk_alloc_allowed = true;
4996 adapter->rx_vec_allowed = true;
5002 ixgbevf_dev_start(struct rte_eth_dev *dev)
5004 struct ixgbe_hw *hw =
5005 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5006 uint32_t intr_vector = 0;
5007 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5008 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5012 PMD_INIT_FUNC_TRACE();
5014 hw->mac.ops.reset_hw(hw);
5015 hw->mac.get_link_status = true;
5017 /* negotiate mailbox API version to use with the PF. */
5018 ixgbevf_negotiate_api(hw);
5020 ixgbevf_dev_tx_init(dev);
5022 /* This can fail when allocating mbufs for descriptor rings */
5023 err = ixgbevf_dev_rx_init(dev);
5025 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5026 ixgbe_dev_clear_queues(dev);
5031 ixgbevf_set_vfta_all(dev, 1);
5034 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5035 ETH_VLAN_EXTEND_MASK;
5036 ixgbevf_vlan_offload_set(dev, mask);
5038 ixgbevf_dev_rxtx_start(dev);
5040 /* check and configure queue intr-vector mapping */
5041 if (dev->data->dev_conf.intr_conf.rxq != 0) {
5042 /* According to datasheet, only vector 0/1/2 can be used,
5043 * now only one vector is used for Rx queue
5046 if (rte_intr_efd_enable(intr_handle, intr_vector))
5050 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5051 intr_handle->intr_vec =
5052 rte_zmalloc("intr_vec",
5053 dev->data->nb_rx_queues * sizeof(int), 0);
5054 if (intr_handle->intr_vec == NULL) {
5055 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5056 " intr_vec", dev->data->nb_rx_queues);
5060 ixgbevf_configure_msix(dev);
5062 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5063 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5064 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5065 * is not cleared, it will fail when following rte_intr_enable( ) tries
5066 * to map Rx queue interrupt to other VFIO vectors.
5067 * So clear uio/vfio intr/evevnfd first to avoid failure.
5069 rte_intr_disable(intr_handle);
5071 rte_intr_enable(intr_handle);
5073 /* Re-enable interrupt for VF */
5074 ixgbevf_intr_enable(hw);
5080 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5082 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5083 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5084 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5086 PMD_INIT_FUNC_TRACE();
5088 ixgbevf_intr_disable(hw);
5090 hw->adapter_stopped = 1;
5091 ixgbe_stop_adapter(hw);
5094 * Clear what we set, but we still keep shadow_vfta to
5095 * restore after device starts
5097 ixgbevf_set_vfta_all(dev, 0);
5099 /* Clear stored conf */
5100 dev->data->scattered_rx = 0;
5102 ixgbe_dev_clear_queues(dev);
5104 /* Clean datapath event and queue/vec mapping */
5105 rte_intr_efd_disable(intr_handle);
5106 if (intr_handle->intr_vec != NULL) {
5107 rte_free(intr_handle->intr_vec);
5108 intr_handle->intr_vec = NULL;
5113 ixgbevf_dev_close(struct rte_eth_dev *dev)
5115 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5117 PMD_INIT_FUNC_TRACE();
5121 ixgbevf_dev_stop(dev);
5123 ixgbe_dev_free_queues(dev);
5126 * Remove the VF MAC address ro ensure
5127 * that the VF traffic goes to the PF
5128 * after stop, close and detach of the VF
5130 ixgbevf_remove_mac_addr(dev, 0);
5137 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5141 ret = eth_ixgbevf_dev_uninit(dev);
5145 ret = eth_ixgbevf_dev_init(dev);
5150 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5152 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5153 struct ixgbe_vfta *shadow_vfta =
5154 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5155 int i = 0, j = 0, vfta = 0, mask = 1;
5157 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5158 vfta = shadow_vfta->vfta[i];
5161 for (j = 0; j < 32; j++) {
5163 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5173 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5175 struct ixgbe_hw *hw =
5176 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5177 struct ixgbe_vfta *shadow_vfta =
5178 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5179 uint32_t vid_idx = 0;
5180 uint32_t vid_bit = 0;
5183 PMD_INIT_FUNC_TRACE();
5185 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5186 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5188 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5191 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5192 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5194 /* Save what we set and retore it after device reset */
5196 shadow_vfta->vfta[vid_idx] |= vid_bit;
5198 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5204 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5206 struct ixgbe_hw *hw =
5207 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5210 PMD_INIT_FUNC_TRACE();
5212 if (queue >= hw->mac.max_rx_queues)
5215 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5217 ctrl |= IXGBE_RXDCTL_VME;
5219 ctrl &= ~IXGBE_RXDCTL_VME;
5220 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5222 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5226 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5228 struct ixgbe_hw *hw =
5229 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5233 /* VF function only support hw strip feature, others are not support */
5234 if (mask & ETH_VLAN_STRIP_MASK) {
5235 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5237 for (i = 0; i < hw->mac.max_rx_queues; i++)
5238 ixgbevf_vlan_strip_queue_set(dev, i, on);
5243 ixgbe_vt_check(struct ixgbe_hw *hw)
5247 /* if Virtualization Technology is enabled */
5248 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5249 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5250 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5258 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5260 uint32_t vector = 0;
5262 switch (hw->mac.mc_filter_type) {
5263 case 0: /* use bits [47:36] of the address */
5264 vector = ((uc_addr->addr_bytes[4] >> 4) |
5265 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5267 case 1: /* use bits [46:35] of the address */
5268 vector = ((uc_addr->addr_bytes[4] >> 3) |
5269 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5271 case 2: /* use bits [45:34] of the address */
5272 vector = ((uc_addr->addr_bytes[4] >> 2) |
5273 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5275 case 3: /* use bits [43:32] of the address */
5276 vector = ((uc_addr->addr_bytes[4]) |
5277 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5279 default: /* Invalid mc_filter_type */
5283 /* vector can only be 12-bits or boundary will be exceeded */
5289 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5297 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5298 const uint32_t ixgbe_uta_bit_shift = 5;
5299 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5300 const uint32_t bit1 = 0x1;
5302 struct ixgbe_hw *hw =
5303 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5304 struct ixgbe_uta_info *uta_info =
5305 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5307 /* The UTA table only exists on 82599 hardware and newer */
5308 if (hw->mac.type < ixgbe_mac_82599EB)
5311 vector = ixgbe_uta_vector(hw, mac_addr);
5312 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5313 uta_shift = vector & ixgbe_uta_bit_mask;
5315 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5319 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5321 uta_info->uta_in_use++;
5322 reg_val |= (bit1 << uta_shift);
5323 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5325 uta_info->uta_in_use--;
5326 reg_val &= ~(bit1 << uta_shift);
5327 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5330 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5332 if (uta_info->uta_in_use > 0)
5333 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5334 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5336 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5342 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5345 struct ixgbe_hw *hw =
5346 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347 struct ixgbe_uta_info *uta_info =
5348 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5350 /* The UTA table only exists on 82599 hardware and newer */
5351 if (hw->mac.type < ixgbe_mac_82599EB)
5355 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5356 uta_info->uta_shadow[i] = ~0;
5357 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5360 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5361 uta_info->uta_shadow[i] = 0;
5362 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5370 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5372 uint32_t new_val = orig_val;
5374 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5375 new_val |= IXGBE_VMOLR_AUPE;
5376 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5377 new_val |= IXGBE_VMOLR_ROMPE;
5378 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5379 new_val |= IXGBE_VMOLR_ROPE;
5380 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5381 new_val |= IXGBE_VMOLR_BAM;
5382 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5383 new_val |= IXGBE_VMOLR_MPE;
5388 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5389 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5390 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5391 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5392 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5393 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5394 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5397 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5398 struct rte_eth_mirror_conf *mirror_conf,
5399 uint8_t rule_id, uint8_t on)
5401 uint32_t mr_ctl, vlvf;
5402 uint32_t mp_lsb = 0;
5403 uint32_t mv_msb = 0;
5404 uint32_t mv_lsb = 0;
5405 uint32_t mp_msb = 0;
5408 uint64_t vlan_mask = 0;
5410 const uint8_t pool_mask_offset = 32;
5411 const uint8_t vlan_mask_offset = 32;
5412 const uint8_t dst_pool_offset = 8;
5413 const uint8_t rule_mr_offset = 4;
5414 const uint8_t mirror_rule_mask = 0x0F;
5416 struct ixgbe_mirror_info *mr_info =
5417 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5418 struct ixgbe_hw *hw =
5419 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5420 uint8_t mirror_type = 0;
5422 if (ixgbe_vt_check(hw) < 0)
5425 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5428 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5429 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5430 mirror_conf->rule_type);
5434 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5435 mirror_type |= IXGBE_MRCTL_VLME;
5436 /* Check if vlan id is valid and find conresponding VLAN ID
5439 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5440 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5441 /* search vlan id related pool vlan filter
5444 reg_index = ixgbe_find_vlvf_slot(
5446 mirror_conf->vlan.vlan_id[i],
5450 vlvf = IXGBE_READ_REG(hw,
5451 IXGBE_VLVF(reg_index));
5452 if ((vlvf & IXGBE_VLVF_VIEN) &&
5453 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5454 mirror_conf->vlan.vlan_id[i]))
5455 vlan_mask |= (1ULL << reg_index);
5462 mv_lsb = vlan_mask & 0xFFFFFFFF;
5463 mv_msb = vlan_mask >> vlan_mask_offset;
5465 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5466 mirror_conf->vlan.vlan_mask;
5467 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5468 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5469 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5470 mirror_conf->vlan.vlan_id[i];
5475 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5476 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5477 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5482 * if enable pool mirror, write related pool mask register,if disable
5483 * pool mirror, clear PFMRVM register
5485 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5486 mirror_type |= IXGBE_MRCTL_VPME;
5488 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5489 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5490 mr_info->mr_conf[rule_id].pool_mask =
5491 mirror_conf->pool_mask;
5496 mr_info->mr_conf[rule_id].pool_mask = 0;
5499 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5500 mirror_type |= IXGBE_MRCTL_UPME;
5501 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5502 mirror_type |= IXGBE_MRCTL_DPME;
5504 /* read mirror control register and recalculate it */
5505 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5508 mr_ctl |= mirror_type;
5509 mr_ctl &= mirror_rule_mask;
5510 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5512 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5515 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5516 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5518 /* write mirrror control register */
5519 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5521 /* write pool mirrror control register */
5522 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5523 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5524 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5527 /* write VLAN mirrror control register */
5528 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5529 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5530 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5538 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5541 uint32_t lsb_val = 0;
5542 uint32_t msb_val = 0;
5543 const uint8_t rule_mr_offset = 4;
5545 struct ixgbe_hw *hw =
5546 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5547 struct ixgbe_mirror_info *mr_info =
5548 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5550 if (ixgbe_vt_check(hw) < 0)
5553 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5556 memset(&mr_info->mr_conf[rule_id], 0,
5557 sizeof(struct rte_eth_mirror_conf));
5559 /* clear PFVMCTL register */
5560 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5562 /* clear pool mask register */
5563 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5564 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5566 /* clear vlan mask register */
5567 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5568 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5574 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5576 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5577 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5579 struct ixgbe_hw *hw =
5580 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5581 uint32_t vec = IXGBE_MISC_VEC_ID;
5583 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5584 if (rte_intr_allow_others(intr_handle))
5585 vec = IXGBE_RX_VEC_START;
5587 RTE_SET_USED(queue_id);
5588 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5590 rte_intr_enable(intr_handle);
5596 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5599 struct ixgbe_hw *hw =
5600 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5601 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5602 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5603 uint32_t vec = IXGBE_MISC_VEC_ID;
5605 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5606 if (rte_intr_allow_others(intr_handle))
5607 vec = IXGBE_RX_VEC_START;
5608 mask &= ~(1 << vec);
5609 RTE_SET_USED(queue_id);
5610 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5616 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5618 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5619 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5621 struct ixgbe_hw *hw =
5622 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5623 struct ixgbe_interrupt *intr =
5624 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5626 if (queue_id < 16) {
5627 ixgbe_disable_intr(hw);
5628 intr->mask |= (1 << queue_id);
5629 ixgbe_enable_intr(dev);
5630 } else if (queue_id < 32) {
5631 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5632 mask &= (1 << queue_id);
5633 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5634 } else if (queue_id < 64) {
5635 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5636 mask &= (1 << (queue_id - 32));
5637 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5639 rte_intr_enable(intr_handle);
5645 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5648 struct ixgbe_hw *hw =
5649 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650 struct ixgbe_interrupt *intr =
5651 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5653 if (queue_id < 16) {
5654 ixgbe_disable_intr(hw);
5655 intr->mask &= ~(1 << queue_id);
5656 ixgbe_enable_intr(dev);
5657 } else if (queue_id < 32) {
5658 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5659 mask &= ~(1 << queue_id);
5660 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5661 } else if (queue_id < 64) {
5662 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5663 mask &= ~(1 << (queue_id - 32));
5664 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5671 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5672 uint8_t queue, uint8_t msix_vector)
5676 if (direction == -1) {
5678 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5679 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5682 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5684 /* rx or tx cause */
5685 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5686 idx = ((16 * (queue & 1)) + (8 * direction));
5687 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5688 tmp &= ~(0xFF << idx);
5689 tmp |= (msix_vector << idx);
5690 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5695 * set the IVAR registers, mapping interrupt causes to vectors
5697 * pointer to ixgbe_hw struct
5699 * 0 for Rx, 1 for Tx, -1 for other causes
5701 * queue to map the corresponding interrupt to
5703 * the vector to map to the corresponding queue
5706 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5707 uint8_t queue, uint8_t msix_vector)
5711 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5712 if (hw->mac.type == ixgbe_mac_82598EB) {
5713 if (direction == -1)
5715 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5716 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5717 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5718 tmp |= (msix_vector << (8 * (queue & 0x3)));
5719 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5720 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5721 (hw->mac.type == ixgbe_mac_X540) ||
5722 (hw->mac.type == ixgbe_mac_X550)) {
5723 if (direction == -1) {
5725 idx = ((queue & 1) * 8);
5726 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5727 tmp &= ~(0xFF << idx);
5728 tmp |= (msix_vector << idx);
5729 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5731 /* rx or tx causes */
5732 idx = ((16 * (queue & 1)) + (8 * direction));
5733 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5734 tmp &= ~(0xFF << idx);
5735 tmp |= (msix_vector << idx);
5736 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5742 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5744 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5745 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5746 struct ixgbe_hw *hw =
5747 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5749 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5750 uint32_t base = IXGBE_MISC_VEC_ID;
5752 /* Configure VF other cause ivar */
5753 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5755 /* won't configure msix register if no mapping is done
5756 * between intr vector and event fd.
5758 if (!rte_intr_dp_is_en(intr_handle))
5761 if (rte_intr_allow_others(intr_handle)) {
5762 base = IXGBE_RX_VEC_START;
5763 vector_idx = IXGBE_RX_VEC_START;
5766 /* Configure all RX queues of VF */
5767 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5768 /* Force all queue use vector 0,
5769 * as IXGBE_VF_MAXMSIVECOTR = 1
5771 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5772 intr_handle->intr_vec[q_idx] = vector_idx;
5773 if (vector_idx < base + intr_handle->nb_efd - 1)
5779 * Sets up the hardware to properly generate MSI-X interrupts
5781 * board private structure
5784 ixgbe_configure_msix(struct rte_eth_dev *dev)
5786 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5787 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5788 struct ixgbe_hw *hw =
5789 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5790 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5791 uint32_t vec = IXGBE_MISC_VEC_ID;
5795 /* won't configure msix register if no mapping is done
5796 * between intr vector and event fd
5798 if (!rte_intr_dp_is_en(intr_handle))
5801 if (rte_intr_allow_others(intr_handle))
5802 vec = base = IXGBE_RX_VEC_START;
5804 /* setup GPIE for MSI-x mode */
5805 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5806 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5807 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5808 /* auto clearing and auto setting corresponding bits in EIMS
5809 * when MSI-X interrupt is triggered
5811 if (hw->mac.type == ixgbe_mac_82598EB) {
5812 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5814 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5815 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5817 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5819 /* Populate the IVAR table and set the ITR values to the
5820 * corresponding register.
5822 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5824 /* by default, 1:1 mapping */
5825 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5826 intr_handle->intr_vec[queue_id] = vec;
5827 if (vec < base + intr_handle->nb_efd - 1)
5831 switch (hw->mac.type) {
5832 case ixgbe_mac_82598EB:
5833 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5836 case ixgbe_mac_82599EB:
5837 case ixgbe_mac_X540:
5838 case ixgbe_mac_X550:
5839 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5844 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5845 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5847 /* set up to autoclear timer, and the vectors */
5848 mask = IXGBE_EIMS_ENABLE_MASK;
5849 mask &= ~(IXGBE_EIMS_OTHER |
5850 IXGBE_EIMS_MAILBOX |
5853 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5857 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5858 uint16_t queue_idx, uint16_t tx_rate)
5860 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5861 uint32_t rf_dec, rf_int;
5863 uint16_t link_speed = dev->data->dev_link.link_speed;
5865 if (queue_idx >= hw->mac.max_tx_queues)
5869 /* Calculate the rate factor values to set */
5870 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5871 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5872 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5874 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5875 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5876 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5877 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5883 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5884 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5887 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5888 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5889 IXGBE_MAX_JUMBO_FRAME_SIZE))
5890 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5891 IXGBE_MMW_SIZE_JUMBO_FRAME);
5893 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5894 IXGBE_MMW_SIZE_DEFAULT);
5896 /* Set RTTBCNRC of queue X */
5897 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5898 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5899 IXGBE_WRITE_FLUSH(hw);
5905 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5906 __attribute__((unused)) uint32_t index,
5907 __attribute__((unused)) uint32_t pool)
5909 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5913 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5914 * operation. Trap this case to avoid exhausting the [very limited]
5915 * set of PF resources used to store VF MAC addresses.
5917 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5919 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5921 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5922 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5923 mac_addr->addr_bytes[0],
5924 mac_addr->addr_bytes[1],
5925 mac_addr->addr_bytes[2],
5926 mac_addr->addr_bytes[3],
5927 mac_addr->addr_bytes[4],
5928 mac_addr->addr_bytes[5],
5934 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5936 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5937 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5938 struct ether_addr *mac_addr;
5943 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5944 * not support the deletion of a given MAC address.
5945 * Instead, it imposes to delete all MAC addresses, then to add again
5946 * all MAC addresses with the exception of the one to be deleted.
5948 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5951 * Add again all MAC addresses, with the exception of the deleted one
5952 * and of the permanent MAC address.
5954 for (i = 0, mac_addr = dev->data->mac_addrs;
5955 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5956 /* Skip the deleted MAC address */
5959 /* Skip NULL MAC addresses */
5960 if (is_zero_ether_addr(mac_addr))
5962 /* Skip the permanent MAC address */
5963 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5965 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5968 "Adding again MAC address "
5969 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5971 mac_addr->addr_bytes[0],
5972 mac_addr->addr_bytes[1],
5973 mac_addr->addr_bytes[2],
5974 mac_addr->addr_bytes[3],
5975 mac_addr->addr_bytes[4],
5976 mac_addr->addr_bytes[5],
5982 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5984 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5986 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5990 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5991 struct rte_eth_syn_filter *filter,
5994 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5995 struct ixgbe_filter_info *filter_info =
5996 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6000 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6003 syn_info = filter_info->syn_info;
6006 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6008 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6009 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6011 if (filter->hig_pri)
6012 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6014 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6016 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6017 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6019 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6022 filter_info->syn_info = synqf;
6023 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6024 IXGBE_WRITE_FLUSH(hw);
6029 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6030 struct rte_eth_syn_filter *filter)
6032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6033 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6035 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6036 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6037 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6044 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6045 enum rte_filter_op filter_op,
6048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6051 MAC_TYPE_FILTER_SUP(hw->mac.type);
6053 if (filter_op == RTE_ETH_FILTER_NOP)
6057 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6062 switch (filter_op) {
6063 case RTE_ETH_FILTER_ADD:
6064 ret = ixgbe_syn_filter_set(dev,
6065 (struct rte_eth_syn_filter *)arg,
6068 case RTE_ETH_FILTER_DELETE:
6069 ret = ixgbe_syn_filter_set(dev,
6070 (struct rte_eth_syn_filter *)arg,
6073 case RTE_ETH_FILTER_GET:
6074 ret = ixgbe_syn_filter_get(dev,
6075 (struct rte_eth_syn_filter *)arg);
6078 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6087 static inline enum ixgbe_5tuple_protocol
6088 convert_protocol_type(uint8_t protocol_value)
6090 if (protocol_value == IPPROTO_TCP)
6091 return IXGBE_FILTER_PROTOCOL_TCP;
6092 else if (protocol_value == IPPROTO_UDP)
6093 return IXGBE_FILTER_PROTOCOL_UDP;
6094 else if (protocol_value == IPPROTO_SCTP)
6095 return IXGBE_FILTER_PROTOCOL_SCTP;
6097 return IXGBE_FILTER_PROTOCOL_NONE;
6100 /* inject a 5-tuple filter to HW */
6102 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6103 struct ixgbe_5tuple_filter *filter)
6105 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6107 uint32_t ftqf, sdpqf;
6108 uint32_t l34timir = 0;
6109 uint8_t mask = 0xff;
6113 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6114 IXGBE_SDPQF_DSTPORT_SHIFT);
6115 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6117 ftqf = (uint32_t)(filter->filter_info.proto &
6118 IXGBE_FTQF_PROTOCOL_MASK);
6119 ftqf |= (uint32_t)((filter->filter_info.priority &
6120 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6121 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6122 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6123 if (filter->filter_info.dst_ip_mask == 0)
6124 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6125 if (filter->filter_info.src_port_mask == 0)
6126 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6127 if (filter->filter_info.dst_port_mask == 0)
6128 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6129 if (filter->filter_info.proto_mask == 0)
6130 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6131 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6132 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6133 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6135 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6136 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6137 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6138 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6140 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6141 l34timir |= (uint32_t)(filter->queue <<
6142 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6143 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6147 * add a 5tuple filter
6150 * dev: Pointer to struct rte_eth_dev.
6151 * index: the index the filter allocates.
6152 * filter: ponter to the filter that will be added.
6153 * rx_queue: the queue id the filter assigned to.
6156 * - On success, zero.
6157 * - On failure, a negative value.
6160 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6161 struct ixgbe_5tuple_filter *filter)
6163 struct ixgbe_filter_info *filter_info =
6164 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6168 * look for an unused 5tuple filter index,
6169 * and insert the filter to list.
6171 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6172 idx = i / (sizeof(uint32_t) * NBBY);
6173 shift = i % (sizeof(uint32_t) * NBBY);
6174 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6175 filter_info->fivetuple_mask[idx] |= 1 << shift;
6177 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6183 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6184 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6188 ixgbe_inject_5tuple_filter(dev, filter);
6194 * remove a 5tuple filter
6197 * dev: Pointer to struct rte_eth_dev.
6198 * filter: the pointer of the filter will be removed.
6201 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6202 struct ixgbe_5tuple_filter *filter)
6204 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6205 struct ixgbe_filter_info *filter_info =
6206 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6207 uint16_t index = filter->index;
6209 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6210 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6211 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6214 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6215 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6216 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6217 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6218 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6222 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6224 struct ixgbe_hw *hw;
6225 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6226 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6228 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6230 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6233 /* refuse mtu that requires the support of scattered packets when this
6234 * feature has not been enabled before.
6236 if (!rx_conf->enable_scatter &&
6237 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6238 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6242 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6243 * request of the version 2.0 of the mailbox API.
6244 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6245 * of the mailbox API.
6246 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6247 * prior to 3.11.33 which contains the following change:
6248 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6250 ixgbevf_rlpml_set_vf(hw, max_frame);
6252 /* update max frame size */
6253 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6257 static inline struct ixgbe_5tuple_filter *
6258 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6259 struct ixgbe_5tuple_filter_info *key)
6261 struct ixgbe_5tuple_filter *it;
6263 TAILQ_FOREACH(it, filter_list, entries) {
6264 if (memcmp(key, &it->filter_info,
6265 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6272 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6274 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6275 struct ixgbe_5tuple_filter_info *filter_info)
6277 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6278 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6279 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6282 switch (filter->dst_ip_mask) {
6284 filter_info->dst_ip_mask = 0;
6285 filter_info->dst_ip = filter->dst_ip;
6288 filter_info->dst_ip_mask = 1;
6291 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6295 switch (filter->src_ip_mask) {
6297 filter_info->src_ip_mask = 0;
6298 filter_info->src_ip = filter->src_ip;
6301 filter_info->src_ip_mask = 1;
6304 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6308 switch (filter->dst_port_mask) {
6310 filter_info->dst_port_mask = 0;
6311 filter_info->dst_port = filter->dst_port;
6314 filter_info->dst_port_mask = 1;
6317 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6321 switch (filter->src_port_mask) {
6323 filter_info->src_port_mask = 0;
6324 filter_info->src_port = filter->src_port;
6327 filter_info->src_port_mask = 1;
6330 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6334 switch (filter->proto_mask) {
6336 filter_info->proto_mask = 0;
6337 filter_info->proto =
6338 convert_protocol_type(filter->proto);
6341 filter_info->proto_mask = 1;
6344 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6348 filter_info->priority = (uint8_t)filter->priority;
6353 * add or delete a ntuple filter
6356 * dev: Pointer to struct rte_eth_dev.
6357 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6358 * add: if true, add filter, if false, remove filter
6361 * - On success, zero.
6362 * - On failure, a negative value.
6365 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6366 struct rte_eth_ntuple_filter *ntuple_filter,
6369 struct ixgbe_filter_info *filter_info =
6370 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6371 struct ixgbe_5tuple_filter_info filter_5tuple;
6372 struct ixgbe_5tuple_filter *filter;
6375 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6376 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6380 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6381 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6385 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6387 if (filter != NULL && add) {
6388 PMD_DRV_LOG(ERR, "filter exists.");
6391 if (filter == NULL && !add) {
6392 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6397 filter = rte_zmalloc("ixgbe_5tuple_filter",
6398 sizeof(struct ixgbe_5tuple_filter), 0);
6401 rte_memcpy(&filter->filter_info,
6403 sizeof(struct ixgbe_5tuple_filter_info));
6404 filter->queue = ntuple_filter->queue;
6405 ret = ixgbe_add_5tuple_filter(dev, filter);
6411 ixgbe_remove_5tuple_filter(dev, filter);
6417 * get a ntuple filter
6420 * dev: Pointer to struct rte_eth_dev.
6421 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6424 * - On success, zero.
6425 * - On failure, a negative value.
6428 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6429 struct rte_eth_ntuple_filter *ntuple_filter)
6431 struct ixgbe_filter_info *filter_info =
6432 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6433 struct ixgbe_5tuple_filter_info filter_5tuple;
6434 struct ixgbe_5tuple_filter *filter;
6437 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6438 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6442 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6443 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6447 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6449 if (filter == NULL) {
6450 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6453 ntuple_filter->queue = filter->queue;
6458 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6459 * @dev: pointer to rte_eth_dev structure
6460 * @filter_op:operation will be taken.
6461 * @arg: a pointer to specific structure corresponding to the filter_op
6464 * - On success, zero.
6465 * - On failure, a negative value.
6468 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6469 enum rte_filter_op filter_op,
6472 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6475 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6477 if (filter_op == RTE_ETH_FILTER_NOP)
6481 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6486 switch (filter_op) {
6487 case RTE_ETH_FILTER_ADD:
6488 ret = ixgbe_add_del_ntuple_filter(dev,
6489 (struct rte_eth_ntuple_filter *)arg,
6492 case RTE_ETH_FILTER_DELETE:
6493 ret = ixgbe_add_del_ntuple_filter(dev,
6494 (struct rte_eth_ntuple_filter *)arg,
6497 case RTE_ETH_FILTER_GET:
6498 ret = ixgbe_get_ntuple_filter(dev,
6499 (struct rte_eth_ntuple_filter *)arg);
6502 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6510 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6511 struct rte_eth_ethertype_filter *filter,
6514 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6515 struct ixgbe_filter_info *filter_info =
6516 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6520 struct ixgbe_ethertype_filter ethertype_filter;
6522 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6525 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6526 filter->ether_type == ETHER_TYPE_IPv6) {
6527 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6528 " ethertype filter.", filter->ether_type);
6532 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6533 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6536 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6537 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6541 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6542 if (ret >= 0 && add) {
6543 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6544 filter->ether_type);
6547 if (ret < 0 && !add) {
6548 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6549 filter->ether_type);
6554 etqf = IXGBE_ETQF_FILTER_EN;
6555 etqf |= (uint32_t)filter->ether_type;
6556 etqs |= (uint32_t)((filter->queue <<
6557 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6558 IXGBE_ETQS_RX_QUEUE);
6559 etqs |= IXGBE_ETQS_QUEUE_EN;
6561 ethertype_filter.ethertype = filter->ether_type;
6562 ethertype_filter.etqf = etqf;
6563 ethertype_filter.etqs = etqs;
6564 ethertype_filter.conf = FALSE;
6565 ret = ixgbe_ethertype_filter_insert(filter_info,
6568 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6572 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6576 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6577 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6578 IXGBE_WRITE_FLUSH(hw);
6584 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6585 struct rte_eth_ethertype_filter *filter)
6587 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6588 struct ixgbe_filter_info *filter_info =
6589 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6590 uint32_t etqf, etqs;
6593 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6595 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6596 filter->ether_type);
6600 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6601 if (etqf & IXGBE_ETQF_FILTER_EN) {
6602 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6603 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6605 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6606 IXGBE_ETQS_RX_QUEUE_SHIFT;
6613 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6614 * @dev: pointer to rte_eth_dev structure
6615 * @filter_op:operation will be taken.
6616 * @arg: a pointer to specific structure corresponding to the filter_op
6619 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6620 enum rte_filter_op filter_op,
6623 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6626 MAC_TYPE_FILTER_SUP(hw->mac.type);
6628 if (filter_op == RTE_ETH_FILTER_NOP)
6632 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6637 switch (filter_op) {
6638 case RTE_ETH_FILTER_ADD:
6639 ret = ixgbe_add_del_ethertype_filter(dev,
6640 (struct rte_eth_ethertype_filter *)arg,
6643 case RTE_ETH_FILTER_DELETE:
6644 ret = ixgbe_add_del_ethertype_filter(dev,
6645 (struct rte_eth_ethertype_filter *)arg,
6648 case RTE_ETH_FILTER_GET:
6649 ret = ixgbe_get_ethertype_filter(dev,
6650 (struct rte_eth_ethertype_filter *)arg);
6653 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6661 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6662 enum rte_filter_type filter_type,
6663 enum rte_filter_op filter_op,
6668 switch (filter_type) {
6669 case RTE_ETH_FILTER_NTUPLE:
6670 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6672 case RTE_ETH_FILTER_ETHERTYPE:
6673 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6675 case RTE_ETH_FILTER_SYN:
6676 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6678 case RTE_ETH_FILTER_FDIR:
6679 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6681 case RTE_ETH_FILTER_L2_TUNNEL:
6682 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6684 case RTE_ETH_FILTER_GENERIC:
6685 if (filter_op != RTE_ETH_FILTER_GET)
6687 *(const void **)arg = &ixgbe_flow_ops;
6690 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6700 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6701 u8 **mc_addr_ptr, u32 *vmdq)
6706 mc_addr = *mc_addr_ptr;
6707 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6712 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6713 struct ether_addr *mc_addr_set,
6714 uint32_t nb_mc_addr)
6716 struct ixgbe_hw *hw;
6719 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6720 mc_addr_list = (u8 *)mc_addr_set;
6721 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6722 ixgbe_dev_addr_list_itr, TRUE);
6726 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6728 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6729 uint64_t systime_cycles;
6731 switch (hw->mac.type) {
6732 case ixgbe_mac_X550:
6733 case ixgbe_mac_X550EM_x:
6734 case ixgbe_mac_X550EM_a:
6735 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6736 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6737 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6741 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6742 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6746 return systime_cycles;
6750 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6752 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6753 uint64_t rx_tstamp_cycles;
6755 switch (hw->mac.type) {
6756 case ixgbe_mac_X550:
6757 case ixgbe_mac_X550EM_x:
6758 case ixgbe_mac_X550EM_a:
6759 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6760 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6761 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6765 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6766 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6767 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6771 return rx_tstamp_cycles;
6775 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6777 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6778 uint64_t tx_tstamp_cycles;
6780 switch (hw->mac.type) {
6781 case ixgbe_mac_X550:
6782 case ixgbe_mac_X550EM_x:
6783 case ixgbe_mac_X550EM_a:
6784 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6785 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6786 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6790 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6791 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6792 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6796 return tx_tstamp_cycles;
6800 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6802 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6803 struct ixgbe_adapter *adapter =
6804 (struct ixgbe_adapter *)dev->data->dev_private;
6805 struct rte_eth_link link;
6806 uint32_t incval = 0;
6809 /* Get current link speed. */
6810 memset(&link, 0, sizeof(link));
6811 ixgbe_dev_link_update(dev, 1);
6812 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6814 switch (link.link_speed) {
6815 case ETH_SPEED_NUM_100M:
6816 incval = IXGBE_INCVAL_100;
6817 shift = IXGBE_INCVAL_SHIFT_100;
6819 case ETH_SPEED_NUM_1G:
6820 incval = IXGBE_INCVAL_1GB;
6821 shift = IXGBE_INCVAL_SHIFT_1GB;
6823 case ETH_SPEED_NUM_10G:
6825 incval = IXGBE_INCVAL_10GB;
6826 shift = IXGBE_INCVAL_SHIFT_10GB;
6830 switch (hw->mac.type) {
6831 case ixgbe_mac_X550:
6832 case ixgbe_mac_X550EM_x:
6833 case ixgbe_mac_X550EM_a:
6834 /* Independent of link speed. */
6836 /* Cycles read will be interpreted as ns. */
6839 case ixgbe_mac_X540:
6840 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6842 case ixgbe_mac_82599EB:
6843 incval >>= IXGBE_INCVAL_SHIFT_82599;
6844 shift -= IXGBE_INCVAL_SHIFT_82599;
6845 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6846 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6849 /* Not supported. */
6853 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6854 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6855 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6857 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6858 adapter->systime_tc.cc_shift = shift;
6859 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6861 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6862 adapter->rx_tstamp_tc.cc_shift = shift;
6863 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6865 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6866 adapter->tx_tstamp_tc.cc_shift = shift;
6867 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6871 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6873 struct ixgbe_adapter *adapter =
6874 (struct ixgbe_adapter *)dev->data->dev_private;
6876 adapter->systime_tc.nsec += delta;
6877 adapter->rx_tstamp_tc.nsec += delta;
6878 adapter->tx_tstamp_tc.nsec += delta;
6884 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6887 struct ixgbe_adapter *adapter =
6888 (struct ixgbe_adapter *)dev->data->dev_private;
6890 ns = rte_timespec_to_ns(ts);
6891 /* Set the timecounters to a new value. */
6892 adapter->systime_tc.nsec = ns;
6893 adapter->rx_tstamp_tc.nsec = ns;
6894 adapter->tx_tstamp_tc.nsec = ns;
6900 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6902 uint64_t ns, systime_cycles;
6903 struct ixgbe_adapter *adapter =
6904 (struct ixgbe_adapter *)dev->data->dev_private;
6906 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6907 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6908 *ts = rte_ns_to_timespec(ns);
6914 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6916 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6920 /* Stop the timesync system time. */
6921 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6922 /* Reset the timesync system time value. */
6923 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6924 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6926 /* Enable system time for platforms where it isn't on by default. */
6927 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6928 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6929 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6931 ixgbe_start_timecounters(dev);
6933 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6934 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6936 IXGBE_ETQF_FILTER_EN |
6939 /* Enable timestamping of received PTP packets. */
6940 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6941 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6942 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6944 /* Enable timestamping of transmitted PTP packets. */
6945 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6946 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6947 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6949 IXGBE_WRITE_FLUSH(hw);
6955 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6957 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6960 /* Disable timestamping of transmitted PTP packets. */
6961 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6962 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6963 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6965 /* Disable timestamping of received PTP packets. */
6966 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6967 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6968 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6970 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6971 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6973 /* Stop incrementating the System Time registers. */
6974 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6980 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6981 struct timespec *timestamp,
6982 uint32_t flags __rte_unused)
6984 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6985 struct ixgbe_adapter *adapter =
6986 (struct ixgbe_adapter *)dev->data->dev_private;
6987 uint32_t tsync_rxctl;
6988 uint64_t rx_tstamp_cycles;
6991 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6992 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6995 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6996 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6997 *timestamp = rte_ns_to_timespec(ns);
7003 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7004 struct timespec *timestamp)
7006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7007 struct ixgbe_adapter *adapter =
7008 (struct ixgbe_adapter *)dev->data->dev_private;
7009 uint32_t tsync_txctl;
7010 uint64_t tx_tstamp_cycles;
7013 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7014 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7017 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7018 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7019 *timestamp = rte_ns_to_timespec(ns);
7025 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7030 const struct reg_info *reg_group;
7031 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7032 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7034 while ((reg_group = reg_set[g_ind++]))
7035 count += ixgbe_regs_group_count(reg_group);
7041 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7045 const struct reg_info *reg_group;
7047 while ((reg_group = ixgbevf_regs[g_ind++]))
7048 count += ixgbe_regs_group_count(reg_group);
7054 ixgbe_get_regs(struct rte_eth_dev *dev,
7055 struct rte_dev_reg_info *regs)
7057 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7058 uint32_t *data = regs->data;
7061 const struct reg_info *reg_group;
7062 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7063 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7066 regs->length = ixgbe_get_reg_length(dev);
7067 regs->width = sizeof(uint32_t);
7071 /* Support only full register dump */
7072 if ((regs->length == 0) ||
7073 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7074 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7076 while ((reg_group = reg_set[g_ind++]))
7077 count += ixgbe_read_regs_group(dev, &data[count],
7086 ixgbevf_get_regs(struct rte_eth_dev *dev,
7087 struct rte_dev_reg_info *regs)
7089 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7090 uint32_t *data = regs->data;
7093 const struct reg_info *reg_group;
7096 regs->length = ixgbevf_get_reg_length(dev);
7097 regs->width = sizeof(uint32_t);
7101 /* Support only full register dump */
7102 if ((regs->length == 0) ||
7103 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7104 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7106 while ((reg_group = ixgbevf_regs[g_ind++]))
7107 count += ixgbe_read_regs_group(dev, &data[count],
7116 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7120 /* Return unit is byte count */
7121 return hw->eeprom.word_size * 2;
7125 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7126 struct rte_dev_eeprom_info *in_eeprom)
7128 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7129 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7130 uint16_t *data = in_eeprom->data;
7133 first = in_eeprom->offset >> 1;
7134 length = in_eeprom->length >> 1;
7135 if ((first > hw->eeprom.word_size) ||
7136 ((first + length) > hw->eeprom.word_size))
7139 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7141 return eeprom->ops.read_buffer(hw, first, length, data);
7145 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7146 struct rte_dev_eeprom_info *in_eeprom)
7148 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7149 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7150 uint16_t *data = in_eeprom->data;
7153 first = in_eeprom->offset >> 1;
7154 length = in_eeprom->length >> 1;
7155 if ((first > hw->eeprom.word_size) ||
7156 ((first + length) > hw->eeprom.word_size))
7159 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7161 return eeprom->ops.write_buffer(hw, first, length, data);
7165 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7167 case ixgbe_mac_X550:
7168 case ixgbe_mac_X550EM_x:
7169 case ixgbe_mac_X550EM_a:
7170 return ETH_RSS_RETA_SIZE_512;
7171 case ixgbe_mac_X550_vf:
7172 case ixgbe_mac_X550EM_x_vf:
7173 case ixgbe_mac_X550EM_a_vf:
7174 return ETH_RSS_RETA_SIZE_64;
7176 return ETH_RSS_RETA_SIZE_128;
7181 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7183 case ixgbe_mac_X550:
7184 case ixgbe_mac_X550EM_x:
7185 case ixgbe_mac_X550EM_a:
7186 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7187 return IXGBE_RETA(reta_idx >> 2);
7189 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7190 case ixgbe_mac_X550_vf:
7191 case ixgbe_mac_X550EM_x_vf:
7192 case ixgbe_mac_X550EM_a_vf:
7193 return IXGBE_VFRETA(reta_idx >> 2);
7195 return IXGBE_RETA(reta_idx >> 2);
7200 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7202 case ixgbe_mac_X550_vf:
7203 case ixgbe_mac_X550EM_x_vf:
7204 case ixgbe_mac_X550EM_a_vf:
7205 return IXGBE_VFMRQC;
7212 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7214 case ixgbe_mac_X550_vf:
7215 case ixgbe_mac_X550EM_x_vf:
7216 case ixgbe_mac_X550EM_a_vf:
7217 return IXGBE_VFRSSRK(i);
7219 return IXGBE_RSSRK(i);
7224 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7226 case ixgbe_mac_82599_vf:
7227 case ixgbe_mac_X540_vf:
7235 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7236 struct rte_eth_dcb_info *dcb_info)
7238 struct ixgbe_dcb_config *dcb_config =
7239 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7240 struct ixgbe_dcb_tc_config *tc;
7241 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7245 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7246 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7248 dcb_info->nb_tcs = 1;
7250 tc_queue = &dcb_info->tc_queue;
7251 nb_tcs = dcb_info->nb_tcs;
7253 if (dcb_config->vt_mode) { /* vt is enabled*/
7254 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7255 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7256 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7257 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7258 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7259 for (j = 0; j < nb_tcs; j++) {
7260 tc_queue->tc_rxq[0][j].base = j;
7261 tc_queue->tc_rxq[0][j].nb_queue = 1;
7262 tc_queue->tc_txq[0][j].base = j;
7263 tc_queue->tc_txq[0][j].nb_queue = 1;
7266 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7267 for (j = 0; j < nb_tcs; j++) {
7268 tc_queue->tc_rxq[i][j].base =
7270 tc_queue->tc_rxq[i][j].nb_queue = 1;
7271 tc_queue->tc_txq[i][j].base =
7273 tc_queue->tc_txq[i][j].nb_queue = 1;
7277 } else { /* vt is disabled*/
7278 struct rte_eth_dcb_rx_conf *rx_conf =
7279 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7280 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7281 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7282 if (dcb_info->nb_tcs == ETH_4_TCS) {
7283 for (i = 0; i < dcb_info->nb_tcs; i++) {
7284 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7285 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7287 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7288 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7289 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7290 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7291 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7292 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7293 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7294 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7295 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7296 for (i = 0; i < dcb_info->nb_tcs; i++) {
7297 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7298 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7300 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7301 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7302 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7303 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7304 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7305 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7306 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7307 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7308 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7309 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7310 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7311 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7312 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7313 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7314 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7315 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7318 for (i = 0; i < dcb_info->nb_tcs; i++) {
7319 tc = &dcb_config->tc_config[i];
7320 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7325 /* Update e-tag ether type */
7327 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7328 uint16_t ether_type)
7330 uint32_t etag_etype;
7332 if (hw->mac.type != ixgbe_mac_X550 &&
7333 hw->mac.type != ixgbe_mac_X550EM_x &&
7334 hw->mac.type != ixgbe_mac_X550EM_a) {
7338 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7339 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7340 etag_etype |= ether_type;
7341 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7342 IXGBE_WRITE_FLUSH(hw);
7347 /* Config l2 tunnel ether type */
7349 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7350 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7353 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7354 struct ixgbe_l2_tn_info *l2_tn_info =
7355 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7357 if (l2_tunnel == NULL)
7360 switch (l2_tunnel->l2_tunnel_type) {
7361 case RTE_L2_TUNNEL_TYPE_E_TAG:
7362 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7363 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7366 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7374 /* Enable e-tag tunnel */
7376 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7378 uint32_t etag_etype;
7380 if (hw->mac.type != ixgbe_mac_X550 &&
7381 hw->mac.type != ixgbe_mac_X550EM_x &&
7382 hw->mac.type != ixgbe_mac_X550EM_a) {
7386 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7387 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7388 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7389 IXGBE_WRITE_FLUSH(hw);
7394 /* Enable l2 tunnel */
7396 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7397 enum rte_eth_tunnel_type l2_tunnel_type)
7400 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7401 struct ixgbe_l2_tn_info *l2_tn_info =
7402 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7404 switch (l2_tunnel_type) {
7405 case RTE_L2_TUNNEL_TYPE_E_TAG:
7406 l2_tn_info->e_tag_en = TRUE;
7407 ret = ixgbe_e_tag_enable(hw);
7410 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7418 /* Disable e-tag tunnel */
7420 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7422 uint32_t etag_etype;
7424 if (hw->mac.type != ixgbe_mac_X550 &&
7425 hw->mac.type != ixgbe_mac_X550EM_x &&
7426 hw->mac.type != ixgbe_mac_X550EM_a) {
7430 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7431 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7432 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7433 IXGBE_WRITE_FLUSH(hw);
7438 /* Disable l2 tunnel */
7440 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7441 enum rte_eth_tunnel_type l2_tunnel_type)
7444 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7445 struct ixgbe_l2_tn_info *l2_tn_info =
7446 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7448 switch (l2_tunnel_type) {
7449 case RTE_L2_TUNNEL_TYPE_E_TAG:
7450 l2_tn_info->e_tag_en = FALSE;
7451 ret = ixgbe_e_tag_disable(hw);
7454 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7463 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7464 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7467 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7468 uint32_t i, rar_entries;
7469 uint32_t rar_low, rar_high;
7471 if (hw->mac.type != ixgbe_mac_X550 &&
7472 hw->mac.type != ixgbe_mac_X550EM_x &&
7473 hw->mac.type != ixgbe_mac_X550EM_a) {
7477 rar_entries = ixgbe_get_num_rx_addrs(hw);
7479 for (i = 1; i < rar_entries; i++) {
7480 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7481 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7482 if ((rar_high & IXGBE_RAH_AV) &&
7483 (rar_high & IXGBE_RAH_ADTYPE) &&
7484 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7485 l2_tunnel->tunnel_id)) {
7486 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7487 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7489 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7499 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7500 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7503 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7504 uint32_t i, rar_entries;
7505 uint32_t rar_low, rar_high;
7507 if (hw->mac.type != ixgbe_mac_X550 &&
7508 hw->mac.type != ixgbe_mac_X550EM_x &&
7509 hw->mac.type != ixgbe_mac_X550EM_a) {
7513 /* One entry for one tunnel. Try to remove potential existing entry. */
7514 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7516 rar_entries = ixgbe_get_num_rx_addrs(hw);
7518 for (i = 1; i < rar_entries; i++) {
7519 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7520 if (rar_high & IXGBE_RAH_AV) {
7523 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7524 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7525 rar_low = l2_tunnel->tunnel_id;
7527 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7528 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7534 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7535 " Please remove a rule before adding a new one.");
7539 static inline struct ixgbe_l2_tn_filter *
7540 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7541 struct ixgbe_l2_tn_key *key)
7545 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7549 return l2_tn_info->hash_map[ret];
7553 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7554 struct ixgbe_l2_tn_filter *l2_tn_filter)
7558 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7559 &l2_tn_filter->key);
7563 "Failed to insert L2 tunnel filter"
7564 " to hash table %d!",
7569 l2_tn_info->hash_map[ret] = l2_tn_filter;
7571 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7577 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7578 struct ixgbe_l2_tn_key *key)
7581 struct ixgbe_l2_tn_filter *l2_tn_filter;
7583 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7587 "No such L2 tunnel filter to delete %d!",
7592 l2_tn_filter = l2_tn_info->hash_map[ret];
7593 l2_tn_info->hash_map[ret] = NULL;
7595 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7596 rte_free(l2_tn_filter);
7601 /* Add l2 tunnel filter */
7603 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7604 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7608 struct ixgbe_l2_tn_info *l2_tn_info =
7609 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7610 struct ixgbe_l2_tn_key key;
7611 struct ixgbe_l2_tn_filter *node;
7614 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7615 key.tn_id = l2_tunnel->tunnel_id;
7617 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7621 "The L2 tunnel filter already exists!");
7625 node = rte_zmalloc("ixgbe_l2_tn",
7626 sizeof(struct ixgbe_l2_tn_filter),
7631 rte_memcpy(&node->key,
7633 sizeof(struct ixgbe_l2_tn_key));
7634 node->pool = l2_tunnel->pool;
7635 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7642 switch (l2_tunnel->l2_tunnel_type) {
7643 case RTE_L2_TUNNEL_TYPE_E_TAG:
7644 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7647 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7652 if ((!restore) && (ret < 0))
7653 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7658 /* Delete l2 tunnel filter */
7660 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7661 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7664 struct ixgbe_l2_tn_info *l2_tn_info =
7665 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7666 struct ixgbe_l2_tn_key key;
7668 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7669 key.tn_id = l2_tunnel->tunnel_id;
7670 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7674 switch (l2_tunnel->l2_tunnel_type) {
7675 case RTE_L2_TUNNEL_TYPE_E_TAG:
7676 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7679 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7688 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7689 * @dev: pointer to rte_eth_dev structure
7690 * @filter_op:operation will be taken.
7691 * @arg: a pointer to specific structure corresponding to the filter_op
7694 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7695 enum rte_filter_op filter_op,
7700 if (filter_op == RTE_ETH_FILTER_NOP)
7704 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7709 switch (filter_op) {
7710 case RTE_ETH_FILTER_ADD:
7711 ret = ixgbe_dev_l2_tunnel_filter_add
7713 (struct rte_eth_l2_tunnel_conf *)arg,
7716 case RTE_ETH_FILTER_DELETE:
7717 ret = ixgbe_dev_l2_tunnel_filter_del
7719 (struct rte_eth_l2_tunnel_conf *)arg);
7722 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7730 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7734 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7736 if (hw->mac.type != ixgbe_mac_X550 &&
7737 hw->mac.type != ixgbe_mac_X550EM_x &&
7738 hw->mac.type != ixgbe_mac_X550EM_a) {
7742 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7743 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7745 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7746 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7751 /* Enable l2 tunnel forwarding */
7753 ixgbe_dev_l2_tunnel_forwarding_enable
7754 (struct rte_eth_dev *dev,
7755 enum rte_eth_tunnel_type l2_tunnel_type)
7757 struct ixgbe_l2_tn_info *l2_tn_info =
7758 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7761 switch (l2_tunnel_type) {
7762 case RTE_L2_TUNNEL_TYPE_E_TAG:
7763 l2_tn_info->e_tag_fwd_en = TRUE;
7764 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7767 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7775 /* Disable l2 tunnel forwarding */
7777 ixgbe_dev_l2_tunnel_forwarding_disable
7778 (struct rte_eth_dev *dev,
7779 enum rte_eth_tunnel_type l2_tunnel_type)
7781 struct ixgbe_l2_tn_info *l2_tn_info =
7782 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7785 switch (l2_tunnel_type) {
7786 case RTE_L2_TUNNEL_TYPE_E_TAG:
7787 l2_tn_info->e_tag_fwd_en = FALSE;
7788 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7791 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7800 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7801 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7804 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7806 uint32_t vmtir, vmvir;
7807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7809 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7811 "VF id %u should be less than %u",
7817 if (hw->mac.type != ixgbe_mac_X550 &&
7818 hw->mac.type != ixgbe_mac_X550EM_x &&
7819 hw->mac.type != ixgbe_mac_X550EM_a) {
7824 vmtir = l2_tunnel->tunnel_id;
7828 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7830 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7831 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7833 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7834 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7839 /* Enable l2 tunnel tag insertion */
7841 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7842 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7846 switch (l2_tunnel->l2_tunnel_type) {
7847 case RTE_L2_TUNNEL_TYPE_E_TAG:
7848 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7851 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7859 /* Disable l2 tunnel tag insertion */
7861 ixgbe_dev_l2_tunnel_insertion_disable
7862 (struct rte_eth_dev *dev,
7863 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7867 switch (l2_tunnel->l2_tunnel_type) {
7868 case RTE_L2_TUNNEL_TYPE_E_TAG:
7869 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7872 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7881 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7886 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7888 if (hw->mac.type != ixgbe_mac_X550 &&
7889 hw->mac.type != ixgbe_mac_X550EM_x &&
7890 hw->mac.type != ixgbe_mac_X550EM_a) {
7894 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7896 qde |= IXGBE_QDE_STRIP_TAG;
7898 qde &= ~IXGBE_QDE_STRIP_TAG;
7899 qde &= ~IXGBE_QDE_READ;
7900 qde |= IXGBE_QDE_WRITE;
7901 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7906 /* Enable l2 tunnel tag stripping */
7908 ixgbe_dev_l2_tunnel_stripping_enable
7909 (struct rte_eth_dev *dev,
7910 enum rte_eth_tunnel_type l2_tunnel_type)
7914 switch (l2_tunnel_type) {
7915 case RTE_L2_TUNNEL_TYPE_E_TAG:
7916 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7919 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7927 /* Disable l2 tunnel tag stripping */
7929 ixgbe_dev_l2_tunnel_stripping_disable
7930 (struct rte_eth_dev *dev,
7931 enum rte_eth_tunnel_type l2_tunnel_type)
7935 switch (l2_tunnel_type) {
7936 case RTE_L2_TUNNEL_TYPE_E_TAG:
7937 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7940 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7948 /* Enable/disable l2 tunnel offload functions */
7950 ixgbe_dev_l2_tunnel_offload_set
7951 (struct rte_eth_dev *dev,
7952 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7958 if (l2_tunnel == NULL)
7962 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7964 ret = ixgbe_dev_l2_tunnel_enable(
7966 l2_tunnel->l2_tunnel_type);
7968 ret = ixgbe_dev_l2_tunnel_disable(
7970 l2_tunnel->l2_tunnel_type);
7973 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7975 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7979 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7984 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7986 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7988 l2_tunnel->l2_tunnel_type);
7990 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7992 l2_tunnel->l2_tunnel_type);
7995 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7997 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7999 l2_tunnel->l2_tunnel_type);
8001 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8003 l2_tunnel->l2_tunnel_type);
8010 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8013 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8014 IXGBE_WRITE_FLUSH(hw);
8019 /* There's only one register for VxLAN UDP port.
8020 * So, we cannot add several ports. Will update it.
8023 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8027 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8031 return ixgbe_update_vxlan_port(hw, port);
8034 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8035 * UDP port, it must have a value.
8036 * So, will reset it to the original value 0.
8039 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8044 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8046 if (cur_port != port) {
8047 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8051 return ixgbe_update_vxlan_port(hw, 0);
8054 /* Add UDP tunneling port */
8056 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8057 struct rte_eth_udp_tunnel *udp_tunnel)
8060 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8062 if (hw->mac.type != ixgbe_mac_X550 &&
8063 hw->mac.type != ixgbe_mac_X550EM_x &&
8064 hw->mac.type != ixgbe_mac_X550EM_a) {
8068 if (udp_tunnel == NULL)
8071 switch (udp_tunnel->prot_type) {
8072 case RTE_TUNNEL_TYPE_VXLAN:
8073 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8076 case RTE_TUNNEL_TYPE_GENEVE:
8077 case RTE_TUNNEL_TYPE_TEREDO:
8078 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8083 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8091 /* Remove UDP tunneling port */
8093 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8094 struct rte_eth_udp_tunnel *udp_tunnel)
8097 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8099 if (hw->mac.type != ixgbe_mac_X550 &&
8100 hw->mac.type != ixgbe_mac_X550EM_x &&
8101 hw->mac.type != ixgbe_mac_X550EM_a) {
8105 if (udp_tunnel == NULL)
8108 switch (udp_tunnel->prot_type) {
8109 case RTE_TUNNEL_TYPE_VXLAN:
8110 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8112 case RTE_TUNNEL_TYPE_GENEVE:
8113 case RTE_TUNNEL_TYPE_TEREDO:
8114 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8118 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8127 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8129 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8131 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8135 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8137 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8139 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8142 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8144 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8147 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8150 /* PF reset VF event */
8151 if (in_msg == IXGBE_PF_CONTROL_MSG)
8152 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8157 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8160 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8161 struct ixgbe_interrupt *intr =
8162 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8163 ixgbevf_intr_disable(hw);
8165 /* read-on-clear nic registers here */
8166 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8169 /* only one misc vector supported - mailbox */
8170 eicr &= IXGBE_VTEICR_MASK;
8171 if (eicr == IXGBE_MISC_VEC_ID)
8172 intr->flags |= IXGBE_FLAG_MAILBOX;
8178 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8180 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8181 struct ixgbe_interrupt *intr =
8182 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8184 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8185 ixgbevf_mbx_process(dev);
8186 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8189 ixgbevf_intr_enable(hw);
8195 ixgbevf_dev_interrupt_handler(void *param)
8197 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8199 ixgbevf_dev_interrupt_get_status(dev);
8200 ixgbevf_dev_interrupt_action(dev);
8204 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8205 * @hw: pointer to hardware structure
8207 * Stops the transmit data path and waits for the HW to internally empty
8208 * the Tx security block
8210 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8212 #define IXGBE_MAX_SECTX_POLL 40
8217 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8218 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8219 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8220 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8221 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8222 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8224 /* Use interrupt-safe sleep just in case */
8228 /* For informational purposes only */
8229 if (i >= IXGBE_MAX_SECTX_POLL)
8230 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8231 "path fully disabled. Continuing with init.");
8233 return IXGBE_SUCCESS;
8237 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8238 * @hw: pointer to hardware structure
8240 * Enables the transmit data path.
8242 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8246 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8247 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8248 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8249 IXGBE_WRITE_FLUSH(hw);
8251 return IXGBE_SUCCESS;
8254 /* restore n-tuple filter */
8256 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8258 struct ixgbe_filter_info *filter_info =
8259 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8260 struct ixgbe_5tuple_filter *node;
8262 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8263 ixgbe_inject_5tuple_filter(dev, node);
8267 /* restore ethernet type filter */
8269 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8271 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8272 struct ixgbe_filter_info *filter_info =
8273 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8276 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8277 if (filter_info->ethertype_mask & (1 << i)) {
8278 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8279 filter_info->ethertype_filters[i].etqf);
8280 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8281 filter_info->ethertype_filters[i].etqs);
8282 IXGBE_WRITE_FLUSH(hw);
8287 /* restore SYN filter */
8289 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8291 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8292 struct ixgbe_filter_info *filter_info =
8293 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8296 synqf = filter_info->syn_info;
8298 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8299 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8300 IXGBE_WRITE_FLUSH(hw);
8304 /* restore L2 tunnel filter */
8306 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8308 struct ixgbe_l2_tn_info *l2_tn_info =
8309 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8310 struct ixgbe_l2_tn_filter *node;
8311 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8313 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8314 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8315 l2_tn_conf.tunnel_id = node->key.tn_id;
8316 l2_tn_conf.pool = node->pool;
8317 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8322 ixgbe_filter_restore(struct rte_eth_dev *dev)
8324 ixgbe_ntuple_filter_restore(dev);
8325 ixgbe_ethertype_filter_restore(dev);
8326 ixgbe_syn_filter_restore(dev);
8327 ixgbe_fdir_filter_restore(dev);
8328 ixgbe_l2_tn_filter_restore(dev);
8334 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8336 struct ixgbe_l2_tn_info *l2_tn_info =
8337 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8338 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8340 if (l2_tn_info->e_tag_en)
8341 (void)ixgbe_e_tag_enable(hw);
8343 if (l2_tn_info->e_tag_fwd_en)
8344 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8346 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8349 /* remove all the n-tuple filters */
8351 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8353 struct ixgbe_filter_info *filter_info =
8354 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8355 struct ixgbe_5tuple_filter *p_5tuple;
8357 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8358 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8361 /* remove all the ether type filters */
8363 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8365 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8366 struct ixgbe_filter_info *filter_info =
8367 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8370 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8371 if (filter_info->ethertype_mask & (1 << i) &&
8372 !filter_info->ethertype_filters[i].conf) {
8373 (void)ixgbe_ethertype_filter_remove(filter_info,
8375 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8376 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8377 IXGBE_WRITE_FLUSH(hw);
8382 /* remove the SYN filter */
8384 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8386 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8387 struct ixgbe_filter_info *filter_info =
8388 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8390 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8391 filter_info->syn_info = 0;
8393 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8394 IXGBE_WRITE_FLUSH(hw);
8398 /* remove all the L2 tunnel filters */
8400 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8402 struct ixgbe_l2_tn_info *l2_tn_info =
8403 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8404 struct ixgbe_l2_tn_filter *l2_tn_filter;
8405 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8408 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8409 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8410 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8411 l2_tn_conf.pool = l2_tn_filter->pool;
8412 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8420 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8421 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8422 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8423 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8424 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8425 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");