drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Timer value included in XOFF frames. */
  89 #define IXGBE_FC_PAUSE 0x680
  90
  91 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  92 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  93 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  94
  95 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  96 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  97 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  98
  99 /*
 100  *  Default values for RX/TX configuration
 101  */
 102 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 103 #define IXGBE_DEFAULT_RX_PTHRESH      8
 104 #define IXGBE_DEFAULT_RX_HTHRESH      8
 105 #define IXGBE_DEFAULT_RX_WTHRESH      0
 106
 107 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_TX_PTHRESH      32
 109 #define IXGBE_DEFAULT_TX_HTHRESH      0
 110 #define IXGBE_DEFAULT_TX_WTHRESH      0
 111 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 112
 113 /* Bit shift and mask */
 114 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 115 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 116 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 117 #define IXGBE_8_BIT_MASK   UINT8_MAX
 118
 119 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 120
 121 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 122
 123 #define IXGBE_HKEY_MAX_INDEX 10
 124
 125 /* Additional timesync values. */
 126 #define IXGBE_TIMINCA_16NS_SHIFT 24
 127 #define IXGBE_TIMINCA_INCVALUE   16000000
 128 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 129                                   | IXGBE_TIMINCA_INCVALUE)
 130
 131 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 132 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 133 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 134 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 135 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 136 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 139 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 140 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 143 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 144                                 int wait_to_complete);
 145 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 146                                 struct rte_eth_stats *stats);
 147 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 148                                 struct rte_eth_xstats *xstats, unsigned n);
 149 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 152                                              uint16_t queue_id,
 153                                              uint8_t stat_idx,
 154                                              uint8_t is_rx);
 155 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 156                                struct rte_eth_dev_info *dev_info);
 157 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 158                                  struct rte_eth_dev_info *dev_info);
 159 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 160
 161 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 162                 uint16_t vlan_id, int on);
 163 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 164 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 165                 uint16_t queue, bool on);
 166 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 167                 int on);
 168 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 169 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 170 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 171 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 172 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 173
 174 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 176 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_fc_conf *fc_conf);
 178 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 179                                struct rte_eth_fc_conf *fc_conf);
 180 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 181                 struct rte_eth_pfc_conf *pfc_conf);
 182 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 183                         struct rte_eth_rss_reta_entry64 *reta_conf,
 184                         uint16_t reta_size);
 185 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 186                         struct rte_eth_rss_reta_entry64 *reta_conf,
 187                         uint16_t reta_size);
 188 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 189 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 190 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 191 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 192 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 193                 void *param);
 194 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 195 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 196                 uint32_t index, uint32_t pool);
 197 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 198 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 199                                            struct ether_addr *mac_addr);
 200 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 201
 202 /* For Virtual Function support */
 203 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 204 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 205 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 206 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 207 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 208 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 209 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 210 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 211                 struct rte_eth_stats *stats);
 212 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 213 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 214                 uint16_t vlan_id, int on);
 215 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 216                 uint16_t queue, int on);
 217 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 218 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 219
 220 /* For Eth VMDQ APIs support */
 221 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 222                 ether_addr* mac_addr,uint8_t on);
 223 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 224 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 225                 uint16_t rx_mask, uint8_t on);
 226 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 227 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 228 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 229                 uint64_t pool_mask,uint8_t vlan_on);
 230 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 231                 struct rte_eth_mirror_conf *mirror_conf,
 232                 uint8_t rule_id, uint8_t on);
 233 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 234                 uint8_t rule_id);
 235
 236 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 237                 uint16_t queue_idx, uint16_t tx_rate);
 238 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 239                 uint16_t tx_rate, uint64_t q_msk);
 240
 241 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 242                                  struct ether_addr *mac_addr,
 243                                  uint32_t index, uint32_t pool);
 244 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 245 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 246                                              struct ether_addr *mac_addr);
 247 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 248                         struct rte_eth_syn_filter *filter,
 249                         bool add);
 250 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 251                         struct rte_eth_syn_filter *filter);
 252 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 253                         enum rte_filter_op filter_op,
 254                         void *arg);
 255 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 256                         struct ixgbe_5tuple_filter *filter);
 257 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 258                         struct ixgbe_5tuple_filter *filter);
 259 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 260                         struct rte_eth_ntuple_filter *filter,
 261                         bool add);
 262 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 263                                 enum rte_filter_op filter_op,
 264                                 void *arg);
 265 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 266                         struct rte_eth_ntuple_filter *filter);
 267 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 268                         struct rte_eth_ethertype_filter *filter,
 269                         bool add);
 270 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 271                                 enum rte_filter_op filter_op,
 272                                 void *arg);
 273 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 274                         struct rte_eth_ethertype_filter *filter);
 275 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 276                      enum rte_filter_type filter_type,
 277                      enum rte_filter_op filter_op,
 278                      void *arg);
 279 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 280
 281 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 282                                       struct ether_addr *mc_addr_set,
 283                                       uint32_t nb_mc_addr);
 284
 285 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 286 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 287                             struct rte_dev_reg_info *regs);
 288 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 289 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 290                                 struct rte_dev_eeprom_info *eeprom);
 291 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 292                                 struct rte_dev_eeprom_info *eeprom);
 293
 294 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 295 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 296                                 struct rte_dev_reg_info *regs);
 297
 298 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 299 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 300 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 301                                             struct timespec *timestamp,
 302                                             uint32_t flags);
 303 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 304                                             struct timespec *timestamp);
 305
 306 /*
 307  * Define VF Stats MACRO for Non "cleared on read" register
 308  */
 309 #define UPDATE_VF_STAT(reg, last, cur)                          \
 310 {                                                               \
 311         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 312         cur += latest - last;                                   \
 313         last = latest;                                          \
 314 }
 315
 316 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 317 {                                                                \
 318         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 319         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 320         u64 latest = ((new_msb << 32) | new_lsb);                \
 321         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 322         last = latest;                                           \
 323 }
 324
 325 #define IXGBE_SET_HWSTRIP(h, q) do{\
 326                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 327                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 328                 (h)->bitmap[idx] |= 1 << bit;\
 329         }while(0)
 330
 331 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 332                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 333                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 334                 (h)->bitmap[idx] &= ~(1 << bit);\
 335         }while(0)
 336
 337 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 338                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 339                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 340                 (r) = (h)->bitmap[idx] >> bit & 1;\
 341         }while(0)
 342
 343 /*
 344  * The set of PCI devices this driver supports
 345  */
 346 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 347
 348 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 349 #include "rte_pci_dev_ids.h"
 350
 351 { .vendor_id = 0, /* sentinel */ },
 352 };
 353
 354
 355 /*
 356  * The set of PCI devices this driver supports (for 82599 VF)
 357  */
 358 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 359
 360 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 361 #include "rte_pci_dev_ids.h"
 362 { .vendor_id = 0, /* sentinel */ },
 363
 364 };
 365
 366 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 367         .dev_configure        = ixgbe_dev_configure,
 368         .dev_start            = ixgbe_dev_start,
 369         .dev_stop             = ixgbe_dev_stop,
 370         .dev_set_link_up    = ixgbe_dev_set_link_up,
 371         .dev_set_link_down  = ixgbe_dev_set_link_down,
 372         .dev_close            = ixgbe_dev_close,
 373         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 374         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 375         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 376         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 377         .link_update          = ixgbe_dev_link_update,
 378         .stats_get            = ixgbe_dev_stats_get,
 379         .xstats_get           = ixgbe_dev_xstats_get,
 380         .stats_reset          = ixgbe_dev_stats_reset,
 381         .xstats_reset         = ixgbe_dev_xstats_reset,
 382         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 383         .dev_infos_get        = ixgbe_dev_info_get,
 384         .mtu_set              = ixgbe_dev_mtu_set,
 385         .vlan_filter_set      = ixgbe_vlan_filter_set,
 386         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 387         .vlan_offload_set     = ixgbe_vlan_offload_set,
 388         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 389         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 390         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 391         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 392         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 393         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 394         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 395         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 396         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 397         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 398         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 399         .dev_led_on           = ixgbe_dev_led_on,
 400         .dev_led_off          = ixgbe_dev_led_off,
 401         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 402         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 403         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 404         .mac_addr_add         = ixgbe_add_rar,
 405         .mac_addr_remove      = ixgbe_remove_rar,
 406         .mac_addr_set         = ixgbe_set_default_mac_addr,
 407         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 408         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 409         .mirror_rule_set      = ixgbe_mirror_rule_set,
 410         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 411         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 412         .set_vf_rx            = ixgbe_set_pool_rx,
 413         .set_vf_tx            = ixgbe_set_pool_tx,
 414         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 415         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 416         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 417         .reta_update          = ixgbe_dev_rss_reta_update,
 418         .reta_query           = ixgbe_dev_rss_reta_query,
 419 #ifdef RTE_NIC_BYPASS
 420         .bypass_init          = ixgbe_bypass_init,
 421         .bypass_state_set     = ixgbe_bypass_state_store,
 422         .bypass_state_show    = ixgbe_bypass_state_show,
 423         .bypass_event_set     = ixgbe_bypass_event_store,
 424         .bypass_event_show    = ixgbe_bypass_event_show,
 425         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 426         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 427         .bypass_ver_show      = ixgbe_bypass_ver_show,
 428         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 429 #endif /* RTE_NIC_BYPASS */
 430         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 431         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 432         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 433         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 434         .timesync_enable      = ixgbe_timesync_enable,
 435         .timesync_disable     = ixgbe_timesync_disable,
 436         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 437         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 438         .get_reg_length       = ixgbe_get_reg_length,
 439         .get_reg              = ixgbe_get_regs,
 440         .get_eeprom_length    = ixgbe_get_eeprom_length,
 441         .get_eeprom           = ixgbe_get_eeprom,
 442         .set_eeprom           = ixgbe_set_eeprom,
 443 };
 444
 445 /*
 446  * dev_ops for virtual function, bare necessities for basic vf
 447  * operation have been implemented
 448  */
 449 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 450         .dev_configure        = ixgbevf_dev_configure,
 451         .dev_start            = ixgbevf_dev_start,
 452         .dev_stop             = ixgbevf_dev_stop,
 453         .link_update          = ixgbe_dev_link_update,
 454         .stats_get            = ixgbevf_dev_stats_get,
 455         .stats_reset          = ixgbevf_dev_stats_reset,
 456         .dev_close            = ixgbevf_dev_close,
 457         .dev_infos_get        = ixgbevf_dev_info_get,
 458         .mtu_set              = ixgbevf_dev_set_mtu,
 459         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 460         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 461         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 462         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 463         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 464         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 465         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 466         .mac_addr_add         = ixgbevf_add_mac_addr,
 467         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 468         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 469         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 470         .get_reg_length       = ixgbevf_get_reg_length,
 471         .get_reg              = ixgbevf_get_regs,
 472 };
 473
 474 /* store statistics names and its offset in stats structure */
 475 struct rte_ixgbe_xstats_name_off {
 476         char name[RTE_ETH_XSTATS_NAME_SIZE];
 477         unsigned offset;
 478 };
 479
 480 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 481         {"rx_illegal_byte_err", offsetof(struct ixgbe_hw_stats, errbc)},
 482         {"rx_len_err", offsetof(struct ixgbe_hw_stats, rlec)},
 483         {"rx_undersize_count", offsetof(struct ixgbe_hw_stats, ruc)},
 484         {"rx_oversize_count", offsetof(struct ixgbe_hw_stats, roc)},
 485         {"rx_fragment_count", offsetof(struct ixgbe_hw_stats, rfc)},
 486         {"rx_jabber_count", offsetof(struct ixgbe_hw_stats, rjc)},
 487         {"l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 488         {"mac_local_fault", offsetof(struct ixgbe_hw_stats, mlfc)},
 489         {"mac_remote_fault", offsetof(struct ixgbe_hw_stats, mrfc)},
 490         {"mac_short_pkt_discard", offsetof(struct ixgbe_hw_stats, mspdc)},
 491         {"fccrc_error", offsetof(struct ixgbe_hw_stats, fccrc)},
 492         {"fcoe_drop", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 493         {"fc_last_error", offsetof(struct ixgbe_hw_stats, fclast)},
 494         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 495         {"rx_phy_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 496         {"mgmt_pkts_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 497         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 498         {"fdir_match", offsetof(struct ixgbe_hw_stats, fdirmatch)},
 499         {"fdir_miss", offsetof(struct ixgbe_hw_stats, fdirmiss)},
 500         {"tx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxontxc)},
 501         {"rx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 502         {"tx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 503         {"rx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 504 };
 505
 506 #define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) /      \
 507                 sizeof(rte_ixgbe_stats_strings[0]))
 508
 509 /**
 510  * Atomically reads the link status information from global
 511  * structure rte_eth_dev.
 512  *
 513  * @param dev
 514  *   - Pointer to the structure rte_eth_dev to read from.
 515  *   - Pointer to the buffer to be saved with the link status.
 516  *
 517  * @return
 518  *   - On success, zero.
 519  *   - On failure, negative value.
 520  */
 521 static inline int
 522 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 523                                 struct rte_eth_link *link)
 524 {
 525         struct rte_eth_link *dst = link;
 526         struct rte_eth_link *src = &(dev->data->dev_link);
 527
 528         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 529                                         *(uint64_t *)src) == 0)
 530                 return -1;
 531
 532         return 0;
 533 }
 534
 535 /**
 536  * Atomically writes the link status information into global
 537  * structure rte_eth_dev.
 538  *
 539  * @param dev
 540  *   - Pointer to the structure rte_eth_dev to read from.
 541  *   - Pointer to the buffer to be saved with the link status.
 542  *
 543  * @return
 544  *   - On success, zero.
 545  *   - On failure, negative value.
 546  */
 547 static inline int
 548 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 549                                 struct rte_eth_link *link)
 550 {
 551         struct rte_eth_link *dst = &(dev->data->dev_link);
 552         struct rte_eth_link *src = link;
 553
 554         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 555                                         *(uint64_t *)src) == 0)
 556                 return -1;
 557
 558         return 0;
 559 }
 560
 561 /*
 562  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 563  */
 564 static inline int
 565 ixgbe_is_sfp(struct ixgbe_hw *hw)
 566 {
 567         switch (hw->phy.type) {
 568         case ixgbe_phy_sfp_avago:
 569         case ixgbe_phy_sfp_ftl:
 570         case ixgbe_phy_sfp_intel:
 571         case ixgbe_phy_sfp_unknown:
 572         case ixgbe_phy_sfp_passive_tyco:
 573         case ixgbe_phy_sfp_passive_unknown:
 574                 return 1;
 575         default:
 576                 return 0;
 577         }
 578 }
 579
 580 static inline int32_t
 581 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 582 {
 583         uint32_t ctrl_ext;
 584         int32_t status;
 585
 586         status = ixgbe_reset_hw(hw);
 587
 588         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 589         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 590         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 591         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 592         IXGBE_WRITE_FLUSH(hw);
 593
 594         return status;
 595 }
 596
 597 static inline void
 598 ixgbe_enable_intr(struct rte_eth_dev *dev)
 599 {
 600         struct ixgbe_interrupt *intr =
 601                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 602         struct ixgbe_hw *hw =
 603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 604
 605         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 606         IXGBE_WRITE_FLUSH(hw);
 607 }
 608
 609 /*
 610  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 611  */
 612 static void
 613 ixgbe_disable_intr(struct ixgbe_hw *hw)
 614 {
 615         PMD_INIT_FUNC_TRACE();
 616
 617         if (hw->mac.type == ixgbe_mac_82598EB) {
 618                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 619         } else {
 620                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 621                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 622                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 623         }
 624         IXGBE_WRITE_FLUSH(hw);
 625 }
 626
 627 /*
 628  * This function resets queue statistics mapping registers.
 629  * From Niantic datasheet, Initialization of Statistics section:
 630  * "...if software requires the queue counters, the RQSMR and TQSM registers
 631  * must be re-programmed following a device reset.
 632  */
 633 static void
 634 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 635 {
 636         uint32_t i;
 637
 638         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 639                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 640                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 641         }
 642 }
 643
 644
 645 static int
 646 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 647                                   uint16_t queue_id,
 648                                   uint8_t stat_idx,
 649                                   uint8_t is_rx)
 650 {
 651 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 652 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 653 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 654
 655         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 656         struct ixgbe_stat_mapping_registers *stat_mappings =
 657                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 658         uint32_t qsmr_mask = 0;
 659         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 660         uint32_t q_map;
 661         uint8_t n, offset;
 662
 663         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 664                 (hw->mac.type != ixgbe_mac_X540) &&
 665                 (hw->mac.type != ixgbe_mac_X550) &&
 666                 (hw->mac.type != ixgbe_mac_X550EM_x))
 667                 return -ENOSYS;
 668
 669         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 670                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 671                      queue_id, stat_idx);
 672
 673         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 674         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 675                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 676                 return -EIO;
 677         }
 678         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 679
 680         /* Now clear any previous stat_idx set */
 681         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 682         if (!is_rx)
 683                 stat_mappings->tqsm[n] &= ~clearing_mask;
 684         else
 685                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 686
 687         q_map = (uint32_t)stat_idx;
 688         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 689         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 690         if (!is_rx)
 691                 stat_mappings->tqsm[n] |= qsmr_mask;
 692         else
 693                 stat_mappings->rqsmr[n] |= qsmr_mask;
 694
 695         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 696                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 697                      queue_id, stat_idx);
 698         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 699                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 700
 701         /* Now write the mapping in the appropriate register */
 702         if (is_rx) {
 703                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 704                              stat_mappings->rqsmr[n], n);
 705                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 706         }
 707         else {
 708                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 709                              stat_mappings->tqsm[n], n);
 710                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 711         }
 712         return 0;
 713 }
 714
 715 static void
 716 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 717 {
 718         struct ixgbe_stat_mapping_registers *stat_mappings =
 719                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 721         int i;
 722
 723         /* write whatever was in stat mapping table to the NIC */
 724         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 725                 /* rx */
 726                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 727
 728                 /* tx */
 729                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 730         }
 731 }
 732
 733 static void
 734 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 735 {
 736         uint8_t i;
 737         struct ixgbe_dcb_tc_config *tc;
 738         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 739
 740         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 741         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 742         for (i = 0; i < dcb_max_tc; i++) {
 743                 tc = &dcb_config->tc_config[i];
 744                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 745                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 746                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 747                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 748                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 749                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 750                 tc->pfc = ixgbe_dcb_pfc_disabled;
 751         }
 752
 753         /* Initialize default user to priority mapping, UPx->TC0 */
 754         tc = &dcb_config->tc_config[0];
 755         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 756         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 757         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 758                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 759                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 760         }
 761         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 762         dcb_config->pfc_mode_enable = false;
 763         dcb_config->vt_mode = true;
 764         dcb_config->round_robin_enable = false;
 765         /* support all DCB capabilities in 82599 */
 766         dcb_config->support.capabilities = 0xFF;
 767
 768         /*we only support 4 Tcs for X540, X550 */
 769         if (hw->mac.type == ixgbe_mac_X540 ||
 770                 hw->mac.type == ixgbe_mac_X550 ||
 771                 hw->mac.type == ixgbe_mac_X550EM_x) {
 772                 dcb_config->num_tcs.pg_tcs = 4;
 773                 dcb_config->num_tcs.pfc_tcs = 4;
 774         }
 775 }
 776
 777 /*
 778  * Ensure that all locks are released before first NVM or PHY access
 779  */
 780 static void
 781 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 782 {
 783         uint16_t mask;
 784
 785         /*
 786          * Phy lock should not fail in this early stage. If this is the case,
 787          * it is due to an improper exit of the application.
 788          * So force the release of the faulty lock. Release of common lock
 789          * is done automatically by swfw_sync function.
 790          */
 791         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 792         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 793                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 794         }
 795         ixgbe_release_swfw_semaphore(hw, mask);
 796
 797         /*
 798          * These ones are more tricky since they are common to all ports; but
 799          * swfw_sync retries last long enough (1s) to be almost sure that if
 800          * lock can not be taken it is due to an improper lock of the
 801          * semaphore.
 802          */
 803         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 804         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 805                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 806         }
 807         ixgbe_release_swfw_semaphore(hw, mask);
 808 }
 809
 810 /*
 811  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 812  * It returns 0 on success.
 813  */
 814 static int
 815 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 816 {
 817         struct rte_pci_device *pci_dev;
 818         struct ixgbe_hw *hw =
 819                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 820         struct ixgbe_vfta * shadow_vfta =
 821                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 822         struct ixgbe_hwstrip *hwstrip =
 823                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 824         struct ixgbe_dcb_config *dcb_config =
 825                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 826         struct ixgbe_filter_info *filter_info =
 827                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 828         uint32_t ctrl_ext;
 829         uint16_t csum;
 830         int diag, i;
 831
 832         PMD_INIT_FUNC_TRACE();
 833
 834         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 835         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 836         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 837
 838         /*
 839          * For secondary processes, we don't initialise any further as primary
 840          * has already done this work. Only check we don't need a different
 841          * RX and TX function.
 842          */
 843         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 844                 struct ixgbe_tx_queue *txq;
 845                 /* TX queue function in primary, set by last queue initialized
 846                  * Tx queue may not initialized by primary process */
 847                 if (eth_dev->data->tx_queues) {
 848                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 849                         ixgbe_set_tx_function(eth_dev, txq);
 850                 } else {
 851                         /* Use default TX function if we get here */
 852                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 853                                            "Using default TX function.");
 854                 }
 855
 856                 ixgbe_set_rx_function(eth_dev);
 857
 858                 return 0;
 859         }
 860         pci_dev = eth_dev->pci_dev;
 861
 862         /* Vendor and Device ID need to be set before init of shared code */
 863         hw->device_id = pci_dev->id.device_id;
 864         hw->vendor_id = pci_dev->id.vendor_id;
 865         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 866         hw->allow_unsupported_sfp = 1;
 867
 868         /* Initialize the shared code (base driver) */
 869 #ifdef RTE_NIC_BYPASS
 870         diag = ixgbe_bypass_init_shared_code(hw);
 871 #else
 872         diag = ixgbe_init_shared_code(hw);
 873 #endif /* RTE_NIC_BYPASS */
 874
 875         if (diag != IXGBE_SUCCESS) {
 876                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 877                 return -EIO;
 878         }
 879
 880         /* pick up the PCI bus settings for reporting later */
 881         ixgbe_get_bus_info(hw);
 882
 883         /* Unlock any pending hardware semaphore */
 884         ixgbe_swfw_lock_reset(hw);
 885
 886         /* Initialize DCB configuration*/
 887         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 888         ixgbe_dcb_init(hw,dcb_config);
 889         /* Get Hardware Flow Control setting */
 890         hw->fc.requested_mode = ixgbe_fc_full;
 891         hw->fc.current_mode = ixgbe_fc_full;
 892         hw->fc.pause_time = IXGBE_FC_PAUSE;
 893         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 894                 hw->fc.low_water[i] = IXGBE_FC_LO;
 895                 hw->fc.high_water[i] = IXGBE_FC_HI;
 896         }
 897         hw->fc.send_xon = 1;
 898
 899         /* Make sure we have a good EEPROM before we read from it */
 900         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 901         if (diag != IXGBE_SUCCESS) {
 902                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 903                 return -EIO;
 904         }
 905
 906 #ifdef RTE_NIC_BYPASS
 907         diag = ixgbe_bypass_init_hw(hw);
 908 #else
 909         diag = ixgbe_init_hw(hw);
 910 #endif /* RTE_NIC_BYPASS */
 911
 912         /*
 913          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 914          * is called too soon after the kernel driver unbinding/binding occurs.
 915          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 916          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 917          * also called. See ixgbe_identify_phy_82599(). The reason for the
 918          * failure is not known, and only occuts when virtualisation features
 919          * are disabled in the bios. A delay of 100ms  was found to be enough by
 920          * trial-and-error, and is doubled to be safe.
 921          */
 922         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 923                 rte_delay_ms(200);
 924                 diag = ixgbe_init_hw(hw);
 925         }
 926
 927         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 928                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 929                     "LOM.  Please be aware there may be issues associated "
 930                     "with your hardware.");
 931                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 932                     "please contact your Intel or hardware representative "
 933                     "who provided you with this hardware.");
 934         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 935                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 936         if (diag) {
 937                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 938                 return -EIO;
 939         }
 940
 941         /* Reset the hw statistics */
 942         ixgbe_dev_stats_reset(eth_dev);
 943
 944         /* disable interrupt */
 945         ixgbe_disable_intr(hw);
 946
 947         /* reset mappings for queue statistics hw counters*/
 948         ixgbe_reset_qstat_mappings(hw);
 949
 950         /* Allocate memory for storing MAC addresses */
 951         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 952                         hw->mac.num_rar_entries, 0);
 953         if (eth_dev->data->mac_addrs == NULL) {
 954                 PMD_INIT_LOG(ERR,
 955                         "Failed to allocate %u bytes needed to store "
 956                         "MAC addresses",
 957                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 958                 return -ENOMEM;
 959         }
 960         /* Copy the permanent MAC address */
 961         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 962                         &eth_dev->data->mac_addrs[0]);
 963
 964         /* Allocate memory for storing hash filter MAC addresses */
 965         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 966                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 967         if (eth_dev->data->hash_mac_addrs == NULL) {
 968                 PMD_INIT_LOG(ERR,
 969                         "Failed to allocate %d bytes needed to store MAC addresses",
 970                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 971                 return -ENOMEM;
 972         }
 973
 974         /* initialize the vfta */
 975         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 976
 977         /* initialize the hw strip bitmap*/
 978         memset(hwstrip, 0, sizeof(*hwstrip));
 979
 980         /* initialize PF if max_vfs not zero */
 981         ixgbe_pf_host_init(eth_dev);
 982
 983         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 984         /* let hardware know driver is loaded */
 985         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 986         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 987         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 988         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 989         IXGBE_WRITE_FLUSH(hw);
 990
 991         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 992                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 993                              (int) hw->mac.type, (int) hw->phy.type,
 994                              (int) hw->phy.sfp_type);
 995         else
 996                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 997                              (int) hw->mac.type, (int) hw->phy.type);
 998
 999         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1000                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1001                         pci_dev->id.device_id);
1002
1003         rte_intr_callback_register(&(pci_dev->intr_handle),
1004                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1005
1006         /* enable uio intr after callback register */
1007         rte_intr_enable(&(pci_dev->intr_handle));
1008
1009         /* enable support intr */
1010         ixgbe_enable_intr(eth_dev);
1011
1012         /* initialize 5tuple filter list */
1013         TAILQ_INIT(&filter_info->fivetuple_list);
1014         memset(filter_info->fivetuple_mask, 0,
1015                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1016
1017         return 0;
1018 }
1019
1020 static int
1021 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1022 {
1023         struct rte_pci_device *pci_dev;
1024         struct ixgbe_hw *hw;
1025
1026         PMD_INIT_FUNC_TRACE();
1027
1028         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1029                 return -EPERM;
1030
1031         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1032         pci_dev = eth_dev->pci_dev;
1033
1034         if (hw->adapter_stopped == 0)
1035                 ixgbe_dev_close(eth_dev);
1036
1037         eth_dev->dev_ops = NULL;
1038         eth_dev->rx_pkt_burst = NULL;
1039         eth_dev->tx_pkt_burst = NULL;
1040
1041         /* Unlock any pending hardware semaphore */
1042         ixgbe_swfw_lock_reset(hw);
1043
1044         /* disable uio intr before callback unregister */
1045         rte_intr_disable(&(pci_dev->intr_handle));
1046         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1047                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1048
1049         /* uninitialize PF if max_vfs not zero */
1050         ixgbe_pf_host_uninit(eth_dev);
1051
1052         rte_free(eth_dev->data->mac_addrs);
1053         eth_dev->data->mac_addrs = NULL;
1054
1055         rte_free(eth_dev->data->hash_mac_addrs);
1056         eth_dev->data->hash_mac_addrs = NULL;
1057
1058         return 0;
1059 }
1060
1061 /*
1062  * Negotiate mailbox API version with the PF.
1063  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1064  * Then we try to negotiate starting with the most recent one.
1065  * If all negotiation attempts fail, then we will proceed with
1066  * the default one (ixgbe_mbox_api_10).
1067  */
1068 static void
1069 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1070 {
1071         int32_t i;
1072
1073         /* start with highest supported, proceed down */
1074         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1075                 ixgbe_mbox_api_11,
1076                 ixgbe_mbox_api_10,
1077         };
1078
1079         for (i = 0;
1080                         i != RTE_DIM(sup_ver) &&
1081                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1082                         i++)
1083                 ;
1084 }
1085
1086 static void
1087 generate_random_mac_addr(struct ether_addr *mac_addr)
1088 {
1089         uint64_t random;
1090
1091         /* Set Organizationally Unique Identifier (OUI) prefix. */
1092         mac_addr->addr_bytes[0] = 0x00;
1093         mac_addr->addr_bytes[1] = 0x09;
1094         mac_addr->addr_bytes[2] = 0xC0;
1095         /* Force indication of locally assigned MAC address. */
1096         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1097         /* Generate the last 3 bytes of the MAC address with a random number. */
1098         random = rte_rand();
1099         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1100 }
1101
1102 /*
1103  * Virtual Function device init
1104  */
1105 static int
1106 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1107 {
1108         int diag;
1109         uint32_t tc, tcs;
1110         struct rte_pci_device *pci_dev;
1111         struct ixgbe_hw *hw =
1112                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1113         struct ixgbe_vfta * shadow_vfta =
1114                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1115         struct ixgbe_hwstrip *hwstrip =
1116                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1117         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1118
1119         PMD_INIT_FUNC_TRACE();
1120
1121         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1122         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1123         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1124
1125         /* for secondary processes, we don't initialise any further as primary
1126          * has already done this work. Only check we don't need a different
1127          * RX function */
1128         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1129                 if (eth_dev->data->scattered_rx)
1130                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1131                 return 0;
1132         }
1133
1134         pci_dev = eth_dev->pci_dev;
1135
1136         hw->device_id = pci_dev->id.device_id;
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1139
1140         /* initialize the vfta */
1141         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1142
1143         /* initialize the hw strip bitmap*/
1144         memset(hwstrip, 0, sizeof(*hwstrip));
1145
1146         /* Initialize the shared code (base driver) */
1147         diag = ixgbe_init_shared_code(hw);
1148         if (diag != IXGBE_SUCCESS) {
1149                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1150                 return -EIO;
1151         }
1152
1153         /* init_mailbox_params */
1154         hw->mbx.ops.init_params(hw);
1155
1156         /* Reset the hw statistics */
1157         ixgbevf_dev_stats_reset(eth_dev);
1158
1159         /* Disable the interrupts for VF */
1160         ixgbevf_intr_disable(hw);
1161
1162         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1163         diag = hw->mac.ops.reset_hw(hw);
1164
1165         /*
1166          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1167          * the underlying PF driver has not assigned a MAC address to the VF.
1168          * In this case, assign a random MAC address.
1169          */
1170         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1171                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1172                 return (diag);
1173         }
1174
1175         /* negotiate mailbox API version to use with the PF. */
1176         ixgbevf_negotiate_api(hw);
1177
1178         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1179         ixgbevf_get_queues(hw, &tcs, &tc);
1180
1181         /* Allocate memory for storing MAC addresses */
1182         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1183                         hw->mac.num_rar_entries, 0);
1184         if (eth_dev->data->mac_addrs == NULL) {
1185                 PMD_INIT_LOG(ERR,
1186                         "Failed to allocate %u bytes needed to store "
1187                         "MAC addresses",
1188                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1189                 return -ENOMEM;
1190         }
1191
1192         /* Generate a random MAC address, if none was assigned by PF. */
1193         if (is_zero_ether_addr(perm_addr)) {
1194                 generate_random_mac_addr(perm_addr);
1195                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1196                 if (diag) {
1197                         rte_free(eth_dev->data->mac_addrs);
1198                         eth_dev->data->mac_addrs = NULL;
1199                         return diag;
1200                 }
1201                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1202                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1203                              "%02x:%02x:%02x:%02x:%02x:%02x",
1204                              perm_addr->addr_bytes[0],
1205                              perm_addr->addr_bytes[1],
1206                              perm_addr->addr_bytes[2],
1207                              perm_addr->addr_bytes[3],
1208                              perm_addr->addr_bytes[4],
1209                              perm_addr->addr_bytes[5]);
1210         }
1211
1212         /* Copy the permanent MAC address */
1213         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1214
1215         /* reset the hardware with the new settings */
1216         diag = hw->mac.ops.start_hw(hw);
1217         switch (diag) {
1218                 case  0:
1219                         break;
1220
1221                 default:
1222                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1223                         return (-EIO);
1224         }
1225
1226         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1227                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1228                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1229
1230         return 0;
1231 }
1232
1233 /* Virtual Function device uninit */
1234
1235 static int
1236 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1237 {
1238         struct ixgbe_hw *hw;
1239         unsigned i;
1240
1241         PMD_INIT_FUNC_TRACE();
1242
1243         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1244                 return -EPERM;
1245
1246         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1247
1248         if (hw->adapter_stopped == 0)
1249                 ixgbevf_dev_close(eth_dev);
1250
1251         eth_dev->dev_ops = NULL;
1252         eth_dev->rx_pkt_burst = NULL;
1253         eth_dev->tx_pkt_burst = NULL;
1254
1255         /* Disable the interrupts for VF */
1256         ixgbevf_intr_disable(hw);
1257
1258         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1259                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1260                 eth_dev->data->rx_queues[i] = NULL;
1261         }
1262         eth_dev->data->nb_rx_queues = 0;
1263
1264         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1265                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1266                 eth_dev->data->tx_queues[i] = NULL;
1267         }
1268         eth_dev->data->nb_tx_queues = 0;
1269
1270         rte_free(eth_dev->data->mac_addrs);
1271         eth_dev->data->mac_addrs = NULL;
1272
1273         return 0;
1274 }
1275
1276 static struct eth_driver rte_ixgbe_pmd = {
1277         .pci_drv = {
1278                 .name = "rte_ixgbe_pmd",
1279                 .id_table = pci_id_ixgbe_map,
1280                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1281                         RTE_PCI_DRV_DETACHABLE,
1282         },
1283         .eth_dev_init = eth_ixgbe_dev_init,
1284         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1285         .dev_private_size = sizeof(struct ixgbe_adapter),
1286 };
1287
1288 /*
1289  * virtual function driver struct
1290  */
1291 static struct eth_driver rte_ixgbevf_pmd = {
1292         .pci_drv = {
1293                 .name = "rte_ixgbevf_pmd",
1294                 .id_table = pci_id_ixgbevf_map,
1295                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1296         },
1297         .eth_dev_init = eth_ixgbevf_dev_init,
1298         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1299         .dev_private_size = sizeof(struct ixgbe_adapter),
1300 };
1301
1302 /*
1303  * Driver initialization routine.
1304  * Invoked once at EAL init time.
1305  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1306  */
1307 static int
1308 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1309 {
1310         PMD_INIT_FUNC_TRACE();
1311
1312         rte_eth_driver_register(&rte_ixgbe_pmd);
1313         return 0;
1314 }
1315
1316 /*
1317  * VF Driver initialization routine.
1318  * Invoked one at EAL init time.
1319  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1320  */
1321 static int
1322 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1323 {
1324         PMD_INIT_FUNC_TRACE();
1325
1326         rte_eth_driver_register(&rte_ixgbevf_pmd);
1327         return (0);
1328 }
1329
1330 static int
1331 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1332 {
1333         struct ixgbe_hw *hw =
1334                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1335         struct ixgbe_vfta * shadow_vfta =
1336                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1337         uint32_t vfta;
1338         uint32_t vid_idx;
1339         uint32_t vid_bit;
1340
1341         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1342         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1343         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1344         if (on)
1345                 vfta |= vid_bit;
1346         else
1347                 vfta &= ~vid_bit;
1348         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1349
1350         /* update local VFTA copy */
1351         shadow_vfta->vfta[vid_idx] = vfta;
1352
1353         return 0;
1354 }
1355
1356 static void
1357 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1358 {
1359         if (on)
1360                 ixgbe_vlan_hw_strip_enable(dev, queue);
1361         else
1362                 ixgbe_vlan_hw_strip_disable(dev, queue);
1363 }
1364
1365 static void
1366 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1367 {
1368         struct ixgbe_hw *hw =
1369                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370
1371         /* Only the high 16-bits is valid */
1372         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1373 }
1374
1375 void
1376 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1377 {
1378         struct ixgbe_hw *hw =
1379                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380         uint32_t vlnctrl;
1381
1382         PMD_INIT_FUNC_TRACE();
1383
1384         /* Filter Table Disable */
1385         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1386         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1387
1388         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1389 }
1390
1391 void
1392 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1393 {
1394         struct ixgbe_hw *hw =
1395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         struct ixgbe_vfta * shadow_vfta =
1397                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1398         uint32_t vlnctrl;
1399         uint16_t i;
1400
1401         PMD_INIT_FUNC_TRACE();
1402
1403         /* Filter Table Enable */
1404         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1405         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1406         vlnctrl |= IXGBE_VLNCTRL_VFE;
1407
1408         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1409
1410         /* write whatever is in local vfta copy */
1411         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1412                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1413 }
1414
1415 static void
1416 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1417 {
1418         struct ixgbe_hwstrip *hwstrip =
1419                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1420
1421         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1422                 return;
1423
1424         if (on)
1425                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1426         else
1427                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1428 }
1429
1430 static void
1431 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1432 {
1433         struct ixgbe_hw *hw =
1434                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1435         uint32_t ctrl;
1436
1437         PMD_INIT_FUNC_TRACE();
1438
1439         if (hw->mac.type == ixgbe_mac_82598EB) {
1440                 /* No queue level support */
1441                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1442                 return;
1443         }
1444         else {
1445                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1446                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1447                 ctrl &= ~IXGBE_RXDCTL_VME;
1448                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1449         }
1450         /* record those setting for HW strip per queue */
1451         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1452 }
1453
1454 static void
1455 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1456 {
1457         struct ixgbe_hw *hw =
1458                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459         uint32_t ctrl;
1460
1461         PMD_INIT_FUNC_TRACE();
1462
1463         if (hw->mac.type == ixgbe_mac_82598EB) {
1464                 /* No queue level supported */
1465                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1466                 return;
1467         }
1468         else {
1469                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1470                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1471                 ctrl |= IXGBE_RXDCTL_VME;
1472                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1473         }
1474         /* record those setting for HW strip per queue */
1475         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1476 }
1477
1478 void
1479 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1480 {
1481         struct ixgbe_hw *hw =
1482                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483         uint32_t ctrl;
1484         uint16_t i;
1485
1486         PMD_INIT_FUNC_TRACE();
1487
1488         if (hw->mac.type == ixgbe_mac_82598EB) {
1489                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1490                 ctrl &= ~IXGBE_VLNCTRL_VME;
1491                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1492         }
1493         else {
1494                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1495                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1496                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1497                         ctrl &= ~IXGBE_RXDCTL_VME;
1498                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1499
1500                         /* record those setting for HW strip per queue */
1501                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1502                 }
1503         }
1504 }
1505
1506 void
1507 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1508 {
1509         struct ixgbe_hw *hw =
1510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1511         uint32_t ctrl;
1512         uint16_t i;
1513
1514         PMD_INIT_FUNC_TRACE();
1515
1516         if (hw->mac.type == ixgbe_mac_82598EB) {
1517                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1518                 ctrl |= IXGBE_VLNCTRL_VME;
1519                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1520         }
1521         else {
1522                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1523                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1524                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1525                         ctrl |= IXGBE_RXDCTL_VME;
1526                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1527
1528                         /* record those setting for HW strip per queue */
1529                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1530                 }
1531         }
1532 }
1533
1534 static void
1535 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1536 {
1537         struct ixgbe_hw *hw =
1538                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1539         uint32_t ctrl;
1540
1541         PMD_INIT_FUNC_TRACE();
1542
1543         /* DMATXCTRL: Geric Double VLAN Disable */
1544         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1545         ctrl &= ~IXGBE_DMATXCTL_GDV;
1546         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1547
1548         /* CTRL_EXT: Global Double VLAN Disable */
1549         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1550         ctrl &= ~IXGBE_EXTENDED_VLAN;
1551         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1552
1553 }
1554
1555 static void
1556 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1557 {
1558         struct ixgbe_hw *hw =
1559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1560         uint32_t ctrl;
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         /* DMATXCTRL: Geric Double VLAN Enable */
1565         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1566         ctrl |= IXGBE_DMATXCTL_GDV;
1567         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1568
1569         /* CTRL_EXT: Global Double VLAN Enable */
1570         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1571         ctrl |= IXGBE_EXTENDED_VLAN;
1572         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1573
1574         /*
1575          * VET EXT field in the EXVET register = 0x8100 by default
1576          * So no need to change. Same to VT field of DMATXCTL register
1577          */
1578 }
1579
1580 static void
1581 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1582 {
1583         if(mask & ETH_VLAN_STRIP_MASK){
1584                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1585                         ixgbe_vlan_hw_strip_enable_all(dev);
1586                 else
1587                         ixgbe_vlan_hw_strip_disable_all(dev);
1588         }
1589
1590         if(mask & ETH_VLAN_FILTER_MASK){
1591                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1592                         ixgbe_vlan_hw_filter_enable(dev);
1593                 else
1594                         ixgbe_vlan_hw_filter_disable(dev);
1595         }
1596
1597         if(mask & ETH_VLAN_EXTEND_MASK){
1598                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1599                         ixgbe_vlan_hw_extend_enable(dev);
1600                 else
1601                         ixgbe_vlan_hw_extend_disable(dev);
1602         }
1603 }
1604
1605 static void
1606 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1607 {
1608         struct ixgbe_hw *hw =
1609                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1610         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1611         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1612         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1613         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1614 }
1615
1616 static int
1617 ixgbe_dev_configure(struct rte_eth_dev *dev)
1618 {
1619         struct ixgbe_interrupt *intr =
1620                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1621         struct ixgbe_adapter *adapter =
1622                 (struct ixgbe_adapter *)dev->data->dev_private;
1623
1624         PMD_INIT_FUNC_TRACE();
1625
1626         /* set flag to update link status after init */
1627         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1628
1629         /*
1630          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1631          * allocation or vector Rx preconditions we will reset it.
1632          */
1633         adapter->rx_bulk_alloc_allowed = true;
1634         adapter->rx_vec_allowed = true;
1635
1636         return 0;
1637 }
1638
1639 /*
1640  * Configure device link speed and setup link.
1641  * It returns 0 on success.
1642  */
1643 static int
1644 ixgbe_dev_start(struct rte_eth_dev *dev)
1645 {
1646         struct ixgbe_hw *hw =
1647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         struct ixgbe_vf_info *vfinfo =
1649                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1650         int err, link_up = 0, negotiate = 0;
1651         uint32_t speed = 0;
1652         int mask = 0;
1653         int status;
1654         uint16_t vf, idx;
1655
1656         PMD_INIT_FUNC_TRACE();
1657
1658         /* IXGBE devices don't support half duplex */
1659         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1660                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1661                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1662                              dev->data->dev_conf.link_duplex,
1663                              dev->data->port_id);
1664                 return -EINVAL;
1665         }
1666
1667         /* stop adapter */
1668         hw->adapter_stopped = 0;
1669         ixgbe_stop_adapter(hw);
1670
1671         /* reinitialize adapter
1672          * this calls reset and start */
1673         status = ixgbe_pf_reset_hw(hw);
1674         if (status != 0)
1675                 return -1;
1676         hw->mac.ops.start_hw(hw);
1677         hw->mac.get_link_status = true;
1678
1679         /* configure PF module if SRIOV enabled */
1680         ixgbe_pf_host_configure(dev);
1681
1682         /* initialize transmission unit */
1683         ixgbe_dev_tx_init(dev);
1684
1685         /* This can fail when allocating mbufs for descriptor rings */
1686         err = ixgbe_dev_rx_init(dev);
1687         if (err) {
1688                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1689                 goto error;
1690         }
1691
1692         err = ixgbe_dev_rxtx_start(dev);
1693         if (err < 0) {
1694                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1695                 goto error;
1696         }
1697
1698         /* Skip link setup if loopback mode is enabled for 82599. */
1699         if (hw->mac.type == ixgbe_mac_82599EB &&
1700                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1701                 goto skip_link_setup;
1702
1703         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1704                 err = hw->mac.ops.setup_sfp(hw);
1705                 if (err)
1706                         goto error;
1707         }
1708
1709         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1710                 /* Turn on the copper */
1711                 ixgbe_set_phy_power(hw, true);
1712         } else {
1713                 /* Turn on the laser */
1714                 ixgbe_enable_tx_laser(hw);
1715         }
1716
1717         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1718         if (err)
1719                 goto error;
1720         dev->data->dev_link.link_status = link_up;
1721
1722         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1723         if (err)
1724                 goto error;
1725
1726         switch(dev->data->dev_conf.link_speed) {
1727         case ETH_LINK_SPEED_AUTONEG:
1728                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1729                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1730                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1731                 break;
1732         case ETH_LINK_SPEED_100:
1733                 /*
1734                  * Invalid for 82598 but error will be detected by
1735                  * ixgbe_setup_link()
1736                  */
1737                 speed = IXGBE_LINK_SPEED_100_FULL;
1738                 break;
1739         case ETH_LINK_SPEED_1000:
1740                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1741                 break;
1742         case ETH_LINK_SPEED_10000:
1743                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1744                 break;
1745         default:
1746                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1747                              dev->data->dev_conf.link_speed,
1748                              dev->data->port_id);
1749                 goto error;
1750         }
1751
1752         err = ixgbe_setup_link(hw, speed, link_up);
1753         if (err)
1754                 goto error;
1755
1756 skip_link_setup:
1757
1758         /* check if lsc interrupt is enabled */
1759         if (dev->data->dev_conf.intr_conf.lsc != 0)
1760                 ixgbe_dev_lsc_interrupt_setup(dev);
1761
1762         /* resume enabled intr since hw reset */
1763         ixgbe_enable_intr(dev);
1764
1765         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1766                 ETH_VLAN_EXTEND_MASK;
1767         ixgbe_vlan_offload_set(dev, mask);
1768
1769         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1770                 /* Enable vlan filtering for VMDq */
1771                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1772         }
1773
1774         /* Configure DCB hw */
1775         ixgbe_configure_dcb(dev);
1776
1777         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1778                 err = ixgbe_fdir_configure(dev);
1779                 if (err)
1780                         goto error;
1781         }
1782
1783         /* Restore vf rate limit */
1784         if (vfinfo != NULL) {
1785                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1786                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1787                                 if (vfinfo[vf].tx_rate[idx] != 0)
1788                                         ixgbe_set_vf_rate_limit(dev, vf,
1789                                                 vfinfo[vf].tx_rate[idx],
1790                                                 1 << idx);
1791         }
1792
1793         ixgbe_restore_statistics_mapping(dev);
1794
1795         return (0);
1796
1797 error:
1798         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1799         ixgbe_dev_clear_queues(dev);
1800         return -EIO;
1801 }
1802
1803 /*
1804  * Stop device: disable rx and tx functions to allow for reconfiguring.
1805  */
1806 static void
1807 ixgbe_dev_stop(struct rte_eth_dev *dev)
1808 {
1809         struct rte_eth_link link;
1810         struct ixgbe_hw *hw =
1811                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812         struct ixgbe_vf_info *vfinfo =
1813                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1814         struct ixgbe_filter_info *filter_info =
1815                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1816         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1817         int vf;
1818
1819         PMD_INIT_FUNC_TRACE();
1820
1821         /* disable interrupts */
1822         ixgbe_disable_intr(hw);
1823
1824         /* reset the NIC */
1825         ixgbe_pf_reset_hw(hw);
1826         hw->adapter_stopped = 0;
1827
1828         /* stop adapter */
1829         ixgbe_stop_adapter(hw);
1830
1831         for (vf = 0; vfinfo != NULL &&
1832                      vf < dev->pci_dev->max_vfs; vf++)
1833                 vfinfo[vf].clear_to_send = false;
1834
1835         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1836                 /* Turn off the copper */
1837                 ixgbe_set_phy_power(hw, false);
1838         } else {
1839                 /* Turn off the laser */
1840                 ixgbe_disable_tx_laser(hw);
1841         }
1842
1843         ixgbe_dev_clear_queues(dev);
1844
1845         /* Clear stored conf */
1846         dev->data->scattered_rx = 0;
1847         dev->data->lro = 0;
1848
1849         /* Clear recorded link status */
1850         memset(&link, 0, sizeof(link));
1851         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1852
1853         /* Remove all ntuple filters of the device */
1854         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1855              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1856                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1857                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1858                              p_5tuple, entries);
1859                 rte_free(p_5tuple);
1860         }
1861         memset(filter_info->fivetuple_mask, 0,
1862                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1863
1864 }
1865
1866 /*
1867  * Set device link up: enable tx.
1868  */
1869 static int
1870 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1871 {
1872         struct ixgbe_hw *hw =
1873                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1874         if (hw->mac.type == ixgbe_mac_82599EB) {
1875 #ifdef RTE_NIC_BYPASS
1876                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1877                         /* Not suported in bypass mode */
1878                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1879                                      "by device id 0x%x", hw->device_id);
1880                         return -ENOTSUP;
1881                 }
1882 #endif
1883         }
1884
1885         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1886                 /* Turn on the copper */
1887                 ixgbe_set_phy_power(hw, true);
1888         } else {
1889                 /* Turn on the laser */
1890                 ixgbe_enable_tx_laser(hw);
1891         }
1892
1893         return 0;
1894 }
1895
1896 /*
1897  * Set device link down: disable tx.
1898  */
1899 static int
1900 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1901 {
1902         struct ixgbe_hw *hw =
1903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         if (hw->mac.type == ixgbe_mac_82599EB) {
1905 #ifdef RTE_NIC_BYPASS
1906                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1907                         /* Not suported in bypass mode */
1908                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1909                                      "by device id 0x%x", hw->device_id);
1910                         return -ENOTSUP;
1911                 }
1912 #endif
1913         }
1914
1915         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1916                 /* Turn off the copper */
1917                 ixgbe_set_phy_power(hw, false);
1918         } else {
1919                 /* Turn off the laser */
1920                 ixgbe_disable_tx_laser(hw);
1921         }
1922
1923         return 0;
1924 }
1925
1926 /*
1927  * Reest and stop device.
1928  */
1929 static void
1930 ixgbe_dev_close(struct rte_eth_dev *dev)
1931 {
1932         struct ixgbe_hw *hw =
1933                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934
1935         PMD_INIT_FUNC_TRACE();
1936
1937         ixgbe_pf_reset_hw(hw);
1938
1939         ixgbe_dev_stop(dev);
1940         hw->adapter_stopped = 1;
1941
1942         ixgbe_dev_free_queues(dev);
1943
1944         ixgbe_disable_pcie_master(hw);
1945
1946         /* reprogram the RAR[0] in case user changed it. */
1947         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1948 }
1949
1950 static void
1951 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
1952                                                    *hw_stats, uint64_t *total_missed_rx,
1953                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
1954                                                    uint64_t *rxnfgpc, uint64_t *txdgpc,
1955                                                    uint64_t *total_qprdc)
1956 {
1957         uint32_t bprc, lxon, lxoff, total;
1958         unsigned i;
1959
1960         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1961         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1962         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1963         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1964
1965         for (i = 0; i < 8; i++) {
1966                 uint32_t mp;
1967                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1968                 /* global total per queue */
1969                 hw_stats->mpc[i] += mp;
1970                 /* Running comprehensive total for stats display */
1971                 *total_missed_rx += hw_stats->mpc[i];
1972                 if (hw->mac.type == ixgbe_mac_82598EB)
1973                         hw_stats->rnbc[i] +=
1974                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1975                 hw_stats->pxontxc[i] +=
1976                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1977                 hw_stats->pxonrxc[i] +=
1978                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1979                 hw_stats->pxofftxc[i] +=
1980                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1981                 hw_stats->pxoffrxc[i] +=
1982                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1983                 hw_stats->pxon2offc[i] +=
1984                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1985         }
1986         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1987                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1988                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1989                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1990                 hw_stats->qbrc[i] +=
1991                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1992                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1993                 hw_stats->qbtc[i] +=
1994                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1995                 *total_qprdc += hw_stats->qprdc[i] +=
1996                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1997
1998                 *total_qprc += hw_stats->qprc[i];
1999                 *total_qbrc += hw_stats->qbrc[i];
2000         }
2001         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2002         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2003         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2004
2005         /* Note that gprc counts missed packets */
2006         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2007         *rxnfgpc += IXGBE_READ_REG(hw, IXGBE_RXNFGPC);
2008         *txdgpc += IXGBE_READ_REG(hw, IXGBE_TXDGPC);
2009
2010         if (hw->mac.type != ixgbe_mac_82598EB) {
2011                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2012                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2013                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2014                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2015                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2016                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2017                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2018                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2019         } else {
2020                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2021                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2022                 /* 82598 only has a counter in the high register */
2023                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2024                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2025                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2026         }
2027
2028         /*
2029          * Workaround: mprc hardware is incorrectly counting
2030          * broadcasts, so for now we subtract those.
2031          */
2032         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2033         hw_stats->bprc += bprc;
2034         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2035         if (hw->mac.type == ixgbe_mac_82598EB)
2036                 hw_stats->mprc -= bprc;
2037
2038         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2039         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2040         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2041         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2042         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2043         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2044
2045         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2046         hw_stats->lxontxc += lxon;
2047         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2048         hw_stats->lxofftxc += lxoff;
2049         total = lxon + lxoff;
2050
2051         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2052         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2053         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2054         hw_stats->gptc -= total;
2055         hw_stats->mptc -= total;
2056         hw_stats->ptc64 -= total;
2057         hw_stats->gotc -= total * ETHER_MIN_LEN;
2058
2059         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2060         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2061         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2062         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2063         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2064         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2065         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2066         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2067         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2068         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2069         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2070         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2071         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2072         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2073         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2074         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2075         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2076         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2077         /* Only read FCOE on 82599 */
2078         if (hw->mac.type != ixgbe_mac_82598EB) {
2079                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2080                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2081                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2082                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2083                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2084         }
2085
2086         /* Flow Director Stats registers */
2087         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2088         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2089 }
2090
2091 /*
2092  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2093  */
2094 static void
2095 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2096 {
2097         struct ixgbe_hw *hw =
2098                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2099         struct ixgbe_hw_stats *hw_stats =
2100                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2101         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2102         uint64_t rxnfgpc, txdgpc;
2103         unsigned i;
2104
2105         total_missed_rx = 0;
2106         total_qbrc = 0;
2107         total_qprc = 0;
2108         total_qprdc = 0;
2109         rxnfgpc = 0;
2110         txdgpc = 0;
2111
2112         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2113                         &total_qprc, &rxnfgpc, &txdgpc, &total_qprdc);
2114
2115         if (stats == NULL)
2116                 return;
2117
2118         /* Fill out the rte_eth_stats statistics structure */
2119         stats->ipackets = total_qprc;
2120         stats->ibytes = total_qbrc;
2121         stats->opackets = hw_stats->gptc;
2122         stats->obytes = hw_stats->gotc;
2123
2124         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2125                 stats->q_ipackets[i] = hw_stats->qprc[i];
2126                 stats->q_opackets[i] = hw_stats->qptc[i];
2127                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2128                 stats->q_obytes[i] = hw_stats->qbtc[i];
2129                 stats->q_errors[i] = hw_stats->qprdc[i];
2130         }
2131
2132         /* Rx Errors */
2133         stats->ierrors  = hw_stats->crcerrs +
2134                           hw_stats->rlec +
2135                           hw_stats->ruc +
2136                           hw_stats->roc +
2137                           total_missed_rx +
2138                           hw_stats->illerrc +
2139                           hw_stats->errbc +
2140                           hw_stats->xec +
2141                           hw_stats->mlfc +
2142                           hw_stats->mrfc +
2143                           hw_stats->rfc +
2144                           hw_stats->rjc +
2145                           hw_stats->fccrc +
2146                           hw_stats->fclast;
2147
2148         /* Tx Errors */
2149         /*txdgpc: packets that are DMA'ed*/
2150         /*gptc: packets that are sent*/
2151         stats->oerrors  = txdgpc - hw_stats->gptc;
2152 }
2153
2154 static void
2155 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2156 {
2157         struct ixgbe_hw_stats *stats =
2158                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2159
2160         /* HW registers are cleared on read */
2161         ixgbe_dev_stats_get(dev, NULL);
2162
2163         /* Reset software totals */
2164         memset(stats, 0, sizeof(*stats));
2165 }
2166
2167 static int
2168 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2169                                          unsigned n)
2170 {
2171         struct ixgbe_hw *hw =
2172                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         struct ixgbe_hw_stats *hw_stats =
2174                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2175         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2176         uint64_t rxnfgpc, txdgpc;
2177         unsigned i, count = IXGBE_NB_XSTATS;
2178
2179         if (n < count)
2180                 return count;
2181
2182         total_missed_rx = 0;
2183         total_qbrc = 0;
2184         total_qprc = 0;
2185         total_qprdc = 0;
2186         rxnfgpc = 0;
2187         txdgpc = 0;
2188
2189         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2190                                                            &total_qprc, &rxnfgpc, &txdgpc, &total_qprdc);
2191
2192         /* If this is a reset xstats is NULL, and we have cleared the
2193          * registers by reading them.
2194          */
2195         if (!xstats)
2196                 return 0;
2197
2198         /* Extended stats */
2199         for (i = 0; i < IXGBE_NB_XSTATS; i++) {
2200                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2201                                 "%s", rte_ixgbe_stats_strings[i].name);
2202                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2203                                                         rte_ixgbe_stats_strings[i].offset);
2204         }
2205
2206         return count;
2207 }
2208
2209 static void
2210 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2211 {
2212         struct ixgbe_hw_stats *stats =
2213                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2214
2215         /* HW registers are cleared on read */
2216         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2217
2218         /* Reset software totals */
2219         memset(stats, 0, sizeof(*stats));
2220 }
2221
2222 static void
2223 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2224 {
2225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2227                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2228
2229         /* Good Rx packet, include VF loopback */
2230         UPDATE_VF_STAT(IXGBE_VFGPRC,
2231             hw_stats->last_vfgprc, hw_stats->vfgprc);
2232
2233         /* Good Rx octets, include VF loopback */
2234         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2235             hw_stats->last_vfgorc, hw_stats->vfgorc);
2236
2237         /* Good Tx packet, include VF loopback */
2238         UPDATE_VF_STAT(IXGBE_VFGPTC,
2239             hw_stats->last_vfgptc, hw_stats->vfgptc);
2240
2241         /* Good Tx octets, include VF loopback */
2242         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2243             hw_stats->last_vfgotc, hw_stats->vfgotc);
2244
2245         /* Rx Multicst Packet */
2246         UPDATE_VF_STAT(IXGBE_VFMPRC,
2247             hw_stats->last_vfmprc, hw_stats->vfmprc);
2248
2249         if (stats == NULL)
2250                 return;
2251
2252         stats->ipackets = hw_stats->vfgprc;
2253         stats->ibytes = hw_stats->vfgorc;
2254         stats->opackets = hw_stats->vfgptc;
2255         stats->obytes = hw_stats->vfgotc;
2256         stats->imcasts = hw_stats->vfmprc;
2257         /* stats->imcasts should be removed as imcasts is deprecated */
2258 }
2259
2260 static void
2261 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2262 {
2263         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2264                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2265
2266         /* Sync HW register to the last stats */
2267         ixgbevf_dev_stats_get(dev, NULL);
2268
2269         /* reset HW current stats*/
2270         hw_stats->vfgprc = 0;
2271         hw_stats->vfgorc = 0;
2272         hw_stats->vfgptc = 0;
2273         hw_stats->vfgotc = 0;
2274         hw_stats->vfmprc = 0;
2275
2276 }
2277
2278 static void
2279 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2280 {
2281         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2282
2283         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2284         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2285         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2286         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2287         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2288         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2289         dev_info->max_vfs = dev->pci_dev->max_vfs;
2290         if (hw->mac.type == ixgbe_mac_82598EB)
2291                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2292         else
2293                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2294         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2295         dev_info->rx_offload_capa =
2296                 DEV_RX_OFFLOAD_VLAN_STRIP |
2297                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2298                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2299                 DEV_RX_OFFLOAD_TCP_CKSUM;
2300
2301         /*
2302          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2303          * mode.
2304          */
2305         if ((hw->mac.type == ixgbe_mac_82599EB ||
2306              hw->mac.type == ixgbe_mac_X540) &&
2307             !RTE_ETH_DEV_SRIOV(dev).active)
2308                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2309
2310         dev_info->tx_offload_capa =
2311                 DEV_TX_OFFLOAD_VLAN_INSERT |
2312                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2313                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2314                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2315                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2316                 DEV_TX_OFFLOAD_TCP_TSO;
2317
2318         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2319                 .rx_thresh = {
2320                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2321                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2322                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2323                 },
2324                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2325                 .rx_drop_en = 0,
2326         };
2327
2328         dev_info->default_txconf = (struct rte_eth_txconf) {
2329                 .tx_thresh = {
2330                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2331                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2332                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2333                 },
2334                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2335                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2336                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2337                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2338         };
2339         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2340         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2341         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2342 }
2343
2344 static void
2345 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2346                      struct rte_eth_dev_info *dev_info)
2347 {
2348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349
2350         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2351         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2352         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2353         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2354         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2355         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2356         dev_info->max_vfs = dev->pci_dev->max_vfs;
2357         if (hw->mac.type == ixgbe_mac_82598EB)
2358                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2359         else
2360                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2361         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2362                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2363                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2364                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2365         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2366                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2367                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2368                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2369                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2370
2371         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2372                 .rx_thresh = {
2373                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2374                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2375                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2376                 },
2377                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2378                 .rx_drop_en = 0,
2379         };
2380
2381         dev_info->default_txconf = (struct rte_eth_txconf) {
2382                 .tx_thresh = {
2383                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2384                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2385                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2386                 },
2387                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2388                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2389                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2390                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2391         };
2392 }
2393
2394 /* return 0 means link status changed, -1 means not changed */
2395 static int
2396 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2397 {
2398         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2399         struct rte_eth_link link, old;
2400         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2401         int link_up;
2402         int diag;
2403
2404         link.link_status = 0;
2405         link.link_speed = 0;
2406         link.link_duplex = 0;
2407         memset(&old, 0, sizeof(old));
2408         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2409
2410         hw->mac.get_link_status = true;
2411
2412         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2413         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2414                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2415         else
2416                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2417
2418         if (diag != 0) {
2419                 link.link_speed = ETH_LINK_SPEED_100;
2420                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2421                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2422                 if (link.link_status == old.link_status)
2423                         return -1;
2424                 return 0;
2425         }
2426
2427         if (link_up == 0) {
2428                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2429                 if (link.link_status == old.link_status)
2430                         return -1;
2431                 return 0;
2432         }
2433         link.link_status = 1;
2434         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2435
2436         switch (link_speed) {
2437         default:
2438         case IXGBE_LINK_SPEED_UNKNOWN:
2439                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2440                 link.link_speed = ETH_LINK_SPEED_100;
2441                 break;
2442
2443         case IXGBE_LINK_SPEED_100_FULL:
2444                 link.link_speed = ETH_LINK_SPEED_100;
2445                 break;
2446
2447         case IXGBE_LINK_SPEED_1GB_FULL:
2448                 link.link_speed = ETH_LINK_SPEED_1000;
2449                 break;
2450
2451         case IXGBE_LINK_SPEED_10GB_FULL:
2452                 link.link_speed = ETH_LINK_SPEED_10000;
2453                 break;
2454         }
2455         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2456
2457         if (link.link_status == old.link_status)
2458                 return -1;
2459
2460         return 0;
2461 }
2462
2463 static void
2464 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2465 {
2466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2467         uint32_t fctrl;
2468
2469         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2470         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2471         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2472 }
2473
2474 static void
2475 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2476 {
2477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2478         uint32_t fctrl;
2479
2480         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2481         fctrl &= (~IXGBE_FCTRL_UPE);
2482         if (dev->data->all_multicast == 1)
2483                 fctrl |= IXGBE_FCTRL_MPE;
2484         else
2485                 fctrl &= (~IXGBE_FCTRL_MPE);
2486         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2487 }
2488
2489 static void
2490 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2491 {
2492         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493         uint32_t fctrl;
2494
2495         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2496         fctrl |= IXGBE_FCTRL_MPE;
2497         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2498 }
2499
2500 static void
2501 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2502 {
2503         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2504         uint32_t fctrl;
2505
2506         if (dev->data->promiscuous == 1)
2507                 return; /* must remain in all_multicast mode */
2508
2509         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2510         fctrl &= (~IXGBE_FCTRL_MPE);
2511         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2512 }
2513
2514 /**
2515  * It clears the interrupt causes and enables the interrupt.
2516  * It will be called once only during nic initialized.
2517  *
2518  * @param dev
2519  *  Pointer to struct rte_eth_dev.
2520  *
2521  * @return
2522  *  - On success, zero.
2523  *  - On failure, a negative value.
2524  */
2525 static int
2526 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2527 {
2528         struct ixgbe_interrupt *intr =
2529                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2530
2531         ixgbe_dev_link_status_print(dev);
2532         intr->mask |= IXGBE_EICR_LSC;
2533
2534         return 0;
2535 }
2536
2537 /*
2538  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2539  *
2540  * @param dev
2541  *  Pointer to struct rte_eth_dev.
2542  *
2543  * @return
2544  *  - On success, zero.
2545  *  - On failure, a negative value.
2546  */
2547 static int
2548 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2549 {
2550         uint32_t eicr;
2551         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2552         struct ixgbe_interrupt *intr =
2553                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2554
2555         /* clear all cause mask */
2556         ixgbe_disable_intr(hw);
2557
2558         /* read-on-clear nic registers here */
2559         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2560         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2561
2562         intr->flags = 0;
2563         if (eicr & IXGBE_EICR_LSC) {
2564                 /* set flag for async link update */
2565                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2566         }
2567
2568         if (eicr & IXGBE_EICR_MAILBOX)
2569                 intr->flags |= IXGBE_FLAG_MAILBOX;
2570
2571         return 0;
2572 }
2573
2574 /**
2575  * It gets and then prints the link status.
2576  *
2577  * @param dev
2578  *  Pointer to struct rte_eth_dev.
2579  *
2580  * @return
2581  *  - On success, zero.
2582  *  - On failure, a negative value.
2583  */
2584 static void
2585 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2586 {
2587         struct rte_eth_link link;
2588
2589         memset(&link, 0, sizeof(link));
2590         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2591         if (link.link_status) {
2592                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2593                                         (int)(dev->data->port_id),
2594                                         (unsigned)link.link_speed,
2595                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2596                                         "full-duplex" : "half-duplex");
2597         } else {
2598                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2599                                 (int)(dev->data->port_id));
2600         }
2601         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2602                                 dev->pci_dev->addr.domain,
2603                                 dev->pci_dev->addr.bus,
2604                                 dev->pci_dev->addr.devid,
2605                                 dev->pci_dev->addr.function);
2606 }
2607
2608 /*
2609  * It executes link_update after knowing an interrupt occurred.
2610  *
2611  * @param dev
2612  *  Pointer to struct rte_eth_dev.
2613  *
2614  * @return
2615  *  - On success, zero.
2616  *  - On failure, a negative value.
2617  */
2618 static int
2619 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2620 {
2621         struct ixgbe_interrupt *intr =
2622                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2623         int64_t timeout;
2624         struct rte_eth_link link;
2625         int intr_enable_delay = false;
2626
2627         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2628
2629         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2630                 ixgbe_pf_mbx_process(dev);
2631                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2632         }
2633
2634         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2635                 /* get the link status before link update, for predicting later */
2636                 memset(&link, 0, sizeof(link));
2637                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2638
2639                 ixgbe_dev_link_update(dev, 0);
2640
2641                 /* likely to up */
2642                 if (!link.link_status)
2643                         /* handle it 1 sec later, wait it being stable */
2644                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2645                 /* likely to down */
2646                 else
2647                         /* handle it 4 sec later, wait it being stable */
2648                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2649
2650                 ixgbe_dev_link_status_print(dev);
2651
2652                 intr_enable_delay = true;
2653         }
2654
2655         if (intr_enable_delay) {
2656                 if (rte_eal_alarm_set(timeout * 1000,
2657                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2658                         PMD_DRV_LOG(ERR, "Error setting alarm");
2659         } else {
2660                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2661                 ixgbe_enable_intr(dev);
2662                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2663         }
2664
2665
2666         return 0;
2667 }
2668
2669 /**
2670  * Interrupt handler which shall be registered for alarm callback for delayed
2671  * handling specific interrupt to wait for the stable nic state. As the
2672  * NIC interrupt state is not stable for ixgbe after link is just down,
2673  * it needs to wait 4 seconds to get the stable status.
2674  *
2675  * @param handle
2676  *  Pointer to interrupt handle.
2677  * @param param
2678  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2679  *
2680  * @return
2681  *  void
2682  */
2683 static void
2684 ixgbe_dev_interrupt_delayed_handler(void *param)
2685 {
2686         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2687         struct ixgbe_interrupt *intr =
2688                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2689         struct ixgbe_hw *hw =
2690                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2691         uint32_t eicr;
2692
2693         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2694         if (eicr & IXGBE_EICR_MAILBOX)
2695                 ixgbe_pf_mbx_process(dev);
2696
2697         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2698                 ixgbe_dev_link_update(dev, 0);
2699                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2700                 ixgbe_dev_link_status_print(dev);
2701                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2702         }
2703
2704         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2705         ixgbe_enable_intr(dev);
2706         rte_intr_enable(&(dev->pci_dev->intr_handle));
2707 }
2708
2709 /**
2710  * Interrupt handler triggered by NIC  for handling
2711  * specific interrupt.
2712  *
2713  * @param handle
2714  *  Pointer to interrupt handle.
2715  * @param param
2716  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2717  *
2718  * @return
2719  *  void
2720  */
2721 static void
2722 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2723                                                         void *param)
2724 {
2725         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2726         ixgbe_dev_interrupt_get_status(dev);
2727         ixgbe_dev_interrupt_action(dev);
2728 }
2729
2730 static int
2731 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2732 {
2733         struct ixgbe_hw *hw;
2734
2735         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2737 }
2738
2739 static int
2740 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2741 {
2742         struct ixgbe_hw *hw;
2743
2744         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2745         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2746 }
2747
2748 static int
2749 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2750 {
2751         struct ixgbe_hw *hw;
2752         uint32_t mflcn_reg;
2753         uint32_t fccfg_reg;
2754         int rx_pause;
2755         int tx_pause;
2756
2757         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2758
2759         fc_conf->pause_time = hw->fc.pause_time;
2760         fc_conf->high_water = hw->fc.high_water[0];
2761         fc_conf->low_water = hw->fc.low_water[0];
2762         fc_conf->send_xon = hw->fc.send_xon;
2763         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2764
2765         /*
2766          * Return rx_pause status according to actual setting of
2767          * MFLCN register.
2768          */
2769         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2770         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2771                 rx_pause = 1;
2772         else
2773                 rx_pause = 0;
2774
2775         /*
2776          * Return tx_pause status according to actual setting of
2777          * FCCFG register.
2778          */
2779         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2780         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2781                 tx_pause = 1;
2782         else
2783                 tx_pause = 0;
2784
2785         if (rx_pause && tx_pause)
2786                 fc_conf->mode = RTE_FC_FULL;
2787         else if (rx_pause)
2788                 fc_conf->mode = RTE_FC_RX_PAUSE;
2789         else if (tx_pause)
2790                 fc_conf->mode = RTE_FC_TX_PAUSE;
2791         else
2792                 fc_conf->mode = RTE_FC_NONE;
2793
2794         return 0;
2795 }
2796
2797 static int
2798 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2799 {
2800         struct ixgbe_hw *hw;
2801         int err;
2802         uint32_t rx_buf_size;
2803         uint32_t max_high_water;
2804         uint32_t mflcn;
2805         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2806                 ixgbe_fc_none,
2807                 ixgbe_fc_rx_pause,
2808                 ixgbe_fc_tx_pause,
2809                 ixgbe_fc_full
2810         };
2811
2812         PMD_INIT_FUNC_TRACE();
2813
2814         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2816         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2817
2818         /*
2819          * At least reserve one Ethernet frame for watermark
2820          * high_water/low_water in kilo bytes for ixgbe
2821          */
2822         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2823         if ((fc_conf->high_water > max_high_water) ||
2824                 (fc_conf->high_water < fc_conf->low_water)) {
2825                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2826                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2827                 return (-EINVAL);
2828         }
2829
2830         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2831         hw->fc.pause_time     = fc_conf->pause_time;
2832         hw->fc.high_water[0]  = fc_conf->high_water;
2833         hw->fc.low_water[0]   = fc_conf->low_water;
2834         hw->fc.send_xon       = fc_conf->send_xon;
2835         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2836
2837         err = ixgbe_fc_enable(hw);
2838
2839         /* Not negotiated is not an error case */
2840         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2841
2842                 /* check if we want to forward MAC frames - driver doesn't have native
2843                  * capability to do that, so we'll write the registers ourselves */
2844
2845                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2846
2847                 /* set or clear MFLCN.PMCF bit depending on configuration */
2848                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2849                         mflcn |= IXGBE_MFLCN_PMCF;
2850                 else
2851                         mflcn &= ~IXGBE_MFLCN_PMCF;
2852
2853                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2854                 IXGBE_WRITE_FLUSH(hw);
2855
2856                 return 0;
2857         }
2858
2859         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2860         return -EIO;
2861 }
2862
2863 /**
2864  *  ixgbe_pfc_enable_generic - Enable flow control
2865  *  @hw: pointer to hardware structure
2866  *  @tc_num: traffic class number
2867  *  Enable flow control according to the current settings.
2868  */
2869 static int
2870 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2871 {
2872         int ret_val = 0;
2873         uint32_t mflcn_reg, fccfg_reg;
2874         uint32_t reg;
2875         uint32_t fcrtl, fcrth;
2876         uint8_t i;
2877         uint8_t nb_rx_en;
2878
2879         /* Validate the water mark configuration */
2880         if (!hw->fc.pause_time) {
2881                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2882                 goto out;
2883         }
2884
2885         /* Low water mark of zero causes XOFF floods */
2886         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2887                  /* High/Low water can not be 0 */
2888                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2889                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2890                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2891                         goto out;
2892                 }
2893
2894                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2895                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2896                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2897                         goto out;
2898                 }
2899         }
2900         /* Negotiate the fc mode to use */
2901         ixgbe_fc_autoneg(hw);
2902
2903         /* Disable any previous flow control settings */
2904         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2905         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2906
2907         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2908         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2909
2910         switch (hw->fc.current_mode) {
2911         case ixgbe_fc_none:
2912                 /*
2913                  * If the count of enabled RX Priority Flow control >1,
2914                  * and the TX pause can not be disabled
2915                  */
2916                 nb_rx_en = 0;
2917                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2918                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2919                         if (reg & IXGBE_FCRTH_FCEN)
2920                                 nb_rx_en++;
2921                 }
2922                 if (nb_rx_en > 1)
2923                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2924                 break;
2925         case ixgbe_fc_rx_pause:
2926                 /*
2927                  * Rx Flow control is enabled and Tx Flow control is
2928                  * disabled by software override. Since there really
2929                  * isn't a way to advertise that we are capable of RX
2930                  * Pause ONLY, we will advertise that we support both
2931                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2932                  * disable the adapter's ability to send PAUSE frames.
2933                  */
2934                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2935                 /*
2936                  * If the count of enabled RX Priority Flow control >1,
2937                  * and the TX pause can not be disabled
2938                  */
2939                 nb_rx_en = 0;
2940                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2941                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2942                         if (reg & IXGBE_FCRTH_FCEN)
2943                                 nb_rx_en++;
2944                 }
2945                 if (nb_rx_en > 1)
2946                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2947                 break;
2948         case ixgbe_fc_tx_pause:
2949                 /*
2950                  * Tx Flow control is enabled, and Rx Flow control is
2951                  * disabled by software override.
2952                  */
2953                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2954                 break;
2955         case ixgbe_fc_full:
2956                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2957                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2958                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2959                 break;
2960         default:
2961                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2962                 ret_val = IXGBE_ERR_CONFIG;
2963                 goto out;
2964                 break;
2965         }
2966
2967         /* Set 802.3x based flow control settings. */
2968         mflcn_reg |= IXGBE_MFLCN_DPF;
2969         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2970         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2971
2972         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2973         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2974                 hw->fc.high_water[tc_num]) {
2975                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2976                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2977                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2978         } else {
2979                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2980                 /*
2981                  * In order to prevent Tx hangs when the internal Tx
2982                  * switch is enabled we must set the high water mark
2983                  * to the maximum FCRTH value.  This allows the Tx
2984                  * switch to function even under heavy Rx workloads.
2985                  */
2986                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2987         }
2988         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2989
2990         /* Configure pause time (2 TCs per register) */
2991         reg = hw->fc.pause_time * 0x00010001;
2992         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2993                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2994
2995         /* Configure flow control refresh threshold value */
2996         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2997
2998 out:
2999         return ret_val;
3000 }
3001
3002 static int
3003 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3004 {
3005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3007
3008         if(hw->mac.type != ixgbe_mac_82598EB) {
3009                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3010         }
3011         return ret_val;
3012 }
3013
3014 static int
3015 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3016 {
3017         int err;
3018         uint32_t rx_buf_size;
3019         uint32_t max_high_water;
3020         uint8_t tc_num;
3021         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3022         struct ixgbe_hw *hw =
3023                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3024         struct ixgbe_dcb_config *dcb_config =
3025                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3026
3027         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3028                 ixgbe_fc_none,
3029                 ixgbe_fc_rx_pause,
3030                 ixgbe_fc_tx_pause,
3031                 ixgbe_fc_full
3032         };
3033
3034         PMD_INIT_FUNC_TRACE();
3035
3036         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3037         tc_num = map[pfc_conf->priority];
3038         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3039         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3040         /*
3041          * At least reserve one Ethernet frame for watermark
3042          * high_water/low_water in kilo bytes for ixgbe
3043          */
3044         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3045         if ((pfc_conf->fc.high_water > max_high_water) ||
3046             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3047                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3048                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3049                 return (-EINVAL);
3050         }
3051
3052         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3053         hw->fc.pause_time = pfc_conf->fc.pause_time;
3054         hw->fc.send_xon = pfc_conf->fc.send_xon;
3055         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3056         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3057
3058         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3059
3060         /* Not negotiated is not an error case */
3061         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3062                 return 0;
3063
3064         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3065         return -EIO;
3066 }
3067
3068 static int
3069 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3070                           struct rte_eth_rss_reta_entry64 *reta_conf,
3071                           uint16_t reta_size)
3072 {
3073         uint8_t i, j, mask;
3074         uint32_t reta, r;
3075         uint16_t idx, shift;
3076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3077
3078         PMD_INIT_FUNC_TRACE();
3079         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3080                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3081                         "(%d) doesn't match the number hardware can supported "
3082                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3083                 return -EINVAL;
3084         }
3085
3086         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3087                 idx = i / RTE_RETA_GROUP_SIZE;
3088                 shift = i % RTE_RETA_GROUP_SIZE;
3089                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3090                                                 IXGBE_4_BIT_MASK);
3091                 if (!mask)
3092                         continue;
3093                 if (mask == IXGBE_4_BIT_MASK)
3094                         r = 0;
3095                 else
3096                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3097                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3098                         if (mask & (0x1 << j))
3099                                 reta |= reta_conf[idx].reta[shift + j] <<
3100                                                         (CHAR_BIT * j);
3101                         else
3102                                 reta |= r & (IXGBE_8_BIT_MASK <<
3103                                                 (CHAR_BIT * j));
3104                 }
3105                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3106         }
3107
3108         return 0;
3109 }
3110
3111 static int
3112 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3113                          struct rte_eth_rss_reta_entry64 *reta_conf,
3114                          uint16_t reta_size)
3115 {
3116         uint8_t i, j, mask;
3117         uint32_t reta;
3118         uint16_t idx, shift;
3119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120
3121         PMD_INIT_FUNC_TRACE();
3122         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3123                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3124                         "(%d) doesn't match the number hardware can supported "
3125                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
3126                 return -EINVAL;
3127         }
3128
3129         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
3130                 idx = i / RTE_RETA_GROUP_SIZE;
3131                 shift = i % RTE_RETA_GROUP_SIZE;
3132                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3133                                                 IXGBE_4_BIT_MASK);
3134                 if (!mask)
3135                         continue;
3136
3137                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
3138                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3139                         if (mask & (0x1 << j))
3140                                 reta_conf[idx].reta[shift + j] =
3141                                         ((reta >> (CHAR_BIT * j)) &
3142                                                 IXGBE_8_BIT_MASK);
3143                 }
3144         }
3145
3146         return 0;
3147 }
3148
3149 static void
3150 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3151                                 uint32_t index, uint32_t pool)
3152 {
3153         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3154         uint32_t enable_addr = 1;
3155
3156         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3157 }
3158
3159 static void
3160 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3161 {
3162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3163
3164         ixgbe_clear_rar(hw, index);
3165 }
3166
3167 static void
3168 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3169 {
3170         ixgbe_remove_rar(dev, 0);
3171
3172         ixgbe_add_rar(dev, addr, 0, 0);
3173 }
3174
3175 static int
3176 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3177 {
3178         uint32_t hlreg0;
3179         uint32_t maxfrs;
3180         struct ixgbe_hw *hw;
3181         struct rte_eth_dev_info dev_info;
3182         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3183
3184         ixgbe_dev_info_get(dev, &dev_info);
3185
3186         /* check that mtu is within the allowed range */
3187         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3188                 return -EINVAL;
3189
3190         /* refuse mtu that requires the support of scattered packets when this
3191          * feature has not been enabled before. */
3192         if (!dev->data->scattered_rx &&
3193             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3194              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3195                 return -EINVAL;
3196
3197         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3198         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3199
3200         /* switch to jumbo mode if needed */
3201         if (frame_size > ETHER_MAX_LEN) {
3202                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3203                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3204         } else {
3205                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3206                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3207         }
3208         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3209
3210         /* update max frame size */
3211         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3212
3213         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3214         maxfrs &= 0x0000FFFF;
3215         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3216         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3217
3218         return 0;
3219 }
3220
3221 /*
3222  * Virtual Function operations
3223  */
3224 static void
3225 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3226 {
3227         PMD_INIT_FUNC_TRACE();
3228
3229         /* Clear interrupt mask to stop from interrupts being generated */
3230         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3231
3232         IXGBE_WRITE_FLUSH(hw);
3233 }
3234
3235 static int
3236 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3237 {
3238         struct rte_eth_conf* conf = &dev->data->dev_conf;
3239         struct ixgbe_adapter *adapter =
3240                         (struct ixgbe_adapter *)dev->data->dev_private;
3241
3242         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3243                      dev->data->port_id);
3244
3245         /*
3246          * VF has no ability to enable/disable HW CRC
3247          * Keep the persistent behavior the same as Host PF
3248          */
3249 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3250         if (!conf->rxmode.hw_strip_crc) {
3251                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
3252                 conf->rxmode.hw_strip_crc = 1;
3253         }
3254 #else
3255         if (conf->rxmode.hw_strip_crc) {
3256                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
3257                 conf->rxmode.hw_strip_crc = 0;
3258         }
3259 #endif
3260
3261         /*
3262          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3263          * allocation or vector Rx preconditions we will reset it.
3264          */
3265         adapter->rx_bulk_alloc_allowed = true;
3266         adapter->rx_vec_allowed = true;
3267
3268         return 0;
3269 }
3270
3271 static int
3272 ixgbevf_dev_start(struct rte_eth_dev *dev)
3273 {
3274         struct ixgbe_hw *hw =
3275                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3276         int err, mask = 0;
3277
3278         PMD_INIT_FUNC_TRACE();
3279
3280         hw->mac.ops.reset_hw(hw);
3281         hw->mac.get_link_status = true;
3282
3283         /* negotiate mailbox API version to use with the PF. */
3284         ixgbevf_negotiate_api(hw);
3285
3286         ixgbevf_dev_tx_init(dev);
3287
3288         /* This can fail when allocating mbufs for descriptor rings */
3289         err = ixgbevf_dev_rx_init(dev);
3290         if (err) {
3291                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3292                 ixgbe_dev_clear_queues(dev);
3293                 return err;
3294         }
3295
3296         /* Set vfta */
3297         ixgbevf_set_vfta_all(dev,1);
3298
3299         /* Set HW strip */
3300         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3301                 ETH_VLAN_EXTEND_MASK;
3302         ixgbevf_vlan_offload_set(dev, mask);
3303
3304         ixgbevf_dev_rxtx_start(dev);
3305
3306         return 0;
3307 }
3308
3309 static void
3310 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3311 {
3312         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313
3314         PMD_INIT_FUNC_TRACE();
3315
3316         hw->adapter_stopped = 1;
3317         ixgbe_stop_adapter(hw);
3318
3319         /*
3320           * Clear what we set, but we still keep shadow_vfta to
3321           * restore after device starts
3322           */
3323         ixgbevf_set_vfta_all(dev,0);
3324
3325         /* Clear stored conf */
3326         dev->data->scattered_rx = 0;
3327
3328         ixgbe_dev_clear_queues(dev);
3329 }
3330
3331 static void
3332 ixgbevf_dev_close(struct rte_eth_dev *dev)
3333 {
3334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335
3336         PMD_INIT_FUNC_TRACE();
3337
3338         ixgbe_reset_hw(hw);
3339
3340         ixgbevf_dev_stop(dev);
3341
3342         ixgbe_dev_free_queues(dev);
3343
3344         /* reprogram the RAR[0] in case user changed it. */
3345         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3346 }
3347
3348 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3349 {
3350         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3351         struct ixgbe_vfta * shadow_vfta =
3352                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3353         int i = 0, j = 0, vfta = 0, mask = 1;
3354
3355         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3356                 vfta = shadow_vfta->vfta[i];
3357                 if(vfta){
3358                         mask = 1;
3359                         for (j = 0; j < 32; j++){
3360                                 if(vfta & mask)
3361                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3362                                 mask<<=1;
3363                         }
3364                 }
3365         }
3366
3367 }
3368
3369 static int
3370 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3371 {
3372         struct ixgbe_hw *hw =
3373                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374         struct ixgbe_vfta * shadow_vfta =
3375                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3376         uint32_t vid_idx = 0;
3377         uint32_t vid_bit = 0;
3378         int ret = 0;
3379
3380         PMD_INIT_FUNC_TRACE();
3381
3382         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3383         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3384         if(ret){
3385                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3386                 return ret;
3387         }
3388         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3389         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3390
3391         /* Save what we set and retore it after device reset */
3392         if (on)
3393                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3394         else
3395                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3396
3397         return 0;
3398 }
3399
3400 static void
3401 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3402 {
3403         struct ixgbe_hw *hw =
3404                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3405         uint32_t ctrl;
3406
3407         PMD_INIT_FUNC_TRACE();
3408
3409         if(queue >= hw->mac.max_rx_queues)
3410                 return;
3411
3412         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3413         if(on)
3414                 ctrl |= IXGBE_RXDCTL_VME;
3415         else
3416                 ctrl &= ~IXGBE_RXDCTL_VME;
3417         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3418
3419         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3420 }
3421
3422 static void
3423 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3424 {
3425         struct ixgbe_hw *hw =
3426                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3427         uint16_t i;
3428         int on = 0;
3429
3430         /* VF function only support hw strip feature, others are not support */
3431         if(mask & ETH_VLAN_STRIP_MASK){
3432                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3433
3434                 for(i=0; i < hw->mac.max_rx_queues; i++)
3435                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3436         }
3437 }
3438
3439 static int
3440 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3441 {
3442         uint32_t reg_val;
3443
3444         /* we only need to do this if VMDq is enabled */
3445         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3446         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3447                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3448                 return (-1);
3449         }
3450
3451         return 0;
3452 }
3453
3454 static uint32_t
3455 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3456 {
3457         uint32_t vector = 0;
3458         switch (hw->mac.mc_filter_type) {
3459         case 0:   /* use bits [47:36] of the address */
3460                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3461                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3462                 break;
3463         case 1:   /* use bits [46:35] of the address */
3464                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3465                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3466                 break;
3467         case 2:   /* use bits [45:34] of the address */
3468                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3469                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3470                 break;
3471         case 3:   /* use bits [43:32] of the address */
3472                 vector = ((uc_addr->addr_bytes[4]) |
3473                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3474                 break;
3475         default:  /* Invalid mc_filter_type */
3476                 break;
3477         }
3478
3479         /* vector can only be 12-bits or boundary will be exceeded */
3480         vector &= 0xFFF;
3481         return vector;
3482 }
3483
3484 static int
3485 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3486                                uint8_t on)
3487 {
3488         uint32_t vector;
3489         uint32_t uta_idx;
3490         uint32_t reg_val;
3491         uint32_t uta_shift;
3492         uint32_t rc;
3493         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3494         const uint32_t ixgbe_uta_bit_shift = 5;
3495         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3496         const uint32_t bit1 = 0x1;
3497
3498         struct ixgbe_hw *hw =
3499                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3500         struct ixgbe_uta_info *uta_info =
3501                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3502
3503         /* The UTA table only exists on 82599 hardware and newer */
3504         if (hw->mac.type < ixgbe_mac_82599EB)
3505                 return (-ENOTSUP);
3506
3507         vector = ixgbe_uta_vector(hw,mac_addr);
3508         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3509         uta_shift = vector & ixgbe_uta_bit_mask;
3510
3511         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3512         if(rc == on)
3513                 return 0;
3514
3515         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3516         if (on) {
3517                 uta_info->uta_in_use++;
3518                 reg_val |= (bit1 << uta_shift);
3519                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3520         } else {
3521                 uta_info->uta_in_use--;
3522                 reg_val &= ~(bit1 << uta_shift);
3523                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3524         }
3525
3526         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3527
3528         if (uta_info->uta_in_use > 0)
3529                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3530                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3531         else
3532                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3533
3534         return 0;
3535 }
3536
3537 static int
3538 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3539 {
3540         int i;
3541         struct ixgbe_hw *hw =
3542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3543         struct ixgbe_uta_info *uta_info =
3544                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3545
3546         /* The UTA table only exists on 82599 hardware and newer */
3547         if (hw->mac.type < ixgbe_mac_82599EB)
3548                 return (-ENOTSUP);
3549
3550         if(on) {
3551                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3552                         uta_info->uta_shadow[i] = ~0;
3553                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3554                 }
3555         } else {
3556                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3557                         uta_info->uta_shadow[i] = 0;
3558                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3559                 }
3560         }
3561         return 0;
3562
3563 }
3564
3565 uint32_t
3566 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3567 {
3568         uint32_t new_val = orig_val;
3569
3570         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3571                 new_val |= IXGBE_VMOLR_AUPE;
3572         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3573                 new_val |= IXGBE_VMOLR_ROMPE;
3574         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3575                 new_val |= IXGBE_VMOLR_ROPE;
3576         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3577                 new_val |= IXGBE_VMOLR_BAM;
3578         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3579                 new_val |= IXGBE_VMOLR_MPE;
3580
3581         return new_val;
3582 }
3583
3584 static int
3585 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3586                                uint16_t rx_mask, uint8_t on)
3587 {
3588         int val = 0;
3589
3590         struct ixgbe_hw *hw =
3591                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3593
3594         if (hw->mac.type == ixgbe_mac_82598EB) {
3595                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3596                              " on 82599 hardware and newer");
3597                 return (-ENOTSUP);
3598         }
3599         if (ixgbe_vmdq_mode_check(hw) < 0)
3600                 return (-ENOTSUP);
3601
3602         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3603
3604         if (on)
3605                 vmolr |= val;
3606         else
3607                 vmolr &= ~val;
3608
3609         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3610
3611         return 0;
3612 }
3613
3614 static int
3615 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3616 {
3617         uint32_t reg,addr;
3618         uint32_t val;
3619         const uint8_t bit1 = 0x1;
3620
3621         struct ixgbe_hw *hw =
3622                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623
3624         if (ixgbe_vmdq_mode_check(hw) < 0)
3625                 return (-ENOTSUP);
3626
3627         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3628         reg = IXGBE_READ_REG(hw, addr);
3629         val = bit1 << pool;
3630
3631         if (on)
3632                 reg |= val;
3633         else
3634                 reg &= ~val;
3635
3636         IXGBE_WRITE_REG(hw, addr,reg);
3637
3638         return 0;
3639 }
3640
3641 static int
3642 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3643 {
3644         uint32_t reg,addr;
3645         uint32_t val;
3646         const uint8_t bit1 = 0x1;
3647
3648         struct ixgbe_hw *hw =
3649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3650
3651         if (ixgbe_vmdq_mode_check(hw) < 0)
3652                 return (-ENOTSUP);
3653
3654         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3655         reg = IXGBE_READ_REG(hw, addr);
3656         val = bit1 << pool;
3657
3658         if (on)
3659                 reg |= val;
3660         else
3661                 reg &= ~val;
3662
3663         IXGBE_WRITE_REG(hw, addr,reg);
3664
3665         return 0;
3666 }
3667
3668 static int
3669 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3670                         uint64_t pool_mask, uint8_t vlan_on)
3671 {
3672         int ret = 0;
3673         uint16_t pool_idx;
3674         struct ixgbe_hw *hw =
3675                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3676
3677         if (ixgbe_vmdq_mode_check(hw) < 0)
3678                 return (-ENOTSUP);
3679         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3680                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3681                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3682                         if (ret < 0)
3683                                 return ret;
3684         }
3685
3686         return ret;
3687 }
3688
3689 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
3690 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
3691 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
3692 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
3693 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3694         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3695         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3696
3697 static int
3698 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3699                         struct rte_eth_mirror_conf *mirror_conf,
3700                         uint8_t rule_id, uint8_t on)
3701 {
3702         uint32_t mr_ctl,vlvf;
3703         uint32_t mp_lsb = 0;
3704         uint32_t mv_msb = 0;
3705         uint32_t mv_lsb = 0;
3706         uint32_t mp_msb = 0;
3707         uint8_t i = 0;
3708         int reg_index = 0;
3709         uint64_t vlan_mask = 0;
3710
3711         const uint8_t pool_mask_offset = 32;
3712         const uint8_t vlan_mask_offset = 32;
3713         const uint8_t dst_pool_offset = 8;
3714         const uint8_t rule_mr_offset  = 4;
3715         const uint8_t mirror_rule_mask= 0x0F;
3716
3717         struct ixgbe_mirror_info *mr_info =
3718                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3719         struct ixgbe_hw *hw =
3720                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3721         uint8_t mirror_type = 0;
3722
3723         if (ixgbe_vmdq_mode_check(hw) < 0)
3724                 return -ENOTSUP;
3725
3726         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3727                 return -EINVAL;
3728
3729         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3730                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3731                         mirror_conf->rule_type);
3732                 return -EINVAL;
3733         }
3734
3735         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3736                 mirror_type |= IXGBE_MRCTL_VLME;
3737                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3738                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3739                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3740                                 /* search vlan id related pool vlan filter index */
3741                                 reg_index = ixgbe_find_vlvf_slot(hw,
3742                                                 mirror_conf->vlan.vlan_id[i]);
3743                                 if(reg_index < 0)
3744                                         return -EINVAL;
3745                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3746                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3747                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3748                                       mirror_conf->vlan.vlan_id[i]))
3749                                         vlan_mask |= (1ULL << reg_index);
3750                                 else
3751                                         return -EINVAL;
3752                         }
3753                 }
3754
3755                 if (on) {
3756                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3757                         mv_msb = vlan_mask >> vlan_mask_offset;
3758
3759                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3760                                                 mirror_conf->vlan.vlan_mask;
3761                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3762                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3763                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3764                                                 mirror_conf->vlan.vlan_id[i];
3765                         }
3766                 } else {
3767                         mv_lsb = 0;
3768                         mv_msb = 0;
3769                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3770                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3771                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3772                 }
3773         }
3774
3775         /*
3776          * if enable pool mirror, write related pool mask register,if disable
3777          * pool mirror, clear PFMRVM register
3778          */
3779         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
3780                 mirror_type |= IXGBE_MRCTL_VPME;
3781                 if (on) {
3782                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3783                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3784                         mr_info->mr_conf[rule_id].pool_mask =
3785                                         mirror_conf->pool_mask;
3786
3787                 } else {
3788                         mp_lsb = 0;
3789                         mp_msb = 0;
3790                         mr_info->mr_conf[rule_id].pool_mask = 0;
3791                 }
3792         }
3793         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
3794                 mirror_type |= IXGBE_MRCTL_UPME;
3795         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
3796                 mirror_type |= IXGBE_MRCTL_DPME;
3797
3798         /* read  mirror control register and recalculate it */
3799         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
3800
3801         if (on) {
3802                 mr_ctl |= mirror_type;
3803                 mr_ctl &= mirror_rule_mask;
3804                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3805         } else
3806                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
3807
3808         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
3809         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3810
3811         /* write mirrror control  register */
3812         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3813
3814         /* write pool mirrror control  register */
3815         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
3816                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3817                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3818                                 mp_msb);
3819         }
3820         /* write VLAN mirrror control  register */
3821         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
3822                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3823                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3824                                 mv_msb);
3825         }
3826
3827         return 0;
3828 }
3829
3830 static int
3831 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3832 {
3833         int mr_ctl = 0;
3834         uint32_t lsb_val = 0;
3835         uint32_t msb_val = 0;
3836         const uint8_t rule_mr_offset = 4;
3837
3838         struct ixgbe_hw *hw =
3839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840         struct ixgbe_mirror_info *mr_info =
3841                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3842
3843         if (ixgbe_vmdq_mode_check(hw) < 0)
3844                 return (-ENOTSUP);
3845
3846         memset(&mr_info->mr_conf[rule_id], 0,
3847                 sizeof(struct rte_eth_mirror_conf));
3848
3849         /* clear PFVMCTL register */
3850         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3851
3852         /* clear pool mask register */
3853         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3854         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3855
3856         /* clear vlan mask register */
3857         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3858         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3859
3860         return 0;
3861 }
3862
3863 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3864         uint16_t queue_idx, uint16_t tx_rate)
3865 {
3866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3867         uint32_t rf_dec, rf_int;
3868         uint32_t bcnrc_val;
3869         uint16_t link_speed = dev->data->dev_link.link_speed;
3870
3871         if (queue_idx >= hw->mac.max_tx_queues)
3872                 return -EINVAL;
3873
3874         if (tx_rate != 0) {
3875                 /* Calculate the rate factor values to set */
3876                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3877                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3878                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3879
3880                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3881                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3882                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3883                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3884         } else {
3885                 bcnrc_val = 0;
3886         }
3887
3888         /*
3889          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3890          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3891          * set as 0x4.
3892          */
3893         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3894                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3895                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3896                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3897                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3898         else
3899                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3900                         IXGBE_MMW_SIZE_DEFAULT);
3901
3902         /* Set RTTBCNRC of queue X */
3903         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3904         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3905         IXGBE_WRITE_FLUSH(hw);
3906
3907         return 0;
3908 }
3909
3910 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3911         uint16_t tx_rate, uint64_t q_msk)
3912 {
3913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3914         struct ixgbe_vf_info *vfinfo =
3915                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3916         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3917         uint32_t queue_stride =
3918                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3919         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3920         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3921         uint16_t total_rate = 0;
3922
3923         if (queue_end >= hw->mac.max_tx_queues)
3924                 return -EINVAL;
3925
3926         if (vfinfo != NULL) {
3927                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3928                         if (vf_idx == vf)
3929                                 continue;
3930                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3931                                 idx++)
3932                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3933                 }
3934         } else
3935                 return -EINVAL;
3936
3937         /* Store tx_rate for this vf. */
3938         for (idx = 0; idx < nb_q_per_pool; idx++) {
3939                 if (((uint64_t)0x1 << idx) & q_msk) {
3940                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3941                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3942                         total_rate += tx_rate;
3943                 }
3944         }
3945
3946         if (total_rate > dev->data->dev_link.link_speed) {
3947                 /*
3948                  * Reset stored TX rate of the VF if it causes exceed
3949                  * link speed.
3950                  */
3951                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3952                 return -EINVAL;
3953         }
3954
3955         /* Set RTTBCNRC of each queue/pool for vf X  */
3956         for (; queue_idx <= queue_end; queue_idx++) {
3957                 if (0x1 & q_msk)
3958                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3959                 q_msk = q_msk >> 1;
3960         }
3961
3962         return 0;
3963 }
3964
3965 static void
3966 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3967                      __attribute__((unused)) uint32_t index,
3968                      __attribute__((unused)) uint32_t pool)
3969 {
3970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971         int diag;
3972
3973         /*
3974          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3975          * operation. Trap this case to avoid exhausting the [very limited]
3976          * set of PF resources used to store VF MAC addresses.
3977          */
3978         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3979                 return;
3980         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3981         if (diag == 0)
3982                 return;
3983         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3984 }
3985
3986 static void
3987 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3988 {
3989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3990         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3991         struct ether_addr *mac_addr;
3992         uint32_t i;
3993         int diag;
3994
3995         /*
3996          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3997          * not support the deletion of a given MAC address.
3998          * Instead, it imposes to delete all MAC addresses, then to add again
3999          * all MAC addresses with the exception of the one to be deleted.
4000          */
4001         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4002
4003         /*
4004          * Add again all MAC addresses, with the exception of the deleted one
4005          * and of the permanent MAC address.
4006          */
4007         for (i = 0, mac_addr = dev->data->mac_addrs;
4008              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4009                 /* Skip the deleted MAC address */
4010                 if (i == index)
4011                         continue;
4012                 /* Skip NULL MAC addresses */
4013                 if (is_zero_ether_addr(mac_addr))
4014                         continue;
4015                 /* Skip the permanent MAC address */
4016                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4017                         continue;
4018                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4019                 if (diag != 0)
4020                         PMD_DRV_LOG(ERR,
4021                                     "Adding again MAC address "
4022                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4023                                     "diag=%d",
4024                                     mac_addr->addr_bytes[0],
4025                                     mac_addr->addr_bytes[1],
4026                                     mac_addr->addr_bytes[2],
4027                                     mac_addr->addr_bytes[3],
4028                                     mac_addr->addr_bytes[4],
4029                                     mac_addr->addr_bytes[5],
4030                                     diag);
4031         }
4032 }
4033
4034 static void
4035 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4036 {
4037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4038
4039         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4040 }
4041
4042 #define MAC_TYPE_FILTER_SUP(type)    do {\
4043         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4044                 (type) != ixgbe_mac_X550)\
4045                 return -ENOTSUP;\
4046 } while (0)
4047
4048 static int
4049 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4050                         struct rte_eth_syn_filter *filter,
4051                         bool add)
4052 {
4053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4054         uint32_t synqf;
4055
4056         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4057                 return -EINVAL;
4058
4059         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4060
4061         if (add) {
4062                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4063                         return -EINVAL;
4064                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4065                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4066
4067                 if (filter->hig_pri)
4068                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4069                 else
4070                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4071         } else {
4072                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4073                         return -ENOENT;
4074                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4075         }
4076         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4077         IXGBE_WRITE_FLUSH(hw);
4078         return 0;
4079 }
4080
4081 static int
4082 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4083                         struct rte_eth_syn_filter *filter)
4084 {
4085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4086         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4087
4088         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4089                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4090                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4091                 return 0;
4092         }
4093         return -ENOENT;
4094 }
4095
4096 static int
4097 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4098                         enum rte_filter_op filter_op,
4099                         void *arg)
4100 {
4101         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102         int ret;
4103
4104         MAC_TYPE_FILTER_SUP(hw->mac.type);
4105
4106         if (filter_op == RTE_ETH_FILTER_NOP)
4107                 return 0;
4108
4109         if (arg == NULL) {
4110                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4111                             filter_op);
4112                 return -EINVAL;
4113         }
4114
4115         switch (filter_op) {
4116         case RTE_ETH_FILTER_ADD:
4117                 ret = ixgbe_syn_filter_set(dev,
4118                                 (struct rte_eth_syn_filter *)arg,
4119                                 TRUE);
4120                 break;
4121         case RTE_ETH_FILTER_DELETE:
4122                 ret = ixgbe_syn_filter_set(dev,
4123                                 (struct rte_eth_syn_filter *)arg,
4124                                 FALSE);
4125                 break;
4126         case RTE_ETH_FILTER_GET:
4127                 ret = ixgbe_syn_filter_get(dev,
4128                                 (struct rte_eth_syn_filter *)arg);
4129                 break;
4130         default:
4131                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4132                 ret = -EINVAL;
4133                 break;
4134         }
4135
4136         return ret;
4137 }
4138
4139
4140 static inline enum ixgbe_5tuple_protocol
4141 convert_protocol_type(uint8_t protocol_value)
4142 {
4143         if (protocol_value == IPPROTO_TCP)
4144                 return IXGBE_FILTER_PROTOCOL_TCP;
4145         else if (protocol_value == IPPROTO_UDP)
4146                 return IXGBE_FILTER_PROTOCOL_UDP;
4147         else if (protocol_value == IPPROTO_SCTP)
4148                 return IXGBE_FILTER_PROTOCOL_SCTP;
4149         else
4150                 return IXGBE_FILTER_PROTOCOL_NONE;
4151 }
4152
4153 /*
4154  * add a 5tuple filter
4155  *
4156  * @param
4157  * dev: Pointer to struct rte_eth_dev.
4158  * index: the index the filter allocates.
4159  * filter: ponter to the filter that will be added.
4160  * rx_queue: the queue id the filter assigned to.
4161  *
4162  * @return
4163  *    - On success, zero.
4164  *    - On failure, a negative value.
4165  */
4166 static int
4167 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4168                         struct ixgbe_5tuple_filter *filter)
4169 {
4170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4171         struct ixgbe_filter_info *filter_info =
4172                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4173         int i, idx, shift;
4174         uint32_t ftqf, sdpqf;
4175         uint32_t l34timir = 0;
4176         uint8_t mask = 0xff;
4177
4178         /*
4179          * look for an unused 5tuple filter index,
4180          * and insert the filter to list.
4181          */
4182         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4183                 idx = i / (sizeof(uint32_t) * NBBY);
4184                 shift = i % (sizeof(uint32_t) * NBBY);
4185                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4186                         filter_info->fivetuple_mask[idx] |= 1 << shift;
4187                         filter->index = i;
4188                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4189                                           filter,
4190                                           entries);
4191                         break;
4192                 }
4193         }
4194         if (i >= IXGBE_MAX_FTQF_FILTERS) {
4195                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4196                 return -ENOSYS;
4197         }
4198
4199         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4200                                 IXGBE_SDPQF_DSTPORT_SHIFT);
4201         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4202
4203         ftqf = (uint32_t)(filter->filter_info.proto &
4204                 IXGBE_FTQF_PROTOCOL_MASK);
4205         ftqf |= (uint32_t)((filter->filter_info.priority &
4206                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4207         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4208                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
4209         if (filter->filter_info.dst_ip_mask == 0)
4210                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
4211         if (filter->filter_info.src_port_mask == 0)
4212                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
4213         if (filter->filter_info.dst_port_mask == 0)
4214                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
4215         if (filter->filter_info.proto_mask == 0)
4216                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
4217         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
4218         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
4219         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
4220
4221         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
4222         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
4223         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
4224         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
4225
4226         l34timir |= IXGBE_L34T_IMIR_RESERVE;
4227         l34timir |= (uint32_t)(filter->queue <<
4228                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
4229         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4230         return 0;
4231 }
4232
4233 /*
4234  * remove a 5tuple filter
4235  *
4236  * @param
4237  * dev: Pointer to struct rte_eth_dev.
4238  * filter: the pointer of the filter will be removed.
4239  */
4240 static void
4241 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4242                         struct ixgbe_5tuple_filter *filter)
4243 {
4244         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4245         struct ixgbe_filter_info *filter_info =
4246                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4247         uint16_t index = filter->index;
4248
4249         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4250                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4251         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4252         rte_free(filter);
4253
4254         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4255         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4256         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4257         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4258         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4259 }
4260
4261 static int
4262 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4263 {
4264         struct ixgbe_hw *hw;
4265         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4266
4267         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4268
4269         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4270                 return -EINVAL;
4271
4272         /* refuse mtu that requires the support of scattered packets when this
4273          * feature has not been enabled before. */
4274         if (!dev->data->scattered_rx &&
4275             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4276              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4277                 return -EINVAL;
4278
4279         /*
4280          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4281          * request of the version 2.0 of the mailbox API.
4282          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4283          * of the mailbox API.
4284          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4285          * prior to 3.11.33 which contains the following change:
4286          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4287          */
4288         ixgbevf_rlpml_set_vf(hw, max_frame);
4289
4290         /* update max frame size */
4291         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4292         return 0;
4293 }
4294
4295 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4296         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4297                 return -ENOTSUP;\
4298 } while (0)
4299
4300 static inline struct ixgbe_5tuple_filter *
4301 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4302                         struct ixgbe_5tuple_filter_info *key)
4303 {
4304         struct ixgbe_5tuple_filter *it;
4305
4306         TAILQ_FOREACH(it, filter_list, entries) {
4307                 if (memcmp(key, &it->filter_info,
4308                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4309                         return it;
4310                 }
4311         }
4312         return NULL;
4313 }
4314
4315 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4316 static inline int
4317 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4318                         struct ixgbe_5tuple_filter_info *filter_info)
4319 {
4320         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4321                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4322                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4323                 return -EINVAL;
4324
4325         switch (filter->dst_ip_mask) {
4326         case UINT32_MAX:
4327                 filter_info->dst_ip_mask = 0;
4328                 filter_info->dst_ip = filter->dst_ip;
4329                 break;
4330         case 0:
4331                 filter_info->dst_ip_mask = 1;
4332                 break;
4333         default:
4334                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4335                 return -EINVAL;
4336         }
4337
4338         switch (filter->src_ip_mask) {
4339         case UINT32_MAX:
4340                 filter_info->src_ip_mask = 0;
4341                 filter_info->src_ip = filter->src_ip;
4342                 break;
4343         case 0:
4344                 filter_info->src_ip_mask = 1;
4345                 break;
4346         default:
4347                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4348                 return -EINVAL;
4349         }
4350
4351         switch (filter->dst_port_mask) {
4352         case UINT16_MAX:
4353                 filter_info->dst_port_mask = 0;
4354                 filter_info->dst_port = filter->dst_port;
4355                 break;
4356         case 0:
4357                 filter_info->dst_port_mask = 1;
4358                 break;
4359         default:
4360                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4361                 return -EINVAL;
4362         }
4363
4364         switch (filter->src_port_mask) {
4365         case UINT16_MAX:
4366                 filter_info->src_port_mask = 0;
4367                 filter_info->src_port = filter->src_port;
4368                 break;
4369         case 0:
4370                 filter_info->src_port_mask = 1;
4371                 break;
4372         default:
4373                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4374                 return -EINVAL;
4375         }
4376
4377         switch (filter->proto_mask) {
4378         case UINT8_MAX:
4379                 filter_info->proto_mask = 0;
4380                 filter_info->proto =
4381                         convert_protocol_type(filter->proto);
4382                 break;
4383         case 0:
4384                 filter_info->proto_mask = 1;
4385                 break;
4386         default:
4387                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4388                 return -EINVAL;
4389         }
4390
4391         filter_info->priority = (uint8_t)filter->priority;
4392         return 0;
4393 }
4394
4395 /*
4396  * add or delete a ntuple filter
4397  *
4398  * @param
4399  * dev: Pointer to struct rte_eth_dev.
4400  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4401  * add: if true, add filter, if false, remove filter
4402  *
4403  * @return
4404  *    - On success, zero.
4405  *    - On failure, a negative value.
4406  */
4407 static int
4408 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4409                         struct rte_eth_ntuple_filter *ntuple_filter,
4410                         bool add)
4411 {
4412         struct ixgbe_filter_info *filter_info =
4413                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4414         struct ixgbe_5tuple_filter_info filter_5tuple;
4415         struct ixgbe_5tuple_filter *filter;
4416         int ret;
4417
4418         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4419                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4420                 return -EINVAL;
4421         }
4422
4423         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4424         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4425         if (ret < 0)
4426                 return ret;
4427
4428         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4429                                          &filter_5tuple);
4430         if (filter != NULL && add) {
4431                 PMD_DRV_LOG(ERR, "filter exists.");
4432                 return -EEXIST;
4433         }
4434         if (filter == NULL && !add) {
4435                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4436                 return -ENOENT;
4437         }
4438
4439         if (add) {
4440                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4441                                 sizeof(struct ixgbe_5tuple_filter), 0);
4442                 if (filter == NULL)
4443                         return -ENOMEM;
4444                 (void)rte_memcpy(&filter->filter_info,
4445                                  &filter_5tuple,
4446                                  sizeof(struct ixgbe_5tuple_filter_info));
4447                 filter->queue = ntuple_filter->queue;
4448                 ret = ixgbe_add_5tuple_filter(dev, filter);
4449                 if (ret < 0) {
4450                         rte_free(filter);
4451                         return ret;
4452                 }
4453         } else
4454                 ixgbe_remove_5tuple_filter(dev, filter);
4455
4456         return 0;
4457 }
4458
4459 /*
4460  * get a ntuple filter
4461  *
4462  * @param
4463  * dev: Pointer to struct rte_eth_dev.
4464  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4465  *
4466  * @return
4467  *    - On success, zero.
4468  *    - On failure, a negative value.
4469  */
4470 static int
4471 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4472                         struct rte_eth_ntuple_filter *ntuple_filter)
4473 {
4474         struct ixgbe_filter_info *filter_info =
4475                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4476         struct ixgbe_5tuple_filter_info filter_5tuple;
4477         struct ixgbe_5tuple_filter *filter;
4478         int ret;
4479
4480         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4481                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4482                 return -EINVAL;
4483         }
4484
4485         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4486         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4487         if (ret < 0)
4488                 return ret;
4489
4490         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4491                                          &filter_5tuple);
4492         if (filter == NULL) {
4493                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4494                 return -ENOENT;
4495         }
4496         ntuple_filter->queue = filter->queue;
4497         return 0;
4498 }
4499
4500 /*
4501  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4502  * @dev: pointer to rte_eth_dev structure
4503  * @filter_op:operation will be taken.
4504  * @arg: a pointer to specific structure corresponding to the filter_op
4505  *
4506  * @return
4507  *    - On success, zero.
4508  *    - On failure, a negative value.
4509  */
4510 static int
4511 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4512                                 enum rte_filter_op filter_op,
4513                                 void *arg)
4514 {
4515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4516         int ret;
4517
4518         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4519
4520         if (filter_op == RTE_ETH_FILTER_NOP)
4521                 return 0;
4522
4523         if (arg == NULL) {
4524                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4525                             filter_op);
4526                 return -EINVAL;
4527         }
4528
4529         switch (filter_op) {
4530         case RTE_ETH_FILTER_ADD:
4531                 ret = ixgbe_add_del_ntuple_filter(dev,
4532                         (struct rte_eth_ntuple_filter *)arg,
4533                         TRUE);
4534                 break;
4535         case RTE_ETH_FILTER_DELETE:
4536                 ret = ixgbe_add_del_ntuple_filter(dev,
4537                         (struct rte_eth_ntuple_filter *)arg,
4538                         FALSE);
4539                 break;
4540         case RTE_ETH_FILTER_GET:
4541                 ret = ixgbe_get_ntuple_filter(dev,
4542                         (struct rte_eth_ntuple_filter *)arg);
4543                 break;
4544         default:
4545                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4546                 ret = -EINVAL;
4547                 break;
4548         }
4549         return ret;
4550 }
4551
4552 static inline int
4553 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4554                         uint16_t ethertype)
4555 {
4556         int i;
4557
4558         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4559                 if (filter_info->ethertype_filters[i] == ethertype &&
4560                     (filter_info->ethertype_mask & (1 << i)))
4561                         return i;
4562         }
4563         return -1;
4564 }
4565
4566 static inline int
4567 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4568                         uint16_t ethertype)
4569 {
4570         int i;
4571
4572         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4573                 if (!(filter_info->ethertype_mask & (1 << i))) {
4574                         filter_info->ethertype_mask |= 1 << i;
4575                         filter_info->ethertype_filters[i] = ethertype;
4576                         return i;
4577                 }
4578         }
4579         return -1;
4580 }
4581
4582 static inline int
4583 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4584                         uint8_t idx)
4585 {
4586         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4587                 return -1;
4588         filter_info->ethertype_mask &= ~(1 << idx);
4589         filter_info->ethertype_filters[idx] = 0;
4590         return idx;
4591 }
4592
4593 static int
4594 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4595                         struct rte_eth_ethertype_filter *filter,
4596                         bool add)
4597 {
4598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4599         struct ixgbe_filter_info *filter_info =
4600                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4601         uint32_t etqf = 0;
4602         uint32_t etqs = 0;
4603         int ret;
4604
4605         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4606                 return -EINVAL;
4607
4608         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4609                 filter->ether_type == ETHER_TYPE_IPv6) {
4610                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4611                         " ethertype filter.", filter->ether_type);
4612                 return -EINVAL;
4613         }
4614
4615         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4616                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4617                 return -EINVAL;
4618         }
4619         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4620                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4621                 return -EINVAL;
4622         }
4623
4624         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4625         if (ret >= 0 && add) {
4626                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4627                             filter->ether_type);
4628                 return -EEXIST;
4629         }
4630         if (ret < 0 && !add) {
4631                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4632                             filter->ether_type);
4633                 return -ENOENT;
4634         }
4635
4636         if (add) {
4637                 ret = ixgbe_ethertype_filter_insert(filter_info,
4638                         filter->ether_type);
4639                 if (ret < 0) {
4640                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4641                         return -ENOSYS;
4642                 }
4643                 etqf = IXGBE_ETQF_FILTER_EN;
4644                 etqf |= (uint32_t)filter->ether_type;
4645                 etqs |= (uint32_t)((filter->queue <<
4646                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4647                                     IXGBE_ETQS_RX_QUEUE);
4648                 etqs |= IXGBE_ETQS_QUEUE_EN;
4649         } else {
4650                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4651                 if (ret < 0)
4652                         return -ENOSYS;
4653         }
4654         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4655         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4656         IXGBE_WRITE_FLUSH(hw);
4657
4658         return 0;
4659 }
4660
4661 static int
4662 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4663                         struct rte_eth_ethertype_filter *filter)
4664 {
4665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4666         struct ixgbe_filter_info *filter_info =
4667                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4668         uint32_t etqf, etqs;
4669         int ret;
4670
4671         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4672         if (ret < 0) {
4673                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4674                             filter->ether_type);
4675                 return -ENOENT;
4676         }
4677
4678         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4679         if (etqf & IXGBE_ETQF_FILTER_EN) {
4680                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4681                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4682                 filter->flags = 0;
4683                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4684                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4685                 return 0;
4686         }
4687         return -ENOENT;
4688 }
4689
4690 /*
4691  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4692  * @dev: pointer to rte_eth_dev structure
4693  * @filter_op:operation will be taken.
4694  * @arg: a pointer to specific structure corresponding to the filter_op
4695  */
4696 static int
4697 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4698                                 enum rte_filter_op filter_op,
4699                                 void *arg)
4700 {
4701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4702         int ret;
4703
4704         MAC_TYPE_FILTER_SUP(hw->mac.type);
4705
4706         if (filter_op == RTE_ETH_FILTER_NOP)
4707                 return 0;
4708
4709         if (arg == NULL) {
4710                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4711                             filter_op);
4712                 return -EINVAL;
4713         }
4714
4715         switch (filter_op) {
4716         case RTE_ETH_FILTER_ADD:
4717                 ret = ixgbe_add_del_ethertype_filter(dev,
4718                         (struct rte_eth_ethertype_filter *)arg,
4719                         TRUE);
4720                 break;
4721         case RTE_ETH_FILTER_DELETE:
4722                 ret = ixgbe_add_del_ethertype_filter(dev,
4723                         (struct rte_eth_ethertype_filter *)arg,
4724                         FALSE);
4725                 break;
4726         case RTE_ETH_FILTER_GET:
4727                 ret = ixgbe_get_ethertype_filter(dev,
4728                         (struct rte_eth_ethertype_filter *)arg);
4729                 break;
4730         default:
4731                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4732                 ret = -EINVAL;
4733                 break;
4734         }
4735         return ret;
4736 }
4737
4738 static int
4739 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4740                      enum rte_filter_type filter_type,
4741                      enum rte_filter_op filter_op,
4742                      void *arg)
4743 {
4744         int ret = -EINVAL;
4745
4746         switch (filter_type) {
4747         case RTE_ETH_FILTER_NTUPLE:
4748                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4749                 break;
4750         case RTE_ETH_FILTER_ETHERTYPE:
4751                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4752                 break;
4753         case RTE_ETH_FILTER_SYN:
4754                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4755                 break;
4756         case RTE_ETH_FILTER_FDIR:
4757                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4758                 break;
4759         default:
4760                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4761                                                         filter_type);
4762                 break;
4763         }
4764
4765         return ret;
4766 }
4767
4768 static u8 *
4769 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4770                         u8 **mc_addr_ptr, u32 *vmdq)
4771 {
4772         u8 *mc_addr;
4773
4774         *vmdq = 0;
4775         mc_addr = *mc_addr_ptr;
4776         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4777         return mc_addr;
4778 }
4779
4780 static int
4781 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4782                           struct ether_addr *mc_addr_set,
4783                           uint32_t nb_mc_addr)
4784 {
4785         struct ixgbe_hw *hw;
4786         u8 *mc_addr_list;
4787
4788         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789         mc_addr_list = (u8 *)mc_addr_set;
4790         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4791                                          ixgbe_dev_addr_list_itr, TRUE);
4792 }
4793
4794 static int
4795 ixgbe_timesync_enable(struct rte_eth_dev *dev)
4796 {
4797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4798         uint32_t tsync_ctl;
4799         uint32_t tsauxc;
4800
4801         /* Enable system time for platforms where it isn't on by default. */
4802         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
4803         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
4804         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
4805
4806         /* Start incrementing the register used to timestamp PTP packets. */
4807         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
4808
4809         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4810         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
4811                         (ETHER_TYPE_1588 |
4812                          IXGBE_ETQF_FILTER_EN |
4813                          IXGBE_ETQF_1588));
4814
4815         /* Enable timestamping of received PTP packets. */
4816         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4817         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
4818         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4819
4820         /* Enable timestamping of transmitted PTP packets. */
4821         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4822         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
4823         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4824
4825         return 0;
4826 }
4827
4828 static int
4829 ixgbe_timesync_disable(struct rte_eth_dev *dev)
4830 {
4831         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4832         uint32_t tsync_ctl;
4833
4834         /* Disable timestamping of transmitted PTP packets. */
4835         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4836         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
4837         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4838
4839         /* Disable timestamping of received PTP packets. */
4840         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4841         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
4842         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4843
4844         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4845         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
4846
4847         /* Stop incrementating the System Time registers. */
4848         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
4849
4850         return 0;
4851 }
4852
4853 static int
4854 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4855                                  struct timespec *timestamp,
4856                                  uint32_t flags __rte_unused)
4857 {
4858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4859         uint32_t tsync_rxctl;
4860         uint32_t rx_stmpl;
4861         uint32_t rx_stmph;
4862
4863         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4864         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
4865                 return -EINVAL;
4866
4867         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
4868         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
4869
4870         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4871         timestamp->tv_nsec = 0;
4872
4873         return  0;
4874 }
4875
4876 static int
4877 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4878                                  struct timespec *timestamp)
4879 {
4880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881         uint32_t tsync_txctl;
4882         uint32_t tx_stmpl;
4883         uint32_t tx_stmph;
4884
4885         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4886         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
4887                 return -EINVAL;
4888
4889         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
4890         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
4891
4892         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4893         timestamp->tv_nsec = 0;
4894
4895         return  0;
4896 }
4897
4898 static int
4899 ixgbe_get_reg_length(struct rte_eth_dev *dev)
4900 {
4901         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4902         int count = 0;
4903         int g_ind = 0;
4904         const struct reg_info *reg_group;
4905         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
4906                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
4907
4908         while ((reg_group = reg_set[g_ind++]))
4909                 count += ixgbe_regs_group_count(reg_group);
4910
4911         return count;
4912 }
4913
4914 static int
4915 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4916 {
4917         int count = 0;
4918         int g_ind = 0;
4919         const struct reg_info *reg_group;
4920
4921         while ((reg_group = ixgbevf_regs[g_ind++]))
4922                 count += ixgbe_regs_group_count(reg_group);
4923
4924         return count;
4925 }
4926
4927 static int
4928 ixgbe_get_regs(struct rte_eth_dev *dev,
4929               struct rte_dev_reg_info *regs)
4930 {
4931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4932         uint32_t *data = regs->data;
4933         int g_ind = 0;
4934         int count = 0;
4935         const struct reg_info *reg_group;
4936         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
4937                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
4938
4939         /* Support only full register dump */
4940         if ((regs->length == 0) ||
4941             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
4942                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4943                         hw->device_id;
4944                 while ((reg_group = reg_set[g_ind++]))
4945                         count += ixgbe_read_regs_group(dev, &data[count],
4946                                 reg_group);
4947                 return 0;
4948         }
4949
4950         return -ENOTSUP;
4951 }
4952
4953 static int
4954 ixgbevf_get_regs(struct rte_eth_dev *dev,
4955                 struct rte_dev_reg_info *regs)
4956 {
4957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958         uint32_t *data = regs->data;
4959         int g_ind = 0;
4960         int count = 0;
4961         const struct reg_info *reg_group;
4962
4963         /* Support only full register dump */
4964         if ((regs->length == 0) ||
4965             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
4966                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
4967                         hw->device_id;
4968                 while ((reg_group = ixgbevf_regs[g_ind++]))
4969                         count += ixgbe_read_regs_group(dev, &data[count],
4970                                                       reg_group);
4971                 return 0;
4972         }
4973
4974         return -ENOTSUP;
4975 }
4976
4977 static int
4978 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
4979 {
4980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4981
4982         /* Return unit is byte count */
4983         return hw->eeprom.word_size * 2;
4984 }
4985
4986 static int
4987 ixgbe_get_eeprom(struct rte_eth_dev *dev,
4988                 struct rte_dev_eeprom_info *in_eeprom)
4989 {
4990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4991         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
4992         uint16_t *data = in_eeprom->data;
4993         int first, length;
4994
4995         first = in_eeprom->offset >> 1;
4996         length = in_eeprom->length >> 1;
4997         if ((first >= hw->eeprom.word_size) ||
4998             ((first + length) >= hw->eeprom.word_size))
4999                 return -EINVAL;
5000
5001         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5002
5003         return eeprom->ops.read_buffer(hw, first, length, data);
5004 }
5005
5006 static int
5007 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5008                 struct rte_dev_eeprom_info *in_eeprom)
5009 {
5010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5011         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5012         uint16_t *data = in_eeprom->data;
5013         int first, length;
5014
5015         first = in_eeprom->offset >> 1;
5016         length = in_eeprom->length >> 1;
5017         if ((first >= hw->eeprom.word_size) ||
5018             ((first + length) >= hw->eeprom.word_size))
5019                 return -EINVAL;
5020
5021         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5022
5023         return eeprom->ops.write_buffer(hw,  first, length, data);
5024 }
5025
5026 static struct rte_driver rte_ixgbe_driver = {
5027         .type = PMD_PDEV,
5028         .init = rte_ixgbe_pmd_init,
5029 };
5030
5031 static struct rte_driver rte_ixgbevf_driver = {
5032         .type = PMD_PDEV,
5033         .init = rte_ixgbevf_pmd_init,
5034 };
5035
5036 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5037 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);