drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define IXGBE_TIMINCA_16NS_SHIFT 24
 130 #define IXGBE_TIMINCA_INCVALUE   16000000
 131 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 132                                   | IXGBE_TIMINCA_INCVALUE)
 133
 134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 147                                 int wait_to_complete);
 148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 149                                 struct rte_eth_stats *stats);
 150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_xstats *xstats, unsigned n);
 152 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 153 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 155                                              uint16_t queue_id,
 156                                              uint8_t stat_idx,
 157                                              uint8_t is_rx);
 158 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 159                                struct rte_eth_dev_info *dev_info);
 160 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 161                                  struct rte_eth_dev_info *dev_info);
 162 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 163
 164 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 165                 uint16_t vlan_id, int on);
 166 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 167 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 168                 uint16_t queue, bool on);
 169 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 170                 int on);
 171 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 172 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 173 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 174 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 176
 177 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 179 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_fc_conf *fc_conf);
 181 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 182                                struct rte_eth_fc_conf *fc_conf);
 183 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 184                 struct rte_eth_pfc_conf *pfc_conf);
 185 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 186                         struct rte_eth_rss_reta_entry64 *reta_conf,
 187                         uint16_t reta_size);
 188 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 189                         struct rte_eth_rss_reta_entry64 *reta_conf,
 190                         uint16_t reta_size);
 191 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 192 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 193 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 195 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 196 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 197                 void *param);
 198 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 199 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 200                 uint32_t index, uint32_t pool);
 201 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 202 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 203                                            struct ether_addr *mac_addr);
 204 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 205
 206 /* For Virtual Function support */
 207 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 208 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 209 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
 210 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
 211 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 212 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 213 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 214 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 215 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 216 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 217 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 218                 struct rte_eth_stats *stats);
 219 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 220 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 221                 uint16_t vlan_id, int on);
 222 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 223                 uint16_t queue, int on);
 224 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 225 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 226 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 227                                           void *param);
 228 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 229                                             uint16_t queue_id);
 230 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 231                                              uint16_t queue_id);
 232 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 233                                  uint8_t queue, uint8_t msix_vector);
 234 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 235
 236 /* For Eth VMDQ APIs support */
 237 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 238                 ether_addr* mac_addr,uint8_t on);
 239 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 240 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 241                 uint16_t rx_mask, uint8_t on);
 242 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 243 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 244 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 245                 uint64_t pool_mask,uint8_t vlan_on);
 246 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 247                 struct rte_eth_mirror_conf *mirror_conf,
 248                 uint8_t rule_id, uint8_t on);
 249 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 250                 uint8_t rule_id);
 251 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 252                                           uint16_t queue_id);
 253 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 254                                            uint16_t queue_id);
 255 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 256                                uint8_t queue, uint8_t msix_vector);
 257 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 258
 259 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 260                 uint16_t queue_idx, uint16_t tx_rate);
 261 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 262                 uint16_t tx_rate, uint64_t q_msk);
 263
 264 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 265                                  struct ether_addr *mac_addr,
 266                                  uint32_t index, uint32_t pool);
 267 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 268 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 269                                              struct ether_addr *mac_addr);
 270 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 271                         struct rte_eth_syn_filter *filter,
 272                         bool add);
 273 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 274                         struct rte_eth_syn_filter *filter);
 275 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 276                         enum rte_filter_op filter_op,
 277                         void *arg);
 278 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 279                         struct ixgbe_5tuple_filter *filter);
 280 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 281                         struct ixgbe_5tuple_filter *filter);
 282 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 283                         struct rte_eth_ntuple_filter *filter,
 284                         bool add);
 285 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 286                                 enum rte_filter_op filter_op,
 287                                 void *arg);
 288 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 289                         struct rte_eth_ntuple_filter *filter);
 290 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 291                         struct rte_eth_ethertype_filter *filter,
 292                         bool add);
 293 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 294                                 enum rte_filter_op filter_op,
 295                                 void *arg);
 296 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 297                         struct rte_eth_ethertype_filter *filter);
 298 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 299                      enum rte_filter_type filter_type,
 300                      enum rte_filter_op filter_op,
 301                      void *arg);
 302 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 303
 304 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 305                                       struct ether_addr *mc_addr_set,
 306                                       uint32_t nb_mc_addr);
 307 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 308                                    struct rte_eth_dcb_info *dcb_info);
 309
 310 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 311 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 312                             struct rte_dev_reg_info *regs);
 313 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 314 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 315                                 struct rte_dev_eeprom_info *eeprom);
 316 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 317                                 struct rte_dev_eeprom_info *eeprom);
 318
 319 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 321                                 struct rte_dev_reg_info *regs);
 322
 323 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 324 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 325 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 326                                             struct timespec *timestamp,
 327                                             uint32_t flags);
 328 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 329                                             struct timespec *timestamp);
 330
 331 /*
 332  * Define VF Stats MACRO for Non "cleared on read" register
 333  */
 334 #define UPDATE_VF_STAT(reg, last, cur)                          \
 335 {                                                               \
 336         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 337         cur += (latest - last) & UINT_MAX;                      \
 338         last = latest;                                          \
 339 }
 340
 341 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 342 {                                                                \
 343         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 344         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 345         u64 latest = ((new_msb << 32) | new_lsb);                \
 346         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 347         last = latest;                                           \
 348 }
 349
 350 #define IXGBE_SET_HWSTRIP(h, q) do{\
 351                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 352                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 353                 (h)->bitmap[idx] |= 1 << bit;\
 354         }while(0)
 355
 356 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 357                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 358                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 359                 (h)->bitmap[idx] &= ~(1 << bit);\
 360         }while(0)
 361
 362 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 363                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 364                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 365                 (r) = (h)->bitmap[idx] >> bit & 1;\
 366         }while(0)
 367
 368 /*
 369  * The set of PCI devices this driver supports
 370  */
 371 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 372
 373 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 374 #include "rte_pci_dev_ids.h"
 375
 376 { .vendor_id = 0, /* sentinel */ },
 377 };
 378
 379
 380 /*
 381  * The set of PCI devices this driver supports (for 82599 VF)
 382  */
 383 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 384
 385 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 386 #include "rte_pci_dev_ids.h"
 387 { .vendor_id = 0, /* sentinel */ },
 388
 389 };
 390
 391 static const struct rte_eth_desc_lim rx_desc_lim = {
 392         .nb_max = IXGBE_MAX_RING_DESC,
 393         .nb_min = IXGBE_MIN_RING_DESC,
 394         .nb_align = IXGBE_RXD_ALIGN,
 395 };
 396
 397 static const struct rte_eth_desc_lim tx_desc_lim = {
 398         .nb_max = IXGBE_MAX_RING_DESC,
 399         .nb_min = IXGBE_MIN_RING_DESC,
 400         .nb_align = IXGBE_TXD_ALIGN,
 401 };
 402
 403 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 404         .dev_configure        = ixgbe_dev_configure,
 405         .dev_start            = ixgbe_dev_start,
 406         .dev_stop             = ixgbe_dev_stop,
 407         .dev_set_link_up    = ixgbe_dev_set_link_up,
 408         .dev_set_link_down  = ixgbe_dev_set_link_down,
 409         .dev_close            = ixgbe_dev_close,
 410         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 411         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 412         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 413         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 414         .link_update          = ixgbe_dev_link_update,
 415         .stats_get            = ixgbe_dev_stats_get,
 416         .xstats_get           = ixgbe_dev_xstats_get,
 417         .stats_reset          = ixgbe_dev_stats_reset,
 418         .xstats_reset         = ixgbe_dev_xstats_reset,
 419         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 420         .dev_infos_get        = ixgbe_dev_info_get,
 421         .mtu_set              = ixgbe_dev_mtu_set,
 422         .vlan_filter_set      = ixgbe_vlan_filter_set,
 423         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 424         .vlan_offload_set     = ixgbe_vlan_offload_set,
 425         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 426         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 427         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 428         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 429         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 430         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 431         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 432         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 433         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 434         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 435         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 436         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 437         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 438         .dev_led_on           = ixgbe_dev_led_on,
 439         .dev_led_off          = ixgbe_dev_led_off,
 440         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 441         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 442         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 443         .mac_addr_add         = ixgbe_add_rar,
 444         .mac_addr_remove      = ixgbe_remove_rar,
 445         .mac_addr_set         = ixgbe_set_default_mac_addr,
 446         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 447         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 448         .mirror_rule_set      = ixgbe_mirror_rule_set,
 449         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 450         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 451         .set_vf_rx            = ixgbe_set_pool_rx,
 452         .set_vf_tx            = ixgbe_set_pool_tx,
 453         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 454         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 455         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 456         .reta_update          = ixgbe_dev_rss_reta_update,
 457         .reta_query           = ixgbe_dev_rss_reta_query,
 458 #ifdef RTE_NIC_BYPASS
 459         .bypass_init          = ixgbe_bypass_init,
 460         .bypass_state_set     = ixgbe_bypass_state_store,
 461         .bypass_state_show    = ixgbe_bypass_state_show,
 462         .bypass_event_set     = ixgbe_bypass_event_store,
 463         .bypass_event_show    = ixgbe_bypass_event_show,
 464         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 465         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 466         .bypass_ver_show      = ixgbe_bypass_ver_show,
 467         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 468 #endif /* RTE_NIC_BYPASS */
 469         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 470         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 471         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 472         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 473         .rxq_info_get         = ixgbe_rxq_info_get,
 474         .txq_info_get         = ixgbe_txq_info_get,
 475         .timesync_enable      = ixgbe_timesync_enable,
 476         .timesync_disable     = ixgbe_timesync_disable,
 477         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 478         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 479         .get_reg_length       = ixgbe_get_reg_length,
 480         .get_reg              = ixgbe_get_regs,
 481         .get_eeprom_length    = ixgbe_get_eeprom_length,
 482         .get_eeprom           = ixgbe_get_eeprom,
 483         .set_eeprom           = ixgbe_set_eeprom,
 484         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 485 };
 486
 487 /*
 488  * dev_ops for virtual function, bare necessities for basic vf
 489  * operation have been implemented
 490  */
 491 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 492         .dev_configure        = ixgbevf_dev_configure,
 493         .dev_start            = ixgbevf_dev_start,
 494         .dev_stop             = ixgbevf_dev_stop,
 495         .link_update          = ixgbe_dev_link_update,
 496         .stats_get            = ixgbevf_dev_stats_get,
 497         .stats_reset          = ixgbevf_dev_stats_reset,
 498         .dev_close            = ixgbevf_dev_close,
 499         .dev_infos_get        = ixgbevf_dev_info_get,
 500         .mtu_set              = ixgbevf_dev_set_mtu,
 501         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 502         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 503         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 504         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 505         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 506         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 507         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 508         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 509         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 510         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 511         .mac_addr_add         = ixgbevf_add_mac_addr,
 512         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 513         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 514         .rxq_info_get         = ixgbe_rxq_info_get,
 515         .txq_info_get         = ixgbe_txq_info_get,
 516         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 517         .get_reg_length       = ixgbevf_get_reg_length,
 518         .get_reg              = ixgbevf_get_regs,
 519         .reta_update          = ixgbe_dev_rss_reta_update,
 520         .reta_query           = ixgbe_dev_rss_reta_query,
 521         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 522         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 523 };
 524
 525 /* store statistics names and its offset in stats structure */
 526 struct rte_ixgbe_xstats_name_off {
 527         char name[RTE_ETH_XSTATS_NAME_SIZE];
 528         unsigned offset;
 529 };
 530
 531 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 532         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 533         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 534         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 535         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 536         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 537         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 538         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 539         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 540         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 541         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 542         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 543         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 544         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 545         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 546         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 547                 prc1023)},
 548         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 549                 prc1522)},
 550         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 551         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 552         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 553         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 554         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 555         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 556         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 557         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 558         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 559         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 560         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 561         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 562         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 563         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 564         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 565         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 566         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 567                 ptc1023)},
 568         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 569                 ptc1522)},
 570         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 571         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 572         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 573         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 574
 575         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 576                 fdirustat_add)},
 577         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 578                 fdirustat_remove)},
 579         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 580                 fdirfstat_fadd)},
 581         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 582                 fdirfstat_fremove)},
 583         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 584                 fdirmatch)},
 585         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 586                 fdirmiss)},
 587
 588         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 589         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 590         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 591                 fclast)},
 592         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 593         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 594         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 595         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 596         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 597                 fcoe_noddp)},
 598         {"rx_fcoe_no_direct_data_placement_ext_buff",
 599                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 600
 601         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 602                 lxontxc)},
 603         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 604                 lxonrxc)},
 605         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 606                 lxofftxc)},
 607         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 608                 lxoffrxc)},
 609         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 610 };
 611
 612 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 613                            sizeof(rte_ixgbe_stats_strings[0]))
 614
 615 /* Per-queue statistics */
 616 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
 617 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
 618 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
 619
 620 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
 621
 622 /**
 623  * Atomically reads the link status information from global
 624  * structure rte_eth_dev.
 625  *
 626  * @param dev
 627  *   - Pointer to the structure rte_eth_dev to read from.
 628  *   - Pointer to the buffer to be saved with the link status.
 629  *
 630  * @return
 631  *   - On success, zero.
 632  *   - On failure, negative value.
 633  */
 634 static inline int
 635 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 636                                 struct rte_eth_link *link)
 637 {
 638         struct rte_eth_link *dst = link;
 639         struct rte_eth_link *src = &(dev->data->dev_link);
 640
 641         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 642                                         *(uint64_t *)src) == 0)
 643                 return -1;
 644
 645         return 0;
 646 }
 647
 648 /**
 649  * Atomically writes the link status information into global
 650  * structure rte_eth_dev.
 651  *
 652  * @param dev
 653  *   - Pointer to the structure rte_eth_dev to read from.
 654  *   - Pointer to the buffer to be saved with the link status.
 655  *
 656  * @return
 657  *   - On success, zero.
 658  *   - On failure, negative value.
 659  */
 660 static inline int
 661 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 662                                 struct rte_eth_link *link)
 663 {
 664         struct rte_eth_link *dst = &(dev->data->dev_link);
 665         struct rte_eth_link *src = link;
 666
 667         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 668                                         *(uint64_t *)src) == 0)
 669                 return -1;
 670
 671         return 0;
 672 }
 673
 674 /*
 675  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 676  */
 677 static inline int
 678 ixgbe_is_sfp(struct ixgbe_hw *hw)
 679 {
 680         switch (hw->phy.type) {
 681         case ixgbe_phy_sfp_avago:
 682         case ixgbe_phy_sfp_ftl:
 683         case ixgbe_phy_sfp_intel:
 684         case ixgbe_phy_sfp_unknown:
 685         case ixgbe_phy_sfp_passive_tyco:
 686         case ixgbe_phy_sfp_passive_unknown:
 687                 return 1;
 688         default:
 689                 return 0;
 690         }
 691 }
 692
 693 static inline int32_t
 694 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 695 {
 696         uint32_t ctrl_ext;
 697         int32_t status;
 698
 699         status = ixgbe_reset_hw(hw);
 700
 701         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 702         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 703         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 704         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 705         IXGBE_WRITE_FLUSH(hw);
 706
 707         return status;
 708 }
 709
 710 static inline void
 711 ixgbe_enable_intr(struct rte_eth_dev *dev)
 712 {
 713         struct ixgbe_interrupt *intr =
 714                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 715         struct ixgbe_hw *hw =
 716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 717
 718         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 719         IXGBE_WRITE_FLUSH(hw);
 720 }
 721
 722 /*
 723  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 724  */
 725 static void
 726 ixgbe_disable_intr(struct ixgbe_hw *hw)
 727 {
 728         PMD_INIT_FUNC_TRACE();
 729
 730         if (hw->mac.type == ixgbe_mac_82598EB) {
 731                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 732         } else {
 733                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 734                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 735                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 736         }
 737         IXGBE_WRITE_FLUSH(hw);
 738 }
 739
 740 /*
 741  * This function resets queue statistics mapping registers.
 742  * From Niantic datasheet, Initialization of Statistics section:
 743  * "...if software requires the queue counters, the RQSMR and TQSM registers
 744  * must be re-programmed following a device reset.
 745  */
 746 static void
 747 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 748 {
 749         uint32_t i;
 750
 751         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 752                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 753                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 754         }
 755 }
 756
 757
 758 static int
 759 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 760                                   uint16_t queue_id,
 761                                   uint8_t stat_idx,
 762                                   uint8_t is_rx)
 763 {
 764 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 765 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 766 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 767
 768         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 769         struct ixgbe_stat_mapping_registers *stat_mappings =
 770                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 771         uint32_t qsmr_mask = 0;
 772         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 773         uint32_t q_map;
 774         uint8_t n, offset;
 775
 776         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 777                 (hw->mac.type != ixgbe_mac_X540) &&
 778                 (hw->mac.type != ixgbe_mac_X550) &&
 779                 (hw->mac.type != ixgbe_mac_X550EM_x))
 780                 return -ENOSYS;
 781
 782         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 783                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 784                      queue_id, stat_idx);
 785
 786         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 787         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 788                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 789                 return -EIO;
 790         }
 791         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 792
 793         /* Now clear any previous stat_idx set */
 794         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 795         if (!is_rx)
 796                 stat_mappings->tqsm[n] &= ~clearing_mask;
 797         else
 798                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 799
 800         q_map = (uint32_t)stat_idx;
 801         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 802         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 803         if (!is_rx)
 804                 stat_mappings->tqsm[n] |= qsmr_mask;
 805         else
 806                 stat_mappings->rqsmr[n] |= qsmr_mask;
 807
 808         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 809                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 810                      queue_id, stat_idx);
 811         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 812                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 813
 814         /* Now write the mapping in the appropriate register */
 815         if (is_rx) {
 816                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 817                              stat_mappings->rqsmr[n], n);
 818                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 819         }
 820         else {
 821                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 822                              stat_mappings->tqsm[n], n);
 823                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 824         }
 825         return 0;
 826 }
 827
 828 static void
 829 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 830 {
 831         struct ixgbe_stat_mapping_registers *stat_mappings =
 832                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 834         int i;
 835
 836         /* write whatever was in stat mapping table to the NIC */
 837         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 838                 /* rx */
 839                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 840
 841                 /* tx */
 842                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 843         }
 844 }
 845
 846 static void
 847 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 848 {
 849         uint8_t i;
 850         struct ixgbe_dcb_tc_config *tc;
 851         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 852
 853         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 854         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 855         for (i = 0; i < dcb_max_tc; i++) {
 856                 tc = &dcb_config->tc_config[i];
 857                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 858                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 859                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 860                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 861                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 862                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 863                 tc->pfc = ixgbe_dcb_pfc_disabled;
 864         }
 865
 866         /* Initialize default user to priority mapping, UPx->TC0 */
 867         tc = &dcb_config->tc_config[0];
 868         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 869         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 870         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 871                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 872                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 873         }
 874         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 875         dcb_config->pfc_mode_enable = false;
 876         dcb_config->vt_mode = true;
 877         dcb_config->round_robin_enable = false;
 878         /* support all DCB capabilities in 82599 */
 879         dcb_config->support.capabilities = 0xFF;
 880
 881         /*we only support 4 Tcs for X540, X550 */
 882         if (hw->mac.type == ixgbe_mac_X540 ||
 883                 hw->mac.type == ixgbe_mac_X550 ||
 884                 hw->mac.type == ixgbe_mac_X550EM_x) {
 885                 dcb_config->num_tcs.pg_tcs = 4;
 886                 dcb_config->num_tcs.pfc_tcs = 4;
 887         }
 888 }
 889
 890 /*
 891  * Ensure that all locks are released before first NVM or PHY access
 892  */
 893 static void
 894 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 895 {
 896         uint16_t mask;
 897
 898         /*
 899          * Phy lock should not fail in this early stage. If this is the case,
 900          * it is due to an improper exit of the application.
 901          * So force the release of the faulty lock. Release of common lock
 902          * is done automatically by swfw_sync function.
 903          */
 904         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 905         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 906                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 907         }
 908         ixgbe_release_swfw_semaphore(hw, mask);
 909
 910         /*
 911          * These ones are more tricky since they are common to all ports; but
 912          * swfw_sync retries last long enough (1s) to be almost sure that if
 913          * lock can not be taken it is due to an improper lock of the
 914          * semaphore.
 915          */
 916         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 917         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 918                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 919         }
 920         ixgbe_release_swfw_semaphore(hw, mask);
 921 }
 922
 923 /*
 924  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 925  * It returns 0 on success.
 926  */
 927 static int
 928 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 929 {
 930         struct rte_pci_device *pci_dev;
 931         struct ixgbe_hw *hw =
 932                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 933         struct ixgbe_vfta * shadow_vfta =
 934                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 935         struct ixgbe_hwstrip *hwstrip =
 936                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 937         struct ixgbe_dcb_config *dcb_config =
 938                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 939         struct ixgbe_filter_info *filter_info =
 940                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 941         uint32_t ctrl_ext;
 942         uint16_t csum;
 943         int diag, i;
 944
 945         PMD_INIT_FUNC_TRACE();
 946
 947         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 948         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 949         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 950
 951         /*
 952          * For secondary processes, we don't initialise any further as primary
 953          * has already done this work. Only check we don't need a different
 954          * RX and TX function.
 955          */
 956         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 957                 struct ixgbe_tx_queue *txq;
 958                 /* TX queue function in primary, set by last queue initialized
 959                  * Tx queue may not initialized by primary process */
 960                 if (eth_dev->data->tx_queues) {
 961                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 962                         ixgbe_set_tx_function(eth_dev, txq);
 963                 } else {
 964                         /* Use default TX function if we get here */
 965                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 966                                              "Using default TX function.");
 967                 }
 968
 969                 ixgbe_set_rx_function(eth_dev);
 970
 971                 return 0;
 972         }
 973         pci_dev = eth_dev->pci_dev;
 974
 975         /* Vendor and Device ID need to be set before init of shared code */
 976         hw->device_id = pci_dev->id.device_id;
 977         hw->vendor_id = pci_dev->id.vendor_id;
 978         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 979         hw->allow_unsupported_sfp = 1;
 980
 981         /* Initialize the shared code (base driver) */
 982 #ifdef RTE_NIC_BYPASS
 983         diag = ixgbe_bypass_init_shared_code(hw);
 984 #else
 985         diag = ixgbe_init_shared_code(hw);
 986 #endif /* RTE_NIC_BYPASS */
 987
 988         if (diag != IXGBE_SUCCESS) {
 989                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 990                 return -EIO;
 991         }
 992
 993         /* pick up the PCI bus settings for reporting later */
 994         ixgbe_get_bus_info(hw);
 995
 996         /* Unlock any pending hardware semaphore */
 997         ixgbe_swfw_lock_reset(hw);
 998
 999         /* Initialize DCB configuration*/
1000         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1001         ixgbe_dcb_init(hw,dcb_config);
1002         /* Get Hardware Flow Control setting */
1003         hw->fc.requested_mode = ixgbe_fc_full;
1004         hw->fc.current_mode = ixgbe_fc_full;
1005         hw->fc.pause_time = IXGBE_FC_PAUSE;
1006         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1007                 hw->fc.low_water[i] = IXGBE_FC_LO;
1008                 hw->fc.high_water[i] = IXGBE_FC_HI;
1009         }
1010         hw->fc.send_xon = 1;
1011
1012         /* Make sure we have a good EEPROM before we read from it */
1013         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1014         if (diag != IXGBE_SUCCESS) {
1015                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1016                 return -EIO;
1017         }
1018
1019 #ifdef RTE_NIC_BYPASS
1020         diag = ixgbe_bypass_init_hw(hw);
1021 #else
1022         diag = ixgbe_init_hw(hw);
1023 #endif /* RTE_NIC_BYPASS */
1024
1025         /*
1026          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1027          * is called too soon after the kernel driver unbinding/binding occurs.
1028          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1029          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1030          * also called. See ixgbe_identify_phy_82599(). The reason for the
1031          * failure is not known, and only occuts when virtualisation features
1032          * are disabled in the bios. A delay of 100ms  was found to be enough by
1033          * trial-and-error, and is doubled to be safe.
1034          */
1035         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1036                 rte_delay_ms(200);
1037                 diag = ixgbe_init_hw(hw);
1038         }
1039
1040         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1041                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1042                     "LOM.  Please be aware there may be issues associated "
1043                     "with your hardware.");
1044                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1045                     "please contact your Intel or hardware representative "
1046                     "who provided you with this hardware.");
1047         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1048                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1049         if (diag) {
1050                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1051                 return -EIO;
1052         }
1053
1054         /* Reset the hw statistics */
1055         ixgbe_dev_stats_reset(eth_dev);
1056
1057         /* disable interrupt */
1058         ixgbe_disable_intr(hw);
1059
1060         /* reset mappings for queue statistics hw counters*/
1061         ixgbe_reset_qstat_mappings(hw);
1062
1063         /* Allocate memory for storing MAC addresses */
1064         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1065                         hw->mac.num_rar_entries, 0);
1066         if (eth_dev->data->mac_addrs == NULL) {
1067                 PMD_INIT_LOG(ERR,
1068                         "Failed to allocate %u bytes needed to store "
1069                         "MAC addresses",
1070                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1071                 return -ENOMEM;
1072         }
1073         /* Copy the permanent MAC address */
1074         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1075                         &eth_dev->data->mac_addrs[0]);
1076
1077         /* Allocate memory for storing hash filter MAC addresses */
1078         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1079                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1080         if (eth_dev->data->hash_mac_addrs == NULL) {
1081                 PMD_INIT_LOG(ERR,
1082                         "Failed to allocate %d bytes needed to store MAC addresses",
1083                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1084                 return -ENOMEM;
1085         }
1086
1087         /* initialize the vfta */
1088         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1089
1090         /* initialize the hw strip bitmap*/
1091         memset(hwstrip, 0, sizeof(*hwstrip));
1092
1093         /* initialize PF if max_vfs not zero */
1094         ixgbe_pf_host_init(eth_dev);
1095
1096         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1097         /* let hardware know driver is loaded */
1098         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1099         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1100         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1101         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1102         IXGBE_WRITE_FLUSH(hw);
1103
1104         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1105                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1106                              (int) hw->mac.type, (int) hw->phy.type,
1107                              (int) hw->phy.sfp_type);
1108         else
1109                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1110                              (int) hw->mac.type, (int) hw->phy.type);
1111
1112         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1113                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1114                         pci_dev->id.device_id);
1115
1116         /* enable support intr */
1117         ixgbe_enable_intr(eth_dev);
1118
1119         /* initialize 5tuple filter list */
1120         TAILQ_INIT(&filter_info->fivetuple_list);
1121         memset(filter_info->fivetuple_mask, 0,
1122                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1123
1124         return 0;
1125 }
1126
1127 static int
1128 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1129 {
1130         struct rte_pci_device *pci_dev;
1131         struct ixgbe_hw *hw;
1132
1133         PMD_INIT_FUNC_TRACE();
1134
1135         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1136                 return -EPERM;
1137
1138         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1139         pci_dev = eth_dev->pci_dev;
1140
1141         if (hw->adapter_stopped == 0)
1142                 ixgbe_dev_close(eth_dev);
1143
1144         eth_dev->dev_ops = NULL;
1145         eth_dev->rx_pkt_burst = NULL;
1146         eth_dev->tx_pkt_burst = NULL;
1147
1148         /* Unlock any pending hardware semaphore */
1149         ixgbe_swfw_lock_reset(hw);
1150
1151         /* disable uio intr before callback unregister */
1152         rte_intr_disable(&(pci_dev->intr_handle));
1153         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1154                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1155
1156         /* uninitialize PF if max_vfs not zero */
1157         ixgbe_pf_host_uninit(eth_dev);
1158
1159         rte_free(eth_dev->data->mac_addrs);
1160         eth_dev->data->mac_addrs = NULL;
1161
1162         rte_free(eth_dev->data->hash_mac_addrs);
1163         eth_dev->data->hash_mac_addrs = NULL;
1164
1165         return 0;
1166 }
1167
1168 /*
1169  * Negotiate mailbox API version with the PF.
1170  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1171  * Then we try to negotiate starting with the most recent one.
1172  * If all negotiation attempts fail, then we will proceed with
1173  * the default one (ixgbe_mbox_api_10).
1174  */
1175 static void
1176 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1177 {
1178         int32_t i;
1179
1180         /* start with highest supported, proceed down */
1181         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1182                 ixgbe_mbox_api_11,
1183                 ixgbe_mbox_api_10,
1184         };
1185
1186         for (i = 0;
1187                         i != RTE_DIM(sup_ver) &&
1188                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1189                         i++)
1190                 ;
1191 }
1192
1193 static void
1194 generate_random_mac_addr(struct ether_addr *mac_addr)
1195 {
1196         uint64_t random;
1197
1198         /* Set Organizationally Unique Identifier (OUI) prefix. */
1199         mac_addr->addr_bytes[0] = 0x00;
1200         mac_addr->addr_bytes[1] = 0x09;
1201         mac_addr->addr_bytes[2] = 0xC0;
1202         /* Force indication of locally assigned MAC address. */
1203         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1204         /* Generate the last 3 bytes of the MAC address with a random number. */
1205         random = rte_rand();
1206         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1207 }
1208
1209 /*
1210  * Virtual Function device init
1211  */
1212 static int
1213 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1214 {
1215         int diag;
1216         uint32_t tc, tcs;
1217         struct rte_pci_device *pci_dev;
1218         struct ixgbe_hw *hw =
1219                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1220         struct ixgbe_vfta * shadow_vfta =
1221                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1222         struct ixgbe_hwstrip *hwstrip =
1223                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1224         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1225
1226         PMD_INIT_FUNC_TRACE();
1227
1228         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1229         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1230         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1231
1232         /* for secondary processes, we don't initialise any further as primary
1233          * has already done this work. Only check we don't need a different
1234          * RX function */
1235         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1236                 if (eth_dev->data->scattered_rx)
1237                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1238                 return 0;
1239         }
1240
1241         pci_dev = eth_dev->pci_dev;
1242
1243         hw->device_id = pci_dev->id.device_id;
1244         hw->vendor_id = pci_dev->id.vendor_id;
1245         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1246
1247         /* initialize the vfta */
1248         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1249
1250         /* initialize the hw strip bitmap*/
1251         memset(hwstrip, 0, sizeof(*hwstrip));
1252
1253         /* Initialize the shared code (base driver) */
1254         diag = ixgbe_init_shared_code(hw);
1255         if (diag != IXGBE_SUCCESS) {
1256                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1257                 return -EIO;
1258         }
1259
1260         /* init_mailbox_params */
1261         hw->mbx.ops.init_params(hw);
1262
1263         /* Reset the hw statistics */
1264         ixgbevf_dev_stats_reset(eth_dev);
1265
1266         /* Disable the interrupts for VF */
1267         ixgbevf_intr_disable(hw);
1268
1269         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1270         diag = hw->mac.ops.reset_hw(hw);
1271
1272         /*
1273          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1274          * the underlying PF driver has not assigned a MAC address to the VF.
1275          * In this case, assign a random MAC address.
1276          */
1277         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1278                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1279                 return (diag);
1280         }
1281
1282         /* negotiate mailbox API version to use with the PF. */
1283         ixgbevf_negotiate_api(hw);
1284
1285         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1286         ixgbevf_get_queues(hw, &tcs, &tc);
1287
1288         /* Allocate memory for storing MAC addresses */
1289         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1290                         hw->mac.num_rar_entries, 0);
1291         if (eth_dev->data->mac_addrs == NULL) {
1292                 PMD_INIT_LOG(ERR,
1293                         "Failed to allocate %u bytes needed to store "
1294                         "MAC addresses",
1295                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1296                 return -ENOMEM;
1297         }
1298
1299         /* Generate a random MAC address, if none was assigned by PF. */
1300         if (is_zero_ether_addr(perm_addr)) {
1301                 generate_random_mac_addr(perm_addr);
1302                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1303                 if (diag) {
1304                         rte_free(eth_dev->data->mac_addrs);
1305                         eth_dev->data->mac_addrs = NULL;
1306                         return diag;
1307                 }
1308                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1309                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1310                              "%02x:%02x:%02x:%02x:%02x:%02x",
1311                              perm_addr->addr_bytes[0],
1312                              perm_addr->addr_bytes[1],
1313                              perm_addr->addr_bytes[2],
1314                              perm_addr->addr_bytes[3],
1315                              perm_addr->addr_bytes[4],
1316                              perm_addr->addr_bytes[5]);
1317         }
1318
1319         /* Copy the permanent MAC address */
1320         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1321
1322         /* reset the hardware with the new settings */
1323         diag = hw->mac.ops.start_hw(hw);
1324         switch (diag) {
1325                 case  0:
1326                         break;
1327
1328                 default:
1329                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1330                         return (-EIO);
1331         }
1332
1333         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1334                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1335                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1336
1337         return 0;
1338 }
1339
1340 /* Virtual Function device uninit */
1341
1342 static int
1343 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1344 {
1345         struct ixgbe_hw *hw;
1346         unsigned i;
1347
1348         PMD_INIT_FUNC_TRACE();
1349
1350         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1351                 return -EPERM;
1352
1353         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1354
1355         if (hw->adapter_stopped == 0)
1356                 ixgbevf_dev_close(eth_dev);
1357
1358         eth_dev->dev_ops = NULL;
1359         eth_dev->rx_pkt_burst = NULL;
1360         eth_dev->tx_pkt_burst = NULL;
1361
1362         /* Disable the interrupts for VF */
1363         ixgbevf_intr_disable(hw);
1364
1365         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1366                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1367                 eth_dev->data->rx_queues[i] = NULL;
1368         }
1369         eth_dev->data->nb_rx_queues = 0;
1370
1371         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1372                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1373                 eth_dev->data->tx_queues[i] = NULL;
1374         }
1375         eth_dev->data->nb_tx_queues = 0;
1376
1377         rte_free(eth_dev->data->mac_addrs);
1378         eth_dev->data->mac_addrs = NULL;
1379
1380         return 0;
1381 }
1382
1383 static struct eth_driver rte_ixgbe_pmd = {
1384         .pci_drv = {
1385                 .name = "rte_ixgbe_pmd",
1386                 .id_table = pci_id_ixgbe_map,
1387                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1388                         RTE_PCI_DRV_DETACHABLE,
1389         },
1390         .eth_dev_init = eth_ixgbe_dev_init,
1391         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1392         .dev_private_size = sizeof(struct ixgbe_adapter),
1393 };
1394
1395 /*
1396  * virtual function driver struct
1397  */
1398 static struct eth_driver rte_ixgbevf_pmd = {
1399         .pci_drv = {
1400                 .name = "rte_ixgbevf_pmd",
1401                 .id_table = pci_id_ixgbevf_map,
1402                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1403         },
1404         .eth_dev_init = eth_ixgbevf_dev_init,
1405         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1406         .dev_private_size = sizeof(struct ixgbe_adapter),
1407 };
1408
1409 /*
1410  * Driver initialization routine.
1411  * Invoked once at EAL init time.
1412  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1413  */
1414 static int
1415 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1416 {
1417         PMD_INIT_FUNC_TRACE();
1418
1419         rte_eth_driver_register(&rte_ixgbe_pmd);
1420         return 0;
1421 }
1422
1423 /*
1424  * VF Driver initialization routine.
1425  * Invoked one at EAL init time.
1426  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1427  */
1428 static int
1429 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1430 {
1431         PMD_INIT_FUNC_TRACE();
1432
1433         rte_eth_driver_register(&rte_ixgbevf_pmd);
1434         return (0);
1435 }
1436
1437 static int
1438 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1439 {
1440         struct ixgbe_hw *hw =
1441                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1442         struct ixgbe_vfta * shadow_vfta =
1443                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1444         uint32_t vfta;
1445         uint32_t vid_idx;
1446         uint32_t vid_bit;
1447
1448         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1449         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1450         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1451         if (on)
1452                 vfta |= vid_bit;
1453         else
1454                 vfta &= ~vid_bit;
1455         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1456
1457         /* update local VFTA copy */
1458         shadow_vfta->vfta[vid_idx] = vfta;
1459
1460         return 0;
1461 }
1462
1463 static void
1464 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1465 {
1466         if (on)
1467                 ixgbe_vlan_hw_strip_enable(dev, queue);
1468         else
1469                 ixgbe_vlan_hw_strip_disable(dev, queue);
1470 }
1471
1472 static void
1473 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1474 {
1475         struct ixgbe_hw *hw =
1476                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477
1478         /* Only the high 16-bits is valid */
1479         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1480 }
1481
1482 void
1483 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1484 {
1485         struct ixgbe_hw *hw =
1486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1487         uint32_t vlnctrl;
1488
1489         PMD_INIT_FUNC_TRACE();
1490
1491         /* Filter Table Disable */
1492         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1493         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1494
1495         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1496 }
1497
1498 void
1499 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1500 {
1501         struct ixgbe_hw *hw =
1502                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1503         struct ixgbe_vfta * shadow_vfta =
1504                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1505         uint32_t vlnctrl;
1506         uint16_t i;
1507
1508         PMD_INIT_FUNC_TRACE();
1509
1510         /* Filter Table Enable */
1511         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1512         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1513         vlnctrl |= IXGBE_VLNCTRL_VFE;
1514
1515         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1516
1517         /* write whatever is in local vfta copy */
1518         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1519                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1520 }
1521
1522 static void
1523 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1524 {
1525         struct ixgbe_hwstrip *hwstrip =
1526                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1527
1528         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1529                 return;
1530
1531         if (on)
1532                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1533         else
1534                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1535 }
1536
1537 static void
1538 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1539 {
1540         struct ixgbe_hw *hw =
1541                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542         uint32_t ctrl;
1543
1544         PMD_INIT_FUNC_TRACE();
1545
1546         if (hw->mac.type == ixgbe_mac_82598EB) {
1547                 /* No queue level support */
1548                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1549                 return;
1550         }
1551         else {
1552                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1553                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1554                 ctrl &= ~IXGBE_RXDCTL_VME;
1555                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1556         }
1557         /* record those setting for HW strip per queue */
1558         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1559 }
1560
1561 static void
1562 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1563 {
1564         struct ixgbe_hw *hw =
1565                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1566         uint32_t ctrl;
1567
1568         PMD_INIT_FUNC_TRACE();
1569
1570         if (hw->mac.type == ixgbe_mac_82598EB) {
1571                 /* No queue level supported */
1572                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1573                 return;
1574         }
1575         else {
1576                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1577                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1578                 ctrl |= IXGBE_RXDCTL_VME;
1579                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1580         }
1581         /* record those setting for HW strip per queue */
1582         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1583 }
1584
1585 void
1586 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1587 {
1588         struct ixgbe_hw *hw =
1589                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1590         uint32_t ctrl;
1591         uint16_t i;
1592
1593         PMD_INIT_FUNC_TRACE();
1594
1595         if (hw->mac.type == ixgbe_mac_82598EB) {
1596                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1597                 ctrl &= ~IXGBE_VLNCTRL_VME;
1598                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1599         }
1600         else {
1601                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1602                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1603                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1604                         ctrl &= ~IXGBE_RXDCTL_VME;
1605                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1606
1607                         /* record those setting for HW strip per queue */
1608                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1609                 }
1610         }
1611 }
1612
1613 void
1614 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1615 {
1616         struct ixgbe_hw *hw =
1617                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618         uint32_t ctrl;
1619         uint16_t i;
1620
1621         PMD_INIT_FUNC_TRACE();
1622
1623         if (hw->mac.type == ixgbe_mac_82598EB) {
1624                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1625                 ctrl |= IXGBE_VLNCTRL_VME;
1626                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1627         }
1628         else {
1629                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1630                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1631                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1632                         ctrl |= IXGBE_RXDCTL_VME;
1633                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1634
1635                         /* record those setting for HW strip per queue */
1636                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1637                 }
1638         }
1639 }
1640
1641 static void
1642 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1643 {
1644         struct ixgbe_hw *hw =
1645                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1646         uint32_t ctrl;
1647
1648         PMD_INIT_FUNC_TRACE();
1649
1650         /* DMATXCTRL: Geric Double VLAN Disable */
1651         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1652         ctrl &= ~IXGBE_DMATXCTL_GDV;
1653         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1654
1655         /* CTRL_EXT: Global Double VLAN Disable */
1656         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1657         ctrl &= ~IXGBE_EXTENDED_VLAN;
1658         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1659
1660 }
1661
1662 static void
1663 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1664 {
1665         struct ixgbe_hw *hw =
1666                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667         uint32_t ctrl;
1668
1669         PMD_INIT_FUNC_TRACE();
1670
1671         /* DMATXCTRL: Geric Double VLAN Enable */
1672         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1673         ctrl |= IXGBE_DMATXCTL_GDV;
1674         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1675
1676         /* CTRL_EXT: Global Double VLAN Enable */
1677         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1678         ctrl |= IXGBE_EXTENDED_VLAN;
1679         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1680
1681         /*
1682          * VET EXT field in the EXVET register = 0x8100 by default
1683          * So no need to change. Same to VT field of DMATXCTL register
1684          */
1685 }
1686
1687 static void
1688 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1689 {
1690         if(mask & ETH_VLAN_STRIP_MASK){
1691                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1692                         ixgbe_vlan_hw_strip_enable_all(dev);
1693                 else
1694                         ixgbe_vlan_hw_strip_disable_all(dev);
1695         }
1696
1697         if(mask & ETH_VLAN_FILTER_MASK){
1698                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1699                         ixgbe_vlan_hw_filter_enable(dev);
1700                 else
1701                         ixgbe_vlan_hw_filter_disable(dev);
1702         }
1703
1704         if(mask & ETH_VLAN_EXTEND_MASK){
1705                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1706                         ixgbe_vlan_hw_extend_enable(dev);
1707                 else
1708                         ixgbe_vlan_hw_extend_disable(dev);
1709         }
1710 }
1711
1712 static void
1713 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1714 {
1715         struct ixgbe_hw *hw =
1716                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1717         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1718         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1719         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1720         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1721 }
1722
1723 static int
1724 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1725 {
1726         switch (nb_rx_q) {
1727         case 1:
1728         case 2:
1729                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1730                 break;
1731         case 4:
1732                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1733                 break;
1734         default:
1735                 return -EINVAL;
1736         }
1737
1738         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1739         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1740
1741         return 0;
1742 }
1743
1744 static int
1745 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1746 {
1747         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1748         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1749         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1750
1751         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1752                 /* check multi-queue mode */
1753                 switch (dev_conf->rxmode.mq_mode) {
1754                 case ETH_MQ_RX_VMDQ_DCB:
1755                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1756                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1757                         PMD_INIT_LOG(ERR, "SRIOV active,"
1758                                         " unsupported mq_mode rx %d.",
1759                                         dev_conf->rxmode.mq_mode);
1760                         return -EINVAL;
1761                 case ETH_MQ_RX_RSS:
1762                 case ETH_MQ_RX_VMDQ_RSS:
1763                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1764                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1765                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1766                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1767                                                 " invalid queue number"
1768                                                 " for VMDQ RSS, allowed"
1769                                                 " value are 1, 2 or 4.");
1770                                         return -EINVAL;
1771                                 }
1772                         break;
1773                 case ETH_MQ_RX_VMDQ_ONLY:
1774                 case ETH_MQ_RX_NONE:
1775                         /* if nothing mq mode configure, use default scheme */
1776                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1777                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1778                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1779                         break;
1780                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1781                         /* SRIOV only works in VMDq enable mode */
1782                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1783                                         " wrong mq_mode rx %d.",
1784                                         dev_conf->rxmode.mq_mode);
1785                         return -EINVAL;
1786                 }
1787
1788                 switch (dev_conf->txmode.mq_mode) {
1789                 case ETH_MQ_TX_VMDQ_DCB:
1790                         /* DCB VMDQ in SRIOV mode, not implement yet */
1791                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1792                                         " unsupported VMDQ mq_mode tx %d.",
1793                                         dev_conf->txmode.mq_mode);
1794                         return -EINVAL;
1795                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1796                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1797                         break;
1798                 }
1799
1800                 /* check valid queue number */
1801                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1802                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1803                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1804                                         " queue number must less equal to %d.",
1805                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1806                         return -EINVAL;
1807                 }
1808         } else {
1809                 /* check configuration for vmdb+dcb mode */
1810                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1811                         const struct rte_eth_vmdq_dcb_conf *conf;
1812
1813                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1814                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1815                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1816                                 return -EINVAL;
1817                         }
1818                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1819                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1820                                conf->nb_queue_pools == ETH_32_POOLS)) {
1821                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1822                                                 " nb_queue_pools must be %d or %d.",
1823                                                 ETH_16_POOLS, ETH_32_POOLS);
1824                                 return -EINVAL;
1825                         }
1826                 }
1827                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1828                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1829
1830                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1831                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1832                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1833                                 return -EINVAL;
1834                         }
1835                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1836                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1837                                conf->nb_queue_pools == ETH_32_POOLS)) {
1838                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1839                                                 " nb_queue_pools != %d and"
1840                                                 " nb_queue_pools != %d.",
1841                                                 ETH_16_POOLS, ETH_32_POOLS);
1842                                 return -EINVAL;
1843                         }
1844                 }
1845
1846                 /* For DCB mode check our configuration before we go further */
1847                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1848                         const struct rte_eth_dcb_rx_conf *conf;
1849
1850                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1851                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1852                                                  IXGBE_DCB_NB_QUEUES);
1853                                 return -EINVAL;
1854                         }
1855                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1856                         if (!(conf->nb_tcs == ETH_4_TCS ||
1857                                conf->nb_tcs == ETH_8_TCS)) {
1858                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1859                                                 " and nb_tcs != %d.",
1860                                                 ETH_4_TCS, ETH_8_TCS);
1861                                 return -EINVAL;
1862                         }
1863                 }
1864
1865                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1866                         const struct rte_eth_dcb_tx_conf *conf;
1867
1868                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1869                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1870                                                  IXGBE_DCB_NB_QUEUES);
1871                                 return -EINVAL;
1872                         }
1873                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1874                         if (!(conf->nb_tcs == ETH_4_TCS ||
1875                                conf->nb_tcs == ETH_8_TCS)) {
1876                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1877                                                 " and nb_tcs != %d.",
1878                                                 ETH_4_TCS, ETH_8_TCS);
1879                                 return -EINVAL;
1880                         }
1881                 }
1882         }
1883         return 0;
1884 }
1885
1886 static int
1887 ixgbe_dev_configure(struct rte_eth_dev *dev)
1888 {
1889         struct ixgbe_interrupt *intr =
1890                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1891         struct ixgbe_adapter *adapter =
1892                 (struct ixgbe_adapter *)dev->data->dev_private;
1893         int ret;
1894
1895         PMD_INIT_FUNC_TRACE();
1896         /* multipe queue mode checking */
1897         ret  = ixgbe_check_mq_mode(dev);
1898         if (ret != 0) {
1899                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1900                             ret);
1901                 return ret;
1902         }
1903
1904         /* set flag to update link status after init */
1905         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1906
1907         /*
1908          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1909          * allocation or vector Rx preconditions we will reset it.
1910          */
1911         adapter->rx_bulk_alloc_allowed = true;
1912         adapter->rx_vec_allowed = true;
1913
1914         return 0;
1915 }
1916
1917 /*
1918  * Configure device link speed and setup link.
1919  * It returns 0 on success.
1920  */
1921 static int
1922 ixgbe_dev_start(struct rte_eth_dev *dev)
1923 {
1924         struct ixgbe_hw *hw =
1925                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         struct ixgbe_vf_info *vfinfo =
1927                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1928         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1929         uint32_t intr_vector = 0;
1930         int err, link_up = 0, negotiate = 0;
1931         uint32_t speed = 0;
1932         int mask = 0;
1933         int status;
1934         uint16_t vf, idx;
1935
1936         PMD_INIT_FUNC_TRACE();
1937
1938         /* IXGBE devices don't support half duplex */
1939         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1940                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1941                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1942                              dev->data->dev_conf.link_duplex,
1943                              dev->data->port_id);
1944                 return -EINVAL;
1945         }
1946
1947         /* stop adapter */
1948         hw->adapter_stopped = 0;
1949         ixgbe_stop_adapter(hw);
1950
1951         /* reinitialize adapter
1952          * this calls reset and start */
1953         status = ixgbe_pf_reset_hw(hw);
1954         if (status != 0)
1955                 return -1;
1956         hw->mac.ops.start_hw(hw);
1957         hw->mac.get_link_status = true;
1958
1959         /* configure PF module if SRIOV enabled */
1960         ixgbe_pf_host_configure(dev);
1961
1962         /* check and configure queue intr-vector mapping */
1963         if (dev->data->dev_conf.intr_conf.rxq != 0)
1964                 intr_vector = dev->data->nb_rx_queues;
1965
1966         if (rte_intr_efd_enable(intr_handle, intr_vector))
1967                 return -1;
1968
1969         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1970                 intr_handle->intr_vec =
1971                         rte_zmalloc("intr_vec",
1972                                     dev->data->nb_rx_queues * sizeof(int),
1973                                     0);
1974                 if (intr_handle->intr_vec == NULL) {
1975                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1976                                      " intr_vec\n", dev->data->nb_rx_queues);
1977                         return -ENOMEM;
1978                 }
1979         }
1980
1981         /* confiugre msix for sleep until rx interrupt */
1982         ixgbe_configure_msix(dev);
1983
1984         /* initialize transmission unit */
1985         ixgbe_dev_tx_init(dev);
1986
1987         /* This can fail when allocating mbufs for descriptor rings */
1988         err = ixgbe_dev_rx_init(dev);
1989         if (err) {
1990                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1991                 goto error;
1992         }
1993
1994         err = ixgbe_dev_rxtx_start(dev);
1995         if (err < 0) {
1996                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1997                 goto error;
1998         }
1999
2000         /* Skip link setup if loopback mode is enabled for 82599. */
2001         if (hw->mac.type == ixgbe_mac_82599EB &&
2002                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2003                 goto skip_link_setup;
2004
2005         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2006                 err = hw->mac.ops.setup_sfp(hw);
2007                 if (err)
2008                         goto error;
2009         }
2010
2011         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2012                 /* Turn on the copper */
2013                 ixgbe_set_phy_power(hw, true);
2014         } else {
2015                 /* Turn on the laser */
2016                 ixgbe_enable_tx_laser(hw);
2017         }
2018
2019         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2020         if (err)
2021                 goto error;
2022         dev->data->dev_link.link_status = link_up;
2023
2024         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2025         if (err)
2026                 goto error;
2027
2028         switch(dev->data->dev_conf.link_speed) {
2029         case ETH_LINK_SPEED_AUTONEG:
2030                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2031                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2032                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2033                 break;
2034         case ETH_LINK_SPEED_100:
2035                 /*
2036                  * Invalid for 82598 but error will be detected by
2037                  * ixgbe_setup_link()
2038                  */
2039                 speed = IXGBE_LINK_SPEED_100_FULL;
2040                 break;
2041         case ETH_LINK_SPEED_1000:
2042                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2043                 break;
2044         case ETH_LINK_SPEED_10000:
2045                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2046                 break;
2047         default:
2048                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2049                              dev->data->dev_conf.link_speed,
2050                              dev->data->port_id);
2051                 goto error;
2052         }
2053
2054         err = ixgbe_setup_link(hw, speed, link_up);
2055         if (err)
2056                 goto error;
2057
2058 skip_link_setup:
2059
2060         /* check if lsc interrupt is enabled */
2061         if (dev->data->dev_conf.intr_conf.lsc != 0) {
2062                 if (rte_intr_allow_others(intr_handle)) {
2063                         rte_intr_callback_register(intr_handle,
2064                                                    ixgbe_dev_interrupt_handler,
2065                                                    (void *)dev);
2066                         ixgbe_dev_lsc_interrupt_setup(dev);
2067                 } else
2068                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2069                                      " no intr multiplex\n");
2070         }
2071
2072         /* check if rxq interrupt is enabled */
2073         if (dev->data->dev_conf.intr_conf.rxq != 0)
2074                 ixgbe_dev_rxq_interrupt_setup(dev);
2075
2076         /* enable uio/vfio intr/eventfd mapping */
2077         rte_intr_enable(intr_handle);
2078
2079         /* resume enabled intr since hw reset */
2080         ixgbe_enable_intr(dev);
2081
2082         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2083                 ETH_VLAN_EXTEND_MASK;
2084         ixgbe_vlan_offload_set(dev, mask);
2085
2086         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2087                 /* Enable vlan filtering for VMDq */
2088                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2089         }
2090
2091         /* Configure DCB hw */
2092         ixgbe_configure_dcb(dev);
2093
2094         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2095                 err = ixgbe_fdir_configure(dev);
2096                 if (err)
2097                         goto error;
2098         }
2099
2100         /* Restore vf rate limit */
2101         if (vfinfo != NULL) {
2102                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2103                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2104                                 if (vfinfo[vf].tx_rate[idx] != 0)
2105                                         ixgbe_set_vf_rate_limit(dev, vf,
2106                                                 vfinfo[vf].tx_rate[idx],
2107                                                 1 << idx);
2108         }
2109
2110         ixgbe_restore_statistics_mapping(dev);
2111
2112         return (0);
2113
2114 error:
2115         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2116         ixgbe_dev_clear_queues(dev);
2117         return -EIO;
2118 }
2119
2120 /*
2121  * Stop device: disable rx and tx functions to allow for reconfiguring.
2122  */
2123 static void
2124 ixgbe_dev_stop(struct rte_eth_dev *dev)
2125 {
2126         struct rte_eth_link link;
2127         struct ixgbe_hw *hw =
2128                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2129         struct ixgbe_vf_info *vfinfo =
2130                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2131         struct ixgbe_filter_info *filter_info =
2132                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2133         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2134         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2135         int vf;
2136
2137         PMD_INIT_FUNC_TRACE();
2138
2139         /* disable interrupts */
2140         ixgbe_disable_intr(hw);
2141
2142         /* disable intr eventfd mapping */
2143         rte_intr_disable(intr_handle);
2144
2145         /* reset the NIC */
2146         ixgbe_pf_reset_hw(hw);
2147         hw->adapter_stopped = 0;
2148
2149         /* stop adapter */
2150         ixgbe_stop_adapter(hw);
2151
2152         for (vf = 0; vfinfo != NULL &&
2153                      vf < dev->pci_dev->max_vfs; vf++)
2154                 vfinfo[vf].clear_to_send = false;
2155
2156         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2157                 /* Turn off the copper */
2158                 ixgbe_set_phy_power(hw, false);
2159         } else {
2160                 /* Turn off the laser */
2161                 ixgbe_disable_tx_laser(hw);
2162         }
2163
2164         ixgbe_dev_clear_queues(dev);
2165
2166         /* Clear stored conf */
2167         dev->data->scattered_rx = 0;
2168         dev->data->lro = 0;
2169
2170         /* Clear recorded link status */
2171         memset(&link, 0, sizeof(link));
2172         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2173
2174         /* Remove all ntuple filters of the device */
2175         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2176              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2177                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2178                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2179                              p_5tuple, entries);
2180                 rte_free(p_5tuple);
2181         }
2182         memset(filter_info->fivetuple_mask, 0,
2183                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2184
2185         /* Clean datapath event and queue/vec mapping */
2186         rte_intr_efd_disable(intr_handle);
2187         if (intr_handle->intr_vec != NULL) {
2188                 rte_free(intr_handle->intr_vec);
2189                 intr_handle->intr_vec = NULL;
2190         }
2191 }
2192
2193 /*
2194  * Set device link up: enable tx.
2195  */
2196 static int
2197 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2198 {
2199         struct ixgbe_hw *hw =
2200                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201         if (hw->mac.type == ixgbe_mac_82599EB) {
2202 #ifdef RTE_NIC_BYPASS
2203                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2204                         /* Not suported in bypass mode */
2205                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2206                                      "by device id 0x%x", hw->device_id);
2207                         return -ENOTSUP;
2208                 }
2209 #endif
2210         }
2211
2212         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2213                 /* Turn on the copper */
2214                 ixgbe_set_phy_power(hw, true);
2215         } else {
2216                 /* Turn on the laser */
2217                 ixgbe_enable_tx_laser(hw);
2218         }
2219
2220         return 0;
2221 }
2222
2223 /*
2224  * Set device link down: disable tx.
2225  */
2226 static int
2227 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2228 {
2229         struct ixgbe_hw *hw =
2230                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2231         if (hw->mac.type == ixgbe_mac_82599EB) {
2232 #ifdef RTE_NIC_BYPASS
2233                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2234                         /* Not suported in bypass mode */
2235                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2236                                      "by device id 0x%x", hw->device_id);
2237                         return -ENOTSUP;
2238                 }
2239 #endif
2240         }
2241
2242         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2243                 /* Turn off the copper */
2244                 ixgbe_set_phy_power(hw, false);
2245         } else {
2246                 /* Turn off the laser */
2247                 ixgbe_disable_tx_laser(hw);
2248         }
2249
2250         return 0;
2251 }
2252
2253 /*
2254  * Reest and stop device.
2255  */
2256 static void
2257 ixgbe_dev_close(struct rte_eth_dev *dev)
2258 {
2259         struct ixgbe_hw *hw =
2260                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261
2262         PMD_INIT_FUNC_TRACE();
2263
2264         ixgbe_pf_reset_hw(hw);
2265
2266         ixgbe_dev_stop(dev);
2267         hw->adapter_stopped = 1;
2268
2269         ixgbe_dev_free_queues(dev);
2270
2271         ixgbe_disable_pcie_master(hw);
2272
2273         /* reprogram the RAR[0] in case user changed it. */
2274         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2275 }
2276
2277 static void
2278 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2279                                                    *hw_stats, uint64_t *total_missed_rx,
2280                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2281                                                    uint64_t *total_qprdc)
2282 {
2283         uint32_t bprc, lxon, lxoff, total;
2284         unsigned i;
2285
2286         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2287         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2288         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2289         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2290
2291         for (i = 0; i < 8; i++) {
2292                 uint32_t mp;
2293                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2294                 /* global total per queue */
2295                 hw_stats->mpc[i] += mp;
2296                 /* Running comprehensive total for stats display */
2297                 *total_missed_rx += hw_stats->mpc[i];
2298                 if (hw->mac.type == ixgbe_mac_82598EB) {
2299                         hw_stats->rnbc[i] +=
2300                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2301                         hw_stats->pxonrxc[i] +=
2302                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2303                         hw_stats->pxoffrxc[i] +=
2304                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2305                 } else {
2306                         hw_stats->pxonrxc[i] +=
2307                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2308                         hw_stats->pxoffrxc[i] +=
2309                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2310                         hw_stats->pxon2offc[i] +=
2311                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2312                 }
2313                 hw_stats->pxontxc[i] +=
2314                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2315                 hw_stats->pxofftxc[i] +=
2316                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2317         }
2318         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2319                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2320                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2321                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2322                 hw_stats->qbrc[i] +=
2323                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2324                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2325                 hw_stats->qbtc[i] +=
2326                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2327                 *total_qprdc += hw_stats->qprdc[i] +=
2328                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2329
2330                 *total_qprc += hw_stats->qprc[i];
2331                 *total_qbrc += hw_stats->qbrc[i];
2332         }
2333         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2334         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2335         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2336
2337         /* Note that gprc counts missed packets */
2338         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2339
2340         if (hw->mac.type != ixgbe_mac_82598EB) {
2341                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2342                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2343                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2344                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2345                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2346                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2347                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2348                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2349         } else {
2350                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2351                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2352                 /* 82598 only has a counter in the high register */
2353                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2354                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2355                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2356         }
2357
2358         /*
2359          * Workaround: mprc hardware is incorrectly counting
2360          * broadcasts, so for now we subtract those.
2361          */
2362         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2363         hw_stats->bprc += bprc;
2364         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2365         if (hw->mac.type == ixgbe_mac_82598EB)
2366                 hw_stats->mprc -= bprc;
2367
2368         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2369         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2370         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2371         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2372         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2373         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2374
2375         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2376         hw_stats->lxontxc += lxon;
2377         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2378         hw_stats->lxofftxc += lxoff;
2379         total = lxon + lxoff;
2380
2381         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2382         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2383         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2384         hw_stats->gptc -= total;
2385         hw_stats->mptc -= total;
2386         hw_stats->ptc64 -= total;
2387         hw_stats->gotc -= total * ETHER_MIN_LEN;
2388
2389         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2390         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2391         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2392         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2393         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2394         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2395         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2396         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2397         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2398         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2399         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2400         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2401         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2402         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2403         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2404         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2405         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2406         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2407         /* Only read FCOE on 82599 */
2408         if (hw->mac.type != ixgbe_mac_82598EB) {
2409                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2410                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2411                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2412                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2413                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2414         }
2415
2416         /* Flow Director Stats registers */
2417         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2418         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2419 }
2420
2421 /*
2422  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2423  */
2424 static void
2425 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2426 {
2427         struct ixgbe_hw *hw =
2428                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429         struct ixgbe_hw_stats *hw_stats =
2430                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2431         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2432         unsigned i;
2433
2434         total_missed_rx = 0;
2435         total_qbrc = 0;
2436         total_qprc = 0;
2437         total_qprdc = 0;
2438
2439         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2440                         &total_qprc, &total_qprdc);
2441
2442         if (stats == NULL)
2443                 return;
2444
2445         /* Fill out the rte_eth_stats statistics structure */
2446         stats->ipackets = total_qprc;
2447         stats->ibytes = total_qbrc;
2448         stats->opackets = hw_stats->gptc;
2449         stats->obytes = hw_stats->gotc;
2450
2451         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2452                 stats->q_ipackets[i] = hw_stats->qprc[i];
2453                 stats->q_opackets[i] = hw_stats->qptc[i];
2454                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2455                 stats->q_obytes[i] = hw_stats->qbtc[i];
2456                 stats->q_errors[i] = hw_stats->qprdc[i];
2457         }
2458
2459         /* Rx Errors */
2460         stats->ierrors  = hw_stats->crcerrs +
2461                           hw_stats->mspdc +
2462                           hw_stats->rlec +
2463                           hw_stats->ruc +
2464                           hw_stats->roc +
2465                           total_missed_rx +
2466                           hw_stats->illerrc +
2467                           hw_stats->errbc +
2468                           hw_stats->xec +
2469                           hw_stats->mlfc +
2470                           hw_stats->mrfc +
2471                           hw_stats->rfc +
2472                           hw_stats->fccrc +
2473                           hw_stats->fclast;
2474
2475         /* Tx Errors */
2476         stats->oerrors  = 0;
2477 }
2478
2479 static void
2480 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2481 {
2482         struct ixgbe_hw_stats *stats =
2483                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2484
2485         /* HW registers are cleared on read */
2486         ixgbe_dev_stats_get(dev, NULL);
2487
2488         /* Reset software totals */
2489         memset(stats, 0, sizeof(*stats));
2490 }
2491
2492 static int
2493 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2494                                          unsigned n)
2495 {
2496         struct ixgbe_hw *hw =
2497                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2498         struct ixgbe_hw_stats *hw_stats =
2499                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2500         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2501         unsigned i, count = IXGBE_NB_XSTATS;
2502
2503         if (n < count)
2504                 return count;
2505
2506         total_missed_rx = 0;
2507         total_qbrc = 0;
2508         total_qprc = 0;
2509         total_qprdc = 0;
2510
2511         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2512                                    &total_qprc, &total_qprdc);
2513
2514         /* If this is a reset xstats is NULL, and we have cleared the
2515          * registers by reading them.
2516          */
2517         if (!xstats)
2518                 return 0;
2519
2520         /* Extended stats from ixgbe_hw_stats */
2521         count = 0;
2522         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2523                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2524                          rte_ixgbe_stats_strings[i].name);
2525                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2526                                 rte_ixgbe_stats_strings[i].offset);
2527                 count++;
2528         }
2529
2530         /* Per-Q stats, with 8 queues available */
2531         for (i = 0; i < 8; i++) {
2532                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2533                          "rx_q%u_mbuf_allocation_errors", i);
2534                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2535                                 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2536                 count++;
2537
2538                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2539                          "rx_q%u_missed_packets", i);
2540                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2541                                 offsetof(struct ixgbe_hw_stats, mpc[i]));
2542                 count++;
2543
2544                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2545                          "rx_q%u_xon_priority_packets", i);
2546                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2547                                 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2548                 count++;
2549
2550                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2551                          "tx_q%u_xon_priority_packets", i);
2552                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2553                                 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2554                 count++;
2555
2556                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2557                          "rx_q%u_xoff_priority_packets", i);
2558                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2559                                 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2560                 count++;
2561
2562                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2563                          "tx_q%u_xoff_priority_packets", i);
2564                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2565                                 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2566                 count++;
2567
2568                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2569                          "xx_q%u_xon_to_xoff_priority_packets", i);
2570                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2571                                 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2572                 count++;
2573         }
2574
2575         for (i = 0; i < 16; i++) {
2576                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2577                          "rx_q%u_packets", i);
2578                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2579                                 offsetof(struct ixgbe_hw_stats, qprc[i]));
2580                 count++;
2581
2582                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2583                          "rx_q%u_bytes", i);
2584                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2585                                 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2586                 count++;
2587
2588                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2589                          "tx_q%u_packets", i);
2590                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2591                                 offsetof(struct ixgbe_hw_stats, qptc[i]));
2592                 count++;
2593
2594                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2595                          "tx_q%u_bytes", i);
2596                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2597                                 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2598                 count++;
2599
2600                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2601                          "rx_q%u_dropped", i);
2602                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2603                                 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2604                 count++;
2605         }
2606
2607         return count;
2608 }
2609
2610 static void
2611 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2612 {
2613         struct ixgbe_hw_stats *stats =
2614                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2615
2616         /* HW registers are cleared on read */
2617         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2618
2619         /* Reset software totals */
2620         memset(stats, 0, sizeof(*stats));
2621 }
2622
2623 static void
2624 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2625 {
2626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2628                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2629
2630         /* Good Rx packet, include VF loopback */
2631         UPDATE_VF_STAT(IXGBE_VFGPRC,
2632             hw_stats->last_vfgprc, hw_stats->vfgprc);
2633
2634         /* Good Rx octets, include VF loopback */
2635         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2636             hw_stats->last_vfgorc, hw_stats->vfgorc);
2637
2638         /* Good Tx packet, include VF loopback */
2639         UPDATE_VF_STAT(IXGBE_VFGPTC,
2640             hw_stats->last_vfgptc, hw_stats->vfgptc);
2641
2642         /* Good Tx octets, include VF loopback */
2643         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2644             hw_stats->last_vfgotc, hw_stats->vfgotc);
2645
2646         /* Rx Multicst Packet */
2647         UPDATE_VF_STAT(IXGBE_VFMPRC,
2648             hw_stats->last_vfmprc, hw_stats->vfmprc);
2649
2650         if (stats == NULL)
2651                 return;
2652
2653         stats->ipackets = hw_stats->vfgprc;
2654         stats->ibytes = hw_stats->vfgorc;
2655         stats->opackets = hw_stats->vfgptc;
2656         stats->obytes = hw_stats->vfgotc;
2657         stats->imcasts = hw_stats->vfmprc;
2658         /* stats->imcasts should be removed as imcasts is deprecated */
2659 }
2660
2661 static void
2662 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2663 {
2664         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2665                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2666
2667         /* Sync HW register to the last stats */
2668         ixgbevf_dev_stats_get(dev, NULL);
2669
2670         /* reset HW current stats*/
2671         hw_stats->vfgprc = 0;
2672         hw_stats->vfgorc = 0;
2673         hw_stats->vfgptc = 0;
2674         hw_stats->vfgotc = 0;
2675         hw_stats->vfmprc = 0;
2676
2677 }
2678
2679 static void
2680 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2681 {
2682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2683
2684         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2685         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2686         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2687         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2688         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2689         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2690         dev_info->max_vfs = dev->pci_dev->max_vfs;
2691         if (hw->mac.type == ixgbe_mac_82598EB)
2692                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2693         else
2694                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2695         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2696         dev_info->rx_offload_capa =
2697                 DEV_RX_OFFLOAD_VLAN_STRIP |
2698                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2699                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2700                 DEV_RX_OFFLOAD_TCP_CKSUM;
2701
2702         /*
2703          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2704          * mode.
2705          */
2706         if ((hw->mac.type == ixgbe_mac_82599EB ||
2707              hw->mac.type == ixgbe_mac_X540) &&
2708             !RTE_ETH_DEV_SRIOV(dev).active)
2709                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2710
2711         dev_info->tx_offload_capa =
2712                 DEV_TX_OFFLOAD_VLAN_INSERT |
2713                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2714                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2715                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2716                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2717                 DEV_TX_OFFLOAD_TCP_TSO;
2718
2719         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2720                 .rx_thresh = {
2721                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2722                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2723                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2724                 },
2725                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2726                 .rx_drop_en = 0,
2727         };
2728
2729         dev_info->default_txconf = (struct rte_eth_txconf) {
2730                 .tx_thresh = {
2731                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2732                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2733                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2734                 },
2735                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2736                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2737                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2738                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2739         };
2740
2741         dev_info->rx_desc_lim = rx_desc_lim;
2742         dev_info->tx_desc_lim = tx_desc_lim;
2743
2744         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2745         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2746         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2747 }
2748
2749 static void
2750 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2751                      struct rte_eth_dev_info *dev_info)
2752 {
2753         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2754
2755         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2756         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2757         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2758         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2759         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2760         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2761         dev_info->max_vfs = dev->pci_dev->max_vfs;
2762         if (hw->mac.type == ixgbe_mac_82598EB)
2763                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2764         else
2765                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2766         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2767                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2768                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2769                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2770         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2771                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2772                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2773                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2774                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2775                                 DEV_TX_OFFLOAD_TCP_TSO;
2776
2777         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2778                 .rx_thresh = {
2779                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2780                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2781                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2782                 },
2783                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2784                 .rx_drop_en = 0,
2785         };
2786
2787         dev_info->default_txconf = (struct rte_eth_txconf) {
2788                 .tx_thresh = {
2789                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2790                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2791                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2792                 },
2793                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2794                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2795                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2796                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2797         };
2798
2799         dev_info->rx_desc_lim = rx_desc_lim;
2800         dev_info->tx_desc_lim = tx_desc_lim;
2801 }
2802
2803 /* return 0 means link status changed, -1 means not changed */
2804 static int
2805 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2806 {
2807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         struct rte_eth_link link, old;
2809         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2810         int link_up;
2811         int diag;
2812
2813         link.link_status = 0;
2814         link.link_speed = 0;
2815         link.link_duplex = 0;
2816         memset(&old, 0, sizeof(old));
2817         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2818
2819         hw->mac.get_link_status = true;
2820
2821         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2822         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2823                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2824         else
2825                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2826
2827         if (diag != 0) {
2828                 link.link_speed = ETH_LINK_SPEED_100;
2829                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2830                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2831                 if (link.link_status == old.link_status)
2832                         return -1;
2833                 return 0;
2834         }
2835
2836         if (link_up == 0) {
2837                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2838                 if (link.link_status == old.link_status)
2839                         return -1;
2840                 return 0;
2841         }
2842         link.link_status = 1;
2843         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2844
2845         switch (link_speed) {
2846         default:
2847         case IXGBE_LINK_SPEED_UNKNOWN:
2848                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2849                 link.link_speed = ETH_LINK_SPEED_100;
2850                 break;
2851
2852         case IXGBE_LINK_SPEED_100_FULL:
2853                 link.link_speed = ETH_LINK_SPEED_100;
2854                 break;
2855
2856         case IXGBE_LINK_SPEED_1GB_FULL:
2857                 link.link_speed = ETH_LINK_SPEED_1000;
2858                 break;
2859
2860         case IXGBE_LINK_SPEED_10GB_FULL:
2861                 link.link_speed = ETH_LINK_SPEED_10000;
2862                 break;
2863         }
2864         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2865
2866         if (link.link_status == old.link_status)
2867                 return -1;
2868
2869         return 0;
2870 }
2871
2872 static void
2873 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2874 {
2875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         uint32_t fctrl;
2877
2878         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2879         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2880         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2881 }
2882
2883 static void
2884 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2885 {
2886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2887         uint32_t fctrl;
2888
2889         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2890         fctrl &= (~IXGBE_FCTRL_UPE);
2891         if (dev->data->all_multicast == 1)
2892                 fctrl |= IXGBE_FCTRL_MPE;
2893         else
2894                 fctrl &= (~IXGBE_FCTRL_MPE);
2895         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2896 }
2897
2898 static void
2899 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2900 {
2901         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2902         uint32_t fctrl;
2903
2904         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2905         fctrl |= IXGBE_FCTRL_MPE;
2906         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2907 }
2908
2909 static void
2910 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2911 {
2912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913         uint32_t fctrl;
2914
2915         if (dev->data->promiscuous == 1)
2916                 return; /* must remain in all_multicast mode */
2917
2918         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2919         fctrl &= (~IXGBE_FCTRL_MPE);
2920         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2921 }
2922
2923 /**
2924  * It clears the interrupt causes and enables the interrupt.
2925  * It will be called once only during nic initialized.
2926  *
2927  * @param dev
2928  *  Pointer to struct rte_eth_dev.
2929  *
2930  * @return
2931  *  - On success, zero.
2932  *  - On failure, a negative value.
2933  */
2934 static int
2935 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2936 {
2937         struct ixgbe_interrupt *intr =
2938                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2939
2940         ixgbe_dev_link_status_print(dev);
2941         intr->mask |= IXGBE_EICR_LSC;
2942
2943         return 0;
2944 }
2945
2946 /**
2947  * It clears the interrupt causes and enables the interrupt.
2948  * It will be called once only during nic initialized.
2949  *
2950  * @param dev
2951  *  Pointer to struct rte_eth_dev.
2952  *
2953  * @return
2954  *  - On success, zero.
2955  *  - On failure, a negative value.
2956  */
2957 static int
2958 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2959 {
2960         struct ixgbe_interrupt *intr =
2961                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2962
2963         intr->mask |= IXGBE_EICR_RTX_QUEUE;
2964
2965         return 0;
2966 }
2967
2968 /*
2969  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2970  *
2971  * @param dev
2972  *  Pointer to struct rte_eth_dev.
2973  *
2974  * @return
2975  *  - On success, zero.
2976  *  - On failure, a negative value.
2977  */
2978 static int
2979 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2980 {
2981         uint32_t eicr;
2982         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2983         struct ixgbe_interrupt *intr =
2984                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2985
2986         /* clear all cause mask */
2987         ixgbe_disable_intr(hw);
2988
2989         /* read-on-clear nic registers here */
2990         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2991         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2992
2993         intr->flags = 0;
2994
2995         /* set flag for async link update */
2996         if (eicr & IXGBE_EICR_LSC)
2997                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2998
2999         if (eicr & IXGBE_EICR_MAILBOX)
3000                 intr->flags |= IXGBE_FLAG_MAILBOX;
3001
3002         return 0;
3003 }
3004
3005 static int
3006 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
3007 {
3008         uint32_t eicr;
3009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3010         struct ixgbe_interrupt *intr =
3011                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3012
3013         /* clear all cause mask */
3014         ixgbevf_intr_disable(hw);
3015
3016         /* read-on-clear nic registers here */
3017         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
3018         PMD_DRV_LOG(INFO, "eicr %x", eicr);
3019
3020         intr->flags = 0;
3021
3022         /* set flag for async link update */
3023         if (eicr & IXGBE_EICR_LSC)
3024                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3025
3026         return 0;
3027 }
3028
3029 /**
3030  * It gets and then prints the link status.
3031  *
3032  * @param dev
3033  *  Pointer to struct rte_eth_dev.
3034  *
3035  * @return
3036  *  - On success, zero.
3037  *  - On failure, a negative value.
3038  */
3039 static void
3040 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3041 {
3042         struct rte_eth_link link;
3043
3044         memset(&link, 0, sizeof(link));
3045         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3046         if (link.link_status) {
3047                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3048                                         (int)(dev->data->port_id),
3049                                         (unsigned)link.link_speed,
3050                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3051                                         "full-duplex" : "half-duplex");
3052         } else {
3053                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3054                                 (int)(dev->data->port_id));
3055         }
3056         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3057                                 dev->pci_dev->addr.domain,
3058                                 dev->pci_dev->addr.bus,
3059                                 dev->pci_dev->addr.devid,
3060                                 dev->pci_dev->addr.function);
3061 }
3062
3063 /*
3064  * It executes link_update after knowing an interrupt occurred.
3065  *
3066  * @param dev
3067  *  Pointer to struct rte_eth_dev.
3068  *
3069  * @return
3070  *  - On success, zero.
3071  *  - On failure, a negative value.
3072  */
3073 static int
3074 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3075 {
3076         struct ixgbe_interrupt *intr =
3077                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3078         int64_t timeout;
3079         struct rte_eth_link link;
3080         int intr_enable_delay = false;
3081
3082         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3083
3084         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3085                 ixgbe_pf_mbx_process(dev);
3086                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3087         }
3088
3089         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3090                 /* get the link status before link update, for predicting later */
3091                 memset(&link, 0, sizeof(link));
3092                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3093
3094                 ixgbe_dev_link_update(dev, 0);
3095
3096                 /* likely to up */
3097                 if (!link.link_status)
3098                         /* handle it 1 sec later, wait it being stable */
3099                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3100                 /* likely to down */
3101                 else
3102                         /* handle it 4 sec later, wait it being stable */
3103                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3104
3105                 ixgbe_dev_link_status_print(dev);
3106
3107                 intr_enable_delay = true;
3108         }
3109
3110         if (intr_enable_delay) {
3111                 if (rte_eal_alarm_set(timeout * 1000,
3112                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3113                         PMD_DRV_LOG(ERR, "Error setting alarm");
3114         } else {
3115                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3116                 ixgbe_enable_intr(dev);
3117                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3118         }
3119
3120
3121         return 0;
3122 }
3123
3124 static int
3125 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
3126 {
3127         struct ixgbe_hw *hw =
3128                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3129
3130         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3131         ixgbevf_intr_enable(hw);
3132         rte_intr_enable(&dev->pci_dev->intr_handle);
3133         return 0;
3134 }
3135
3136 /**
3137  * Interrupt handler which shall be registered for alarm callback for delayed
3138  * handling specific interrupt to wait for the stable nic state. As the
3139  * NIC interrupt state is not stable for ixgbe after link is just down,
3140  * it needs to wait 4 seconds to get the stable status.
3141  *
3142  * @param handle
3143  *  Pointer to interrupt handle.
3144  * @param param
3145  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3146  *
3147  * @return
3148  *  void
3149  */
3150 static void
3151 ixgbe_dev_interrupt_delayed_handler(void *param)
3152 {
3153         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3154         struct ixgbe_interrupt *intr =
3155                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3156         struct ixgbe_hw *hw =
3157                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3158         uint32_t eicr;
3159
3160         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3161         if (eicr & IXGBE_EICR_MAILBOX)
3162                 ixgbe_pf_mbx_process(dev);
3163
3164         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3165                 ixgbe_dev_link_update(dev, 0);
3166                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3167                 ixgbe_dev_link_status_print(dev);
3168                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3169         }
3170
3171         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3172         ixgbe_enable_intr(dev);
3173         rte_intr_enable(&(dev->pci_dev->intr_handle));
3174 }
3175
3176 /**
3177  * Interrupt handler triggered by NIC  for handling
3178  * specific interrupt.
3179  *
3180  * @param handle
3181  *  Pointer to interrupt handle.
3182  * @param param
3183  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3184  *
3185  * @return
3186  *  void
3187  */
3188 static void
3189 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3190                             void *param)
3191 {
3192         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3193
3194         ixgbe_dev_interrupt_get_status(dev);
3195         ixgbe_dev_interrupt_action(dev);
3196 }
3197
3198 static void
3199 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3200                               void *param)
3201 {
3202         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3203
3204         ixgbevf_dev_interrupt_get_status(dev);
3205         ixgbevf_dev_interrupt_action(dev);
3206 }
3207
3208 static int
3209 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3210 {
3211         struct ixgbe_hw *hw;
3212
3213         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3214         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3215 }
3216
3217 static int
3218 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3219 {
3220         struct ixgbe_hw *hw;
3221
3222         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3223         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3224 }
3225
3226 static int
3227 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3228 {
3229         struct ixgbe_hw *hw;
3230         uint32_t mflcn_reg;
3231         uint32_t fccfg_reg;
3232         int rx_pause;
3233         int tx_pause;
3234
3235         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3236
3237         fc_conf->pause_time = hw->fc.pause_time;
3238         fc_conf->high_water = hw->fc.high_water[0];
3239         fc_conf->low_water = hw->fc.low_water[0];
3240         fc_conf->send_xon = hw->fc.send_xon;
3241         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3242
3243         /*
3244          * Return rx_pause status according to actual setting of
3245          * MFLCN register.
3246          */
3247         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3248         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3249                 rx_pause = 1;
3250         else
3251                 rx_pause = 0;
3252
3253         /*
3254          * Return tx_pause status according to actual setting of
3255          * FCCFG register.
3256          */
3257         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3258         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3259                 tx_pause = 1;
3260         else
3261                 tx_pause = 0;
3262
3263         if (rx_pause && tx_pause)
3264                 fc_conf->mode = RTE_FC_FULL;
3265         else if (rx_pause)
3266                 fc_conf->mode = RTE_FC_RX_PAUSE;
3267         else if (tx_pause)
3268                 fc_conf->mode = RTE_FC_TX_PAUSE;
3269         else
3270                 fc_conf->mode = RTE_FC_NONE;
3271
3272         return 0;
3273 }
3274
3275 static int
3276 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3277 {
3278         struct ixgbe_hw *hw;
3279         int err;
3280         uint32_t rx_buf_size;
3281         uint32_t max_high_water;
3282         uint32_t mflcn;
3283         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3284                 ixgbe_fc_none,
3285                 ixgbe_fc_rx_pause,
3286                 ixgbe_fc_tx_pause,
3287                 ixgbe_fc_full
3288         };
3289
3290         PMD_INIT_FUNC_TRACE();
3291
3292         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3293         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3294         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3295
3296         /*
3297          * At least reserve one Ethernet frame for watermark
3298          * high_water/low_water in kilo bytes for ixgbe
3299          */
3300         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3301         if ((fc_conf->high_water > max_high_water) ||
3302                 (fc_conf->high_water < fc_conf->low_water)) {
3303                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3304                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3305                 return (-EINVAL);
3306         }
3307
3308         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3309         hw->fc.pause_time     = fc_conf->pause_time;
3310         hw->fc.high_water[0]  = fc_conf->high_water;
3311         hw->fc.low_water[0]   = fc_conf->low_water;
3312         hw->fc.send_xon       = fc_conf->send_xon;
3313         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3314
3315         err = ixgbe_fc_enable(hw);
3316
3317         /* Not negotiated is not an error case */
3318         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3319
3320                 /* check if we want to forward MAC frames - driver doesn't have native
3321                  * capability to do that, so we'll write the registers ourselves */
3322
3323                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3324
3325                 /* set or clear MFLCN.PMCF bit depending on configuration */
3326                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3327                         mflcn |= IXGBE_MFLCN_PMCF;
3328                 else
3329                         mflcn &= ~IXGBE_MFLCN_PMCF;
3330
3331                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3332                 IXGBE_WRITE_FLUSH(hw);
3333
3334                 return 0;
3335         }
3336
3337         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3338         return -EIO;
3339 }
3340
3341 /**
3342  *  ixgbe_pfc_enable_generic - Enable flow control
3343  *  @hw: pointer to hardware structure
3344  *  @tc_num: traffic class number
3345  *  Enable flow control according to the current settings.
3346  */
3347 static int
3348 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3349 {
3350         int ret_val = 0;
3351         uint32_t mflcn_reg, fccfg_reg;
3352         uint32_t reg;
3353         uint32_t fcrtl, fcrth;
3354         uint8_t i;
3355         uint8_t nb_rx_en;
3356
3357         /* Validate the water mark configuration */
3358         if (!hw->fc.pause_time) {
3359                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3360                 goto out;
3361         }
3362
3363         /* Low water mark of zero causes XOFF floods */
3364         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3365                  /* High/Low water can not be 0 */
3366                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3367                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3368                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3369                         goto out;
3370                 }
3371
3372                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3373                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3374                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3375                         goto out;
3376                 }
3377         }
3378         /* Negotiate the fc mode to use */
3379         ixgbe_fc_autoneg(hw);
3380
3381         /* Disable any previous flow control settings */
3382         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3383         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3384
3385         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3386         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3387
3388         switch (hw->fc.current_mode) {
3389         case ixgbe_fc_none:
3390                 /*
3391                  * If the count of enabled RX Priority Flow control >1,
3392                  * and the TX pause can not be disabled
3393                  */
3394                 nb_rx_en = 0;
3395                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3396                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3397                         if (reg & IXGBE_FCRTH_FCEN)
3398                                 nb_rx_en++;
3399                 }
3400                 if (nb_rx_en > 1)
3401                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3402                 break;
3403         case ixgbe_fc_rx_pause:
3404                 /*
3405                  * Rx Flow control is enabled and Tx Flow control is
3406                  * disabled by software override. Since there really
3407                  * isn't a way to advertise that we are capable of RX
3408                  * Pause ONLY, we will advertise that we support both
3409                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3410                  * disable the adapter's ability to send PAUSE frames.
3411                  */
3412                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3413                 /*
3414                  * If the count of enabled RX Priority Flow control >1,
3415                  * and the TX pause can not be disabled
3416                  */
3417                 nb_rx_en = 0;
3418                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3419                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3420                         if (reg & IXGBE_FCRTH_FCEN)
3421                                 nb_rx_en++;
3422                 }
3423                 if (nb_rx_en > 1)
3424                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3425                 break;
3426         case ixgbe_fc_tx_pause:
3427                 /*
3428                  * Tx Flow control is enabled, and Rx Flow control is
3429                  * disabled by software override.
3430                  */
3431                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3432                 break;
3433         case ixgbe_fc_full:
3434                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3435                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3436                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3437                 break;
3438         default:
3439                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3440                 ret_val = IXGBE_ERR_CONFIG;
3441                 goto out;
3442                 break;
3443         }
3444
3445         /* Set 802.3x based flow control settings. */
3446         mflcn_reg |= IXGBE_MFLCN_DPF;
3447         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3448         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3449
3450         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3451         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3452                 hw->fc.high_water[tc_num]) {
3453                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3454                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3455                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3456         } else {
3457                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3458                 /*
3459                  * In order to prevent Tx hangs when the internal Tx
3460                  * switch is enabled we must set the high water mark
3461                  * to the maximum FCRTH value.  This allows the Tx
3462                  * switch to function even under heavy Rx workloads.
3463                  */
3464                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3465         }
3466         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3467
3468         /* Configure pause time (2 TCs per register) */
3469         reg = hw->fc.pause_time * 0x00010001;
3470         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3471                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3472
3473         /* Configure flow control refresh threshold value */
3474         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3475
3476 out:
3477         return ret_val;
3478 }
3479
3480 static int
3481 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3482 {
3483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3484         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3485
3486         if(hw->mac.type != ixgbe_mac_82598EB) {
3487                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3488         }
3489         return ret_val;
3490 }
3491
3492 static int
3493 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3494 {
3495         int err;
3496         uint32_t rx_buf_size;
3497         uint32_t max_high_water;
3498         uint8_t tc_num;
3499         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3500         struct ixgbe_hw *hw =
3501                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3502         struct ixgbe_dcb_config *dcb_config =
3503                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3504
3505         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3506                 ixgbe_fc_none,
3507                 ixgbe_fc_rx_pause,
3508                 ixgbe_fc_tx_pause,
3509                 ixgbe_fc_full
3510         };
3511
3512         PMD_INIT_FUNC_TRACE();
3513
3514         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3515         tc_num = map[pfc_conf->priority];
3516         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3517         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3518         /*
3519          * At least reserve one Ethernet frame for watermark
3520          * high_water/low_water in kilo bytes for ixgbe
3521          */
3522         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3523         if ((pfc_conf->fc.high_water > max_high_water) ||
3524             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3525                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3526                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3527                 return (-EINVAL);
3528         }
3529
3530         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3531         hw->fc.pause_time = pfc_conf->fc.pause_time;
3532         hw->fc.send_xon = pfc_conf->fc.send_xon;
3533         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3534         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3535
3536         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3537
3538         /* Not negotiated is not an error case */
3539         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3540                 return 0;
3541
3542         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3543         return -EIO;
3544 }
3545
3546 static int
3547 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3548                           struct rte_eth_rss_reta_entry64 *reta_conf,
3549                           uint16_t reta_size)
3550 {
3551         uint8_t i, j, mask;
3552         uint32_t reta, r;
3553         uint16_t idx, shift;
3554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3555         uint16_t sp_reta_size;
3556         uint32_t reta_reg;
3557
3558         PMD_INIT_FUNC_TRACE();
3559
3560         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3561                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3562                         "NIC.");
3563                 return -ENOTSUP;
3564         }
3565
3566         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3567         if (reta_size != sp_reta_size) {
3568                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3569                         "(%d) doesn't match the number hardware can supported "
3570                         "(%d)\n", reta_size, sp_reta_size);
3571                 return -EINVAL;
3572         }
3573
3574         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3575                 idx = i / RTE_RETA_GROUP_SIZE;
3576                 shift = i % RTE_RETA_GROUP_SIZE;
3577                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3578                                                 IXGBE_4_BIT_MASK);
3579                 if (!mask)
3580                         continue;
3581                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3582                 if (mask == IXGBE_4_BIT_MASK)
3583                         r = 0;
3584                 else
3585                         r = IXGBE_READ_REG(hw, reta_reg);
3586                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3587                         if (mask & (0x1 << j))
3588                                 reta |= reta_conf[idx].reta[shift + j] <<
3589                                                         (CHAR_BIT * j);
3590                         else
3591                                 reta |= r & (IXGBE_8_BIT_MASK <<
3592                                                 (CHAR_BIT * j));
3593                 }
3594                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3595         }
3596
3597         return 0;
3598 }
3599
3600 static int
3601 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3602                          struct rte_eth_rss_reta_entry64 *reta_conf,
3603                          uint16_t reta_size)
3604 {
3605         uint8_t i, j, mask;
3606         uint32_t reta;
3607         uint16_t idx, shift;
3608         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3609         uint16_t sp_reta_size;
3610         uint32_t reta_reg;
3611
3612         PMD_INIT_FUNC_TRACE();
3613         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3614         if (reta_size != sp_reta_size) {
3615                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3616                         "(%d) doesn't match the number hardware can supported "
3617                         "(%d)\n", reta_size, sp_reta_size);
3618                 return -EINVAL;
3619         }
3620
3621         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3622                 idx = i / RTE_RETA_GROUP_SIZE;
3623                 shift = i % RTE_RETA_GROUP_SIZE;
3624                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3625                                                 IXGBE_4_BIT_MASK);
3626                 if (!mask)
3627                         continue;
3628
3629                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3630                 reta = IXGBE_READ_REG(hw, reta_reg);
3631                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3632                         if (mask & (0x1 << j))
3633                                 reta_conf[idx].reta[shift + j] =
3634                                         ((reta >> (CHAR_BIT * j)) &
3635                                                 IXGBE_8_BIT_MASK);
3636                 }
3637         }
3638
3639         return 0;
3640 }
3641
3642 static void
3643 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3644                                 uint32_t index, uint32_t pool)
3645 {
3646         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647         uint32_t enable_addr = 1;
3648
3649         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3650 }
3651
3652 static void
3653 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3654 {
3655         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656
3657         ixgbe_clear_rar(hw, index);
3658 }
3659
3660 static void
3661 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3662 {
3663         ixgbe_remove_rar(dev, 0);
3664
3665         ixgbe_add_rar(dev, addr, 0, 0);
3666 }
3667
3668 static int
3669 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3670 {
3671         uint32_t hlreg0;
3672         uint32_t maxfrs;
3673         struct ixgbe_hw *hw;
3674         struct rte_eth_dev_info dev_info;
3675         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3676
3677         ixgbe_dev_info_get(dev, &dev_info);
3678
3679         /* check that mtu is within the allowed range */
3680         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3681                 return -EINVAL;
3682
3683         /* refuse mtu that requires the support of scattered packets when this
3684          * feature has not been enabled before. */
3685         if (!dev->data->scattered_rx &&
3686             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3687              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3688                 return -EINVAL;
3689
3690         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3691         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3692
3693         /* switch to jumbo mode if needed */
3694         if (frame_size > ETHER_MAX_LEN) {
3695                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3696                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3697         } else {
3698                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3699                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3700         }
3701         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3702
3703         /* update max frame size */
3704         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3705
3706         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3707         maxfrs &= 0x0000FFFF;
3708         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3709         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3710
3711         return 0;
3712 }
3713
3714 /*
3715  * Virtual Function operations
3716  */
3717 static void
3718 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3719 {
3720         PMD_INIT_FUNC_TRACE();
3721
3722         /* Clear interrupt mask to stop from interrupts being generated */
3723         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3724
3725         IXGBE_WRITE_FLUSH(hw);
3726 }
3727
3728 static void
3729 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3730 {
3731         PMD_INIT_FUNC_TRACE();
3732
3733         /* VF enable interrupt autoclean */
3734         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3735         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3736         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3737
3738         IXGBE_WRITE_FLUSH(hw);
3739 }
3740
3741 static int
3742 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3743 {
3744         struct rte_eth_conf* conf = &dev->data->dev_conf;
3745         struct ixgbe_adapter *adapter =
3746                         (struct ixgbe_adapter *)dev->data->dev_private;
3747
3748         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3749                      dev->data->port_id);
3750
3751         /*
3752          * VF has no ability to enable/disable HW CRC
3753          * Keep the persistent behavior the same as Host PF
3754          */
3755 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3756         if (!conf->rxmode.hw_strip_crc) {
3757                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3758                 conf->rxmode.hw_strip_crc = 1;
3759         }
3760 #else
3761         if (conf->rxmode.hw_strip_crc) {
3762                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3763                 conf->rxmode.hw_strip_crc = 0;
3764         }
3765 #endif
3766
3767         /*
3768          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3769          * allocation or vector Rx preconditions we will reset it.
3770          */
3771         adapter->rx_bulk_alloc_allowed = true;
3772         adapter->rx_vec_allowed = true;
3773
3774         return 0;
3775 }
3776
3777 static int
3778 ixgbevf_dev_start(struct rte_eth_dev *dev)
3779 {
3780         struct ixgbe_hw *hw =
3781                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3782         uint32_t intr_vector = 0;
3783         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3784
3785         int err, mask = 0;
3786
3787         PMD_INIT_FUNC_TRACE();
3788
3789         hw->mac.ops.reset_hw(hw);
3790         hw->mac.get_link_status = true;
3791
3792         /* negotiate mailbox API version to use with the PF. */
3793         ixgbevf_negotiate_api(hw);
3794
3795         ixgbevf_dev_tx_init(dev);
3796
3797         /* This can fail when allocating mbufs for descriptor rings */
3798         err = ixgbevf_dev_rx_init(dev);
3799         if (err) {
3800                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3801                 ixgbe_dev_clear_queues(dev);
3802                 return err;
3803         }
3804
3805         /* Set vfta */
3806         ixgbevf_set_vfta_all(dev,1);
3807
3808         /* Set HW strip */
3809         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3810                 ETH_VLAN_EXTEND_MASK;
3811         ixgbevf_vlan_offload_set(dev, mask);
3812
3813         ixgbevf_dev_rxtx_start(dev);
3814
3815         /* check and configure queue intr-vector mapping */
3816         if (dev->data->dev_conf.intr_conf.rxq != 0)
3817                 intr_vector = dev->data->nb_rx_queues;
3818
3819         if (rte_intr_efd_enable(intr_handle, intr_vector))
3820                 return -1;
3821
3822         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3823                 intr_handle->intr_vec =
3824                         rte_zmalloc("intr_vec",
3825                                     dev->data->nb_rx_queues * sizeof(int), 0);
3826                 if (intr_handle->intr_vec == NULL) {
3827                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3828                                      " intr_vec\n", dev->data->nb_rx_queues);
3829                         return -ENOMEM;
3830                 }
3831         }
3832         ixgbevf_configure_msix(dev);
3833
3834         if (dev->data->dev_conf.intr_conf.lsc != 0) {
3835                 if (rte_intr_allow_others(intr_handle))
3836                         rte_intr_callback_register(intr_handle,
3837                                         ixgbevf_dev_interrupt_handler,
3838                                         (void *)dev);
3839                 else
3840                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
3841                                      " no intr multiplex\n");
3842         }
3843
3844         rte_intr_enable(intr_handle);
3845
3846         /* Re-enable interrupt for VF */
3847         ixgbevf_intr_enable(hw);
3848
3849         return 0;
3850 }
3851
3852 static void
3853 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3854 {
3855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3856         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3857
3858         PMD_INIT_FUNC_TRACE();
3859
3860         hw->adapter_stopped = 1;
3861         ixgbe_stop_adapter(hw);
3862
3863         /*
3864           * Clear what we set, but we still keep shadow_vfta to
3865           * restore after device starts
3866           */
3867         ixgbevf_set_vfta_all(dev,0);
3868
3869         /* Clear stored conf */
3870         dev->data->scattered_rx = 0;
3871
3872         ixgbe_dev_clear_queues(dev);
3873
3874         /* disable intr eventfd mapping */
3875         rte_intr_disable(intr_handle);
3876
3877         /* Clean datapath event and queue/vec mapping */
3878         rte_intr_efd_disable(intr_handle);
3879         if (intr_handle->intr_vec != NULL) {
3880                 rte_free(intr_handle->intr_vec);
3881                 intr_handle->intr_vec = NULL;
3882         }
3883 }
3884
3885 static void
3886 ixgbevf_dev_close(struct rte_eth_dev *dev)
3887 {
3888         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889         struct rte_pci_device *pci_dev;
3890
3891         PMD_INIT_FUNC_TRACE();
3892
3893         ixgbe_reset_hw(hw);
3894
3895         ixgbevf_dev_stop(dev);
3896
3897         ixgbe_dev_free_queues(dev);
3898
3899         /* reprogram the RAR[0] in case user changed it. */
3900         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3901
3902         pci_dev = dev->pci_dev;
3903         if (pci_dev->intr_handle.intr_vec) {
3904                 rte_free(pci_dev->intr_handle.intr_vec);
3905                 pci_dev->intr_handle.intr_vec = NULL;
3906         }
3907 }
3908
3909 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3910 {
3911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3912         struct ixgbe_vfta * shadow_vfta =
3913                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3914         int i = 0, j = 0, vfta = 0, mask = 1;
3915
3916         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3917                 vfta = shadow_vfta->vfta[i];
3918                 if(vfta){
3919                         mask = 1;
3920                         for (j = 0; j < 32; j++){
3921                                 if(vfta & mask)
3922                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3923                                 mask<<=1;
3924                         }
3925                 }
3926         }
3927
3928 }
3929
3930 static int
3931 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3932 {
3933         struct ixgbe_hw *hw =
3934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3935         struct ixgbe_vfta * shadow_vfta =
3936                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3937         uint32_t vid_idx = 0;
3938         uint32_t vid_bit = 0;
3939         int ret = 0;
3940
3941         PMD_INIT_FUNC_TRACE();
3942
3943         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3944         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3945         if(ret){
3946                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3947                 return ret;
3948         }
3949         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3950         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3951
3952         /* Save what we set and retore it after device reset */
3953         if (on)
3954                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3955         else
3956                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3957
3958         return 0;
3959 }
3960
3961 static void
3962 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3963 {
3964         struct ixgbe_hw *hw =
3965                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3966         uint32_t ctrl;
3967
3968         PMD_INIT_FUNC_TRACE();
3969
3970         if(queue >= hw->mac.max_rx_queues)
3971                 return;
3972
3973         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3974         if(on)
3975                 ctrl |= IXGBE_RXDCTL_VME;
3976         else
3977                 ctrl &= ~IXGBE_RXDCTL_VME;
3978         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3979
3980         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3981 }
3982
3983 static void
3984 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3985 {
3986         struct ixgbe_hw *hw =
3987                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3988         uint16_t i;
3989         int on = 0;
3990
3991         /* VF function only support hw strip feature, others are not support */
3992         if(mask & ETH_VLAN_STRIP_MASK){
3993                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3994
3995                 for(i=0; i < hw->mac.max_rx_queues; i++)
3996                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3997         }
3998 }
3999
4000 static int
4001 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4002 {
4003         uint32_t reg_val;
4004
4005         /* we only need to do this if VMDq is enabled */
4006         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4007         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4008                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4009                 return (-1);
4010         }
4011
4012         return 0;
4013 }
4014
4015 static uint32_t
4016 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4017 {
4018         uint32_t vector = 0;
4019         switch (hw->mac.mc_filter_type) {
4020         case 0:   /* use bits [47:36] of the address */
4021                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4022                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4023                 break;
4024         case 1:   /* use bits [46:35] of the address */
4025                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4026                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4027                 break;
4028         case 2:   /* use bits [45:34] of the address */
4029                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4030                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4031                 break;
4032         case 3:   /* use bits [43:32] of the address */
4033                 vector = ((uc_addr->addr_bytes[4]) |
4034                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4035                 break;
4036         default:  /* Invalid mc_filter_type */
4037                 break;
4038         }
4039
4040         /* vector can only be 12-bits or boundary will be exceeded */
4041         vector &= 0xFFF;
4042         return vector;
4043 }
4044
4045 static int
4046 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4047                                uint8_t on)
4048 {
4049         uint32_t vector;
4050         uint32_t uta_idx;
4051         uint32_t reg_val;
4052         uint32_t uta_shift;
4053         uint32_t rc;
4054         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4055         const uint32_t ixgbe_uta_bit_shift = 5;
4056         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4057         const uint32_t bit1 = 0x1;
4058
4059         struct ixgbe_hw *hw =
4060                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4061         struct ixgbe_uta_info *uta_info =
4062                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4063
4064         /* The UTA table only exists on 82599 hardware and newer */
4065         if (hw->mac.type < ixgbe_mac_82599EB)
4066                 return (-ENOTSUP);
4067
4068         vector = ixgbe_uta_vector(hw,mac_addr);
4069         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4070         uta_shift = vector & ixgbe_uta_bit_mask;
4071
4072         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4073         if(rc == on)
4074                 return 0;
4075
4076         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4077         if (on) {
4078                 uta_info->uta_in_use++;
4079                 reg_val |= (bit1 << uta_shift);
4080                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4081         } else {
4082                 uta_info->uta_in_use--;
4083                 reg_val &= ~(bit1 << uta_shift);
4084                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4085         }
4086
4087         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4088
4089         if (uta_info->uta_in_use > 0)
4090                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4091                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4092         else
4093                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4094
4095         return 0;
4096 }
4097
4098 static int
4099 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4100 {
4101         int i;
4102         struct ixgbe_hw *hw =
4103                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4104         struct ixgbe_uta_info *uta_info =
4105                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4106
4107         /* The UTA table only exists on 82599 hardware and newer */
4108         if (hw->mac.type < ixgbe_mac_82599EB)
4109                 return (-ENOTSUP);
4110
4111         if(on) {
4112                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4113                         uta_info->uta_shadow[i] = ~0;
4114                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4115                 }
4116         } else {
4117                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4118                         uta_info->uta_shadow[i] = 0;
4119                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4120                 }
4121         }
4122         return 0;
4123
4124 }
4125
4126 uint32_t
4127 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4128 {
4129         uint32_t new_val = orig_val;
4130
4131         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4132                 new_val |= IXGBE_VMOLR_AUPE;
4133         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4134                 new_val |= IXGBE_VMOLR_ROMPE;
4135         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4136                 new_val |= IXGBE_VMOLR_ROPE;
4137         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4138                 new_val |= IXGBE_VMOLR_BAM;
4139         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4140                 new_val |= IXGBE_VMOLR_MPE;
4141
4142         return new_val;
4143 }
4144
4145 static int
4146 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4147                                uint16_t rx_mask, uint8_t on)
4148 {
4149         int val = 0;
4150
4151         struct ixgbe_hw *hw =
4152                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4154
4155         if (hw->mac.type == ixgbe_mac_82598EB) {
4156                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4157                              " on 82599 hardware and newer");
4158                 return (-ENOTSUP);
4159         }
4160         if (ixgbe_vmdq_mode_check(hw) < 0)
4161                 return (-ENOTSUP);
4162
4163         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4164
4165         if (on)
4166                 vmolr |= val;
4167         else
4168                 vmolr &= ~val;
4169
4170         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4171
4172         return 0;
4173 }
4174
4175 static int
4176 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4177 {
4178         uint32_t reg,addr;
4179         uint32_t val;
4180         const uint8_t bit1 = 0x1;
4181
4182         struct ixgbe_hw *hw =
4183                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4184
4185         if (ixgbe_vmdq_mode_check(hw) < 0)
4186                 return (-ENOTSUP);
4187
4188         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4189         reg = IXGBE_READ_REG(hw, addr);
4190         val = bit1 << pool;
4191
4192         if (on)
4193                 reg |= val;
4194         else
4195                 reg &= ~val;
4196
4197         IXGBE_WRITE_REG(hw, addr,reg);
4198
4199         return 0;
4200 }
4201
4202 static int
4203 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4204 {
4205         uint32_t reg,addr;
4206         uint32_t val;
4207         const uint8_t bit1 = 0x1;
4208
4209         struct ixgbe_hw *hw =
4210                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211
4212         if (ixgbe_vmdq_mode_check(hw) < 0)
4213                 return (-ENOTSUP);
4214
4215         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4216         reg = IXGBE_READ_REG(hw, addr);
4217         val = bit1 << pool;
4218
4219         if (on)
4220                 reg |= val;
4221         else
4222                 reg &= ~val;
4223
4224         IXGBE_WRITE_REG(hw, addr,reg);
4225
4226         return 0;
4227 }
4228
4229 static int
4230 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4231                         uint64_t pool_mask, uint8_t vlan_on)
4232 {
4233         int ret = 0;
4234         uint16_t pool_idx;
4235         struct ixgbe_hw *hw =
4236                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4237
4238         if (ixgbe_vmdq_mode_check(hw) < 0)
4239                 return (-ENOTSUP);
4240         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4241                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4242                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4243                         if (ret < 0)
4244                                 return ret;
4245         }
4246
4247         return ret;
4248 }
4249
4250 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4251 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4252 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4253 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4254 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4255         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4256         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4257
4258 static int
4259 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4260                         struct rte_eth_mirror_conf *mirror_conf,
4261                         uint8_t rule_id, uint8_t on)
4262 {
4263         uint32_t mr_ctl,vlvf;
4264         uint32_t mp_lsb = 0;
4265         uint32_t mv_msb = 0;
4266         uint32_t mv_lsb = 0;
4267         uint32_t mp_msb = 0;
4268         uint8_t i = 0;
4269         int reg_index = 0;
4270         uint64_t vlan_mask = 0;
4271
4272         const uint8_t pool_mask_offset = 32;
4273         const uint8_t vlan_mask_offset = 32;
4274         const uint8_t dst_pool_offset = 8;
4275         const uint8_t rule_mr_offset  = 4;
4276         const uint8_t mirror_rule_mask= 0x0F;
4277
4278         struct ixgbe_mirror_info *mr_info =
4279                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4280         struct ixgbe_hw *hw =
4281                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282         uint8_t mirror_type = 0;
4283
4284         if (ixgbe_vmdq_mode_check(hw) < 0)
4285                 return -ENOTSUP;
4286
4287         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4288                 return -EINVAL;
4289
4290         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4291                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4292                         mirror_conf->rule_type);
4293                 return -EINVAL;
4294         }
4295
4296         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4297                 mirror_type |= IXGBE_MRCTL_VLME;
4298                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4299                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4300                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4301                                 /* search vlan id related pool vlan filter index */
4302                                 reg_index = ixgbe_find_vlvf_slot(hw,
4303                                                 mirror_conf->vlan.vlan_id[i]);
4304                                 if(reg_index < 0)
4305                                         return -EINVAL;
4306                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4307                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4308                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4309                                       mirror_conf->vlan.vlan_id[i]))
4310                                         vlan_mask |= (1ULL << reg_index);
4311                                 else
4312                                         return -EINVAL;
4313                         }
4314                 }
4315
4316                 if (on) {
4317                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4318                         mv_msb = vlan_mask >> vlan_mask_offset;
4319
4320                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4321                                                 mirror_conf->vlan.vlan_mask;
4322                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4323                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4324                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4325                                                 mirror_conf->vlan.vlan_id[i];
4326                         }
4327                 } else {
4328                         mv_lsb = 0;
4329                         mv_msb = 0;
4330                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4331                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4332                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4333                 }
4334         }
4335
4336         /*
4337          * if enable pool mirror, write related pool mask register,if disable
4338          * pool mirror, clear PFMRVM register
4339          */
4340         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4341                 mirror_type |= IXGBE_MRCTL_VPME;
4342                 if (on) {
4343                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4344                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4345                         mr_info->mr_conf[rule_id].pool_mask =
4346                                         mirror_conf->pool_mask;
4347
4348                 } else {
4349                         mp_lsb = 0;
4350                         mp_msb = 0;
4351                         mr_info->mr_conf[rule_id].pool_mask = 0;
4352                 }
4353         }
4354         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4355                 mirror_type |= IXGBE_MRCTL_UPME;
4356         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4357                 mirror_type |= IXGBE_MRCTL_DPME;
4358
4359         /* read  mirror control register and recalculate it */
4360         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4361
4362         if (on) {
4363                 mr_ctl |= mirror_type;
4364                 mr_ctl &= mirror_rule_mask;
4365                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4366         } else
4367                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4368
4369         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4370         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4371
4372         /* write mirrror control  register */
4373         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4374
4375         /* write pool mirrror control  register */
4376         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4377                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4378                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4379                                 mp_msb);
4380         }
4381         /* write VLAN mirrror control  register */
4382         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4383                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4384                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4385                                 mv_msb);
4386         }
4387
4388         return 0;
4389 }
4390
4391 static int
4392 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4393 {
4394         int mr_ctl = 0;
4395         uint32_t lsb_val = 0;
4396         uint32_t msb_val = 0;
4397         const uint8_t rule_mr_offset = 4;
4398
4399         struct ixgbe_hw *hw =
4400                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4401         struct ixgbe_mirror_info *mr_info =
4402                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4403
4404         if (ixgbe_vmdq_mode_check(hw) < 0)
4405                 return (-ENOTSUP);
4406
4407         memset(&mr_info->mr_conf[rule_id], 0,
4408                 sizeof(struct rte_eth_mirror_conf));
4409
4410         /* clear PFVMCTL register */
4411         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4412
4413         /* clear pool mask register */
4414         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4415         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4416
4417         /* clear vlan mask register */
4418         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4419         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4420
4421         return 0;
4422 }
4423
4424 static int
4425 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4426 {
4427         uint32_t mask;
4428         struct ixgbe_hw *hw =
4429                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4430
4431         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4432         mask |= (1 << queue_id);
4433         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4434
4435         rte_intr_enable(&dev->pci_dev->intr_handle);
4436
4437         return 0;
4438 }
4439
4440 static int
4441 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4442 {
4443         uint32_t mask;
4444         struct ixgbe_hw *hw =
4445                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446
4447         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4448         mask &= ~(1 << queue_id);
4449         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4450
4451         return 0;
4452 }
4453
4454 static int
4455 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4456 {
4457         uint32_t mask;
4458         struct ixgbe_hw *hw =
4459                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4460         struct ixgbe_interrupt *intr =
4461                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4462
4463         if (queue_id < 16) {
4464                 ixgbe_disable_intr(hw);
4465                 intr->mask |= (1 << queue_id);
4466                 ixgbe_enable_intr(dev);
4467         } else if (queue_id < 32) {
4468                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4469                 mask &= (1 << queue_id);
4470                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4471         } else if (queue_id < 64) {
4472                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4473                 mask &= (1 << (queue_id - 32));
4474                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4475         }
4476         rte_intr_enable(&dev->pci_dev->intr_handle);
4477
4478         return 0;
4479 }
4480
4481 static int
4482 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4483 {
4484         uint32_t mask;
4485         struct ixgbe_hw *hw =
4486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487         struct ixgbe_interrupt *intr =
4488                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4489
4490         if (queue_id < 16) {
4491                 ixgbe_disable_intr(hw);
4492                 intr->mask &= ~(1 << queue_id);
4493                 ixgbe_enable_intr(dev);
4494         } else if (queue_id < 32) {
4495                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4496                 mask &= ~(1 << queue_id);
4497                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4498         } else if (queue_id < 64) {
4499                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4500                 mask &= ~(1 << (queue_id - 32));
4501                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4502         }
4503
4504         return 0;
4505 }
4506
4507 static void
4508 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4509                      uint8_t queue, uint8_t msix_vector)
4510 {
4511         uint32_t tmp, idx;
4512
4513         if (direction == -1) {
4514                 /* other causes */
4515                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4516                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4517                 tmp &= ~0xFF;
4518                 tmp |= msix_vector;
4519                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4520         } else {
4521                 /* rx or tx cause */
4522                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4523                 idx = ((16 * (queue & 1)) + (8 * direction));
4524                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4525                 tmp &= ~(0xFF << idx);
4526                 tmp |= (msix_vector << idx);
4527                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4528         }
4529 }
4530
4531 /**
4532  * set the IVAR registers, mapping interrupt causes to vectors
4533  * @param hw
4534  *  pointer to ixgbe_hw struct
4535  * @direction
4536  *  0 for Rx, 1 for Tx, -1 for other causes
4537  * @queue
4538  *  queue to map the corresponding interrupt to
4539  * @msix_vector
4540  *  the vector to map to the corresponding queue
4541  */
4542 static void
4543 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4544                    uint8_t queue, uint8_t msix_vector)
4545 {
4546         uint32_t tmp, idx;
4547
4548         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4549         if (hw->mac.type == ixgbe_mac_82598EB) {
4550                 if (direction == -1)
4551                         direction = 0;
4552                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4553                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4554                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4555                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4556                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4557         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4558                         (hw->mac.type == ixgbe_mac_X540)) {
4559                 if (direction == -1) {
4560                         /* other causes */
4561                         idx = ((queue & 1) * 8);
4562                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4563                         tmp &= ~(0xFF << idx);
4564                         tmp |= (msix_vector << idx);
4565                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4566                 } else {
4567                         /* rx or tx causes */
4568                         idx = ((16 * (queue & 1)) + (8 * direction));
4569                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4570                         tmp &= ~(0xFF << idx);
4571                         tmp |= (msix_vector << idx);
4572                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4573                 }
4574         }
4575 }
4576
4577 static void
4578 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4579 {
4580         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4581         struct ixgbe_hw *hw =
4582                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4583         uint32_t q_idx;
4584         uint32_t vector_idx = 0;
4585
4586         /* won't configure msix register if no mapping is done
4587          * between intr vector and event fd.
4588          */
4589         if (!rte_intr_dp_is_en(intr_handle))
4590                 return;
4591
4592         /* Configure all RX queues of VF */
4593         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4594                 /* Force all queue use vector 0,
4595                  * as IXGBE_VF_MAXMSIVECOTR = 1
4596                  */
4597                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4598                 intr_handle->intr_vec[q_idx] = vector_idx;
4599         }
4600
4601         /* Configure VF Rx queue ivar */
4602         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4603 }
4604
4605 /**
4606  * Sets up the hardware to properly generate MSI-X interrupts
4607  * @hw
4608  *  board private structure
4609  */
4610 static void
4611 ixgbe_configure_msix(struct rte_eth_dev *dev)
4612 {
4613         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4614         struct ixgbe_hw *hw =
4615                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616         uint32_t queue_id, vec = 0;
4617         uint32_t mask;
4618         uint32_t gpie;
4619
4620         /* won't configure msix register if no mapping is done
4621          * between intr vector and event fd
4622          */
4623         if (!rte_intr_dp_is_en(intr_handle))
4624                 return;
4625
4626         /* setup GPIE for MSI-x mode */
4627         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4628         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4629                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4630         /* auto clearing and auto setting corresponding bits in EIMS
4631          * when MSI-X interrupt is triggered
4632          */
4633         if (hw->mac.type == ixgbe_mac_82598EB) {
4634                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4635         } else {
4636                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4637                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4638         }
4639         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4640
4641         /* Populate the IVAR table and set the ITR values to the
4642          * corresponding register.
4643          */
4644         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4645              queue_id++) {
4646                 /* by default, 1:1 mapping */
4647                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4648                 intr_handle->intr_vec[queue_id] = vec;
4649                 if (vec < intr_handle->nb_efd - 1)
4650                         vec++;
4651         }
4652
4653         switch (hw->mac.type) {
4654         case ixgbe_mac_82598EB:
4655                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4656                                    intr_handle->max_intr - 1);
4657                 break;
4658         case ixgbe_mac_82599EB:
4659         case ixgbe_mac_X540:
4660                 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4661                 break;
4662         default:
4663                 break;
4664         }
4665         IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4666                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4667
4668         /* set up to autoclear timer, and the vectors */
4669         mask = IXGBE_EIMS_ENABLE_MASK;
4670         mask &= ~(IXGBE_EIMS_OTHER |
4671                   IXGBE_EIMS_MAILBOX |
4672                   IXGBE_EIMS_LSC);
4673
4674         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4675 }
4676
4677 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4678         uint16_t queue_idx, uint16_t tx_rate)
4679 {
4680         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4681         uint32_t rf_dec, rf_int;
4682         uint32_t bcnrc_val;
4683         uint16_t link_speed = dev->data->dev_link.link_speed;
4684
4685         if (queue_idx >= hw->mac.max_tx_queues)
4686                 return -EINVAL;
4687
4688         if (tx_rate != 0) {
4689                 /* Calculate the rate factor values to set */
4690                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4691                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4692                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4693
4694                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4695                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4696                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4697                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4698         } else {
4699                 bcnrc_val = 0;
4700         }
4701
4702         /*
4703          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4704          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4705          * set as 0x4.
4706          */
4707         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4708                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4709                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4710                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4711                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4712         else
4713                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4714                         IXGBE_MMW_SIZE_DEFAULT);
4715
4716         /* Set RTTBCNRC of queue X */
4717         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4718         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4719         IXGBE_WRITE_FLUSH(hw);
4720
4721         return 0;
4722 }
4723
4724 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4725         uint16_t tx_rate, uint64_t q_msk)
4726 {
4727         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4728         struct ixgbe_vf_info *vfinfo =
4729                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4730         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4731         uint32_t queue_stride =
4732                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4733         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4734         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4735         uint16_t total_rate = 0;
4736
4737         if (queue_end >= hw->mac.max_tx_queues)
4738                 return -EINVAL;
4739
4740         if (vfinfo != NULL) {
4741                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4742                         if (vf_idx == vf)
4743                                 continue;
4744                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4745                                 idx++)
4746                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4747                 }
4748         } else
4749                 return -EINVAL;
4750
4751         /* Store tx_rate for this vf. */
4752         for (idx = 0; idx < nb_q_per_pool; idx++) {
4753                 if (((uint64_t)0x1 << idx) & q_msk) {
4754                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4755                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4756                         total_rate += tx_rate;
4757                 }
4758         }
4759
4760         if (total_rate > dev->data->dev_link.link_speed) {
4761                 /*
4762                  * Reset stored TX rate of the VF if it causes exceed
4763                  * link speed.
4764                  */
4765                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4766                 return -EINVAL;
4767         }
4768
4769         /* Set RTTBCNRC of each queue/pool for vf X  */
4770         for (; queue_idx <= queue_end; queue_idx++) {
4771                 if (0x1 & q_msk)
4772                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4773                 q_msk = q_msk >> 1;
4774         }
4775
4776         return 0;
4777 }
4778
4779 static void
4780 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4781                      __attribute__((unused)) uint32_t index,
4782                      __attribute__((unused)) uint32_t pool)
4783 {
4784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4785         int diag;
4786
4787         /*
4788          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4789          * operation. Trap this case to avoid exhausting the [very limited]
4790          * set of PF resources used to store VF MAC addresses.
4791          */
4792         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4793                 return;
4794         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4795         if (diag == 0)
4796                 return;
4797         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4798 }
4799
4800 static void
4801 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4802 {
4803         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4804         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4805         struct ether_addr *mac_addr;
4806         uint32_t i;
4807         int diag;
4808
4809         /*
4810          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4811          * not support the deletion of a given MAC address.
4812          * Instead, it imposes to delete all MAC addresses, then to add again
4813          * all MAC addresses with the exception of the one to be deleted.
4814          */
4815         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4816
4817         /*
4818          * Add again all MAC addresses, with the exception of the deleted one
4819          * and of the permanent MAC address.
4820          */
4821         for (i = 0, mac_addr = dev->data->mac_addrs;
4822              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4823                 /* Skip the deleted MAC address */
4824                 if (i == index)
4825                         continue;
4826                 /* Skip NULL MAC addresses */
4827                 if (is_zero_ether_addr(mac_addr))
4828                         continue;
4829                 /* Skip the permanent MAC address */
4830                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4831                         continue;
4832                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4833                 if (diag != 0)
4834                         PMD_DRV_LOG(ERR,
4835                                     "Adding again MAC address "
4836                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4837                                     "diag=%d",
4838                                     mac_addr->addr_bytes[0],
4839                                     mac_addr->addr_bytes[1],
4840                                     mac_addr->addr_bytes[2],
4841                                     mac_addr->addr_bytes[3],
4842                                     mac_addr->addr_bytes[4],
4843                                     mac_addr->addr_bytes[5],
4844                                     diag);
4845         }
4846 }
4847
4848 static void
4849 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4850 {
4851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4852
4853         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4854 }
4855
4856 #define MAC_TYPE_FILTER_SUP(type)    do {\
4857         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4858                 (type) != ixgbe_mac_X550)\
4859                 return -ENOTSUP;\
4860 } while (0)
4861
4862 static int
4863 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4864                         struct rte_eth_syn_filter *filter,
4865                         bool add)
4866 {
4867         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4868         uint32_t synqf;
4869
4870         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4871                 return -EINVAL;
4872
4873         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4874
4875         if (add) {
4876                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4877                         return -EINVAL;
4878                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4879                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4880
4881                 if (filter->hig_pri)
4882                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4883                 else
4884                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4885         } else {
4886                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4887                         return -ENOENT;
4888                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4889         }
4890         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4891         IXGBE_WRITE_FLUSH(hw);
4892         return 0;
4893 }
4894
4895 static int
4896 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4897                         struct rte_eth_syn_filter *filter)
4898 {
4899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4900         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4901
4902         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4903                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4904                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4905                 return 0;
4906         }
4907         return -ENOENT;
4908 }
4909
4910 static int
4911 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4912                         enum rte_filter_op filter_op,
4913                         void *arg)
4914 {
4915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4916         int ret;
4917
4918         MAC_TYPE_FILTER_SUP(hw->mac.type);
4919
4920         if (filter_op == RTE_ETH_FILTER_NOP)
4921                 return 0;
4922
4923         if (arg == NULL) {
4924                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4925                             filter_op);
4926                 return -EINVAL;
4927         }
4928
4929         switch (filter_op) {
4930         case RTE_ETH_FILTER_ADD:
4931                 ret = ixgbe_syn_filter_set(dev,
4932                                 (struct rte_eth_syn_filter *)arg,
4933                                 TRUE);
4934                 break;
4935         case RTE_ETH_FILTER_DELETE:
4936                 ret = ixgbe_syn_filter_set(dev,
4937                                 (struct rte_eth_syn_filter *)arg,
4938                                 FALSE);
4939                 break;
4940         case RTE_ETH_FILTER_GET:
4941                 ret = ixgbe_syn_filter_get(dev,
4942                                 (struct rte_eth_syn_filter *)arg);
4943                 break;
4944         default:
4945                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4946                 ret = -EINVAL;
4947                 break;
4948         }
4949
4950         return ret;
4951 }
4952
4953
4954 static inline enum ixgbe_5tuple_protocol
4955 convert_protocol_type(uint8_t protocol_value)
4956 {
4957         if (protocol_value == IPPROTO_TCP)
4958                 return IXGBE_FILTER_PROTOCOL_TCP;
4959         else if (protocol_value == IPPROTO_UDP)
4960                 return IXGBE_FILTER_PROTOCOL_UDP;
4961         else if (protocol_value == IPPROTO_SCTP)
4962                 return IXGBE_FILTER_PROTOCOL_SCTP;
4963         else
4964                 return IXGBE_FILTER_PROTOCOL_NONE;
4965 }
4966
4967 /*
4968  * add a 5tuple filter
4969  *
4970  * @param
4971  * dev: Pointer to struct rte_eth_dev.
4972  * index: the index the filter allocates.
4973  * filter: ponter to the filter that will be added.
4974  * rx_queue: the queue id the filter assigned to.
4975  *
4976  * @return
4977  *    - On success, zero.
4978  *    - On failure, a negative value.
4979  */
4980 static int
4981 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4982                         struct ixgbe_5tuple_filter *filter)
4983 {
4984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4985         struct ixgbe_filter_info *filter_info =
4986                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4987         int i, idx, shift;
4988         uint32_t ftqf, sdpqf;
4989         uint32_t l34timir = 0;
4990         uint8_t mask = 0xff;
4991
4992         /*
4993          * look for an unused 5tuple filter index,
4994          * and insert the filter to list.
4995          */
4996         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4997                 idx = i / (sizeof(uint32_t) * NBBY);
4998                 shift = i % (sizeof(uint32_t) * NBBY);
4999                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5000                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5001                         filter->index = i;
5002                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5003                                           filter,
5004                                           entries);
5005                         break;
5006                 }
5007         }
5008         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5009                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5010                 return -ENOSYS;
5011         }
5012
5013         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5014                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5015         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5016
5017         ftqf = (uint32_t)(filter->filter_info.proto &
5018                 IXGBE_FTQF_PROTOCOL_MASK);
5019         ftqf |= (uint32_t)((filter->filter_info.priority &
5020                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5021         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5022                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5023         if (filter->filter_info.dst_ip_mask == 0)
5024                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5025         if (filter->filter_info.src_port_mask == 0)
5026                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5027         if (filter->filter_info.dst_port_mask == 0)
5028                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5029         if (filter->filter_info.proto_mask == 0)
5030                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5031         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5032         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5033         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5034
5035         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5036         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5037         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5038         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5039
5040         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5041         l34timir |= (uint32_t)(filter->queue <<
5042                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5043         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5044         return 0;
5045 }
5046
5047 /*
5048  * remove a 5tuple filter
5049  *
5050  * @param
5051  * dev: Pointer to struct rte_eth_dev.
5052  * filter: the pointer of the filter will be removed.
5053  */
5054 static void
5055 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5056                         struct ixgbe_5tuple_filter *filter)
5057 {
5058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5059         struct ixgbe_filter_info *filter_info =
5060                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5061         uint16_t index = filter->index;
5062
5063         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5064                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5065         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5066         rte_free(filter);
5067
5068         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5069         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5070         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5071         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5072         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5073 }
5074
5075 static int
5076 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5077 {
5078         struct ixgbe_hw *hw;
5079         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5080
5081         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082
5083         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5084                 return -EINVAL;
5085
5086         /* refuse mtu that requires the support of scattered packets when this
5087          * feature has not been enabled before. */
5088         if (!dev->data->scattered_rx &&
5089             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5090              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5091                 return -EINVAL;
5092
5093         /*
5094          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5095          * request of the version 2.0 of the mailbox API.
5096          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5097          * of the mailbox API.
5098          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5099          * prior to 3.11.33 which contains the following change:
5100          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5101          */
5102         ixgbevf_rlpml_set_vf(hw, max_frame);
5103
5104         /* update max frame size */
5105         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5106         return 0;
5107 }
5108
5109 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5110         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5111                 return -ENOTSUP;\
5112 } while (0)
5113
5114 static inline struct ixgbe_5tuple_filter *
5115 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5116                         struct ixgbe_5tuple_filter_info *key)
5117 {
5118         struct ixgbe_5tuple_filter *it;
5119
5120         TAILQ_FOREACH(it, filter_list, entries) {
5121                 if (memcmp(key, &it->filter_info,
5122                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5123                         return it;
5124                 }
5125         }
5126         return NULL;
5127 }
5128
5129 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5130 static inline int
5131 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5132                         struct ixgbe_5tuple_filter_info *filter_info)
5133 {
5134         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5135                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5136                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5137                 return -EINVAL;
5138
5139         switch (filter->dst_ip_mask) {
5140         case UINT32_MAX:
5141                 filter_info->dst_ip_mask = 0;
5142                 filter_info->dst_ip = filter->dst_ip;
5143                 break;
5144         case 0:
5145                 filter_info->dst_ip_mask = 1;
5146                 break;
5147         default:
5148                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5149                 return -EINVAL;
5150         }
5151
5152         switch (filter->src_ip_mask) {
5153         case UINT32_MAX:
5154                 filter_info->src_ip_mask = 0;
5155                 filter_info->src_ip = filter->src_ip;
5156                 break;
5157         case 0:
5158                 filter_info->src_ip_mask = 1;
5159                 break;
5160         default:
5161                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5162                 return -EINVAL;
5163         }
5164
5165         switch (filter->dst_port_mask) {
5166         case UINT16_MAX:
5167                 filter_info->dst_port_mask = 0;
5168                 filter_info->dst_port = filter->dst_port;
5169                 break;
5170         case 0:
5171                 filter_info->dst_port_mask = 1;
5172                 break;
5173         default:
5174                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5175                 return -EINVAL;
5176         }
5177
5178         switch (filter->src_port_mask) {
5179         case UINT16_MAX:
5180                 filter_info->src_port_mask = 0;
5181                 filter_info->src_port = filter->src_port;
5182                 break;
5183         case 0:
5184                 filter_info->src_port_mask = 1;
5185                 break;
5186         default:
5187                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5188                 return -EINVAL;
5189         }
5190
5191         switch (filter->proto_mask) {
5192         case UINT8_MAX:
5193                 filter_info->proto_mask = 0;
5194                 filter_info->proto =
5195                         convert_protocol_type(filter->proto);
5196                 break;
5197         case 0:
5198                 filter_info->proto_mask = 1;
5199                 break;
5200         default:
5201                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5202                 return -EINVAL;
5203         }
5204
5205         filter_info->priority = (uint8_t)filter->priority;
5206         return 0;
5207 }
5208
5209 /*
5210  * add or delete a ntuple filter
5211  *
5212  * @param
5213  * dev: Pointer to struct rte_eth_dev.
5214  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5215  * add: if true, add filter, if false, remove filter
5216  *
5217  * @return
5218  *    - On success, zero.
5219  *    - On failure, a negative value.
5220  */
5221 static int
5222 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5223                         struct rte_eth_ntuple_filter *ntuple_filter,
5224                         bool add)
5225 {
5226         struct ixgbe_filter_info *filter_info =
5227                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5228         struct ixgbe_5tuple_filter_info filter_5tuple;
5229         struct ixgbe_5tuple_filter *filter;
5230         int ret;
5231
5232         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5233                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5234                 return -EINVAL;
5235         }
5236
5237         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5238         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5239         if (ret < 0)
5240                 return ret;
5241
5242         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5243                                          &filter_5tuple);
5244         if (filter != NULL && add) {
5245                 PMD_DRV_LOG(ERR, "filter exists.");
5246                 return -EEXIST;
5247         }
5248         if (filter == NULL && !add) {
5249                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5250                 return -ENOENT;
5251         }
5252
5253         if (add) {
5254                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5255                                 sizeof(struct ixgbe_5tuple_filter), 0);
5256                 if (filter == NULL)
5257                         return -ENOMEM;
5258                 (void)rte_memcpy(&filter->filter_info,
5259                                  &filter_5tuple,
5260                                  sizeof(struct ixgbe_5tuple_filter_info));
5261                 filter->queue = ntuple_filter->queue;
5262                 ret = ixgbe_add_5tuple_filter(dev, filter);
5263                 if (ret < 0) {
5264                         rte_free(filter);
5265                         return ret;
5266                 }
5267         } else
5268                 ixgbe_remove_5tuple_filter(dev, filter);
5269
5270         return 0;
5271 }
5272
5273 /*
5274  * get a ntuple filter
5275  *
5276  * @param
5277  * dev: Pointer to struct rte_eth_dev.
5278  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5279  *
5280  * @return
5281  *    - On success, zero.
5282  *    - On failure, a negative value.
5283  */
5284 static int
5285 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5286                         struct rte_eth_ntuple_filter *ntuple_filter)
5287 {
5288         struct ixgbe_filter_info *filter_info =
5289                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5290         struct ixgbe_5tuple_filter_info filter_5tuple;
5291         struct ixgbe_5tuple_filter *filter;
5292         int ret;
5293
5294         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5295                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5296                 return -EINVAL;
5297         }
5298
5299         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5300         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5301         if (ret < 0)
5302                 return ret;
5303
5304         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5305                                          &filter_5tuple);
5306         if (filter == NULL) {
5307                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5308                 return -ENOENT;
5309         }
5310         ntuple_filter->queue = filter->queue;
5311         return 0;
5312 }
5313
5314 /*
5315  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5316  * @dev: pointer to rte_eth_dev structure
5317  * @filter_op:operation will be taken.
5318  * @arg: a pointer to specific structure corresponding to the filter_op
5319  *
5320  * @return
5321  *    - On success, zero.
5322  *    - On failure, a negative value.
5323  */
5324 static int
5325 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5326                                 enum rte_filter_op filter_op,
5327                                 void *arg)
5328 {
5329         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5330         int ret;
5331
5332         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5333
5334         if (filter_op == RTE_ETH_FILTER_NOP)
5335                 return 0;
5336
5337         if (arg == NULL) {
5338                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5339                             filter_op);
5340                 return -EINVAL;
5341         }
5342
5343         switch (filter_op) {
5344         case RTE_ETH_FILTER_ADD:
5345                 ret = ixgbe_add_del_ntuple_filter(dev,
5346                         (struct rte_eth_ntuple_filter *)arg,
5347                         TRUE);
5348                 break;
5349         case RTE_ETH_FILTER_DELETE:
5350                 ret = ixgbe_add_del_ntuple_filter(dev,
5351                         (struct rte_eth_ntuple_filter *)arg,
5352                         FALSE);
5353                 break;
5354         case RTE_ETH_FILTER_GET:
5355                 ret = ixgbe_get_ntuple_filter(dev,
5356                         (struct rte_eth_ntuple_filter *)arg);
5357                 break;
5358         default:
5359                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5360                 ret = -EINVAL;
5361                 break;
5362         }
5363         return ret;
5364 }
5365
5366 static inline int
5367 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5368                         uint16_t ethertype)
5369 {
5370         int i;
5371
5372         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5373                 if (filter_info->ethertype_filters[i] == ethertype &&
5374                     (filter_info->ethertype_mask & (1 << i)))
5375                         return i;
5376         }
5377         return -1;
5378 }
5379
5380 static inline int
5381 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5382                         uint16_t ethertype)
5383 {
5384         int i;
5385
5386         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5387                 if (!(filter_info->ethertype_mask & (1 << i))) {
5388                         filter_info->ethertype_mask |= 1 << i;
5389                         filter_info->ethertype_filters[i] = ethertype;
5390                         return i;
5391                 }
5392         }
5393         return -1;
5394 }
5395
5396 static inline int
5397 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5398                         uint8_t idx)
5399 {
5400         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5401                 return -1;
5402         filter_info->ethertype_mask &= ~(1 << idx);
5403         filter_info->ethertype_filters[idx] = 0;
5404         return idx;
5405 }
5406
5407 static int
5408 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5409                         struct rte_eth_ethertype_filter *filter,
5410                         bool add)
5411 {
5412         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5413         struct ixgbe_filter_info *filter_info =
5414                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5415         uint32_t etqf = 0;
5416         uint32_t etqs = 0;
5417         int ret;
5418
5419         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5420                 return -EINVAL;
5421
5422         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5423                 filter->ether_type == ETHER_TYPE_IPv6) {
5424                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5425                         " ethertype filter.", filter->ether_type);
5426                 return -EINVAL;
5427         }
5428
5429         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5430                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5431                 return -EINVAL;
5432         }
5433         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5434                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5435                 return -EINVAL;
5436         }
5437
5438         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5439         if (ret >= 0 && add) {
5440                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5441                             filter->ether_type);
5442                 return -EEXIST;
5443         }
5444         if (ret < 0 && !add) {
5445                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5446                             filter->ether_type);
5447                 return -ENOENT;
5448         }
5449
5450         if (add) {
5451                 ret = ixgbe_ethertype_filter_insert(filter_info,
5452                         filter->ether_type);
5453                 if (ret < 0) {
5454                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5455                         return -ENOSYS;
5456                 }
5457                 etqf = IXGBE_ETQF_FILTER_EN;
5458                 etqf |= (uint32_t)filter->ether_type;
5459                 etqs |= (uint32_t)((filter->queue <<
5460                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5461                                     IXGBE_ETQS_RX_QUEUE);
5462                 etqs |= IXGBE_ETQS_QUEUE_EN;
5463         } else {
5464                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5465                 if (ret < 0)
5466                         return -ENOSYS;
5467         }
5468         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5469         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5470         IXGBE_WRITE_FLUSH(hw);
5471
5472         return 0;
5473 }
5474
5475 static int
5476 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5477                         struct rte_eth_ethertype_filter *filter)
5478 {
5479         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5480         struct ixgbe_filter_info *filter_info =
5481                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5482         uint32_t etqf, etqs;
5483         int ret;
5484
5485         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5486         if (ret < 0) {
5487                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5488                             filter->ether_type);
5489                 return -ENOENT;
5490         }
5491
5492         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5493         if (etqf & IXGBE_ETQF_FILTER_EN) {
5494                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5495                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5496                 filter->flags = 0;
5497                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5498                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5499                 return 0;
5500         }
5501         return -ENOENT;
5502 }
5503
5504 /*
5505  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5506  * @dev: pointer to rte_eth_dev structure
5507  * @filter_op:operation will be taken.
5508  * @arg: a pointer to specific structure corresponding to the filter_op
5509  */
5510 static int
5511 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5512                                 enum rte_filter_op filter_op,
5513                                 void *arg)
5514 {
5515         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5516         int ret;
5517
5518         MAC_TYPE_FILTER_SUP(hw->mac.type);
5519
5520         if (filter_op == RTE_ETH_FILTER_NOP)
5521                 return 0;
5522
5523         if (arg == NULL) {
5524                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5525                             filter_op);
5526                 return -EINVAL;
5527         }
5528
5529         switch (filter_op) {
5530         case RTE_ETH_FILTER_ADD:
5531                 ret = ixgbe_add_del_ethertype_filter(dev,
5532                         (struct rte_eth_ethertype_filter *)arg,
5533                         TRUE);
5534                 break;
5535         case RTE_ETH_FILTER_DELETE:
5536                 ret = ixgbe_add_del_ethertype_filter(dev,
5537                         (struct rte_eth_ethertype_filter *)arg,
5538                         FALSE);
5539                 break;
5540         case RTE_ETH_FILTER_GET:
5541                 ret = ixgbe_get_ethertype_filter(dev,
5542                         (struct rte_eth_ethertype_filter *)arg);
5543                 break;
5544         default:
5545                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5546                 ret = -EINVAL;
5547                 break;
5548         }
5549         return ret;
5550 }
5551
5552 static int
5553 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5554                      enum rte_filter_type filter_type,
5555                      enum rte_filter_op filter_op,
5556                      void *arg)
5557 {
5558         int ret = -EINVAL;
5559
5560         switch (filter_type) {
5561         case RTE_ETH_FILTER_NTUPLE:
5562                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5563                 break;
5564         case RTE_ETH_FILTER_ETHERTYPE:
5565                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5566                 break;
5567         case RTE_ETH_FILTER_SYN:
5568                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5569                 break;
5570         case RTE_ETH_FILTER_FDIR:
5571                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5572                 break;
5573         default:
5574                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5575                                                         filter_type);
5576                 break;
5577         }
5578
5579         return ret;
5580 }
5581
5582 static u8 *
5583 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5584                         u8 **mc_addr_ptr, u32 *vmdq)
5585 {
5586         u8 *mc_addr;
5587
5588         *vmdq = 0;
5589         mc_addr = *mc_addr_ptr;
5590         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5591         return mc_addr;
5592 }
5593
5594 static int
5595 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5596                           struct ether_addr *mc_addr_set,
5597                           uint32_t nb_mc_addr)
5598 {
5599         struct ixgbe_hw *hw;
5600         u8 *mc_addr_list;
5601
5602         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5603         mc_addr_list = (u8 *)mc_addr_set;
5604         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5605                                          ixgbe_dev_addr_list_itr, TRUE);
5606 }
5607
5608 static int
5609 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5610 {
5611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5612         uint32_t tsync_ctl;
5613         uint32_t tsauxc;
5614
5615         /* Enable system time for platforms where it isn't on by default. */
5616         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5617         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5618         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5619
5620         /* Start incrementing the register used to timestamp PTP packets. */
5621         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5622
5623         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5624         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5625                         (ETHER_TYPE_1588 |
5626                          IXGBE_ETQF_FILTER_EN |
5627                          IXGBE_ETQF_1588));
5628
5629         /* Enable timestamping of received PTP packets. */
5630         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5631         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5632         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5633
5634         /* Enable timestamping of transmitted PTP packets. */
5635         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5636         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5637         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5638
5639         return 0;
5640 }
5641
5642 static int
5643 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5644 {
5645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5646         uint32_t tsync_ctl;
5647
5648         /* Disable timestamping of transmitted PTP packets. */
5649         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5650         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5651         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5652
5653         /* Disable timestamping of received PTP packets. */
5654         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5655         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5656         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5657
5658         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5659         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5660
5661         /* Stop incrementating the System Time registers. */
5662         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5663
5664         return 0;
5665 }
5666
5667 static int
5668 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5669                                  struct timespec *timestamp,
5670                                  uint32_t flags __rte_unused)
5671 {
5672         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5673         uint32_t tsync_rxctl;
5674         uint32_t rx_stmpl;
5675         uint32_t rx_stmph;
5676
5677         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5678         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5679                 return -EINVAL;
5680
5681         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5682         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5683
5684         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5685         timestamp->tv_nsec = 0;
5686
5687         return  0;
5688 }
5689
5690 static int
5691 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5692                                  struct timespec *timestamp)
5693 {
5694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5695         uint32_t tsync_txctl;
5696         uint32_t tx_stmpl;
5697         uint32_t tx_stmph;
5698
5699         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5700         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5701                 return -EINVAL;
5702
5703         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5704         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5705
5706         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5707         timestamp->tv_nsec = 0;
5708
5709         return  0;
5710 }
5711
5712 static int
5713 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5714 {
5715         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5716         int count = 0;
5717         int g_ind = 0;
5718         const struct reg_info *reg_group;
5719         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5720                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5721
5722         while ((reg_group = reg_set[g_ind++]))
5723                 count += ixgbe_regs_group_count(reg_group);
5724
5725         return count;
5726 }
5727
5728 static int
5729 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5730 {
5731         int count = 0;
5732         int g_ind = 0;
5733         const struct reg_info *reg_group;
5734
5735         while ((reg_group = ixgbevf_regs[g_ind++]))
5736                 count += ixgbe_regs_group_count(reg_group);
5737
5738         return count;
5739 }
5740
5741 static int
5742 ixgbe_get_regs(struct rte_eth_dev *dev,
5743               struct rte_dev_reg_info *regs)
5744 {
5745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         uint32_t *data = regs->data;
5747         int g_ind = 0;
5748         int count = 0;
5749         const struct reg_info *reg_group;
5750         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5751                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5752
5753         /* Support only full register dump */
5754         if ((regs->length == 0) ||
5755             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5756                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5757                         hw->device_id;
5758                 while ((reg_group = reg_set[g_ind++]))
5759                         count += ixgbe_read_regs_group(dev, &data[count],
5760                                 reg_group);
5761                 return 0;
5762         }
5763
5764         return -ENOTSUP;
5765 }
5766
5767 static int
5768 ixgbevf_get_regs(struct rte_eth_dev *dev,
5769                 struct rte_dev_reg_info *regs)
5770 {
5771         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5772         uint32_t *data = regs->data;
5773         int g_ind = 0;
5774         int count = 0;
5775         const struct reg_info *reg_group;
5776
5777         /* Support only full register dump */
5778         if ((regs->length == 0) ||
5779             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5780                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5781                         hw->device_id;
5782                 while ((reg_group = ixgbevf_regs[g_ind++]))
5783                         count += ixgbe_read_regs_group(dev, &data[count],
5784                                                       reg_group);
5785                 return 0;
5786         }
5787
5788         return -ENOTSUP;
5789 }
5790
5791 static int
5792 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5793 {
5794         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5795
5796         /* Return unit is byte count */
5797         return hw->eeprom.word_size * 2;
5798 }
5799
5800 static int
5801 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5802                 struct rte_dev_eeprom_info *in_eeprom)
5803 {
5804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5805         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5806         uint16_t *data = in_eeprom->data;
5807         int first, length;
5808
5809         first = in_eeprom->offset >> 1;
5810         length = in_eeprom->length >> 1;
5811         if ((first > hw->eeprom.word_size) ||
5812             ((first + length) > hw->eeprom.word_size))
5813                 return -EINVAL;
5814
5815         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5816
5817         return eeprom->ops.read_buffer(hw, first, length, data);
5818 }
5819
5820 static int
5821 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5822                 struct rte_dev_eeprom_info *in_eeprom)
5823 {
5824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5825         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5826         uint16_t *data = in_eeprom->data;
5827         int first, length;
5828
5829         first = in_eeprom->offset >> 1;
5830         length = in_eeprom->length >> 1;
5831         if ((first > hw->eeprom.word_size) ||
5832             ((first + length) > hw->eeprom.word_size))
5833                 return -EINVAL;
5834
5835         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5836
5837         return eeprom->ops.write_buffer(hw,  first, length, data);
5838 }
5839
5840 uint16_t
5841 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5842         switch (mac_type) {
5843         case ixgbe_mac_X550:
5844         case ixgbe_mac_X550EM_x:
5845                 return ETH_RSS_RETA_SIZE_512;
5846         case ixgbe_mac_X550_vf:
5847         case ixgbe_mac_X550EM_x_vf:
5848                 return ETH_RSS_RETA_SIZE_64;
5849         default:
5850                 return ETH_RSS_RETA_SIZE_128;
5851         }
5852 }
5853
5854 uint32_t
5855 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5856         switch (mac_type) {
5857         case ixgbe_mac_X550:
5858         case ixgbe_mac_X550EM_x:
5859                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5860                         return IXGBE_RETA(reta_idx >> 2);
5861                 else
5862                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5863         case ixgbe_mac_X550_vf:
5864         case ixgbe_mac_X550EM_x_vf:
5865                 return IXGBE_VFRETA(reta_idx >> 2);
5866         default:
5867                 return IXGBE_RETA(reta_idx >> 2);
5868         }
5869 }
5870
5871 uint32_t
5872 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5873         switch (mac_type) {
5874         case ixgbe_mac_X550_vf:
5875         case ixgbe_mac_X550EM_x_vf:
5876                 return IXGBE_VFMRQC;
5877         default:
5878                 return IXGBE_MRQC;
5879         }
5880 }
5881
5882 uint32_t
5883 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5884         switch (mac_type) {
5885         case ixgbe_mac_X550_vf:
5886         case ixgbe_mac_X550EM_x_vf:
5887                 return IXGBE_VFRSSRK(i);
5888         default:
5889                 return IXGBE_RSSRK(i);
5890         }
5891 }
5892
5893 bool
5894 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5895         switch (mac_type) {
5896         case ixgbe_mac_82599_vf:
5897         case ixgbe_mac_X540_vf:
5898                 return 0;
5899         default:
5900                 return 1;
5901         }
5902 }
5903
5904 static int
5905 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5906                         struct rte_eth_dcb_info *dcb_info)
5907 {
5908         struct ixgbe_dcb_config *dcb_config =
5909                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5910         struct ixgbe_dcb_tc_config *tc;
5911         uint8_t i, j;
5912
5913         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5914                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5915         else
5916                 dcb_info->nb_tcs = 1;
5917
5918         if (dcb_config->vt_mode) { /* vt is enabled*/
5919                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5920                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5921                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5922                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5923                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5924                         for (j = 0; j < dcb_info->nb_tcs; j++) {
5925                                 dcb_info->tc_queue.tc_rxq[i][j].base =
5926                                                 i * dcb_info->nb_tcs + j;
5927                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5928                                 dcb_info->tc_queue.tc_txq[i][j].base =
5929                                                 i * dcb_info->nb_tcs + j;
5930                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
5931                         }
5932                 }
5933         } else { /* vt is disabled*/
5934                 struct rte_eth_dcb_rx_conf *rx_conf =
5935                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
5936                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5937                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
5938                 if (dcb_info->nb_tcs == ETH_4_TCS) {
5939                         for (i = 0; i < dcb_info->nb_tcs; i++) {
5940                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
5941                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5942                         }
5943                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
5944                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
5945                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
5946                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
5947                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
5948                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5949                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5950                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5951                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
5952                         for (i = 0; i < dcb_info->nb_tcs; i++) {
5953                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
5954                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
5955                         }
5956                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
5957                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
5958                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
5959                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
5960                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
5961                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
5962                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
5963                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
5964                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
5965                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
5966                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
5967                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
5968                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
5969                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
5970                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
5971                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
5972                 }
5973         }
5974         for (i = 0; i < dcb_info->nb_tcs; i++) {
5975                 tc = &dcb_config->tc_config[i];
5976                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
5977         }
5978         return 0;
5979 }
5980
5981 static struct rte_driver rte_ixgbe_driver = {
5982         .type = PMD_PDEV,
5983         .init = rte_ixgbe_pmd_init,
5984 };
5985
5986 static struct rte_driver rte_ixgbevf_driver = {
5987         .type = PMD_PDEV,
5988         .init = rte_ixgbevf_pmd_init,
5989 };
5990
5991 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5992 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);