drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 549         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 550         .dev_led_on           = ixgbe_dev_led_on,
 551         .dev_led_off          = ixgbe_dev_led_off,
 552         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 553         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 554         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 555         .mac_addr_add         = ixgbe_add_rar,
 556         .mac_addr_remove      = ixgbe_remove_rar,
 557         .mac_addr_set         = ixgbe_set_default_mac_addr,
 558         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 559         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 560         .mirror_rule_set      = ixgbe_mirror_rule_set,
 561         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 562         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 563         .reta_update          = ixgbe_dev_rss_reta_update,
 564         .reta_query           = ixgbe_dev_rss_reta_query,
 565         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 566         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 567         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 568         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 569         .rxq_info_get         = ixgbe_rxq_info_get,
 570         .txq_info_get         = ixgbe_txq_info_get,
 571         .timesync_enable      = ixgbe_timesync_enable,
 572         .timesync_disable     = ixgbe_timesync_disable,
 573         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 574         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 575         .get_reg              = ixgbe_get_regs,
 576         .get_eeprom_length    = ixgbe_get_eeprom_length,
 577         .get_eeprom           = ixgbe_get_eeprom,
 578         .set_eeprom           = ixgbe_set_eeprom,
 579         .get_module_info      = ixgbe_get_module_info,
 580         .get_module_eeprom    = ixgbe_get_module_eeprom,
 581         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 582         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 583         .timesync_read_time   = ixgbe_timesync_read_time,
 584         .timesync_write_time  = ixgbe_timesync_write_time,
 585         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 586         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 587         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 588         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 589         .tm_ops_get           = ixgbe_tm_ops_get,
 590         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 591 };
 592
 593 /*
 594  * dev_ops for virtual function, bare necessities for basic vf
 595  * operation have been implemented
 596  */
 597 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 598         .dev_configure        = ixgbevf_dev_configure,
 599         .dev_start            = ixgbevf_dev_start,
 600         .dev_stop             = ixgbevf_dev_stop,
 601         .link_update          = ixgbevf_dev_link_update,
 602         .stats_get            = ixgbevf_dev_stats_get,
 603         .xstats_get           = ixgbevf_dev_xstats_get,
 604         .stats_reset          = ixgbevf_dev_stats_reset,
 605         .xstats_reset         = ixgbevf_dev_stats_reset,
 606         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 607         .dev_close            = ixgbevf_dev_close,
 608         .dev_reset            = ixgbevf_dev_reset,
 609         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 610         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 611         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 612         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 613         .dev_infos_get        = ixgbevf_dev_info_get,
 614         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 615         .mtu_set              = ixgbevf_dev_set_mtu,
 616         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 617         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 618         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 619         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 620         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 621         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 622         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 623         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 624         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 625         .mac_addr_add         = ixgbevf_add_mac_addr,
 626         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 627         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 628         .rxq_info_get         = ixgbe_rxq_info_get,
 629         .txq_info_get         = ixgbe_txq_info_get,
 630         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 631         .get_reg              = ixgbevf_get_regs,
 632         .reta_update          = ixgbe_dev_rss_reta_update,
 633         .reta_query           = ixgbe_dev_rss_reta_query,
 634         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 635         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 636         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 637 };
 638
 639 /* store statistics names and its offset in stats structure */
 640 struct rte_ixgbe_xstats_name_off {
 641         char name[RTE_ETH_XSTATS_NAME_SIZE];
 642         unsigned offset;
 643 };
 644
 645 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 646         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 647         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 648         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 649         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 650         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 651         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 652         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 653         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 654         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 655         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 656         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 657         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 658         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 659         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 660         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 661                 prc1023)},
 662         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 663                 prc1522)},
 664         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 665         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 666         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 667         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 668         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 669         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 670         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 671         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 672         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 673         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 674         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 675         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 676         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 677         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 678         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 679         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 680         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 ptc1023)},
 682         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 ptc1522)},
 684         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 685         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 686         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 687         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 688
 689         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirustat_add)},
 691         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirustat_remove)},
 693         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 694                 fdirfstat_fadd)},
 695         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 696                 fdirfstat_fremove)},
 697         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 698                 fdirmatch)},
 699         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 700                 fdirmiss)},
 701
 702         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 703         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 704         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 705                 fclast)},
 706         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 707         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 708         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 709         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 710         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 711                 fcoe_noddp)},
 712         {"rx_fcoe_no_direct_data_placement_ext_buff",
 713                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 714
 715         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 716                 lxontxc)},
 717         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 718                 lxonrxc)},
 719         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 720                 lxofftxc)},
 721         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 722                 lxoffrxc)},
 723         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 724 };
 725
 726 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 727                            sizeof(rte_ixgbe_stats_strings[0]))
 728
 729 /* MACsec statistics */
 730 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 731         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 out_pkts_untagged)},
 733         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 734                 out_pkts_encrypted)},
 735         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 736                 out_pkts_protected)},
 737         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 738                 out_octets_encrypted)},
 739         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 740                 out_octets_protected)},
 741         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 742                 in_pkts_untagged)},
 743         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_badtag)},
 745         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_nosci)},
 747         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_unknownsci)},
 749         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 750                 in_octets_decrypted)},
 751         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 752                 in_octets_validated)},
 753         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_unchecked)},
 755         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_delayed)},
 757         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_late)},
 759         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_ok)},
 761         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_invalid)},
 763         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_notvalid)},
 765         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unusedsa)},
 767         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_notusingsa)},
 769 };
 770
 771 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 772                            sizeof(rte_ixgbe_macsec_strings[0]))
 773
 774 /* Per-queue statistics */
 775 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 776         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 777         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 778         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 779         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 780 };
 781
 782 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 783                            sizeof(rte_ixgbe_rxq_strings[0]))
 784 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 785
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 787         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 788         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 789         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 790                 pxon2offc)},
 791 };
 792
 793 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 794                            sizeof(rte_ixgbe_txq_strings[0]))
 795 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 798         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 799 };
 800
 801 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 802                 sizeof(rte_ixgbevf_stats_strings[0]))
 803
 804 /*
 805  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 806  */
 807 static inline int
 808 ixgbe_is_sfp(struct ixgbe_hw *hw)
 809 {
 810         switch (hw->phy.type) {
 811         case ixgbe_phy_sfp_avago:
 812         case ixgbe_phy_sfp_ftl:
 813         case ixgbe_phy_sfp_intel:
 814         case ixgbe_phy_sfp_unknown:
 815         case ixgbe_phy_sfp_passive_tyco:
 816         case ixgbe_phy_sfp_passive_unknown:
 817                 return 1;
 818         default:
 819                 return 0;
 820         }
 821 }
 822
 823 static inline int32_t
 824 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 825 {
 826         uint32_t ctrl_ext;
 827         int32_t status;
 828
 829         status = ixgbe_reset_hw(hw);
 830
 831         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 832         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 833         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 834         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 835         IXGBE_WRITE_FLUSH(hw);
 836
 837         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 838                 status = IXGBE_SUCCESS;
 839         return status;
 840 }
 841
 842 static inline void
 843 ixgbe_enable_intr(struct rte_eth_dev *dev)
 844 {
 845         struct ixgbe_interrupt *intr =
 846                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 847         struct ixgbe_hw *hw =
 848                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 849
 850         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 851         IXGBE_WRITE_FLUSH(hw);
 852 }
 853
 854 /*
 855  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 856  */
 857 static void
 858 ixgbe_disable_intr(struct ixgbe_hw *hw)
 859 {
 860         PMD_INIT_FUNC_TRACE();
 861
 862         if (hw->mac.type == ixgbe_mac_82598EB) {
 863                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 864         } else {
 865                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 866                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 867                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 868         }
 869         IXGBE_WRITE_FLUSH(hw);
 870 }
 871
 872 /*
 873  * This function resets queue statistics mapping registers.
 874  * From Niantic datasheet, Initialization of Statistics section:
 875  * "...if software requires the queue counters, the RQSMR and TQSM registers
 876  * must be re-programmed following a device reset.
 877  */
 878 static void
 879 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 880 {
 881         uint32_t i;
 882
 883         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 884                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 885                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 886         }
 887 }
 888
 889
 890 static int
 891 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 892                                   uint16_t queue_id,
 893                                   uint8_t stat_idx,
 894                                   uint8_t is_rx)
 895 {
 896 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 897 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 898 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 899
 900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 901         struct ixgbe_stat_mapping_registers *stat_mappings =
 902                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 903         uint32_t qsmr_mask = 0;
 904         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 905         uint32_t q_map;
 906         uint8_t n, offset;
 907
 908         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 909                 (hw->mac.type != ixgbe_mac_X540) &&
 910                 (hw->mac.type != ixgbe_mac_X550) &&
 911                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 912                 (hw->mac.type != ixgbe_mac_X550EM_a))
 913                 return -ENOSYS;
 914
 915         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 916                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 917                      queue_id, stat_idx);
 918
 919         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 920         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 921                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 922                 return -EIO;
 923         }
 924         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 925
 926         /* Now clear any previous stat_idx set */
 927         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 928         if (!is_rx)
 929                 stat_mappings->tqsm[n] &= ~clearing_mask;
 930         else
 931                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 932
 933         q_map = (uint32_t)stat_idx;
 934         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 935         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 936         if (!is_rx)
 937                 stat_mappings->tqsm[n] |= qsmr_mask;
 938         else
 939                 stat_mappings->rqsmr[n] |= qsmr_mask;
 940
 941         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 942                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 943                      queue_id, stat_idx);
 944         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 945                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 946
 947         /* Now write the mapping in the appropriate register */
 948         if (is_rx) {
 949                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 950                              stat_mappings->rqsmr[n], n);
 951                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 952         } else {
 953                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 954                              stat_mappings->tqsm[n], n);
 955                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 956         }
 957         return 0;
 958 }
 959
 960 static void
 961 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 962 {
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         int i;
 967
 968         /* write whatever was in stat mapping table to the NIC */
 969         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 970                 /* rx */
 971                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 972
 973                 /* tx */
 974                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 975         }
 976 }
 977
 978 static void
 979 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 980 {
 981         uint8_t i;
 982         struct ixgbe_dcb_tc_config *tc;
 983         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 984
 985         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 986         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 987         for (i = 0; i < dcb_max_tc; i++) {
 988                 tc = &dcb_config->tc_config[i];
 989                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 990                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 991                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 992                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 993                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 994                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 995                 tc->pfc = ixgbe_dcb_pfc_disabled;
 996         }
 997
 998         /* Initialize default user to priority mapping, UPx->TC0 */
 999         tc = &dcb_config->tc_config[0];
1000         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1001         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1002         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1003                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1004                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1005         }
1006         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1007         dcb_config->pfc_mode_enable = false;
1008         dcb_config->vt_mode = true;
1009         dcb_config->round_robin_enable = false;
1010         /* support all DCB capabilities in 82599 */
1011         dcb_config->support.capabilities = 0xFF;
1012
1013         /*we only support 4 Tcs for X540, X550 */
1014         if (hw->mac.type == ixgbe_mac_X540 ||
1015                 hw->mac.type == ixgbe_mac_X550 ||
1016                 hw->mac.type == ixgbe_mac_X550EM_x ||
1017                 hw->mac.type == ixgbe_mac_X550EM_a) {
1018                 dcb_config->num_tcs.pg_tcs = 4;
1019                 dcb_config->num_tcs.pfc_tcs = 4;
1020         }
1021 }
1022
1023 /*
1024  * Ensure that all locks are released before first NVM or PHY access
1025  */
1026 static void
1027 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1028 {
1029         uint16_t mask;
1030
1031         /*
1032          * Phy lock should not fail in this early stage. If this is the case,
1033          * it is due to an improper exit of the application.
1034          * So force the release of the faulty lock. Release of common lock
1035          * is done automatically by swfw_sync function.
1036          */
1037         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1038         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1039                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1040         }
1041         ixgbe_release_swfw_semaphore(hw, mask);
1042
1043         /*
1044          * These ones are more tricky since they are common to all ports; but
1045          * swfw_sync retries last long enough (1s) to be almost sure that if
1046          * lock can not be taken it is due to an improper lock of the
1047          * semaphore.
1048          */
1049         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1050         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1051                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1052         }
1053         ixgbe_release_swfw_semaphore(hw, mask);
1054 }
1055
1056 /*
1057  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1058  * It returns 0 on success.
1059  */
1060 static int
1061 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1062 {
1063         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1064         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1065         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1066         struct ixgbe_hw *hw =
1067                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1068         struct ixgbe_vfta *shadow_vfta =
1069                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1070         struct ixgbe_hwstrip *hwstrip =
1071                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1072         struct ixgbe_dcb_config *dcb_config =
1073                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1074         struct ixgbe_filter_info *filter_info =
1075                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1076         struct ixgbe_bw_conf *bw_conf =
1077                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1078         uint32_t ctrl_ext;
1079         uint16_t csum;
1080         int diag, i;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         ixgbe_dev_macsec_setting_reset(eth_dev);
1085
1086         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1087         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1088         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1089         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1090         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1091         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1092         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1093         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1094
1095         /*
1096          * For secondary processes, we don't initialise any further as primary
1097          * has already done this work. Only check we don't need a different
1098          * RX and TX function.
1099          */
1100         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1101                 struct ixgbe_tx_queue *txq;
1102                 /* TX queue function in primary, set by last queue initialized
1103                  * Tx queue may not initialized by primary process
1104                  */
1105                 if (eth_dev->data->tx_queues) {
1106                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1107                         ixgbe_set_tx_function(eth_dev, txq);
1108                 } else {
1109                         /* Use default TX function if we get here */
1110                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1111                                      "Using default TX function.");
1112                 }
1113
1114                 ixgbe_set_rx_function(eth_dev);
1115
1116                 return 0;
1117         }
1118
1119         rte_atomic32_clear(&ad->link_thread_running);
1120         rte_eth_copy_pci_info(eth_dev, pci_dev);
1121
1122         /* Vendor and Device ID need to be set before init of shared code */
1123         hw->device_id = pci_dev->id.device_id;
1124         hw->vendor_id = pci_dev->id.vendor_id;
1125         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1126         hw->allow_unsupported_sfp = 1;
1127
1128         /* Initialize the shared code (base driver) */
1129 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1130         diag = ixgbe_bypass_init_shared_code(hw);
1131 #else
1132         diag = ixgbe_init_shared_code(hw);
1133 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1134
1135         if (diag != IXGBE_SUCCESS) {
1136                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1137                 return -EIO;
1138         }
1139
1140         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1141                 PMD_INIT_LOG(ERR, "\nERROR: "
1142                         "Firmware recovery mode detected. Limiting functionality.\n"
1143                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1144                         "User Guide for details on firmware recovery mode.");
1145                 return -EIO;
1146         }
1147
1148         /* pick up the PCI bus settings for reporting later */
1149         ixgbe_get_bus_info(hw);
1150
1151         /* Unlock any pending hardware semaphore */
1152         ixgbe_swfw_lock_reset(hw);
1153
1154 #ifdef RTE_LIBRTE_SECURITY
1155         /* Initialize security_ctx only for primary process*/
1156         if (ixgbe_ipsec_ctx_create(eth_dev))
1157                 return -ENOMEM;
1158 #endif
1159
1160         /* Initialize DCB configuration*/
1161         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1162         ixgbe_dcb_init(hw, dcb_config);
1163         /* Get Hardware Flow Control setting */
1164         hw->fc.requested_mode = ixgbe_fc_none;
1165         hw->fc.current_mode = ixgbe_fc_none;
1166         hw->fc.pause_time = IXGBE_FC_PAUSE;
1167         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1168                 hw->fc.low_water[i] = IXGBE_FC_LO;
1169                 hw->fc.high_water[i] = IXGBE_FC_HI;
1170         }
1171         hw->fc.send_xon = 1;
1172
1173         /* Make sure we have a good EEPROM before we read from it */
1174         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1175         if (diag != IXGBE_SUCCESS) {
1176                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1177                 return -EIO;
1178         }
1179
1180 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1181         diag = ixgbe_bypass_init_hw(hw);
1182 #else
1183         diag = ixgbe_init_hw(hw);
1184 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1185
1186         /*
1187          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1188          * is called too soon after the kernel driver unbinding/binding occurs.
1189          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1190          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1191          * also called. See ixgbe_identify_phy_82599(). The reason for the
1192          * failure is not known, and only occuts when virtualisation features
1193          * are disabled in the bios. A delay of 100ms  was found to be enough by
1194          * trial-and-error, and is doubled to be safe.
1195          */
1196         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1197                 rte_delay_ms(200);
1198                 diag = ixgbe_init_hw(hw);
1199         }
1200
1201         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1202                 diag = IXGBE_SUCCESS;
1203
1204         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1205                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1206                              "LOM.  Please be aware there may be issues associated "
1207                              "with your hardware.");
1208                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1209                              "please contact your Intel or hardware representative "
1210                              "who provided you with this hardware.");
1211         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1212                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1213         if (diag) {
1214                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1215                 return -EIO;
1216         }
1217
1218         /* Reset the hw statistics */
1219         ixgbe_dev_stats_reset(eth_dev);
1220
1221         /* disable interrupt */
1222         ixgbe_disable_intr(hw);
1223
1224         /* reset mappings for queue statistics hw counters*/
1225         ixgbe_reset_qstat_mappings(hw);
1226
1227         /* Allocate memory for storing MAC addresses */
1228         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1229                                                hw->mac.num_rar_entries, 0);
1230         if (eth_dev->data->mac_addrs == NULL) {
1231                 PMD_INIT_LOG(ERR,
1232                              "Failed to allocate %u bytes needed to store "
1233                              "MAC addresses",
1234                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1235                 return -ENOMEM;
1236         }
1237         /* Copy the permanent MAC address */
1238         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1239                         &eth_dev->data->mac_addrs[0]);
1240
1241         /* Allocate memory for storing hash filter MAC addresses */
1242         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1243                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1244         if (eth_dev->data->hash_mac_addrs == NULL) {
1245                 PMD_INIT_LOG(ERR,
1246                              "Failed to allocate %d bytes needed to store MAC addresses",
1247                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1248                 return -ENOMEM;
1249         }
1250
1251         /* initialize the vfta */
1252         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1253
1254         /* initialize the hw strip bitmap*/
1255         memset(hwstrip, 0, sizeof(*hwstrip));
1256
1257         /* initialize PF if max_vfs not zero */
1258         ixgbe_pf_host_init(eth_dev);
1259
1260         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1261         /* let hardware know driver is loaded */
1262         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1263         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1264         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1265         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1266         IXGBE_WRITE_FLUSH(hw);
1267
1268         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1269                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1270                              (int) hw->mac.type, (int) hw->phy.type,
1271                              (int) hw->phy.sfp_type);
1272         else
1273                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1274                              (int) hw->mac.type, (int) hw->phy.type);
1275
1276         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1277                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1278                      pci_dev->id.device_id);
1279
1280         rte_intr_callback_register(intr_handle,
1281                                    ixgbe_dev_interrupt_handler, eth_dev);
1282
1283         /* enable uio/vfio intr/eventfd mapping */
1284         rte_intr_enable(intr_handle);
1285
1286         /* enable support intr */
1287         ixgbe_enable_intr(eth_dev);
1288
1289         /* initialize filter info */
1290         memset(filter_info, 0,
1291                sizeof(struct ixgbe_filter_info));
1292
1293         /* initialize 5tuple filter list */
1294         TAILQ_INIT(&filter_info->fivetuple_list);
1295
1296         /* initialize flow director filter list & hash */
1297         ixgbe_fdir_filter_init(eth_dev);
1298
1299         /* initialize l2 tunnel filter list & hash */
1300         ixgbe_l2_tn_filter_init(eth_dev);
1301
1302         /* initialize flow filter lists */
1303         ixgbe_filterlist_init();
1304
1305         /* initialize bandwidth configuration info */
1306         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1307
1308         /* initialize Traffic Manager configuration */
1309         ixgbe_tm_conf_init(eth_dev);
1310
1311         return 0;
1312 }
1313
1314 static int
1315 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1316 {
1317         PMD_INIT_FUNC_TRACE();
1318
1319         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1320                 return 0;
1321
1322         ixgbe_dev_close(eth_dev);
1323
1324         return 0;
1325 }
1326
1327 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1328 {
1329         struct ixgbe_filter_info *filter_info =
1330                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1331         struct ixgbe_5tuple_filter *p_5tuple;
1332
1333         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1334                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1335                              p_5tuple,
1336                              entries);
1337                 rte_free(p_5tuple);
1338         }
1339         memset(filter_info->fivetuple_mask, 0,
1340                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1341
1342         return 0;
1343 }
1344
1345 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1346 {
1347         struct ixgbe_hw_fdir_info *fdir_info =
1348                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1349         struct ixgbe_fdir_filter *fdir_filter;
1350
1351                 if (fdir_info->hash_map)
1352                 rte_free(fdir_info->hash_map);
1353         if (fdir_info->hash_handle)
1354                 rte_hash_free(fdir_info->hash_handle);
1355
1356         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1357                 TAILQ_REMOVE(&fdir_info->fdir_list,
1358                              fdir_filter,
1359                              entries);
1360                 rte_free(fdir_filter);
1361         }
1362
1363         return 0;
1364 }
1365
1366 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct ixgbe_l2_tn_info *l2_tn_info =
1369                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1370         struct ixgbe_l2_tn_filter *l2_tn_filter;
1371
1372         if (l2_tn_info->hash_map)
1373                 rte_free(l2_tn_info->hash_map);
1374         if (l2_tn_info->hash_handle)
1375                 rte_hash_free(l2_tn_info->hash_handle);
1376
1377         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1378                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1379                              l2_tn_filter,
1380                              entries);
1381                 rte_free(l2_tn_filter);
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1388 {
1389         struct ixgbe_hw_fdir_info *fdir_info =
1390                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1391         char fdir_hash_name[RTE_HASH_NAMESIZE];
1392         struct rte_hash_parameters fdir_hash_params = {
1393                 .name = fdir_hash_name,
1394                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1395                 .key_len = sizeof(union ixgbe_atr_input),
1396                 .hash_func = rte_hash_crc,
1397                 .hash_func_init_val = 0,
1398                 .socket_id = rte_socket_id(),
1399         };
1400
1401         TAILQ_INIT(&fdir_info->fdir_list);
1402         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1403                  "fdir_%s", eth_dev->device->name);
1404         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1405         if (!fdir_info->hash_handle) {
1406                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1407                 return -EINVAL;
1408         }
1409         fdir_info->hash_map = rte_zmalloc("ixgbe",
1410                                           sizeof(struct ixgbe_fdir_filter *) *
1411                                           IXGBE_MAX_FDIR_FILTER_NUM,
1412                                           0);
1413         if (!fdir_info->hash_map) {
1414                 PMD_INIT_LOG(ERR,
1415                              "Failed to allocate memory for fdir hash map!");
1416                 return -ENOMEM;
1417         }
1418         fdir_info->mask_added = FALSE;
1419
1420         return 0;
1421 }
1422
1423 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1424 {
1425         struct ixgbe_l2_tn_info *l2_tn_info =
1426                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1427         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1428         struct rte_hash_parameters l2_tn_hash_params = {
1429                 .name = l2_tn_hash_name,
1430                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1431                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1432                 .hash_func = rte_hash_crc,
1433                 .hash_func_init_val = 0,
1434                 .socket_id = rte_socket_id(),
1435         };
1436
1437         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1438         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1439                  "l2_tn_%s", eth_dev->device->name);
1440         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1441         if (!l2_tn_info->hash_handle) {
1442                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1443                 return -EINVAL;
1444         }
1445         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1446                                    sizeof(struct ixgbe_l2_tn_filter *) *
1447                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1448                                    0);
1449         if (!l2_tn_info->hash_map) {
1450                 PMD_INIT_LOG(ERR,
1451                         "Failed to allocate memory for L2 TN hash map!");
1452                 return -ENOMEM;
1453         }
1454         l2_tn_info->e_tag_en = FALSE;
1455         l2_tn_info->e_tag_fwd_en = FALSE;
1456         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1457
1458         return 0;
1459 }
1460 /*
1461  * Negotiate mailbox API version with the PF.
1462  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1463  * Then we try to negotiate starting with the most recent one.
1464  * If all negotiation attempts fail, then we will proceed with
1465  * the default one (ixgbe_mbox_api_10).
1466  */
1467 static void
1468 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1469 {
1470         int32_t i;
1471
1472         /* start with highest supported, proceed down */
1473         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1474                 ixgbe_mbox_api_13,
1475                 ixgbe_mbox_api_12,
1476                 ixgbe_mbox_api_11,
1477                 ixgbe_mbox_api_10,
1478         };
1479
1480         for (i = 0;
1481                         i != RTE_DIM(sup_ver) &&
1482                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1483                         i++)
1484                 ;
1485 }
1486
1487 static void
1488 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1489 {
1490         uint64_t random;
1491
1492         /* Set Organizationally Unique Identifier (OUI) prefix. */
1493         mac_addr->addr_bytes[0] = 0x00;
1494         mac_addr->addr_bytes[1] = 0x09;
1495         mac_addr->addr_bytes[2] = 0xC0;
1496         /* Force indication of locally assigned MAC address. */
1497         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1498         /* Generate the last 3 bytes of the MAC address with a random number. */
1499         random = rte_rand();
1500         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1501 }
1502
1503 static int
1504 devarg_handle_int(__rte_unused const char *key, const char *value,
1505                   void *extra_args)
1506 {
1507         uint16_t *n = extra_args;
1508
1509         if (value == NULL || extra_args == NULL)
1510                 return -EINVAL;
1511
1512         *n = (uint16_t)strtoul(value, NULL, 0);
1513         if (*n == USHRT_MAX && errno == ERANGE)
1514                 return -1;
1515
1516         return 0;
1517 }
1518
1519 static void
1520 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1521                       struct rte_devargs *devargs)
1522 {
1523         struct rte_kvargs *kvlist;
1524         uint16_t pflink_fullchk;
1525
1526         if (devargs == NULL)
1527                 return;
1528
1529         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1530         if (kvlist == NULL)
1531                 return;
1532
1533         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1534             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1535                                devarg_handle_int, &pflink_fullchk) == 0 &&
1536             pflink_fullchk == 1)
1537                 adapter->pflink_fullchk = 1;
1538
1539         rte_kvargs_free(kvlist);
1540 }
1541
1542 /*
1543  * Virtual Function device init
1544  */
1545 static int
1546 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1547 {
1548         int diag;
1549         uint32_t tc, tcs;
1550         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1551         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1552         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1553         struct ixgbe_hw *hw =
1554                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1555         struct ixgbe_vfta *shadow_vfta =
1556                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1557         struct ixgbe_hwstrip *hwstrip =
1558                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1559         struct rte_ether_addr *perm_addr =
1560                 (struct rte_ether_addr *)hw->mac.perm_addr;
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1565         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1566         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1567         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1568         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1569         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1570
1571         /* for secondary processes, we don't initialise any further as primary
1572          * has already done this work. Only check we don't need a different
1573          * RX function
1574          */
1575         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1576                 struct ixgbe_tx_queue *txq;
1577                 /* TX queue function in primary, set by last queue initialized
1578                  * Tx queue may not initialized by primary process
1579                  */
1580                 if (eth_dev->data->tx_queues) {
1581                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1582                         ixgbe_set_tx_function(eth_dev, txq);
1583                 } else {
1584                         /* Use default TX function if we get here */
1585                         PMD_INIT_LOG(NOTICE,
1586                                      "No TX queues configured yet. Using default TX function.");
1587                 }
1588
1589                 ixgbe_set_rx_function(eth_dev);
1590
1591                 return 0;
1592         }
1593
1594         rte_atomic32_clear(&ad->link_thread_running);
1595         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1596                               pci_dev->device.devargs);
1597
1598         rte_eth_copy_pci_info(eth_dev, pci_dev);
1599
1600         hw->device_id = pci_dev->id.device_id;
1601         hw->vendor_id = pci_dev->id.vendor_id;
1602         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1603
1604         /* initialize the vfta */
1605         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1606
1607         /* initialize the hw strip bitmap*/
1608         memset(hwstrip, 0, sizeof(*hwstrip));
1609
1610         /* Initialize the shared code (base driver) */
1611         diag = ixgbe_init_shared_code(hw);
1612         if (diag != IXGBE_SUCCESS) {
1613                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1614                 return -EIO;
1615         }
1616
1617         /* init_mailbox_params */
1618         hw->mbx.ops.init_params(hw);
1619
1620         /* Reset the hw statistics */
1621         ixgbevf_dev_stats_reset(eth_dev);
1622
1623         /* Disable the interrupts for VF */
1624         ixgbevf_intr_disable(eth_dev);
1625
1626         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1627         diag = hw->mac.ops.reset_hw(hw);
1628
1629         /*
1630          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1631          * the underlying PF driver has not assigned a MAC address to the VF.
1632          * In this case, assign a random MAC address.
1633          */
1634         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1635                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1636                 /*
1637                  * This error code will be propagated to the app by
1638                  * rte_eth_dev_reset, so use a public error code rather than
1639                  * the internal-only IXGBE_ERR_RESET_FAILED
1640                  */
1641                 return -EAGAIN;
1642         }
1643
1644         /* negotiate mailbox API version to use with the PF. */
1645         ixgbevf_negotiate_api(hw);
1646
1647         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1648         ixgbevf_get_queues(hw, &tcs, &tc);
1649
1650         /* Allocate memory for storing MAC addresses */
1651         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1652                                                hw->mac.num_rar_entries, 0);
1653         if (eth_dev->data->mac_addrs == NULL) {
1654                 PMD_INIT_LOG(ERR,
1655                              "Failed to allocate %u bytes needed to store "
1656                              "MAC addresses",
1657                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1658                 return -ENOMEM;
1659         }
1660
1661         /* Generate a random MAC address, if none was assigned by PF. */
1662         if (rte_is_zero_ether_addr(perm_addr)) {
1663                 generate_random_mac_addr(perm_addr);
1664                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1665                 if (diag) {
1666                         rte_free(eth_dev->data->mac_addrs);
1667                         eth_dev->data->mac_addrs = NULL;
1668                         return diag;
1669                 }
1670                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1671                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1672                              "%02x:%02x:%02x:%02x:%02x:%02x",
1673                              perm_addr->addr_bytes[0],
1674                              perm_addr->addr_bytes[1],
1675                              perm_addr->addr_bytes[2],
1676                              perm_addr->addr_bytes[3],
1677                              perm_addr->addr_bytes[4],
1678                              perm_addr->addr_bytes[5]);
1679         }
1680
1681         /* Copy the permanent MAC address */
1682         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1683
1684         /* reset the hardware with the new settings */
1685         diag = hw->mac.ops.start_hw(hw);
1686         switch (diag) {
1687         case  0:
1688                 break;
1689
1690         default:
1691                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1692                 return -EIO;
1693         }
1694
1695         rte_intr_callback_register(intr_handle,
1696                                    ixgbevf_dev_interrupt_handler, eth_dev);
1697         rte_intr_enable(intr_handle);
1698         ixgbevf_intr_enable(eth_dev);
1699
1700         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1701                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1702                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1703
1704         return 0;
1705 }
1706
1707 /* Virtual Function device uninit */
1708
1709 static int
1710 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1711 {
1712         PMD_INIT_FUNC_TRACE();
1713
1714         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1715                 return 0;
1716
1717         ixgbevf_dev_close(eth_dev);
1718
1719         return 0;
1720 }
1721
1722 static int
1723 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1724                 struct rte_pci_device *pci_dev)
1725 {
1726         char name[RTE_ETH_NAME_MAX_LEN];
1727         struct rte_eth_dev *pf_ethdev;
1728         struct rte_eth_devargs eth_da;
1729         int i, retval;
1730
1731         if (pci_dev->device.devargs) {
1732                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1733                                 &eth_da);
1734                 if (retval)
1735                         return retval;
1736         } else
1737                 memset(&eth_da, 0, sizeof(eth_da));
1738
1739         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1740                 sizeof(struct ixgbe_adapter),
1741                 eth_dev_pci_specific_init, pci_dev,
1742                 eth_ixgbe_dev_init, NULL);
1743
1744         if (retval || eth_da.nb_representor_ports < 1)
1745                 return retval;
1746
1747         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1748         if (pf_ethdev == NULL)
1749                 return -ENODEV;
1750
1751         /* probe VF representor ports */
1752         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1753                 struct ixgbe_vf_info *vfinfo;
1754                 struct ixgbe_vf_representor representor;
1755
1756                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1757                         pf_ethdev->data->dev_private);
1758                 if (vfinfo == NULL) {
1759                         PMD_DRV_LOG(ERR,
1760                                 "no virtual functions supported by PF");
1761                         break;
1762                 }
1763
1764                 representor.vf_id = eth_da.representor_ports[i];
1765                 representor.switch_domain_id = vfinfo->switch_domain_id;
1766                 representor.pf_ethdev = pf_ethdev;
1767
1768                 /* representor port net_bdf_port */
1769                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1770                         pci_dev->device.name,
1771                         eth_da.representor_ports[i]);
1772
1773                 retval = rte_eth_dev_create(&pci_dev->device, name,
1774                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1775                         ixgbe_vf_representor_init, &representor);
1776
1777                 if (retval)
1778                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1779                                 "representor %s.", name);
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1786 {
1787         struct rte_eth_dev *ethdev;
1788
1789         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1790         if (!ethdev)
1791                 return 0;
1792
1793         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1794                 return rte_eth_dev_pci_generic_remove(pci_dev,
1795                                         ixgbe_vf_representor_uninit);
1796         else
1797                 return rte_eth_dev_pci_generic_remove(pci_dev,
1798                                                 eth_ixgbe_dev_uninit);
1799 }
1800
1801 static struct rte_pci_driver rte_ixgbe_pmd = {
1802         .id_table = pci_id_ixgbe_map,
1803         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1804         .probe = eth_ixgbe_pci_probe,
1805         .remove = eth_ixgbe_pci_remove,
1806 };
1807
1808 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1809         struct rte_pci_device *pci_dev)
1810 {
1811         return rte_eth_dev_pci_generic_probe(pci_dev,
1812                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1813 }
1814
1815 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1816 {
1817         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1818 }
1819
1820 /*
1821  * virtual function driver struct
1822  */
1823 static struct rte_pci_driver rte_ixgbevf_pmd = {
1824         .id_table = pci_id_ixgbevf_map,
1825         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1826         .probe = eth_ixgbevf_pci_probe,
1827         .remove = eth_ixgbevf_pci_remove,
1828 };
1829
1830 static int
1831 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1832 {
1833         struct ixgbe_hw *hw =
1834                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1835         struct ixgbe_vfta *shadow_vfta =
1836                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1837         uint32_t vfta;
1838         uint32_t vid_idx;
1839         uint32_t vid_bit;
1840
1841         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1842         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1843         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1844         if (on)
1845                 vfta |= vid_bit;
1846         else
1847                 vfta &= ~vid_bit;
1848         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1849
1850         /* update local VFTA copy */
1851         shadow_vfta->vfta[vid_idx] = vfta;
1852
1853         return 0;
1854 }
1855
1856 static void
1857 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1858 {
1859         if (on)
1860                 ixgbe_vlan_hw_strip_enable(dev, queue);
1861         else
1862                 ixgbe_vlan_hw_strip_disable(dev, queue);
1863 }
1864
1865 static int
1866 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1867                     enum rte_vlan_type vlan_type,
1868                     uint16_t tpid)
1869 {
1870         struct ixgbe_hw *hw =
1871                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872         int ret = 0;
1873         uint32_t reg;
1874         uint32_t qinq;
1875
1876         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1877         qinq &= IXGBE_DMATXCTL_GDV;
1878
1879         switch (vlan_type) {
1880         case ETH_VLAN_TYPE_INNER:
1881                 if (qinq) {
1882                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1889                 } else {
1890                         ret = -ENOTSUP;
1891                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1892                                     " by single VLAN");
1893                 }
1894                 break;
1895         case ETH_VLAN_TYPE_OUTER:
1896                 if (qinq) {
1897                         /* Only the high 16-bits is valid */
1898                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1899                                         IXGBE_EXVET_VET_EXT_SHIFT);
1900                 } else {
1901                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1902                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1903                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1904                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1905                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1906                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1907                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1908                 }
1909
1910                 break;
1911         default:
1912                 ret = -EINVAL;
1913                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1914                 break;
1915         }
1916
1917         return ret;
1918 }
1919
1920 void
1921 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1922 {
1923         struct ixgbe_hw *hw =
1924                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925         uint32_t vlnctrl;
1926
1927         PMD_INIT_FUNC_TRACE();
1928
1929         /* Filter Table Disable */
1930         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1932
1933         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1934 }
1935
1936 void
1937 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         struct ixgbe_vfta *shadow_vfta =
1942                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1943         uint32_t vlnctrl;
1944         uint16_t i;
1945
1946         PMD_INIT_FUNC_TRACE();
1947
1948         /* Filter Table Enable */
1949         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1950         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1951         vlnctrl |= IXGBE_VLNCTRL_VFE;
1952
1953         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1954
1955         /* write whatever is in local vfta copy */
1956         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1957                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1958 }
1959
1960 static void
1961 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1962 {
1963         struct ixgbe_hwstrip *hwstrip =
1964                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1965         struct ixgbe_rx_queue *rxq;
1966
1967         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1968                 return;
1969
1970         if (on)
1971                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1972         else
1973                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1974
1975         if (queue >= dev->data->nb_rx_queues)
1976                 return;
1977
1978         rxq = dev->data->rx_queues[queue];
1979
1980         if (on) {
1981                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1982                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1983         } else {
1984                 rxq->vlan_flags = PKT_RX_VLAN;
1985                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1986         }
1987 }
1988
1989 static void
1990 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1991 {
1992         struct ixgbe_hw *hw =
1993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994         uint32_t ctrl;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         if (hw->mac.type == ixgbe_mac_82598EB) {
1999                 /* No queue level support */
2000                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2001                 return;
2002         }
2003
2004         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2005         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2006         ctrl &= ~IXGBE_RXDCTL_VME;
2007         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2008
2009         /* record those setting for HW strip per queue */
2010         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2011 }
2012
2013 static void
2014 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2015 {
2016         struct ixgbe_hw *hw =
2017                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2018         uint32_t ctrl;
2019
2020         PMD_INIT_FUNC_TRACE();
2021
2022         if (hw->mac.type == ixgbe_mac_82598EB) {
2023                 /* No queue level supported */
2024                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2025                 return;
2026         }
2027
2028         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2029         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2030         ctrl |= IXGBE_RXDCTL_VME;
2031         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2032
2033         /* record those setting for HW strip per queue */
2034         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2035 }
2036
2037 static void
2038 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2039 {
2040         struct ixgbe_hw *hw =
2041                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042         uint32_t ctrl;
2043
2044         PMD_INIT_FUNC_TRACE();
2045
2046         /* DMATXCTRL: Geric Double VLAN Disable */
2047         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2048         ctrl &= ~IXGBE_DMATXCTL_GDV;
2049         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2050
2051         /* CTRL_EXT: Global Double VLAN Disable */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2053         ctrl &= ~IXGBE_EXTENDED_VLAN;
2054         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2055
2056 }
2057
2058 static void
2059 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t ctrl;
2064
2065         PMD_INIT_FUNC_TRACE();
2066
2067         /* DMATXCTRL: Geric Double VLAN Enable */
2068         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2069         ctrl |= IXGBE_DMATXCTL_GDV;
2070         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2071
2072         /* CTRL_EXT: Global Double VLAN Enable */
2073         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2074         ctrl |= IXGBE_EXTENDED_VLAN;
2075         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2076
2077         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2078         if (hw->mac.type == ixgbe_mac_X550 ||
2079             hw->mac.type == ixgbe_mac_X550EM_x ||
2080             hw->mac.type == ixgbe_mac_X550EM_a) {
2081                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2082                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2083                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2084         }
2085
2086         /*
2087          * VET EXT field in the EXVET register = 0x8100 by default
2088          * So no need to change. Same to VT field of DMATXCTL register
2089          */
2090 }
2091
2092 void
2093 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2094 {
2095         struct ixgbe_hw *hw =
2096                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2097         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2098         uint32_t ctrl;
2099         uint16_t i;
2100         struct ixgbe_rx_queue *rxq;
2101         bool on;
2102
2103         PMD_INIT_FUNC_TRACE();
2104
2105         if (hw->mac.type == ixgbe_mac_82598EB) {
2106                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2107                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2108                         ctrl |= IXGBE_VLNCTRL_VME;
2109                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2110                 } else {
2111                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2112                         ctrl &= ~IXGBE_VLNCTRL_VME;
2113                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2114                 }
2115         } else {
2116                 /*
2117                  * Other 10G NIC, the VLAN strip can be setup
2118                  * per queue in RXDCTL
2119                  */
2120                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2121                         rxq = dev->data->rx_queues[i];
2122                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2123                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2124                                 ctrl |= IXGBE_RXDCTL_VME;
2125                                 on = TRUE;
2126                         } else {
2127                                 ctrl &= ~IXGBE_RXDCTL_VME;
2128                                 on = FALSE;
2129                         }
2130                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2131
2132                         /* record those setting for HW strip per queue */
2133                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2134                 }
2135         }
2136 }
2137
2138 static void
2139 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2140 {
2141         uint16_t i;
2142         struct rte_eth_rxmode *rxmode;
2143         struct ixgbe_rx_queue *rxq;
2144
2145         if (mask & ETH_VLAN_STRIP_MASK) {
2146                 rxmode = &dev->data->dev_conf.rxmode;
2147                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2148                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2149                                 rxq = dev->data->rx_queues[i];
2150                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2151                         }
2152                 else
2153                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2154                                 rxq = dev->data->rx_queues[i];
2155                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2156                         }
2157         }
2158 }
2159
2160 static int
2161 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2162 {
2163         struct rte_eth_rxmode *rxmode;
2164         rxmode = &dev->data->dev_conf.rxmode;
2165
2166         if (mask & ETH_VLAN_STRIP_MASK) {
2167                 ixgbe_vlan_hw_strip_config(dev);
2168         }
2169
2170         if (mask & ETH_VLAN_FILTER_MASK) {
2171                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2172                         ixgbe_vlan_hw_filter_enable(dev);
2173                 else
2174                         ixgbe_vlan_hw_filter_disable(dev);
2175         }
2176
2177         if (mask & ETH_VLAN_EXTEND_MASK) {
2178                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2179                         ixgbe_vlan_hw_extend_enable(dev);
2180                 else
2181                         ixgbe_vlan_hw_extend_disable(dev);
2182         }
2183
2184         return 0;
2185 }
2186
2187 static int
2188 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2189 {
2190         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2191
2192         ixgbe_vlan_offload_config(dev, mask);
2193
2194         return 0;
2195 }
2196
2197 static void
2198 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2199 {
2200         struct ixgbe_hw *hw =
2201                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2203         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2204
2205         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2206         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2207 }
2208
2209 static int
2210 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2211 {
2212         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2213
2214         switch (nb_rx_q) {
2215         case 1:
2216         case 2:
2217                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2218                 break;
2219         case 4:
2220                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2221                 break;
2222         default:
2223                 return -EINVAL;
2224         }
2225
2226         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2227                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2228         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2229                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2230         return 0;
2231 }
2232
2233 static int
2234 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2235 {
2236         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2237         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2239         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2240
2241         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2242                 /* check multi-queue mode */
2243                 switch (dev_conf->rxmode.mq_mode) {
2244                 case ETH_MQ_RX_VMDQ_DCB:
2245                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2246                         break;
2247                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2248                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2249                         PMD_INIT_LOG(ERR, "SRIOV active,"
2250                                         " unsupported mq_mode rx %d.",
2251                                         dev_conf->rxmode.mq_mode);
2252                         return -EINVAL;
2253                 case ETH_MQ_RX_RSS:
2254                 case ETH_MQ_RX_VMDQ_RSS:
2255                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2256                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2257                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2258                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2259                                                 " invalid queue number"
2260                                                 " for VMDQ RSS, allowed"
2261                                                 " value are 1, 2 or 4.");
2262                                         return -EINVAL;
2263                                 }
2264                         break;
2265                 case ETH_MQ_RX_VMDQ_ONLY:
2266                 case ETH_MQ_RX_NONE:
2267                         /* if nothing mq mode configure, use default scheme */
2268                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2269                         break;
2270                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2271                         /* SRIOV only works in VMDq enable mode */
2272                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2273                                         " wrong mq_mode rx %d.",
2274                                         dev_conf->rxmode.mq_mode);
2275                         return -EINVAL;
2276                 }
2277
2278                 switch (dev_conf->txmode.mq_mode) {
2279                 case ETH_MQ_TX_VMDQ_DCB:
2280                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2281                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2282                         break;
2283                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2284                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2285                         break;
2286                 }
2287
2288                 /* check valid queue number */
2289                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2290                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2291                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2292                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2293                                         " must be less than or equal to %d.",
2294                                         nb_rx_q, nb_tx_q,
2295                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2296                         return -EINVAL;
2297                 }
2298         } else {
2299                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2300                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2301                                           " not supported.");
2302                         return -EINVAL;
2303                 }
2304                 /* check configuration for vmdb+dcb mode */
2305                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2306                         const struct rte_eth_vmdq_dcb_conf *conf;
2307
2308                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2309                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2310                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2311                                 return -EINVAL;
2312                         }
2313                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2314                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2315                                conf->nb_queue_pools == ETH_32_POOLS)) {
2316                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2317                                                 " nb_queue_pools must be %d or %d.",
2318                                                 ETH_16_POOLS, ETH_32_POOLS);
2319                                 return -EINVAL;
2320                         }
2321                 }
2322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2323                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2324
2325                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2327                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2328                                 return -EINVAL;
2329                         }
2330                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2331                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2332                                conf->nb_queue_pools == ETH_32_POOLS)) {
2333                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2334                                                 " nb_queue_pools != %d and"
2335                                                 " nb_queue_pools != %d.",
2336                                                 ETH_16_POOLS, ETH_32_POOLS);
2337                                 return -EINVAL;
2338                         }
2339                 }
2340
2341                 /* For DCB mode check our configuration before we go further */
2342                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2343                         const struct rte_eth_dcb_rx_conf *conf;
2344
2345                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2346                         if (!(conf->nb_tcs == ETH_4_TCS ||
2347                                conf->nb_tcs == ETH_8_TCS)) {
2348                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2349                                                 " and nb_tcs != %d.",
2350                                                 ETH_4_TCS, ETH_8_TCS);
2351                                 return -EINVAL;
2352                         }
2353                 }
2354
2355                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2356                         const struct rte_eth_dcb_tx_conf *conf;
2357
2358                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2359                         if (!(conf->nb_tcs == ETH_4_TCS ||
2360                                conf->nb_tcs == ETH_8_TCS)) {
2361                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2362                                                 " and nb_tcs != %d.",
2363                                                 ETH_4_TCS, ETH_8_TCS);
2364                                 return -EINVAL;
2365                         }
2366                 }
2367
2368                 /*
2369                  * When DCB/VT is off, maximum number of queues changes,
2370                  * except for 82598EB, which remains constant.
2371                  */
2372                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2373                                 hw->mac.type != ixgbe_mac_82598EB) {
2374                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2375                                 PMD_INIT_LOG(ERR,
2376                                              "Neither VT nor DCB are enabled, "
2377                                              "nb_tx_q > %d.",
2378                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2379                                 return -EINVAL;
2380                         }
2381                 }
2382         }
2383         return 0;
2384 }
2385
2386 static int
2387 ixgbe_dev_configure(struct rte_eth_dev *dev)
2388 {
2389         struct ixgbe_interrupt *intr =
2390                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2391         struct ixgbe_adapter *adapter = dev->data->dev_private;
2392         int ret;
2393
2394         PMD_INIT_FUNC_TRACE();
2395
2396         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2397                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2398
2399         /* multipe queue mode checking */
2400         ret  = ixgbe_check_mq_mode(dev);
2401         if (ret != 0) {
2402                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2403                             ret);
2404                 return ret;
2405         }
2406
2407         /* set flag to update link status after init */
2408         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2409
2410         /*
2411          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2412          * allocation or vector Rx preconditions we will reset it.
2413          */
2414         adapter->rx_bulk_alloc_allowed = true;
2415         adapter->rx_vec_allowed = true;
2416
2417         return 0;
2418 }
2419
2420 static void
2421 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2422 {
2423         struct ixgbe_hw *hw =
2424                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2425         struct ixgbe_interrupt *intr =
2426                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2427         uint32_t gpie;
2428
2429         /* only set up it on X550EM_X */
2430         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2431                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2432                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2433                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2434                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2435                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2436         }
2437 }
2438
2439 int
2440 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2441                         uint16_t tx_rate, uint64_t q_msk)
2442 {
2443         struct ixgbe_hw *hw;
2444         struct ixgbe_vf_info *vfinfo;
2445         struct rte_eth_link link;
2446         uint8_t  nb_q_per_pool;
2447         uint32_t queue_stride;
2448         uint32_t queue_idx, idx = 0, vf_idx;
2449         uint32_t queue_end;
2450         uint16_t total_rate = 0;
2451         struct rte_pci_device *pci_dev;
2452         int ret;
2453
2454         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2455         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2456         if (ret < 0)
2457                 return ret;
2458
2459         if (vf >= pci_dev->max_vfs)
2460                 return -EINVAL;
2461
2462         if (tx_rate > link.link_speed)
2463                 return -EINVAL;
2464
2465         if (q_msk == 0)
2466                 return 0;
2467
2468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2470         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2471         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2472         queue_idx = vf * queue_stride;
2473         queue_end = queue_idx + nb_q_per_pool - 1;
2474         if (queue_end >= hw->mac.max_tx_queues)
2475                 return -EINVAL;
2476
2477         if (vfinfo) {
2478                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2479                         if (vf_idx == vf)
2480                                 continue;
2481                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2482                                 idx++)
2483                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2484                 }
2485         } else {
2486                 return -EINVAL;
2487         }
2488
2489         /* Store tx_rate for this vf. */
2490         for (idx = 0; idx < nb_q_per_pool; idx++) {
2491                 if (((uint64_t)0x1 << idx) & q_msk) {
2492                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2493                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2494                         total_rate += tx_rate;
2495                 }
2496         }
2497
2498         if (total_rate > dev->data->dev_link.link_speed) {
2499                 /* Reset stored TX rate of the VF if it causes exceed
2500                  * link speed.
2501                  */
2502                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2503                 return -EINVAL;
2504         }
2505
2506         /* Set RTTBCNRC of each queue/pool for vf X  */
2507         for (; queue_idx <= queue_end; queue_idx++) {
2508                 if (0x1 & q_msk)
2509                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2510                 q_msk = q_msk >> 1;
2511         }
2512
2513         return 0;
2514 }
2515
2516 static int
2517 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2518 {
2519         struct ixgbe_adapter *adapter = dev->data->dev_private;
2520         int err;
2521         uint32_t mflcn;
2522
2523         ixgbe_setup_fc(hw);
2524
2525         err = ixgbe_fc_enable(hw);
2526
2527         /* Not negotiated is not an error case */
2528         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2529                 /*
2530                  *check if we want to forward MAC frames - driver doesn't
2531                  *have native capability to do that,
2532                  *so we'll write the registers ourselves
2533                  */
2534
2535                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2536
2537                 /* set or clear MFLCN.PMCF bit depending on configuration */
2538                 if (adapter->mac_ctrl_frame_fwd != 0)
2539                         mflcn |= IXGBE_MFLCN_PMCF;
2540                 else
2541                         mflcn &= ~IXGBE_MFLCN_PMCF;
2542
2543                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2544                 IXGBE_WRITE_FLUSH(hw);
2545
2546                 return 0;
2547         }
2548         return err;
2549 }
2550
2551 /*
2552  * Configure device link speed and setup link.
2553  * It returns 0 on success.
2554  */
2555 static int
2556 ixgbe_dev_start(struct rte_eth_dev *dev)
2557 {
2558         struct ixgbe_hw *hw =
2559                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2560         struct ixgbe_vf_info *vfinfo =
2561                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2564         uint32_t intr_vector = 0;
2565         int err;
2566         bool link_up = false, negotiate = 0;
2567         uint32_t speed = 0;
2568         uint32_t allowed_speeds = 0;
2569         int mask = 0;
2570         int status;
2571         uint16_t vf, idx;
2572         uint32_t *link_speeds;
2573         struct ixgbe_tm_conf *tm_conf =
2574                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2575         struct ixgbe_macsec_setting *macsec_setting =
2576                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2577
2578         PMD_INIT_FUNC_TRACE();
2579
2580         /* Stop the link setup handler before resetting the HW. */
2581         ixgbe_dev_wait_setup_link_complete(dev, 0);
2582
2583         /* disable uio/vfio intr/eventfd mapping */
2584         rte_intr_disable(intr_handle);
2585
2586         /* stop adapter */
2587         hw->adapter_stopped = 0;
2588         ixgbe_stop_adapter(hw);
2589
2590         /* reinitialize adapter
2591          * this calls reset and start
2592          */
2593         status = ixgbe_pf_reset_hw(hw);
2594         if (status != 0)
2595                 return -1;
2596         hw->mac.ops.start_hw(hw);
2597         hw->mac.get_link_status = true;
2598
2599         /* configure PF module if SRIOV enabled */
2600         ixgbe_pf_host_configure(dev);
2601
2602         ixgbe_dev_phy_intr_setup(dev);
2603
2604         /* check and configure queue intr-vector mapping */
2605         if ((rte_intr_cap_multiple(intr_handle) ||
2606              !RTE_ETH_DEV_SRIOV(dev).active) &&
2607             dev->data->dev_conf.intr_conf.rxq != 0) {
2608                 intr_vector = dev->data->nb_rx_queues;
2609                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2610                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2611                                         IXGBE_MAX_INTR_QUEUE_NUM);
2612                         return -ENOTSUP;
2613                 }
2614                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2615                         return -1;
2616         }
2617
2618         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2619                 intr_handle->intr_vec =
2620                         rte_zmalloc("intr_vec",
2621                                     dev->data->nb_rx_queues * sizeof(int), 0);
2622                 if (intr_handle->intr_vec == NULL) {
2623                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2624                                      " intr_vec", dev->data->nb_rx_queues);
2625                         return -ENOMEM;
2626                 }
2627         }
2628
2629         /* confiugre msix for sleep until rx interrupt */
2630         ixgbe_configure_msix(dev);
2631
2632         /* initialize transmission unit */
2633         ixgbe_dev_tx_init(dev);
2634
2635         /* This can fail when allocating mbufs for descriptor rings */
2636         err = ixgbe_dev_rx_init(dev);
2637         if (err) {
2638                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2639                 goto error;
2640         }
2641
2642         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2643                 ETH_VLAN_EXTEND_MASK;
2644         err = ixgbe_vlan_offload_config(dev, mask);
2645         if (err) {
2646                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2647                 goto error;
2648         }
2649
2650         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2651                 /* Enable vlan filtering for VMDq */
2652                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2653         }
2654
2655         /* Configure DCB hw */
2656         ixgbe_configure_dcb(dev);
2657
2658         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2659                 err = ixgbe_fdir_configure(dev);
2660                 if (err)
2661                         goto error;
2662         }
2663
2664         /* Restore vf rate limit */
2665         if (vfinfo != NULL) {
2666                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2667                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2668                                 if (vfinfo[vf].tx_rate[idx] != 0)
2669                                         ixgbe_set_vf_rate_limit(
2670                                                 dev, vf,
2671                                                 vfinfo[vf].tx_rate[idx],
2672                                                 1 << idx);
2673         }
2674
2675         ixgbe_restore_statistics_mapping(dev);
2676
2677         err = ixgbe_flow_ctrl_enable(dev, hw);
2678         if (err < 0) {
2679                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2680                 goto error;
2681         }
2682
2683         err = ixgbe_dev_rxtx_start(dev);
2684         if (err < 0) {
2685                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2686                 goto error;
2687         }
2688
2689         /* Skip link setup if loopback mode is enabled. */
2690         if (dev->data->dev_conf.lpbk_mode != 0) {
2691                 err = ixgbe_check_supported_loopback_mode(dev);
2692                 if (err < 0) {
2693                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2694                         goto error;
2695                 } else {
2696                         goto skip_link_setup;
2697                 }
2698         }
2699
2700         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2701                 err = hw->mac.ops.setup_sfp(hw);
2702                 if (err)
2703                         goto error;
2704         }
2705
2706         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2707                 /* Turn on the copper */
2708                 ixgbe_set_phy_power(hw, true);
2709         } else {
2710                 /* Turn on the laser */
2711                 ixgbe_enable_tx_laser(hw);
2712         }
2713
2714         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2715         if (err)
2716                 goto error;
2717         dev->data->dev_link.link_status = link_up;
2718
2719         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2720         if (err)
2721                 goto error;
2722
2723         switch (hw->mac.type) {
2724         case ixgbe_mac_X550:
2725         case ixgbe_mac_X550EM_x:
2726         case ixgbe_mac_X550EM_a:
2727                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2728                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2729                         ETH_LINK_SPEED_10G;
2730                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2731                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2732                         allowed_speeds = ETH_LINK_SPEED_10M |
2733                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2734                 break;
2735         default:
2736                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2737                         ETH_LINK_SPEED_10G;
2738         }
2739
2740         link_speeds = &dev->data->dev_conf.link_speeds;
2741
2742         /* Ignore autoneg flag bit and check the validity of
2743          * link_speed
2744          */
2745         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2746                 PMD_INIT_LOG(ERR, "Invalid link setting");
2747                 goto error;
2748         }
2749
2750         speed = 0x0;
2751         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2752                 switch (hw->mac.type) {
2753                 case ixgbe_mac_82598EB:
2754                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2755                         break;
2756                 case ixgbe_mac_82599EB:
2757                 case ixgbe_mac_X540:
2758                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2759                         break;
2760                 case ixgbe_mac_X550:
2761                 case ixgbe_mac_X550EM_x:
2762                 case ixgbe_mac_X550EM_a:
2763                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2764                         break;
2765                 default:
2766                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2767                 }
2768         } else {
2769                 if (*link_speeds & ETH_LINK_SPEED_10G)
2770                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2771                 if (*link_speeds & ETH_LINK_SPEED_5G)
2772                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2773                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2774                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2775                 if (*link_speeds & ETH_LINK_SPEED_1G)
2776                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2777                 if (*link_speeds & ETH_LINK_SPEED_100M)
2778                         speed |= IXGBE_LINK_SPEED_100_FULL;
2779                 if (*link_speeds & ETH_LINK_SPEED_10M)
2780                         speed |= IXGBE_LINK_SPEED_10_FULL;
2781         }
2782
2783         err = ixgbe_setup_link(hw, speed, link_up);
2784         if (err)
2785                 goto error;
2786
2787 skip_link_setup:
2788
2789         if (rte_intr_allow_others(intr_handle)) {
2790                 /* check if lsc interrupt is enabled */
2791                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2792                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2793                 else
2794                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2795                 ixgbe_dev_macsec_interrupt_setup(dev);
2796         } else {
2797                 rte_intr_callback_unregister(intr_handle,
2798                                              ixgbe_dev_interrupt_handler, dev);
2799                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2800                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2801                                      " no intr multiplex");
2802         }
2803
2804         /* check if rxq interrupt is enabled */
2805         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2806             rte_intr_dp_is_en(intr_handle))
2807                 ixgbe_dev_rxq_interrupt_setup(dev);
2808
2809         /* enable uio/vfio intr/eventfd mapping */
2810         rte_intr_enable(intr_handle);
2811
2812         /* resume enabled intr since hw reset */
2813         ixgbe_enable_intr(dev);
2814         ixgbe_l2_tunnel_conf(dev);
2815         ixgbe_filter_restore(dev);
2816
2817         if (tm_conf->root && !tm_conf->committed)
2818                 PMD_DRV_LOG(WARNING,
2819                             "please call hierarchy_commit() "
2820                             "before starting the port");
2821
2822         /* wait for the controller to acquire link */
2823         err = ixgbe_wait_for_link_up(hw);
2824         if (err)
2825                 goto error;
2826
2827         /*
2828          * Update link status right before return, because it may
2829          * start link configuration process in a separate thread.
2830          */
2831         ixgbe_dev_link_update(dev, 0);
2832
2833         /* setup the macsec setting register */
2834         if (macsec_setting->offload_en)
2835                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2836
2837         return 0;
2838
2839 error:
2840         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2841         ixgbe_dev_clear_queues(dev);
2842         return -EIO;
2843 }
2844
2845 /*
2846  * Stop device: disable rx and tx functions to allow for reconfiguring.
2847  */
2848 static int
2849 ixgbe_dev_stop(struct rte_eth_dev *dev)
2850 {
2851         struct rte_eth_link link;
2852         struct ixgbe_adapter *adapter = dev->data->dev_private;
2853         struct ixgbe_hw *hw =
2854                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2855         struct ixgbe_vf_info *vfinfo =
2856                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2858         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2859         int vf;
2860         struct ixgbe_tm_conf *tm_conf =
2861                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2862
2863         if (hw->adapter_stopped)
2864                 return 0;
2865
2866         PMD_INIT_FUNC_TRACE();
2867
2868         ixgbe_dev_wait_setup_link_complete(dev, 0);
2869
2870         /* disable interrupts */
2871         ixgbe_disable_intr(hw);
2872
2873         /* reset the NIC */
2874         ixgbe_pf_reset_hw(hw);
2875         hw->adapter_stopped = 0;
2876
2877         /* stop adapter */
2878         ixgbe_stop_adapter(hw);
2879
2880         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2881                 vfinfo[vf].clear_to_send = false;
2882
2883         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2884                 /* Turn off the copper */
2885                 ixgbe_set_phy_power(hw, false);
2886         } else {
2887                 /* Turn off the laser */
2888                 ixgbe_disable_tx_laser(hw);
2889         }
2890
2891         ixgbe_dev_clear_queues(dev);
2892
2893         /* Clear stored conf */
2894         dev->data->scattered_rx = 0;
2895         dev->data->lro = 0;
2896
2897         /* Clear recorded link status */
2898         memset(&link, 0, sizeof(link));
2899         rte_eth_linkstatus_set(dev, &link);
2900
2901         if (!rte_intr_allow_others(intr_handle))
2902                 /* resume to the default handler */
2903                 rte_intr_callback_register(intr_handle,
2904                                            ixgbe_dev_interrupt_handler,
2905                                            (void *)dev);
2906
2907         /* Clean datapath event and queue/vec mapping */
2908         rte_intr_efd_disable(intr_handle);
2909         if (intr_handle->intr_vec != NULL) {
2910                 rte_free(intr_handle->intr_vec);
2911                 intr_handle->intr_vec = NULL;
2912         }
2913
2914         /* reset hierarchy commit */
2915         tm_conf->committed = false;
2916
2917         adapter->rss_reta_updated = 0;
2918
2919         hw->adapter_stopped = true;
2920         dev->data->dev_started = 0;
2921
2922         return 0;
2923 }
2924
2925 /*
2926  * Set device link up: enable tx.
2927  */
2928 static int
2929 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2930 {
2931         struct ixgbe_hw *hw =
2932                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2933         if (hw->mac.type == ixgbe_mac_82599EB) {
2934 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2935                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2936                         /* Not suported in bypass mode */
2937                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2938                                      "by device id 0x%x", hw->device_id);
2939                         return -ENOTSUP;
2940                 }
2941 #endif
2942         }
2943
2944         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2945                 /* Turn on the copper */
2946                 ixgbe_set_phy_power(hw, true);
2947         } else {
2948                 /* Turn on the laser */
2949                 ixgbe_enable_tx_laser(hw);
2950                 ixgbe_dev_link_update(dev, 0);
2951         }
2952
2953         return 0;
2954 }
2955
2956 /*
2957  * Set device link down: disable tx.
2958  */
2959 static int
2960 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2961 {
2962         struct ixgbe_hw *hw =
2963                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         if (hw->mac.type == ixgbe_mac_82599EB) {
2965 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2966                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2967                         /* Not suported in bypass mode */
2968                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2969                                      "by device id 0x%x", hw->device_id);
2970                         return -ENOTSUP;
2971                 }
2972 #endif
2973         }
2974
2975         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2976                 /* Turn off the copper */
2977                 ixgbe_set_phy_power(hw, false);
2978         } else {
2979                 /* Turn off the laser */
2980                 ixgbe_disable_tx_laser(hw);
2981                 ixgbe_dev_link_update(dev, 0);
2982         }
2983
2984         return 0;
2985 }
2986
2987 /*
2988  * Reset and stop device.
2989  */
2990 static int
2991 ixgbe_dev_close(struct rte_eth_dev *dev)
2992 {
2993         struct ixgbe_hw *hw =
2994                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2995         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2996         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2997         int retries = 0;
2998         int ret;
2999
3000         PMD_INIT_FUNC_TRACE();
3001         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3002                 return 0;
3003
3004         ixgbe_pf_reset_hw(hw);
3005
3006         ret = ixgbe_dev_stop(dev);
3007
3008         ixgbe_dev_free_queues(dev);
3009
3010         ixgbe_disable_pcie_master(hw);
3011
3012         /* reprogram the RAR[0] in case user changed it. */
3013         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3014
3015         /* Unlock any pending hardware semaphore */
3016         ixgbe_swfw_lock_reset(hw);
3017
3018         /* disable uio intr before callback unregister */
3019         rte_intr_disable(intr_handle);
3020
3021         do {
3022                 ret = rte_intr_callback_unregister(intr_handle,
3023                                 ixgbe_dev_interrupt_handler, dev);
3024                 if (ret >= 0 || ret == -ENOENT) {
3025                         break;
3026                 } else if (ret != -EAGAIN) {
3027                         PMD_INIT_LOG(ERR,
3028                                 "intr callback unregister failed: %d",
3029                                 ret);
3030                 }
3031                 rte_delay_ms(100);
3032         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3033
3034         /* cancel the delay handler before remove dev */
3035         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3036
3037         /* uninitialize PF if max_vfs not zero */
3038         ixgbe_pf_host_uninit(dev);
3039
3040         /* remove all the fdir filters & hash */
3041         ixgbe_fdir_filter_uninit(dev);
3042
3043         /* remove all the L2 tunnel filters & hash */
3044         ixgbe_l2_tn_filter_uninit(dev);
3045
3046         /* Remove all ntuple filters of the device */
3047         ixgbe_ntuple_filter_uninit(dev);
3048
3049         /* clear all the filters list */
3050         ixgbe_filterlist_flush();
3051
3052         /* Remove all Traffic Manager configuration */
3053         ixgbe_tm_conf_uninit(dev);
3054
3055 #ifdef RTE_LIBRTE_SECURITY
3056         rte_free(dev->security_ctx);
3057 #endif
3058
3059         return ret;
3060 }
3061
3062 /*
3063  * Reset PF device.
3064  */
3065 static int
3066 ixgbe_dev_reset(struct rte_eth_dev *dev)
3067 {
3068         int ret;
3069
3070         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3071          * its VF to make them align with it. The detailed notification
3072          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3073          * To avoid unexpected behavior in VF, currently reset of PF with
3074          * SR-IOV activation is not supported. It might be supported later.
3075          */
3076         if (dev->data->sriov.active)
3077                 return -ENOTSUP;
3078
3079         ret = eth_ixgbe_dev_uninit(dev);
3080         if (ret)
3081                 return ret;
3082
3083         ret = eth_ixgbe_dev_init(dev, NULL);
3084
3085         return ret;
3086 }
3087
3088 static void
3089 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3090                            struct ixgbe_hw_stats *hw_stats,
3091                            struct ixgbe_macsec_stats *macsec_stats,
3092                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3093                            uint64_t *total_qprc, uint64_t *total_qprdc)
3094 {
3095         uint32_t bprc, lxon, lxoff, total;
3096         uint32_t delta_gprc = 0;
3097         unsigned i;
3098         /* Workaround for RX byte count not including CRC bytes when CRC
3099          * strip is enabled. CRC bytes are removed from counters when crc_strip
3100          * is disabled.
3101          */
3102         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3103                         IXGBE_HLREG0_RXCRCSTRP);
3104
3105         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3106         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3107         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3108         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3109
3110         for (i = 0; i < 8; i++) {
3111                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3112
3113                 /* global total per queue */
3114                 hw_stats->mpc[i] += mp;
3115                 /* Running comprehensive total for stats display */
3116                 *total_missed_rx += hw_stats->mpc[i];
3117                 if (hw->mac.type == ixgbe_mac_82598EB) {
3118                         hw_stats->rnbc[i] +=
3119                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3120                         hw_stats->pxonrxc[i] +=
3121                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3122                         hw_stats->pxoffrxc[i] +=
3123                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3124                 } else {
3125                         hw_stats->pxonrxc[i] +=
3126                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3127                         hw_stats->pxoffrxc[i] +=
3128                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3129                         hw_stats->pxon2offc[i] +=
3130                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3131                 }
3132                 hw_stats->pxontxc[i] +=
3133                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3134                 hw_stats->pxofftxc[i] +=
3135                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3136         }
3137         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3138                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3139                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3140                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3141
3142                 delta_gprc += delta_qprc;
3143
3144                 hw_stats->qprc[i] += delta_qprc;
3145                 hw_stats->qptc[i] += delta_qptc;
3146
3147                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3148                 hw_stats->qbrc[i] +=
3149                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3150                 if (crc_strip == 0)
3151                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3152
3153                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3154                 hw_stats->qbtc[i] +=
3155                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3156
3157                 hw_stats->qprdc[i] += delta_qprdc;
3158                 *total_qprdc += hw_stats->qprdc[i];
3159
3160                 *total_qprc += hw_stats->qprc[i];
3161                 *total_qbrc += hw_stats->qbrc[i];
3162         }
3163         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3164         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3165         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3166
3167         /*
3168          * An errata states that gprc actually counts good + missed packets:
3169          * Workaround to set gprc to summated queue packet receives
3170          */
3171         hw_stats->gprc = *total_qprc;
3172
3173         if (hw->mac.type != ixgbe_mac_82598EB) {
3174                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3175                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3176                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3177                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3178                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3179                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3180                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3181                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3182         } else {
3183                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3184                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3185                 /* 82598 only has a counter in the high register */
3186                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3187                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3188                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3189         }
3190         uint64_t old_tpr = hw_stats->tpr;
3191
3192         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3193         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3194
3195         if (crc_strip == 0)
3196                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3197
3198         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3199         hw_stats->gptc += delta_gptc;
3200         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3201         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3202
3203         /*
3204          * Workaround: mprc hardware is incorrectly counting
3205          * broadcasts, so for now we subtract those.
3206          */
3207         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3208         hw_stats->bprc += bprc;
3209         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3210         if (hw->mac.type == ixgbe_mac_82598EB)
3211                 hw_stats->mprc -= bprc;
3212
3213         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3214         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3215         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3216         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3217         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3218         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3219
3220         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3221         hw_stats->lxontxc += lxon;
3222         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3223         hw_stats->lxofftxc += lxoff;
3224         total = lxon + lxoff;
3225
3226         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3227         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3228         hw_stats->gptc -= total;
3229         hw_stats->mptc -= total;
3230         hw_stats->ptc64 -= total;
3231         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3232
3233         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3234         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3235         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3236         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3237         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3238         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3239         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3240         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3241         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3242         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3243         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3244         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3245         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3246         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3247         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3248         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3249         /* Only read FCOE on 82599 */
3250         if (hw->mac.type != ixgbe_mac_82598EB) {
3251                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3252                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3253                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3254                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3255                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3256         }
3257
3258         /* Flow Director Stats registers */
3259         if (hw->mac.type != ixgbe_mac_82598EB) {
3260                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3261                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3262                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3263                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3264                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3265                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3266                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3267                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3268                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3269                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3270         }
3271         /* MACsec Stats registers */
3272         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3273         macsec_stats->out_pkts_encrypted +=
3274                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3275         macsec_stats->out_pkts_protected +=
3276                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3277         macsec_stats->out_octets_encrypted +=
3278                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3279         macsec_stats->out_octets_protected +=
3280                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3281         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3282         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3283         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3284         macsec_stats->in_pkts_unknownsci +=
3285                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3286         macsec_stats->in_octets_decrypted +=
3287                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3288         macsec_stats->in_octets_validated +=
3289                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3290         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3291         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3292         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3293         for (i = 0; i < 2; i++) {
3294                 macsec_stats->in_pkts_ok +=
3295                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3296                 macsec_stats->in_pkts_invalid +=
3297                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3298                 macsec_stats->in_pkts_notvalid +=
3299                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3300         }
3301         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3302         macsec_stats->in_pkts_notusingsa +=
3303                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3304 }
3305
3306 /*
3307  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3308  */
3309 static int
3310 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3311 {
3312         struct ixgbe_hw *hw =
3313                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3314         struct ixgbe_hw_stats *hw_stats =
3315                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3316         struct ixgbe_macsec_stats *macsec_stats =
3317                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3318                                 dev->data->dev_private);
3319         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3320         unsigned i;
3321
3322         total_missed_rx = 0;
3323         total_qbrc = 0;
3324         total_qprc = 0;
3325         total_qprdc = 0;
3326
3327         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3328                         &total_qbrc, &total_qprc, &total_qprdc);
3329
3330         if (stats == NULL)
3331                 return -EINVAL;
3332
3333         /* Fill out the rte_eth_stats statistics structure */
3334         stats->ipackets = total_qprc;
3335         stats->ibytes = total_qbrc;
3336         stats->opackets = hw_stats->gptc;
3337         stats->obytes = hw_stats->gotc;
3338
3339         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3340                 stats->q_ipackets[i] = hw_stats->qprc[i];
3341                 stats->q_opackets[i] = hw_stats->qptc[i];
3342                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3343                 stats->q_obytes[i] = hw_stats->qbtc[i];
3344                 stats->q_errors[i] = hw_stats->qprdc[i];
3345         }
3346
3347         /* Rx Errors */
3348         stats->imissed  = total_missed_rx;
3349         stats->ierrors  = hw_stats->crcerrs +
3350                           hw_stats->mspdc +
3351                           hw_stats->rlec +
3352                           hw_stats->ruc +
3353                           hw_stats->roc +
3354                           hw_stats->illerrc +
3355                           hw_stats->errbc +
3356                           hw_stats->rfc +
3357                           hw_stats->fccrc +
3358                           hw_stats->fclast;
3359
3360         /* Tx Errors */
3361         stats->oerrors  = 0;
3362         return 0;
3363 }
3364
3365 static int
3366 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3367 {
3368         struct ixgbe_hw_stats *stats =
3369                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3370
3371         /* HW registers are cleared on read */
3372         ixgbe_dev_stats_get(dev, NULL);
3373
3374         /* Reset software totals */
3375         memset(stats, 0, sizeof(*stats));
3376
3377         return 0;
3378 }
3379
3380 /* This function calculates the number of xstats based on the current config */
3381 static unsigned
3382 ixgbe_xstats_calc_num(void) {
3383         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3384                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3385                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3386 }
3387
3388 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3389         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3390 {
3391         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3392         unsigned stat, i, count;
3393
3394         if (xstats_names != NULL) {
3395                 count = 0;
3396
3397                 /* Note: limit >= cnt_stats checked upstream
3398                  * in rte_eth_xstats_names()
3399                  */
3400
3401                 /* Extended stats from ixgbe_hw_stats */
3402                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3403                         strlcpy(xstats_names[count].name,
3404                                 rte_ixgbe_stats_strings[i].name,
3405                                 sizeof(xstats_names[count].name));
3406                         count++;
3407                 }
3408
3409                 /* MACsec Stats */
3410                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3411                         strlcpy(xstats_names[count].name,
3412                                 rte_ixgbe_macsec_strings[i].name,
3413                                 sizeof(xstats_names[count].name));
3414                         count++;
3415                 }
3416
3417                 /* RX Priority Stats */
3418                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3419                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3420                                 snprintf(xstats_names[count].name,
3421                                         sizeof(xstats_names[count].name),
3422                                         "rx_priority%u_%s", i,
3423                                         rte_ixgbe_rxq_strings[stat].name);
3424                                 count++;
3425                         }
3426                 }
3427
3428                 /* TX Priority Stats */
3429                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3430                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3431                                 snprintf(xstats_names[count].name,
3432                                         sizeof(xstats_names[count].name),
3433                                         "tx_priority%u_%s", i,
3434                                         rte_ixgbe_txq_strings[stat].name);
3435                                 count++;
3436                         }
3437                 }
3438         }
3439         return cnt_stats;
3440 }
3441
3442 static int ixgbe_dev_xstats_get_names_by_id(
3443         struct rte_eth_dev *dev,
3444         struct rte_eth_xstat_name *xstats_names,
3445         const uint64_t *ids,
3446         unsigned int limit)
3447 {
3448         if (!ids) {
3449                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3450                 unsigned int stat, i, count;
3451
3452                 if (xstats_names != NULL) {
3453                         count = 0;
3454
3455                         /* Note: limit >= cnt_stats checked upstream
3456                          * in rte_eth_xstats_names()
3457                          */
3458
3459                         /* Extended stats from ixgbe_hw_stats */
3460                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3461                                 strlcpy(xstats_names[count].name,
3462                                         rte_ixgbe_stats_strings[i].name,
3463                                         sizeof(xstats_names[count].name));
3464                                 count++;
3465                         }
3466
3467                         /* MACsec Stats */
3468                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3469                                 strlcpy(xstats_names[count].name,
3470                                         rte_ixgbe_macsec_strings[i].name,
3471                                         sizeof(xstats_names[count].name));
3472                                 count++;
3473                         }
3474
3475                         /* RX Priority Stats */
3476                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3477                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3478                                         snprintf(xstats_names[count].name,
3479                                             sizeof(xstats_names[count].name),
3480                                             "rx_priority%u_%s", i,
3481                                             rte_ixgbe_rxq_strings[stat].name);
3482                                         count++;
3483                                 }
3484                         }
3485
3486                         /* TX Priority Stats */
3487                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3488                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3489                                         snprintf(xstats_names[count].name,
3490                                             sizeof(xstats_names[count].name),
3491                                             "tx_priority%u_%s", i,
3492                                             rte_ixgbe_txq_strings[stat].name);
3493                                         count++;
3494                                 }
3495                         }
3496                 }
3497                 return cnt_stats;
3498         }
3499
3500         uint16_t i;
3501         uint16_t size = ixgbe_xstats_calc_num();
3502         struct rte_eth_xstat_name xstats_names_copy[size];
3503
3504         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3505                         size);
3506
3507         for (i = 0; i < limit; i++) {
3508                 if (ids[i] >= size) {
3509                         PMD_INIT_LOG(ERR, "id value isn't valid");
3510                         return -1;
3511                 }
3512                 strcpy(xstats_names[i].name,
3513                                 xstats_names_copy[ids[i]].name);
3514         }
3515         return limit;
3516 }
3517
3518 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3519         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3520 {
3521         unsigned i;
3522
3523         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3524                 return -ENOMEM;
3525
3526         if (xstats_names != NULL)
3527                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3528                         strlcpy(xstats_names[i].name,
3529                                 rte_ixgbevf_stats_strings[i].name,
3530                                 sizeof(xstats_names[i].name));
3531         return IXGBEVF_NB_XSTATS;
3532 }
3533
3534 static int
3535 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3536                                          unsigned n)
3537 {
3538         struct ixgbe_hw *hw =
3539                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3540         struct ixgbe_hw_stats *hw_stats =
3541                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3542         struct ixgbe_macsec_stats *macsec_stats =
3543                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3544                                 dev->data->dev_private);
3545         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3546         unsigned i, stat, count = 0;
3547
3548         count = ixgbe_xstats_calc_num();
3549
3550         if (n < count)
3551                 return count;
3552
3553         total_missed_rx = 0;
3554         total_qbrc = 0;
3555         total_qprc = 0;
3556         total_qprdc = 0;
3557
3558         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3559                         &total_qbrc, &total_qprc, &total_qprdc);
3560
3561         /* If this is a reset xstats is NULL, and we have cleared the
3562          * registers by reading them.
3563          */
3564         if (!xstats)
3565                 return 0;
3566
3567         /* Extended stats from ixgbe_hw_stats */
3568         count = 0;
3569         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3570                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3571                                 rte_ixgbe_stats_strings[i].offset);
3572                 xstats[count].id = count;
3573                 count++;
3574         }
3575
3576         /* MACsec Stats */
3577         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3578                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3579                                 rte_ixgbe_macsec_strings[i].offset);
3580                 xstats[count].id = count;
3581                 count++;
3582         }
3583
3584         /* RX Priority Stats */
3585         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3586                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3587                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3588                                         rte_ixgbe_rxq_strings[stat].offset +
3589                                         (sizeof(uint64_t) * i));
3590                         xstats[count].id = count;
3591                         count++;
3592                 }
3593         }
3594
3595         /* TX Priority Stats */
3596         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3597                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3598                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3599                                         rte_ixgbe_txq_strings[stat].offset +
3600                                         (sizeof(uint64_t) * i));
3601                         xstats[count].id = count;
3602                         count++;
3603                 }
3604         }
3605         return count;
3606 }
3607
3608 static int
3609 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3610                 uint64_t *values, unsigned int n)
3611 {
3612         if (!ids) {
3613                 struct ixgbe_hw *hw =
3614                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3615                 struct ixgbe_hw_stats *hw_stats =
3616                                 IXGBE_DEV_PRIVATE_TO_STATS(
3617                                                 dev->data->dev_private);
3618                 struct ixgbe_macsec_stats *macsec_stats =
3619                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3620                                         dev->data->dev_private);
3621                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3622                 unsigned int i, stat, count = 0;
3623
3624                 count = ixgbe_xstats_calc_num();
3625
3626                 if (!ids && n < count)
3627                         return count;
3628
3629                 total_missed_rx = 0;
3630                 total_qbrc = 0;
3631                 total_qprc = 0;
3632                 total_qprdc = 0;
3633
3634                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3635                                 &total_missed_rx, &total_qbrc, &total_qprc,
3636                                 &total_qprdc);
3637
3638                 /* If this is a reset xstats is NULL, and we have cleared the
3639                  * registers by reading them.
3640                  */
3641                 if (!ids && !values)
3642                         return 0;
3643
3644                 /* Extended stats from ixgbe_hw_stats */
3645                 count = 0;
3646                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3647                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3648                                         rte_ixgbe_stats_strings[i].offset);
3649                         count++;
3650                 }
3651
3652                 /* MACsec Stats */
3653                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3654                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3655                                         rte_ixgbe_macsec_strings[i].offset);
3656                         count++;
3657                 }
3658
3659                 /* RX Priority Stats */
3660                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3661                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3662                                 values[count] =
3663                                         *(uint64_t *)(((char *)hw_stats) +
3664                                         rte_ixgbe_rxq_strings[stat].offset +
3665                                         (sizeof(uint64_t) * i));
3666                                 count++;
3667                         }
3668                 }
3669
3670                 /* TX Priority Stats */
3671                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3672                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3673                                 values[count] =
3674                                         *(uint64_t *)(((char *)hw_stats) +
3675                                         rte_ixgbe_txq_strings[stat].offset +
3676                                         (sizeof(uint64_t) * i));
3677                                 count++;
3678                         }
3679                 }
3680                 return count;
3681         }
3682
3683         uint16_t i;
3684         uint16_t size = ixgbe_xstats_calc_num();
3685         uint64_t values_copy[size];
3686
3687         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3688
3689         for (i = 0; i < n; i++) {
3690                 if (ids[i] >= size) {
3691                         PMD_INIT_LOG(ERR, "id value isn't valid");
3692                         return -1;
3693                 }
3694                 values[i] = values_copy[ids[i]];
3695         }
3696         return n;
3697 }
3698
3699 static int
3700 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3701 {
3702         struct ixgbe_hw_stats *stats =
3703                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3704         struct ixgbe_macsec_stats *macsec_stats =
3705                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3706                                 dev->data->dev_private);
3707
3708         unsigned count = ixgbe_xstats_calc_num();
3709
3710         /* HW registers are cleared on read */
3711         ixgbe_dev_xstats_get(dev, NULL, count);
3712
3713         /* Reset software totals */
3714         memset(stats, 0, sizeof(*stats));
3715         memset(macsec_stats, 0, sizeof(*macsec_stats));
3716
3717         return 0;
3718 }
3719
3720 static void
3721 ixgbevf_update_stats(struct rte_eth_dev *dev)
3722 {
3723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3724         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3725                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3726
3727         /* Good Rx packet, include VF loopback */
3728         UPDATE_VF_STAT(IXGBE_VFGPRC,
3729             hw_stats->last_vfgprc, hw_stats->vfgprc);
3730
3731         /* Good Rx octets, include VF loopback */
3732         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3733             hw_stats->last_vfgorc, hw_stats->vfgorc);
3734
3735         /* Good Tx packet, include VF loopback */
3736         UPDATE_VF_STAT(IXGBE_VFGPTC,
3737             hw_stats->last_vfgptc, hw_stats->vfgptc);
3738
3739         /* Good Tx octets, include VF loopback */
3740         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3741             hw_stats->last_vfgotc, hw_stats->vfgotc);
3742
3743         /* Rx Multicst Packet */
3744         UPDATE_VF_STAT(IXGBE_VFMPRC,
3745             hw_stats->last_vfmprc, hw_stats->vfmprc);
3746 }
3747
3748 static int
3749 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3750                        unsigned n)
3751 {
3752         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3753                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3754         unsigned i;
3755
3756         if (n < IXGBEVF_NB_XSTATS)
3757                 return IXGBEVF_NB_XSTATS;
3758
3759         ixgbevf_update_stats(dev);
3760
3761         if (!xstats)
3762                 return 0;
3763
3764         /* Extended stats */
3765         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3766                 xstats[i].id = i;
3767                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3768                         rte_ixgbevf_stats_strings[i].offset);
3769         }
3770
3771         return IXGBEVF_NB_XSTATS;
3772 }
3773
3774 static int
3775 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3776 {
3777         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3778                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3779
3780         ixgbevf_update_stats(dev);
3781
3782         if (stats == NULL)
3783                 return -EINVAL;
3784
3785         stats->ipackets = hw_stats->vfgprc;
3786         stats->ibytes = hw_stats->vfgorc;
3787         stats->opackets = hw_stats->vfgptc;
3788         stats->obytes = hw_stats->vfgotc;
3789         return 0;
3790 }
3791
3792 static int
3793 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3794 {
3795         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3796                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3797
3798         /* Sync HW register to the last stats */
3799         ixgbevf_dev_stats_get(dev, NULL);
3800
3801         /* reset HW current stats*/
3802         hw_stats->vfgprc = 0;
3803         hw_stats->vfgorc = 0;
3804         hw_stats->vfgptc = 0;
3805         hw_stats->vfgotc = 0;
3806
3807         return 0;
3808 }
3809
3810 static int
3811 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3812 {
3813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3814         u16 eeprom_verh, eeprom_verl;
3815         u32 etrack_id;
3816         int ret;
3817
3818         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3819         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3820
3821         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3822         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3823
3824         ret += 1; /* add the size of '\0' */
3825         if (fw_size < (u32)ret)
3826                 return ret;
3827         else
3828                 return 0;
3829 }
3830
3831 static int
3832 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3833 {
3834         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3836         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3837
3838         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3839         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3840         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3841                 /*
3842                  * When DCB/VT is off, maximum number of queues changes,
3843                  * except for 82598EB, which remains constant.
3844                  */
3845                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3846                                 hw->mac.type != ixgbe_mac_82598EB)
3847                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3848         }
3849         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3850         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3851         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3852         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3853         dev_info->max_vfs = pci_dev->max_vfs;
3854         if (hw->mac.type == ixgbe_mac_82598EB)
3855                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3856         else
3857                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3858         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3859         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3860         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3861         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3862         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3863                                      dev_info->rx_queue_offload_capa);
3864         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3865         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3866
3867         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3868                 .rx_thresh = {
3869                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3870                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3871                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3872                 },
3873                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3874                 .rx_drop_en = 0,
3875                 .offloads = 0,
3876         };
3877
3878         dev_info->default_txconf = (struct rte_eth_txconf) {
3879                 .tx_thresh = {
3880                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3881                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3882                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3883                 },
3884                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3885                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3886                 .offloads = 0,
3887         };
3888
3889         dev_info->rx_desc_lim = rx_desc_lim;
3890         dev_info->tx_desc_lim = tx_desc_lim;
3891
3892         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3893         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3894         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3895
3896         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3897         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3898                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3899                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3900                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3901
3902         if (hw->mac.type == ixgbe_mac_X540 ||
3903             hw->mac.type == ixgbe_mac_X540_vf ||
3904             hw->mac.type == ixgbe_mac_X550 ||
3905             hw->mac.type == ixgbe_mac_X550_vf) {
3906                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3907         }
3908         if (hw->mac.type == ixgbe_mac_X550) {
3909                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3910                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3911         }
3912
3913         /* Driver-preferred Rx/Tx parameters */
3914         dev_info->default_rxportconf.burst_size = 32;
3915         dev_info->default_txportconf.burst_size = 32;
3916         dev_info->default_rxportconf.nb_queues = 1;
3917         dev_info->default_txportconf.nb_queues = 1;
3918         dev_info->default_rxportconf.ring_size = 256;
3919         dev_info->default_txportconf.ring_size = 256;
3920
3921         return 0;
3922 }
3923
3924 static const uint32_t *
3925 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3926 {
3927         static const uint32_t ptypes[] = {
3928                 /* For non-vec functions,
3929                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3930                  * for vec functions,
3931                  * refers to _recv_raw_pkts_vec().
3932                  */
3933                 RTE_PTYPE_L2_ETHER,
3934                 RTE_PTYPE_L3_IPV4,
3935                 RTE_PTYPE_L3_IPV4_EXT,
3936                 RTE_PTYPE_L3_IPV6,
3937                 RTE_PTYPE_L3_IPV6_EXT,
3938                 RTE_PTYPE_L4_SCTP,
3939                 RTE_PTYPE_L4_TCP,
3940                 RTE_PTYPE_L4_UDP,
3941                 RTE_PTYPE_TUNNEL_IP,
3942                 RTE_PTYPE_INNER_L3_IPV6,
3943                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3944                 RTE_PTYPE_INNER_L4_TCP,
3945                 RTE_PTYPE_INNER_L4_UDP,
3946                 RTE_PTYPE_UNKNOWN
3947         };
3948
3949         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3950             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3951             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3952             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3953                 return ptypes;
3954
3955 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3956         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3957             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3958                 return ptypes;
3959 #endif
3960         return NULL;
3961 }
3962
3963 static int
3964 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3965                      struct rte_eth_dev_info *dev_info)
3966 {
3967         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3968         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3969
3970         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3971         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3972         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3973         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3974         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3975         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3976         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3977         dev_info->max_vfs = pci_dev->max_vfs;
3978         if (hw->mac.type == ixgbe_mac_82598EB)
3979                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3980         else
3981                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3982         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3983         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3984                                      dev_info->rx_queue_offload_capa);
3985         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3986         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3987         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3988         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3989         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3990
3991         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3992                 .rx_thresh = {
3993                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3994                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3995                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3996                 },
3997                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3998                 .rx_drop_en = 0,
3999                 .offloads = 0,
4000         };
4001
4002         dev_info->default_txconf = (struct rte_eth_txconf) {
4003                 .tx_thresh = {
4004                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4005                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4006                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4007                 },
4008                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4009                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4010                 .offloads = 0,
4011         };
4012
4013         dev_info->rx_desc_lim = rx_desc_lim;
4014         dev_info->tx_desc_lim = tx_desc_lim;
4015
4016         return 0;
4017 }
4018
4019 static int
4020 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4021                    bool *link_up, int wait_to_complete)
4022 {
4023         struct ixgbe_adapter *adapter = container_of(hw,
4024                                                      struct ixgbe_adapter, hw);
4025         struct ixgbe_mbx_info *mbx = &hw->mbx;
4026         struct ixgbe_mac_info *mac = &hw->mac;
4027         uint32_t links_reg, in_msg;
4028         int ret_val = 0;
4029
4030         /* If we were hit with a reset drop the link */
4031         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4032                 mac->get_link_status = true;
4033
4034         if (!mac->get_link_status)
4035                 goto out;
4036
4037         /* if link status is down no point in checking to see if pf is up */
4038         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4039         if (!(links_reg & IXGBE_LINKS_UP))
4040                 goto out;
4041
4042         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4043          * before the link status is correct
4044          */
4045         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4046                 int i;
4047
4048                 for (i = 0; i < 5; i++) {
4049                         rte_delay_us(100);
4050                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4051
4052                         if (!(links_reg & IXGBE_LINKS_UP))
4053                                 goto out;
4054                 }
4055         }
4056
4057         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4058         case IXGBE_LINKS_SPEED_10G_82599:
4059                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4060                 if (hw->mac.type >= ixgbe_mac_X550) {
4061                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4062                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4063                 }
4064                 break;
4065         case IXGBE_LINKS_SPEED_1G_82599:
4066                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4067                 break;
4068         case IXGBE_LINKS_SPEED_100_82599:
4069                 *speed = IXGBE_LINK_SPEED_100_FULL;
4070                 if (hw->mac.type == ixgbe_mac_X550) {
4071                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4072                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4073                 }
4074                 break;
4075         case IXGBE_LINKS_SPEED_10_X550EM_A:
4076                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4077                 /* Since Reserved in older MAC's */
4078                 if (hw->mac.type >= ixgbe_mac_X550)
4079                         *speed = IXGBE_LINK_SPEED_10_FULL;
4080                 break;
4081         default:
4082                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4083         }
4084
4085         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4086                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4087                         mac->get_link_status = true;
4088                 else
4089                         mac->get_link_status = false;
4090
4091                 goto out;
4092         }
4093
4094         /* if the read failed it could just be a mailbox collision, best wait
4095          * until we are called again and don't report an error
4096          */
4097         if (mbx->ops.read(hw, &in_msg, 1, 0))
4098                 goto out;
4099
4100         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4101                 /* msg is not CTS and is NACK we must have lost CTS status */
4102                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4103                         mac->get_link_status = false;
4104                 goto out;
4105         }
4106
4107         /* the pf is talking, if we timed out in the past we reinit */
4108         if (!mbx->timeout) {
4109                 ret_val = -1;
4110                 goto out;
4111         }
4112
4113         /* if we passed all the tests above then the link is up and we no
4114          * longer need to check for link
4115          */
4116         mac->get_link_status = false;
4117
4118 out:
4119         *link_up = !mac->get_link_status;
4120         return ret_val;
4121 }
4122
4123 /*
4124  * If @timeout_ms was 0, it means that it will not return until link complete.
4125  * It returns 1 on complete, return 0 on timeout.
4126  */
4127 static int
4128 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4129 {
4130 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4131         struct ixgbe_adapter *ad = dev->data->dev_private;
4132         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4133
4134         while (rte_atomic32_read(&ad->link_thread_running)) {
4135                 msec_delay(1);
4136                 timeout--;
4137
4138                 if (timeout_ms) {
4139                         if (!timeout)
4140                                 return 0;
4141                 } else if (!timeout) {
4142                         /* It will not return until link complete */
4143                         timeout = WARNING_TIMEOUT;
4144                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4145                 }
4146         }
4147
4148         return 1;
4149 }
4150
4151 static void *
4152 ixgbe_dev_setup_link_thread_handler(void *param)
4153 {
4154         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4155         struct ixgbe_adapter *ad = dev->data->dev_private;
4156         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4157         struct ixgbe_interrupt *intr =
4158                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4159         u32 speed;
4160         bool autoneg = false;
4161
4162         pthread_detach(pthread_self());
4163         speed = hw->phy.autoneg_advertised;
4164         if (!speed)
4165                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4166
4167         ixgbe_setup_link(hw, speed, true);
4168
4169         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4170         rte_atomic32_clear(&ad->link_thread_running);
4171         return NULL;
4172 }
4173
4174 /*
4175  * In freebsd environment, nic_uio drivers do not support interrupts,
4176  * rte_intr_callback_register() will fail to register interrupts.
4177  * We can not make link status to change from down to up by interrupt
4178  * callback. So we need to wait for the controller to acquire link
4179  * when ports start.
4180  * It returns 0 on link up.
4181  */
4182 static int
4183 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4184 {
4185 #ifdef RTE_EXEC_ENV_FREEBSD
4186         int err, i;
4187         bool link_up = false;
4188         uint32_t speed = 0;
4189         const int nb_iter = 25;
4190
4191         for (i = 0; i < nb_iter; i++) {
4192                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4193                 if (err)
4194                         return err;
4195                 if (link_up)
4196                         return 0;
4197                 msec_delay(200);
4198         }
4199
4200         return 0;
4201 #else
4202         RTE_SET_USED(hw);
4203         return 0;
4204 #endif
4205 }
4206
4207 /* return 0 means link status changed, -1 means not changed */
4208 int
4209 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4210                             int wait_to_complete, int vf)
4211 {
4212         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213         struct ixgbe_adapter *ad = dev->data->dev_private;
4214         struct rte_eth_link link;
4215         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4216         struct ixgbe_interrupt *intr =
4217                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4218         bool link_up;
4219         int diag;
4220         int wait = 1;
4221         u32 esdp_reg;
4222
4223         memset(&link, 0, sizeof(link));
4224         link.link_status = ETH_LINK_DOWN;
4225         link.link_speed = ETH_SPEED_NUM_NONE;
4226         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4227         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4228                         ETH_LINK_SPEED_FIXED);
4229
4230         hw->mac.get_link_status = true;
4231
4232         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4233                 return rte_eth_linkstatus_set(dev, &link);
4234
4235         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4236         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4237                 wait = 0;
4238
4239 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4240 #ifdef RTE_EXEC_ENV_FREEBSD
4241         wait = 1;
4242 #endif
4243
4244         if (vf)
4245                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4246         else
4247                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4248
4249         if (diag != 0) {
4250                 link.link_speed = ETH_SPEED_NUM_100M;
4251                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4252                 return rte_eth_linkstatus_set(dev, &link);
4253         }
4254
4255         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4256                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4257                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4258                         link_up = 0;
4259         }
4260
4261         if (link_up == 0) {
4262                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4263                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4264                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4265                                 /* To avoid race condition between threads, set
4266                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4267                                  * when there is no link thread running.
4268                                  */
4269                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4270                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4271                                         "ixgbe-link-handler",
4272                                         NULL,
4273                                         ixgbe_dev_setup_link_thread_handler,
4274                                         dev) < 0) {
4275                                         PMD_DRV_LOG(ERR,
4276                                                 "Create link thread failed!");
4277                                         rte_atomic32_clear(&ad->link_thread_running);
4278                                 }
4279                         } else {
4280                                 PMD_DRV_LOG(ERR,
4281                                         "Other link thread is running now!");
4282                         }
4283                 }
4284                 return rte_eth_linkstatus_set(dev, &link);
4285         }
4286
4287         link.link_status = ETH_LINK_UP;
4288         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4289
4290         switch (link_speed) {
4291         default:
4292         case IXGBE_LINK_SPEED_UNKNOWN:
4293                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4294                 break;
4295
4296         case IXGBE_LINK_SPEED_10_FULL:
4297                 link.link_speed = ETH_SPEED_NUM_10M;
4298                 break;
4299
4300         case IXGBE_LINK_SPEED_100_FULL:
4301                 link.link_speed = ETH_SPEED_NUM_100M;
4302                 break;
4303
4304         case IXGBE_LINK_SPEED_1GB_FULL:
4305                 link.link_speed = ETH_SPEED_NUM_1G;
4306                 break;
4307
4308         case IXGBE_LINK_SPEED_2_5GB_FULL:
4309                 link.link_speed = ETH_SPEED_NUM_2_5G;
4310                 break;
4311
4312         case IXGBE_LINK_SPEED_5GB_FULL:
4313                 link.link_speed = ETH_SPEED_NUM_5G;
4314                 break;
4315
4316         case IXGBE_LINK_SPEED_10GB_FULL:
4317                 link.link_speed = ETH_SPEED_NUM_10G;
4318                 break;
4319         }
4320
4321         return rte_eth_linkstatus_set(dev, &link);
4322 }
4323
4324 static int
4325 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4326 {
4327         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4328 }
4329
4330 static int
4331 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4332 {
4333         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4334 }
4335
4336 static int
4337 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4338 {
4339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4340         uint32_t fctrl;
4341
4342         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4343         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4344         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4345
4346         return 0;
4347 }
4348
4349 static int
4350 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4351 {
4352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4353         uint32_t fctrl;
4354
4355         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4356         fctrl &= (~IXGBE_FCTRL_UPE);
4357         if (dev->data->all_multicast == 1)
4358                 fctrl |= IXGBE_FCTRL_MPE;
4359         else
4360                 fctrl &= (~IXGBE_FCTRL_MPE);
4361         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4362
4363         return 0;
4364 }
4365
4366 static int
4367 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4368 {
4369         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370         uint32_t fctrl;
4371
4372         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4373         fctrl |= IXGBE_FCTRL_MPE;
4374         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4375
4376         return 0;
4377 }
4378
4379 static int
4380 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4381 {
4382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4383         uint32_t fctrl;
4384
4385         if (dev->data->promiscuous == 1)
4386                 return 0; /* must remain in all_multicast mode */
4387
4388         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4389         fctrl &= (~IXGBE_FCTRL_MPE);
4390         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4391
4392         return 0;
4393 }
4394
4395 /**
4396  * It clears the interrupt causes and enables the interrupt.
4397  * It will be called once only during nic initialized.
4398  *
4399  * @param dev
4400  *  Pointer to struct rte_eth_dev.
4401  * @param on
4402  *  Enable or Disable.
4403  *
4404  * @return
4405  *  - On success, zero.
4406  *  - On failure, a negative value.
4407  */
4408 static int
4409 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4410 {
4411         struct ixgbe_interrupt *intr =
4412                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4413
4414         ixgbe_dev_link_status_print(dev);
4415         if (on)
4416                 intr->mask |= IXGBE_EICR_LSC;
4417         else
4418                 intr->mask &= ~IXGBE_EICR_LSC;
4419
4420         return 0;
4421 }
4422
4423 /**
4424  * It clears the interrupt causes and enables the interrupt.
4425  * It will be called once only during nic initialized.
4426  *
4427  * @param dev
4428  *  Pointer to struct rte_eth_dev.
4429  *
4430  * @return
4431  *  - On success, zero.
4432  *  - On failure, a negative value.
4433  */
4434 static int
4435 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4436 {
4437         struct ixgbe_interrupt *intr =
4438                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4439
4440         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4441
4442         return 0;
4443 }
4444
4445 /**
4446  * It clears the interrupt causes and enables the interrupt.
4447  * It will be called once only during nic initialized.
4448  *
4449  * @param dev
4450  *  Pointer to struct rte_eth_dev.
4451  *
4452  * @return
4453  *  - On success, zero.
4454  *  - On failure, a negative value.
4455  */
4456 static int
4457 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4458 {
4459         struct ixgbe_interrupt *intr =
4460                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4461
4462         intr->mask |= IXGBE_EICR_LINKSEC;
4463
4464         return 0;
4465 }
4466
4467 /*
4468  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4469  *
4470  * @param dev
4471  *  Pointer to struct rte_eth_dev.
4472  *
4473  * @return
4474  *  - On success, zero.
4475  *  - On failure, a negative value.
4476  */
4477 static int
4478 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4479 {
4480         uint32_t eicr;
4481         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4482         struct ixgbe_interrupt *intr =
4483                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4484
4485         /* clear all cause mask */
4486         ixgbe_disable_intr(hw);
4487
4488         /* read-on-clear nic registers here */
4489         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4490         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4491
4492         intr->flags = 0;
4493
4494         /* set flag for async link update */
4495         if (eicr & IXGBE_EICR_LSC)
4496                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4497
4498         if (eicr & IXGBE_EICR_MAILBOX)
4499                 intr->flags |= IXGBE_FLAG_MAILBOX;
4500
4501         if (eicr & IXGBE_EICR_LINKSEC)
4502                 intr->flags |= IXGBE_FLAG_MACSEC;
4503
4504         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4505             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4506             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4507                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4508
4509         return 0;
4510 }
4511
4512 /**
4513  * It gets and then prints the link status.
4514  *
4515  * @param dev
4516  *  Pointer to struct rte_eth_dev.
4517  *
4518  * @return
4519  *  - On success, zero.
4520  *  - On failure, a negative value.
4521  */
4522 static void
4523 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4524 {
4525         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4526         struct rte_eth_link link;
4527
4528         rte_eth_linkstatus_get(dev, &link);
4529
4530         if (link.link_status) {
4531                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4532                                         (int)(dev->data->port_id),
4533                                         (unsigned)link.link_speed,
4534                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4535                                         "full-duplex" : "half-duplex");
4536         } else {
4537                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4538                                 (int)(dev->data->port_id));
4539         }
4540         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4541                                 pci_dev->addr.domain,
4542                                 pci_dev->addr.bus,
4543                                 pci_dev->addr.devid,
4544                                 pci_dev->addr.function);
4545 }
4546
4547 /*
4548  * It executes link_update after knowing an interrupt occurred.
4549  *
4550  * @param dev
4551  *  Pointer to struct rte_eth_dev.
4552  *
4553  * @return
4554  *  - On success, zero.
4555  *  - On failure, a negative value.
4556  */
4557 static int
4558 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4559 {
4560         struct ixgbe_interrupt *intr =
4561                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4562         int64_t timeout;
4563         struct ixgbe_hw *hw =
4564                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4565
4566         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4567
4568         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4569                 ixgbe_pf_mbx_process(dev);
4570                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4571         }
4572
4573         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4574                 ixgbe_handle_lasi(hw);
4575                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4576         }
4577
4578         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4579                 struct rte_eth_link link;
4580
4581                 /* get the link status before link update, for predicting later */
4582                 rte_eth_linkstatus_get(dev, &link);
4583
4584                 ixgbe_dev_link_update(dev, 0);
4585
4586                 /* likely to up */
4587                 if (!link.link_status)
4588                         /* handle it 1 sec later, wait it being stable */
4589                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4590                 /* likely to down */
4591                 else
4592                         /* handle it 4 sec later, wait it being stable */
4593                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4594
4595                 ixgbe_dev_link_status_print(dev);
4596                 if (rte_eal_alarm_set(timeout * 1000,
4597                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4598                         PMD_DRV_LOG(ERR, "Error setting alarm");
4599                 else {
4600                         /* remember original mask */
4601                         intr->mask_original = intr->mask;
4602                         /* only disable lsc interrupt */
4603                         intr->mask &= ~IXGBE_EIMS_LSC;
4604                 }
4605         }
4606
4607         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4608         ixgbe_enable_intr(dev);
4609
4610         return 0;
4611 }
4612
4613 /**
4614  * Interrupt handler which shall be registered for alarm callback for delayed
4615  * handling specific interrupt to wait for the stable nic state. As the
4616  * NIC interrupt state is not stable for ixgbe after link is just down,
4617  * it needs to wait 4 seconds to get the stable status.
4618  *
4619  * @param handle
4620  *  Pointer to interrupt handle.
4621  * @param param
4622  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4623  *
4624  * @return
4625  *  void
4626  */
4627 static void
4628 ixgbe_dev_interrupt_delayed_handler(void *param)
4629 {
4630         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4631         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4632         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4633         struct ixgbe_interrupt *intr =
4634                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4635         struct ixgbe_hw *hw =
4636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4637         uint32_t eicr;
4638
4639         ixgbe_disable_intr(hw);
4640
4641         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4642         if (eicr & IXGBE_EICR_MAILBOX)
4643                 ixgbe_pf_mbx_process(dev);
4644
4645         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4646                 ixgbe_handle_lasi(hw);
4647                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4648         }
4649
4650         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4651                 ixgbe_dev_link_update(dev, 0);
4652                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4653                 ixgbe_dev_link_status_print(dev);
4654                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4655         }
4656
4657         if (intr->flags & IXGBE_FLAG_MACSEC) {
4658                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4659                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4660         }
4661
4662         /* restore original mask */
4663         intr->mask = intr->mask_original;
4664         intr->mask_original = 0;
4665
4666         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4667         ixgbe_enable_intr(dev);
4668         rte_intr_ack(intr_handle);
4669 }
4670
4671 /**
4672  * Interrupt handler triggered by NIC  for handling
4673  * specific interrupt.
4674  *
4675  * @param handle
4676  *  Pointer to interrupt handle.
4677  * @param param
4678  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4679  *
4680  * @return
4681  *  void
4682  */
4683 static void
4684 ixgbe_dev_interrupt_handler(void *param)
4685 {
4686         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4687
4688         ixgbe_dev_interrupt_get_status(dev);
4689         ixgbe_dev_interrupt_action(dev);
4690 }
4691
4692 static int
4693 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4694 {
4695         struct ixgbe_hw *hw;
4696
4697         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4699 }
4700
4701 static int
4702 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4703 {
4704         struct ixgbe_hw *hw;
4705
4706         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4707         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4708 }
4709
4710 static int
4711 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4712 {
4713         struct ixgbe_hw *hw;
4714         uint32_t mflcn_reg;
4715         uint32_t fccfg_reg;
4716         int rx_pause;
4717         int tx_pause;
4718
4719         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4720
4721         fc_conf->pause_time = hw->fc.pause_time;
4722         fc_conf->high_water = hw->fc.high_water[0];
4723         fc_conf->low_water = hw->fc.low_water[0];
4724         fc_conf->send_xon = hw->fc.send_xon;
4725         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4726
4727         /*
4728          * Return rx_pause status according to actual setting of
4729          * MFLCN register.
4730          */
4731         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4732         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4733                 fc_conf->mac_ctrl_frame_fwd = 1;
4734         else
4735                 fc_conf->mac_ctrl_frame_fwd = 0;
4736
4737         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4738                 rx_pause = 1;
4739         else
4740                 rx_pause = 0;
4741
4742         /*
4743          * Return tx_pause status according to actual setting of
4744          * FCCFG register.
4745          */
4746         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4747         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4748                 tx_pause = 1;
4749         else
4750                 tx_pause = 0;
4751
4752         if (rx_pause && tx_pause)
4753                 fc_conf->mode = RTE_FC_FULL;
4754         else if (rx_pause)
4755                 fc_conf->mode = RTE_FC_RX_PAUSE;
4756         else if (tx_pause)
4757                 fc_conf->mode = RTE_FC_TX_PAUSE;
4758         else
4759                 fc_conf->mode = RTE_FC_NONE;
4760
4761         return 0;
4762 }
4763
4764 static int
4765 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4766 {
4767         struct ixgbe_hw *hw;
4768         struct ixgbe_adapter *adapter = dev->data->dev_private;
4769         int err;
4770         uint32_t rx_buf_size;
4771         uint32_t max_high_water;
4772         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4773                 ixgbe_fc_none,
4774                 ixgbe_fc_rx_pause,
4775                 ixgbe_fc_tx_pause,
4776                 ixgbe_fc_full
4777         };
4778
4779         PMD_INIT_FUNC_TRACE();
4780
4781         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4782         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4783         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4784
4785         /*
4786          * At least reserve one Ethernet frame for watermark
4787          * high_water/low_water in kilo bytes for ixgbe
4788          */
4789         max_high_water = (rx_buf_size -
4790                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4791         if ((fc_conf->high_water > max_high_water) ||
4792                 (fc_conf->high_water < fc_conf->low_water)) {
4793                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4794                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4795                 return -EINVAL;
4796         }
4797
4798         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4799         hw->fc.pause_time     = fc_conf->pause_time;
4800         hw->fc.high_water[0]  = fc_conf->high_water;
4801         hw->fc.low_water[0]   = fc_conf->low_water;
4802         hw->fc.send_xon       = fc_conf->send_xon;
4803         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4804         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4805
4806         err = ixgbe_flow_ctrl_enable(dev, hw);
4807         if (err < 0) {
4808                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4809                 return -EIO;
4810         }
4811         return err;
4812 }
4813
4814 /**
4815  *  ixgbe_pfc_enable_generic - Enable flow control
4816  *  @hw: pointer to hardware structure
4817  *  @tc_num: traffic class number
4818  *  Enable flow control according to the current settings.
4819  */
4820 static int
4821 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4822 {
4823         int ret_val = 0;
4824         uint32_t mflcn_reg, fccfg_reg;
4825         uint32_t reg;
4826         uint32_t fcrtl, fcrth;
4827         uint8_t i;
4828         uint8_t nb_rx_en;
4829
4830         /* Validate the water mark configuration */
4831         if (!hw->fc.pause_time) {
4832                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4833                 goto out;
4834         }
4835
4836         /* Low water mark of zero causes XOFF floods */
4837         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4838                  /* High/Low water can not be 0 */
4839                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4840                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4841                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4842                         goto out;
4843                 }
4844
4845                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4846                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4847                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4848                         goto out;
4849                 }
4850         }
4851         /* Negotiate the fc mode to use */
4852         ixgbe_fc_autoneg(hw);
4853
4854         /* Disable any previous flow control settings */
4855         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4856         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4857
4858         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4859         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4860
4861         switch (hw->fc.current_mode) {
4862         case ixgbe_fc_none:
4863                 /*
4864                  * If the count of enabled RX Priority Flow control >1,
4865                  * and the TX pause can not be disabled
4866                  */
4867                 nb_rx_en = 0;
4868                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4869                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4870                         if (reg & IXGBE_FCRTH_FCEN)
4871                                 nb_rx_en++;
4872                 }
4873                 if (nb_rx_en > 1)
4874                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4875                 break;
4876         case ixgbe_fc_rx_pause:
4877                 /*
4878                  * Rx Flow control is enabled and Tx Flow control is
4879                  * disabled by software override. Since there really
4880                  * isn't a way to advertise that we are capable of RX
4881                  * Pause ONLY, we will advertise that we support both
4882                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4883                  * disable the adapter's ability to send PAUSE frames.
4884                  */
4885                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4886                 /*
4887                  * If the count of enabled RX Priority Flow control >1,
4888                  * and the TX pause can not be disabled
4889                  */
4890                 nb_rx_en = 0;
4891                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4892                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4893                         if (reg & IXGBE_FCRTH_FCEN)
4894                                 nb_rx_en++;
4895                 }
4896                 if (nb_rx_en > 1)
4897                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4898                 break;
4899         case ixgbe_fc_tx_pause:
4900                 /*
4901                  * Tx Flow control is enabled, and Rx Flow control is
4902                  * disabled by software override.
4903                  */
4904                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4905                 break;
4906         case ixgbe_fc_full:
4907                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4908                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4909                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4910                 break;
4911         default:
4912                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4913                 ret_val = IXGBE_ERR_CONFIG;
4914                 goto out;
4915         }
4916
4917         /* Set 802.3x based flow control settings. */
4918         mflcn_reg |= IXGBE_MFLCN_DPF;
4919         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4920         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4921
4922         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4923         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4924                 hw->fc.high_water[tc_num]) {
4925                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4926                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4927                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4928         } else {
4929                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4930                 /*
4931                  * In order to prevent Tx hangs when the internal Tx
4932                  * switch is enabled we must set the high water mark
4933                  * to the maximum FCRTH value.  This allows the Tx
4934                  * switch to function even under heavy Rx workloads.
4935                  */
4936                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4937         }
4938         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4939
4940         /* Configure pause time (2 TCs per register) */
4941         reg = hw->fc.pause_time * 0x00010001;
4942         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4943                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4944
4945         /* Configure flow control refresh threshold value */
4946         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4947
4948 out:
4949         return ret_val;
4950 }
4951
4952 static int
4953 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4954 {
4955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4956         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4957
4958         if (hw->mac.type != ixgbe_mac_82598EB) {
4959                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4960         }
4961         return ret_val;
4962 }
4963
4964 static int
4965 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4966 {
4967         int err;
4968         uint32_t rx_buf_size;
4969         uint32_t max_high_water;
4970         uint8_t tc_num;
4971         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4972         struct ixgbe_hw *hw =
4973                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4974         struct ixgbe_dcb_config *dcb_config =
4975                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4976
4977         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4978                 ixgbe_fc_none,
4979                 ixgbe_fc_rx_pause,
4980                 ixgbe_fc_tx_pause,
4981                 ixgbe_fc_full
4982         };
4983
4984         PMD_INIT_FUNC_TRACE();
4985
4986         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4987         tc_num = map[pfc_conf->priority];
4988         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4989         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4990         /*
4991          * At least reserve one Ethernet frame for watermark
4992          * high_water/low_water in kilo bytes for ixgbe
4993          */
4994         max_high_water = (rx_buf_size -
4995                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4996         if ((pfc_conf->fc.high_water > max_high_water) ||
4997             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4998                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4999                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5000                 return -EINVAL;
5001         }
5002
5003         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5004         hw->fc.pause_time = pfc_conf->fc.pause_time;
5005         hw->fc.send_xon = pfc_conf->fc.send_xon;
5006         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5007         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5008
5009         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5010
5011         /* Not negotiated is not an error case */
5012         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5013                 return 0;
5014
5015         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5016         return -EIO;
5017 }
5018
5019 static int
5020 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5021                           struct rte_eth_rss_reta_entry64 *reta_conf,
5022                           uint16_t reta_size)
5023 {
5024         uint16_t i, sp_reta_size;
5025         uint8_t j, mask;
5026         uint32_t reta, r;
5027         uint16_t idx, shift;
5028         struct ixgbe_adapter *adapter = dev->data->dev_private;
5029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5030         uint32_t reta_reg;
5031
5032         PMD_INIT_FUNC_TRACE();
5033
5034         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5035                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5036                         "NIC.");
5037                 return -ENOTSUP;
5038         }
5039
5040         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5041         if (reta_size != sp_reta_size) {
5042                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5043                         "(%d) doesn't match the number hardware can supported "
5044                         "(%d)", reta_size, sp_reta_size);
5045                 return -EINVAL;
5046         }
5047
5048         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5049                 idx = i / RTE_RETA_GROUP_SIZE;
5050                 shift = i % RTE_RETA_GROUP_SIZE;
5051                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5052                                                 IXGBE_4_BIT_MASK);
5053                 if (!mask)
5054                         continue;
5055                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5056                 if (mask == IXGBE_4_BIT_MASK)
5057                         r = 0;
5058                 else
5059                         r = IXGBE_READ_REG(hw, reta_reg);
5060                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5061                         if (mask & (0x1 << j))
5062                                 reta |= reta_conf[idx].reta[shift + j] <<
5063                                                         (CHAR_BIT * j);
5064                         else
5065                                 reta |= r & (IXGBE_8_BIT_MASK <<
5066                                                 (CHAR_BIT * j));
5067                 }
5068                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5069         }
5070         adapter->rss_reta_updated = 1;
5071
5072         return 0;
5073 }
5074
5075 static int
5076 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5077                          struct rte_eth_rss_reta_entry64 *reta_conf,
5078                          uint16_t reta_size)
5079 {
5080         uint16_t i, sp_reta_size;
5081         uint8_t j, mask;
5082         uint32_t reta;
5083         uint16_t idx, shift;
5084         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5085         uint32_t reta_reg;
5086
5087         PMD_INIT_FUNC_TRACE();
5088         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5089         if (reta_size != sp_reta_size) {
5090                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5091                         "(%d) doesn't match the number hardware can supported "
5092                         "(%d)", reta_size, sp_reta_size);
5093                 return -EINVAL;
5094         }
5095
5096         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5097                 idx = i / RTE_RETA_GROUP_SIZE;
5098                 shift = i % RTE_RETA_GROUP_SIZE;
5099                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5100                                                 IXGBE_4_BIT_MASK);
5101                 if (!mask)
5102                         continue;
5103
5104                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5105                 reta = IXGBE_READ_REG(hw, reta_reg);
5106                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5107                         if (mask & (0x1 << j))
5108                                 reta_conf[idx].reta[shift + j] =
5109                                         ((reta >> (CHAR_BIT * j)) &
5110                                                 IXGBE_8_BIT_MASK);
5111                 }
5112         }
5113
5114         return 0;
5115 }
5116
5117 static int
5118 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5119                                 uint32_t index, uint32_t pool)
5120 {
5121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5122         uint32_t enable_addr = 1;
5123
5124         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5125                              pool, enable_addr);
5126 }
5127
5128 static void
5129 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5130 {
5131         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5132
5133         ixgbe_clear_rar(hw, index);
5134 }
5135
5136 static int
5137 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5138 {
5139         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5140
5141         ixgbe_remove_rar(dev, 0);
5142         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5143
5144         return 0;
5145 }
5146
5147 static bool
5148 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5149 {
5150         if (strcmp(dev->device->driver->name, drv->driver.name))
5151                 return false;
5152
5153         return true;
5154 }
5155
5156 bool
5157 is_ixgbe_supported(struct rte_eth_dev *dev)
5158 {
5159         return is_device_supported(dev, &rte_ixgbe_pmd);
5160 }
5161
5162 static int
5163 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5164 {
5165         uint32_t hlreg0;
5166         uint32_t maxfrs;
5167         struct ixgbe_hw *hw;
5168         struct rte_eth_dev_info dev_info;
5169         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5170         struct rte_eth_dev_data *dev_data = dev->data;
5171         int ret;
5172
5173         ret = ixgbe_dev_info_get(dev, &dev_info);
5174         if (ret != 0)
5175                 return ret;
5176
5177         /* check that mtu is within the allowed range */
5178         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5179                 return -EINVAL;
5180
5181         /* If device is started, refuse mtu that requires the support of
5182          * scattered packets when this feature has not been enabled before.
5183          */
5184         if (dev_data->dev_started && !dev_data->scattered_rx &&
5185             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5186              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5187                 PMD_INIT_LOG(ERR, "Stop port first.");
5188                 return -EINVAL;
5189         }
5190
5191         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5192         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5193
5194         /* switch to jumbo mode if needed */
5195         if (frame_size > RTE_ETHER_MAX_LEN) {
5196                 dev->data->dev_conf.rxmode.offloads |=
5197                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5198                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5199         } else {
5200                 dev->data->dev_conf.rxmode.offloads &=
5201                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5202                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5203         }
5204         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5205
5206         /* update max frame size */
5207         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5208
5209         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5210         maxfrs &= 0x0000FFFF;
5211         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5212         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5213
5214         return 0;
5215 }
5216
5217 /*
5218  * Virtual Function operations
5219  */
5220 static void
5221 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5222 {
5223         struct ixgbe_interrupt *intr =
5224                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5225         struct ixgbe_hw *hw =
5226                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5227
5228         PMD_INIT_FUNC_TRACE();
5229
5230         /* Clear interrupt mask to stop from interrupts being generated */
5231         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5232
5233         IXGBE_WRITE_FLUSH(hw);
5234
5235         /* Clear mask value. */
5236         intr->mask = 0;
5237 }
5238
5239 static void
5240 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5241 {
5242         struct ixgbe_interrupt *intr =
5243                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5244         struct ixgbe_hw *hw =
5245                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5246
5247         PMD_INIT_FUNC_TRACE();
5248
5249         /* VF enable interrupt autoclean */
5250         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5251         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5252         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5253
5254         IXGBE_WRITE_FLUSH(hw);
5255
5256         /* Save IXGBE_VTEIMS value to mask. */
5257         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5258 }
5259
5260 static int
5261 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5262 {
5263         struct rte_eth_conf *conf = &dev->data->dev_conf;
5264         struct ixgbe_adapter *adapter = dev->data->dev_private;
5265
5266         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5267                      dev->data->port_id);
5268
5269         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5270                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5271
5272         /*
5273          * VF has no ability to enable/disable HW CRC
5274          * Keep the persistent behavior the same as Host PF
5275          */
5276 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5277         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5278                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5279                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5280         }
5281 #else
5282         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5283                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5284                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5285         }
5286 #endif
5287
5288         /*
5289          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5290          * allocation or vector Rx preconditions we will reset it.
5291          */
5292         adapter->rx_bulk_alloc_allowed = true;
5293         adapter->rx_vec_allowed = true;
5294
5295         return 0;
5296 }
5297
5298 static int
5299 ixgbevf_dev_start(struct rte_eth_dev *dev)
5300 {
5301         struct ixgbe_hw *hw =
5302                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5303         uint32_t intr_vector = 0;
5304         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5305         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5306
5307         int err, mask = 0;
5308
5309         PMD_INIT_FUNC_TRACE();
5310
5311         /* Stop the link setup handler before resetting the HW. */
5312         ixgbe_dev_wait_setup_link_complete(dev, 0);
5313
5314         err = hw->mac.ops.reset_hw(hw);
5315
5316         /**
5317          * In this case, reuses the MAC address assigned by VF
5318          * initialization.
5319          */
5320         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5321                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5322                 return err;
5323         }
5324
5325         hw->mac.get_link_status = true;
5326
5327         /* negotiate mailbox API version to use with the PF. */
5328         ixgbevf_negotiate_api(hw);
5329
5330         ixgbevf_dev_tx_init(dev);
5331
5332         /* This can fail when allocating mbufs for descriptor rings */
5333         err = ixgbevf_dev_rx_init(dev);
5334         if (err) {
5335                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5336                 ixgbe_dev_clear_queues(dev);
5337                 return err;
5338         }
5339
5340         /* Set vfta */
5341         ixgbevf_set_vfta_all(dev, 1);
5342
5343         /* Set HW strip */
5344         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5345                 ETH_VLAN_EXTEND_MASK;
5346         err = ixgbevf_vlan_offload_config(dev, mask);
5347         if (err) {
5348                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5349                 ixgbe_dev_clear_queues(dev);
5350                 return err;
5351         }
5352
5353         ixgbevf_dev_rxtx_start(dev);
5354
5355         /* check and configure queue intr-vector mapping */
5356         if (rte_intr_cap_multiple(intr_handle) &&
5357             dev->data->dev_conf.intr_conf.rxq) {
5358                 /* According to datasheet, only vector 0/1/2 can be used,
5359                  * now only one vector is used for Rx queue
5360                  */
5361                 intr_vector = 1;
5362                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5363                         return -1;
5364         }
5365
5366         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5367                 intr_handle->intr_vec =
5368                         rte_zmalloc("intr_vec",
5369                                     dev->data->nb_rx_queues * sizeof(int), 0);
5370                 if (intr_handle->intr_vec == NULL) {
5371                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5372                                      " intr_vec", dev->data->nb_rx_queues);
5373                         return -ENOMEM;
5374                 }
5375         }
5376         ixgbevf_configure_msix(dev);
5377
5378         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5379          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5380          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5381          * is not cleared, it will fail when following rte_intr_enable( ) tries
5382          * to map Rx queue interrupt to other VFIO vectors.
5383          * So clear uio/vfio intr/evevnfd first to avoid failure.
5384          */
5385         rte_intr_disable(intr_handle);
5386
5387         rte_intr_enable(intr_handle);
5388
5389         /* Re-enable interrupt for VF */
5390         ixgbevf_intr_enable(dev);
5391
5392         /*
5393          * Update link status right before return, because it may
5394          * start link configuration process in a separate thread.
5395          */
5396         ixgbevf_dev_link_update(dev, 0);
5397
5398         hw->adapter_stopped = false;
5399
5400         return 0;
5401 }
5402
5403 static int
5404 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5405 {
5406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5407         struct ixgbe_adapter *adapter = dev->data->dev_private;
5408         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5409         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5410
5411         if (hw->adapter_stopped)
5412                 return 0;
5413
5414         PMD_INIT_FUNC_TRACE();
5415
5416         ixgbe_dev_wait_setup_link_complete(dev, 0);
5417
5418         ixgbevf_intr_disable(dev);
5419
5420         dev->data->dev_started = 0;
5421         hw->adapter_stopped = 1;
5422         ixgbe_stop_adapter(hw);
5423
5424         /*
5425           * Clear what we set, but we still keep shadow_vfta to
5426           * restore after device starts
5427           */
5428         ixgbevf_set_vfta_all(dev, 0);
5429
5430         /* Clear stored conf */
5431         dev->data->scattered_rx = 0;
5432
5433         ixgbe_dev_clear_queues(dev);
5434
5435         /* Clean datapath event and queue/vec mapping */
5436         rte_intr_efd_disable(intr_handle);
5437         if (intr_handle->intr_vec != NULL) {
5438                 rte_free(intr_handle->intr_vec);
5439                 intr_handle->intr_vec = NULL;
5440         }
5441
5442         adapter->rss_reta_updated = 0;
5443
5444         return 0;
5445 }
5446
5447 static int
5448 ixgbevf_dev_close(struct rte_eth_dev *dev)
5449 {
5450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5451         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5452         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5453         int ret;
5454
5455         PMD_INIT_FUNC_TRACE();
5456         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5457                 return 0;
5458
5459         ixgbe_reset_hw(hw);
5460
5461         ret = ixgbevf_dev_stop(dev);
5462
5463         ixgbe_dev_free_queues(dev);
5464
5465         /**
5466          * Remove the VF MAC address ro ensure
5467          * that the VF traffic goes to the PF
5468          * after stop, close and detach of the VF
5469          **/
5470         ixgbevf_remove_mac_addr(dev, 0);
5471
5472         rte_intr_disable(intr_handle);
5473         rte_intr_callback_unregister(intr_handle,
5474                                      ixgbevf_dev_interrupt_handler, dev);
5475
5476         return ret;
5477 }
5478
5479 /*
5480  * Reset VF device
5481  */
5482 static int
5483 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5484 {
5485         int ret;
5486
5487         ret = eth_ixgbevf_dev_uninit(dev);
5488         if (ret)
5489                 return ret;
5490
5491         ret = eth_ixgbevf_dev_init(dev);
5492
5493         return ret;
5494 }
5495
5496 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5497 {
5498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5499         struct ixgbe_vfta *shadow_vfta =
5500                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5501         int i = 0, j = 0, vfta = 0, mask = 1;
5502
5503         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5504                 vfta = shadow_vfta->vfta[i];
5505                 if (vfta) {
5506                         mask = 1;
5507                         for (j = 0; j < 32; j++) {
5508                                 if (vfta & mask)
5509                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5510                                                        on, false);
5511                                 mask <<= 1;
5512                         }
5513                 }
5514         }
5515
5516 }
5517
5518 static int
5519 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5520 {
5521         struct ixgbe_hw *hw =
5522                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5523         struct ixgbe_vfta *shadow_vfta =
5524                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5525         uint32_t vid_idx = 0;
5526         uint32_t vid_bit = 0;
5527         int ret = 0;
5528
5529         PMD_INIT_FUNC_TRACE();
5530
5531         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5532         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5533         if (ret) {
5534                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5535                 return ret;
5536         }
5537         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5538         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5539
5540         /* Save what we set and retore it after device reset */
5541         if (on)
5542                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5543         else
5544                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5545
5546         return 0;
5547 }
5548
5549 static void
5550 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5551 {
5552         struct ixgbe_hw *hw =
5553                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5554         uint32_t ctrl;
5555
5556         PMD_INIT_FUNC_TRACE();
5557
5558         if (queue >= hw->mac.max_rx_queues)
5559                 return;
5560
5561         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5562         if (on)
5563                 ctrl |= IXGBE_RXDCTL_VME;
5564         else
5565                 ctrl &= ~IXGBE_RXDCTL_VME;
5566         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5567
5568         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5569 }
5570
5571 static int
5572 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5573 {
5574         struct ixgbe_rx_queue *rxq;
5575         uint16_t i;
5576         int on = 0;
5577
5578         /* VF function only support hw strip feature, others are not support */
5579         if (mask & ETH_VLAN_STRIP_MASK) {
5580                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5581                         rxq = dev->data->rx_queues[i];
5582                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5583                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5584                 }
5585         }
5586
5587         return 0;
5588 }
5589
5590 static int
5591 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5592 {
5593         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5594
5595         ixgbevf_vlan_offload_config(dev, mask);
5596
5597         return 0;
5598 }
5599
5600 int
5601 ixgbe_vt_check(struct ixgbe_hw *hw)
5602 {
5603         uint32_t reg_val;
5604
5605         /* if Virtualization Technology is enabled */
5606         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5607         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5608                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5609                 return -1;
5610         }
5611
5612         return 0;
5613 }
5614
5615 static uint32_t
5616 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5617 {
5618         uint32_t vector = 0;
5619
5620         switch (hw->mac.mc_filter_type) {
5621         case 0:   /* use bits [47:36] of the address */
5622                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5623                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5624                 break;
5625         case 1:   /* use bits [46:35] of the address */
5626                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5627                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5628                 break;
5629         case 2:   /* use bits [45:34] of the address */
5630                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5631                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5632                 break;
5633         case 3:   /* use bits [43:32] of the address */
5634                 vector = ((uc_addr->addr_bytes[4]) |
5635                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5636                 break;
5637         default:  /* Invalid mc_filter_type */
5638                 break;
5639         }
5640
5641         /* vector can only be 12-bits or boundary will be exceeded */
5642         vector &= 0xFFF;
5643         return vector;
5644 }
5645
5646 static int
5647 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5648                         struct rte_ether_addr *mac_addr, uint8_t on)
5649 {
5650         uint32_t vector;
5651         uint32_t uta_idx;
5652         uint32_t reg_val;
5653         uint32_t uta_shift;
5654         uint32_t rc;
5655         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5656         const uint32_t ixgbe_uta_bit_shift = 5;
5657         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5658         const uint32_t bit1 = 0x1;
5659
5660         struct ixgbe_hw *hw =
5661                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5662         struct ixgbe_uta_info *uta_info =
5663                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5664
5665         /* The UTA table only exists on 82599 hardware and newer */
5666         if (hw->mac.type < ixgbe_mac_82599EB)
5667                 return -ENOTSUP;
5668
5669         vector = ixgbe_uta_vector(hw, mac_addr);
5670         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5671         uta_shift = vector & ixgbe_uta_bit_mask;
5672
5673         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5674         if (rc == on)
5675                 return 0;
5676
5677         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5678         if (on) {
5679                 uta_info->uta_in_use++;
5680                 reg_val |= (bit1 << uta_shift);
5681                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5682         } else {
5683                 uta_info->uta_in_use--;
5684                 reg_val &= ~(bit1 << uta_shift);
5685                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5686         }
5687
5688         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5689
5690         if (uta_info->uta_in_use > 0)
5691                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5692                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5693         else
5694                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5695
5696         return 0;
5697 }
5698
5699 static int
5700 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5701 {
5702         int i;
5703         struct ixgbe_hw *hw =
5704                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5705         struct ixgbe_uta_info *uta_info =
5706                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5707
5708         /* The UTA table only exists on 82599 hardware and newer */
5709         if (hw->mac.type < ixgbe_mac_82599EB)
5710                 return -ENOTSUP;
5711
5712         if (on) {
5713                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5714                         uta_info->uta_shadow[i] = ~0;
5715                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5716                 }
5717         } else {
5718                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5719                         uta_info->uta_shadow[i] = 0;
5720                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5721                 }
5722         }
5723         return 0;
5724
5725 }
5726
5727 uint32_t
5728 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5729 {
5730         uint32_t new_val = orig_val;
5731
5732         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5733                 new_val |= IXGBE_VMOLR_AUPE;
5734         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5735                 new_val |= IXGBE_VMOLR_ROMPE;
5736         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5737                 new_val |= IXGBE_VMOLR_ROPE;
5738         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5739                 new_val |= IXGBE_VMOLR_BAM;
5740         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5741                 new_val |= IXGBE_VMOLR_MPE;
5742
5743         return new_val;
5744 }
5745
5746 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5747 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5748 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5749 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5750 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5751         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5752         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5753
5754 static int
5755 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5756                       struct rte_eth_mirror_conf *mirror_conf,
5757                       uint8_t rule_id, uint8_t on)
5758 {
5759         uint32_t mr_ctl, vlvf;
5760         uint32_t mp_lsb = 0;
5761         uint32_t mv_msb = 0;
5762         uint32_t mv_lsb = 0;
5763         uint32_t mp_msb = 0;
5764         uint8_t i = 0;
5765         int reg_index = 0;
5766         uint64_t vlan_mask = 0;
5767
5768         const uint8_t pool_mask_offset = 32;
5769         const uint8_t vlan_mask_offset = 32;
5770         const uint8_t dst_pool_offset = 8;
5771         const uint8_t rule_mr_offset  = 4;
5772         const uint8_t mirror_rule_mask = 0x0F;
5773
5774         struct ixgbe_mirror_info *mr_info =
5775                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5776         struct ixgbe_hw *hw =
5777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5778         uint8_t mirror_type = 0;
5779
5780         if (ixgbe_vt_check(hw) < 0)
5781                 return -ENOTSUP;
5782
5783         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5784                 return -EINVAL;
5785
5786         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5787                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5788                             mirror_conf->rule_type);
5789                 return -EINVAL;
5790         }
5791
5792         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5793                 mirror_type |= IXGBE_MRCTL_VLME;
5794                 /* Check if vlan id is valid and find conresponding VLAN ID
5795                  * index in VLVF
5796                  */
5797                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5798                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5799                                 /* search vlan id related pool vlan filter
5800                                  * index
5801                                  */
5802                                 reg_index = ixgbe_find_vlvf_slot(
5803                                                 hw,
5804                                                 mirror_conf->vlan.vlan_id[i],
5805                                                 false);
5806                                 if (reg_index < 0)
5807                                         return -EINVAL;
5808                                 vlvf = IXGBE_READ_REG(hw,
5809                                                       IXGBE_VLVF(reg_index));
5810                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5811                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5812                                       mirror_conf->vlan.vlan_id[i]))
5813                                         vlan_mask |= (1ULL << reg_index);
5814                                 else
5815                                         return -EINVAL;
5816                         }
5817                 }
5818
5819                 if (on) {
5820                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5821                         mv_msb = vlan_mask >> vlan_mask_offset;
5822
5823                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5824                                                 mirror_conf->vlan.vlan_mask;
5825                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5826                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5827                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5828                                                 mirror_conf->vlan.vlan_id[i];
5829                         }
5830                 } else {
5831                         mv_lsb = 0;
5832                         mv_msb = 0;
5833                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5834                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5835                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5836                 }
5837         }
5838
5839         /**
5840          * if enable pool mirror, write related pool mask register,if disable
5841          * pool mirror, clear PFMRVM register
5842          */
5843         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5844                 mirror_type |= IXGBE_MRCTL_VPME;
5845                 if (on) {
5846                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5847                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5848                         mr_info->mr_conf[rule_id].pool_mask =
5849                                         mirror_conf->pool_mask;
5850
5851                 } else {
5852                         mp_lsb = 0;
5853                         mp_msb = 0;
5854                         mr_info->mr_conf[rule_id].pool_mask = 0;
5855                 }
5856         }
5857         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5858                 mirror_type |= IXGBE_MRCTL_UPME;
5859         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5860                 mirror_type |= IXGBE_MRCTL_DPME;
5861
5862         /* read  mirror control register and recalculate it */
5863         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5864
5865         if (on) {
5866                 mr_ctl |= mirror_type;
5867                 mr_ctl &= mirror_rule_mask;
5868                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5869         } else {
5870                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5871         }
5872
5873         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5874         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5875
5876         /* write mirrror control  register */
5877         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5878
5879         /* write pool mirrror control  register */
5880         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5881                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5882                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5883                                 mp_msb);
5884         }
5885         /* write VLAN mirrror control  register */
5886         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5887                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5888                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5889                                 mv_msb);
5890         }
5891
5892         return 0;
5893 }
5894
5895 static int
5896 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5897 {
5898         int mr_ctl = 0;
5899         uint32_t lsb_val = 0;
5900         uint32_t msb_val = 0;
5901         const uint8_t rule_mr_offset = 4;
5902
5903         struct ixgbe_hw *hw =
5904                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5905         struct ixgbe_mirror_info *mr_info =
5906                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5907
5908         if (ixgbe_vt_check(hw) < 0)
5909                 return -ENOTSUP;
5910
5911         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5912                 return -EINVAL;
5913
5914         memset(&mr_info->mr_conf[rule_id], 0,
5915                sizeof(struct rte_eth_mirror_conf));
5916
5917         /* clear PFVMCTL register */
5918         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5919
5920         /* clear pool mask register */
5921         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5922         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5923
5924         /* clear vlan mask register */
5925         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5926         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5927
5928         return 0;
5929 }
5930
5931 static int
5932 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5933 {
5934         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5935         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5936         struct ixgbe_interrupt *intr =
5937                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5938         struct ixgbe_hw *hw =
5939                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5940         uint32_t vec = IXGBE_MISC_VEC_ID;
5941
5942         if (rte_intr_allow_others(intr_handle))
5943                 vec = IXGBE_RX_VEC_START;
5944         intr->mask |= (1 << vec);
5945         RTE_SET_USED(queue_id);
5946         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5947
5948         rte_intr_ack(intr_handle);
5949
5950         return 0;
5951 }
5952
5953 static int
5954 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5955 {
5956         struct ixgbe_interrupt *intr =
5957                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5958         struct ixgbe_hw *hw =
5959                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5960         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5961         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5962         uint32_t vec = IXGBE_MISC_VEC_ID;
5963
5964         if (rte_intr_allow_others(intr_handle))
5965                 vec = IXGBE_RX_VEC_START;
5966         intr->mask &= ~(1 << vec);
5967         RTE_SET_USED(queue_id);
5968         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5969
5970         return 0;
5971 }
5972
5973 static int
5974 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5975 {
5976         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5977         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5978         uint32_t mask;
5979         struct ixgbe_hw *hw =
5980                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981         struct ixgbe_interrupt *intr =
5982                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5983
5984         if (queue_id < 16) {
5985                 ixgbe_disable_intr(hw);
5986                 intr->mask |= (1 << queue_id);
5987                 ixgbe_enable_intr(dev);
5988         } else if (queue_id < 32) {
5989                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5990                 mask &= (1 << queue_id);
5991                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5992         } else if (queue_id < 64) {
5993                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5994                 mask &= (1 << (queue_id - 32));
5995                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5996         }
5997         rte_intr_ack(intr_handle);
5998
5999         return 0;
6000 }
6001
6002 static int
6003 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6004 {
6005         uint32_t mask;
6006         struct ixgbe_hw *hw =
6007                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6008         struct ixgbe_interrupt *intr =
6009                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6010
6011         if (queue_id < 16) {
6012                 ixgbe_disable_intr(hw);
6013                 intr->mask &= ~(1 << queue_id);
6014                 ixgbe_enable_intr(dev);
6015         } else if (queue_id < 32) {
6016                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6017                 mask &= ~(1 << queue_id);
6018                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6019         } else if (queue_id < 64) {
6020                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6021                 mask &= ~(1 << (queue_id - 32));
6022                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6023         }
6024
6025         return 0;
6026 }
6027
6028 static void
6029 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6030                      uint8_t queue, uint8_t msix_vector)
6031 {
6032         uint32_t tmp, idx;
6033
6034         if (direction == -1) {
6035                 /* other causes */
6036                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6037                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6038                 tmp &= ~0xFF;
6039                 tmp |= msix_vector;
6040                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6041         } else {
6042                 /* rx or tx cause */
6043                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6044                 idx = ((16 * (queue & 1)) + (8 * direction));
6045                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6046                 tmp &= ~(0xFF << idx);
6047                 tmp |= (msix_vector << idx);
6048                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6049         }
6050 }
6051
6052 /**
6053  * set the IVAR registers, mapping interrupt causes to vectors
6054  * @param hw
6055  *  pointer to ixgbe_hw struct
6056  * @direction
6057  *  0 for Rx, 1 for Tx, -1 for other causes
6058  * @queue
6059  *  queue to map the corresponding interrupt to
6060  * @msix_vector
6061  *  the vector to map to the corresponding queue
6062  */
6063 static void
6064 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6065                    uint8_t queue, uint8_t msix_vector)
6066 {
6067         uint32_t tmp, idx;
6068
6069         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6070         if (hw->mac.type == ixgbe_mac_82598EB) {
6071                 if (direction == -1)
6072                         direction = 0;
6073                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6074                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6075                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6076                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6077                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6078         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6079                         (hw->mac.type == ixgbe_mac_X540) ||
6080                         (hw->mac.type == ixgbe_mac_X550) ||
6081                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6082                 if (direction == -1) {
6083                         /* other causes */
6084                         idx = ((queue & 1) * 8);
6085                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6086                         tmp &= ~(0xFF << idx);
6087                         tmp |= (msix_vector << idx);
6088                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6089                 } else {
6090                         /* rx or tx causes */
6091                         idx = ((16 * (queue & 1)) + (8 * direction));
6092                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6093                         tmp &= ~(0xFF << idx);
6094                         tmp |= (msix_vector << idx);
6095                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6096                 }
6097         }
6098 }
6099
6100 static void
6101 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6102 {
6103         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6104         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6105         struct ixgbe_hw *hw =
6106                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6107         uint32_t q_idx;
6108         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6109         uint32_t base = IXGBE_MISC_VEC_ID;
6110
6111         /* Configure VF other cause ivar */
6112         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6113
6114         /* won't configure msix register if no mapping is done
6115          * between intr vector and event fd.
6116          */
6117         if (!rte_intr_dp_is_en(intr_handle))
6118                 return;
6119
6120         if (rte_intr_allow_others(intr_handle)) {
6121                 base = IXGBE_RX_VEC_START;
6122                 vector_idx = IXGBE_RX_VEC_START;
6123         }
6124
6125         /* Configure all RX queues of VF */
6126         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6127                 /* Force all queue use vector 0,
6128                  * as IXGBE_VF_MAXMSIVECOTR = 1
6129                  */
6130                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6131                 intr_handle->intr_vec[q_idx] = vector_idx;
6132                 if (vector_idx < base + intr_handle->nb_efd - 1)
6133                         vector_idx++;
6134         }
6135
6136         /* As RX queue setting above show, all queues use the vector 0.
6137          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6138          */
6139         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6140                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6141                         | IXGBE_EITR_CNT_WDIS);
6142 }
6143
6144 /**
6145  * Sets up the hardware to properly generate MSI-X interrupts
6146  * @hw
6147  *  board private structure
6148  */
6149 static void
6150 ixgbe_configure_msix(struct rte_eth_dev *dev)
6151 {
6152         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6153         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6154         struct ixgbe_hw *hw =
6155                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6156         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6157         uint32_t vec = IXGBE_MISC_VEC_ID;
6158         uint32_t mask;
6159         uint32_t gpie;
6160
6161         /* won't configure msix register if no mapping is done
6162          * between intr vector and event fd
6163          * but if misx has been enabled already, need to configure
6164          * auto clean, auto mask and throttling.
6165          */
6166         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6167         if (!rte_intr_dp_is_en(intr_handle) &&
6168             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6169                 return;
6170
6171         if (rte_intr_allow_others(intr_handle))
6172                 vec = base = IXGBE_RX_VEC_START;
6173
6174         /* setup GPIE for MSI-x mode */
6175         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6176         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6177                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6178         /* auto clearing and auto setting corresponding bits in EIMS
6179          * when MSI-X interrupt is triggered
6180          */
6181         if (hw->mac.type == ixgbe_mac_82598EB) {
6182                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6183         } else {
6184                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6185                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6186         }
6187         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6188
6189         /* Populate the IVAR table and set the ITR values to the
6190          * corresponding register.
6191          */
6192         if (rte_intr_dp_is_en(intr_handle)) {
6193                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6194                         queue_id++) {
6195                         /* by default, 1:1 mapping */
6196                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6197                         intr_handle->intr_vec[queue_id] = vec;
6198                         if (vec < base + intr_handle->nb_efd - 1)
6199                                 vec++;
6200                 }
6201
6202                 switch (hw->mac.type) {
6203                 case ixgbe_mac_82598EB:
6204                         ixgbe_set_ivar_map(hw, -1,
6205                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6206                                            IXGBE_MISC_VEC_ID);
6207                         break;
6208                 case ixgbe_mac_82599EB:
6209                 case ixgbe_mac_X540:
6210                 case ixgbe_mac_X550:
6211                 case ixgbe_mac_X550EM_x:
6212                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6213                         break;
6214                 default:
6215                         break;
6216                 }
6217         }
6218         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6219                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6220                         | IXGBE_EITR_CNT_WDIS);
6221
6222         /* set up to autoclear timer, and the vectors */
6223         mask = IXGBE_EIMS_ENABLE_MASK;
6224         mask &= ~(IXGBE_EIMS_OTHER |
6225                   IXGBE_EIMS_MAILBOX |
6226                   IXGBE_EIMS_LSC);
6227
6228         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6229 }
6230
6231 int
6232 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6233                            uint16_t queue_idx, uint16_t tx_rate)
6234 {
6235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6236         struct rte_eth_rxmode *rxmode;
6237         uint32_t rf_dec, rf_int;
6238         uint32_t bcnrc_val;
6239         uint16_t link_speed = dev->data->dev_link.link_speed;
6240
6241         if (queue_idx >= hw->mac.max_tx_queues)
6242                 return -EINVAL;
6243
6244         if (tx_rate != 0) {
6245                 /* Calculate the rate factor values to set */
6246                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6247                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6248                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6249
6250                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6251                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6252                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6253                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6254         } else {
6255                 bcnrc_val = 0;
6256         }
6257
6258         rxmode = &dev->data->dev_conf.rxmode;
6259         /*
6260          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6261          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6262          * set as 0x4.
6263          */
6264         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6265             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6266                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6267                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6268         else
6269                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6270                         IXGBE_MMW_SIZE_DEFAULT);
6271
6272         /* Set RTTBCNRC of queue X */
6273         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6274         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6275         IXGBE_WRITE_FLUSH(hw);
6276
6277         return 0;
6278 }
6279
6280 static int
6281 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6282                      __rte_unused uint32_t index,
6283                      __rte_unused uint32_t pool)
6284 {
6285         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6286         int diag;
6287
6288         /*
6289          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6290          * operation. Trap this case to avoid exhausting the [very limited]
6291          * set of PF resources used to store VF MAC addresses.
6292          */
6293         if (memcmp(hw->mac.perm_addr, mac_addr,
6294                         sizeof(struct rte_ether_addr)) == 0)
6295                 return -1;
6296         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6297         if (diag != 0)
6298                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6299                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6300                             mac_addr->addr_bytes[0],
6301                             mac_addr->addr_bytes[1],
6302                             mac_addr->addr_bytes[2],
6303                             mac_addr->addr_bytes[3],
6304                             mac_addr->addr_bytes[4],
6305                             mac_addr->addr_bytes[5],
6306                             diag);
6307         return diag;
6308 }
6309
6310 static void
6311 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6312 {
6313         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6314         struct rte_ether_addr *perm_addr =
6315                 (struct rte_ether_addr *)hw->mac.perm_addr;
6316         struct rte_ether_addr *mac_addr;
6317         uint32_t i;
6318         int diag;
6319
6320         /*
6321          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6322          * not support the deletion of a given MAC address.
6323          * Instead, it imposes to delete all MAC addresses, then to add again
6324          * all MAC addresses with the exception of the one to be deleted.
6325          */
6326         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6327
6328         /*
6329          * Add again all MAC addresses, with the exception of the deleted one
6330          * and of the permanent MAC address.
6331          */
6332         for (i = 0, mac_addr = dev->data->mac_addrs;
6333              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6334                 /* Skip the deleted MAC address */
6335                 if (i == index)
6336                         continue;
6337                 /* Skip NULL MAC addresses */
6338                 if (rte_is_zero_ether_addr(mac_addr))
6339                         continue;
6340                 /* Skip the permanent MAC address */
6341                 if (memcmp(perm_addr, mac_addr,
6342                                 sizeof(struct rte_ether_addr)) == 0)
6343                         continue;
6344                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6345                 if (diag != 0)
6346                         PMD_DRV_LOG(ERR,
6347                                     "Adding again MAC address "
6348                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6349                                     "diag=%d",
6350                                     mac_addr->addr_bytes[0],
6351                                     mac_addr->addr_bytes[1],
6352                                     mac_addr->addr_bytes[2],
6353                                     mac_addr->addr_bytes[3],
6354                                     mac_addr->addr_bytes[4],
6355                                     mac_addr->addr_bytes[5],
6356                                     diag);
6357         }
6358 }
6359
6360 static int
6361 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6362                         struct rte_ether_addr *addr)
6363 {
6364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6365
6366         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6367
6368         return 0;
6369 }
6370
6371 int
6372 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6373                         struct rte_eth_syn_filter *filter,
6374                         bool add)
6375 {
6376         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6377         struct ixgbe_filter_info *filter_info =
6378                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6379         uint32_t syn_info;
6380         uint32_t synqf;
6381
6382         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6383                 return -EINVAL;
6384
6385         syn_info = filter_info->syn_info;
6386
6387         if (add) {
6388                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6389                         return -EINVAL;
6390                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6391                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6392
6393                 if (filter->hig_pri)
6394                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6395                 else
6396                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6397         } else {
6398                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6399                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6400                         return -ENOENT;
6401                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6402         }
6403
6404         filter_info->syn_info = synqf;
6405         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6406         IXGBE_WRITE_FLUSH(hw);
6407         return 0;
6408 }
6409
6410 static int
6411 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6412                         struct rte_eth_syn_filter *filter)
6413 {
6414         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6415         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6416
6417         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6418                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6419                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6420                 return 0;
6421         }
6422         return -ENOENT;
6423 }
6424
6425 static int
6426 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6427                         enum rte_filter_op filter_op,
6428                         void *arg)
6429 {
6430         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6431         int ret;
6432
6433         MAC_TYPE_FILTER_SUP(hw->mac.type);
6434
6435         if (filter_op == RTE_ETH_FILTER_NOP)
6436                 return 0;
6437
6438         if (arg == NULL) {
6439                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6440                             filter_op);
6441                 return -EINVAL;
6442         }
6443
6444         switch (filter_op) {
6445         case RTE_ETH_FILTER_ADD:
6446                 ret = ixgbe_syn_filter_set(dev,
6447                                 (struct rte_eth_syn_filter *)arg,
6448                                 TRUE);
6449                 break;
6450         case RTE_ETH_FILTER_DELETE:
6451                 ret = ixgbe_syn_filter_set(dev,
6452                                 (struct rte_eth_syn_filter *)arg,
6453                                 FALSE);
6454                 break;
6455         case RTE_ETH_FILTER_GET:
6456                 ret = ixgbe_syn_filter_get(dev,
6457                                 (struct rte_eth_syn_filter *)arg);
6458                 break;
6459         default:
6460                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6461                 ret = -EINVAL;
6462                 break;
6463         }
6464
6465         return ret;
6466 }
6467
6468
6469 static inline enum ixgbe_5tuple_protocol
6470 convert_protocol_type(uint8_t protocol_value)
6471 {
6472         if (protocol_value == IPPROTO_TCP)
6473                 return IXGBE_FILTER_PROTOCOL_TCP;
6474         else if (protocol_value == IPPROTO_UDP)
6475                 return IXGBE_FILTER_PROTOCOL_UDP;
6476         else if (protocol_value == IPPROTO_SCTP)
6477                 return IXGBE_FILTER_PROTOCOL_SCTP;
6478         else
6479                 return IXGBE_FILTER_PROTOCOL_NONE;
6480 }
6481
6482 /* inject a 5-tuple filter to HW */
6483 static inline void
6484 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6485                            struct ixgbe_5tuple_filter *filter)
6486 {
6487         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6488         int i;
6489         uint32_t ftqf, sdpqf;
6490         uint32_t l34timir = 0;
6491         uint8_t mask = 0xff;
6492
6493         i = filter->index;
6494
6495         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6496                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6497         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6498
6499         ftqf = (uint32_t)(filter->filter_info.proto &
6500                 IXGBE_FTQF_PROTOCOL_MASK);
6501         ftqf |= (uint32_t)((filter->filter_info.priority &
6502                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6503         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6504                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6505         if (filter->filter_info.dst_ip_mask == 0)
6506                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6507         if (filter->filter_info.src_port_mask == 0)
6508                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6509         if (filter->filter_info.dst_port_mask == 0)
6510                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6511         if (filter->filter_info.proto_mask == 0)
6512                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6513         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6514         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6515         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6516
6517         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6518         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6519         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6520         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6521
6522         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6523         l34timir |= (uint32_t)(filter->queue <<
6524                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6525         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6526 }
6527
6528 /*
6529  * add a 5tuple filter
6530  *
6531  * @param
6532  * dev: Pointer to struct rte_eth_dev.
6533  * index: the index the filter allocates.
6534  * filter: ponter to the filter that will be added.
6535  * rx_queue: the queue id the filter assigned to.
6536  *
6537  * @return
6538  *    - On success, zero.
6539  *    - On failure, a negative value.
6540  */
6541 static int
6542 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6543                         struct ixgbe_5tuple_filter *filter)
6544 {
6545         struct ixgbe_filter_info *filter_info =
6546                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6547         int i, idx, shift;
6548
6549         /*
6550          * look for an unused 5tuple filter index,
6551          * and insert the filter to list.
6552          */
6553         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6554                 idx = i / (sizeof(uint32_t) * NBBY);
6555                 shift = i % (sizeof(uint32_t) * NBBY);
6556                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6557                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6558                         filter->index = i;
6559                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6560                                           filter,
6561                                           entries);
6562                         break;
6563                 }
6564         }
6565         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6566                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6567                 return -ENOSYS;
6568         }
6569
6570         ixgbe_inject_5tuple_filter(dev, filter);
6571
6572         return 0;
6573 }
6574
6575 /*
6576  * remove a 5tuple filter
6577  *
6578  * @param
6579  * dev: Pointer to struct rte_eth_dev.
6580  * filter: the pointer of the filter will be removed.
6581  */
6582 static void
6583 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6584                         struct ixgbe_5tuple_filter *filter)
6585 {
6586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6587         struct ixgbe_filter_info *filter_info =
6588                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6589         uint16_t index = filter->index;
6590
6591         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6592                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6593         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6594         rte_free(filter);
6595
6596         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6597         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6598         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6599         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6600         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6601 }
6602
6603 static int
6604 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6605 {
6606         struct ixgbe_hw *hw;
6607         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6608         struct rte_eth_dev_data *dev_data = dev->data;
6609
6610         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6611
6612         if (mtu < RTE_ETHER_MIN_MTU ||
6613                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6614                 return -EINVAL;
6615
6616         /* If device is started, refuse mtu that requires the support of
6617          * scattered packets when this feature has not been enabled before.
6618          */
6619         if (dev_data->dev_started && !dev_data->scattered_rx &&
6620             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6621              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6622                 PMD_INIT_LOG(ERR, "Stop port first.");
6623                 return -EINVAL;
6624         }
6625
6626         /*
6627          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6628          * request of the version 2.0 of the mailbox API.
6629          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6630          * of the mailbox API.
6631          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6632          * prior to 3.11.33 which contains the following change:
6633          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6634          */
6635         ixgbevf_rlpml_set_vf(hw, max_frame);
6636
6637         /* update max frame size */
6638         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6639         return 0;
6640 }
6641
6642 static inline struct ixgbe_5tuple_filter *
6643 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6644                         struct ixgbe_5tuple_filter_info *key)
6645 {
6646         struct ixgbe_5tuple_filter *it;
6647
6648         TAILQ_FOREACH(it, filter_list, entries) {
6649                 if (memcmp(key, &it->filter_info,
6650                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6651                         return it;
6652                 }
6653         }
6654         return NULL;
6655 }
6656
6657 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6658 static inline int
6659 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6660                         struct ixgbe_5tuple_filter_info *filter_info)
6661 {
6662         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6663                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6664                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6665                 return -EINVAL;
6666
6667         switch (filter->dst_ip_mask) {
6668         case UINT32_MAX:
6669                 filter_info->dst_ip_mask = 0;
6670                 filter_info->dst_ip = filter->dst_ip;
6671                 break;
6672         case 0:
6673                 filter_info->dst_ip_mask = 1;
6674                 break;
6675         default:
6676                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6677                 return -EINVAL;
6678         }
6679
6680         switch (filter->src_ip_mask) {
6681         case UINT32_MAX:
6682                 filter_info->src_ip_mask = 0;
6683                 filter_info->src_ip = filter->src_ip;
6684                 break;
6685         case 0:
6686                 filter_info->src_ip_mask = 1;
6687                 break;
6688         default:
6689                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6690                 return -EINVAL;
6691         }
6692
6693         switch (filter->dst_port_mask) {
6694         case UINT16_MAX:
6695                 filter_info->dst_port_mask = 0;
6696                 filter_info->dst_port = filter->dst_port;
6697                 break;
6698         case 0:
6699                 filter_info->dst_port_mask = 1;
6700                 break;
6701         default:
6702                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6703                 return -EINVAL;
6704         }
6705
6706         switch (filter->src_port_mask) {
6707         case UINT16_MAX:
6708                 filter_info->src_port_mask = 0;
6709                 filter_info->src_port = filter->src_port;
6710                 break;
6711         case 0:
6712                 filter_info->src_port_mask = 1;
6713                 break;
6714         default:
6715                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6716                 return -EINVAL;
6717         }
6718
6719         switch (filter->proto_mask) {
6720         case UINT8_MAX:
6721                 filter_info->proto_mask = 0;
6722                 filter_info->proto =
6723                         convert_protocol_type(filter->proto);
6724                 break;
6725         case 0:
6726                 filter_info->proto_mask = 1;
6727                 break;
6728         default:
6729                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6730                 return -EINVAL;
6731         }
6732
6733         filter_info->priority = (uint8_t)filter->priority;
6734         return 0;
6735 }
6736
6737 /*
6738  * add or delete a ntuple filter
6739  *
6740  * @param
6741  * dev: Pointer to struct rte_eth_dev.
6742  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6743  * add: if true, add filter, if false, remove filter
6744  *
6745  * @return
6746  *    - On success, zero.
6747  *    - On failure, a negative value.
6748  */
6749 int
6750 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6751                         struct rte_eth_ntuple_filter *ntuple_filter,
6752                         bool add)
6753 {
6754         struct ixgbe_filter_info *filter_info =
6755                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6756         struct ixgbe_5tuple_filter_info filter_5tuple;
6757         struct ixgbe_5tuple_filter *filter;
6758         int ret;
6759
6760         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6761                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6762                 return -EINVAL;
6763         }
6764
6765         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6766         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6767         if (ret < 0)
6768                 return ret;
6769
6770         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6771                                          &filter_5tuple);
6772         if (filter != NULL && add) {
6773                 PMD_DRV_LOG(ERR, "filter exists.");
6774                 return -EEXIST;
6775         }
6776         if (filter == NULL && !add) {
6777                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6778                 return -ENOENT;
6779         }
6780
6781         if (add) {
6782                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6783                                 sizeof(struct ixgbe_5tuple_filter), 0);
6784                 if (filter == NULL)
6785                         return -ENOMEM;
6786                 rte_memcpy(&filter->filter_info,
6787                                  &filter_5tuple,
6788                                  sizeof(struct ixgbe_5tuple_filter_info));
6789                 filter->queue = ntuple_filter->queue;
6790                 ret = ixgbe_add_5tuple_filter(dev, filter);
6791                 if (ret < 0) {
6792                         rte_free(filter);
6793                         return ret;
6794                 }
6795         } else
6796                 ixgbe_remove_5tuple_filter(dev, filter);
6797
6798         return 0;
6799 }
6800
6801 /*
6802  * get a ntuple filter
6803  *
6804  * @param
6805  * dev: Pointer to struct rte_eth_dev.
6806  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6807  *
6808  * @return
6809  *    - On success, zero.
6810  *    - On failure, a negative value.
6811  */
6812 static int
6813 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6814                         struct rte_eth_ntuple_filter *ntuple_filter)
6815 {
6816         struct ixgbe_filter_info *filter_info =
6817                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6818         struct ixgbe_5tuple_filter_info filter_5tuple;
6819         struct ixgbe_5tuple_filter *filter;
6820         int ret;
6821
6822         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6823                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6824                 return -EINVAL;
6825         }
6826
6827         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6828         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6829         if (ret < 0)
6830                 return ret;
6831
6832         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6833                                          &filter_5tuple);
6834         if (filter == NULL) {
6835                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6836                 return -ENOENT;
6837         }
6838         ntuple_filter->queue = filter->queue;
6839         return 0;
6840 }
6841
6842 /*
6843  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6844  * @dev: pointer to rte_eth_dev structure
6845  * @filter_op:operation will be taken.
6846  * @arg: a pointer to specific structure corresponding to the filter_op
6847  *
6848  * @return
6849  *    - On success, zero.
6850  *    - On failure, a negative value.
6851  */
6852 static int
6853 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6854                                 enum rte_filter_op filter_op,
6855                                 void *arg)
6856 {
6857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6858         int ret;
6859
6860         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6861
6862         if (filter_op == RTE_ETH_FILTER_NOP)
6863                 return 0;
6864
6865         if (arg == NULL) {
6866                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6867                             filter_op);
6868                 return -EINVAL;
6869         }
6870
6871         switch (filter_op) {
6872         case RTE_ETH_FILTER_ADD:
6873                 ret = ixgbe_add_del_ntuple_filter(dev,
6874                         (struct rte_eth_ntuple_filter *)arg,
6875                         TRUE);
6876                 break;
6877         case RTE_ETH_FILTER_DELETE:
6878                 ret = ixgbe_add_del_ntuple_filter(dev,
6879                         (struct rte_eth_ntuple_filter *)arg,
6880                         FALSE);
6881                 break;
6882         case RTE_ETH_FILTER_GET:
6883                 ret = ixgbe_get_ntuple_filter(dev,
6884                         (struct rte_eth_ntuple_filter *)arg);
6885                 break;
6886         default:
6887                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6888                 ret = -EINVAL;
6889                 break;
6890         }
6891         return ret;
6892 }
6893
6894 int
6895 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6896                         struct rte_eth_ethertype_filter *filter,
6897                         bool add)
6898 {
6899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6900         struct ixgbe_filter_info *filter_info =
6901                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6902         uint32_t etqf = 0;
6903         uint32_t etqs = 0;
6904         int ret;
6905         struct ixgbe_ethertype_filter ethertype_filter;
6906
6907         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6908                 return -EINVAL;
6909
6910         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6911                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6912                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6913                         " ethertype filter.", filter->ether_type);
6914                 return -EINVAL;
6915         }
6916
6917         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6918                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6919                 return -EINVAL;
6920         }
6921         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6922                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6923                 return -EINVAL;
6924         }
6925
6926         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6927         if (ret >= 0 && add) {
6928                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6929                             filter->ether_type);
6930                 return -EEXIST;
6931         }
6932         if (ret < 0 && !add) {
6933                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6934                             filter->ether_type);
6935                 return -ENOENT;
6936         }
6937
6938         if (add) {
6939                 etqf = IXGBE_ETQF_FILTER_EN;
6940                 etqf |= (uint32_t)filter->ether_type;
6941                 etqs |= (uint32_t)((filter->queue <<
6942                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6943                                     IXGBE_ETQS_RX_QUEUE);
6944                 etqs |= IXGBE_ETQS_QUEUE_EN;
6945
6946                 ethertype_filter.ethertype = filter->ether_type;
6947                 ethertype_filter.etqf = etqf;
6948                 ethertype_filter.etqs = etqs;
6949                 ethertype_filter.conf = FALSE;
6950                 ret = ixgbe_ethertype_filter_insert(filter_info,
6951                                                     &ethertype_filter);
6952                 if (ret < 0) {
6953                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6954                         return -ENOSPC;
6955                 }
6956         } else {
6957                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6958                 if (ret < 0)
6959                         return -ENOSYS;
6960         }
6961         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6962         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6963         IXGBE_WRITE_FLUSH(hw);
6964
6965         return 0;
6966 }
6967
6968 static int
6969 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6970                         struct rte_eth_ethertype_filter *filter)
6971 {
6972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6973         struct ixgbe_filter_info *filter_info =
6974                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6975         uint32_t etqf, etqs;
6976         int ret;
6977
6978         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6979         if (ret < 0) {
6980                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6981                             filter->ether_type);
6982                 return -ENOENT;
6983         }
6984
6985         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6986         if (etqf & IXGBE_ETQF_FILTER_EN) {
6987                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6988                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6989                 filter->flags = 0;
6990                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6991                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6992                 return 0;
6993         }
6994         return -ENOENT;
6995 }
6996
6997 /*
6998  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6999  * @dev: pointer to rte_eth_dev structure
7000  * @filter_op:operation will be taken.
7001  * @arg: a pointer to specific structure corresponding to the filter_op
7002  */
7003 static int
7004 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7005                                 enum rte_filter_op filter_op,
7006                                 void *arg)
7007 {
7008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7009         int ret;
7010
7011         MAC_TYPE_FILTER_SUP(hw->mac.type);
7012
7013         if (filter_op == RTE_ETH_FILTER_NOP)
7014                 return 0;
7015
7016         if (arg == NULL) {
7017                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7018                             filter_op);
7019                 return -EINVAL;
7020         }
7021
7022         switch (filter_op) {
7023         case RTE_ETH_FILTER_ADD:
7024                 ret = ixgbe_add_del_ethertype_filter(dev,
7025                         (struct rte_eth_ethertype_filter *)arg,
7026                         TRUE);
7027                 break;
7028         case RTE_ETH_FILTER_DELETE:
7029                 ret = ixgbe_add_del_ethertype_filter(dev,
7030                         (struct rte_eth_ethertype_filter *)arg,
7031                         FALSE);
7032                 break;
7033         case RTE_ETH_FILTER_GET:
7034                 ret = ixgbe_get_ethertype_filter(dev,
7035                         (struct rte_eth_ethertype_filter *)arg);
7036                 break;
7037         default:
7038                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7039                 ret = -EINVAL;
7040                 break;
7041         }
7042         return ret;
7043 }
7044
7045 static int
7046 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7047                      enum rte_filter_type filter_type,
7048                      enum rte_filter_op filter_op,
7049                      void *arg)
7050 {
7051         int ret = 0;
7052
7053         switch (filter_type) {
7054         case RTE_ETH_FILTER_NTUPLE:
7055                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7056                 break;
7057         case RTE_ETH_FILTER_ETHERTYPE:
7058                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7059                 break;
7060         case RTE_ETH_FILTER_SYN:
7061                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7062                 break;
7063         case RTE_ETH_FILTER_FDIR:
7064                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7065                 break;
7066         case RTE_ETH_FILTER_L2_TUNNEL:
7067                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7068                 break;
7069         case RTE_ETH_FILTER_GENERIC:
7070                 if (filter_op != RTE_ETH_FILTER_GET)
7071                         return -EINVAL;
7072                 *(const void **)arg = &ixgbe_flow_ops;
7073                 break;
7074         default:
7075                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7076                                                         filter_type);
7077                 ret = -EINVAL;
7078                 break;
7079         }
7080
7081         return ret;
7082 }
7083
7084 static u8 *
7085 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7086                         u8 **mc_addr_ptr, u32 *vmdq)
7087 {
7088         u8 *mc_addr;
7089
7090         *vmdq = 0;
7091         mc_addr = *mc_addr_ptr;
7092         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7093         return mc_addr;
7094 }
7095
7096 static int
7097 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7098                           struct rte_ether_addr *mc_addr_set,
7099                           uint32_t nb_mc_addr)
7100 {
7101         struct ixgbe_hw *hw;
7102         u8 *mc_addr_list;
7103
7104         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7105         mc_addr_list = (u8 *)mc_addr_set;
7106         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7107                                          ixgbe_dev_addr_list_itr, TRUE);
7108 }
7109
7110 static uint64_t
7111 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7112 {
7113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7114         uint64_t systime_cycles;
7115
7116         switch (hw->mac.type) {
7117         case ixgbe_mac_X550:
7118         case ixgbe_mac_X550EM_x:
7119         case ixgbe_mac_X550EM_a:
7120                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7121                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7122                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7123                                 * NSEC_PER_SEC;
7124                 break;
7125         default:
7126                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7127                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7128                                 << 32;
7129         }
7130
7131         return systime_cycles;
7132 }
7133
7134 static uint64_t
7135 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7136 {
7137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7138         uint64_t rx_tstamp_cycles;
7139
7140         switch (hw->mac.type) {
7141         case ixgbe_mac_X550:
7142         case ixgbe_mac_X550EM_x:
7143         case ixgbe_mac_X550EM_a:
7144                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7145                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7146                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7147                                 * NSEC_PER_SEC;
7148                 break;
7149         default:
7150                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7151                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7152                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7153                                 << 32;
7154         }
7155
7156         return rx_tstamp_cycles;
7157 }
7158
7159 static uint64_t
7160 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7161 {
7162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7163         uint64_t tx_tstamp_cycles;
7164
7165         switch (hw->mac.type) {
7166         case ixgbe_mac_X550:
7167         case ixgbe_mac_X550EM_x:
7168         case ixgbe_mac_X550EM_a:
7169                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7170                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7171                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7172                                 * NSEC_PER_SEC;
7173                 break;
7174         default:
7175                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7176                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7177                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7178                                 << 32;
7179         }
7180
7181         return tx_tstamp_cycles;
7182 }
7183
7184 static void
7185 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7186 {
7187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7188         struct ixgbe_adapter *adapter = dev->data->dev_private;
7189         struct rte_eth_link link;
7190         uint32_t incval = 0;
7191         uint32_t shift = 0;
7192
7193         /* Get current link speed. */
7194         ixgbe_dev_link_update(dev, 1);
7195         rte_eth_linkstatus_get(dev, &link);
7196
7197         switch (link.link_speed) {
7198         case ETH_SPEED_NUM_100M:
7199                 incval = IXGBE_INCVAL_100;
7200                 shift = IXGBE_INCVAL_SHIFT_100;
7201                 break;
7202         case ETH_SPEED_NUM_1G:
7203                 incval = IXGBE_INCVAL_1GB;
7204                 shift = IXGBE_INCVAL_SHIFT_1GB;
7205                 break;
7206         case ETH_SPEED_NUM_10G:
7207         default:
7208                 incval = IXGBE_INCVAL_10GB;
7209                 shift = IXGBE_INCVAL_SHIFT_10GB;
7210                 break;
7211         }
7212
7213         switch (hw->mac.type) {
7214         case ixgbe_mac_X550:
7215         case ixgbe_mac_X550EM_x:
7216         case ixgbe_mac_X550EM_a:
7217                 /* Independent of link speed. */
7218                 incval = 1;
7219                 /* Cycles read will be interpreted as ns. */
7220                 shift = 0;
7221                 /* Fall-through */
7222         case ixgbe_mac_X540:
7223                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7224                 break;
7225         case ixgbe_mac_82599EB:
7226                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7227                 shift -= IXGBE_INCVAL_SHIFT_82599;
7228                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7229                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7230                 break;
7231         default:
7232                 /* Not supported. */
7233                 return;
7234         }
7235
7236         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7237         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7238         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7239
7240         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7241         adapter->systime_tc.cc_shift = shift;
7242         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7243
7244         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7245         adapter->rx_tstamp_tc.cc_shift = shift;
7246         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7247
7248         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7249         adapter->tx_tstamp_tc.cc_shift = shift;
7250         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7251 }
7252
7253 static int
7254 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7255 {
7256         struct ixgbe_adapter *adapter = dev->data->dev_private;
7257
7258         adapter->systime_tc.nsec += delta;
7259         adapter->rx_tstamp_tc.nsec += delta;
7260         adapter->tx_tstamp_tc.nsec += delta;
7261
7262         return 0;
7263 }
7264
7265 static int
7266 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7267 {
7268         uint64_t ns;
7269         struct ixgbe_adapter *adapter = dev->data->dev_private;
7270
7271         ns = rte_timespec_to_ns(ts);
7272         /* Set the timecounters to a new value. */
7273         adapter->systime_tc.nsec = ns;
7274         adapter->rx_tstamp_tc.nsec = ns;
7275         adapter->tx_tstamp_tc.nsec = ns;
7276
7277         return 0;
7278 }
7279
7280 static int
7281 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7282 {
7283         uint64_t ns, systime_cycles;
7284         struct ixgbe_adapter *adapter = dev->data->dev_private;
7285
7286         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7287         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7288         *ts = rte_ns_to_timespec(ns);
7289
7290         return 0;
7291 }
7292
7293 static int
7294 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7295 {
7296         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7297         uint32_t tsync_ctl;
7298         uint32_t tsauxc;
7299
7300         /* Stop the timesync system time. */
7301         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7302         /* Reset the timesync system time value. */
7303         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7304         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7305
7306         /* Enable system time for platforms where it isn't on by default. */
7307         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7308         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7309         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7310
7311         ixgbe_start_timecounters(dev);
7312
7313         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7314         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7315                         (RTE_ETHER_TYPE_1588 |
7316                          IXGBE_ETQF_FILTER_EN |
7317                          IXGBE_ETQF_1588));
7318
7319         /* Enable timestamping of received PTP packets. */
7320         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7321         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7322         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7323
7324         /* Enable timestamping of transmitted PTP packets. */
7325         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7326         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7327         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7328
7329         IXGBE_WRITE_FLUSH(hw);
7330
7331         return 0;
7332 }
7333
7334 static int
7335 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7336 {
7337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7338         uint32_t tsync_ctl;
7339
7340         /* Disable timestamping of transmitted PTP packets. */
7341         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7342         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7343         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7344
7345         /* Disable timestamping of received PTP packets. */
7346         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7347         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7348         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7349
7350         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7351         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7352
7353         /* Stop incrementating the System Time registers. */
7354         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7355
7356         return 0;
7357 }
7358
7359 static int
7360 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7361                                  struct timespec *timestamp,
7362                                  uint32_t flags __rte_unused)
7363 {
7364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7365         struct ixgbe_adapter *adapter = dev->data->dev_private;
7366         uint32_t tsync_rxctl;
7367         uint64_t rx_tstamp_cycles;
7368         uint64_t ns;
7369
7370         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7371         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7372                 return -EINVAL;
7373
7374         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7375         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7376         *timestamp = rte_ns_to_timespec(ns);
7377
7378         return  0;
7379 }
7380
7381 static int
7382 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7383                                  struct timespec *timestamp)
7384 {
7385         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7386         struct ixgbe_adapter *adapter = dev->data->dev_private;
7387         uint32_t tsync_txctl;
7388         uint64_t tx_tstamp_cycles;
7389         uint64_t ns;
7390
7391         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7392         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7393                 return -EINVAL;
7394
7395         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7396         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7397         *timestamp = rte_ns_to_timespec(ns);
7398
7399         return 0;
7400 }
7401
7402 static int
7403 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7404 {
7405         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7406         int count = 0;
7407         int g_ind = 0;
7408         const struct reg_info *reg_group;
7409         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7410                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7411
7412         while ((reg_group = reg_set[g_ind++]))
7413                 count += ixgbe_regs_group_count(reg_group);
7414
7415         return count;
7416 }
7417
7418 static int
7419 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7420 {
7421         int count = 0;
7422         int g_ind = 0;
7423         const struct reg_info *reg_group;
7424
7425         while ((reg_group = ixgbevf_regs[g_ind++]))
7426                 count += ixgbe_regs_group_count(reg_group);
7427
7428         return count;
7429 }
7430
7431 static int
7432 ixgbe_get_regs(struct rte_eth_dev *dev,
7433               struct rte_dev_reg_info *regs)
7434 {
7435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7436         uint32_t *data = regs->data;
7437         int g_ind = 0;
7438         int count = 0;
7439         const struct reg_info *reg_group;
7440         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7441                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7442
7443         if (data == NULL) {
7444                 regs->length = ixgbe_get_reg_length(dev);
7445                 regs->width = sizeof(uint32_t);
7446                 return 0;
7447         }
7448
7449         /* Support only full register dump */
7450         if ((regs->length == 0) ||
7451             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7452                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7453                         hw->device_id;
7454                 while ((reg_group = reg_set[g_ind++]))
7455                         count += ixgbe_read_regs_group(dev, &data[count],
7456                                 reg_group);
7457                 return 0;
7458         }
7459
7460         return -ENOTSUP;
7461 }
7462
7463 static int
7464 ixgbevf_get_regs(struct rte_eth_dev *dev,
7465                 struct rte_dev_reg_info *regs)
7466 {
7467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7468         uint32_t *data = regs->data;
7469         int g_ind = 0;
7470         int count = 0;
7471         const struct reg_info *reg_group;
7472
7473         if (data == NULL) {
7474                 regs->length = ixgbevf_get_reg_length(dev);
7475                 regs->width = sizeof(uint32_t);
7476                 return 0;
7477         }
7478
7479         /* Support only full register dump */
7480         if ((regs->length == 0) ||
7481             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7482                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7483                         hw->device_id;
7484                 while ((reg_group = ixgbevf_regs[g_ind++]))
7485                         count += ixgbe_read_regs_group(dev, &data[count],
7486                                                       reg_group);
7487                 return 0;
7488         }
7489
7490         return -ENOTSUP;
7491 }
7492
7493 static int
7494 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7495 {
7496         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7497
7498         /* Return unit is byte count */
7499         return hw->eeprom.word_size * 2;
7500 }
7501
7502 static int
7503 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7504                 struct rte_dev_eeprom_info *in_eeprom)
7505 {
7506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7508         uint16_t *data = in_eeprom->data;
7509         int first, length;
7510
7511         first = in_eeprom->offset >> 1;
7512         length = in_eeprom->length >> 1;
7513         if ((first > hw->eeprom.word_size) ||
7514             ((first + length) > hw->eeprom.word_size))
7515                 return -EINVAL;
7516
7517         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7518
7519         return eeprom->ops.read_buffer(hw, first, length, data);
7520 }
7521
7522 static int
7523 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7524                 struct rte_dev_eeprom_info *in_eeprom)
7525 {
7526         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7527         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7528         uint16_t *data = in_eeprom->data;
7529         int first, length;
7530
7531         first = in_eeprom->offset >> 1;
7532         length = in_eeprom->length >> 1;
7533         if ((first > hw->eeprom.word_size) ||
7534             ((first + length) > hw->eeprom.word_size))
7535                 return -EINVAL;
7536
7537         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7538
7539         return eeprom->ops.write_buffer(hw,  first, length, data);
7540 }
7541
7542 static int
7543 ixgbe_get_module_info(struct rte_eth_dev *dev,
7544                       struct rte_eth_dev_module_info *modinfo)
7545 {
7546         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7547         uint32_t status;
7548         uint8_t sff8472_rev, addr_mode;
7549         bool page_swap = false;
7550
7551         /* Check whether we support SFF-8472 or not */
7552         status = hw->phy.ops.read_i2c_eeprom(hw,
7553                                              IXGBE_SFF_SFF_8472_COMP,
7554                                              &sff8472_rev);
7555         if (status != 0)
7556                 return -EIO;
7557
7558         /* addressing mode is not supported */
7559         status = hw->phy.ops.read_i2c_eeprom(hw,
7560                                              IXGBE_SFF_SFF_8472_SWAP,
7561                                              &addr_mode);
7562         if (status != 0)
7563                 return -EIO;
7564
7565         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7566                 PMD_DRV_LOG(ERR,
7567                             "Address change required to access page 0xA2, "
7568                             "but not supported. Please report the module "
7569                             "type to the driver maintainers.");
7570                 page_swap = true;
7571         }
7572
7573         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7574                 /* We have a SFP, but it does not support SFF-8472 */
7575                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7576                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7577         } else {
7578                 /* We have a SFP which supports a revision of SFF-8472. */
7579                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7580                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7581         }
7582
7583         return 0;
7584 }
7585
7586 static int
7587 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7588                         struct rte_dev_eeprom_info *info)
7589 {
7590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7591         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7592         uint8_t databyte = 0xFF;
7593         uint8_t *data = info->data;
7594         uint32_t i = 0;
7595
7596         if (info->length == 0)
7597                 return -EINVAL;
7598
7599         for (i = info->offset; i < info->offset + info->length; i++) {
7600                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7601                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7602                 else
7603                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7604
7605                 if (status != 0)
7606                         return -EIO;
7607
7608                 data[i - info->offset] = databyte;
7609         }
7610
7611         return 0;
7612 }
7613
7614 uint16_t
7615 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7616         switch (mac_type) {
7617         case ixgbe_mac_X550:
7618         case ixgbe_mac_X550EM_x:
7619         case ixgbe_mac_X550EM_a:
7620                 return ETH_RSS_RETA_SIZE_512;
7621         case ixgbe_mac_X550_vf:
7622         case ixgbe_mac_X550EM_x_vf:
7623         case ixgbe_mac_X550EM_a_vf:
7624                 return ETH_RSS_RETA_SIZE_64;
7625         case ixgbe_mac_X540_vf:
7626         case ixgbe_mac_82599_vf:
7627                 return 0;
7628         default:
7629                 return ETH_RSS_RETA_SIZE_128;
7630         }
7631 }
7632
7633 uint32_t
7634 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7635         switch (mac_type) {
7636         case ixgbe_mac_X550:
7637         case ixgbe_mac_X550EM_x:
7638         case ixgbe_mac_X550EM_a:
7639                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7640                         return IXGBE_RETA(reta_idx >> 2);
7641                 else
7642                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7643         case ixgbe_mac_X550_vf:
7644         case ixgbe_mac_X550EM_x_vf:
7645         case ixgbe_mac_X550EM_a_vf:
7646                 return IXGBE_VFRETA(reta_idx >> 2);
7647         default:
7648                 return IXGBE_RETA(reta_idx >> 2);
7649         }
7650 }
7651
7652 uint32_t
7653 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7654         switch (mac_type) {
7655         case ixgbe_mac_X550_vf:
7656         case ixgbe_mac_X550EM_x_vf:
7657         case ixgbe_mac_X550EM_a_vf:
7658                 return IXGBE_VFMRQC;
7659         default:
7660                 return IXGBE_MRQC;
7661         }
7662 }
7663
7664 uint32_t
7665 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7666         switch (mac_type) {
7667         case ixgbe_mac_X550_vf:
7668         case ixgbe_mac_X550EM_x_vf:
7669         case ixgbe_mac_X550EM_a_vf:
7670                 return IXGBE_VFRSSRK(i);
7671         default:
7672                 return IXGBE_RSSRK(i);
7673         }
7674 }
7675
7676 bool
7677 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7678         switch (mac_type) {
7679         case ixgbe_mac_82599_vf:
7680         case ixgbe_mac_X540_vf:
7681                 return 0;
7682         default:
7683                 return 1;
7684         }
7685 }
7686
7687 static int
7688 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7689                         struct rte_eth_dcb_info *dcb_info)
7690 {
7691         struct ixgbe_dcb_config *dcb_config =
7692                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7693         struct ixgbe_dcb_tc_config *tc;
7694         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7695         uint8_t nb_tcs;
7696         uint8_t i, j;
7697
7698         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7699                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7700         else
7701                 dcb_info->nb_tcs = 1;
7702
7703         tc_queue = &dcb_info->tc_queue;
7704         nb_tcs = dcb_info->nb_tcs;
7705
7706         if (dcb_config->vt_mode) { /* vt is enabled*/
7707                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7708                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7709                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7710                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7711                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7712                         for (j = 0; j < nb_tcs; j++) {
7713                                 tc_queue->tc_rxq[0][j].base = j;
7714                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7715                                 tc_queue->tc_txq[0][j].base = j;
7716                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7717                         }
7718                 } else {
7719                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7720                                 for (j = 0; j < nb_tcs; j++) {
7721                                         tc_queue->tc_rxq[i][j].base =
7722                                                 i * nb_tcs + j;
7723                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7724                                         tc_queue->tc_txq[i][j].base =
7725                                                 i * nb_tcs + j;
7726                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7727                                 }
7728                         }
7729                 }
7730         } else { /* vt is disabled*/
7731                 struct rte_eth_dcb_rx_conf *rx_conf =
7732                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7733                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7734                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7735                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7736                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7737                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7738                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7739                         }
7740                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7741                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7742                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7743                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7744                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7745                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7746                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7747                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7748                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7749                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7750                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7751                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7752                         }
7753                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7754                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7755                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7756                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7757                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7758                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7759                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7760                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7761                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7762                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7763                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7764                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7765                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7766                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7767                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7768                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7769                 }
7770         }
7771         for (i = 0; i < dcb_info->nb_tcs; i++) {
7772                 tc = &dcb_config->tc_config[i];
7773                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7774         }
7775         return 0;
7776 }
7777
7778 /* Update e-tag ether type */
7779 static int
7780 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7781                             uint16_t ether_type)
7782 {
7783         uint32_t etag_etype;
7784
7785         if (hw->mac.type != ixgbe_mac_X550 &&
7786             hw->mac.type != ixgbe_mac_X550EM_x &&
7787             hw->mac.type != ixgbe_mac_X550EM_a) {
7788                 return -ENOTSUP;
7789         }
7790
7791         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7792         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7793         etag_etype |= ether_type;
7794         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7795         IXGBE_WRITE_FLUSH(hw);
7796
7797         return 0;
7798 }
7799
7800 /* Config l2 tunnel ether type */
7801 static int
7802 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7803                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7804 {
7805         int ret = 0;
7806         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7807         struct ixgbe_l2_tn_info *l2_tn_info =
7808                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7809
7810         if (l2_tunnel == NULL)
7811                 return -EINVAL;
7812
7813         switch (l2_tunnel->l2_tunnel_type) {
7814         case RTE_L2_TUNNEL_TYPE_E_TAG:
7815                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7816                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7817                 break;
7818         default:
7819                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7820                 ret = -EINVAL;
7821                 break;
7822         }
7823
7824         return ret;
7825 }
7826
7827 /* Enable e-tag tunnel */
7828 static int
7829 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7830 {
7831         uint32_t etag_etype;
7832
7833         if (hw->mac.type != ixgbe_mac_X550 &&
7834             hw->mac.type != ixgbe_mac_X550EM_x &&
7835             hw->mac.type != ixgbe_mac_X550EM_a) {
7836                 return -ENOTSUP;
7837         }
7838
7839         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7840         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7841         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7842         IXGBE_WRITE_FLUSH(hw);
7843
7844         return 0;
7845 }
7846
7847 /* Enable l2 tunnel */
7848 static int
7849 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7850                            enum rte_eth_tunnel_type l2_tunnel_type)
7851 {
7852         int ret = 0;
7853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7854         struct ixgbe_l2_tn_info *l2_tn_info =
7855                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7856
7857         switch (l2_tunnel_type) {
7858         case RTE_L2_TUNNEL_TYPE_E_TAG:
7859                 l2_tn_info->e_tag_en = TRUE;
7860                 ret = ixgbe_e_tag_enable(hw);
7861                 break;
7862         default:
7863                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7864                 ret = -EINVAL;
7865                 break;
7866         }
7867
7868         return ret;
7869 }
7870
7871 /* Disable e-tag tunnel */
7872 static int
7873 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7874 {
7875         uint32_t etag_etype;
7876
7877         if (hw->mac.type != ixgbe_mac_X550 &&
7878             hw->mac.type != ixgbe_mac_X550EM_x &&
7879             hw->mac.type != ixgbe_mac_X550EM_a) {
7880                 return -ENOTSUP;
7881         }
7882
7883         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7884         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7885         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7886         IXGBE_WRITE_FLUSH(hw);
7887
7888         return 0;
7889 }
7890
7891 /* Disable l2 tunnel */
7892 static int
7893 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7894                             enum rte_eth_tunnel_type l2_tunnel_type)
7895 {
7896         int ret = 0;
7897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7898         struct ixgbe_l2_tn_info *l2_tn_info =
7899                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7900
7901         switch (l2_tunnel_type) {
7902         case RTE_L2_TUNNEL_TYPE_E_TAG:
7903                 l2_tn_info->e_tag_en = FALSE;
7904                 ret = ixgbe_e_tag_disable(hw);
7905                 break;
7906         default:
7907                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7908                 ret = -EINVAL;
7909                 break;
7910         }
7911
7912         return ret;
7913 }
7914
7915 static int
7916 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7917                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7918 {
7919         int ret = 0;
7920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7921         uint32_t i, rar_entries;
7922         uint32_t rar_low, rar_high;
7923
7924         if (hw->mac.type != ixgbe_mac_X550 &&
7925             hw->mac.type != ixgbe_mac_X550EM_x &&
7926             hw->mac.type != ixgbe_mac_X550EM_a) {
7927                 return -ENOTSUP;
7928         }
7929
7930         rar_entries = ixgbe_get_num_rx_addrs(hw);
7931
7932         for (i = 1; i < rar_entries; i++) {
7933                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7934                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7935                 if ((rar_high & IXGBE_RAH_AV) &&
7936                     (rar_high & IXGBE_RAH_ADTYPE) &&
7937                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7938                      l2_tunnel->tunnel_id)) {
7939                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7940                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7941
7942                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7943
7944                         return ret;
7945                 }
7946         }
7947
7948         return ret;
7949 }
7950
7951 static int
7952 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7953                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7954 {
7955         int ret = 0;
7956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7957         uint32_t i, rar_entries;
7958         uint32_t rar_low, rar_high;
7959
7960         if (hw->mac.type != ixgbe_mac_X550 &&
7961             hw->mac.type != ixgbe_mac_X550EM_x &&
7962             hw->mac.type != ixgbe_mac_X550EM_a) {
7963                 return -ENOTSUP;
7964         }
7965
7966         /* One entry for one tunnel. Try to remove potential existing entry. */
7967         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7968
7969         rar_entries = ixgbe_get_num_rx_addrs(hw);
7970
7971         for (i = 1; i < rar_entries; i++) {
7972                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7973                 if (rar_high & IXGBE_RAH_AV) {
7974                         continue;
7975                 } else {
7976                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7977                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7978                         rar_low = l2_tunnel->tunnel_id;
7979
7980                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7981                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7982
7983                         return ret;
7984                 }
7985         }
7986
7987         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7988                      " Please remove a rule before adding a new one.");
7989         return -EINVAL;
7990 }
7991
7992 static inline struct ixgbe_l2_tn_filter *
7993 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7994                           struct ixgbe_l2_tn_key *key)
7995 {
7996         int ret;
7997
7998         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7999         if (ret < 0)
8000                 return NULL;
8001
8002         return l2_tn_info->hash_map[ret];
8003 }
8004
8005 static inline int
8006 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8007                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8008 {
8009         int ret;
8010
8011         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8012                                &l2_tn_filter->key);
8013
8014         if (ret < 0) {
8015                 PMD_DRV_LOG(ERR,
8016                             "Failed to insert L2 tunnel filter"
8017                             " to hash table %d!",
8018                             ret);
8019                 return ret;
8020         }
8021
8022         l2_tn_info->hash_map[ret] = l2_tn_filter;
8023
8024         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8025
8026         return 0;
8027 }
8028
8029 static inline int
8030 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8031                           struct ixgbe_l2_tn_key *key)
8032 {
8033         int ret;
8034         struct ixgbe_l2_tn_filter *l2_tn_filter;
8035
8036         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8037
8038         if (ret < 0) {
8039                 PMD_DRV_LOG(ERR,
8040                             "No such L2 tunnel filter to delete %d!",
8041                             ret);
8042                 return ret;
8043         }
8044
8045         l2_tn_filter = l2_tn_info->hash_map[ret];
8046         l2_tn_info->hash_map[ret] = NULL;
8047
8048         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8049         rte_free(l2_tn_filter);
8050
8051         return 0;
8052 }
8053
8054 /* Add l2 tunnel filter */
8055 int
8056 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8057                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8058                                bool restore)
8059 {
8060         int ret;
8061         struct ixgbe_l2_tn_info *l2_tn_info =
8062                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8063         struct ixgbe_l2_tn_key key;
8064         struct ixgbe_l2_tn_filter *node;
8065
8066         if (!restore) {
8067                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8068                 key.tn_id = l2_tunnel->tunnel_id;
8069
8070                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8071
8072                 if (node) {
8073                         PMD_DRV_LOG(ERR,
8074                                     "The L2 tunnel filter already exists!");
8075                         return -EINVAL;
8076                 }
8077
8078                 node = rte_zmalloc("ixgbe_l2_tn",
8079                                    sizeof(struct ixgbe_l2_tn_filter),
8080                                    0);
8081                 if (!node)
8082                         return -ENOMEM;
8083
8084                 rte_memcpy(&node->key,
8085                                  &key,
8086                                  sizeof(struct ixgbe_l2_tn_key));
8087                 node->pool = l2_tunnel->pool;
8088                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8089                 if (ret < 0) {
8090                         rte_free(node);
8091                         return ret;
8092                 }
8093         }
8094
8095         switch (l2_tunnel->l2_tunnel_type) {
8096         case RTE_L2_TUNNEL_TYPE_E_TAG:
8097                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8098                 break;
8099         default:
8100                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8101                 ret = -EINVAL;
8102                 break;
8103         }
8104
8105         if ((!restore) && (ret < 0))
8106                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8107
8108         return ret;
8109 }
8110
8111 /* Delete l2 tunnel filter */
8112 int
8113 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8114                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8115 {
8116         int ret;
8117         struct ixgbe_l2_tn_info *l2_tn_info =
8118                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8119         struct ixgbe_l2_tn_key key;
8120
8121         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8122         key.tn_id = l2_tunnel->tunnel_id;
8123         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8124         if (ret < 0)
8125                 return ret;
8126
8127         switch (l2_tunnel->l2_tunnel_type) {
8128         case RTE_L2_TUNNEL_TYPE_E_TAG:
8129                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8130                 break;
8131         default:
8132                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8133                 ret = -EINVAL;
8134                 break;
8135         }
8136
8137         return ret;
8138 }
8139
8140 /**
8141  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8142  * @dev: pointer to rte_eth_dev structure
8143  * @filter_op:operation will be taken.
8144  * @arg: a pointer to specific structure corresponding to the filter_op
8145  */
8146 static int
8147 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8148                                   enum rte_filter_op filter_op,
8149                                   void *arg)
8150 {
8151         int ret;
8152
8153         if (filter_op == RTE_ETH_FILTER_NOP)
8154                 return 0;
8155
8156         if (arg == NULL) {
8157                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8158                             filter_op);
8159                 return -EINVAL;
8160         }
8161
8162         switch (filter_op) {
8163         case RTE_ETH_FILTER_ADD:
8164                 ret = ixgbe_dev_l2_tunnel_filter_add
8165                         (dev,
8166                          (struct rte_eth_l2_tunnel_conf *)arg,
8167                          FALSE);
8168                 break;
8169         case RTE_ETH_FILTER_DELETE:
8170                 ret = ixgbe_dev_l2_tunnel_filter_del
8171                         (dev,
8172                          (struct rte_eth_l2_tunnel_conf *)arg);
8173                 break;
8174         default:
8175                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8176                 ret = -EINVAL;
8177                 break;
8178         }
8179         return ret;
8180 }
8181
8182 static int
8183 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8184 {
8185         int ret = 0;
8186         uint32_t ctrl;
8187         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8188
8189         if (hw->mac.type != ixgbe_mac_X550 &&
8190             hw->mac.type != ixgbe_mac_X550EM_x &&
8191             hw->mac.type != ixgbe_mac_X550EM_a) {
8192                 return -ENOTSUP;
8193         }
8194
8195         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8196         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8197         if (en)
8198                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8199         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8200
8201         return ret;
8202 }
8203
8204 /* Enable l2 tunnel forwarding */
8205 static int
8206 ixgbe_dev_l2_tunnel_forwarding_enable
8207         (struct rte_eth_dev *dev,
8208          enum rte_eth_tunnel_type l2_tunnel_type)
8209 {
8210         struct ixgbe_l2_tn_info *l2_tn_info =
8211                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8212         int ret = 0;
8213
8214         switch (l2_tunnel_type) {
8215         case RTE_L2_TUNNEL_TYPE_E_TAG:
8216                 l2_tn_info->e_tag_fwd_en = TRUE;
8217                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8218                 break;
8219         default:
8220                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8221                 ret = -EINVAL;
8222                 break;
8223         }
8224
8225         return ret;
8226 }
8227
8228 /* Disable l2 tunnel forwarding */
8229 static int
8230 ixgbe_dev_l2_tunnel_forwarding_disable
8231         (struct rte_eth_dev *dev,
8232          enum rte_eth_tunnel_type l2_tunnel_type)
8233 {
8234         struct ixgbe_l2_tn_info *l2_tn_info =
8235                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8236         int ret = 0;
8237
8238         switch (l2_tunnel_type) {
8239         case RTE_L2_TUNNEL_TYPE_E_TAG:
8240                 l2_tn_info->e_tag_fwd_en = FALSE;
8241                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8242                 break;
8243         default:
8244                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8245                 ret = -EINVAL;
8246                 break;
8247         }
8248
8249         return ret;
8250 }
8251
8252 static int
8253 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8254                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8255                              bool en)
8256 {
8257         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8258         int ret = 0;
8259         uint32_t vmtir, vmvir;
8260         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8261
8262         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8263                 PMD_DRV_LOG(ERR,
8264                             "VF id %u should be less than %u",
8265                             l2_tunnel->vf_id,
8266                             pci_dev->max_vfs);
8267                 return -EINVAL;
8268         }
8269
8270         if (hw->mac.type != ixgbe_mac_X550 &&
8271             hw->mac.type != ixgbe_mac_X550EM_x &&
8272             hw->mac.type != ixgbe_mac_X550EM_a) {
8273                 return -ENOTSUP;
8274         }
8275
8276         if (en)
8277                 vmtir = l2_tunnel->tunnel_id;
8278         else
8279                 vmtir = 0;
8280
8281         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8282
8283         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8284         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8285         if (en)
8286                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8287         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8288
8289         return ret;
8290 }
8291
8292 /* Enable l2 tunnel tag insertion */
8293 static int
8294 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8295                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8296 {
8297         int ret = 0;
8298
8299         switch (l2_tunnel->l2_tunnel_type) {
8300         case RTE_L2_TUNNEL_TYPE_E_TAG:
8301                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8302                 break;
8303         default:
8304                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8305                 ret = -EINVAL;
8306                 break;
8307         }
8308
8309         return ret;
8310 }
8311
8312 /* Disable l2 tunnel tag insertion */
8313 static int
8314 ixgbe_dev_l2_tunnel_insertion_disable
8315         (struct rte_eth_dev *dev,
8316          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8317 {
8318         int ret = 0;
8319
8320         switch (l2_tunnel->l2_tunnel_type) {
8321         case RTE_L2_TUNNEL_TYPE_E_TAG:
8322                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8323                 break;
8324         default:
8325                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8326                 ret = -EINVAL;
8327                 break;
8328         }
8329
8330         return ret;
8331 }
8332
8333 static int
8334 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8335                              bool en)
8336 {
8337         int ret = 0;
8338         uint32_t qde;
8339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8340
8341         if (hw->mac.type != ixgbe_mac_X550 &&
8342             hw->mac.type != ixgbe_mac_X550EM_x &&
8343             hw->mac.type != ixgbe_mac_X550EM_a) {
8344                 return -ENOTSUP;
8345         }
8346
8347         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8348         if (en)
8349                 qde |= IXGBE_QDE_STRIP_TAG;
8350         else
8351                 qde &= ~IXGBE_QDE_STRIP_TAG;
8352         qde &= ~IXGBE_QDE_READ;
8353         qde |= IXGBE_QDE_WRITE;
8354         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8355
8356         return ret;
8357 }
8358
8359 /* Enable l2 tunnel tag stripping */
8360 static int
8361 ixgbe_dev_l2_tunnel_stripping_enable
8362         (struct rte_eth_dev *dev,
8363          enum rte_eth_tunnel_type l2_tunnel_type)
8364 {
8365         int ret = 0;
8366
8367         switch (l2_tunnel_type) {
8368         case RTE_L2_TUNNEL_TYPE_E_TAG:
8369                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8370                 break;
8371         default:
8372                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8373                 ret = -EINVAL;
8374                 break;
8375         }
8376
8377         return ret;
8378 }
8379
8380 /* Disable l2 tunnel tag stripping */
8381 static int
8382 ixgbe_dev_l2_tunnel_stripping_disable
8383         (struct rte_eth_dev *dev,
8384          enum rte_eth_tunnel_type l2_tunnel_type)
8385 {
8386         int ret = 0;
8387
8388         switch (l2_tunnel_type) {
8389         case RTE_L2_TUNNEL_TYPE_E_TAG:
8390                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8391                 break;
8392         default:
8393                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8394                 ret = -EINVAL;
8395                 break;
8396         }
8397
8398         return ret;
8399 }
8400
8401 /* Enable/disable l2 tunnel offload functions */
8402 static int
8403 ixgbe_dev_l2_tunnel_offload_set
8404         (struct rte_eth_dev *dev,
8405          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8406          uint32_t mask,
8407          uint8_t en)
8408 {
8409         int ret = 0;
8410
8411         if (l2_tunnel == NULL)
8412                 return -EINVAL;
8413
8414         ret = -EINVAL;
8415         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8416                 if (en)
8417                         ret = ixgbe_dev_l2_tunnel_enable(
8418                                 dev,
8419                                 l2_tunnel->l2_tunnel_type);
8420                 else
8421                         ret = ixgbe_dev_l2_tunnel_disable(
8422                                 dev,
8423                                 l2_tunnel->l2_tunnel_type);
8424         }
8425
8426         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8427                 if (en)
8428                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8429                                 dev,
8430                                 l2_tunnel);
8431                 else
8432                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8433                                 dev,
8434                                 l2_tunnel);
8435         }
8436
8437         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8438                 if (en)
8439                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8440                                 dev,
8441                                 l2_tunnel->l2_tunnel_type);
8442                 else
8443                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8444                                 dev,
8445                                 l2_tunnel->l2_tunnel_type);
8446         }
8447
8448         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8449                 if (en)
8450                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8451                                 dev,
8452                                 l2_tunnel->l2_tunnel_type);
8453                 else
8454                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8455                                 dev,
8456                                 l2_tunnel->l2_tunnel_type);
8457         }
8458
8459         return ret;
8460 }
8461
8462 static int
8463 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8464                         uint16_t port)
8465 {
8466         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8467         IXGBE_WRITE_FLUSH(hw);
8468
8469         return 0;
8470 }
8471
8472 /* There's only one register for VxLAN UDP port.
8473  * So, we cannot add several ports. Will update it.
8474  */
8475 static int
8476 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8477                      uint16_t port)
8478 {
8479         if (port == 0) {
8480                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8481                 return -EINVAL;
8482         }
8483
8484         return ixgbe_update_vxlan_port(hw, port);
8485 }
8486
8487 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8488  * UDP port, it must have a value.
8489  * So, will reset it to the original value 0.
8490  */
8491 static int
8492 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8493                      uint16_t port)
8494 {
8495         uint16_t cur_port;
8496
8497         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8498
8499         if (cur_port != port) {
8500                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8501                 return -EINVAL;
8502         }
8503
8504         return ixgbe_update_vxlan_port(hw, 0);
8505 }
8506
8507 /* Add UDP tunneling port */
8508 static int
8509 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8510                               struct rte_eth_udp_tunnel *udp_tunnel)
8511 {
8512         int ret = 0;
8513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8514
8515         if (hw->mac.type != ixgbe_mac_X550 &&
8516             hw->mac.type != ixgbe_mac_X550EM_x &&
8517             hw->mac.type != ixgbe_mac_X550EM_a) {
8518                 return -ENOTSUP;
8519         }
8520
8521         if (udp_tunnel == NULL)
8522                 return -EINVAL;
8523
8524         switch (udp_tunnel->prot_type) {
8525         case RTE_TUNNEL_TYPE_VXLAN:
8526                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8527                 break;
8528
8529         case RTE_TUNNEL_TYPE_GENEVE:
8530         case RTE_TUNNEL_TYPE_TEREDO:
8531                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8532                 ret = -EINVAL;
8533                 break;
8534
8535         default:
8536                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8537                 ret = -EINVAL;
8538                 break;
8539         }
8540
8541         return ret;
8542 }
8543
8544 /* Remove UDP tunneling port */
8545 static int
8546 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8547                               struct rte_eth_udp_tunnel *udp_tunnel)
8548 {
8549         int ret = 0;
8550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8551
8552         if (hw->mac.type != ixgbe_mac_X550 &&
8553             hw->mac.type != ixgbe_mac_X550EM_x &&
8554             hw->mac.type != ixgbe_mac_X550EM_a) {
8555                 return -ENOTSUP;
8556         }
8557
8558         if (udp_tunnel == NULL)
8559                 return -EINVAL;
8560
8561         switch (udp_tunnel->prot_type) {
8562         case RTE_TUNNEL_TYPE_VXLAN:
8563                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8564                 break;
8565         case RTE_TUNNEL_TYPE_GENEVE:
8566         case RTE_TUNNEL_TYPE_TEREDO:
8567                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8568                 ret = -EINVAL;
8569                 break;
8570         default:
8571                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8572                 ret = -EINVAL;
8573                 break;
8574         }
8575
8576         return ret;
8577 }
8578
8579 static int
8580 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8581 {
8582         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8583         int ret;
8584
8585         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8586         case IXGBE_SUCCESS:
8587                 ret = 0;
8588                 break;
8589         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8590                 ret = -ENOTSUP;
8591                 break;
8592         default:
8593                 ret = -EAGAIN;
8594                 break;
8595         }
8596
8597         return ret;
8598 }
8599
8600 static int
8601 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8602 {
8603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8604         int ret;
8605
8606         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8607         case IXGBE_SUCCESS:
8608                 ret = 0;
8609                 break;
8610         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8611                 ret = -ENOTSUP;
8612                 break;
8613         default:
8614                 ret = -EAGAIN;
8615                 break;
8616         }
8617
8618         return ret;
8619 }
8620
8621 static int
8622 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8623 {
8624         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8625         int ret;
8626         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8627
8628         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8629         case IXGBE_SUCCESS:
8630                 ret = 0;
8631                 break;
8632         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8633                 ret = -ENOTSUP;
8634                 break;
8635         default:
8636                 ret = -EAGAIN;
8637                 break;
8638         }
8639
8640         return ret;
8641 }
8642
8643 static int
8644 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8645 {
8646         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8647         int ret;
8648
8649         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8650         case IXGBE_SUCCESS:
8651                 ret = 0;
8652                 break;
8653         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8654                 ret = -ENOTSUP;
8655                 break;
8656         default:
8657                 ret = -EAGAIN;
8658                 break;
8659         }
8660
8661         return ret;
8662 }
8663
8664 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8665 {
8666         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8667         u32 in_msg = 0;
8668
8669         /* peek the message first */
8670         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8671
8672         /* PF reset VF event */
8673         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8674                 /* dummy mbx read to ack pf */
8675                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8676                         return;
8677                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8678                                              NULL);
8679         }
8680 }
8681
8682 static int
8683 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8684 {
8685         uint32_t eicr;
8686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8687         struct ixgbe_interrupt *intr =
8688                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8689         ixgbevf_intr_disable(dev);
8690
8691         /* read-on-clear nic registers here */
8692         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8693         intr->flags = 0;
8694
8695         /* only one misc vector supported - mailbox */
8696         eicr &= IXGBE_VTEICR_MASK;
8697         if (eicr == IXGBE_MISC_VEC_ID)
8698                 intr->flags |= IXGBE_FLAG_MAILBOX;
8699
8700         return 0;
8701 }
8702
8703 static int
8704 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8705 {
8706         struct ixgbe_interrupt *intr =
8707                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8708
8709         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8710                 ixgbevf_mbx_process(dev);
8711                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8712         }
8713
8714         ixgbevf_intr_enable(dev);
8715
8716         return 0;
8717 }
8718
8719 static void
8720 ixgbevf_dev_interrupt_handler(void *param)
8721 {
8722         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8723
8724         ixgbevf_dev_interrupt_get_status(dev);
8725         ixgbevf_dev_interrupt_action(dev);
8726 }
8727
8728 /**
8729  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8730  *  @hw: pointer to hardware structure
8731  *
8732  *  Stops the transmit data path and waits for the HW to internally empty
8733  *  the Tx security block
8734  **/
8735 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8736 {
8737 #define IXGBE_MAX_SECTX_POLL 40
8738
8739         int i;
8740         int sectxreg;
8741
8742         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8743         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8744         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8745         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8746                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8747                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8748                         break;
8749                 /* Use interrupt-safe sleep just in case */
8750                 usec_delay(1000);
8751         }
8752
8753         /* For informational purposes only */
8754         if (i >= IXGBE_MAX_SECTX_POLL)
8755                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8756                          "path fully disabled.  Continuing with init.");
8757
8758         return IXGBE_SUCCESS;
8759 }
8760
8761 /**
8762  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8763  *  @hw: pointer to hardware structure
8764  *
8765  *  Enables the transmit data path.
8766  **/
8767 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8768 {
8769         uint32_t sectxreg;
8770
8771         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8772         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8773         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8774         IXGBE_WRITE_FLUSH(hw);
8775
8776         return IXGBE_SUCCESS;
8777 }
8778
8779 /* restore n-tuple filter */
8780 static inline void
8781 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8782 {
8783         struct ixgbe_filter_info *filter_info =
8784                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8785         struct ixgbe_5tuple_filter *node;
8786
8787         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8788                 ixgbe_inject_5tuple_filter(dev, node);
8789         }
8790 }
8791
8792 /* restore ethernet type filter */
8793 static inline void
8794 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8795 {
8796         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8797         struct ixgbe_filter_info *filter_info =
8798                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8799         int i;
8800
8801         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8802                 if (filter_info->ethertype_mask & (1 << i)) {
8803                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8804                                         filter_info->ethertype_filters[i].etqf);
8805                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8806                                         filter_info->ethertype_filters[i].etqs);
8807                         IXGBE_WRITE_FLUSH(hw);
8808                 }
8809         }
8810 }
8811
8812 /* restore SYN filter */
8813 static inline void
8814 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8815 {
8816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8817         struct ixgbe_filter_info *filter_info =
8818                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8819         uint32_t synqf;
8820
8821         synqf = filter_info->syn_info;
8822
8823         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8824                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8825                 IXGBE_WRITE_FLUSH(hw);
8826         }
8827 }
8828
8829 /* restore L2 tunnel filter */
8830 static inline void
8831 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8832 {
8833         struct ixgbe_l2_tn_info *l2_tn_info =
8834                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8835         struct ixgbe_l2_tn_filter *node;
8836         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8837
8838         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8839                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8840                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8841                 l2_tn_conf.pool           = node->pool;
8842                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8843         }
8844 }
8845
8846 /* restore rss filter */
8847 static inline void
8848 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8849 {
8850         struct ixgbe_filter_info *filter_info =
8851                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8852
8853         if (filter_info->rss_info.conf.queue_num)
8854                 ixgbe_config_rss_filter(dev,
8855                         &filter_info->rss_info, TRUE);
8856 }
8857
8858 static int
8859 ixgbe_filter_restore(struct rte_eth_dev *dev)
8860 {
8861         ixgbe_ntuple_filter_restore(dev);
8862         ixgbe_ethertype_filter_restore(dev);
8863         ixgbe_syn_filter_restore(dev);
8864         ixgbe_fdir_filter_restore(dev);
8865         ixgbe_l2_tn_filter_restore(dev);
8866         ixgbe_rss_filter_restore(dev);
8867
8868         return 0;
8869 }
8870
8871 static void
8872 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8873 {
8874         struct ixgbe_l2_tn_info *l2_tn_info =
8875                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8877
8878         if (l2_tn_info->e_tag_en)
8879                 (void)ixgbe_e_tag_enable(hw);
8880
8881         if (l2_tn_info->e_tag_fwd_en)
8882                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8883
8884         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8885 }
8886
8887 /* remove all the n-tuple filters */
8888 void
8889 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8890 {
8891         struct ixgbe_filter_info *filter_info =
8892                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8893         struct ixgbe_5tuple_filter *p_5tuple;
8894
8895         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8896                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8897 }
8898
8899 /* remove all the ether type filters */
8900 void
8901 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8902 {
8903         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8904         struct ixgbe_filter_info *filter_info =
8905                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8906         int i;
8907
8908         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8909                 if (filter_info->ethertype_mask & (1 << i) &&
8910                     !filter_info->ethertype_filters[i].conf) {
8911                         (void)ixgbe_ethertype_filter_remove(filter_info,
8912                                                             (uint8_t)i);
8913                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8914                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8915                         IXGBE_WRITE_FLUSH(hw);
8916                 }
8917         }
8918 }
8919
8920 /* remove the SYN filter */
8921 void
8922 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8923 {
8924         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8925         struct ixgbe_filter_info *filter_info =
8926                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8927
8928         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8929                 filter_info->syn_info = 0;
8930
8931                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8932                 IXGBE_WRITE_FLUSH(hw);
8933         }
8934 }
8935
8936 /* remove all the L2 tunnel filters */
8937 int
8938 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8939 {
8940         struct ixgbe_l2_tn_info *l2_tn_info =
8941                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8942         struct ixgbe_l2_tn_filter *l2_tn_filter;
8943         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8944         int ret = 0;
8945
8946         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8947                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8948                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8949                 l2_tn_conf.pool           = l2_tn_filter->pool;
8950                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8951                 if (ret < 0)
8952                         return ret;
8953         }
8954
8955         return 0;
8956 }
8957
8958 void
8959 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8960                                 struct ixgbe_macsec_setting *macsec_setting)
8961 {
8962         struct ixgbe_macsec_setting *macsec =
8963                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8964
8965         macsec->offload_en = macsec_setting->offload_en;
8966         macsec->encrypt_en = macsec_setting->encrypt_en;
8967         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8968 }
8969
8970 void
8971 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8972 {
8973         struct ixgbe_macsec_setting *macsec =
8974                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8975
8976         macsec->offload_en = 0;
8977         macsec->encrypt_en = 0;
8978         macsec->replayprotect_en = 0;
8979 }
8980
8981 void
8982 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8983                                 struct ixgbe_macsec_setting *macsec_setting)
8984 {
8985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8986         uint32_t ctrl;
8987         uint8_t en = macsec_setting->encrypt_en;
8988         uint8_t rp = macsec_setting->replayprotect_en;
8989
8990         /**
8991          * Workaround:
8992          * As no ixgbe_disable_sec_rx_path equivalent is
8993          * implemented for tx in the base code, and we are
8994          * not allowed to modify the base code in DPDK, so
8995          * just call the hand-written one directly for now.
8996          * The hardware support has been checked by
8997          * ixgbe_disable_sec_rx_path().
8998          */
8999         ixgbe_disable_sec_tx_path_generic(hw);
9000
9001         /* Enable Ethernet CRC (required by MACsec offload) */
9002         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9003         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9004         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9005
9006         /* Enable the TX and RX crypto engines */
9007         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9008         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9009         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9010
9011         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9012         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9013         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9014
9015         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9016         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9017         ctrl |= 0x3;
9018         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9019
9020         /* Enable SA lookup */
9021         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9022         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9023         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9024                      IXGBE_LSECTXCTRL_AUTH;
9025         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9026         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9027         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9028         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9029
9030         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9031         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9032         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9033         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9034         if (rp)
9035                 ctrl |= IXGBE_LSECRXCTRL_RP;
9036         else
9037                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9038         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9039
9040         /* Start the data paths */
9041         ixgbe_enable_sec_rx_path(hw);
9042         /**
9043          * Workaround:
9044          * As no ixgbe_enable_sec_rx_path equivalent is
9045          * implemented for tx in the base code, and we are
9046          * not allowed to modify the base code in DPDK, so
9047          * just call the hand-written one directly for now.
9048          */
9049         ixgbe_enable_sec_tx_path_generic(hw);
9050 }
9051
9052 void
9053 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9054 {
9055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9056         uint32_t ctrl;
9057
9058         /**
9059          * Workaround:
9060          * As no ixgbe_disable_sec_rx_path equivalent is
9061          * implemented for tx in the base code, and we are
9062          * not allowed to modify the base code in DPDK, so
9063          * just call the hand-written one directly for now.
9064          * The hardware support has been checked by
9065          * ixgbe_disable_sec_rx_path().
9066          */
9067         ixgbe_disable_sec_tx_path_generic(hw);
9068
9069         /* Disable the TX and RX crypto engines */
9070         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9071         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9072         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9073
9074         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9075         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9076         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9077
9078         /* Disable SA lookup */
9079         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9080         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9081         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9082         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9083
9084         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9085         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9086         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9087         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9088
9089         /* Start the data paths */
9090         ixgbe_enable_sec_rx_path(hw);
9091         /**
9092          * Workaround:
9093          * As no ixgbe_enable_sec_rx_path equivalent is
9094          * implemented for tx in the base code, and we are
9095          * not allowed to modify the base code in DPDK, so
9096          * just call the hand-written one directly for now.
9097          */
9098         ixgbe_enable_sec_tx_path_generic(hw);
9099 }
9100
9101 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9102 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9103 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9104 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9105 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9106 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9107 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9108                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9109
9110 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9111 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9112
9113 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9114 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9115 #endif
9116 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9117 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9118 #endif
9119 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9120 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9121 #endif