drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 enum ixgbevf_xcast_modes {
 155         IXGBEVF_XCAST_MODE_NONE = 0,
 156         IXGBEVF_XCAST_MODE_MULTI,
 157         IXGBEVF_XCAST_MODE_ALLMULTI,
 158 };
 159
 160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 162 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 163 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 165 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 166 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 167 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 169 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 172 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 173                                 int wait_to_complete);
 174 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 175                                 struct rte_eth_stats *stats);
 176 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 177                                 struct rte_eth_xstats *xstats, unsigned n);
 178 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 179                                   struct rte_eth_xstats *xstats, unsigned n);
 180 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 183                                              uint16_t queue_id,
 184                                              uint8_t stat_idx,
 185                                              uint8_t is_rx);
 186 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 187                                struct rte_eth_dev_info *dev_info);
 188 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                  struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 202 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 203 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 204 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 205 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 206
 207 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 208 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 209 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 210                                struct rte_eth_fc_conf *fc_conf);
 211 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 212                                struct rte_eth_fc_conf *fc_conf);
 213 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 214                 struct rte_eth_pfc_conf *pfc_conf);
 215 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 224 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 226 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 227                 void *param);
 228 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 229 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 230                 uint32_t index, uint32_t pool);
 231 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 232 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 233                                            struct ether_addr *mac_addr);
 234 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 244 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 245 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 246                 struct rte_eth_stats *stats);
 247 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 248 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 249                 uint16_t vlan_id, int on);
 250 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 251                 uint16_t queue, int on);
 252 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 254 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 255                                             uint16_t queue_id);
 256 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 257                                              uint16_t queue_id);
 258 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 259                                  uint8_t queue, uint8_t msix_vector);
 260 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 261 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 263
 264 /* For Eth VMDQ APIs support */
 265 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 266                 ether_addr* mac_addr,uint8_t on);
 267 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 268 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 269                 uint16_t rx_mask, uint8_t on);
 270 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 271 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 272 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 273                 uint64_t pool_mask,uint8_t vlan_on);
 274 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 275                 struct rte_eth_mirror_conf *mirror_conf,
 276                 uint8_t rule_id, uint8_t on);
 277 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 278                 uint8_t rule_id);
 279 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 280                                           uint16_t queue_id);
 281 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 282                                            uint16_t queue_id);
 283 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 284                                uint8_t queue, uint8_t msix_vector);
 285 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 286
 287 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 288                 uint16_t queue_idx, uint16_t tx_rate);
 289 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 290                 uint16_t tx_rate, uint64_t q_msk);
 291
 292 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 293                                  struct ether_addr *mac_addr,
 294                                  uint32_t index, uint32_t pool);
 295 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 296 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 297                                              struct ether_addr *mac_addr);
 298 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 299                         struct rte_eth_syn_filter *filter,
 300                         bool add);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ntuple_filter *filter,
 312                         bool add);
 313 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ntuple_filter *filter);
 318 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter,
 320                         bool add);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379
 380 /*
 381  * Define VF Stats MACRO for Non "cleared on read" register
 382  */
 383 #define UPDATE_VF_STAT(reg, last, cur)                          \
 384 {                                                               \
 385         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 386         cur += (latest - last) & UINT_MAX;                      \
 387         last = latest;                                          \
 388 }
 389
 390 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 391 {                                                                \
 392         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 393         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 394         u64 latest = ((new_msb << 32) | new_lsb);                \
 395         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 396         last = latest;                                           \
 397 }
 398
 399 #define IXGBE_SET_HWSTRIP(h, q) do{\
 400                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 401                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 402                 (h)->bitmap[idx] |= 1 << bit;\
 403         } while (0)
 404
 405 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 406                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 407                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 408                 (h)->bitmap[idx] &= ~(1 << bit);\
 409         } while (0)
 410
 411 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 412                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 413                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 414                 (r) = (h)->bitmap[idx] >> bit & 1;\
 415         } while (0)
 416
 417 /*
 418  * The set of PCI devices this driver supports
 419  */
 420 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 421
 422 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 423 #include "rte_pci_dev_ids.h"
 424
 425 { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428
 429 /*
 430  * The set of PCI devices this driver supports (for 82599 VF)
 431  */
 432 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 433
 434 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 435 #include "rte_pci_dev_ids.h"
 436 { .vendor_id = 0, /* sentinel */ },
 437
 438 };
 439
 440 static const struct rte_eth_desc_lim rx_desc_lim = {
 441         .nb_max = IXGBE_MAX_RING_DESC,
 442         .nb_min = IXGBE_MIN_RING_DESC,
 443         .nb_align = IXGBE_RXD_ALIGN,
 444 };
 445
 446 static const struct rte_eth_desc_lim tx_desc_lim = {
 447         .nb_max = IXGBE_MAX_RING_DESC,
 448         .nb_min = IXGBE_MIN_RING_DESC,
 449         .nb_align = IXGBE_TXD_ALIGN,
 450 };
 451
 452 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 453         .dev_configure        = ixgbe_dev_configure,
 454         .dev_start            = ixgbe_dev_start,
 455         .dev_stop             = ixgbe_dev_stop,
 456         .dev_set_link_up    = ixgbe_dev_set_link_up,
 457         .dev_set_link_down  = ixgbe_dev_set_link_down,
 458         .dev_close            = ixgbe_dev_close,
 459         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 460         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 461         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 462         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 463         .link_update          = ixgbe_dev_link_update,
 464         .stats_get            = ixgbe_dev_stats_get,
 465         .xstats_get           = ixgbe_dev_xstats_get,
 466         .stats_reset          = ixgbe_dev_stats_reset,
 467         .xstats_reset         = ixgbe_dev_xstats_reset,
 468         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 469         .dev_infos_get        = ixgbe_dev_info_get,
 470         .mtu_set              = ixgbe_dev_mtu_set,
 471         .vlan_filter_set      = ixgbe_vlan_filter_set,
 472         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 473         .vlan_offload_set     = ixgbe_vlan_offload_set,
 474         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 475         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 476         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 477         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 478         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 479         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 480         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 482         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 483         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 484         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 485         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 486         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 487         .dev_led_on           = ixgbe_dev_led_on,
 488         .dev_led_off          = ixgbe_dev_led_off,
 489         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 490         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 491         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 492         .mac_addr_add         = ixgbe_add_rar,
 493         .mac_addr_remove      = ixgbe_remove_rar,
 494         .mac_addr_set         = ixgbe_set_default_mac_addr,
 495         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 496         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 497         .mirror_rule_set      = ixgbe_mirror_rule_set,
 498         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 499         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 500         .set_vf_rx            = ixgbe_set_pool_rx,
 501         .set_vf_tx            = ixgbe_set_pool_tx,
 502         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 503         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 504         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 505         .reta_update          = ixgbe_dev_rss_reta_update,
 506         .reta_query           = ixgbe_dev_rss_reta_query,
 507 #ifdef RTE_NIC_BYPASS
 508         .bypass_init          = ixgbe_bypass_init,
 509         .bypass_state_set     = ixgbe_bypass_state_store,
 510         .bypass_state_show    = ixgbe_bypass_state_show,
 511         .bypass_event_set     = ixgbe_bypass_event_store,
 512         .bypass_event_show    = ixgbe_bypass_event_show,
 513         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 514         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 515         .bypass_ver_show      = ixgbe_bypass_ver_show,
 516         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 517 #endif /* RTE_NIC_BYPASS */
 518         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 519         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 520         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 521         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 522         .rxq_info_get         = ixgbe_rxq_info_get,
 523         .txq_info_get         = ixgbe_txq_info_get,
 524         .timesync_enable      = ixgbe_timesync_enable,
 525         .timesync_disable     = ixgbe_timesync_disable,
 526         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 527         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 528         .get_reg_length       = ixgbe_get_reg_length,
 529         .get_reg              = ixgbe_get_regs,
 530         .get_eeprom_length    = ixgbe_get_eeprom_length,
 531         .get_eeprom           = ixgbe_get_eeprom,
 532         .set_eeprom           = ixgbe_set_eeprom,
 533         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 534         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 535         .timesync_read_time   = ixgbe_timesync_read_time,
 536         .timesync_write_time  = ixgbe_timesync_write_time,
 537         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 538         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 539         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 540         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 541 };
 542
 543 /*
 544  * dev_ops for virtual function, bare necessities for basic vf
 545  * operation have been implemented
 546  */
 547 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 548         .dev_configure        = ixgbevf_dev_configure,
 549         .dev_start            = ixgbevf_dev_start,
 550         .dev_stop             = ixgbevf_dev_stop,
 551         .link_update          = ixgbe_dev_link_update,
 552         .stats_get            = ixgbevf_dev_stats_get,
 553         .xstats_get           = ixgbevf_dev_xstats_get,
 554         .stats_reset          = ixgbevf_dev_stats_reset,
 555         .xstats_reset         = ixgbevf_dev_stats_reset,
 556         .dev_close            = ixgbevf_dev_close,
 557         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 558         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 559         .dev_infos_get        = ixgbevf_dev_info_get,
 560         .mtu_set              = ixgbevf_dev_set_mtu,
 561         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 562         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 563         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 564         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 565         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 566         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 567         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 568         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 569         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 570         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 571         .mac_addr_add         = ixgbevf_add_mac_addr,
 572         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 573         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 574         .rxq_info_get         = ixgbe_rxq_info_get,
 575         .txq_info_get         = ixgbe_txq_info_get,
 576         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 577         .get_reg_length       = ixgbevf_get_reg_length,
 578         .get_reg              = ixgbevf_get_regs,
 579         .reta_update          = ixgbe_dev_rss_reta_update,
 580         .reta_query           = ixgbe_dev_rss_reta_query,
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583 };
 584
 585 /* store statistics names and its offset in stats structure */
 586 struct rte_ixgbe_xstats_name_off {
 587         char name[RTE_ETH_XSTATS_NAME_SIZE];
 588         unsigned offset;
 589 };
 590
 591 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 592         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 593         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 594         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 595         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 596         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 597         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 598         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 599         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 600         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 601         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 602         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 603         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 604         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 605         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 606         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 607                 prc1023)},
 608         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 609                 prc1522)},
 610         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 611         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 612         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 613         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 614         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 615         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 616         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 617         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 618         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 619         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 620         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 621         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 622         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 623         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 624         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 625         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 627                 ptc1023)},
 628         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 629                 ptc1522)},
 630         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 631         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 632         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 633         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 634
 635         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirustat_add)},
 637         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 638                 fdirustat_remove)},
 639         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 640                 fdirfstat_fadd)},
 641         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 642                 fdirfstat_fremove)},
 643         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 644                 fdirmatch)},
 645         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 646                 fdirmiss)},
 647
 648         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 649         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 650         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 651                 fclast)},
 652         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 653         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 654         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 655         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 656         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 657                 fcoe_noddp)},
 658         {"rx_fcoe_no_direct_data_placement_ext_buff",
 659                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 660
 661         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 662                 lxontxc)},
 663         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 664                 lxonrxc)},
 665         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 666                 lxofftxc)},
 667         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 668                 lxoffrxc)},
 669         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 670 };
 671
 672 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 673                            sizeof(rte_ixgbe_stats_strings[0]))
 674
 675 /* Per-queue statistics */
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 677         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 678         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 679         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 680         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 681 };
 682
 683 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 684                            sizeof(rte_ixgbe_rxq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 687         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 688         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 689         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 690                 pxon2offc)},
 691 };
 692
 693 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 694                            sizeof(rte_ixgbe_txq_strings[0]))
 695
 696 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 697         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 698 };
 699
 700 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 701                 sizeof(rte_ixgbevf_stats_strings[0]))
 702
 703 /**
 704  * Atomically reads the link status information from global
 705  * structure rte_eth_dev.
 706  *
 707  * @param dev
 708  *   - Pointer to the structure rte_eth_dev to read from.
 709  *   - Pointer to the buffer to be saved with the link status.
 710  *
 711  * @return
 712  *   - On success, zero.
 713  *   - On failure, negative value.
 714  */
 715 static inline int
 716 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 717                                 struct rte_eth_link *link)
 718 {
 719         struct rte_eth_link *dst = link;
 720         struct rte_eth_link *src = &(dev->data->dev_link);
 721
 722         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 723                                         *(uint64_t *)src) == 0)
 724                 return -1;
 725
 726         return 0;
 727 }
 728
 729 /**
 730  * Atomically writes the link status information into global
 731  * structure rte_eth_dev.
 732  *
 733  * @param dev
 734  *   - Pointer to the structure rte_eth_dev to read from.
 735  *   - Pointer to the buffer to be saved with the link status.
 736  *
 737  * @return
 738  *   - On success, zero.
 739  *   - On failure, negative value.
 740  */
 741 static inline int
 742 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 743                                 struct rte_eth_link *link)
 744 {
 745         struct rte_eth_link *dst = &(dev->data->dev_link);
 746         struct rte_eth_link *src = link;
 747
 748         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 749                                         *(uint64_t *)src) == 0)
 750                 return -1;
 751
 752         return 0;
 753 }
 754
 755 /*
 756  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 757  */
 758 static inline int
 759 ixgbe_is_sfp(struct ixgbe_hw *hw)
 760 {
 761         switch (hw->phy.type) {
 762         case ixgbe_phy_sfp_avago:
 763         case ixgbe_phy_sfp_ftl:
 764         case ixgbe_phy_sfp_intel:
 765         case ixgbe_phy_sfp_unknown:
 766         case ixgbe_phy_sfp_passive_tyco:
 767         case ixgbe_phy_sfp_passive_unknown:
 768                 return 1;
 769         default:
 770                 return 0;
 771         }
 772 }
 773
 774 static inline int32_t
 775 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 776 {
 777         uint32_t ctrl_ext;
 778         int32_t status;
 779
 780         status = ixgbe_reset_hw(hw);
 781
 782         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 783         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 784         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 785         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 786         IXGBE_WRITE_FLUSH(hw);
 787
 788         return status;
 789 }
 790
 791 static inline void
 792 ixgbe_enable_intr(struct rte_eth_dev *dev)
 793 {
 794         struct ixgbe_interrupt *intr =
 795                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 796         struct ixgbe_hw *hw =
 797                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 798
 799         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 800         IXGBE_WRITE_FLUSH(hw);
 801 }
 802
 803 /*
 804  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 805  */
 806 static void
 807 ixgbe_disable_intr(struct ixgbe_hw *hw)
 808 {
 809         PMD_INIT_FUNC_TRACE();
 810
 811         if (hw->mac.type == ixgbe_mac_82598EB) {
 812                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 813         } else {
 814                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 815                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 816                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 817         }
 818         IXGBE_WRITE_FLUSH(hw);
 819 }
 820
 821 /*
 822  * This function resets queue statistics mapping registers.
 823  * From Niantic datasheet, Initialization of Statistics section:
 824  * "...if software requires the queue counters, the RQSMR and TQSM registers
 825  * must be re-programmed following a device reset.
 826  */
 827 static void
 828 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 829 {
 830         uint32_t i;
 831
 832         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 833                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 834                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 835         }
 836 }
 837
 838
 839 static int
 840 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 841                                   uint16_t queue_id,
 842                                   uint8_t stat_idx,
 843                                   uint8_t is_rx)
 844 {
 845 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 846 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 847 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 848
 849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 850         struct ixgbe_stat_mapping_registers *stat_mappings =
 851                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 852         uint32_t qsmr_mask = 0;
 853         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 854         uint32_t q_map;
 855         uint8_t n, offset;
 856
 857         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 858                 (hw->mac.type != ixgbe_mac_X540) &&
 859                 (hw->mac.type != ixgbe_mac_X550) &&
 860                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 861                 (hw->mac.type != ixgbe_mac_X550EM_a))
 862                 return -ENOSYS;
 863
 864         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 865                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 866                      queue_id, stat_idx);
 867
 868         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 869         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 870                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 871                 return -EIO;
 872         }
 873         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 874
 875         /* Now clear any previous stat_idx set */
 876         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 877         if (!is_rx)
 878                 stat_mappings->tqsm[n] &= ~clearing_mask;
 879         else
 880                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 881
 882         q_map = (uint32_t)stat_idx;
 883         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 884         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 885         if (!is_rx)
 886                 stat_mappings->tqsm[n] |= qsmr_mask;
 887         else
 888                 stat_mappings->rqsmr[n] |= qsmr_mask;
 889
 890         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 891                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 892                      queue_id, stat_idx);
 893         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 894                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 895
 896         /* Now write the mapping in the appropriate register */
 897         if (is_rx) {
 898                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 899                              stat_mappings->rqsmr[n], n);
 900                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 901         }
 902         else {
 903                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 904                              stat_mappings->tqsm[n], n);
 905                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 906         }
 907         return 0;
 908 }
 909
 910 static void
 911 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 912 {
 913         struct ixgbe_stat_mapping_registers *stat_mappings =
 914                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 916         int i;
 917
 918         /* write whatever was in stat mapping table to the NIC */
 919         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 920                 /* rx */
 921                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 922
 923                 /* tx */
 924                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 925         }
 926 }
 927
 928 static void
 929 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 930 {
 931         uint8_t i;
 932         struct ixgbe_dcb_tc_config *tc;
 933         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 934
 935         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 936         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 937         for (i = 0; i < dcb_max_tc; i++) {
 938                 tc = &dcb_config->tc_config[i];
 939                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 940                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 941                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 942                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 943                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 944                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 945                 tc->pfc = ixgbe_dcb_pfc_disabled;
 946         }
 947
 948         /* Initialize default user to priority mapping, UPx->TC0 */
 949         tc = &dcb_config->tc_config[0];
 950         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 951         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 952         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 953                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 954                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 955         }
 956         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 957         dcb_config->pfc_mode_enable = false;
 958         dcb_config->vt_mode = true;
 959         dcb_config->round_robin_enable = false;
 960         /* support all DCB capabilities in 82599 */
 961         dcb_config->support.capabilities = 0xFF;
 962
 963         /*we only support 4 Tcs for X540, X550 */
 964         if (hw->mac.type == ixgbe_mac_X540 ||
 965                 hw->mac.type == ixgbe_mac_X550 ||
 966                 hw->mac.type == ixgbe_mac_X550EM_x ||
 967                 hw->mac.type == ixgbe_mac_X550EM_a) {
 968                 dcb_config->num_tcs.pg_tcs = 4;
 969                 dcb_config->num_tcs.pfc_tcs = 4;
 970         }
 971 }
 972
 973 /*
 974  * Ensure that all locks are released before first NVM or PHY access
 975  */
 976 static void
 977 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 978 {
 979         uint16_t mask;
 980
 981         /*
 982          * Phy lock should not fail in this early stage. If this is the case,
 983          * it is due to an improper exit of the application.
 984          * So force the release of the faulty lock. Release of common lock
 985          * is done automatically by swfw_sync function.
 986          */
 987         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 988         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 989                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 990         }
 991         ixgbe_release_swfw_semaphore(hw, mask);
 992
 993         /*
 994          * These ones are more tricky since they are common to all ports; but
 995          * swfw_sync retries last long enough (1s) to be almost sure that if
 996          * lock can not be taken it is due to an improper lock of the
 997          * semaphore.
 998          */
 999         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1000         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1001                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1002         }
1003         ixgbe_release_swfw_semaphore(hw, mask);
1004 }
1005
1006 /*
1007  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1008  * It returns 0 on success.
1009  */
1010 static int
1011 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1012 {
1013         struct rte_pci_device *pci_dev;
1014         struct ixgbe_hw *hw =
1015                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1016         struct ixgbe_vfta * shadow_vfta =
1017                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1018         struct ixgbe_hwstrip *hwstrip =
1019                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1020         struct ixgbe_dcb_config *dcb_config =
1021                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1022         struct ixgbe_filter_info *filter_info =
1023                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1024         uint32_t ctrl_ext;
1025         uint16_t csum;
1026         int diag, i;
1027
1028         PMD_INIT_FUNC_TRACE();
1029
1030         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1031         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1032         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1033
1034         /*
1035          * For secondary processes, we don't initialise any further as primary
1036          * has already done this work. Only check we don't need a different
1037          * RX and TX function.
1038          */
1039         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040                 struct ixgbe_tx_queue *txq;
1041                 /* TX queue function in primary, set by last queue initialized
1042                  * Tx queue may not initialized by primary process */
1043                 if (eth_dev->data->tx_queues) {
1044                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1045                         ixgbe_set_tx_function(eth_dev, txq);
1046                 } else {
1047                         /* Use default TX function if we get here */
1048                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1049                                              "Using default TX function.");
1050                 }
1051
1052                 ixgbe_set_rx_function(eth_dev);
1053
1054                 return 0;
1055         }
1056         pci_dev = eth_dev->pci_dev;
1057
1058         rte_eth_copy_pci_info(eth_dev, pci_dev);
1059
1060         /* Vendor and Device ID need to be set before init of shared code */
1061         hw->device_id = pci_dev->id.device_id;
1062         hw->vendor_id = pci_dev->id.vendor_id;
1063         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1064         hw->allow_unsupported_sfp = 1;
1065
1066         /* Initialize the shared code (base driver) */
1067 #ifdef RTE_NIC_BYPASS
1068         diag = ixgbe_bypass_init_shared_code(hw);
1069 #else
1070         diag = ixgbe_init_shared_code(hw);
1071 #endif /* RTE_NIC_BYPASS */
1072
1073         if (diag != IXGBE_SUCCESS) {
1074                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1075                 return -EIO;
1076         }
1077
1078         /* pick up the PCI bus settings for reporting later */
1079         ixgbe_get_bus_info(hw);
1080
1081         /* Unlock any pending hardware semaphore */
1082         ixgbe_swfw_lock_reset(hw);
1083
1084         /* Initialize DCB configuration*/
1085         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1086         ixgbe_dcb_init(hw,dcb_config);
1087         /* Get Hardware Flow Control setting */
1088         hw->fc.requested_mode = ixgbe_fc_full;
1089         hw->fc.current_mode = ixgbe_fc_full;
1090         hw->fc.pause_time = IXGBE_FC_PAUSE;
1091         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1092                 hw->fc.low_water[i] = IXGBE_FC_LO;
1093                 hw->fc.high_water[i] = IXGBE_FC_HI;
1094         }
1095         hw->fc.send_xon = 1;
1096
1097         /* Make sure we have a good EEPROM before we read from it */
1098         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1099         if (diag != IXGBE_SUCCESS) {
1100                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1101                 return -EIO;
1102         }
1103
1104 #ifdef RTE_NIC_BYPASS
1105         diag = ixgbe_bypass_init_hw(hw);
1106 #else
1107         diag = ixgbe_init_hw(hw);
1108 #endif /* RTE_NIC_BYPASS */
1109
1110         /*
1111          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1112          * is called too soon after the kernel driver unbinding/binding occurs.
1113          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1114          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1115          * also called. See ixgbe_identify_phy_82599(). The reason for the
1116          * failure is not known, and only occuts when virtualisation features
1117          * are disabled in the bios. A delay of 100ms  was found to be enough by
1118          * trial-and-error, and is doubled to be safe.
1119          */
1120         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1121                 rte_delay_ms(200);
1122                 diag = ixgbe_init_hw(hw);
1123         }
1124
1125         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1126                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1127                     "LOM.  Please be aware there may be issues associated "
1128                     "with your hardware.");
1129                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1130                     "please contact your Intel or hardware representative "
1131                     "who provided you with this hardware.");
1132         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1133                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1134         if (diag) {
1135                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1136                 return -EIO;
1137         }
1138
1139         /* Reset the hw statistics */
1140         ixgbe_dev_stats_reset(eth_dev);
1141
1142         /* disable interrupt */
1143         ixgbe_disable_intr(hw);
1144
1145         /* reset mappings for queue statistics hw counters*/
1146         ixgbe_reset_qstat_mappings(hw);
1147
1148         /* Allocate memory for storing MAC addresses */
1149         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1150                         hw->mac.num_rar_entries, 0);
1151         if (eth_dev->data->mac_addrs == NULL) {
1152                 PMD_INIT_LOG(ERR,
1153                         "Failed to allocate %u bytes needed to store "
1154                         "MAC addresses",
1155                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1156                 return -ENOMEM;
1157         }
1158         /* Copy the permanent MAC address */
1159         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1160                         &eth_dev->data->mac_addrs[0]);
1161
1162         /* Allocate memory for storing hash filter MAC addresses */
1163         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1164                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1165         if (eth_dev->data->hash_mac_addrs == NULL) {
1166                 PMD_INIT_LOG(ERR,
1167                         "Failed to allocate %d bytes needed to store MAC addresses",
1168                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1169                 return -ENOMEM;
1170         }
1171
1172         /* initialize the vfta */
1173         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1174
1175         /* initialize the hw strip bitmap*/
1176         memset(hwstrip, 0, sizeof(*hwstrip));
1177
1178         /* initialize PF if max_vfs not zero */
1179         ixgbe_pf_host_init(eth_dev);
1180
1181         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1182         /* let hardware know driver is loaded */
1183         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1184         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1185         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1186         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1187         IXGBE_WRITE_FLUSH(hw);
1188
1189         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1190                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1191                              (int) hw->mac.type, (int) hw->phy.type,
1192                              (int) hw->phy.sfp_type);
1193         else
1194                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1195                              (int) hw->mac.type, (int) hw->phy.type);
1196
1197         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1198                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1199                         pci_dev->id.device_id);
1200
1201         rte_intr_callback_register(&pci_dev->intr_handle,
1202                                    ixgbe_dev_interrupt_handler,
1203                                    (void *)eth_dev);
1204
1205         /* enable uio/vfio intr/eventfd mapping */
1206         rte_intr_enable(&pci_dev->intr_handle);
1207
1208         /* enable support intr */
1209         ixgbe_enable_intr(eth_dev);
1210
1211         /* initialize 5tuple filter list */
1212         TAILQ_INIT(&filter_info->fivetuple_list);
1213         memset(filter_info->fivetuple_mask, 0,
1214                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1215
1216         return 0;
1217 }
1218
1219 static int
1220 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1221 {
1222         struct rte_pci_device *pci_dev;
1223         struct ixgbe_hw *hw;
1224
1225         PMD_INIT_FUNC_TRACE();
1226
1227         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1228                 return -EPERM;
1229
1230         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1231         pci_dev = eth_dev->pci_dev;
1232
1233         if (hw->adapter_stopped == 0)
1234                 ixgbe_dev_close(eth_dev);
1235
1236         eth_dev->dev_ops = NULL;
1237         eth_dev->rx_pkt_burst = NULL;
1238         eth_dev->tx_pkt_burst = NULL;
1239
1240         /* Unlock any pending hardware semaphore */
1241         ixgbe_swfw_lock_reset(hw);
1242
1243         /* disable uio intr before callback unregister */
1244         rte_intr_disable(&(pci_dev->intr_handle));
1245         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1246                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1247
1248         /* uninitialize PF if max_vfs not zero */
1249         ixgbe_pf_host_uninit(eth_dev);
1250
1251         rte_free(eth_dev->data->mac_addrs);
1252         eth_dev->data->mac_addrs = NULL;
1253
1254         rte_free(eth_dev->data->hash_mac_addrs);
1255         eth_dev->data->hash_mac_addrs = NULL;
1256
1257         return 0;
1258 }
1259
1260 /*
1261  * Negotiate mailbox API version with the PF.
1262  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1263  * Then we try to negotiate starting with the most recent one.
1264  * If all negotiation attempts fail, then we will proceed with
1265  * the default one (ixgbe_mbox_api_10).
1266  */
1267 static void
1268 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1269 {
1270         int32_t i;
1271
1272         /* start with highest supported, proceed down */
1273         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1274                 ixgbe_mbox_api_12,
1275                 ixgbe_mbox_api_11,
1276                 ixgbe_mbox_api_10,
1277         };
1278
1279         for (i = 0;
1280                         i != RTE_DIM(sup_ver) &&
1281                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1282                         i++)
1283                 ;
1284 }
1285
1286 static void
1287 generate_random_mac_addr(struct ether_addr *mac_addr)
1288 {
1289         uint64_t random;
1290
1291         /* Set Organizationally Unique Identifier (OUI) prefix. */
1292         mac_addr->addr_bytes[0] = 0x00;
1293         mac_addr->addr_bytes[1] = 0x09;
1294         mac_addr->addr_bytes[2] = 0xC0;
1295         /* Force indication of locally assigned MAC address. */
1296         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1297         /* Generate the last 3 bytes of the MAC address with a random number. */
1298         random = rte_rand();
1299         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1300 }
1301
1302 /*
1303  * Virtual Function device init
1304  */
1305 static int
1306 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1307 {
1308         int diag;
1309         uint32_t tc, tcs;
1310         struct rte_pci_device *pci_dev;
1311         struct ixgbe_hw *hw =
1312                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1313         struct ixgbe_vfta * shadow_vfta =
1314                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1315         struct ixgbe_hwstrip *hwstrip =
1316                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1317         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1318
1319         PMD_INIT_FUNC_TRACE();
1320
1321         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1322         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1323         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1324
1325         /* for secondary processes, we don't initialise any further as primary
1326          * has already done this work. Only check we don't need a different
1327          * RX function */
1328         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1329                 if (eth_dev->data->scattered_rx)
1330                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1331                 return 0;
1332         }
1333
1334         pci_dev = eth_dev->pci_dev;
1335
1336         rte_eth_copy_pci_info(eth_dev, pci_dev);
1337
1338         hw->device_id = pci_dev->id.device_id;
1339         hw->vendor_id = pci_dev->id.vendor_id;
1340         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1341
1342         /* initialize the vfta */
1343         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1344
1345         /* initialize the hw strip bitmap*/
1346         memset(hwstrip, 0, sizeof(*hwstrip));
1347
1348         /* Initialize the shared code (base driver) */
1349         diag = ixgbe_init_shared_code(hw);
1350         if (diag != IXGBE_SUCCESS) {
1351                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1352                 return -EIO;
1353         }
1354
1355         /* init_mailbox_params */
1356         hw->mbx.ops.init_params(hw);
1357
1358         /* Reset the hw statistics */
1359         ixgbevf_dev_stats_reset(eth_dev);
1360
1361         /* Disable the interrupts for VF */
1362         ixgbevf_intr_disable(hw);
1363
1364         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1365         diag = hw->mac.ops.reset_hw(hw);
1366
1367         /*
1368          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1369          * the underlying PF driver has not assigned a MAC address to the VF.
1370          * In this case, assign a random MAC address.
1371          */
1372         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1373                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1374                 return diag;
1375         }
1376
1377         /* negotiate mailbox API version to use with the PF. */
1378         ixgbevf_negotiate_api(hw);
1379
1380         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1381         ixgbevf_get_queues(hw, &tcs, &tc);
1382
1383         /* Allocate memory for storing MAC addresses */
1384         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1385                         hw->mac.num_rar_entries, 0);
1386         if (eth_dev->data->mac_addrs == NULL) {
1387                 PMD_INIT_LOG(ERR,
1388                         "Failed to allocate %u bytes needed to store "
1389                         "MAC addresses",
1390                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1391                 return -ENOMEM;
1392         }
1393
1394         /* Generate a random MAC address, if none was assigned by PF. */
1395         if (is_zero_ether_addr(perm_addr)) {
1396                 generate_random_mac_addr(perm_addr);
1397                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1398                 if (diag) {
1399                         rte_free(eth_dev->data->mac_addrs);
1400                         eth_dev->data->mac_addrs = NULL;
1401                         return diag;
1402                 }
1403                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1404                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1405                              "%02x:%02x:%02x:%02x:%02x:%02x",
1406                              perm_addr->addr_bytes[0],
1407                              perm_addr->addr_bytes[1],
1408                              perm_addr->addr_bytes[2],
1409                              perm_addr->addr_bytes[3],
1410                              perm_addr->addr_bytes[4],
1411                              perm_addr->addr_bytes[5]);
1412         }
1413
1414         /* Copy the permanent MAC address */
1415         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1416
1417         /* reset the hardware with the new settings */
1418         diag = hw->mac.ops.start_hw(hw);
1419         switch (diag) {
1420                 case  0:
1421                         break;
1422
1423                 default:
1424                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1425                         return -EIO;
1426         }
1427
1428         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1429                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1430                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1431
1432         return 0;
1433 }
1434
1435 /* Virtual Function device uninit */
1436
1437 static int
1438 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1439 {
1440         struct ixgbe_hw *hw;
1441         unsigned i;
1442
1443         PMD_INIT_FUNC_TRACE();
1444
1445         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1446                 return -EPERM;
1447
1448         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1449
1450         if (hw->adapter_stopped == 0)
1451                 ixgbevf_dev_close(eth_dev);
1452
1453         eth_dev->dev_ops = NULL;
1454         eth_dev->rx_pkt_burst = NULL;
1455         eth_dev->tx_pkt_burst = NULL;
1456
1457         /* Disable the interrupts for VF */
1458         ixgbevf_intr_disable(hw);
1459
1460         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1461                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1462                 eth_dev->data->rx_queues[i] = NULL;
1463         }
1464         eth_dev->data->nb_rx_queues = 0;
1465
1466         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1467                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1468                 eth_dev->data->tx_queues[i] = NULL;
1469         }
1470         eth_dev->data->nb_tx_queues = 0;
1471
1472         rte_free(eth_dev->data->mac_addrs);
1473         eth_dev->data->mac_addrs = NULL;
1474
1475         return 0;
1476 }
1477
1478 static struct eth_driver rte_ixgbe_pmd = {
1479         .pci_drv = {
1480                 .name = "rte_ixgbe_pmd",
1481                 .id_table = pci_id_ixgbe_map,
1482                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1483                         RTE_PCI_DRV_DETACHABLE,
1484         },
1485         .eth_dev_init = eth_ixgbe_dev_init,
1486         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1487         .dev_private_size = sizeof(struct ixgbe_adapter),
1488 };
1489
1490 /*
1491  * virtual function driver struct
1492  */
1493 static struct eth_driver rte_ixgbevf_pmd = {
1494         .pci_drv = {
1495                 .name = "rte_ixgbevf_pmd",
1496                 .id_table = pci_id_ixgbevf_map,
1497                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1498         },
1499         .eth_dev_init = eth_ixgbevf_dev_init,
1500         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1501         .dev_private_size = sizeof(struct ixgbe_adapter),
1502 };
1503
1504 /*
1505  * Driver initialization routine.
1506  * Invoked once at EAL init time.
1507  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1508  */
1509 static int
1510 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1511 {
1512         PMD_INIT_FUNC_TRACE();
1513
1514         rte_eth_driver_register(&rte_ixgbe_pmd);
1515         return 0;
1516 }
1517
1518 /*
1519  * VF Driver initialization routine.
1520  * Invoked one at EAL init time.
1521  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1522  */
1523 static int
1524 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1525 {
1526         PMD_INIT_FUNC_TRACE();
1527
1528         rte_eth_driver_register(&rte_ixgbevf_pmd);
1529         return 0;
1530 }
1531
1532 static int
1533 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1534 {
1535         struct ixgbe_hw *hw =
1536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         struct ixgbe_vfta * shadow_vfta =
1538                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1539         uint32_t vfta;
1540         uint32_t vid_idx;
1541         uint32_t vid_bit;
1542
1543         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1544         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1545         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1546         if (on)
1547                 vfta |= vid_bit;
1548         else
1549                 vfta &= ~vid_bit;
1550         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1551
1552         /* update local VFTA copy */
1553         shadow_vfta->vfta[vid_idx] = vfta;
1554
1555         return 0;
1556 }
1557
1558 static void
1559 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1560 {
1561         if (on)
1562                 ixgbe_vlan_hw_strip_enable(dev, queue);
1563         else
1564                 ixgbe_vlan_hw_strip_disable(dev, queue);
1565 }
1566
1567 static int
1568 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1569                     enum rte_vlan_type vlan_type,
1570                     uint16_t tpid)
1571 {
1572         struct ixgbe_hw *hw =
1573                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574         int ret = 0;
1575
1576         switch (vlan_type) {
1577         case ETH_VLAN_TYPE_INNER:
1578                 /* Only the high 16-bits is valid */
1579                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1580                 break;
1581         default:
1582                 ret = -EINVAL;
1583                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1584                 break;
1585         }
1586
1587         return ret;
1588 }
1589
1590 void
1591 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1592 {
1593         struct ixgbe_hw *hw =
1594                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         uint32_t vlnctrl;
1596
1597         PMD_INIT_FUNC_TRACE();
1598
1599         /* Filter Table Disable */
1600         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1601         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1602
1603         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1604 }
1605
1606 void
1607 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1608 {
1609         struct ixgbe_hw *hw =
1610                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1611         struct ixgbe_vfta * shadow_vfta =
1612                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1613         uint32_t vlnctrl;
1614         uint16_t i;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         /* Filter Table Enable */
1619         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1620         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1621         vlnctrl |= IXGBE_VLNCTRL_VFE;
1622
1623         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1624
1625         /* write whatever is in local vfta copy */
1626         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1627                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1628 }
1629
1630 static void
1631 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1632 {
1633         struct ixgbe_hwstrip *hwstrip =
1634                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1635
1636         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1637                 return;
1638
1639         if (on)
1640                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1641         else
1642                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1643 }
1644
1645 static void
1646 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1647 {
1648         struct ixgbe_hw *hw =
1649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1650         uint32_t ctrl;
1651
1652         PMD_INIT_FUNC_TRACE();
1653
1654         if (hw->mac.type == ixgbe_mac_82598EB) {
1655                 /* No queue level support */
1656                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1657                 return;
1658         }
1659         else {
1660                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1661                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1662                 ctrl &= ~IXGBE_RXDCTL_VME;
1663                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1664         }
1665         /* record those setting for HW strip per queue */
1666         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1667 }
1668
1669 static void
1670 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         uint32_t ctrl;
1675
1676         PMD_INIT_FUNC_TRACE();
1677
1678         if (hw->mac.type == ixgbe_mac_82598EB) {
1679                 /* No queue level supported */
1680                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1681                 return;
1682         }
1683         else {
1684                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1685                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1686                 ctrl |= IXGBE_RXDCTL_VME;
1687                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1688         }
1689         /* record those setting for HW strip per queue */
1690         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1691 }
1692
1693 void
1694 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1695 {
1696         struct ixgbe_hw *hw =
1697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698         uint32_t ctrl;
1699         uint16_t i;
1700
1701         PMD_INIT_FUNC_TRACE();
1702
1703         if (hw->mac.type == ixgbe_mac_82598EB) {
1704                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1705                 ctrl &= ~IXGBE_VLNCTRL_VME;
1706                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1707         }
1708         else {
1709                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1710                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1711                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1712                         ctrl &= ~IXGBE_RXDCTL_VME;
1713                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1714
1715                         /* record those setting for HW strip per queue */
1716                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1717                 }
1718         }
1719 }
1720
1721 void
1722 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1723 {
1724         struct ixgbe_hw *hw =
1725                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         uint32_t ctrl;
1727         uint16_t i;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         if (hw->mac.type == ixgbe_mac_82598EB) {
1732                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1733                 ctrl |= IXGBE_VLNCTRL_VME;
1734                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1735         }
1736         else {
1737                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1738                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1739                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1740                         ctrl |= IXGBE_RXDCTL_VME;
1741                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1742
1743                         /* record those setting for HW strip per queue */
1744                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1745                 }
1746         }
1747 }
1748
1749 static void
1750 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1751 {
1752         struct ixgbe_hw *hw =
1753                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1754         uint32_t ctrl;
1755
1756         PMD_INIT_FUNC_TRACE();
1757
1758         /* DMATXCTRL: Geric Double VLAN Disable */
1759         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1760         ctrl &= ~IXGBE_DMATXCTL_GDV;
1761         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1762
1763         /* CTRL_EXT: Global Double VLAN Disable */
1764         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1765         ctrl &= ~IXGBE_EXTENDED_VLAN;
1766         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1767
1768 }
1769
1770 static void
1771 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1772 {
1773         struct ixgbe_hw *hw =
1774                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1775         uint32_t ctrl;
1776
1777         PMD_INIT_FUNC_TRACE();
1778
1779         /* DMATXCTRL: Geric Double VLAN Enable */
1780         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1781         ctrl |= IXGBE_DMATXCTL_GDV;
1782         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1783
1784         /* CTRL_EXT: Global Double VLAN Enable */
1785         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1786         ctrl |= IXGBE_EXTENDED_VLAN;
1787         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1788
1789         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1790         if (hw->mac.type == ixgbe_mac_X550 ||
1791             hw->mac.type == ixgbe_mac_X550EM_x) {
1792                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1793                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1794                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1795         }
1796
1797         /*
1798          * VET EXT field in the EXVET register = 0x8100 by default
1799          * So no need to change. Same to VT field of DMATXCTL register
1800          */
1801 }
1802
1803 static void
1804 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1805 {
1806         if (mask & ETH_VLAN_STRIP_MASK) {
1807                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1808                         ixgbe_vlan_hw_strip_enable_all(dev);
1809                 else
1810                         ixgbe_vlan_hw_strip_disable_all(dev);
1811         }
1812
1813         if (mask & ETH_VLAN_FILTER_MASK) {
1814                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1815                         ixgbe_vlan_hw_filter_enable(dev);
1816                 else
1817                         ixgbe_vlan_hw_filter_disable(dev);
1818         }
1819
1820         if (mask & ETH_VLAN_EXTEND_MASK) {
1821                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1822                         ixgbe_vlan_hw_extend_enable(dev);
1823                 else
1824                         ixgbe_vlan_hw_extend_disable(dev);
1825         }
1826 }
1827
1828 static void
1829 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1830 {
1831         struct ixgbe_hw *hw =
1832                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1834         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1835         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1836         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1837 }
1838
1839 static int
1840 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1841 {
1842         switch (nb_rx_q) {
1843         case 1:
1844         case 2:
1845                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1846                 break;
1847         case 4:
1848                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1849                 break;
1850         default:
1851                 return -EINVAL;
1852         }
1853
1854         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1855         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1856
1857         return 0;
1858 }
1859
1860 static int
1861 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1862 {
1863         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1864         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1865         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1866
1867         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1868                 /* check multi-queue mode */
1869                 switch (dev_conf->rxmode.mq_mode) {
1870                 case ETH_MQ_RX_VMDQ_DCB:
1871                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1872                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1873                         PMD_INIT_LOG(ERR, "SRIOV active,"
1874                                         " unsupported mq_mode rx %d.",
1875                                         dev_conf->rxmode.mq_mode);
1876                         return -EINVAL;
1877                 case ETH_MQ_RX_RSS:
1878                 case ETH_MQ_RX_VMDQ_RSS:
1879                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1880                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1881                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1882                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1883                                                 " invalid queue number"
1884                                                 " for VMDQ RSS, allowed"
1885                                                 " value are 1, 2 or 4.");
1886                                         return -EINVAL;
1887                                 }
1888                         break;
1889                 case ETH_MQ_RX_VMDQ_ONLY:
1890                 case ETH_MQ_RX_NONE:
1891                         /* if nothing mq mode configure, use default scheme */
1892                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1893                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1894                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1895                         break;
1896                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1897                         /* SRIOV only works in VMDq enable mode */
1898                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1899                                         " wrong mq_mode rx %d.",
1900                                         dev_conf->rxmode.mq_mode);
1901                         return -EINVAL;
1902                 }
1903
1904                 switch (dev_conf->txmode.mq_mode) {
1905                 case ETH_MQ_TX_VMDQ_DCB:
1906                         /* DCB VMDQ in SRIOV mode, not implement yet */
1907                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1908                                         " unsupported VMDQ mq_mode tx %d.",
1909                                         dev_conf->txmode.mq_mode);
1910                         return -EINVAL;
1911                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1912                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1913                         break;
1914                 }
1915
1916                 /* check valid queue number */
1917                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1918                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1919                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1920                                         " queue number must less equal to %d.",
1921                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1922                         return -EINVAL;
1923                 }
1924         } else {
1925                 /* check configuration for vmdb+dcb mode */
1926                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1927                         const struct rte_eth_vmdq_dcb_conf *conf;
1928
1929                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1930                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1931                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1932                                 return -EINVAL;
1933                         }
1934                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1935                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1936                                conf->nb_queue_pools == ETH_32_POOLS)) {
1937                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1938                                                 " nb_queue_pools must be %d or %d.",
1939                                                 ETH_16_POOLS, ETH_32_POOLS);
1940                                 return -EINVAL;
1941                         }
1942                 }
1943                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1944                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1945
1946                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1947                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1948                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1949                                 return -EINVAL;
1950                         }
1951                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1952                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1953                                conf->nb_queue_pools == ETH_32_POOLS)) {
1954                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1955                                                 " nb_queue_pools != %d and"
1956                                                 " nb_queue_pools != %d.",
1957                                                 ETH_16_POOLS, ETH_32_POOLS);
1958                                 return -EINVAL;
1959                         }
1960                 }
1961
1962                 /* For DCB mode check our configuration before we go further */
1963                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1964                         const struct rte_eth_dcb_rx_conf *conf;
1965
1966                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1967                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1968                                                  IXGBE_DCB_NB_QUEUES);
1969                                 return -EINVAL;
1970                         }
1971                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1972                         if (!(conf->nb_tcs == ETH_4_TCS ||
1973                                conf->nb_tcs == ETH_8_TCS)) {
1974                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1975                                                 " and nb_tcs != %d.",
1976                                                 ETH_4_TCS, ETH_8_TCS);
1977                                 return -EINVAL;
1978                         }
1979                 }
1980
1981                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1982                         const struct rte_eth_dcb_tx_conf *conf;
1983
1984                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1985                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1986                                                  IXGBE_DCB_NB_QUEUES);
1987                                 return -EINVAL;
1988                         }
1989                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1990                         if (!(conf->nb_tcs == ETH_4_TCS ||
1991                                conf->nb_tcs == ETH_8_TCS)) {
1992                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1993                                                 " and nb_tcs != %d.",
1994                                                 ETH_4_TCS, ETH_8_TCS);
1995                                 return -EINVAL;
1996                         }
1997                 }
1998         }
1999         return 0;
2000 }
2001
2002 static int
2003 ixgbe_dev_configure(struct rte_eth_dev *dev)
2004 {
2005         struct ixgbe_interrupt *intr =
2006                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2007         struct ixgbe_adapter *adapter =
2008                 (struct ixgbe_adapter *)dev->data->dev_private;
2009         int ret;
2010
2011         PMD_INIT_FUNC_TRACE();
2012         /* multipe queue mode checking */
2013         ret  = ixgbe_check_mq_mode(dev);
2014         if (ret != 0) {
2015                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2016                             ret);
2017                 return ret;
2018         }
2019
2020         /* set flag to update link status after init */
2021         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2022
2023         /*
2024          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2025          * allocation or vector Rx preconditions we will reset it.
2026          */
2027         adapter->rx_bulk_alloc_allowed = true;
2028         adapter->rx_vec_allowed = true;
2029
2030         return 0;
2031 }
2032
2033 static void
2034 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2035 {
2036         struct ixgbe_hw *hw =
2037                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038         struct ixgbe_interrupt *intr =
2039                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2040         uint32_t gpie;
2041
2042         /* only set up it on X550EM_X */
2043         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2044                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2045                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2046                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2047                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2048                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2049         }
2050 }
2051
2052 /*
2053  * Configure device link speed and setup link.
2054  * It returns 0 on success.
2055  */
2056 static int
2057 ixgbe_dev_start(struct rte_eth_dev *dev)
2058 {
2059         struct ixgbe_hw *hw =
2060                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2061         struct ixgbe_vf_info *vfinfo =
2062                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2063         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2064         uint32_t intr_vector = 0;
2065         int err, link_up = 0, negotiate = 0;
2066         uint32_t speed = 0;
2067         int mask = 0;
2068         int status;
2069         uint16_t vf, idx;
2070
2071         PMD_INIT_FUNC_TRACE();
2072
2073         /* IXGBE devices don't support half duplex */
2074         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2075                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2076                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2077                              dev->data->dev_conf.link_duplex,
2078                              dev->data->port_id);
2079                 return -EINVAL;
2080         }
2081
2082         /* disable uio/vfio intr/eventfd mapping */
2083         rte_intr_disable(intr_handle);
2084
2085         /* stop adapter */
2086         hw->adapter_stopped = 0;
2087         ixgbe_stop_adapter(hw);
2088
2089         /* reinitialize adapter
2090          * this calls reset and start */
2091         status = ixgbe_pf_reset_hw(hw);
2092         if (status != 0)
2093                 return -1;
2094         hw->mac.ops.start_hw(hw);
2095         hw->mac.get_link_status = true;
2096
2097         /* configure PF module if SRIOV enabled */
2098         ixgbe_pf_host_configure(dev);
2099
2100         ixgbe_dev_phy_intr_setup(dev);
2101
2102         /* check and configure queue intr-vector mapping */
2103         if ((rte_intr_cap_multiple(intr_handle) ||
2104              !RTE_ETH_DEV_SRIOV(dev).active) &&
2105             dev->data->dev_conf.intr_conf.rxq != 0) {
2106                 intr_vector = dev->data->nb_rx_queues;
2107                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2108                         return -1;
2109         }
2110
2111         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2112                 intr_handle->intr_vec =
2113                         rte_zmalloc("intr_vec",
2114                                     dev->data->nb_rx_queues * sizeof(int), 0);
2115                 if (intr_handle->intr_vec == NULL) {
2116                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2117                                      " intr_vec\n", dev->data->nb_rx_queues);
2118                         return -ENOMEM;
2119                 }
2120         }
2121
2122         /* confiugre msix for sleep until rx interrupt */
2123         ixgbe_configure_msix(dev);
2124
2125         /* initialize transmission unit */
2126         ixgbe_dev_tx_init(dev);
2127
2128         /* This can fail when allocating mbufs for descriptor rings */
2129         err = ixgbe_dev_rx_init(dev);
2130         if (err) {
2131                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2132                 goto error;
2133         }
2134
2135         err = ixgbe_dev_rxtx_start(dev);
2136         if (err < 0) {
2137                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2138                 goto error;
2139         }
2140
2141         /* Skip link setup if loopback mode is enabled for 82599. */
2142         if (hw->mac.type == ixgbe_mac_82599EB &&
2143                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2144                 goto skip_link_setup;
2145
2146         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2147                 err = hw->mac.ops.setup_sfp(hw);
2148                 if (err)
2149                         goto error;
2150         }
2151
2152         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2153                 /* Turn on the copper */
2154                 ixgbe_set_phy_power(hw, true);
2155         } else {
2156                 /* Turn on the laser */
2157                 ixgbe_enable_tx_laser(hw);
2158         }
2159
2160         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2161         if (err)
2162                 goto error;
2163         dev->data->dev_link.link_status = link_up;
2164
2165         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2166         if (err)
2167                 goto error;
2168
2169         switch(dev->data->dev_conf.link_speed) {
2170         case ETH_LINK_SPEED_AUTONEG:
2171                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2172                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2173                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2174                 break;
2175         case ETH_LINK_SPEED_100:
2176                 /*
2177                  * Invalid for 82598 but error will be detected by
2178                  * ixgbe_setup_link()
2179                  */
2180                 speed = IXGBE_LINK_SPEED_100_FULL;
2181                 break;
2182         case ETH_LINK_SPEED_1000:
2183                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2184                 break;
2185         case ETH_LINK_SPEED_10000:
2186                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2187                 break;
2188         default:
2189                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2190                              dev->data->dev_conf.link_speed,
2191                              dev->data->port_id);
2192                 goto error;
2193         }
2194
2195         err = ixgbe_setup_link(hw, speed, link_up);
2196         if (err)
2197                 goto error;
2198
2199 skip_link_setup:
2200
2201         if (rte_intr_allow_others(intr_handle)) {
2202                 /* check if lsc interrupt is enabled */
2203                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2204                         ixgbe_dev_lsc_interrupt_setup(dev);
2205         } else {
2206                 rte_intr_callback_unregister(intr_handle,
2207                                              ixgbe_dev_interrupt_handler,
2208                                              (void *)dev);
2209                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2210                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2211                                      " no intr multiplex\n");
2212         }
2213
2214         /* check if rxq interrupt is enabled */
2215         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2216             rte_intr_dp_is_en(intr_handle))
2217                 ixgbe_dev_rxq_interrupt_setup(dev);
2218
2219         /* enable uio/vfio intr/eventfd mapping */
2220         rte_intr_enable(intr_handle);
2221
2222         /* resume enabled intr since hw reset */
2223         ixgbe_enable_intr(dev);
2224
2225         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2226                 ETH_VLAN_EXTEND_MASK;
2227         ixgbe_vlan_offload_set(dev, mask);
2228
2229         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2230                 /* Enable vlan filtering for VMDq */
2231                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2232         }
2233
2234         /* Configure DCB hw */
2235         ixgbe_configure_dcb(dev);
2236
2237         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2238                 err = ixgbe_fdir_configure(dev);
2239                 if (err)
2240                         goto error;
2241         }
2242
2243         /* Restore vf rate limit */
2244         if (vfinfo != NULL) {
2245                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2246                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2247                                 if (vfinfo[vf].tx_rate[idx] != 0)
2248                                         ixgbe_set_vf_rate_limit(dev, vf,
2249                                                 vfinfo[vf].tx_rate[idx],
2250                                                 1 << idx);
2251         }
2252
2253         ixgbe_restore_statistics_mapping(dev);
2254
2255         return 0;
2256
2257 error:
2258         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2259         ixgbe_dev_clear_queues(dev);
2260         return -EIO;
2261 }
2262
2263 /*
2264  * Stop device: disable rx and tx functions to allow for reconfiguring.
2265  */
2266 static void
2267 ixgbe_dev_stop(struct rte_eth_dev *dev)
2268 {
2269         struct rte_eth_link link;
2270         struct ixgbe_hw *hw =
2271                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272         struct ixgbe_vf_info *vfinfo =
2273                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2274         struct ixgbe_filter_info *filter_info =
2275                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2276         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2277         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2278         int vf;
2279
2280         PMD_INIT_FUNC_TRACE();
2281
2282         /* disable interrupts */
2283         ixgbe_disable_intr(hw);
2284
2285         /* reset the NIC */
2286         ixgbe_pf_reset_hw(hw);
2287         hw->adapter_stopped = 0;
2288
2289         /* stop adapter */
2290         ixgbe_stop_adapter(hw);
2291
2292         for (vf = 0; vfinfo != NULL &&
2293                      vf < dev->pci_dev->max_vfs; vf++)
2294                 vfinfo[vf].clear_to_send = false;
2295
2296         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2297                 /* Turn off the copper */
2298                 ixgbe_set_phy_power(hw, false);
2299         } else {
2300                 /* Turn off the laser */
2301                 ixgbe_disable_tx_laser(hw);
2302         }
2303
2304         ixgbe_dev_clear_queues(dev);
2305
2306         /* Clear stored conf */
2307         dev->data->scattered_rx = 0;
2308         dev->data->lro = 0;
2309
2310         /* Clear recorded link status */
2311         memset(&link, 0, sizeof(link));
2312         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2313
2314         /* Remove all ntuple filters of the device */
2315         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2316              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2317                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2318                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2319                              p_5tuple, entries);
2320                 rte_free(p_5tuple);
2321         }
2322         memset(filter_info->fivetuple_mask, 0,
2323                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2324
2325         if (!rte_intr_allow_others(intr_handle))
2326                 /* resume to the default handler */
2327                 rte_intr_callback_register(intr_handle,
2328                                            ixgbe_dev_interrupt_handler,
2329                                            (void *)dev);
2330
2331         /* Clean datapath event and queue/vec mapping */
2332         rte_intr_efd_disable(intr_handle);
2333         if (intr_handle->intr_vec != NULL) {
2334                 rte_free(intr_handle->intr_vec);
2335                 intr_handle->intr_vec = NULL;
2336         }
2337 }
2338
2339 /*
2340  * Set device link up: enable tx.
2341  */
2342 static int
2343 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2344 {
2345         struct ixgbe_hw *hw =
2346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         if (hw->mac.type == ixgbe_mac_82599EB) {
2348 #ifdef RTE_NIC_BYPASS
2349                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2350                         /* Not suported in bypass mode */
2351                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2352                                      "by device id 0x%x", hw->device_id);
2353                         return -ENOTSUP;
2354                 }
2355 #endif
2356         }
2357
2358         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2359                 /* Turn on the copper */
2360                 ixgbe_set_phy_power(hw, true);
2361         } else {
2362                 /* Turn on the laser */
2363                 ixgbe_enable_tx_laser(hw);
2364         }
2365
2366         return 0;
2367 }
2368
2369 /*
2370  * Set device link down: disable tx.
2371  */
2372 static int
2373 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2374 {
2375         struct ixgbe_hw *hw =
2376                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2377         if (hw->mac.type == ixgbe_mac_82599EB) {
2378 #ifdef RTE_NIC_BYPASS
2379                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2380                         /* Not suported in bypass mode */
2381                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2382                                      "by device id 0x%x", hw->device_id);
2383                         return -ENOTSUP;
2384                 }
2385 #endif
2386         }
2387
2388         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2389                 /* Turn off the copper */
2390                 ixgbe_set_phy_power(hw, false);
2391         } else {
2392                 /* Turn off the laser */
2393                 ixgbe_disable_tx_laser(hw);
2394         }
2395
2396         return 0;
2397 }
2398
2399 /*
2400  * Reest and stop device.
2401  */
2402 static void
2403 ixgbe_dev_close(struct rte_eth_dev *dev)
2404 {
2405         struct ixgbe_hw *hw =
2406                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407
2408         PMD_INIT_FUNC_TRACE();
2409
2410         ixgbe_pf_reset_hw(hw);
2411
2412         ixgbe_dev_stop(dev);
2413         hw->adapter_stopped = 1;
2414
2415         ixgbe_dev_free_queues(dev);
2416
2417         ixgbe_disable_pcie_master(hw);
2418
2419         /* reprogram the RAR[0] in case user changed it. */
2420         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2421 }
2422
2423 static void
2424 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2425                            struct ixgbe_hw_stats *hw_stats,
2426                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2427                            uint64_t *total_qprc, uint64_t *total_qprdc)
2428 {
2429         uint32_t bprc, lxon, lxoff, total;
2430         uint32_t delta_gprc = 0;
2431         unsigned i;
2432         /* Workaround for RX byte count not including CRC bytes when CRC
2433 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2434          * is disabled.
2435 +        */
2436         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2437                         IXGBE_HLREG0_RXCRCSTRP);
2438
2439         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2440         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2441         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2442         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2443
2444         for (i = 0; i < 8; i++) {
2445                 uint32_t mp;
2446                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2447                 /* global total per queue */
2448                 hw_stats->mpc[i] += mp;
2449                 /* Running comprehensive total for stats display */
2450                 *total_missed_rx += hw_stats->mpc[i];
2451                 if (hw->mac.type == ixgbe_mac_82598EB) {
2452                         hw_stats->rnbc[i] +=
2453                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2454                         hw_stats->pxonrxc[i] +=
2455                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2456                         hw_stats->pxoffrxc[i] +=
2457                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2458                 } else {
2459                         hw_stats->pxonrxc[i] +=
2460                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2461                         hw_stats->pxoffrxc[i] +=
2462                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2463                         hw_stats->pxon2offc[i] +=
2464                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2465                 }
2466                 hw_stats->pxontxc[i] +=
2467                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2468                 hw_stats->pxofftxc[i] +=
2469                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2470         }
2471         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2472                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2473                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2474                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2475
2476                 delta_gprc += delta_qprc;
2477
2478                 hw_stats->qprc[i] += delta_qprc;
2479                 hw_stats->qptc[i] += delta_qptc;
2480
2481                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2482                 hw_stats->qbrc[i] +=
2483                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2484                 if (crc_strip == 0)
2485                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2486
2487                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2488                 hw_stats->qbtc[i] +=
2489                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2490
2491                 hw_stats->qprdc[i] += delta_qprdc;
2492                 *total_qprdc += hw_stats->qprdc[i];
2493
2494                 *total_qprc += hw_stats->qprc[i];
2495                 *total_qbrc += hw_stats->qbrc[i];
2496         }
2497         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2498         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2499         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2500
2501         /*
2502          * An errata states that gprc actually counts good + missed packets:
2503          * Workaround to set gprc to summated queue packet receives
2504          */
2505         hw_stats->gprc = *total_qprc;
2506
2507         if (hw->mac.type != ixgbe_mac_82598EB) {
2508                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2509                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2510                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2511                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2512                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2513                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2514                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2515                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2516         } else {
2517                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2518                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2519                 /* 82598 only has a counter in the high register */
2520                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2521                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2522                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2523         }
2524         uint64_t old_tpr = hw_stats->tpr;
2525
2526         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2527         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2528
2529         if (crc_strip == 0)
2530                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2531
2532         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2533         hw_stats->gptc += delta_gptc;
2534         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2535         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2536
2537         /*
2538          * Workaround: mprc hardware is incorrectly counting
2539          * broadcasts, so for now we subtract those.
2540          */
2541         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2542         hw_stats->bprc += bprc;
2543         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2544         if (hw->mac.type == ixgbe_mac_82598EB)
2545                 hw_stats->mprc -= bprc;
2546
2547         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2548         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2549         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2550         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2551         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2552         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2553
2554         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2555         hw_stats->lxontxc += lxon;
2556         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2557         hw_stats->lxofftxc += lxoff;
2558         total = lxon + lxoff;
2559
2560         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2561         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2562         hw_stats->gptc -= total;
2563         hw_stats->mptc -= total;
2564         hw_stats->ptc64 -= total;
2565         hw_stats->gotc -= total * ETHER_MIN_LEN;
2566
2567         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2568         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2569         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2570         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2571         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2572         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2573         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2574         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2575         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2576         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2577         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2578         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2579         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2580         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2581         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2582         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2583         /* Only read FCOE on 82599 */
2584         if (hw->mac.type != ixgbe_mac_82598EB) {
2585                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2586                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2587                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2588                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2589                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2590         }
2591
2592         /* Flow Director Stats registers */
2593         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2594         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2595 }
2596
2597 /*
2598  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2599  */
2600 static void
2601 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2602 {
2603         struct ixgbe_hw *hw =
2604                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605         struct ixgbe_hw_stats *hw_stats =
2606                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2607         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2608         unsigned i;
2609
2610         total_missed_rx = 0;
2611         total_qbrc = 0;
2612         total_qprc = 0;
2613         total_qprdc = 0;
2614
2615         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2616                         &total_qprc, &total_qprdc);
2617
2618         if (stats == NULL)
2619                 return;
2620
2621         /* Fill out the rte_eth_stats statistics structure */
2622         stats->ipackets = total_qprc;
2623         stats->ibytes = total_qbrc;
2624         stats->opackets = hw_stats->gptc;
2625         stats->obytes = hw_stats->gotc;
2626
2627         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2628                 stats->q_ipackets[i] = hw_stats->qprc[i];
2629                 stats->q_opackets[i] = hw_stats->qptc[i];
2630                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2631                 stats->q_obytes[i] = hw_stats->qbtc[i];
2632                 stats->q_errors[i] = hw_stats->qprdc[i];
2633         }
2634
2635         /* Rx Errors */
2636         stats->imissed  = total_missed_rx;
2637         stats->ierrors  = hw_stats->crcerrs +
2638                           hw_stats->mspdc +
2639                           hw_stats->rlec +
2640                           hw_stats->ruc +
2641                           hw_stats->roc +
2642                           total_missed_rx +
2643                           hw_stats->illerrc +
2644                           hw_stats->errbc +
2645                           hw_stats->rfc +
2646                           hw_stats->fccrc +
2647                           hw_stats->fclast;
2648
2649         /* Tx Errors */
2650         stats->oerrors  = 0;
2651 }
2652
2653 static void
2654 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2655 {
2656         struct ixgbe_hw_stats *stats =
2657                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2658
2659         /* HW registers are cleared on read */
2660         ixgbe_dev_stats_get(dev, NULL);
2661
2662         /* Reset software totals */
2663         memset(stats, 0, sizeof(*stats));
2664 }
2665
2666 /* This function calculates the number of xstats based on the current config */
2667 static unsigned
2668 ixgbe_xstats_calc_num(void) {
2669         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2670                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2671 }
2672
2673 static int
2674 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2675                                          unsigned n)
2676 {
2677         struct ixgbe_hw *hw =
2678                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2679         struct ixgbe_hw_stats *hw_stats =
2680                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2681         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2682         unsigned i, stat, count = 0;
2683
2684         count = ixgbe_xstats_calc_num();
2685
2686         if (n < count)
2687                 return count;
2688
2689         total_missed_rx = 0;
2690         total_qbrc = 0;
2691         total_qprc = 0;
2692         total_qprdc = 0;
2693
2694         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2695                                    &total_qprc, &total_qprdc);
2696
2697         /* If this is a reset xstats is NULL, and we have cleared the
2698          * registers by reading them.
2699          */
2700         if (!xstats)
2701                 return 0;
2702
2703         /* Extended stats from ixgbe_hw_stats */
2704         count = 0;
2705         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2706                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2707                          rte_ixgbe_stats_strings[i].name);
2708                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2709                                 rte_ixgbe_stats_strings[i].offset);
2710                 count++;
2711         }
2712
2713         /* RX Priority Stats */
2714         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2715                 for (i = 0; i < 8; i++) {
2716                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2717                                  "rx_priority%u_%s", i,
2718                                  rte_ixgbe_rxq_strings[stat].name);
2719                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2720                                         rte_ixgbe_rxq_strings[stat].offset +
2721                                         (sizeof(uint64_t) * i));
2722                         count++;
2723                 }
2724         }
2725
2726         /* TX Priority Stats */
2727         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2728                 for (i = 0; i < 8; i++) {
2729                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2730                                  "tx_priority%u_%s", i,
2731                                  rte_ixgbe_txq_strings[stat].name);
2732                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2733                                         rte_ixgbe_txq_strings[stat].offset +
2734                                         (sizeof(uint64_t) * i));
2735                         count++;
2736                 }
2737         }
2738
2739         return count;
2740 }
2741
2742 static void
2743 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2744 {
2745         struct ixgbe_hw_stats *stats =
2746                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2747
2748         unsigned count = ixgbe_xstats_calc_num();
2749
2750         /* HW registers are cleared on read */
2751         ixgbe_dev_xstats_get(dev, NULL, count);
2752
2753         /* Reset software totals */
2754         memset(stats, 0, sizeof(*stats));
2755 }
2756
2757 static void
2758 ixgbevf_update_stats(struct rte_eth_dev *dev)
2759 {
2760         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2761         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2762                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2763
2764         /* Good Rx packet, include VF loopback */
2765         UPDATE_VF_STAT(IXGBE_VFGPRC,
2766             hw_stats->last_vfgprc, hw_stats->vfgprc);
2767
2768         /* Good Rx octets, include VF loopback */
2769         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2770             hw_stats->last_vfgorc, hw_stats->vfgorc);
2771
2772         /* Good Tx packet, include VF loopback */
2773         UPDATE_VF_STAT(IXGBE_VFGPTC,
2774             hw_stats->last_vfgptc, hw_stats->vfgptc);
2775
2776         /* Good Tx octets, include VF loopback */
2777         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2778             hw_stats->last_vfgotc, hw_stats->vfgotc);
2779
2780         /* Rx Multicst Packet */
2781         UPDATE_VF_STAT(IXGBE_VFMPRC,
2782             hw_stats->last_vfmprc, hw_stats->vfmprc);
2783 }
2784
2785 static int
2786 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2787                        unsigned n)
2788 {
2789         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2790                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2791         unsigned i;
2792
2793         if (n < IXGBEVF_NB_XSTATS)
2794                 return IXGBEVF_NB_XSTATS;
2795
2796         ixgbevf_update_stats(dev);
2797
2798         if (!xstats)
2799                 return 0;
2800
2801         /* Extended stats */
2802         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2803                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2804                          "%s", rte_ixgbevf_stats_strings[i].name);
2805                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2806                         rte_ixgbevf_stats_strings[i].offset);
2807         }
2808
2809         return IXGBEVF_NB_XSTATS;
2810 }
2811
2812 static void
2813 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2814 {
2815         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2816                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2817
2818         ixgbevf_update_stats(dev);
2819
2820         if (stats == NULL)
2821                 return;
2822
2823         stats->ipackets = hw_stats->vfgprc;
2824         stats->ibytes = hw_stats->vfgorc;
2825         stats->opackets = hw_stats->vfgptc;
2826         stats->obytes = hw_stats->vfgotc;
2827         stats->imcasts = hw_stats->vfmprc;
2828         /* stats->imcasts should be removed as imcasts is deprecated */
2829 }
2830
2831 static void
2832 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2833 {
2834         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2835                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2836
2837         /* Sync HW register to the last stats */
2838         ixgbevf_dev_stats_get(dev, NULL);
2839
2840         /* reset HW current stats*/
2841         hw_stats->vfgprc = 0;
2842         hw_stats->vfgorc = 0;
2843         hw_stats->vfgptc = 0;
2844         hw_stats->vfgotc = 0;
2845         hw_stats->vfmprc = 0;
2846
2847 }
2848
2849 static void
2850 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2851 {
2852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2853
2854         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2855         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2856         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2857         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2858         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2859         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2860         dev_info->max_vfs = dev->pci_dev->max_vfs;
2861         if (hw->mac.type == ixgbe_mac_82598EB)
2862                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2863         else
2864                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2865         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2866         dev_info->rx_offload_capa =
2867                 DEV_RX_OFFLOAD_VLAN_STRIP |
2868                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2869                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2870                 DEV_RX_OFFLOAD_TCP_CKSUM;
2871
2872         /*
2873          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2874          * mode.
2875          */
2876         if ((hw->mac.type == ixgbe_mac_82599EB ||
2877              hw->mac.type == ixgbe_mac_X540) &&
2878             !RTE_ETH_DEV_SRIOV(dev).active)
2879                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2880
2881         if (hw->mac.type == ixgbe_mac_X550 ||
2882             hw->mac.type == ixgbe_mac_X550EM_x)
2883                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2884
2885         dev_info->tx_offload_capa =
2886                 DEV_TX_OFFLOAD_VLAN_INSERT |
2887                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2888                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2889                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2890                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2891                 DEV_TX_OFFLOAD_TCP_TSO;
2892
2893         if (hw->mac.type == ixgbe_mac_X550 ||
2894             hw->mac.type == ixgbe_mac_X550EM_x)
2895                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2896
2897         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2898                 .rx_thresh = {
2899                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2900                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2901                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2902                 },
2903                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2904                 .rx_drop_en = 0,
2905         };
2906
2907         dev_info->default_txconf = (struct rte_eth_txconf) {
2908                 .tx_thresh = {
2909                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2910                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2911                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2912                 },
2913                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2914                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2915                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2916                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2917         };
2918
2919         dev_info->rx_desc_lim = rx_desc_lim;
2920         dev_info->tx_desc_lim = tx_desc_lim;
2921
2922         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2923         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2924         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2925 }
2926
2927 static void
2928 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2929                      struct rte_eth_dev_info *dev_info)
2930 {
2931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2932
2933         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2934         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2935         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2936         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2937         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2938         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2939         dev_info->max_vfs = dev->pci_dev->max_vfs;
2940         if (hw->mac.type == ixgbe_mac_82598EB)
2941                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2942         else
2943                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2944         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2945                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2946                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2947                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2948         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2949                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2950                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2951                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2952                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2953                                 DEV_TX_OFFLOAD_TCP_TSO;
2954
2955         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2956                 .rx_thresh = {
2957                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2958                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2959                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2960                 },
2961                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2962                 .rx_drop_en = 0,
2963         };
2964
2965         dev_info->default_txconf = (struct rte_eth_txconf) {
2966                 .tx_thresh = {
2967                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2968                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2969                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2970                 },
2971                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2972                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2973                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2974                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2975         };
2976
2977         dev_info->rx_desc_lim = rx_desc_lim;
2978         dev_info->tx_desc_lim = tx_desc_lim;
2979 }
2980
2981 /* return 0 means link status changed, -1 means not changed */
2982 static int
2983 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2984 {
2985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986         struct rte_eth_link link, old;
2987         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2988         int link_up;
2989         int diag;
2990
2991         link.link_status = 0;
2992         link.link_speed = 0;
2993         link.link_duplex = 0;
2994         memset(&old, 0, sizeof(old));
2995         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2996
2997         hw->mac.get_link_status = true;
2998
2999         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3000         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3001                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3002         else
3003                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3004
3005         if (diag != 0) {
3006                 link.link_speed = ETH_LINK_SPEED_100;
3007                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3008                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3009                 if (link.link_status == old.link_status)
3010                         return -1;
3011                 return 0;
3012         }
3013
3014         if (link_up == 0) {
3015                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3016                 if (link.link_status == old.link_status)
3017                         return -1;
3018                 return 0;
3019         }
3020         link.link_status = 1;
3021         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3022
3023         switch (link_speed) {
3024         default:
3025         case IXGBE_LINK_SPEED_UNKNOWN:
3026                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3027                 link.link_speed = ETH_LINK_SPEED_100;
3028                 break;
3029
3030         case IXGBE_LINK_SPEED_100_FULL:
3031                 link.link_speed = ETH_LINK_SPEED_100;
3032                 break;
3033
3034         case IXGBE_LINK_SPEED_1GB_FULL:
3035                 link.link_speed = ETH_LINK_SPEED_1000;
3036                 break;
3037
3038         case IXGBE_LINK_SPEED_10GB_FULL:
3039                 link.link_speed = ETH_LINK_SPEED_10000;
3040                 break;
3041         }
3042         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3043
3044         if (link.link_status == old.link_status)
3045                 return -1;
3046
3047         return 0;
3048 }
3049
3050 static void
3051 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3052 {
3053         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3054         uint32_t fctrl;
3055
3056         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3057         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3058         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3059 }
3060
3061 static void
3062 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3063 {
3064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3065         uint32_t fctrl;
3066
3067         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3068         fctrl &= (~IXGBE_FCTRL_UPE);
3069         if (dev->data->all_multicast == 1)
3070                 fctrl |= IXGBE_FCTRL_MPE;
3071         else
3072                 fctrl &= (~IXGBE_FCTRL_MPE);
3073         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3074 }
3075
3076 static void
3077 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3078 {
3079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080         uint32_t fctrl;
3081
3082         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3083         fctrl |= IXGBE_FCTRL_MPE;
3084         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3085 }
3086
3087 static void
3088 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3089 {
3090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091         uint32_t fctrl;
3092
3093         if (dev->data->promiscuous == 1)
3094                 return; /* must remain in all_multicast mode */
3095
3096         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3097         fctrl &= (~IXGBE_FCTRL_MPE);
3098         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3099 }
3100
3101 /**
3102  * It clears the interrupt causes and enables the interrupt.
3103  * It will be called once only during nic initialized.
3104  *
3105  * @param dev
3106  *  Pointer to struct rte_eth_dev.
3107  *
3108  * @return
3109  *  - On success, zero.
3110  *  - On failure, a negative value.
3111  */
3112 static int
3113 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3114 {
3115         struct ixgbe_interrupt *intr =
3116                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3117
3118         ixgbe_dev_link_status_print(dev);
3119         intr->mask |= IXGBE_EICR_LSC;
3120
3121         return 0;
3122 }
3123
3124 /**
3125  * It clears the interrupt causes and enables the interrupt.
3126  * It will be called once only during nic initialized.
3127  *
3128  * @param dev
3129  *  Pointer to struct rte_eth_dev.
3130  *
3131  * @return
3132  *  - On success, zero.
3133  *  - On failure, a negative value.
3134  */
3135 static int
3136 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3137 {
3138         struct ixgbe_interrupt *intr =
3139                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3140
3141         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3142
3143         return 0;
3144 }
3145
3146 /*
3147  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3148  *
3149  * @param dev
3150  *  Pointer to struct rte_eth_dev.
3151  *
3152  * @return
3153  *  - On success, zero.
3154  *  - On failure, a negative value.
3155  */
3156 static int
3157 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3158 {
3159         uint32_t eicr;
3160         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3161         struct ixgbe_interrupt *intr =
3162                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3163
3164         /* clear all cause mask */
3165         ixgbe_disable_intr(hw);
3166
3167         /* read-on-clear nic registers here */
3168         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3169         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3170
3171         intr->flags = 0;
3172
3173         /* set flag for async link update */
3174         if (eicr & IXGBE_EICR_LSC)
3175                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3176
3177         if (eicr & IXGBE_EICR_MAILBOX)
3178                 intr->flags |= IXGBE_FLAG_MAILBOX;
3179
3180         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3181             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3182             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3183                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3184
3185         return 0;
3186 }
3187
3188 /**
3189  * It gets and then prints the link status.
3190  *
3191  * @param dev
3192  *  Pointer to struct rte_eth_dev.
3193  *
3194  * @return
3195  *  - On success, zero.
3196  *  - On failure, a negative value.
3197  */
3198 static void
3199 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3200 {
3201         struct rte_eth_link link;
3202
3203         memset(&link, 0, sizeof(link));
3204         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3205         if (link.link_status) {
3206                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3207                                         (int)(dev->data->port_id),
3208                                         (unsigned)link.link_speed,
3209                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3210                                         "full-duplex" : "half-duplex");
3211         } else {
3212                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3213                                 (int)(dev->data->port_id));
3214         }
3215         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3216                                 dev->pci_dev->addr.domain,
3217                                 dev->pci_dev->addr.bus,
3218                                 dev->pci_dev->addr.devid,
3219                                 dev->pci_dev->addr.function);
3220 }
3221
3222 /*
3223  * It executes link_update after knowing an interrupt occurred.
3224  *
3225  * @param dev
3226  *  Pointer to struct rte_eth_dev.
3227  *
3228  * @return
3229  *  - On success, zero.
3230  *  - On failure, a negative value.
3231  */
3232 static int
3233 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3234 {
3235         struct ixgbe_interrupt *intr =
3236                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3237         int64_t timeout;
3238         struct rte_eth_link link;
3239         int intr_enable_delay = false;
3240         struct ixgbe_hw *hw =
3241                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3242
3243         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3244
3245         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3246                 ixgbe_pf_mbx_process(dev);
3247                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3248         }
3249
3250         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3251                 ixgbe_handle_lasi(hw);
3252                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3253         }
3254
3255         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3256                 /* get the link status before link update, for predicting later */
3257                 memset(&link, 0, sizeof(link));
3258                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3259
3260                 ixgbe_dev_link_update(dev, 0);
3261
3262                 /* likely to up */
3263                 if (!link.link_status)
3264                         /* handle it 1 sec later, wait it being stable */
3265                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3266                 /* likely to down */
3267                 else
3268                         /* handle it 4 sec later, wait it being stable */
3269                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3270
3271                 ixgbe_dev_link_status_print(dev);
3272
3273                 intr_enable_delay = true;
3274         }
3275
3276         if (intr_enable_delay) {
3277                 if (rte_eal_alarm_set(timeout * 1000,
3278                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3279                         PMD_DRV_LOG(ERR, "Error setting alarm");
3280         } else {
3281                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3282                 ixgbe_enable_intr(dev);
3283                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3284         }
3285
3286
3287         return 0;
3288 }
3289
3290 /**
3291  * Interrupt handler which shall be registered for alarm callback for delayed
3292  * handling specific interrupt to wait for the stable nic state. As the
3293  * NIC interrupt state is not stable for ixgbe after link is just down,
3294  * it needs to wait 4 seconds to get the stable status.
3295  *
3296  * @param handle
3297  *  Pointer to interrupt handle.
3298  * @param param
3299  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3300  *
3301  * @return
3302  *  void
3303  */
3304 static void
3305 ixgbe_dev_interrupt_delayed_handler(void *param)
3306 {
3307         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3308         struct ixgbe_interrupt *intr =
3309                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3310         struct ixgbe_hw *hw =
3311                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312         uint32_t eicr;
3313
3314         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3315         if (eicr & IXGBE_EICR_MAILBOX)
3316                 ixgbe_pf_mbx_process(dev);
3317
3318         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3319                 ixgbe_handle_lasi(hw);
3320                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3321         }
3322
3323         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3324                 ixgbe_dev_link_update(dev, 0);
3325                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3326                 ixgbe_dev_link_status_print(dev);
3327                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3328         }
3329
3330         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3331         ixgbe_enable_intr(dev);
3332         rte_intr_enable(&(dev->pci_dev->intr_handle));
3333 }
3334
3335 /**
3336  * Interrupt handler triggered by NIC  for handling
3337  * specific interrupt.
3338  *
3339  * @param handle
3340  *  Pointer to interrupt handle.
3341  * @param param
3342  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3343  *
3344  * @return
3345  *  void
3346  */
3347 static void
3348 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3349                             void *param)
3350 {
3351         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3352
3353         ixgbe_dev_interrupt_get_status(dev);
3354         ixgbe_dev_interrupt_action(dev);
3355 }
3356
3357 static int
3358 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3359 {
3360         struct ixgbe_hw *hw;
3361
3362         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3363         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3364 }
3365
3366 static int
3367 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3368 {
3369         struct ixgbe_hw *hw;
3370
3371         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3372         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3373 }
3374
3375 static int
3376 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3377 {
3378         struct ixgbe_hw *hw;
3379         uint32_t mflcn_reg;
3380         uint32_t fccfg_reg;
3381         int rx_pause;
3382         int tx_pause;
3383
3384         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3385
3386         fc_conf->pause_time = hw->fc.pause_time;
3387         fc_conf->high_water = hw->fc.high_water[0];
3388         fc_conf->low_water = hw->fc.low_water[0];
3389         fc_conf->send_xon = hw->fc.send_xon;
3390         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3391
3392         /*
3393          * Return rx_pause status according to actual setting of
3394          * MFLCN register.
3395          */
3396         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3397         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3398                 rx_pause = 1;
3399         else
3400                 rx_pause = 0;
3401
3402         /*
3403          * Return tx_pause status according to actual setting of
3404          * FCCFG register.
3405          */
3406         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3407         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3408                 tx_pause = 1;
3409         else
3410                 tx_pause = 0;
3411
3412         if (rx_pause && tx_pause)
3413                 fc_conf->mode = RTE_FC_FULL;
3414         else if (rx_pause)
3415                 fc_conf->mode = RTE_FC_RX_PAUSE;
3416         else if (tx_pause)
3417                 fc_conf->mode = RTE_FC_TX_PAUSE;
3418         else
3419                 fc_conf->mode = RTE_FC_NONE;
3420
3421         return 0;
3422 }
3423
3424 static int
3425 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3426 {
3427         struct ixgbe_hw *hw;
3428         int err;
3429         uint32_t rx_buf_size;
3430         uint32_t max_high_water;
3431         uint32_t mflcn;
3432         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3433                 ixgbe_fc_none,
3434                 ixgbe_fc_rx_pause,
3435                 ixgbe_fc_tx_pause,
3436                 ixgbe_fc_full
3437         };
3438
3439         PMD_INIT_FUNC_TRACE();
3440
3441         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3443         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3444
3445         /*
3446          * At least reserve one Ethernet frame for watermark
3447          * high_water/low_water in kilo bytes for ixgbe
3448          */
3449         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3450         if ((fc_conf->high_water > max_high_water) ||
3451                 (fc_conf->high_water < fc_conf->low_water)) {
3452                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3453                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3454                 return -EINVAL;
3455         }
3456
3457         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3458         hw->fc.pause_time     = fc_conf->pause_time;
3459         hw->fc.high_water[0]  = fc_conf->high_water;
3460         hw->fc.low_water[0]   = fc_conf->low_water;
3461         hw->fc.send_xon       = fc_conf->send_xon;
3462         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3463
3464         err = ixgbe_fc_enable(hw);
3465
3466         /* Not negotiated is not an error case */
3467         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3468
3469                 /* check if we want to forward MAC frames - driver doesn't have native
3470                  * capability to do that, so we'll write the registers ourselves */
3471
3472                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3473
3474                 /* set or clear MFLCN.PMCF bit depending on configuration */
3475                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3476                         mflcn |= IXGBE_MFLCN_PMCF;
3477                 else
3478                         mflcn &= ~IXGBE_MFLCN_PMCF;
3479
3480                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3481                 IXGBE_WRITE_FLUSH(hw);
3482
3483                 return 0;
3484         }
3485
3486         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3487         return -EIO;
3488 }
3489
3490 /**
3491  *  ixgbe_pfc_enable_generic - Enable flow control
3492  *  @hw: pointer to hardware structure
3493  *  @tc_num: traffic class number
3494  *  Enable flow control according to the current settings.
3495  */
3496 static int
3497 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3498 {
3499         int ret_val = 0;
3500         uint32_t mflcn_reg, fccfg_reg;
3501         uint32_t reg;
3502         uint32_t fcrtl, fcrth;
3503         uint8_t i;
3504         uint8_t nb_rx_en;
3505
3506         /* Validate the water mark configuration */
3507         if (!hw->fc.pause_time) {
3508                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3509                 goto out;
3510         }
3511
3512         /* Low water mark of zero causes XOFF floods */
3513         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3514                  /* High/Low water can not be 0 */
3515                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3516                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3517                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3518                         goto out;
3519                 }
3520
3521                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3522                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3523                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3524                         goto out;
3525                 }
3526         }
3527         /* Negotiate the fc mode to use */
3528         ixgbe_fc_autoneg(hw);
3529
3530         /* Disable any previous flow control settings */
3531         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3532         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3533
3534         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3535         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3536
3537         switch (hw->fc.current_mode) {
3538         case ixgbe_fc_none:
3539                 /*
3540                  * If the count of enabled RX Priority Flow control >1,
3541                  * and the TX pause can not be disabled
3542                  */
3543                 nb_rx_en = 0;
3544                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3545                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3546                         if (reg & IXGBE_FCRTH_FCEN)
3547                                 nb_rx_en++;
3548                 }
3549                 if (nb_rx_en > 1)
3550                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3551                 break;
3552         case ixgbe_fc_rx_pause:
3553                 /*
3554                  * Rx Flow control is enabled and Tx Flow control is
3555                  * disabled by software override. Since there really
3556                  * isn't a way to advertise that we are capable of RX
3557                  * Pause ONLY, we will advertise that we support both
3558                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3559                  * disable the adapter's ability to send PAUSE frames.
3560                  */
3561                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3562                 /*
3563                  * If the count of enabled RX Priority Flow control >1,
3564                  * and the TX pause can not be disabled
3565                  */
3566                 nb_rx_en = 0;
3567                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3568                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3569                         if (reg & IXGBE_FCRTH_FCEN)
3570                                 nb_rx_en++;
3571                 }
3572                 if (nb_rx_en > 1)
3573                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3574                 break;
3575         case ixgbe_fc_tx_pause:
3576                 /*
3577                  * Tx Flow control is enabled, and Rx Flow control is
3578                  * disabled by software override.
3579                  */
3580                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3581                 break;
3582         case ixgbe_fc_full:
3583                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3584                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3585                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3586                 break;
3587         default:
3588                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3589                 ret_val = IXGBE_ERR_CONFIG;
3590                 goto out;
3591                 break;
3592         }
3593
3594         /* Set 802.3x based flow control settings. */
3595         mflcn_reg |= IXGBE_MFLCN_DPF;
3596         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3597         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3598
3599         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3600         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3601                 hw->fc.high_water[tc_num]) {
3602                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3603                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3604                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3605         } else {
3606                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3607                 /*
3608                  * In order to prevent Tx hangs when the internal Tx
3609                  * switch is enabled we must set the high water mark
3610                  * to the maximum FCRTH value.  This allows the Tx
3611                  * switch to function even under heavy Rx workloads.
3612                  */
3613                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3614         }
3615         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3616
3617         /* Configure pause time (2 TCs per register) */
3618         reg = hw->fc.pause_time * 0x00010001;
3619         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3620                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3621
3622         /* Configure flow control refresh threshold value */
3623         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3624
3625 out:
3626         return ret_val;
3627 }
3628
3629 static int
3630 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3631 {
3632         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3634
3635         if (hw->mac.type != ixgbe_mac_82598EB) {
3636                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3637         }
3638         return ret_val;
3639 }
3640
3641 static int
3642 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3643 {
3644         int err;
3645         uint32_t rx_buf_size;
3646         uint32_t max_high_water;
3647         uint8_t tc_num;
3648         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3649         struct ixgbe_hw *hw =
3650                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3651         struct ixgbe_dcb_config *dcb_config =
3652                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3653
3654         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3655                 ixgbe_fc_none,
3656                 ixgbe_fc_rx_pause,
3657                 ixgbe_fc_tx_pause,
3658                 ixgbe_fc_full
3659         };
3660
3661         PMD_INIT_FUNC_TRACE();
3662
3663         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3664         tc_num = map[pfc_conf->priority];
3665         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3666         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3667         /*
3668          * At least reserve one Ethernet frame for watermark
3669          * high_water/low_water in kilo bytes for ixgbe
3670          */
3671         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3672         if ((pfc_conf->fc.high_water > max_high_water) ||
3673             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3674                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3675                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3676                 return -EINVAL;
3677         }
3678
3679         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3680         hw->fc.pause_time = pfc_conf->fc.pause_time;
3681         hw->fc.send_xon = pfc_conf->fc.send_xon;
3682         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3683         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3684
3685         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3686
3687         /* Not negotiated is not an error case */
3688         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3689                 return 0;
3690
3691         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3692         return -EIO;
3693 }
3694
3695 static int
3696 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3697                           struct rte_eth_rss_reta_entry64 *reta_conf,
3698                           uint16_t reta_size)
3699 {
3700         uint8_t i, j, mask;
3701         uint32_t reta, r;
3702         uint16_t idx, shift;
3703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3704         uint16_t sp_reta_size;
3705         uint32_t reta_reg;
3706
3707         PMD_INIT_FUNC_TRACE();
3708
3709         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3710                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3711                         "NIC.");
3712                 return -ENOTSUP;
3713         }
3714
3715         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3716         if (reta_size != sp_reta_size) {
3717                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3718                         "(%d) doesn't match the number hardware can supported "
3719                         "(%d)\n", reta_size, sp_reta_size);
3720                 return -EINVAL;
3721         }
3722
3723         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3724                 idx = i / RTE_RETA_GROUP_SIZE;
3725                 shift = i % RTE_RETA_GROUP_SIZE;
3726                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3727                                                 IXGBE_4_BIT_MASK);
3728                 if (!mask)
3729                         continue;
3730                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3731                 if (mask == IXGBE_4_BIT_MASK)
3732                         r = 0;
3733                 else
3734                         r = IXGBE_READ_REG(hw, reta_reg);
3735                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3736                         if (mask & (0x1 << j))
3737                                 reta |= reta_conf[idx].reta[shift + j] <<
3738                                                         (CHAR_BIT * j);
3739                         else
3740                                 reta |= r & (IXGBE_8_BIT_MASK <<
3741                                                 (CHAR_BIT * j));
3742                 }
3743                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3744         }
3745
3746         return 0;
3747 }
3748
3749 static int
3750 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3751                          struct rte_eth_rss_reta_entry64 *reta_conf,
3752                          uint16_t reta_size)
3753 {
3754         uint8_t i, j, mask;
3755         uint32_t reta;
3756         uint16_t idx, shift;
3757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3758         uint16_t sp_reta_size;
3759         uint32_t reta_reg;
3760
3761         PMD_INIT_FUNC_TRACE();
3762         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3763         if (reta_size != sp_reta_size) {
3764                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3765                         "(%d) doesn't match the number hardware can supported "
3766                         "(%d)\n", reta_size, sp_reta_size);
3767                 return -EINVAL;
3768         }
3769
3770         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3771                 idx = i / RTE_RETA_GROUP_SIZE;
3772                 shift = i % RTE_RETA_GROUP_SIZE;
3773                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3774                                                 IXGBE_4_BIT_MASK);
3775                 if (!mask)
3776                         continue;
3777
3778                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3779                 reta = IXGBE_READ_REG(hw, reta_reg);
3780                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3781                         if (mask & (0x1 << j))
3782                                 reta_conf[idx].reta[shift + j] =
3783                                         ((reta >> (CHAR_BIT * j)) &
3784                                                 IXGBE_8_BIT_MASK);
3785                 }
3786         }
3787
3788         return 0;
3789 }
3790
3791 static void
3792 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3793                                 uint32_t index, uint32_t pool)
3794 {
3795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796         uint32_t enable_addr = 1;
3797
3798         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3799 }
3800
3801 static void
3802 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3803 {
3804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3805
3806         ixgbe_clear_rar(hw, index);
3807 }
3808
3809 static void
3810 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3811 {
3812         ixgbe_remove_rar(dev, 0);
3813
3814         ixgbe_add_rar(dev, addr, 0, 0);
3815 }
3816
3817 static int
3818 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3819 {
3820         uint32_t hlreg0;
3821         uint32_t maxfrs;
3822         struct ixgbe_hw *hw;
3823         struct rte_eth_dev_info dev_info;
3824         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3825
3826         ixgbe_dev_info_get(dev, &dev_info);
3827
3828         /* check that mtu is within the allowed range */
3829         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3830                 return -EINVAL;
3831
3832         /* refuse mtu that requires the support of scattered packets when this
3833          * feature has not been enabled before. */
3834         if (!dev->data->scattered_rx &&
3835             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3836              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3837                 return -EINVAL;
3838
3839         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3840         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3841
3842         /* switch to jumbo mode if needed */
3843         if (frame_size > ETHER_MAX_LEN) {
3844                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3845                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3846         } else {
3847                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3848                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3849         }
3850         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3851
3852         /* update max frame size */
3853         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3854
3855         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3856         maxfrs &= 0x0000FFFF;
3857         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3858         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3859
3860         return 0;
3861 }
3862
3863 /*
3864  * Virtual Function operations
3865  */
3866 static void
3867 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3868 {
3869         PMD_INIT_FUNC_TRACE();
3870
3871         /* Clear interrupt mask to stop from interrupts being generated */
3872         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3873
3874         IXGBE_WRITE_FLUSH(hw);
3875 }
3876
3877 static void
3878 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3879 {
3880         PMD_INIT_FUNC_TRACE();
3881
3882         /* VF enable interrupt autoclean */
3883         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3884         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3885         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3886
3887         IXGBE_WRITE_FLUSH(hw);
3888 }
3889
3890 static int
3891 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3892 {
3893         struct rte_eth_conf* conf = &dev->data->dev_conf;
3894         struct ixgbe_adapter *adapter =
3895                         (struct ixgbe_adapter *)dev->data->dev_private;
3896
3897         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3898                      dev->data->port_id);
3899
3900         /*
3901          * VF has no ability to enable/disable HW CRC
3902          * Keep the persistent behavior the same as Host PF
3903          */
3904 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3905         if (!conf->rxmode.hw_strip_crc) {
3906                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3907                 conf->rxmode.hw_strip_crc = 1;
3908         }
3909 #else
3910         if (conf->rxmode.hw_strip_crc) {
3911                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3912                 conf->rxmode.hw_strip_crc = 0;
3913         }
3914 #endif
3915
3916         /*
3917          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3918          * allocation or vector Rx preconditions we will reset it.
3919          */
3920         adapter->rx_bulk_alloc_allowed = true;
3921         adapter->rx_vec_allowed = true;
3922
3923         return 0;
3924 }
3925
3926 static int
3927 ixgbevf_dev_start(struct rte_eth_dev *dev)
3928 {
3929         struct ixgbe_hw *hw =
3930                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931         uint32_t intr_vector = 0;
3932         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3933
3934         int err, mask = 0;
3935
3936         PMD_INIT_FUNC_TRACE();
3937
3938         hw->mac.ops.reset_hw(hw);
3939         hw->mac.get_link_status = true;
3940
3941         /* negotiate mailbox API version to use with the PF. */
3942         ixgbevf_negotiate_api(hw);
3943
3944         ixgbevf_dev_tx_init(dev);
3945
3946         /* This can fail when allocating mbufs for descriptor rings */
3947         err = ixgbevf_dev_rx_init(dev);
3948         if (err) {
3949                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3950                 ixgbe_dev_clear_queues(dev);
3951                 return err;
3952         }
3953
3954         /* Set vfta */
3955         ixgbevf_set_vfta_all(dev,1);
3956
3957         /* Set HW strip */
3958         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3959                 ETH_VLAN_EXTEND_MASK;
3960         ixgbevf_vlan_offload_set(dev, mask);
3961
3962         ixgbevf_dev_rxtx_start(dev);
3963
3964         /* check and configure queue intr-vector mapping */
3965         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3966                 intr_vector = dev->data->nb_rx_queues;
3967                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3968                         return -1;
3969         }
3970
3971         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3972                 intr_handle->intr_vec =
3973                         rte_zmalloc("intr_vec",
3974                                     dev->data->nb_rx_queues * sizeof(int), 0);
3975                 if (intr_handle->intr_vec == NULL) {
3976                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3977                                      " intr_vec\n", dev->data->nb_rx_queues);
3978                         return -ENOMEM;
3979                 }
3980         }
3981         ixgbevf_configure_msix(dev);
3982
3983         rte_intr_enable(intr_handle);
3984
3985         /* Re-enable interrupt for VF */
3986         ixgbevf_intr_enable(hw);
3987
3988         return 0;
3989 }
3990
3991 static void
3992 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3993 {
3994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3996
3997         PMD_INIT_FUNC_TRACE();
3998
3999         hw->adapter_stopped = 1;
4000         ixgbe_stop_adapter(hw);
4001
4002         /*
4003           * Clear what we set, but we still keep shadow_vfta to
4004           * restore after device starts
4005           */
4006         ixgbevf_set_vfta_all(dev,0);
4007
4008         /* Clear stored conf */
4009         dev->data->scattered_rx = 0;
4010
4011         ixgbe_dev_clear_queues(dev);
4012
4013         /* Clean datapath event and queue/vec mapping */
4014         rte_intr_efd_disable(intr_handle);
4015         if (intr_handle->intr_vec != NULL) {
4016                 rte_free(intr_handle->intr_vec);
4017                 intr_handle->intr_vec = NULL;
4018         }
4019 }
4020
4021 static void
4022 ixgbevf_dev_close(struct rte_eth_dev *dev)
4023 {
4024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4025
4026         PMD_INIT_FUNC_TRACE();
4027
4028         ixgbe_reset_hw(hw);
4029
4030         ixgbevf_dev_stop(dev);
4031
4032         ixgbe_dev_free_queues(dev);
4033
4034         /* reprogram the RAR[0] in case user changed it. */
4035         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
4036 }
4037
4038 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4039 {
4040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4041         struct ixgbe_vfta * shadow_vfta =
4042                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4043         int i = 0, j = 0, vfta = 0, mask = 1;
4044
4045         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
4046                 vfta = shadow_vfta->vfta[i];
4047                 if (vfta) {
4048                         mask = 1;
4049                         for (j = 0; j < 32; j++){
4050                                 if (vfta & mask)
4051                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4052                                 mask<<=1;
4053                         }
4054                 }
4055         }
4056
4057 }
4058
4059 static int
4060 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4061 {
4062         struct ixgbe_hw *hw =
4063                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4064         struct ixgbe_vfta * shadow_vfta =
4065                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4066         uint32_t vid_idx = 0;
4067         uint32_t vid_bit = 0;
4068         int ret = 0;
4069
4070         PMD_INIT_FUNC_TRACE();
4071
4072         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4073         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4074         if (ret) {
4075                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4076                 return ret;
4077         }
4078         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4079         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4080
4081         /* Save what we set and retore it after device reset */
4082         if (on)
4083                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4084         else
4085                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4086
4087         return 0;
4088 }
4089
4090 static void
4091 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4092 {
4093         struct ixgbe_hw *hw =
4094                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4095         uint32_t ctrl;
4096
4097         PMD_INIT_FUNC_TRACE();
4098
4099         if (queue >= hw->mac.max_rx_queues)
4100                 return;
4101
4102         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4103         if (on)
4104                 ctrl |= IXGBE_RXDCTL_VME;
4105         else
4106                 ctrl &= ~IXGBE_RXDCTL_VME;
4107         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4108
4109         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4110 }
4111
4112 static void
4113 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4114 {
4115         struct ixgbe_hw *hw =
4116                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4117         uint16_t i;
4118         int on = 0;
4119
4120         /* VF function only support hw strip feature, others are not support */
4121         if (mask & ETH_VLAN_STRIP_MASK) {
4122                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4123
4124                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4125                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4126         }
4127 }
4128
4129 static int
4130 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4131 {
4132         uint32_t reg_val;
4133
4134         /* we only need to do this if VMDq is enabled */
4135         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4136         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4137                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4138                 return -1;
4139         }
4140
4141         return 0;
4142 }
4143
4144 static uint32_t
4145 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4146 {
4147         uint32_t vector = 0;
4148         switch (hw->mac.mc_filter_type) {
4149         case 0:   /* use bits [47:36] of the address */
4150                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4151                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4152                 break;
4153         case 1:   /* use bits [46:35] of the address */
4154                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4155                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4156                 break;
4157         case 2:   /* use bits [45:34] of the address */
4158                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4159                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4160                 break;
4161         case 3:   /* use bits [43:32] of the address */
4162                 vector = ((uc_addr->addr_bytes[4]) |
4163                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4164                 break;
4165         default:  /* Invalid mc_filter_type */
4166                 break;
4167         }
4168
4169         /* vector can only be 12-bits or boundary will be exceeded */
4170         vector &= 0xFFF;
4171         return vector;
4172 }
4173
4174 static int
4175 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4176                                uint8_t on)
4177 {
4178         uint32_t vector;
4179         uint32_t uta_idx;
4180         uint32_t reg_val;
4181         uint32_t uta_shift;
4182         uint32_t rc;
4183         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4184         const uint32_t ixgbe_uta_bit_shift = 5;
4185         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4186         const uint32_t bit1 = 0x1;
4187
4188         struct ixgbe_hw *hw =
4189                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4190         struct ixgbe_uta_info *uta_info =
4191                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4192
4193         /* The UTA table only exists on 82599 hardware and newer */
4194         if (hw->mac.type < ixgbe_mac_82599EB)
4195                 return -ENOTSUP;
4196
4197         vector = ixgbe_uta_vector(hw,mac_addr);
4198         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4199         uta_shift = vector & ixgbe_uta_bit_mask;
4200
4201         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4202         if (rc == on)
4203                 return 0;
4204
4205         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4206         if (on) {
4207                 uta_info->uta_in_use++;
4208                 reg_val |= (bit1 << uta_shift);
4209                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4210         } else {
4211                 uta_info->uta_in_use--;
4212                 reg_val &= ~(bit1 << uta_shift);
4213                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4214         }
4215
4216         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4217
4218         if (uta_info->uta_in_use > 0)
4219                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4220                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4221         else
4222                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4223
4224         return 0;
4225 }
4226
4227 static int
4228 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4229 {
4230         int i;
4231         struct ixgbe_hw *hw =
4232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4233         struct ixgbe_uta_info *uta_info =
4234                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4235
4236         /* The UTA table only exists on 82599 hardware and newer */
4237         if (hw->mac.type < ixgbe_mac_82599EB)
4238                 return -ENOTSUP;
4239
4240         if (on) {
4241                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4242                         uta_info->uta_shadow[i] = ~0;
4243                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4244                 }
4245         } else {
4246                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4247                         uta_info->uta_shadow[i] = 0;
4248                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4249                 }
4250         }
4251         return 0;
4252
4253 }
4254
4255 uint32_t
4256 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4257 {
4258         uint32_t new_val = orig_val;
4259
4260         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4261                 new_val |= IXGBE_VMOLR_AUPE;
4262         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4263                 new_val |= IXGBE_VMOLR_ROMPE;
4264         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4265                 new_val |= IXGBE_VMOLR_ROPE;
4266         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4267                 new_val |= IXGBE_VMOLR_BAM;
4268         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4269                 new_val |= IXGBE_VMOLR_MPE;
4270
4271         return new_val;
4272 }
4273
4274 static int
4275 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4276                                uint16_t rx_mask, uint8_t on)
4277 {
4278         int val = 0;
4279
4280         struct ixgbe_hw *hw =
4281                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4283
4284         if (hw->mac.type == ixgbe_mac_82598EB) {
4285                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4286                              " on 82599 hardware and newer");
4287                 return -ENOTSUP;
4288         }
4289         if (ixgbe_vmdq_mode_check(hw) < 0)
4290                 return -ENOTSUP;
4291
4292         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4293
4294         if (on)
4295                 vmolr |= val;
4296         else
4297                 vmolr &= ~val;
4298
4299         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4300
4301         return 0;
4302 }
4303
4304 static int
4305 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4306 {
4307         uint32_t reg,addr;
4308         uint32_t val;
4309         const uint8_t bit1 = 0x1;
4310
4311         struct ixgbe_hw *hw =
4312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4313
4314         if (ixgbe_vmdq_mode_check(hw) < 0)
4315                 return -ENOTSUP;
4316
4317         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4318         reg = IXGBE_READ_REG(hw, addr);
4319         val = bit1 << pool;
4320
4321         if (on)
4322                 reg |= val;
4323         else
4324                 reg &= ~val;
4325
4326         IXGBE_WRITE_REG(hw, addr,reg);
4327
4328         return 0;
4329 }
4330
4331 static int
4332 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4333 {
4334         uint32_t reg,addr;
4335         uint32_t val;
4336         const uint8_t bit1 = 0x1;
4337
4338         struct ixgbe_hw *hw =
4339                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4340
4341         if (ixgbe_vmdq_mode_check(hw) < 0)
4342                 return -ENOTSUP;
4343
4344         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4345         reg = IXGBE_READ_REG(hw, addr);
4346         val = bit1 << pool;
4347
4348         if (on)
4349                 reg |= val;
4350         else
4351                 reg &= ~val;
4352
4353         IXGBE_WRITE_REG(hw, addr,reg);
4354
4355         return 0;
4356 }
4357
4358 static int
4359 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4360                         uint64_t pool_mask, uint8_t vlan_on)
4361 {
4362         int ret = 0;
4363         uint16_t pool_idx;
4364         struct ixgbe_hw *hw =
4365                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366
4367         if (ixgbe_vmdq_mode_check(hw) < 0)
4368                 return -ENOTSUP;
4369         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4370                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4371                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4372                         if (ret < 0)
4373                                 return ret;
4374         }
4375
4376         return ret;
4377 }
4378
4379 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4380 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4381 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4382 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4383 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4384         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4385         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4386
4387 static int
4388 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4389                         struct rte_eth_mirror_conf *mirror_conf,
4390                         uint8_t rule_id, uint8_t on)
4391 {
4392         uint32_t mr_ctl,vlvf;
4393         uint32_t mp_lsb = 0;
4394         uint32_t mv_msb = 0;
4395         uint32_t mv_lsb = 0;
4396         uint32_t mp_msb = 0;
4397         uint8_t i = 0;
4398         int reg_index = 0;
4399         uint64_t vlan_mask = 0;
4400
4401         const uint8_t pool_mask_offset = 32;
4402         const uint8_t vlan_mask_offset = 32;
4403         const uint8_t dst_pool_offset = 8;
4404         const uint8_t rule_mr_offset  = 4;
4405         const uint8_t mirror_rule_mask= 0x0F;
4406
4407         struct ixgbe_mirror_info *mr_info =
4408                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4409         struct ixgbe_hw *hw =
4410                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4411         uint8_t mirror_type = 0;
4412
4413         if (ixgbe_vmdq_mode_check(hw) < 0)
4414                 return -ENOTSUP;
4415
4416         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4417                 return -EINVAL;
4418
4419         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4420                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4421                         mirror_conf->rule_type);
4422                 return -EINVAL;
4423         }
4424
4425         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4426                 mirror_type |= IXGBE_MRCTL_VLME;
4427                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4428                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4429                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4430                                 /* search vlan id related pool vlan filter index */
4431                                 reg_index = ixgbe_find_vlvf_slot(hw,
4432                                                 mirror_conf->vlan.vlan_id[i]);
4433                                 if (reg_index < 0)
4434                                         return -EINVAL;
4435                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4436                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4437                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4438                                       mirror_conf->vlan.vlan_id[i]))
4439                                         vlan_mask |= (1ULL << reg_index);
4440                                 else
4441                                         return -EINVAL;
4442                         }
4443                 }
4444
4445                 if (on) {
4446                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4447                         mv_msb = vlan_mask >> vlan_mask_offset;
4448
4449                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4450                                                 mirror_conf->vlan.vlan_mask;
4451                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4452                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4453                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4454                                                 mirror_conf->vlan.vlan_id[i];
4455                         }
4456                 } else {
4457                         mv_lsb = 0;
4458                         mv_msb = 0;
4459                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4460                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4461                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4462                 }
4463         }
4464
4465         /*
4466          * if enable pool mirror, write related pool mask register,if disable
4467          * pool mirror, clear PFMRVM register
4468          */
4469         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4470                 mirror_type |= IXGBE_MRCTL_VPME;
4471                 if (on) {
4472                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4473                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4474                         mr_info->mr_conf[rule_id].pool_mask =
4475                                         mirror_conf->pool_mask;
4476
4477                 } else {
4478                         mp_lsb = 0;
4479                         mp_msb = 0;
4480                         mr_info->mr_conf[rule_id].pool_mask = 0;
4481                 }
4482         }
4483         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4484                 mirror_type |= IXGBE_MRCTL_UPME;
4485         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4486                 mirror_type |= IXGBE_MRCTL_DPME;
4487
4488         /* read  mirror control register and recalculate it */
4489         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4490
4491         if (on) {
4492                 mr_ctl |= mirror_type;
4493                 mr_ctl &= mirror_rule_mask;
4494                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4495         } else
4496                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4497
4498         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4499         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4500
4501         /* write mirrror control  register */
4502         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4503
4504         /* write pool mirrror control  register */
4505         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4506                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4507                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4508                                 mp_msb);
4509         }
4510         /* write VLAN mirrror control  register */
4511         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4512                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4513                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4514                                 mv_msb);
4515         }
4516
4517         return 0;
4518 }
4519
4520 static int
4521 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4522 {
4523         int mr_ctl = 0;
4524         uint32_t lsb_val = 0;
4525         uint32_t msb_val = 0;
4526         const uint8_t rule_mr_offset = 4;
4527
4528         struct ixgbe_hw *hw =
4529                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4530         struct ixgbe_mirror_info *mr_info =
4531                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4532
4533         if (ixgbe_vmdq_mode_check(hw) < 0)
4534                 return -ENOTSUP;
4535
4536         memset(&mr_info->mr_conf[rule_id], 0,
4537                 sizeof(struct rte_eth_mirror_conf));
4538
4539         /* clear PFVMCTL register */
4540         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4541
4542         /* clear pool mask register */
4543         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4544         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4545
4546         /* clear vlan mask register */
4547         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4548         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4549
4550         return 0;
4551 }
4552
4553 static int
4554 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4555 {
4556         uint32_t mask;
4557         struct ixgbe_hw *hw =
4558                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559
4560         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4561         mask |= (1 << IXGBE_MISC_VEC_ID);
4562         RTE_SET_USED(queue_id);
4563         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4564
4565         rte_intr_enable(&dev->pci_dev->intr_handle);
4566
4567         return 0;
4568 }
4569
4570 static int
4571 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4572 {
4573         uint32_t mask;
4574         struct ixgbe_hw *hw =
4575                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4576
4577         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4578         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4579         RTE_SET_USED(queue_id);
4580         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4581
4582         return 0;
4583 }
4584
4585 static int
4586 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4587 {
4588         uint32_t mask;
4589         struct ixgbe_hw *hw =
4590                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4591         struct ixgbe_interrupt *intr =
4592                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4593
4594         if (queue_id < 16) {
4595                 ixgbe_disable_intr(hw);
4596                 intr->mask |= (1 << queue_id);
4597                 ixgbe_enable_intr(dev);
4598         } else if (queue_id < 32) {
4599                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4600                 mask &= (1 << queue_id);
4601                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4602         } else if (queue_id < 64) {
4603                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4604                 mask &= (1 << (queue_id - 32));
4605                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4606         }
4607         rte_intr_enable(&dev->pci_dev->intr_handle);
4608
4609         return 0;
4610 }
4611
4612 static int
4613 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4614 {
4615         uint32_t mask;
4616         struct ixgbe_hw *hw =
4617                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4618         struct ixgbe_interrupt *intr =
4619                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4620
4621         if (queue_id < 16) {
4622                 ixgbe_disable_intr(hw);
4623                 intr->mask &= ~(1 << queue_id);
4624                 ixgbe_enable_intr(dev);
4625         } else if (queue_id < 32) {
4626                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4627                 mask &= ~(1 << queue_id);
4628                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4629         } else if (queue_id < 64) {
4630                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4631                 mask &= ~(1 << (queue_id - 32));
4632                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4633         }
4634
4635         return 0;
4636 }
4637
4638 static void
4639 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4640                      uint8_t queue, uint8_t msix_vector)
4641 {
4642         uint32_t tmp, idx;
4643
4644         if (direction == -1) {
4645                 /* other causes */
4646                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4647                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4648                 tmp &= ~0xFF;
4649                 tmp |= msix_vector;
4650                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4651         } else {
4652                 /* rx or tx cause */
4653                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4654                 idx = ((16 * (queue & 1)) + (8 * direction));
4655                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4656                 tmp &= ~(0xFF << idx);
4657                 tmp |= (msix_vector << idx);
4658                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4659         }
4660 }
4661
4662 /**
4663  * set the IVAR registers, mapping interrupt causes to vectors
4664  * @param hw
4665  *  pointer to ixgbe_hw struct
4666  * @direction
4667  *  0 for Rx, 1 for Tx, -1 for other causes
4668  * @queue
4669  *  queue to map the corresponding interrupt to
4670  * @msix_vector
4671  *  the vector to map to the corresponding queue
4672  */
4673 static void
4674 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4675                    uint8_t queue, uint8_t msix_vector)
4676 {
4677         uint32_t tmp, idx;
4678
4679         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4680         if (hw->mac.type == ixgbe_mac_82598EB) {
4681                 if (direction == -1)
4682                         direction = 0;
4683                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4684                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4685                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4686                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4687                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4688         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4689                         (hw->mac.type == ixgbe_mac_X540)) {
4690                 if (direction == -1) {
4691                         /* other causes */
4692                         idx = ((queue & 1) * 8);
4693                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4694                         tmp &= ~(0xFF << idx);
4695                         tmp |= (msix_vector << idx);
4696                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4697                 } else {
4698                         /* rx or tx causes */
4699                         idx = ((16 * (queue & 1)) + (8 * direction));
4700                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4701                         tmp &= ~(0xFF << idx);
4702                         tmp |= (msix_vector << idx);
4703                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4704                 }
4705         }
4706 }
4707
4708 static void
4709 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4710 {
4711         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4712         struct ixgbe_hw *hw =
4713                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4714         uint32_t q_idx;
4715         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4716
4717         /* won't configure msix register if no mapping is done
4718          * between intr vector and event fd.
4719          */
4720         if (!rte_intr_dp_is_en(intr_handle))
4721                 return;
4722
4723         /* Configure all RX queues of VF */
4724         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4725                 /* Force all queue use vector 0,
4726                  * as IXGBE_VF_MAXMSIVECOTR = 1
4727                  */
4728                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4729                 intr_handle->intr_vec[q_idx] = vector_idx;
4730         }
4731
4732         /* Configure VF other cause ivar */
4733         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4734 }
4735
4736 /**
4737  * Sets up the hardware to properly generate MSI-X interrupts
4738  * @hw
4739  *  board private structure
4740  */
4741 static void
4742 ixgbe_configure_msix(struct rte_eth_dev *dev)
4743 {
4744         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4745         struct ixgbe_hw *hw =
4746                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4747         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4748         uint32_t vec = IXGBE_MISC_VEC_ID;
4749         uint32_t mask;
4750         uint32_t gpie;
4751
4752         /* won't configure msix register if no mapping is done
4753          * between intr vector and event fd
4754          */
4755         if (!rte_intr_dp_is_en(intr_handle))
4756                 return;
4757
4758         if (rte_intr_allow_others(intr_handle))
4759                 vec = base = IXGBE_RX_VEC_START;
4760
4761         /* setup GPIE for MSI-x mode */
4762         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4763         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4764                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4765         /* auto clearing and auto setting corresponding bits in EIMS
4766          * when MSI-X interrupt is triggered
4767          */
4768         if (hw->mac.type == ixgbe_mac_82598EB) {
4769                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4770         } else {
4771                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4772                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4773         }
4774         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4775
4776         /* Populate the IVAR table and set the ITR values to the
4777          * corresponding register.
4778          */
4779         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4780              queue_id++) {
4781                 /* by default, 1:1 mapping */
4782                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4783                 intr_handle->intr_vec[queue_id] = vec;
4784                 if (vec < base + intr_handle->nb_efd - 1)
4785                         vec++;
4786         }
4787
4788         switch (hw->mac.type) {
4789         case ixgbe_mac_82598EB:
4790                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4791                                    IXGBE_MISC_VEC_ID);
4792                 break;
4793         case ixgbe_mac_82599EB:
4794         case ixgbe_mac_X540:
4795                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4796                 break;
4797         default:
4798                 break;
4799         }
4800         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4801                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4802
4803         /* set up to autoclear timer, and the vectors */
4804         mask = IXGBE_EIMS_ENABLE_MASK;
4805         mask &= ~(IXGBE_EIMS_OTHER |
4806                   IXGBE_EIMS_MAILBOX |
4807                   IXGBE_EIMS_LSC);
4808
4809         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4810 }
4811
4812 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4813         uint16_t queue_idx, uint16_t tx_rate)
4814 {
4815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4816         uint32_t rf_dec, rf_int;
4817         uint32_t bcnrc_val;
4818         uint16_t link_speed = dev->data->dev_link.link_speed;
4819
4820         if (queue_idx >= hw->mac.max_tx_queues)
4821                 return -EINVAL;
4822
4823         if (tx_rate != 0) {
4824                 /* Calculate the rate factor values to set */
4825                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4826                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4827                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4828
4829                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4830                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4831                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4832                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4833         } else {
4834                 bcnrc_val = 0;
4835         }
4836
4837         /*
4838          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4839          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4840          * set as 0x4.
4841          */
4842         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4843                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4844                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4845                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4846                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4847         else
4848                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4849                         IXGBE_MMW_SIZE_DEFAULT);
4850
4851         /* Set RTTBCNRC of queue X */
4852         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4853         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4854         IXGBE_WRITE_FLUSH(hw);
4855
4856         return 0;
4857 }
4858
4859 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4860         uint16_t tx_rate, uint64_t q_msk)
4861 {
4862         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4863         struct ixgbe_vf_info *vfinfo =
4864                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4865         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4866         uint32_t queue_stride =
4867                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4868         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4869         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4870         uint16_t total_rate = 0;
4871
4872         if (queue_end >= hw->mac.max_tx_queues)
4873                 return -EINVAL;
4874
4875         if (vfinfo != NULL) {
4876                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4877                         if (vf_idx == vf)
4878                                 continue;
4879                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4880                                 idx++)
4881                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4882                 }
4883         } else
4884                 return -EINVAL;
4885
4886         /* Store tx_rate for this vf. */
4887         for (idx = 0; idx < nb_q_per_pool; idx++) {
4888                 if (((uint64_t)0x1 << idx) & q_msk) {
4889                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4890                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4891                         total_rate += tx_rate;
4892                 }
4893         }
4894
4895         if (total_rate > dev->data->dev_link.link_speed) {
4896                 /*
4897                  * Reset stored TX rate of the VF if it causes exceed
4898                  * link speed.
4899                  */
4900                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4901                 return -EINVAL;
4902         }
4903
4904         /* Set RTTBCNRC of each queue/pool for vf X  */
4905         for (; queue_idx <= queue_end; queue_idx++) {
4906                 if (0x1 & q_msk)
4907                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4908                 q_msk = q_msk >> 1;
4909         }
4910
4911         return 0;
4912 }
4913
4914 static void
4915 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4916                      __attribute__((unused)) uint32_t index,
4917                      __attribute__((unused)) uint32_t pool)
4918 {
4919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4920         int diag;
4921
4922         /*
4923          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4924          * operation. Trap this case to avoid exhausting the [very limited]
4925          * set of PF resources used to store VF MAC addresses.
4926          */
4927         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4928                 return;
4929         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4930         if (diag == 0)
4931                 return;
4932         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4933 }
4934
4935 static void
4936 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4937 {
4938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4940         struct ether_addr *mac_addr;
4941         uint32_t i;
4942         int diag;
4943
4944         /*
4945          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4946          * not support the deletion of a given MAC address.
4947          * Instead, it imposes to delete all MAC addresses, then to add again
4948          * all MAC addresses with the exception of the one to be deleted.
4949          */
4950         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4951
4952         /*
4953          * Add again all MAC addresses, with the exception of the deleted one
4954          * and of the permanent MAC address.
4955          */
4956         for (i = 0, mac_addr = dev->data->mac_addrs;
4957              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4958                 /* Skip the deleted MAC address */
4959                 if (i == index)
4960                         continue;
4961                 /* Skip NULL MAC addresses */
4962                 if (is_zero_ether_addr(mac_addr))
4963                         continue;
4964                 /* Skip the permanent MAC address */
4965                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4966                         continue;
4967                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4968                 if (diag != 0)
4969                         PMD_DRV_LOG(ERR,
4970                                     "Adding again MAC address "
4971                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4972                                     "diag=%d",
4973                                     mac_addr->addr_bytes[0],
4974                                     mac_addr->addr_bytes[1],
4975                                     mac_addr->addr_bytes[2],
4976                                     mac_addr->addr_bytes[3],
4977                                     mac_addr->addr_bytes[4],
4978                                     mac_addr->addr_bytes[5],
4979                                     diag);
4980         }
4981 }
4982
4983 static void
4984 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4985 {
4986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4987
4988         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4989 }
4990
4991 #define MAC_TYPE_FILTER_SUP(type)    do {\
4992         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4993                 (type) != ixgbe_mac_X550)\
4994                 return -ENOTSUP;\
4995 } while (0)
4996
4997 static int
4998 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4999                         struct rte_eth_syn_filter *filter,
5000                         bool add)
5001 {
5002         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5003         uint32_t synqf;
5004
5005         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5006                 return -EINVAL;
5007
5008         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5009
5010         if (add) {
5011                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5012                         return -EINVAL;
5013                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5014                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5015
5016                 if (filter->hig_pri)
5017                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5018                 else
5019                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5020         } else {
5021                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5022                         return -ENOENT;
5023                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5024         }
5025         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5026         IXGBE_WRITE_FLUSH(hw);
5027         return 0;
5028 }
5029
5030 static int
5031 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5032                         struct rte_eth_syn_filter *filter)
5033 {
5034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5035         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5036
5037         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5038                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5039                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5040                 return 0;
5041         }
5042         return -ENOENT;
5043 }
5044
5045 static int
5046 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5047                         enum rte_filter_op filter_op,
5048                         void *arg)
5049 {
5050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         int ret;
5052
5053         MAC_TYPE_FILTER_SUP(hw->mac.type);
5054
5055         if (filter_op == RTE_ETH_FILTER_NOP)
5056                 return 0;
5057
5058         if (arg == NULL) {
5059                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5060                             filter_op);
5061                 return -EINVAL;
5062         }
5063
5064         switch (filter_op) {
5065         case RTE_ETH_FILTER_ADD:
5066                 ret = ixgbe_syn_filter_set(dev,
5067                                 (struct rte_eth_syn_filter *)arg,
5068                                 TRUE);
5069                 break;
5070         case RTE_ETH_FILTER_DELETE:
5071                 ret = ixgbe_syn_filter_set(dev,
5072                                 (struct rte_eth_syn_filter *)arg,
5073                                 FALSE);
5074                 break;
5075         case RTE_ETH_FILTER_GET:
5076                 ret = ixgbe_syn_filter_get(dev,
5077                                 (struct rte_eth_syn_filter *)arg);
5078                 break;
5079         default:
5080                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5081                 ret = -EINVAL;
5082                 break;
5083         }
5084
5085         return ret;
5086 }
5087
5088
5089 static inline enum ixgbe_5tuple_protocol
5090 convert_protocol_type(uint8_t protocol_value)
5091 {
5092         if (protocol_value == IPPROTO_TCP)
5093                 return IXGBE_FILTER_PROTOCOL_TCP;
5094         else if (protocol_value == IPPROTO_UDP)
5095                 return IXGBE_FILTER_PROTOCOL_UDP;
5096         else if (protocol_value == IPPROTO_SCTP)
5097                 return IXGBE_FILTER_PROTOCOL_SCTP;
5098         else
5099                 return IXGBE_FILTER_PROTOCOL_NONE;
5100 }
5101
5102 /*
5103  * add a 5tuple filter
5104  *
5105  * @param
5106  * dev: Pointer to struct rte_eth_dev.
5107  * index: the index the filter allocates.
5108  * filter: ponter to the filter that will be added.
5109  * rx_queue: the queue id the filter assigned to.
5110  *
5111  * @return
5112  *    - On success, zero.
5113  *    - On failure, a negative value.
5114  */
5115 static int
5116 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5117                         struct ixgbe_5tuple_filter *filter)
5118 {
5119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120         struct ixgbe_filter_info *filter_info =
5121                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5122         int i, idx, shift;
5123         uint32_t ftqf, sdpqf;
5124         uint32_t l34timir = 0;
5125         uint8_t mask = 0xff;
5126
5127         /*
5128          * look for an unused 5tuple filter index,
5129          * and insert the filter to list.
5130          */
5131         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5132                 idx = i / (sizeof(uint32_t) * NBBY);
5133                 shift = i % (sizeof(uint32_t) * NBBY);
5134                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5135                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5136                         filter->index = i;
5137                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5138                                           filter,
5139                                           entries);
5140                         break;
5141                 }
5142         }
5143         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5144                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5145                 return -ENOSYS;
5146         }
5147
5148         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5149                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5150         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5151
5152         ftqf = (uint32_t)(filter->filter_info.proto &
5153                 IXGBE_FTQF_PROTOCOL_MASK);
5154         ftqf |= (uint32_t)((filter->filter_info.priority &
5155                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5156         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5157                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5158         if (filter->filter_info.dst_ip_mask == 0)
5159                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5160         if (filter->filter_info.src_port_mask == 0)
5161                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5162         if (filter->filter_info.dst_port_mask == 0)
5163                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5164         if (filter->filter_info.proto_mask == 0)
5165                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5166         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5167         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5168         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5169
5170         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5171         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5172         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5173         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5174
5175         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5176         l34timir |= (uint32_t)(filter->queue <<
5177                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5178         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5179         return 0;
5180 }
5181
5182 /*
5183  * remove a 5tuple filter
5184  *
5185  * @param
5186  * dev: Pointer to struct rte_eth_dev.
5187  * filter: the pointer of the filter will be removed.
5188  */
5189 static void
5190 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5191                         struct ixgbe_5tuple_filter *filter)
5192 {
5193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194         struct ixgbe_filter_info *filter_info =
5195                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5196         uint16_t index = filter->index;
5197
5198         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5199                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5200         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5201         rte_free(filter);
5202
5203         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5204         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5205         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5206         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5207         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5208 }
5209
5210 static int
5211 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5212 {
5213         struct ixgbe_hw *hw;
5214         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5215
5216         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5217
5218         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5219                 return -EINVAL;
5220
5221         /* refuse mtu that requires the support of scattered packets when this
5222          * feature has not been enabled before. */
5223         if (!dev->data->scattered_rx &&
5224             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5225              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5226                 return -EINVAL;
5227
5228         /*
5229          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5230          * request of the version 2.0 of the mailbox API.
5231          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5232          * of the mailbox API.
5233          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5234          * prior to 3.11.33 which contains the following change:
5235          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5236          */
5237         ixgbevf_rlpml_set_vf(hw, max_frame);
5238
5239         /* update max frame size */
5240         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5241         return 0;
5242 }
5243
5244 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5245         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5246                 return -ENOTSUP;\
5247 } while (0)
5248
5249 static inline struct ixgbe_5tuple_filter *
5250 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5251                         struct ixgbe_5tuple_filter_info *key)
5252 {
5253         struct ixgbe_5tuple_filter *it;
5254
5255         TAILQ_FOREACH(it, filter_list, entries) {
5256                 if (memcmp(key, &it->filter_info,
5257                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5258                         return it;
5259                 }
5260         }
5261         return NULL;
5262 }
5263
5264 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5265 static inline int
5266 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5267                         struct ixgbe_5tuple_filter_info *filter_info)
5268 {
5269         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5270                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5271                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5272                 return -EINVAL;
5273
5274         switch (filter->dst_ip_mask) {
5275         case UINT32_MAX:
5276                 filter_info->dst_ip_mask = 0;
5277                 filter_info->dst_ip = filter->dst_ip;
5278                 break;
5279         case 0:
5280                 filter_info->dst_ip_mask = 1;
5281                 break;
5282         default:
5283                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5284                 return -EINVAL;
5285         }
5286
5287         switch (filter->src_ip_mask) {
5288         case UINT32_MAX:
5289                 filter_info->src_ip_mask = 0;
5290                 filter_info->src_ip = filter->src_ip;
5291                 break;
5292         case 0:
5293                 filter_info->src_ip_mask = 1;
5294                 break;
5295         default:
5296                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5297                 return -EINVAL;
5298         }
5299
5300         switch (filter->dst_port_mask) {
5301         case UINT16_MAX:
5302                 filter_info->dst_port_mask = 0;
5303                 filter_info->dst_port = filter->dst_port;
5304                 break;
5305         case 0:
5306                 filter_info->dst_port_mask = 1;
5307                 break;
5308         default:
5309                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5310                 return -EINVAL;
5311         }
5312
5313         switch (filter->src_port_mask) {
5314         case UINT16_MAX:
5315                 filter_info->src_port_mask = 0;
5316                 filter_info->src_port = filter->src_port;
5317                 break;
5318         case 0:
5319                 filter_info->src_port_mask = 1;
5320                 break;
5321         default:
5322                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5323                 return -EINVAL;
5324         }
5325
5326         switch (filter->proto_mask) {
5327         case UINT8_MAX:
5328                 filter_info->proto_mask = 0;
5329                 filter_info->proto =
5330                         convert_protocol_type(filter->proto);
5331                 break;
5332         case 0:
5333                 filter_info->proto_mask = 1;
5334                 break;
5335         default:
5336                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5337                 return -EINVAL;
5338         }
5339
5340         filter_info->priority = (uint8_t)filter->priority;
5341         return 0;
5342 }
5343
5344 /*
5345  * add or delete a ntuple filter
5346  *
5347  * @param
5348  * dev: Pointer to struct rte_eth_dev.
5349  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5350  * add: if true, add filter, if false, remove filter
5351  *
5352  * @return
5353  *    - On success, zero.
5354  *    - On failure, a negative value.
5355  */
5356 static int
5357 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5358                         struct rte_eth_ntuple_filter *ntuple_filter,
5359                         bool add)
5360 {
5361         struct ixgbe_filter_info *filter_info =
5362                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5363         struct ixgbe_5tuple_filter_info filter_5tuple;
5364         struct ixgbe_5tuple_filter *filter;
5365         int ret;
5366
5367         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5368                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5369                 return -EINVAL;
5370         }
5371
5372         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5373         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5374         if (ret < 0)
5375                 return ret;
5376
5377         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5378                                          &filter_5tuple);
5379         if (filter != NULL && add) {
5380                 PMD_DRV_LOG(ERR, "filter exists.");
5381                 return -EEXIST;
5382         }
5383         if (filter == NULL && !add) {
5384                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5385                 return -ENOENT;
5386         }
5387
5388         if (add) {
5389                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5390                                 sizeof(struct ixgbe_5tuple_filter), 0);
5391                 if (filter == NULL)
5392                         return -ENOMEM;
5393                 (void)rte_memcpy(&filter->filter_info,
5394                                  &filter_5tuple,
5395                                  sizeof(struct ixgbe_5tuple_filter_info));
5396                 filter->queue = ntuple_filter->queue;
5397                 ret = ixgbe_add_5tuple_filter(dev, filter);
5398                 if (ret < 0) {
5399                         rte_free(filter);
5400                         return ret;
5401                 }
5402         } else
5403                 ixgbe_remove_5tuple_filter(dev, filter);
5404
5405         return 0;
5406 }
5407
5408 /*
5409  * get a ntuple filter
5410  *
5411  * @param
5412  * dev: Pointer to struct rte_eth_dev.
5413  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5414  *
5415  * @return
5416  *    - On success, zero.
5417  *    - On failure, a negative value.
5418  */
5419 static int
5420 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5421                         struct rte_eth_ntuple_filter *ntuple_filter)
5422 {
5423         struct ixgbe_filter_info *filter_info =
5424                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5425         struct ixgbe_5tuple_filter_info filter_5tuple;
5426         struct ixgbe_5tuple_filter *filter;
5427         int ret;
5428
5429         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5430                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5431                 return -EINVAL;
5432         }
5433
5434         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5435         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5436         if (ret < 0)
5437                 return ret;
5438
5439         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5440                                          &filter_5tuple);
5441         if (filter == NULL) {
5442                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5443                 return -ENOENT;
5444         }
5445         ntuple_filter->queue = filter->queue;
5446         return 0;
5447 }
5448
5449 /*
5450  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5451  * @dev: pointer to rte_eth_dev structure
5452  * @filter_op:operation will be taken.
5453  * @arg: a pointer to specific structure corresponding to the filter_op
5454  *
5455  * @return
5456  *    - On success, zero.
5457  *    - On failure, a negative value.
5458  */
5459 static int
5460 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5461                                 enum rte_filter_op filter_op,
5462                                 void *arg)
5463 {
5464         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5465         int ret;
5466
5467         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5468
5469         if (filter_op == RTE_ETH_FILTER_NOP)
5470                 return 0;
5471
5472         if (arg == NULL) {
5473                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5474                             filter_op);
5475                 return -EINVAL;
5476         }
5477
5478         switch (filter_op) {
5479         case RTE_ETH_FILTER_ADD:
5480                 ret = ixgbe_add_del_ntuple_filter(dev,
5481                         (struct rte_eth_ntuple_filter *)arg,
5482                         TRUE);
5483                 break;
5484         case RTE_ETH_FILTER_DELETE:
5485                 ret = ixgbe_add_del_ntuple_filter(dev,
5486                         (struct rte_eth_ntuple_filter *)arg,
5487                         FALSE);
5488                 break;
5489         case RTE_ETH_FILTER_GET:
5490                 ret = ixgbe_get_ntuple_filter(dev,
5491                         (struct rte_eth_ntuple_filter *)arg);
5492                 break;
5493         default:
5494                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5495                 ret = -EINVAL;
5496                 break;
5497         }
5498         return ret;
5499 }
5500
5501 static inline int
5502 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5503                         uint16_t ethertype)
5504 {
5505         int i;
5506
5507         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5508                 if (filter_info->ethertype_filters[i] == ethertype &&
5509                     (filter_info->ethertype_mask & (1 << i)))
5510                         return i;
5511         }
5512         return -1;
5513 }
5514
5515 static inline int
5516 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5517                         uint16_t ethertype)
5518 {
5519         int i;
5520
5521         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5522                 if (!(filter_info->ethertype_mask & (1 << i))) {
5523                         filter_info->ethertype_mask |= 1 << i;
5524                         filter_info->ethertype_filters[i] = ethertype;
5525                         return i;
5526                 }
5527         }
5528         return -1;
5529 }
5530
5531 static inline int
5532 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5533                         uint8_t idx)
5534 {
5535         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5536                 return -1;
5537         filter_info->ethertype_mask &= ~(1 << idx);
5538         filter_info->ethertype_filters[idx] = 0;
5539         return idx;
5540 }
5541
5542 static int
5543 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5544                         struct rte_eth_ethertype_filter *filter,
5545                         bool add)
5546 {
5547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548         struct ixgbe_filter_info *filter_info =
5549                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5550         uint32_t etqf = 0;
5551         uint32_t etqs = 0;
5552         int ret;
5553
5554         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5555                 return -EINVAL;
5556
5557         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5558                 filter->ether_type == ETHER_TYPE_IPv6) {
5559                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5560                         " ethertype filter.", filter->ether_type);
5561                 return -EINVAL;
5562         }
5563
5564         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5565                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5566                 return -EINVAL;
5567         }
5568         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5569                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5570                 return -EINVAL;
5571         }
5572
5573         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5574         if (ret >= 0 && add) {
5575                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5576                             filter->ether_type);
5577                 return -EEXIST;
5578         }
5579         if (ret < 0 && !add) {
5580                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5581                             filter->ether_type);
5582                 return -ENOENT;
5583         }
5584
5585         if (add) {
5586                 ret = ixgbe_ethertype_filter_insert(filter_info,
5587                         filter->ether_type);
5588                 if (ret < 0) {
5589                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5590                         return -ENOSYS;
5591                 }
5592                 etqf = IXGBE_ETQF_FILTER_EN;
5593                 etqf |= (uint32_t)filter->ether_type;
5594                 etqs |= (uint32_t)((filter->queue <<
5595                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5596                                     IXGBE_ETQS_RX_QUEUE);
5597                 etqs |= IXGBE_ETQS_QUEUE_EN;
5598         } else {
5599                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5600                 if (ret < 0)
5601                         return -ENOSYS;
5602         }
5603         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5604         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5605         IXGBE_WRITE_FLUSH(hw);
5606
5607         return 0;
5608 }
5609
5610 static int
5611 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5612                         struct rte_eth_ethertype_filter *filter)
5613 {
5614         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5615         struct ixgbe_filter_info *filter_info =
5616                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5617         uint32_t etqf, etqs;
5618         int ret;
5619
5620         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5621         if (ret < 0) {
5622                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5623                             filter->ether_type);
5624                 return -ENOENT;
5625         }
5626
5627         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5628         if (etqf & IXGBE_ETQF_FILTER_EN) {
5629                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5630                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5631                 filter->flags = 0;
5632                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5633                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5634                 return 0;
5635         }
5636         return -ENOENT;
5637 }
5638
5639 /*
5640  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5641  * @dev: pointer to rte_eth_dev structure
5642  * @filter_op:operation will be taken.
5643  * @arg: a pointer to specific structure corresponding to the filter_op
5644  */
5645 static int
5646 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5647                                 enum rte_filter_op filter_op,
5648                                 void *arg)
5649 {
5650         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5651         int ret;
5652
5653         MAC_TYPE_FILTER_SUP(hw->mac.type);
5654
5655         if (filter_op == RTE_ETH_FILTER_NOP)
5656                 return 0;
5657
5658         if (arg == NULL) {
5659                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5660                             filter_op);
5661                 return -EINVAL;
5662         }
5663
5664         switch (filter_op) {
5665         case RTE_ETH_FILTER_ADD:
5666                 ret = ixgbe_add_del_ethertype_filter(dev,
5667                         (struct rte_eth_ethertype_filter *)arg,
5668                         TRUE);
5669                 break;
5670         case RTE_ETH_FILTER_DELETE:
5671                 ret = ixgbe_add_del_ethertype_filter(dev,
5672                         (struct rte_eth_ethertype_filter *)arg,
5673                         FALSE);
5674                 break;
5675         case RTE_ETH_FILTER_GET:
5676                 ret = ixgbe_get_ethertype_filter(dev,
5677                         (struct rte_eth_ethertype_filter *)arg);
5678                 break;
5679         default:
5680                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5681                 ret = -EINVAL;
5682                 break;
5683         }
5684         return ret;
5685 }
5686
5687 static int
5688 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5689                      enum rte_filter_type filter_type,
5690                      enum rte_filter_op filter_op,
5691                      void *arg)
5692 {
5693         int ret = -EINVAL;
5694
5695         switch (filter_type) {
5696         case RTE_ETH_FILTER_NTUPLE:
5697                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5698                 break;
5699         case RTE_ETH_FILTER_ETHERTYPE:
5700                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5701                 break;
5702         case RTE_ETH_FILTER_SYN:
5703                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5704                 break;
5705         case RTE_ETH_FILTER_FDIR:
5706                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5707                 break;
5708         case RTE_ETH_FILTER_L2_TUNNEL:
5709                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5710                 break;
5711         default:
5712                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5713                                                         filter_type);
5714                 break;
5715         }
5716
5717         return ret;
5718 }
5719
5720 static u8 *
5721 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5722                         u8 **mc_addr_ptr, u32 *vmdq)
5723 {
5724         u8 *mc_addr;
5725
5726         *vmdq = 0;
5727         mc_addr = *mc_addr_ptr;
5728         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5729         return mc_addr;
5730 }
5731
5732 static int
5733 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5734                           struct ether_addr *mc_addr_set,
5735                           uint32_t nb_mc_addr)
5736 {
5737         struct ixgbe_hw *hw;
5738         u8 *mc_addr_list;
5739
5740         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5741         mc_addr_list = (u8 *)mc_addr_set;
5742         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5743                                          ixgbe_dev_addr_list_itr, TRUE);
5744 }
5745
5746 static uint64_t
5747 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5748 {
5749         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750         uint64_t systime_cycles;
5751
5752         switch (hw->mac.type) {
5753         case ixgbe_mac_X550:
5754                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5755                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5756                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5757                                 * NSEC_PER_SEC;
5758                 break;
5759         default:
5760                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5761                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5762                                 << 32;
5763         }
5764
5765         return systime_cycles;
5766 }
5767
5768 static uint64_t
5769 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5770 {
5771         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5772         uint64_t rx_tstamp_cycles;
5773
5774         switch (hw->mac.type) {
5775         case ixgbe_mac_X550:
5776                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5777                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5778                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5779                                 * NSEC_PER_SEC;
5780                 break;
5781         default:
5782                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5783                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5784                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5785                                 << 32;
5786         }
5787
5788         return rx_tstamp_cycles;
5789 }
5790
5791 static uint64_t
5792 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5793 {
5794         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5795         uint64_t tx_tstamp_cycles;
5796
5797         switch (hw->mac.type) {
5798         case ixgbe_mac_X550:
5799                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5800                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5801                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5802                                 * NSEC_PER_SEC;
5803                 break;
5804         default:
5805                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5806                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5807                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5808                                 << 32;
5809         }
5810
5811         return tx_tstamp_cycles;
5812 }
5813
5814 static void
5815 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5816 {
5817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5818         struct ixgbe_adapter *adapter =
5819                 (struct ixgbe_adapter *)dev->data->dev_private;
5820         struct rte_eth_link link;
5821         uint32_t incval = 0;
5822         uint32_t shift = 0;
5823
5824         /* Get current link speed. */
5825         memset(&link, 0, sizeof(link));
5826         ixgbe_dev_link_update(dev, 1);
5827         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5828
5829         switch (link.link_speed) {
5830         case ETH_LINK_SPEED_100:
5831                 incval = IXGBE_INCVAL_100;
5832                 shift = IXGBE_INCVAL_SHIFT_100;
5833                 break;
5834         case ETH_LINK_SPEED_1000:
5835                 incval = IXGBE_INCVAL_1GB;
5836                 shift = IXGBE_INCVAL_SHIFT_1GB;
5837                 break;
5838         case ETH_LINK_SPEED_10000:
5839         default:
5840                 incval = IXGBE_INCVAL_10GB;
5841                 shift = IXGBE_INCVAL_SHIFT_10GB;
5842                 break;
5843         }
5844
5845         switch (hw->mac.type) {
5846         case ixgbe_mac_X550:
5847                 /* Independent of link speed. */
5848                 incval = 1;
5849                 /* Cycles read will be interpreted as ns. */
5850                 shift = 0;
5851                 /* Fall-through */
5852         case ixgbe_mac_X540:
5853                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5854                 break;
5855         case ixgbe_mac_82599EB:
5856                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5857                 shift -= IXGBE_INCVAL_SHIFT_82599;
5858                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5859                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5860                 break;
5861         default:
5862                 /* Not supported. */
5863                 return;
5864         }
5865
5866         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5867         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5868         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5869
5870         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5871         adapter->systime_tc.cc_shift = shift;
5872         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5873
5874         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5875         adapter->rx_tstamp_tc.cc_shift = shift;
5876         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5877
5878         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5879         adapter->tx_tstamp_tc.cc_shift = shift;
5880         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5881 }
5882
5883 static int
5884 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5885 {
5886         struct ixgbe_adapter *adapter =
5887                         (struct ixgbe_adapter *)dev->data->dev_private;
5888
5889         adapter->systime_tc.nsec += delta;
5890         adapter->rx_tstamp_tc.nsec += delta;
5891         adapter->tx_tstamp_tc.nsec += delta;
5892
5893         return 0;
5894 }
5895
5896 static int
5897 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5898 {
5899         uint64_t ns;
5900         struct ixgbe_adapter *adapter =
5901                         (struct ixgbe_adapter *)dev->data->dev_private;
5902
5903         ns = rte_timespec_to_ns(ts);
5904         /* Set the timecounters to a new value. */
5905         adapter->systime_tc.nsec = ns;
5906         adapter->rx_tstamp_tc.nsec = ns;
5907         adapter->tx_tstamp_tc.nsec = ns;
5908
5909         return 0;
5910 }
5911
5912 static int
5913 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5914 {
5915         uint64_t ns, systime_cycles;
5916         struct ixgbe_adapter *adapter =
5917                         (struct ixgbe_adapter *)dev->data->dev_private;
5918
5919         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5920         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5921         *ts = rte_ns_to_timespec(ns);
5922
5923         return 0;
5924 }
5925
5926 static int
5927 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5928 {
5929         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5930         uint32_t tsync_ctl;
5931         uint32_t tsauxc;
5932
5933         /* Stop the timesync system time. */
5934         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5935         /* Reset the timesync system time value. */
5936         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5937         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5938
5939         /* Enable system time for platforms where it isn't on by default. */
5940         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5941         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5942         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5943
5944         ixgbe_start_timecounters(dev);
5945
5946         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5947         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5948                         (ETHER_TYPE_1588 |
5949                          IXGBE_ETQF_FILTER_EN |
5950                          IXGBE_ETQF_1588));
5951
5952         /* Enable timestamping of received PTP packets. */
5953         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5954         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5955         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5956
5957         /* Enable timestamping of transmitted PTP packets. */
5958         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5959         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5960         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5961
5962         IXGBE_WRITE_FLUSH(hw);
5963
5964         return 0;
5965 }
5966
5967 static int
5968 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5969 {
5970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5971         uint32_t tsync_ctl;
5972
5973         /* Disable timestamping of transmitted PTP packets. */
5974         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5975         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5976         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5977
5978         /* Disable timestamping of received PTP packets. */
5979         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5980         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5981         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5982
5983         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5984         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5985
5986         /* Stop incrementating the System Time registers. */
5987         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5988
5989         return 0;
5990 }
5991
5992 static int
5993 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5994                                  struct timespec *timestamp,
5995                                  uint32_t flags __rte_unused)
5996 {
5997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5998         struct ixgbe_adapter *adapter =
5999                 (struct ixgbe_adapter *)dev->data->dev_private;
6000         uint32_t tsync_rxctl;
6001         uint64_t rx_tstamp_cycles;
6002         uint64_t ns;
6003
6004         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6005         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6006                 return -EINVAL;
6007
6008         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6009         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6010         *timestamp = rte_ns_to_timespec(ns);
6011
6012         return  0;
6013 }
6014
6015 static int
6016 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6017                                  struct timespec *timestamp)
6018 {
6019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6020         struct ixgbe_adapter *adapter =
6021                 (struct ixgbe_adapter *)dev->data->dev_private;
6022         uint32_t tsync_txctl;
6023         uint64_t tx_tstamp_cycles;
6024         uint64_t ns;
6025
6026         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6027         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6028                 return -EINVAL;
6029
6030         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6031         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6032         *timestamp = rte_ns_to_timespec(ns);
6033
6034         return 0;
6035 }
6036
6037 static int
6038 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6039 {
6040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6041         int count = 0;
6042         int g_ind = 0;
6043         const struct reg_info *reg_group;
6044         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6045                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6046
6047         while ((reg_group = reg_set[g_ind++]))
6048                 count += ixgbe_regs_group_count(reg_group);
6049
6050         return count;
6051 }
6052
6053 static int
6054 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6055 {
6056         int count = 0;
6057         int g_ind = 0;
6058         const struct reg_info *reg_group;
6059
6060         while ((reg_group = ixgbevf_regs[g_ind++]))
6061                 count += ixgbe_regs_group_count(reg_group);
6062
6063         return count;
6064 }
6065
6066 static int
6067 ixgbe_get_regs(struct rte_eth_dev *dev,
6068               struct rte_dev_reg_info *regs)
6069 {
6070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6071         uint32_t *data = regs->data;
6072         int g_ind = 0;
6073         int count = 0;
6074         const struct reg_info *reg_group;
6075         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6076                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6077
6078         /* Support only full register dump */
6079         if ((regs->length == 0) ||
6080             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6081                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6082                         hw->device_id;
6083                 while ((reg_group = reg_set[g_ind++]))
6084                         count += ixgbe_read_regs_group(dev, &data[count],
6085                                 reg_group);
6086                 return 0;
6087         }
6088
6089         return -ENOTSUP;
6090 }
6091
6092 static int
6093 ixgbevf_get_regs(struct rte_eth_dev *dev,
6094                 struct rte_dev_reg_info *regs)
6095 {
6096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6097         uint32_t *data = regs->data;
6098         int g_ind = 0;
6099         int count = 0;
6100         const struct reg_info *reg_group;
6101
6102         /* Support only full register dump */
6103         if ((regs->length == 0) ||
6104             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6105                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6106                         hw->device_id;
6107                 while ((reg_group = ixgbevf_regs[g_ind++]))
6108                         count += ixgbe_read_regs_group(dev, &data[count],
6109                                                       reg_group);
6110                 return 0;
6111         }
6112
6113         return -ENOTSUP;
6114 }
6115
6116 static int
6117 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6118 {
6119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6120
6121         /* Return unit is byte count */
6122         return hw->eeprom.word_size * 2;
6123 }
6124
6125 static int
6126 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6127                 struct rte_dev_eeprom_info *in_eeprom)
6128 {
6129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6130         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6131         uint16_t *data = in_eeprom->data;
6132         int first, length;
6133
6134         first = in_eeprom->offset >> 1;
6135         length = in_eeprom->length >> 1;
6136         if ((first > hw->eeprom.word_size) ||
6137             ((first + length) > hw->eeprom.word_size))
6138                 return -EINVAL;
6139
6140         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6141
6142         return eeprom->ops.read_buffer(hw, first, length, data);
6143 }
6144
6145 static int
6146 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6147                 struct rte_dev_eeprom_info *in_eeprom)
6148 {
6149         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6150         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6151         uint16_t *data = in_eeprom->data;
6152         int first, length;
6153
6154         first = in_eeprom->offset >> 1;
6155         length = in_eeprom->length >> 1;
6156         if ((first > hw->eeprom.word_size) ||
6157             ((first + length) > hw->eeprom.word_size))
6158                 return -EINVAL;
6159
6160         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6161
6162         return eeprom->ops.write_buffer(hw,  first, length, data);
6163 }
6164
6165 uint16_t
6166 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6167         switch (mac_type) {
6168         case ixgbe_mac_X550:
6169         case ixgbe_mac_X550EM_x:
6170         case ixgbe_mac_X550EM_a:
6171                 return ETH_RSS_RETA_SIZE_512;
6172         case ixgbe_mac_X550_vf:
6173         case ixgbe_mac_X550EM_x_vf:
6174         case ixgbe_mac_X550EM_a_vf:
6175                 return ETH_RSS_RETA_SIZE_64;
6176         default:
6177                 return ETH_RSS_RETA_SIZE_128;
6178         }
6179 }
6180
6181 uint32_t
6182 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6183         switch (mac_type) {
6184         case ixgbe_mac_X550:
6185         case ixgbe_mac_X550EM_x:
6186         case ixgbe_mac_X550EM_a:
6187                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6188                         return IXGBE_RETA(reta_idx >> 2);
6189                 else
6190                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6191         case ixgbe_mac_X550_vf:
6192         case ixgbe_mac_X550EM_x_vf:
6193         case ixgbe_mac_X550EM_a_vf:
6194                 return IXGBE_VFRETA(reta_idx >> 2);
6195         default:
6196                 return IXGBE_RETA(reta_idx >> 2);
6197         }
6198 }
6199
6200 uint32_t
6201 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6202         switch (mac_type) {
6203         case ixgbe_mac_X550_vf:
6204         case ixgbe_mac_X550EM_x_vf:
6205         case ixgbe_mac_X550EM_a_vf:
6206                 return IXGBE_VFMRQC;
6207         default:
6208                 return IXGBE_MRQC;
6209         }
6210 }
6211
6212 uint32_t
6213 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6214         switch (mac_type) {
6215         case ixgbe_mac_X550_vf:
6216         case ixgbe_mac_X550EM_x_vf:
6217         case ixgbe_mac_X550EM_a_vf:
6218                 return IXGBE_VFRSSRK(i);
6219         default:
6220                 return IXGBE_RSSRK(i);
6221         }
6222 }
6223
6224 bool
6225 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6226         switch (mac_type) {
6227         case ixgbe_mac_82599_vf:
6228         case ixgbe_mac_X540_vf:
6229                 return 0;
6230         default:
6231                 return 1;
6232         }
6233 }
6234
6235 static int
6236 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6237                         struct rte_eth_dcb_info *dcb_info)
6238 {
6239         struct ixgbe_dcb_config *dcb_config =
6240                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6241         struct ixgbe_dcb_tc_config *tc;
6242         uint8_t i, j;
6243
6244         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6245                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6246         else
6247                 dcb_info->nb_tcs = 1;
6248
6249         if (dcb_config->vt_mode) { /* vt is enabled*/
6250                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6251                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6252                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6253                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6254                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6255                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6256                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6257                                                 i * dcb_info->nb_tcs + j;
6258                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6259                                 dcb_info->tc_queue.tc_txq[i][j].base =
6260                                                 i * dcb_info->nb_tcs + j;
6261                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6262                         }
6263                 }
6264         } else { /* vt is disabled*/
6265                 struct rte_eth_dcb_rx_conf *rx_conf =
6266                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6267                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6268                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6269                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6270                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6271                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6272                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6273                         }
6274                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6275                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6276                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6277                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6278                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6279                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6280                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6281                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6282                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6283                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6284                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6285                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6286                         }
6287                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6288                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6289                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6290                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6291                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6292                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6293                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6294                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6295                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6296                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6297                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6298                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6299                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6300                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6301                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6302                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6303                 }
6304         }
6305         for (i = 0; i < dcb_info->nb_tcs; i++) {
6306                 tc = &dcb_config->tc_config[i];
6307                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6308         }
6309         return 0;
6310 }
6311
6312 /* Update e-tag ether type */
6313 static int
6314 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6315                             uint16_t ether_type)
6316 {
6317         uint32_t etag_etype;
6318
6319         if (hw->mac.type != ixgbe_mac_X550 &&
6320             hw->mac.type != ixgbe_mac_X550EM_x) {
6321                 return -ENOTSUP;
6322         }
6323
6324         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6325         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6326         etag_etype |= ether_type;
6327         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6328         IXGBE_WRITE_FLUSH(hw);
6329
6330         return 0;
6331 }
6332
6333 /* Config l2 tunnel ether type */
6334 static int
6335 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6336                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6337 {
6338         int ret = 0;
6339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6340
6341         if (l2_tunnel == NULL)
6342                 return -EINVAL;
6343
6344         switch (l2_tunnel->l2_tunnel_type) {
6345         case RTE_L2_TUNNEL_TYPE_E_TAG:
6346                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6347                 break;
6348         default:
6349                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6350                 ret = -EINVAL;
6351                 break;
6352         }
6353
6354         return ret;
6355 }
6356
6357 /* Enable e-tag tunnel */
6358 static int
6359 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6360 {
6361         uint32_t etag_etype;
6362
6363         if (hw->mac.type != ixgbe_mac_X550 &&
6364             hw->mac.type != ixgbe_mac_X550EM_x) {
6365                 return -ENOTSUP;
6366         }
6367
6368         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6369         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6370         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6371         IXGBE_WRITE_FLUSH(hw);
6372
6373         return 0;
6374 }
6375
6376 /* Enable l2 tunnel */
6377 static int
6378 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6379                            enum rte_eth_tunnel_type l2_tunnel_type)
6380 {
6381         int ret = 0;
6382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6383
6384         switch (l2_tunnel_type) {
6385         case RTE_L2_TUNNEL_TYPE_E_TAG:
6386                 ret = ixgbe_e_tag_enable(hw);
6387                 break;
6388         default:
6389                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6390                 ret = -EINVAL;
6391                 break;
6392         }
6393
6394         return ret;
6395 }
6396
6397 /* Disable e-tag tunnel */
6398 static int
6399 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6400 {
6401         uint32_t etag_etype;
6402
6403         if (hw->mac.type != ixgbe_mac_X550 &&
6404             hw->mac.type != ixgbe_mac_X550EM_x) {
6405                 return -ENOTSUP;
6406         }
6407
6408         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6409         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6410         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6411         IXGBE_WRITE_FLUSH(hw);
6412
6413         return 0;
6414 }
6415
6416 /* Disable l2 tunnel */
6417 static int
6418 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6419                             enum rte_eth_tunnel_type l2_tunnel_type)
6420 {
6421         int ret = 0;
6422         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6423
6424         switch (l2_tunnel_type) {
6425         case RTE_L2_TUNNEL_TYPE_E_TAG:
6426                 ret = ixgbe_e_tag_disable(hw);
6427                 break;
6428         default:
6429                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6430                 ret = -EINVAL;
6431                 break;
6432         }
6433
6434         return ret;
6435 }
6436
6437 static int
6438 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6439                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6440 {
6441         int ret = 0;
6442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6443         uint32_t i, rar_entries;
6444         uint32_t rar_low, rar_high;
6445
6446         if (hw->mac.type != ixgbe_mac_X550 &&
6447             hw->mac.type != ixgbe_mac_X550EM_x) {
6448                 return -ENOTSUP;
6449         }
6450
6451         rar_entries = ixgbe_get_num_rx_addrs(hw);
6452
6453         for (i = 1; i < rar_entries; i++) {
6454                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6455                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6456                 if ((rar_high & IXGBE_RAH_AV) &&
6457                     (rar_high & IXGBE_RAH_ADTYPE) &&
6458                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6459                      l2_tunnel->tunnel_id)) {
6460                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6461                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6462
6463                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6464
6465                         return ret;
6466                 }
6467         }
6468
6469         return ret;
6470 }
6471
6472 static int
6473 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6474                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6475 {
6476         int ret = 0;
6477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6478         uint32_t i, rar_entries;
6479         uint32_t rar_low, rar_high;
6480
6481         if (hw->mac.type != ixgbe_mac_X550 &&
6482             hw->mac.type != ixgbe_mac_X550EM_x) {
6483                 return -ENOTSUP;
6484         }
6485
6486         /* One entry for one tunnel. Try to remove potential existing entry. */
6487         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6488
6489         rar_entries = ixgbe_get_num_rx_addrs(hw);
6490
6491         for (i = 1; i < rar_entries; i++) {
6492                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6493                 if (rar_high & IXGBE_RAH_AV) {
6494                         continue;
6495                 } else {
6496                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6497                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6498                         rar_low = l2_tunnel->tunnel_id;
6499
6500                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6501                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6502
6503                         return ret;
6504                 }
6505         }
6506
6507         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6508                      " Please remove a rule before adding a new one.");
6509         return -EINVAL;
6510 }
6511
6512 /* Add l2 tunnel filter */
6513 static int
6514 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6515                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6516 {
6517         int ret = 0;
6518
6519         switch (l2_tunnel->l2_tunnel_type) {
6520         case RTE_L2_TUNNEL_TYPE_E_TAG:
6521                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6522                 break;
6523         default:
6524                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6525                 ret = -EINVAL;
6526                 break;
6527         }
6528
6529         return ret;
6530 }
6531
6532 /* Delete l2 tunnel filter */
6533 static int
6534 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6535                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6536 {
6537         int ret = 0;
6538
6539         switch (l2_tunnel->l2_tunnel_type) {
6540         case RTE_L2_TUNNEL_TYPE_E_TAG:
6541                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6542                 break;
6543         default:
6544                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6545                 ret = -EINVAL;
6546                 break;
6547         }
6548
6549         return ret;
6550 }
6551
6552 /**
6553  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6554  * @dev: pointer to rte_eth_dev structure
6555  * @filter_op:operation will be taken.
6556  * @arg: a pointer to specific structure corresponding to the filter_op
6557  */
6558 static int
6559 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6560                                   enum rte_filter_op filter_op,
6561                                   void *arg)
6562 {
6563         int ret = 0;
6564
6565         if (filter_op == RTE_ETH_FILTER_NOP)
6566                 return 0;
6567
6568         if (arg == NULL) {
6569                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6570                             filter_op);
6571                 return -EINVAL;
6572         }
6573
6574         switch (filter_op) {
6575         case RTE_ETH_FILTER_ADD:
6576                 ret = ixgbe_dev_l2_tunnel_filter_add
6577                         (dev,
6578                          (struct rte_eth_l2_tunnel_conf *)arg);
6579                 break;
6580         case RTE_ETH_FILTER_DELETE:
6581                 ret = ixgbe_dev_l2_tunnel_filter_del
6582                         (dev,
6583                          (struct rte_eth_l2_tunnel_conf *)arg);
6584                 break;
6585         default:
6586                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6587                 ret = -EINVAL;
6588                 break;
6589         }
6590         return ret;
6591 }
6592
6593 static int
6594 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6595 {
6596         int ret = 0;
6597         uint32_t ctrl;
6598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6599
6600         if (hw->mac.type != ixgbe_mac_X550 &&
6601             hw->mac.type != ixgbe_mac_X550EM_x) {
6602                 return -ENOTSUP;
6603         }
6604
6605         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6606         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6607         if (en)
6608                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6609         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6610
6611         return ret;
6612 }
6613
6614 /* Enable l2 tunnel forwarding */
6615 static int
6616 ixgbe_dev_l2_tunnel_forwarding_enable
6617         (struct rte_eth_dev *dev,
6618          enum rte_eth_tunnel_type l2_tunnel_type)
6619 {
6620         int ret = 0;
6621
6622         switch (l2_tunnel_type) {
6623         case RTE_L2_TUNNEL_TYPE_E_TAG:
6624                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6625                 break;
6626         default:
6627                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6628                 ret = -EINVAL;
6629                 break;
6630         }
6631
6632         return ret;
6633 }
6634
6635 /* Disable l2 tunnel forwarding */
6636 static int
6637 ixgbe_dev_l2_tunnel_forwarding_disable
6638         (struct rte_eth_dev *dev,
6639          enum rte_eth_tunnel_type l2_tunnel_type)
6640 {
6641         int ret = 0;
6642
6643         switch (l2_tunnel_type) {
6644         case RTE_L2_TUNNEL_TYPE_E_TAG:
6645                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6646                 break;
6647         default:
6648                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6649                 ret = -EINVAL;
6650                 break;
6651         }
6652
6653         return ret;
6654 }
6655
6656 static int
6657 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6658                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6659                              bool en)
6660 {
6661         int ret = 0;
6662         uint32_t vmtir, vmvir;
6663         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6664
6665         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6666                 PMD_DRV_LOG(ERR,
6667                             "VF id %u should be less than %u",
6668                             l2_tunnel->vf_id,
6669                             dev->pci_dev->max_vfs);
6670                 return -EINVAL;
6671         }
6672
6673         if (hw->mac.type != ixgbe_mac_X550 &&
6674             hw->mac.type != ixgbe_mac_X550EM_x) {
6675                 return -ENOTSUP;
6676         }
6677
6678         if (en)
6679                 vmtir = l2_tunnel->tunnel_id;
6680         else
6681                 vmtir = 0;
6682
6683         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6684
6685         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6686         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6687         if (en)
6688                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6689         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6690
6691         return ret;
6692 }
6693
6694 /* Enable l2 tunnel tag insertion */
6695 static int
6696 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6697                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6698 {
6699         int ret = 0;
6700
6701         switch (l2_tunnel->l2_tunnel_type) {
6702         case RTE_L2_TUNNEL_TYPE_E_TAG:
6703                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6704                 break;
6705         default:
6706                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6707                 ret = -EINVAL;
6708                 break;
6709         }
6710
6711         return ret;
6712 }
6713
6714 /* Disable l2 tunnel tag insertion */
6715 static int
6716 ixgbe_dev_l2_tunnel_insertion_disable
6717         (struct rte_eth_dev *dev,
6718          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6719 {
6720         int ret = 0;
6721
6722         switch (l2_tunnel->l2_tunnel_type) {
6723         case RTE_L2_TUNNEL_TYPE_E_TAG:
6724                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6725                 break;
6726         default:
6727                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6728                 ret = -EINVAL;
6729                 break;
6730         }
6731
6732         return ret;
6733 }
6734
6735 static int
6736 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6737                              bool en)
6738 {
6739         int ret = 0;
6740         uint32_t qde;
6741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6742
6743         if (hw->mac.type != ixgbe_mac_X550 &&
6744             hw->mac.type != ixgbe_mac_X550EM_x) {
6745                 return -ENOTSUP;
6746         }
6747
6748         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6749         if (en)
6750                 qde |= IXGBE_QDE_STRIP_TAG;
6751         else
6752                 qde &= ~IXGBE_QDE_STRIP_TAG;
6753         qde &= ~IXGBE_QDE_READ;
6754         qde |= IXGBE_QDE_WRITE;
6755         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6756
6757         return ret;
6758 }
6759
6760 /* Enable l2 tunnel tag stripping */
6761 static int
6762 ixgbe_dev_l2_tunnel_stripping_enable
6763         (struct rte_eth_dev *dev,
6764          enum rte_eth_tunnel_type l2_tunnel_type)
6765 {
6766         int ret = 0;
6767
6768         switch (l2_tunnel_type) {
6769         case RTE_L2_TUNNEL_TYPE_E_TAG:
6770                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6771                 break;
6772         default:
6773                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6774                 ret = -EINVAL;
6775                 break;
6776         }
6777
6778         return ret;
6779 }
6780
6781 /* Disable l2 tunnel tag stripping */
6782 static int
6783 ixgbe_dev_l2_tunnel_stripping_disable
6784         (struct rte_eth_dev *dev,
6785          enum rte_eth_tunnel_type l2_tunnel_type)
6786 {
6787         int ret = 0;
6788
6789         switch (l2_tunnel_type) {
6790         case RTE_L2_TUNNEL_TYPE_E_TAG:
6791                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6792                 break;
6793         default:
6794                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6795                 ret = -EINVAL;
6796                 break;
6797         }
6798
6799         return ret;
6800 }
6801
6802 /* Enable/disable l2 tunnel offload functions */
6803 static int
6804 ixgbe_dev_l2_tunnel_offload_set
6805         (struct rte_eth_dev *dev,
6806          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6807          uint32_t mask,
6808          uint8_t en)
6809 {
6810         int ret = 0;
6811
6812         if (l2_tunnel == NULL)
6813                 return -EINVAL;
6814
6815         ret = -EINVAL;
6816         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6817                 if (en)
6818                         ret = ixgbe_dev_l2_tunnel_enable(
6819                                 dev,
6820                                 l2_tunnel->l2_tunnel_type);
6821                 else
6822                         ret = ixgbe_dev_l2_tunnel_disable(
6823                                 dev,
6824                                 l2_tunnel->l2_tunnel_type);
6825         }
6826
6827         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6828                 if (en)
6829                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6830                                 dev,
6831                                 l2_tunnel);
6832                 else
6833                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6834                                 dev,
6835                                 l2_tunnel);
6836         }
6837
6838         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6839                 if (en)
6840                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6841                                 dev,
6842                                 l2_tunnel->l2_tunnel_type);
6843                 else
6844                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6845                                 dev,
6846                                 l2_tunnel->l2_tunnel_type);
6847         }
6848
6849         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6850                 if (en)
6851                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6852                                 dev,
6853                                 l2_tunnel->l2_tunnel_type);
6854                 else
6855                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6856                                 dev,
6857                                 l2_tunnel->l2_tunnel_type);
6858         }
6859
6860         return ret;
6861 }
6862
6863 static int
6864 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6865                         uint16_t port)
6866 {
6867         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6868         IXGBE_WRITE_FLUSH(hw);
6869
6870         return 0;
6871 }
6872
6873 /* There's only one register for VxLAN UDP port.
6874  * So, we cannot add several ports. Will update it.
6875  */
6876 static int
6877 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6878                      uint16_t port)
6879 {
6880         if (port == 0) {
6881                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6882                 return -EINVAL;
6883         }
6884
6885         return ixgbe_update_vxlan_port(hw, port);
6886 }
6887
6888 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6889  * UDP port, it must have a value.
6890  * So, will reset it to the original value 0.
6891  */
6892 static int
6893 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6894                      uint16_t port)
6895 {
6896         uint16_t cur_port;
6897
6898         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6899
6900         if (cur_port != port) {
6901                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6902                 return -EINVAL;
6903         }
6904
6905         return ixgbe_update_vxlan_port(hw, 0);
6906 }
6907
6908 /* Add UDP tunneling port */
6909 static int
6910 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6911                               struct rte_eth_udp_tunnel *udp_tunnel)
6912 {
6913         int ret = 0;
6914         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6915
6916         if (hw->mac.type != ixgbe_mac_X550 &&
6917             hw->mac.type != ixgbe_mac_X550EM_x) {
6918                 return -ENOTSUP;
6919         }
6920
6921         if (udp_tunnel == NULL)
6922                 return -EINVAL;
6923
6924         switch (udp_tunnel->prot_type) {
6925         case RTE_TUNNEL_TYPE_VXLAN:
6926                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6927                 break;
6928
6929         case RTE_TUNNEL_TYPE_GENEVE:
6930         case RTE_TUNNEL_TYPE_TEREDO:
6931                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6932                 ret = -EINVAL;
6933                 break;
6934
6935         default:
6936                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6937                 ret = -EINVAL;
6938                 break;
6939         }
6940
6941         return ret;
6942 }
6943
6944 /* Remove UDP tunneling port */
6945 static int
6946 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6947                               struct rte_eth_udp_tunnel *udp_tunnel)
6948 {
6949         int ret = 0;
6950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6951
6952         if (hw->mac.type != ixgbe_mac_X550 &&
6953             hw->mac.type != ixgbe_mac_X550EM_x) {
6954                 return -ENOTSUP;
6955         }
6956
6957         if (udp_tunnel == NULL)
6958                 return -EINVAL;
6959
6960         switch (udp_tunnel->prot_type) {
6961         case RTE_TUNNEL_TYPE_VXLAN:
6962                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6963                 break;
6964         case RTE_TUNNEL_TYPE_GENEVE:
6965         case RTE_TUNNEL_TYPE_TEREDO:
6966                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6967                 ret = -EINVAL;
6968                 break;
6969         default:
6970                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6971                 ret = -EINVAL;
6972                 break;
6973         }
6974
6975         return ret;
6976 }
6977
6978 /* ixgbevf_update_xcast_mode - Update Multicast mode
6979  * @hw: pointer to the HW structure
6980  * @netdev: pointer to net device structure
6981  * @xcast_mode: new multicast mode
6982  *
6983  * Updates the Multicast Mode of VF.
6984  */
6985 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
6986                                      int xcast_mode)
6987 {
6988         struct ixgbe_mbx_info *mbx = &hw->mbx;
6989         u32 msgbuf[2];
6990         s32 err;
6991
6992         switch (hw->api_version) {
6993         case ixgbe_mbox_api_12:
6994                 break;
6995         default:
6996                 return -EOPNOTSUPP;
6997         }
6998
6999         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7000         msgbuf[1] = xcast_mode;
7001
7002         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7003         if (err)
7004                 return err;
7005
7006         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7007         if (err)
7008                 return err;
7009
7010         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7011         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7012                 return -EPERM;
7013
7014         return 0;
7015 }
7016
7017 static void
7018 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7019 {
7020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7021
7022         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7023 }
7024
7025 static void
7026 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7027 {
7028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7029
7030         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7031 }
7032
7033 static struct rte_driver rte_ixgbe_driver = {
7034         .type = PMD_PDEV,
7035         .init = rte_ixgbe_pmd_init,
7036 };
7037
7038 static struct rte_driver rte_ixgbevf_driver = {
7039         .type = PMD_PDEV,
7040         .init = rte_ixgbevf_pmd_init,
7041 };
7042
7043 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7044 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);