1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
31 #include <rte_random.h>
33 #include <rte_hash_crc.h>
34 #ifdef RTE_LIBRTE_SECURITY
35 #include <rte_security_driver.h>
38 #include "ixgbe_logs.h"
39 #include "base/ixgbe_api.h"
40 #include "base/ixgbe_vf.h"
41 #include "base/ixgbe_common.h"
42 #include "ixgbe_ethdev.h"
43 #include "ixgbe_bypass.h"
44 #include "ixgbe_rxtx.h"
45 #include "base/ixgbe_type.h"
46 #include "base/ixgbe_phy.h"
47 #include "ixgbe_regs.h"
50 * High threshold controlling when to start sending XOFF frames. Must be at
51 * least 8 bytes less than receive packet buffer size. This value is in units
54 #define IXGBE_FC_HI 0x80
57 * Low threshold controlling when to start sending XON frames. This value is
58 * in units of 1024 bytes.
60 #define IXGBE_FC_LO 0x40
62 /* Timer value included in XOFF frames. */
63 #define IXGBE_FC_PAUSE 0x680
65 /*Default value of Max Rx Queue*/
66 #define IXGBE_MAX_RX_QUEUE_NUM 128
68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
69 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
70 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
72 #define IXGBE_MMW_SIZE_DEFAULT 0x4
73 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
74 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
77 * Default values for RX/TX configuration
79 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
80 #define IXGBE_DEFAULT_RX_PTHRESH 8
81 #define IXGBE_DEFAULT_RX_HTHRESH 8
82 #define IXGBE_DEFAULT_RX_WTHRESH 0
84 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
85 #define IXGBE_DEFAULT_TX_PTHRESH 32
86 #define IXGBE_DEFAULT_TX_HTHRESH 0
87 #define IXGBE_DEFAULT_TX_WTHRESH 0
88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
90 /* Bit shift and mask */
91 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
92 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
93 #define IXGBE_8_BIT_WIDTH CHAR_BIT
94 #define IXGBE_8_BIT_MASK UINT8_MAX
96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
100 /* Additional timesync values. */
101 #define NSEC_PER_SEC 1000000000L
102 #define IXGBE_INCVAL_10GB 0x66666666
103 #define IXGBE_INCVAL_1GB 0x40000000
104 #define IXGBE_INCVAL_100 0x50000000
105 #define IXGBE_INCVAL_SHIFT_10GB 28
106 #define IXGBE_INCVAL_SHIFT_1GB 24
107 #define IXGBE_INCVAL_SHIFT_100 21
108 #define IXGBE_INCVAL_SHIFT_82599 7
109 #define IXGBE_INCPER_SHIFT_82599 24
111 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
113 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
115 #define IXGBE_ETAG_ETYPE 0x00005084
116 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
117 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
118 #define IXGBE_RAH_ADTYPE 0x40000000
119 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
120 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
123 #define IXGBE_QDE_STRIP_TAG 0x00000004
124 #define IXGBE_VTEICR_MASK 0x07
126 #define IXGBE_EXVET_VET_EXT_SHIFT 16
127 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
148 int wait_to_complete);
149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
150 struct rte_eth_stats *stats);
151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
152 struct rte_eth_xstat *xstats, unsigned n);
153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
154 struct rte_eth_xstat *xstats, unsigned n);
156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
157 uint64_t *values, unsigned int n);
158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
161 struct rte_eth_xstat_name *xstats_names,
163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
164 struct rte_eth_xstat_name *xstats_names, unsigned limit);
165 static int ixgbe_dev_xstats_get_names_by_id(
166 struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names,
170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
177 struct rte_eth_dev_info *dev_info);
178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
180 struct rte_eth_dev_info *dev_info);
181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
184 uint16_t vlan_id, int on);
185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
186 enum rte_vlan_type vlan_type,
188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
189 uint16_t queue, bool on);
190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
192 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
193 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
194 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
195 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
196 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
198 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
199 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
200 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
201 struct rte_eth_fc_conf *fc_conf);
202 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
203 struct rte_eth_fc_conf *fc_conf);
204 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
205 struct rte_eth_pfc_conf *pfc_conf);
206 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
207 struct rte_eth_rss_reta_entry64 *reta_conf,
209 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
213 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
214 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
215 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
216 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
217 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
218 struct rte_intr_handle *handle);
219 static void ixgbe_dev_interrupt_handler(void *param);
220 static void ixgbe_dev_interrupt_delayed_handler(void *param);
221 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
222 uint32_t index, uint32_t pool);
223 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
224 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
225 struct ether_addr *mac_addr);
226 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
227 static bool is_device_supported(struct rte_eth_dev *dev,
228 struct rte_pci_driver *drv);
230 /* For Virtual Function support */
231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
233 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
234 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
235 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
236 int wait_to_complete);
237 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
238 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
239 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
240 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
241 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
242 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
243 struct rte_eth_stats *stats);
244 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
245 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
246 uint16_t vlan_id, int on);
247 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
248 uint16_t queue, int on);
249 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
250 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
251 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
253 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
255 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
256 uint8_t queue, uint8_t msix_vector);
257 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
258 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
259 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
261 /* For Eth VMDQ APIs support */
262 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
263 ether_addr * mac_addr, uint8_t on);
264 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
265 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
266 struct rte_eth_mirror_conf *mirror_conf,
267 uint8_t rule_id, uint8_t on);
268 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
270 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
272 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
274 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
275 uint8_t queue, uint8_t msix_vector);
276 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
278 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
279 struct ether_addr *mac_addr,
280 uint32_t index, uint32_t pool);
281 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
282 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
283 struct ether_addr *mac_addr);
284 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
285 struct rte_eth_syn_filter *filter);
286 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
287 enum rte_filter_op filter_op,
289 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
290 struct ixgbe_5tuple_filter *filter);
291 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
292 struct ixgbe_5tuple_filter *filter);
293 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
294 enum rte_filter_op filter_op,
296 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
297 struct rte_eth_ntuple_filter *filter);
298 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
299 enum rte_filter_op filter_op,
301 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
302 struct rte_eth_ethertype_filter *filter);
303 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
304 enum rte_filter_type filter_type,
305 enum rte_filter_op filter_op,
307 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
309 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
310 struct ether_addr *mc_addr_set,
311 uint32_t nb_mc_addr);
312 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
313 struct rte_eth_dcb_info *dcb_info);
315 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
316 static int ixgbe_get_regs(struct rte_eth_dev *dev,
317 struct rte_dev_reg_info *regs);
318 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
319 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
320 struct rte_dev_eeprom_info *eeprom);
321 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
322 struct rte_dev_eeprom_info *eeprom);
324 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
325 struct rte_eth_dev_module_info *modinfo);
326 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
327 struct rte_dev_eeprom_info *info);
329 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
330 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
331 struct rte_dev_reg_info *regs);
333 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
334 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
335 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
336 struct timespec *timestamp,
338 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
339 struct timespec *timestamp);
340 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
341 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
342 struct timespec *timestamp);
343 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
344 const struct timespec *timestamp);
345 static void ixgbevf_dev_interrupt_handler(void *param);
347 static int ixgbe_dev_l2_tunnel_eth_type_conf
348 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
349 static int ixgbe_dev_l2_tunnel_offload_set
350 (struct rte_eth_dev *dev,
351 struct rte_eth_l2_tunnel_conf *l2_tunnel,
354 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
355 enum rte_filter_op filter_op,
358 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
359 struct rte_eth_udp_tunnel *udp_tunnel);
360 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
361 struct rte_eth_udp_tunnel *udp_tunnel);
362 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
363 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
366 * Define VF Stats MACRO for Non "cleared on read" register
368 #define UPDATE_VF_STAT(reg, last, cur) \
370 uint32_t latest = IXGBE_READ_REG(hw, reg); \
371 cur += (latest - last) & UINT_MAX; \
375 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
377 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
378 u64 new_msb = IXGBE_READ_REG(hw, msb); \
379 u64 latest = ((new_msb << 32) | new_lsb); \
380 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
384 #define IXGBE_SET_HWSTRIP(h, q) do {\
385 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
386 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
387 (h)->bitmap[idx] |= 1 << bit;\
390 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
391 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
392 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
393 (h)->bitmap[idx] &= ~(1 << bit);\
396 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
397 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
398 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
399 (r) = (h)->bitmap[idx] >> bit & 1;\
402 int ixgbe_logtype_init;
403 int ixgbe_logtype_driver;
406 * The set of PCI devices this driver supports
408 static const struct rte_pci_id pci_id_ixgbe_map[] = {
409 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
410 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
457 #ifdef RTE_LIBRTE_IXGBE_BYPASS
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
460 { .vendor_id = 0, /* sentinel */ },
464 * The set of PCI devices this driver supports (for 82599 VF)
466 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
477 { .vendor_id = 0, /* sentinel */ },
480 static const struct rte_eth_desc_lim rx_desc_lim = {
481 .nb_max = IXGBE_MAX_RING_DESC,
482 .nb_min = IXGBE_MIN_RING_DESC,
483 .nb_align = IXGBE_RXD_ALIGN,
486 static const struct rte_eth_desc_lim tx_desc_lim = {
487 .nb_max = IXGBE_MAX_RING_DESC,
488 .nb_min = IXGBE_MIN_RING_DESC,
489 .nb_align = IXGBE_TXD_ALIGN,
490 .nb_seg_max = IXGBE_TX_MAX_SEG,
491 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
494 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
495 .dev_configure = ixgbe_dev_configure,
496 .dev_start = ixgbe_dev_start,
497 .dev_stop = ixgbe_dev_stop,
498 .dev_set_link_up = ixgbe_dev_set_link_up,
499 .dev_set_link_down = ixgbe_dev_set_link_down,
500 .dev_close = ixgbe_dev_close,
501 .dev_reset = ixgbe_dev_reset,
502 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
503 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
504 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
505 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
506 .link_update = ixgbe_dev_link_update,
507 .stats_get = ixgbe_dev_stats_get,
508 .xstats_get = ixgbe_dev_xstats_get,
509 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
510 .stats_reset = ixgbe_dev_stats_reset,
511 .xstats_reset = ixgbe_dev_xstats_reset,
512 .xstats_get_names = ixgbe_dev_xstats_get_names,
513 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
514 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
515 .fw_version_get = ixgbe_fw_version_get,
516 .dev_infos_get = ixgbe_dev_info_get,
517 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
518 .mtu_set = ixgbe_dev_mtu_set,
519 .vlan_filter_set = ixgbe_vlan_filter_set,
520 .vlan_tpid_set = ixgbe_vlan_tpid_set,
521 .vlan_offload_set = ixgbe_vlan_offload_set,
522 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
523 .rx_queue_start = ixgbe_dev_rx_queue_start,
524 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
525 .tx_queue_start = ixgbe_dev_tx_queue_start,
526 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
527 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
528 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
529 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
530 .rx_queue_release = ixgbe_dev_rx_queue_release,
531 .rx_queue_count = ixgbe_dev_rx_queue_count,
532 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
533 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
534 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
535 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
536 .tx_queue_release = ixgbe_dev_tx_queue_release,
537 .dev_led_on = ixgbe_dev_led_on,
538 .dev_led_off = ixgbe_dev_led_off,
539 .flow_ctrl_get = ixgbe_flow_ctrl_get,
540 .flow_ctrl_set = ixgbe_flow_ctrl_set,
541 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
542 .mac_addr_add = ixgbe_add_rar,
543 .mac_addr_remove = ixgbe_remove_rar,
544 .mac_addr_set = ixgbe_set_default_mac_addr,
545 .uc_hash_table_set = ixgbe_uc_hash_table_set,
546 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
547 .mirror_rule_set = ixgbe_mirror_rule_set,
548 .mirror_rule_reset = ixgbe_mirror_rule_reset,
549 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
550 .reta_update = ixgbe_dev_rss_reta_update,
551 .reta_query = ixgbe_dev_rss_reta_query,
552 .rss_hash_update = ixgbe_dev_rss_hash_update,
553 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
554 .filter_ctrl = ixgbe_dev_filter_ctrl,
555 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
556 .rxq_info_get = ixgbe_rxq_info_get,
557 .txq_info_get = ixgbe_txq_info_get,
558 .timesync_enable = ixgbe_timesync_enable,
559 .timesync_disable = ixgbe_timesync_disable,
560 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
561 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
562 .get_reg = ixgbe_get_regs,
563 .get_eeprom_length = ixgbe_get_eeprom_length,
564 .get_eeprom = ixgbe_get_eeprom,
565 .set_eeprom = ixgbe_set_eeprom,
566 .get_module_info = ixgbe_get_module_info,
567 .get_module_eeprom = ixgbe_get_module_eeprom,
568 .get_dcb_info = ixgbe_dev_get_dcb_info,
569 .timesync_adjust_time = ixgbe_timesync_adjust_time,
570 .timesync_read_time = ixgbe_timesync_read_time,
571 .timesync_write_time = ixgbe_timesync_write_time,
572 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
573 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
574 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
575 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
576 .tm_ops_get = ixgbe_tm_ops_get,
580 * dev_ops for virtual function, bare necessities for basic vf
581 * operation have been implemented
583 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
584 .dev_configure = ixgbevf_dev_configure,
585 .dev_start = ixgbevf_dev_start,
586 .dev_stop = ixgbevf_dev_stop,
587 .link_update = ixgbevf_dev_link_update,
588 .stats_get = ixgbevf_dev_stats_get,
589 .xstats_get = ixgbevf_dev_xstats_get,
590 .stats_reset = ixgbevf_dev_stats_reset,
591 .xstats_reset = ixgbevf_dev_stats_reset,
592 .xstats_get_names = ixgbevf_dev_xstats_get_names,
593 .dev_close = ixgbevf_dev_close,
594 .dev_reset = ixgbevf_dev_reset,
595 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
596 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
597 .dev_infos_get = ixgbevf_dev_info_get,
598 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
599 .mtu_set = ixgbevf_dev_set_mtu,
600 .vlan_filter_set = ixgbevf_vlan_filter_set,
601 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
602 .vlan_offload_set = ixgbevf_vlan_offload_set,
603 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
604 .rx_queue_release = ixgbe_dev_rx_queue_release,
605 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
606 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
607 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
608 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
609 .tx_queue_release = ixgbe_dev_tx_queue_release,
610 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
611 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
612 .mac_addr_add = ixgbevf_add_mac_addr,
613 .mac_addr_remove = ixgbevf_remove_mac_addr,
614 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
615 .rxq_info_get = ixgbe_rxq_info_get,
616 .txq_info_get = ixgbe_txq_info_get,
617 .mac_addr_set = ixgbevf_set_default_mac_addr,
618 .get_reg = ixgbevf_get_regs,
619 .reta_update = ixgbe_dev_rss_reta_update,
620 .reta_query = ixgbe_dev_rss_reta_query,
621 .rss_hash_update = ixgbe_dev_rss_hash_update,
622 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
625 /* store statistics names and its offset in stats structure */
626 struct rte_ixgbe_xstats_name_off {
627 char name[RTE_ETH_XSTATS_NAME_SIZE];
631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
632 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
633 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
634 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
635 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
636 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
637 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
638 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
639 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
640 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
641 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
642 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
643 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
644 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
645 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
646 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
648 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
650 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
651 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
652 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
653 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
654 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
655 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
656 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
657 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
658 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
659 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
660 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
661 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
662 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
663 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
664 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
665 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
666 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
668 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
670 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
671 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
672 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
673 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
675 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
677 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
679 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
681 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
683 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
685 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
688 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
689 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
690 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
692 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
693 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
694 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
695 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
696 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
698 {"rx_fcoe_no_direct_data_placement_ext_buff",
699 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
701 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
703 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
705 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
707 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
709 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
712 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
713 sizeof(rte_ixgbe_stats_strings[0]))
715 /* MACsec statistics */
716 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
717 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
719 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
720 out_pkts_encrypted)},
721 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
722 out_pkts_protected)},
723 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
724 out_octets_encrypted)},
725 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
726 out_octets_protected)},
727 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
729 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
731 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
733 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
734 in_pkts_unknownsci)},
735 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
736 in_octets_decrypted)},
737 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
738 in_octets_validated)},
739 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
741 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
743 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
754 in_pkts_notusingsa)},
757 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
758 sizeof(rte_ixgbe_macsec_strings[0]))
760 /* Per-queue statistics */
761 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
762 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
763 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
764 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
765 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
768 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
769 sizeof(rte_ixgbe_rxq_strings[0]))
770 #define IXGBE_NB_RXQ_PRIO_VALUES 8
772 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
773 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
774 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
775 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
779 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
780 sizeof(rte_ixgbe_txq_strings[0]))
781 #define IXGBE_NB_TXQ_PRIO_VALUES 8
783 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
784 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
787 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
788 sizeof(rte_ixgbevf_stats_strings[0]))
791 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
794 ixgbe_is_sfp(struct ixgbe_hw *hw)
796 switch (hw->phy.type) {
797 case ixgbe_phy_sfp_avago:
798 case ixgbe_phy_sfp_ftl:
799 case ixgbe_phy_sfp_intel:
800 case ixgbe_phy_sfp_unknown:
801 case ixgbe_phy_sfp_passive_tyco:
802 case ixgbe_phy_sfp_passive_unknown:
809 static inline int32_t
810 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
815 status = ixgbe_reset_hw(hw);
817 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
818 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
819 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
820 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
821 IXGBE_WRITE_FLUSH(hw);
823 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
824 status = IXGBE_SUCCESS;
829 ixgbe_enable_intr(struct rte_eth_dev *dev)
831 struct ixgbe_interrupt *intr =
832 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
833 struct ixgbe_hw *hw =
834 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
836 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
837 IXGBE_WRITE_FLUSH(hw);
841 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
844 ixgbe_disable_intr(struct ixgbe_hw *hw)
846 PMD_INIT_FUNC_TRACE();
848 if (hw->mac.type == ixgbe_mac_82598EB) {
849 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
851 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
852 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
853 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
855 IXGBE_WRITE_FLUSH(hw);
859 * This function resets queue statistics mapping registers.
860 * From Niantic datasheet, Initialization of Statistics section:
861 * "...if software requires the queue counters, the RQSMR and TQSM registers
862 * must be re-programmed following a device reset.
865 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
869 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
870 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
871 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
877 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
882 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
883 #define NB_QMAP_FIELDS_PER_QSM_REG 4
884 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
886 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
887 struct ixgbe_stat_mapping_registers *stat_mappings =
888 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
889 uint32_t qsmr_mask = 0;
890 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
894 if ((hw->mac.type != ixgbe_mac_82599EB) &&
895 (hw->mac.type != ixgbe_mac_X540) &&
896 (hw->mac.type != ixgbe_mac_X550) &&
897 (hw->mac.type != ixgbe_mac_X550EM_x) &&
898 (hw->mac.type != ixgbe_mac_X550EM_a))
901 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
902 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
905 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
906 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
907 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
910 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
912 /* Now clear any previous stat_idx set */
913 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
915 stat_mappings->tqsm[n] &= ~clearing_mask;
917 stat_mappings->rqsmr[n] &= ~clearing_mask;
919 q_map = (uint32_t)stat_idx;
920 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
921 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
923 stat_mappings->tqsm[n] |= qsmr_mask;
925 stat_mappings->rqsmr[n] |= qsmr_mask;
927 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
928 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
930 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
931 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
933 /* Now write the mapping in the appropriate register */
935 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
936 stat_mappings->rqsmr[n], n);
937 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
939 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
940 stat_mappings->tqsm[n], n);
941 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
947 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
949 struct ixgbe_stat_mapping_registers *stat_mappings =
950 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
951 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
954 /* write whatever was in stat mapping table to the NIC */
955 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
957 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
960 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
965 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
968 struct ixgbe_dcb_tc_config *tc;
969 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
971 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
972 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
973 for (i = 0; i < dcb_max_tc; i++) {
974 tc = &dcb_config->tc_config[i];
975 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
976 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
977 (uint8_t)(100/dcb_max_tc + (i & 1));
978 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
979 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
980 (uint8_t)(100/dcb_max_tc + (i & 1));
981 tc->pfc = ixgbe_dcb_pfc_disabled;
984 /* Initialize default user to priority mapping, UPx->TC0 */
985 tc = &dcb_config->tc_config[0];
986 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
987 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
988 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
989 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
990 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
992 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
993 dcb_config->pfc_mode_enable = false;
994 dcb_config->vt_mode = true;
995 dcb_config->round_robin_enable = false;
996 /* support all DCB capabilities in 82599 */
997 dcb_config->support.capabilities = 0xFF;
999 /*we only support 4 Tcs for X540, X550 */
1000 if (hw->mac.type == ixgbe_mac_X540 ||
1001 hw->mac.type == ixgbe_mac_X550 ||
1002 hw->mac.type == ixgbe_mac_X550EM_x ||
1003 hw->mac.type == ixgbe_mac_X550EM_a) {
1004 dcb_config->num_tcs.pg_tcs = 4;
1005 dcb_config->num_tcs.pfc_tcs = 4;
1010 * Ensure that all locks are released before first NVM or PHY access
1013 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 * Phy lock should not fail in this early stage. If this is the case,
1019 * it is due to an improper exit of the application.
1020 * So force the release of the faulty lock. Release of common lock
1021 * is done automatically by swfw_sync function.
1023 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1024 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1025 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1027 ixgbe_release_swfw_semaphore(hw, mask);
1030 * These ones are more tricky since they are common to all ports; but
1031 * swfw_sync retries last long enough (1s) to be almost sure that if
1032 * lock can not be taken it is due to an improper lock of the
1035 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1036 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1037 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1039 ixgbe_release_swfw_semaphore(hw, mask);
1043 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1044 * It returns 0 on success.
1047 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1049 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1050 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1051 struct ixgbe_hw *hw =
1052 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1053 struct ixgbe_vfta *shadow_vfta =
1054 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1055 struct ixgbe_hwstrip *hwstrip =
1056 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1057 struct ixgbe_dcb_config *dcb_config =
1058 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1059 struct ixgbe_filter_info *filter_info =
1060 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1061 struct ixgbe_bw_conf *bw_conf =
1062 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067 PMD_INIT_FUNC_TRACE();
1069 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1070 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1071 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1072 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1075 * For secondary processes, we don't initialise any further as primary
1076 * has already done this work. Only check we don't need a different
1077 * RX and TX function.
1079 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1080 struct ixgbe_tx_queue *txq;
1081 /* TX queue function in primary, set by last queue initialized
1082 * Tx queue may not initialized by primary process
1084 if (eth_dev->data->tx_queues) {
1085 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1086 ixgbe_set_tx_function(eth_dev, txq);
1088 /* Use default TX function if we get here */
1089 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1090 "Using default TX function.");
1093 ixgbe_set_rx_function(eth_dev);
1098 rte_eth_copy_pci_info(eth_dev, pci_dev);
1100 /* Vendor and Device ID need to be set before init of shared code */
1101 hw->device_id = pci_dev->id.device_id;
1102 hw->vendor_id = pci_dev->id.vendor_id;
1103 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1104 hw->allow_unsupported_sfp = 1;
1106 /* Initialize the shared code (base driver) */
1107 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1108 diag = ixgbe_bypass_init_shared_code(hw);
1110 diag = ixgbe_init_shared_code(hw);
1111 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1113 if (diag != IXGBE_SUCCESS) {
1114 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1118 /* pick up the PCI bus settings for reporting later */
1119 ixgbe_get_bus_info(hw);
1121 /* Unlock any pending hardware semaphore */
1122 ixgbe_swfw_lock_reset(hw);
1124 #ifdef RTE_LIBRTE_SECURITY
1125 /* Initialize security_ctx only for primary process*/
1126 if (ixgbe_ipsec_ctx_create(eth_dev))
1130 /* Initialize DCB configuration*/
1131 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1132 ixgbe_dcb_init(hw, dcb_config);
1133 /* Get Hardware Flow Control setting */
1134 hw->fc.requested_mode = ixgbe_fc_full;
1135 hw->fc.current_mode = ixgbe_fc_full;
1136 hw->fc.pause_time = IXGBE_FC_PAUSE;
1137 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1138 hw->fc.low_water[i] = IXGBE_FC_LO;
1139 hw->fc.high_water[i] = IXGBE_FC_HI;
1141 hw->fc.send_xon = 1;
1143 /* Make sure we have a good EEPROM before we read from it */
1144 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1145 if (diag != IXGBE_SUCCESS) {
1146 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1150 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1151 diag = ixgbe_bypass_init_hw(hw);
1153 diag = ixgbe_init_hw(hw);
1154 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1157 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1158 * is called too soon after the kernel driver unbinding/binding occurs.
1159 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1160 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1161 * also called. See ixgbe_identify_phy_82599(). The reason for the
1162 * failure is not known, and only occuts when virtualisation features
1163 * are disabled in the bios. A delay of 100ms was found to be enough by
1164 * trial-and-error, and is doubled to be safe.
1166 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1168 diag = ixgbe_init_hw(hw);
1171 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1172 diag = IXGBE_SUCCESS;
1174 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1175 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1176 "LOM. Please be aware there may be issues associated "
1177 "with your hardware.");
1178 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1179 "please contact your Intel or hardware representative "
1180 "who provided you with this hardware.");
1181 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1182 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1184 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1188 /* Reset the hw statistics */
1189 ixgbe_dev_stats_reset(eth_dev);
1191 /* disable interrupt */
1192 ixgbe_disable_intr(hw);
1194 /* reset mappings for queue statistics hw counters*/
1195 ixgbe_reset_qstat_mappings(hw);
1197 /* Allocate memory for storing MAC addresses */
1198 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1199 hw->mac.num_rar_entries, 0);
1200 if (eth_dev->data->mac_addrs == NULL) {
1202 "Failed to allocate %u bytes needed to store "
1204 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1207 /* Copy the permanent MAC address */
1208 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1209 ð_dev->data->mac_addrs[0]);
1211 /* Allocate memory for storing hash filter MAC addresses */
1212 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1213 IXGBE_VMDQ_NUM_UC_MAC, 0);
1214 if (eth_dev->data->hash_mac_addrs == NULL) {
1216 "Failed to allocate %d bytes needed to store MAC addresses",
1217 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1221 /* initialize the vfta */
1222 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1224 /* initialize the hw strip bitmap*/
1225 memset(hwstrip, 0, sizeof(*hwstrip));
1227 /* initialize PF if max_vfs not zero */
1228 ixgbe_pf_host_init(eth_dev);
1230 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1231 /* let hardware know driver is loaded */
1232 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1233 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1234 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1235 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1236 IXGBE_WRITE_FLUSH(hw);
1238 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1239 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1240 (int) hw->mac.type, (int) hw->phy.type,
1241 (int) hw->phy.sfp_type);
1243 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1244 (int) hw->mac.type, (int) hw->phy.type);
1246 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1247 eth_dev->data->port_id, pci_dev->id.vendor_id,
1248 pci_dev->id.device_id);
1250 rte_intr_callback_register(intr_handle,
1251 ixgbe_dev_interrupt_handler, eth_dev);
1253 /* enable uio/vfio intr/eventfd mapping */
1254 rte_intr_enable(intr_handle);
1256 /* enable support intr */
1257 ixgbe_enable_intr(eth_dev);
1259 /* initialize filter info */
1260 memset(filter_info, 0,
1261 sizeof(struct ixgbe_filter_info));
1263 /* initialize 5tuple filter list */
1264 TAILQ_INIT(&filter_info->fivetuple_list);
1266 /* initialize flow director filter list & hash */
1267 ixgbe_fdir_filter_init(eth_dev);
1269 /* initialize l2 tunnel filter list & hash */
1270 ixgbe_l2_tn_filter_init(eth_dev);
1272 /* initialize flow filter lists */
1273 ixgbe_filterlist_init();
1275 /* initialize bandwidth configuration info */
1276 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1278 /* initialize Traffic Manager configuration */
1279 ixgbe_tm_conf_init(eth_dev);
1285 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1287 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1288 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1289 struct ixgbe_hw *hw;
1293 PMD_INIT_FUNC_TRACE();
1295 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1298 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1300 if (hw->adapter_stopped == 0)
1301 ixgbe_dev_close(eth_dev);
1303 eth_dev->dev_ops = NULL;
1304 eth_dev->rx_pkt_burst = NULL;
1305 eth_dev->tx_pkt_burst = NULL;
1307 /* Unlock any pending hardware semaphore */
1308 ixgbe_swfw_lock_reset(hw);
1310 /* disable uio intr before callback unregister */
1311 rte_intr_disable(intr_handle);
1314 ret = rte_intr_callback_unregister(intr_handle,
1315 ixgbe_dev_interrupt_handler, eth_dev);
1318 } else if (ret != -EAGAIN) {
1320 "intr callback unregister failed: %d",
1325 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1327 /* uninitialize PF if max_vfs not zero */
1328 ixgbe_pf_host_uninit(eth_dev);
1330 rte_free(eth_dev->data->mac_addrs);
1331 eth_dev->data->mac_addrs = NULL;
1333 rte_free(eth_dev->data->hash_mac_addrs);
1334 eth_dev->data->hash_mac_addrs = NULL;
1336 /* remove all the fdir filters & hash */
1337 ixgbe_fdir_filter_uninit(eth_dev);
1339 /* remove all the L2 tunnel filters & hash */
1340 ixgbe_l2_tn_filter_uninit(eth_dev);
1342 /* Remove all ntuple filters of the device */
1343 ixgbe_ntuple_filter_uninit(eth_dev);
1345 /* clear all the filters list */
1346 ixgbe_filterlist_flush();
1348 /* Remove all Traffic Manager configuration */
1349 ixgbe_tm_conf_uninit(eth_dev);
1351 #ifdef RTE_LIBRTE_SECURITY
1352 rte_free(eth_dev->security_ctx);
1358 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1360 struct ixgbe_filter_info *filter_info =
1361 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1362 struct ixgbe_5tuple_filter *p_5tuple;
1364 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1365 TAILQ_REMOVE(&filter_info->fivetuple_list,
1370 memset(filter_info->fivetuple_mask, 0,
1371 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1376 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1378 struct ixgbe_hw_fdir_info *fdir_info =
1379 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1380 struct ixgbe_fdir_filter *fdir_filter;
1382 if (fdir_info->hash_map)
1383 rte_free(fdir_info->hash_map);
1384 if (fdir_info->hash_handle)
1385 rte_hash_free(fdir_info->hash_handle);
1387 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1388 TAILQ_REMOVE(&fdir_info->fdir_list,
1391 rte_free(fdir_filter);
1397 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1399 struct ixgbe_l2_tn_info *l2_tn_info =
1400 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1401 struct ixgbe_l2_tn_filter *l2_tn_filter;
1403 if (l2_tn_info->hash_map)
1404 rte_free(l2_tn_info->hash_map);
1405 if (l2_tn_info->hash_handle)
1406 rte_hash_free(l2_tn_info->hash_handle);
1408 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1409 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1412 rte_free(l2_tn_filter);
1418 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1420 struct ixgbe_hw_fdir_info *fdir_info =
1421 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1422 char fdir_hash_name[RTE_HASH_NAMESIZE];
1423 struct rte_hash_parameters fdir_hash_params = {
1424 .name = fdir_hash_name,
1425 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1426 .key_len = sizeof(union ixgbe_atr_input),
1427 .hash_func = rte_hash_crc,
1428 .hash_func_init_val = 0,
1429 .socket_id = rte_socket_id(),
1432 TAILQ_INIT(&fdir_info->fdir_list);
1433 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1434 "fdir_%s", eth_dev->device->name);
1435 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1436 if (!fdir_info->hash_handle) {
1437 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1440 fdir_info->hash_map = rte_zmalloc("ixgbe",
1441 sizeof(struct ixgbe_fdir_filter *) *
1442 IXGBE_MAX_FDIR_FILTER_NUM,
1444 if (!fdir_info->hash_map) {
1446 "Failed to allocate memory for fdir hash map!");
1449 fdir_info->mask_added = FALSE;
1454 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1456 struct ixgbe_l2_tn_info *l2_tn_info =
1457 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1458 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1459 struct rte_hash_parameters l2_tn_hash_params = {
1460 .name = l2_tn_hash_name,
1461 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1462 .key_len = sizeof(struct ixgbe_l2_tn_key),
1463 .hash_func = rte_hash_crc,
1464 .hash_func_init_val = 0,
1465 .socket_id = rte_socket_id(),
1468 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1469 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1470 "l2_tn_%s", eth_dev->device->name);
1471 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1472 if (!l2_tn_info->hash_handle) {
1473 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1476 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1477 sizeof(struct ixgbe_l2_tn_filter *) *
1478 IXGBE_MAX_L2_TN_FILTER_NUM,
1480 if (!l2_tn_info->hash_map) {
1482 "Failed to allocate memory for L2 TN hash map!");
1485 l2_tn_info->e_tag_en = FALSE;
1486 l2_tn_info->e_tag_fwd_en = FALSE;
1487 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1492 * Negotiate mailbox API version with the PF.
1493 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1494 * Then we try to negotiate starting with the most recent one.
1495 * If all negotiation attempts fail, then we will proceed with
1496 * the default one (ixgbe_mbox_api_10).
1499 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1503 /* start with highest supported, proceed down */
1504 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1511 i != RTE_DIM(sup_ver) &&
1512 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1518 generate_random_mac_addr(struct ether_addr *mac_addr)
1522 /* Set Organizationally Unique Identifier (OUI) prefix. */
1523 mac_addr->addr_bytes[0] = 0x00;
1524 mac_addr->addr_bytes[1] = 0x09;
1525 mac_addr->addr_bytes[2] = 0xC0;
1526 /* Force indication of locally assigned MAC address. */
1527 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1528 /* Generate the last 3 bytes of the MAC address with a random number. */
1529 random = rte_rand();
1530 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1534 * Virtual Function device init
1537 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1541 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1542 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1543 struct ixgbe_hw *hw =
1544 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1545 struct ixgbe_vfta *shadow_vfta =
1546 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1547 struct ixgbe_hwstrip *hwstrip =
1548 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1549 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1551 PMD_INIT_FUNC_TRACE();
1553 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1554 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1555 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1557 /* for secondary processes, we don't initialise any further as primary
1558 * has already done this work. Only check we don't need a different
1561 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1562 struct ixgbe_tx_queue *txq;
1563 /* TX queue function in primary, set by last queue initialized
1564 * Tx queue may not initialized by primary process
1566 if (eth_dev->data->tx_queues) {
1567 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1568 ixgbe_set_tx_function(eth_dev, txq);
1570 /* Use default TX function if we get here */
1571 PMD_INIT_LOG(NOTICE,
1572 "No TX queues configured yet. Using default TX function.");
1575 ixgbe_set_rx_function(eth_dev);
1580 rte_eth_copy_pci_info(eth_dev, pci_dev);
1582 hw->device_id = pci_dev->id.device_id;
1583 hw->vendor_id = pci_dev->id.vendor_id;
1584 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1586 /* initialize the vfta */
1587 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1589 /* initialize the hw strip bitmap*/
1590 memset(hwstrip, 0, sizeof(*hwstrip));
1592 /* Initialize the shared code (base driver) */
1593 diag = ixgbe_init_shared_code(hw);
1594 if (diag != IXGBE_SUCCESS) {
1595 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1599 /* init_mailbox_params */
1600 hw->mbx.ops.init_params(hw);
1602 /* Reset the hw statistics */
1603 ixgbevf_dev_stats_reset(eth_dev);
1605 /* Disable the interrupts for VF */
1606 ixgbevf_intr_disable(eth_dev);
1608 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1609 diag = hw->mac.ops.reset_hw(hw);
1612 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1613 * the underlying PF driver has not assigned a MAC address to the VF.
1614 * In this case, assign a random MAC address.
1616 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1617 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1621 /* negotiate mailbox API version to use with the PF. */
1622 ixgbevf_negotiate_api(hw);
1624 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1625 ixgbevf_get_queues(hw, &tcs, &tc);
1627 /* Allocate memory for storing MAC addresses */
1628 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1629 hw->mac.num_rar_entries, 0);
1630 if (eth_dev->data->mac_addrs == NULL) {
1632 "Failed to allocate %u bytes needed to store "
1634 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1638 /* Generate a random MAC address, if none was assigned by PF. */
1639 if (is_zero_ether_addr(perm_addr)) {
1640 generate_random_mac_addr(perm_addr);
1641 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1643 rte_free(eth_dev->data->mac_addrs);
1644 eth_dev->data->mac_addrs = NULL;
1647 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1648 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1649 "%02x:%02x:%02x:%02x:%02x:%02x",
1650 perm_addr->addr_bytes[0],
1651 perm_addr->addr_bytes[1],
1652 perm_addr->addr_bytes[2],
1653 perm_addr->addr_bytes[3],
1654 perm_addr->addr_bytes[4],
1655 perm_addr->addr_bytes[5]);
1658 /* Copy the permanent MAC address */
1659 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1661 /* reset the hardware with the new settings */
1662 diag = hw->mac.ops.start_hw(hw);
1668 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1672 rte_intr_callback_register(intr_handle,
1673 ixgbevf_dev_interrupt_handler, eth_dev);
1674 rte_intr_enable(intr_handle);
1675 ixgbevf_intr_enable(eth_dev);
1677 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1678 eth_dev->data->port_id, pci_dev->id.vendor_id,
1679 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1684 /* Virtual Function device uninit */
1687 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1689 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1690 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1691 struct ixgbe_hw *hw;
1693 PMD_INIT_FUNC_TRACE();
1695 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1698 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1700 if (hw->adapter_stopped == 0)
1701 ixgbevf_dev_close(eth_dev);
1703 eth_dev->dev_ops = NULL;
1704 eth_dev->rx_pkt_burst = NULL;
1705 eth_dev->tx_pkt_burst = NULL;
1707 /* Disable the interrupts for VF */
1708 ixgbevf_intr_disable(eth_dev);
1710 rte_free(eth_dev->data->mac_addrs);
1711 eth_dev->data->mac_addrs = NULL;
1713 rte_intr_disable(intr_handle);
1714 rte_intr_callback_unregister(intr_handle,
1715 ixgbevf_dev_interrupt_handler, eth_dev);
1721 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1722 struct rte_pci_device *pci_dev)
1724 char name[RTE_ETH_NAME_MAX_LEN];
1725 struct rte_eth_dev *pf_ethdev;
1726 struct rte_eth_devargs eth_da;
1729 if (pci_dev->device.devargs) {
1730 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1735 memset(ð_da, 0, sizeof(eth_da));
1737 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1738 sizeof(struct ixgbe_adapter),
1739 eth_dev_pci_specific_init, pci_dev,
1740 eth_ixgbe_dev_init, NULL);
1742 if (retval || eth_da.nb_representor_ports < 1)
1745 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1746 if (pf_ethdev == NULL)
1749 /* probe VF representor ports */
1750 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1751 struct ixgbe_vf_info *vfinfo;
1752 struct ixgbe_vf_representor representor;
1754 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1755 pf_ethdev->data->dev_private);
1756 if (vfinfo == NULL) {
1758 "no virtual functions supported by PF");
1762 representor.vf_id = eth_da.representor_ports[i];
1763 representor.switch_domain_id = vfinfo->switch_domain_id;
1764 representor.pf_ethdev = pf_ethdev;
1766 /* representor port net_bdf_port */
1767 snprintf(name, sizeof(name), "net_%s_representor_%d",
1768 pci_dev->device.name,
1769 eth_da.representor_ports[i]);
1771 retval = rte_eth_dev_create(&pci_dev->device, name,
1772 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1773 ixgbe_vf_representor_init, &representor);
1776 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1777 "representor %s.", name);
1783 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1785 struct rte_eth_dev *ethdev;
1787 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1791 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1792 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1794 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1797 static struct rte_pci_driver rte_ixgbe_pmd = {
1798 .id_table = pci_id_ixgbe_map,
1799 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1800 RTE_PCI_DRV_IOVA_AS_VA,
1801 .probe = eth_ixgbe_pci_probe,
1802 .remove = eth_ixgbe_pci_remove,
1805 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1806 struct rte_pci_device *pci_dev)
1808 return rte_eth_dev_pci_generic_probe(pci_dev,
1809 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1812 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1814 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1818 * virtual function driver struct
1820 static struct rte_pci_driver rte_ixgbevf_pmd = {
1821 .id_table = pci_id_ixgbevf_map,
1822 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1823 .probe = eth_ixgbevf_pci_probe,
1824 .remove = eth_ixgbevf_pci_remove,
1828 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1830 struct ixgbe_hw *hw =
1831 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832 struct ixgbe_vfta *shadow_vfta =
1833 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1838 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1839 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1840 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1845 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1847 /* update local VFTA copy */
1848 shadow_vfta->vfta[vid_idx] = vfta;
1854 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1857 ixgbe_vlan_hw_strip_enable(dev, queue);
1859 ixgbe_vlan_hw_strip_disable(dev, queue);
1863 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1864 enum rte_vlan_type vlan_type,
1867 struct ixgbe_hw *hw =
1868 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874 qinq &= IXGBE_DMATXCTL_GDV;
1876 switch (vlan_type) {
1877 case ETH_VLAN_TYPE_INNER:
1879 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1880 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1881 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1882 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1883 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1884 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1885 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1888 PMD_DRV_LOG(ERR, "Inner type is not supported"
1892 case ETH_VLAN_TYPE_OUTER:
1894 /* Only the high 16-bits is valid */
1895 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1896 IXGBE_EXVET_VET_EXT_SHIFT);
1898 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1899 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1900 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1901 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1902 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1903 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1904 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1910 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1918 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1920 struct ixgbe_hw *hw =
1921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 PMD_INIT_FUNC_TRACE();
1926 /* Filter Table Disable */
1927 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1928 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1930 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1934 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1936 struct ixgbe_hw *hw =
1937 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938 struct ixgbe_vfta *shadow_vfta =
1939 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1943 PMD_INIT_FUNC_TRACE();
1945 /* Filter Table Enable */
1946 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1947 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1948 vlnctrl |= IXGBE_VLNCTRL_VFE;
1950 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1952 /* write whatever is in local vfta copy */
1953 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1954 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1958 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1960 struct ixgbe_hwstrip *hwstrip =
1961 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1962 struct ixgbe_rx_queue *rxq;
1964 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1968 IXGBE_SET_HWSTRIP(hwstrip, queue);
1970 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1972 if (queue >= dev->data->nb_rx_queues)
1975 rxq = dev->data->rx_queues[queue];
1978 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1980 rxq->vlan_flags = PKT_RX_VLAN;
1984 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1986 struct ixgbe_hw *hw =
1987 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1990 PMD_INIT_FUNC_TRACE();
1992 if (hw->mac.type == ixgbe_mac_82598EB) {
1993 /* No queue level support */
1994 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1998 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1999 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2000 ctrl &= ~IXGBE_RXDCTL_VME;
2001 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2003 /* record those setting for HW strip per queue */
2004 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2008 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2010 struct ixgbe_hw *hw =
2011 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2014 PMD_INIT_FUNC_TRACE();
2016 if (hw->mac.type == ixgbe_mac_82598EB) {
2017 /* No queue level supported */
2018 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2022 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2023 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2024 ctrl |= IXGBE_RXDCTL_VME;
2025 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2027 /* record those setting for HW strip per queue */
2028 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2032 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2034 struct ixgbe_hw *hw =
2035 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2038 PMD_INIT_FUNC_TRACE();
2040 /* DMATXCTRL: Geric Double VLAN Disable */
2041 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2042 ctrl &= ~IXGBE_DMATXCTL_GDV;
2043 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2045 /* CTRL_EXT: Global Double VLAN Disable */
2046 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2047 ctrl &= ~IXGBE_EXTENDED_VLAN;
2048 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2053 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2055 struct ixgbe_hw *hw =
2056 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059 PMD_INIT_FUNC_TRACE();
2061 /* DMATXCTRL: Geric Double VLAN Enable */
2062 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2063 ctrl |= IXGBE_DMATXCTL_GDV;
2064 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2066 /* CTRL_EXT: Global Double VLAN Enable */
2067 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2068 ctrl |= IXGBE_EXTENDED_VLAN;
2069 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2071 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2072 if (hw->mac.type == ixgbe_mac_X550 ||
2073 hw->mac.type == ixgbe_mac_X550EM_x ||
2074 hw->mac.type == ixgbe_mac_X550EM_a) {
2075 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2076 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2077 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2081 * VET EXT field in the EXVET register = 0x8100 by default
2082 * So no need to change. Same to VT field of DMATXCTL register
2087 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2089 struct ixgbe_hw *hw =
2090 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2094 struct ixgbe_rx_queue *rxq;
2097 PMD_INIT_FUNC_TRACE();
2099 if (hw->mac.type == ixgbe_mac_82598EB) {
2100 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2101 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2102 ctrl |= IXGBE_VLNCTRL_VME;
2103 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2105 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2106 ctrl &= ~IXGBE_VLNCTRL_VME;
2107 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2111 * Other 10G NIC, the VLAN strip can be setup
2112 * per queue in RXDCTL
2114 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2115 rxq = dev->data->rx_queues[i];
2116 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2117 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2118 ctrl |= IXGBE_RXDCTL_VME;
2121 ctrl &= ~IXGBE_RXDCTL_VME;
2124 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2126 /* record those setting for HW strip per queue */
2127 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2133 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2135 struct rte_eth_rxmode *rxmode;
2136 rxmode = &dev->data->dev_conf.rxmode;
2138 if (mask & ETH_VLAN_STRIP_MASK) {
2139 ixgbe_vlan_hw_strip_config(dev);
2142 if (mask & ETH_VLAN_FILTER_MASK) {
2143 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2144 ixgbe_vlan_hw_filter_enable(dev);
2146 ixgbe_vlan_hw_filter_disable(dev);
2149 if (mask & ETH_VLAN_EXTEND_MASK) {
2150 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2151 ixgbe_vlan_hw_extend_enable(dev);
2153 ixgbe_vlan_hw_extend_disable(dev);
2160 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2162 struct ixgbe_hw *hw =
2163 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2164 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2165 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2167 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2168 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2172 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2174 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2179 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2182 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2188 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2189 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2190 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2191 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2196 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2198 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2199 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2201 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2203 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2204 /* check multi-queue mode */
2205 switch (dev_conf->rxmode.mq_mode) {
2206 case ETH_MQ_RX_VMDQ_DCB:
2207 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2209 case ETH_MQ_RX_VMDQ_DCB_RSS:
2210 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2211 PMD_INIT_LOG(ERR, "SRIOV active,"
2212 " unsupported mq_mode rx %d.",
2213 dev_conf->rxmode.mq_mode);
2216 case ETH_MQ_RX_VMDQ_RSS:
2217 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2218 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2219 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2220 PMD_INIT_LOG(ERR, "SRIOV is active,"
2221 " invalid queue number"
2222 " for VMDQ RSS, allowed"
2223 " value are 1, 2 or 4.");
2227 case ETH_MQ_RX_VMDQ_ONLY:
2228 case ETH_MQ_RX_NONE:
2229 /* if nothing mq mode configure, use default scheme */
2230 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2232 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2233 /* SRIOV only works in VMDq enable mode */
2234 PMD_INIT_LOG(ERR, "SRIOV is active,"
2235 " wrong mq_mode rx %d.",
2236 dev_conf->rxmode.mq_mode);
2240 switch (dev_conf->txmode.mq_mode) {
2241 case ETH_MQ_TX_VMDQ_DCB:
2242 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2243 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2245 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2246 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2250 /* check valid queue number */
2251 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2252 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2253 PMD_INIT_LOG(ERR, "SRIOV is active,"
2254 " nb_rx_q=%d nb_tx_q=%d queue number"
2255 " must be less than or equal to %d.",
2257 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2261 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2262 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2266 /* check configuration for vmdb+dcb mode */
2267 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2268 const struct rte_eth_vmdq_dcb_conf *conf;
2270 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2271 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2272 IXGBE_VMDQ_DCB_NB_QUEUES);
2275 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2276 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2277 conf->nb_queue_pools == ETH_32_POOLS)) {
2278 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2279 " nb_queue_pools must be %d or %d.",
2280 ETH_16_POOLS, ETH_32_POOLS);
2284 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2285 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2287 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2288 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2289 IXGBE_VMDQ_DCB_NB_QUEUES);
2292 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2293 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2294 conf->nb_queue_pools == ETH_32_POOLS)) {
2295 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2296 " nb_queue_pools != %d and"
2297 " nb_queue_pools != %d.",
2298 ETH_16_POOLS, ETH_32_POOLS);
2303 /* For DCB mode check our configuration before we go further */
2304 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2305 const struct rte_eth_dcb_rx_conf *conf;
2307 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2308 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2309 IXGBE_DCB_NB_QUEUES);
2312 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2313 if (!(conf->nb_tcs == ETH_4_TCS ||
2314 conf->nb_tcs == ETH_8_TCS)) {
2315 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2316 " and nb_tcs != %d.",
2317 ETH_4_TCS, ETH_8_TCS);
2322 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2323 const struct rte_eth_dcb_tx_conf *conf;
2325 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2326 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2327 IXGBE_DCB_NB_QUEUES);
2330 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2331 if (!(conf->nb_tcs == ETH_4_TCS ||
2332 conf->nb_tcs == ETH_8_TCS)) {
2333 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2334 " and nb_tcs != %d.",
2335 ETH_4_TCS, ETH_8_TCS);
2341 * When DCB/VT is off, maximum number of queues changes,
2342 * except for 82598EB, which remains constant.
2344 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2345 hw->mac.type != ixgbe_mac_82598EB) {
2346 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2348 "Neither VT nor DCB are enabled, "
2350 IXGBE_NONE_MODE_TX_NB_QUEUES);
2359 ixgbe_dev_configure(struct rte_eth_dev *dev)
2361 struct ixgbe_interrupt *intr =
2362 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2363 struct ixgbe_adapter *adapter =
2364 (struct ixgbe_adapter *)dev->data->dev_private;
2365 struct rte_eth_dev_info dev_info;
2366 uint64_t rx_offloads;
2367 uint64_t tx_offloads;
2370 PMD_INIT_FUNC_TRACE();
2371 /* multipe queue mode checking */
2372 ret = ixgbe_check_mq_mode(dev);
2374 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2379 ixgbe_dev_info_get(dev, &dev_info);
2380 rx_offloads = dev->data->dev_conf.rxmode.offloads;
2381 if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2382 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2383 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2384 rx_offloads, dev_info.rx_offload_capa);
2387 tx_offloads = dev->data->dev_conf.txmode.offloads;
2388 if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2389 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2390 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2391 tx_offloads, dev_info.tx_offload_capa);
2395 /* set flag to update link status after init */
2396 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2399 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2400 * allocation or vector Rx preconditions we will reset it.
2402 adapter->rx_bulk_alloc_allowed = true;
2403 adapter->rx_vec_allowed = true;
2409 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2411 struct ixgbe_hw *hw =
2412 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413 struct ixgbe_interrupt *intr =
2414 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2417 /* only set up it on X550EM_X */
2418 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2419 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2420 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2421 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2422 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2423 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2428 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2429 uint16_t tx_rate, uint64_t q_msk)
2431 struct ixgbe_hw *hw;
2432 struct ixgbe_vf_info *vfinfo;
2433 struct rte_eth_link link;
2434 uint8_t nb_q_per_pool;
2435 uint32_t queue_stride;
2436 uint32_t queue_idx, idx = 0, vf_idx;
2438 uint16_t total_rate = 0;
2439 struct rte_pci_device *pci_dev;
2441 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2442 rte_eth_link_get_nowait(dev->data->port_id, &link);
2444 if (vf >= pci_dev->max_vfs)
2447 if (tx_rate > link.link_speed)
2453 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2454 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2455 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2456 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2457 queue_idx = vf * queue_stride;
2458 queue_end = queue_idx + nb_q_per_pool - 1;
2459 if (queue_end >= hw->mac.max_tx_queues)
2463 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2466 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2468 total_rate += vfinfo[vf_idx].tx_rate[idx];
2474 /* Store tx_rate for this vf. */
2475 for (idx = 0; idx < nb_q_per_pool; idx++) {
2476 if (((uint64_t)0x1 << idx) & q_msk) {
2477 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2478 vfinfo[vf].tx_rate[idx] = tx_rate;
2479 total_rate += tx_rate;
2483 if (total_rate > dev->data->dev_link.link_speed) {
2484 /* Reset stored TX rate of the VF if it causes exceed
2487 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2491 /* Set RTTBCNRC of each queue/pool for vf X */
2492 for (; queue_idx <= queue_end; queue_idx++) {
2494 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2502 * Configure device link speed and setup link.
2503 * It returns 0 on success.
2506 ixgbe_dev_start(struct rte_eth_dev *dev)
2508 struct ixgbe_hw *hw =
2509 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2510 struct ixgbe_vf_info *vfinfo =
2511 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2512 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2513 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2514 uint32_t intr_vector = 0;
2515 int err, link_up = 0, negotiate = 0;
2517 uint32_t allowed_speeds = 0;
2521 uint32_t *link_speeds;
2522 struct ixgbe_tm_conf *tm_conf =
2523 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2525 PMD_INIT_FUNC_TRACE();
2527 /* IXGBE devices don't support:
2528 * - half duplex (checked afterwards for valid speeds)
2529 * - fixed speed: TODO implement
2531 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2533 "Invalid link_speeds for port %u, fix speed not supported",
2534 dev->data->port_id);
2538 /* disable uio/vfio intr/eventfd mapping */
2539 rte_intr_disable(intr_handle);
2542 hw->adapter_stopped = 0;
2543 ixgbe_stop_adapter(hw);
2545 /* reinitialize adapter
2546 * this calls reset and start
2548 status = ixgbe_pf_reset_hw(hw);
2551 hw->mac.ops.start_hw(hw);
2552 hw->mac.get_link_status = true;
2554 /* configure PF module if SRIOV enabled */
2555 ixgbe_pf_host_configure(dev);
2557 ixgbe_dev_phy_intr_setup(dev);
2559 /* check and configure queue intr-vector mapping */
2560 if ((rte_intr_cap_multiple(intr_handle) ||
2561 !RTE_ETH_DEV_SRIOV(dev).active) &&
2562 dev->data->dev_conf.intr_conf.rxq != 0) {
2563 intr_vector = dev->data->nb_rx_queues;
2564 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2565 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2566 IXGBE_MAX_INTR_QUEUE_NUM);
2569 if (rte_intr_efd_enable(intr_handle, intr_vector))
2573 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2574 intr_handle->intr_vec =
2575 rte_zmalloc("intr_vec",
2576 dev->data->nb_rx_queues * sizeof(int), 0);
2577 if (intr_handle->intr_vec == NULL) {
2578 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2579 " intr_vec", dev->data->nb_rx_queues);
2584 /* confiugre msix for sleep until rx interrupt */
2585 ixgbe_configure_msix(dev);
2587 /* initialize transmission unit */
2588 ixgbe_dev_tx_init(dev);
2590 /* This can fail when allocating mbufs for descriptor rings */
2591 err = ixgbe_dev_rx_init(dev);
2593 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2597 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2598 ETH_VLAN_EXTEND_MASK;
2599 err = ixgbe_vlan_offload_set(dev, mask);
2601 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2605 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2606 /* Enable vlan filtering for VMDq */
2607 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2610 /* Configure DCB hw */
2611 ixgbe_configure_dcb(dev);
2613 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2614 err = ixgbe_fdir_configure(dev);
2619 /* Restore vf rate limit */
2620 if (vfinfo != NULL) {
2621 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2622 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2623 if (vfinfo[vf].tx_rate[idx] != 0)
2624 ixgbe_set_vf_rate_limit(
2626 vfinfo[vf].tx_rate[idx],
2630 ixgbe_restore_statistics_mapping(dev);
2632 err = ixgbe_dev_rxtx_start(dev);
2634 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2638 /* Skip link setup if loopback mode is enabled for 82599. */
2639 if (hw->mac.type == ixgbe_mac_82599EB &&
2640 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2641 goto skip_link_setup;
2643 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2644 err = hw->mac.ops.setup_sfp(hw);
2649 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2650 /* Turn on the copper */
2651 ixgbe_set_phy_power(hw, true);
2653 /* Turn on the laser */
2654 ixgbe_enable_tx_laser(hw);
2657 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2660 dev->data->dev_link.link_status = link_up;
2662 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2666 switch (hw->mac.type) {
2667 case ixgbe_mac_X550:
2668 case ixgbe_mac_X550EM_x:
2669 case ixgbe_mac_X550EM_a:
2670 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2671 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2675 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2679 link_speeds = &dev->data->dev_conf.link_speeds;
2680 if (*link_speeds & ~allowed_speeds) {
2681 PMD_INIT_LOG(ERR, "Invalid link setting");
2686 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2687 switch (hw->mac.type) {
2688 case ixgbe_mac_82598EB:
2689 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2691 case ixgbe_mac_82599EB:
2692 case ixgbe_mac_X540:
2693 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2695 case ixgbe_mac_X550:
2696 case ixgbe_mac_X550EM_x:
2697 case ixgbe_mac_X550EM_a:
2698 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2701 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2704 if (*link_speeds & ETH_LINK_SPEED_10G)
2705 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2706 if (*link_speeds & ETH_LINK_SPEED_5G)
2707 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2708 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2709 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2710 if (*link_speeds & ETH_LINK_SPEED_1G)
2711 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2712 if (*link_speeds & ETH_LINK_SPEED_100M)
2713 speed |= IXGBE_LINK_SPEED_100_FULL;
2716 err = ixgbe_setup_link(hw, speed, link_up);
2720 ixgbe_dev_link_update(dev, 0);
2724 if (rte_intr_allow_others(intr_handle)) {
2725 /* check if lsc interrupt is enabled */
2726 if (dev->data->dev_conf.intr_conf.lsc != 0)
2727 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2729 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2730 ixgbe_dev_macsec_interrupt_setup(dev);
2732 rte_intr_callback_unregister(intr_handle,
2733 ixgbe_dev_interrupt_handler, dev);
2734 if (dev->data->dev_conf.intr_conf.lsc != 0)
2735 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2736 " no intr multiplex");
2739 /* check if rxq interrupt is enabled */
2740 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2741 rte_intr_dp_is_en(intr_handle))
2742 ixgbe_dev_rxq_interrupt_setup(dev);
2744 /* enable uio/vfio intr/eventfd mapping */
2745 rte_intr_enable(intr_handle);
2747 /* resume enabled intr since hw reset */
2748 ixgbe_enable_intr(dev);
2749 ixgbe_l2_tunnel_conf(dev);
2750 ixgbe_filter_restore(dev);
2752 if (tm_conf->root && !tm_conf->committed)
2753 PMD_DRV_LOG(WARNING,
2754 "please call hierarchy_commit() "
2755 "before starting the port");
2760 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2761 ixgbe_dev_clear_queues(dev);
2766 * Stop device: disable rx and tx functions to allow for reconfiguring.
2769 ixgbe_dev_stop(struct rte_eth_dev *dev)
2771 struct rte_eth_link link;
2772 struct ixgbe_hw *hw =
2773 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2774 struct ixgbe_vf_info *vfinfo =
2775 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2776 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2777 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2779 struct ixgbe_tm_conf *tm_conf =
2780 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2782 PMD_INIT_FUNC_TRACE();
2784 /* disable interrupts */
2785 ixgbe_disable_intr(hw);
2788 ixgbe_pf_reset_hw(hw);
2789 hw->adapter_stopped = 0;
2792 ixgbe_stop_adapter(hw);
2794 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2795 vfinfo[vf].clear_to_send = false;
2797 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2798 /* Turn off the copper */
2799 ixgbe_set_phy_power(hw, false);
2801 /* Turn off the laser */
2802 ixgbe_disable_tx_laser(hw);
2805 ixgbe_dev_clear_queues(dev);
2807 /* Clear stored conf */
2808 dev->data->scattered_rx = 0;
2811 /* Clear recorded link status */
2812 memset(&link, 0, sizeof(link));
2813 rte_eth_linkstatus_set(dev, &link);
2815 if (!rte_intr_allow_others(intr_handle))
2816 /* resume to the default handler */
2817 rte_intr_callback_register(intr_handle,
2818 ixgbe_dev_interrupt_handler,
2821 /* Clean datapath event and queue/vec mapping */
2822 rte_intr_efd_disable(intr_handle);
2823 if (intr_handle->intr_vec != NULL) {
2824 rte_free(intr_handle->intr_vec);
2825 intr_handle->intr_vec = NULL;
2828 /* reset hierarchy commit */
2829 tm_conf->committed = false;
2833 * Set device link up: enable tx.
2836 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2838 struct ixgbe_hw *hw =
2839 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2840 if (hw->mac.type == ixgbe_mac_82599EB) {
2841 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2842 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2843 /* Not suported in bypass mode */
2844 PMD_INIT_LOG(ERR, "Set link up is not supported "
2845 "by device id 0x%x", hw->device_id);
2851 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2852 /* Turn on the copper */
2853 ixgbe_set_phy_power(hw, true);
2855 /* Turn on the laser */
2856 ixgbe_enable_tx_laser(hw);
2863 * Set device link down: disable tx.
2866 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2868 struct ixgbe_hw *hw =
2869 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2870 if (hw->mac.type == ixgbe_mac_82599EB) {
2871 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2872 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2873 /* Not suported in bypass mode */
2874 PMD_INIT_LOG(ERR, "Set link down is not supported "
2875 "by device id 0x%x", hw->device_id);
2881 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2882 /* Turn off the copper */
2883 ixgbe_set_phy_power(hw, false);
2885 /* Turn off the laser */
2886 ixgbe_disable_tx_laser(hw);
2893 * Reset and stop device.
2896 ixgbe_dev_close(struct rte_eth_dev *dev)
2898 struct ixgbe_hw *hw =
2899 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901 PMD_INIT_FUNC_TRACE();
2903 ixgbe_pf_reset_hw(hw);
2905 ixgbe_dev_stop(dev);
2906 hw->adapter_stopped = 1;
2908 ixgbe_dev_free_queues(dev);
2910 ixgbe_disable_pcie_master(hw);
2912 /* reprogram the RAR[0] in case user changed it. */
2913 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2920 ixgbe_dev_reset(struct rte_eth_dev *dev)
2924 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2925 * its VF to make them align with it. The detailed notification
2926 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2927 * To avoid unexpected behavior in VF, currently reset of PF with
2928 * SR-IOV activation is not supported. It might be supported later.
2930 if (dev->data->sriov.active)
2933 ret = eth_ixgbe_dev_uninit(dev);
2937 ret = eth_ixgbe_dev_init(dev, NULL);
2943 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2944 struct ixgbe_hw_stats *hw_stats,
2945 struct ixgbe_macsec_stats *macsec_stats,
2946 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2947 uint64_t *total_qprc, uint64_t *total_qprdc)
2949 uint32_t bprc, lxon, lxoff, total;
2950 uint32_t delta_gprc = 0;
2952 /* Workaround for RX byte count not including CRC bytes when CRC
2953 * strip is enabled. CRC bytes are removed from counters when crc_strip
2956 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2957 IXGBE_HLREG0_RXCRCSTRP);
2959 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2960 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2961 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2962 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2964 for (i = 0; i < 8; i++) {
2965 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2967 /* global total per queue */
2968 hw_stats->mpc[i] += mp;
2969 /* Running comprehensive total for stats display */
2970 *total_missed_rx += hw_stats->mpc[i];
2971 if (hw->mac.type == ixgbe_mac_82598EB) {
2972 hw_stats->rnbc[i] +=
2973 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2974 hw_stats->pxonrxc[i] +=
2975 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2976 hw_stats->pxoffrxc[i] +=
2977 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2979 hw_stats->pxonrxc[i] +=
2980 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2981 hw_stats->pxoffrxc[i] +=
2982 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2983 hw_stats->pxon2offc[i] +=
2984 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2986 hw_stats->pxontxc[i] +=
2987 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2988 hw_stats->pxofftxc[i] +=
2989 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2991 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2992 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2993 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2994 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2996 delta_gprc += delta_qprc;
2998 hw_stats->qprc[i] += delta_qprc;
2999 hw_stats->qptc[i] += delta_qptc;
3001 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3002 hw_stats->qbrc[i] +=
3003 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3005 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3007 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3008 hw_stats->qbtc[i] +=
3009 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3011 hw_stats->qprdc[i] += delta_qprdc;
3012 *total_qprdc += hw_stats->qprdc[i];
3014 *total_qprc += hw_stats->qprc[i];
3015 *total_qbrc += hw_stats->qbrc[i];
3017 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3018 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3019 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3022 * An errata states that gprc actually counts good + missed packets:
3023 * Workaround to set gprc to summated queue packet receives
3025 hw_stats->gprc = *total_qprc;
3027 if (hw->mac.type != ixgbe_mac_82598EB) {
3028 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3029 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3030 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3031 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3032 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3033 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3034 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3035 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3037 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3038 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3039 /* 82598 only has a counter in the high register */
3040 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3041 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3042 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3044 uint64_t old_tpr = hw_stats->tpr;
3046 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3047 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3050 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3052 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3053 hw_stats->gptc += delta_gptc;
3054 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3055 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3058 * Workaround: mprc hardware is incorrectly counting
3059 * broadcasts, so for now we subtract those.
3061 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3062 hw_stats->bprc += bprc;
3063 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3064 if (hw->mac.type == ixgbe_mac_82598EB)
3065 hw_stats->mprc -= bprc;
3067 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3068 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3069 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3070 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3071 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3072 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3074 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3075 hw_stats->lxontxc += lxon;
3076 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3077 hw_stats->lxofftxc += lxoff;
3078 total = lxon + lxoff;
3080 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3081 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3082 hw_stats->gptc -= total;
3083 hw_stats->mptc -= total;
3084 hw_stats->ptc64 -= total;
3085 hw_stats->gotc -= total * ETHER_MIN_LEN;
3087 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3088 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3089 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3090 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3091 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3092 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3093 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3094 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3095 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3096 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3097 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3098 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3099 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3100 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3101 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3102 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3103 /* Only read FCOE on 82599 */
3104 if (hw->mac.type != ixgbe_mac_82598EB) {
3105 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3106 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3107 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3108 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3109 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3112 /* Flow Director Stats registers */
3113 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3114 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3116 /* MACsec Stats registers */
3117 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3118 macsec_stats->out_pkts_encrypted +=
3119 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3120 macsec_stats->out_pkts_protected +=
3121 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3122 macsec_stats->out_octets_encrypted +=
3123 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3124 macsec_stats->out_octets_protected +=
3125 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3126 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3127 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3128 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3129 macsec_stats->in_pkts_unknownsci +=
3130 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3131 macsec_stats->in_octets_decrypted +=
3132 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3133 macsec_stats->in_octets_validated +=
3134 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3135 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3136 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3137 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3138 for (i = 0; i < 2; i++) {
3139 macsec_stats->in_pkts_ok +=
3140 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3141 macsec_stats->in_pkts_invalid +=
3142 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3143 macsec_stats->in_pkts_notvalid +=
3144 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3146 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3147 macsec_stats->in_pkts_notusingsa +=
3148 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3152 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3155 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3157 struct ixgbe_hw *hw =
3158 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159 struct ixgbe_hw_stats *hw_stats =
3160 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3161 struct ixgbe_macsec_stats *macsec_stats =
3162 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3163 dev->data->dev_private);
3164 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3167 total_missed_rx = 0;
3172 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3173 &total_qbrc, &total_qprc, &total_qprdc);
3178 /* Fill out the rte_eth_stats statistics structure */
3179 stats->ipackets = total_qprc;
3180 stats->ibytes = total_qbrc;
3181 stats->opackets = hw_stats->gptc;
3182 stats->obytes = hw_stats->gotc;
3184 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3185 stats->q_ipackets[i] = hw_stats->qprc[i];
3186 stats->q_opackets[i] = hw_stats->qptc[i];
3187 stats->q_ibytes[i] = hw_stats->qbrc[i];
3188 stats->q_obytes[i] = hw_stats->qbtc[i];
3189 stats->q_errors[i] = hw_stats->qprdc[i];
3193 stats->imissed = total_missed_rx;
3194 stats->ierrors = hw_stats->crcerrs +
3211 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3213 struct ixgbe_hw_stats *stats =
3214 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3216 /* HW registers are cleared on read */
3217 ixgbe_dev_stats_get(dev, NULL);
3219 /* Reset software totals */
3220 memset(stats, 0, sizeof(*stats));
3223 /* This function calculates the number of xstats based on the current config */
3225 ixgbe_xstats_calc_num(void) {
3226 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3227 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3228 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3231 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3232 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3234 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3235 unsigned stat, i, count;
3237 if (xstats_names != NULL) {
3240 /* Note: limit >= cnt_stats checked upstream
3241 * in rte_eth_xstats_names()
3244 /* Extended stats from ixgbe_hw_stats */
3245 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3246 snprintf(xstats_names[count].name,
3247 sizeof(xstats_names[count].name),
3249 rte_ixgbe_stats_strings[i].name);
3254 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3255 snprintf(xstats_names[count].name,
3256 sizeof(xstats_names[count].name),
3258 rte_ixgbe_macsec_strings[i].name);
3262 /* RX Priority Stats */
3263 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3264 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3265 snprintf(xstats_names[count].name,
3266 sizeof(xstats_names[count].name),
3267 "rx_priority%u_%s", i,
3268 rte_ixgbe_rxq_strings[stat].name);
3273 /* TX Priority Stats */
3274 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3275 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3276 snprintf(xstats_names[count].name,
3277 sizeof(xstats_names[count].name),
3278 "tx_priority%u_%s", i,
3279 rte_ixgbe_txq_strings[stat].name);
3287 static int ixgbe_dev_xstats_get_names_by_id(
3288 struct rte_eth_dev *dev,
3289 struct rte_eth_xstat_name *xstats_names,
3290 const uint64_t *ids,
3294 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3295 unsigned int stat, i, count;
3297 if (xstats_names != NULL) {
3300 /* Note: limit >= cnt_stats checked upstream
3301 * in rte_eth_xstats_names()
3304 /* Extended stats from ixgbe_hw_stats */
3305 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3306 snprintf(xstats_names[count].name,
3307 sizeof(xstats_names[count].name),
3309 rte_ixgbe_stats_strings[i].name);
3314 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3315 snprintf(xstats_names[count].name,
3316 sizeof(xstats_names[count].name),
3318 rte_ixgbe_macsec_strings[i].name);
3322 /* RX Priority Stats */
3323 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3324 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3325 snprintf(xstats_names[count].name,
3326 sizeof(xstats_names[count].name),
3327 "rx_priority%u_%s", i,
3328 rte_ixgbe_rxq_strings[stat].name);
3333 /* TX Priority Stats */
3334 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3335 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3336 snprintf(xstats_names[count].name,
3337 sizeof(xstats_names[count].name),
3338 "tx_priority%u_%s", i,
3339 rte_ixgbe_txq_strings[stat].name);
3348 uint16_t size = ixgbe_xstats_calc_num();
3349 struct rte_eth_xstat_name xstats_names_copy[size];
3351 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3354 for (i = 0; i < limit; i++) {
3355 if (ids[i] >= size) {
3356 PMD_INIT_LOG(ERR, "id value isn't valid");
3359 strcpy(xstats_names[i].name,
3360 xstats_names_copy[ids[i]].name);
3365 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3366 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3370 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3373 if (xstats_names != NULL)
3374 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3375 snprintf(xstats_names[i].name,
3376 sizeof(xstats_names[i].name),
3377 "%s", rte_ixgbevf_stats_strings[i].name);
3378 return IXGBEVF_NB_XSTATS;
3382 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3385 struct ixgbe_hw *hw =
3386 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3387 struct ixgbe_hw_stats *hw_stats =
3388 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3389 struct ixgbe_macsec_stats *macsec_stats =
3390 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3391 dev->data->dev_private);
3392 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3393 unsigned i, stat, count = 0;
3395 count = ixgbe_xstats_calc_num();
3400 total_missed_rx = 0;
3405 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3406 &total_qbrc, &total_qprc, &total_qprdc);
3408 /* If this is a reset xstats is NULL, and we have cleared the
3409 * registers by reading them.
3414 /* Extended stats from ixgbe_hw_stats */
3416 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3417 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3418 rte_ixgbe_stats_strings[i].offset);
3419 xstats[count].id = count;
3424 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3425 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3426 rte_ixgbe_macsec_strings[i].offset);
3427 xstats[count].id = count;
3431 /* RX Priority Stats */
3432 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3433 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3434 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3435 rte_ixgbe_rxq_strings[stat].offset +
3436 (sizeof(uint64_t) * i));
3437 xstats[count].id = count;
3442 /* TX Priority Stats */
3443 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3444 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3445 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3446 rte_ixgbe_txq_strings[stat].offset +
3447 (sizeof(uint64_t) * i));
3448 xstats[count].id = count;
3456 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3457 uint64_t *values, unsigned int n)
3460 struct ixgbe_hw *hw =
3461 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462 struct ixgbe_hw_stats *hw_stats =
3463 IXGBE_DEV_PRIVATE_TO_STATS(
3464 dev->data->dev_private);
3465 struct ixgbe_macsec_stats *macsec_stats =
3466 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3467 dev->data->dev_private);
3468 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3469 unsigned int i, stat, count = 0;
3471 count = ixgbe_xstats_calc_num();
3473 if (!ids && n < count)
3476 total_missed_rx = 0;
3481 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3482 &total_missed_rx, &total_qbrc, &total_qprc,
3485 /* If this is a reset xstats is NULL, and we have cleared the
3486 * registers by reading them.
3488 if (!ids && !values)
3491 /* Extended stats from ixgbe_hw_stats */
3493 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3494 values[count] = *(uint64_t *)(((char *)hw_stats) +
3495 rte_ixgbe_stats_strings[i].offset);
3500 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3501 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3502 rte_ixgbe_macsec_strings[i].offset);
3506 /* RX Priority Stats */
3507 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3508 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3510 *(uint64_t *)(((char *)hw_stats) +
3511 rte_ixgbe_rxq_strings[stat].offset +
3512 (sizeof(uint64_t) * i));
3517 /* TX Priority Stats */
3518 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3519 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3521 *(uint64_t *)(((char *)hw_stats) +
3522 rte_ixgbe_txq_strings[stat].offset +
3523 (sizeof(uint64_t) * i));
3531 uint16_t size = ixgbe_xstats_calc_num();
3532 uint64_t values_copy[size];
3534 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3536 for (i = 0; i < n; i++) {
3537 if (ids[i] >= size) {
3538 PMD_INIT_LOG(ERR, "id value isn't valid");
3541 values[i] = values_copy[ids[i]];
3547 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3549 struct ixgbe_hw_stats *stats =
3550 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3551 struct ixgbe_macsec_stats *macsec_stats =
3552 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3553 dev->data->dev_private);
3555 unsigned count = ixgbe_xstats_calc_num();
3557 /* HW registers are cleared on read */
3558 ixgbe_dev_xstats_get(dev, NULL, count);
3560 /* Reset software totals */
3561 memset(stats, 0, sizeof(*stats));
3562 memset(macsec_stats, 0, sizeof(*macsec_stats));
3566 ixgbevf_update_stats(struct rte_eth_dev *dev)
3568 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3569 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3570 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3572 /* Good Rx packet, include VF loopback */
3573 UPDATE_VF_STAT(IXGBE_VFGPRC,
3574 hw_stats->last_vfgprc, hw_stats->vfgprc);
3576 /* Good Rx octets, include VF loopback */
3577 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3578 hw_stats->last_vfgorc, hw_stats->vfgorc);
3580 /* Good Tx packet, include VF loopback */
3581 UPDATE_VF_STAT(IXGBE_VFGPTC,
3582 hw_stats->last_vfgptc, hw_stats->vfgptc);
3584 /* Good Tx octets, include VF loopback */
3585 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3586 hw_stats->last_vfgotc, hw_stats->vfgotc);
3588 /* Rx Multicst Packet */
3589 UPDATE_VF_STAT(IXGBE_VFMPRC,
3590 hw_stats->last_vfmprc, hw_stats->vfmprc);
3594 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3597 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3598 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3601 if (n < IXGBEVF_NB_XSTATS)
3602 return IXGBEVF_NB_XSTATS;
3604 ixgbevf_update_stats(dev);
3609 /* Extended stats */
3610 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3612 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3613 rte_ixgbevf_stats_strings[i].offset);
3616 return IXGBEVF_NB_XSTATS;
3620 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3622 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3623 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3625 ixgbevf_update_stats(dev);
3630 stats->ipackets = hw_stats->vfgprc;
3631 stats->ibytes = hw_stats->vfgorc;
3632 stats->opackets = hw_stats->vfgptc;
3633 stats->obytes = hw_stats->vfgotc;
3638 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3640 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3641 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3643 /* Sync HW register to the last stats */
3644 ixgbevf_dev_stats_get(dev, NULL);
3646 /* reset HW current stats*/
3647 hw_stats->vfgprc = 0;
3648 hw_stats->vfgorc = 0;
3649 hw_stats->vfgptc = 0;
3650 hw_stats->vfgotc = 0;
3654 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3656 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657 u16 eeprom_verh, eeprom_verl;
3661 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3662 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3664 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3665 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3667 ret += 1; /* add the size of '\0' */
3668 if (fw_size < (u32)ret)
3675 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3677 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3678 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3681 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3682 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3683 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3685 * When DCB/VT is off, maximum number of queues changes,
3686 * except for 82598EB, which remains constant.
3688 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3689 hw->mac.type != ixgbe_mac_82598EB)
3690 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3692 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3693 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3694 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3695 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3696 dev_info->max_vfs = pci_dev->max_vfs;
3697 if (hw->mac.type == ixgbe_mac_82598EB)
3698 dev_info->max_vmdq_pools = ETH_16_POOLS;
3700 dev_info->max_vmdq_pools = ETH_64_POOLS;
3701 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3702 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3703 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3704 dev_info->rx_queue_offload_capa);
3705 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3706 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3708 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3710 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3711 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3712 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3714 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3719 dev_info->default_txconf = (struct rte_eth_txconf) {
3721 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3722 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3723 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3725 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3726 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3730 dev_info->rx_desc_lim = rx_desc_lim;
3731 dev_info->tx_desc_lim = tx_desc_lim;
3733 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3734 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3735 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3737 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3738 if (hw->mac.type == ixgbe_mac_X540 ||
3739 hw->mac.type == ixgbe_mac_X540_vf ||
3740 hw->mac.type == ixgbe_mac_X550 ||
3741 hw->mac.type == ixgbe_mac_X550_vf) {
3742 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3744 if (hw->mac.type == ixgbe_mac_X550) {
3745 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3746 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3750 static const uint32_t *
3751 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3753 static const uint32_t ptypes[] = {
3754 /* For non-vec functions,
3755 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3756 * for vec functions,
3757 * refers to _recv_raw_pkts_vec().
3761 RTE_PTYPE_L3_IPV4_EXT,
3763 RTE_PTYPE_L3_IPV6_EXT,
3767 RTE_PTYPE_TUNNEL_IP,
3768 RTE_PTYPE_INNER_L3_IPV6,
3769 RTE_PTYPE_INNER_L3_IPV6_EXT,
3770 RTE_PTYPE_INNER_L4_TCP,
3771 RTE_PTYPE_INNER_L4_UDP,
3775 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3776 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3777 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3778 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3781 #if defined(RTE_ARCH_X86)
3782 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3783 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3790 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3791 struct rte_eth_dev_info *dev_info)
3793 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3794 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3796 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3797 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3798 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3799 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3800 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3801 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3802 dev_info->max_vfs = pci_dev->max_vfs;
3803 if (hw->mac.type == ixgbe_mac_82598EB)
3804 dev_info->max_vmdq_pools = ETH_16_POOLS;
3806 dev_info->max_vmdq_pools = ETH_64_POOLS;
3807 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3808 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3809 dev_info->rx_queue_offload_capa);
3810 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3811 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3813 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3815 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3816 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3817 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3819 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3824 dev_info->default_txconf = (struct rte_eth_txconf) {
3826 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3827 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3828 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3830 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3831 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3835 dev_info->rx_desc_lim = rx_desc_lim;
3836 dev_info->tx_desc_lim = tx_desc_lim;
3840 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3841 int *link_up, int wait_to_complete)
3844 * for a quick link status checking, wait_to_compelet == 0,
3845 * skip PF link status checking
3847 bool no_pflink_check = wait_to_complete == 0;
3848 struct ixgbe_mbx_info *mbx = &hw->mbx;
3849 struct ixgbe_mac_info *mac = &hw->mac;
3850 uint32_t links_reg, in_msg;
3853 /* If we were hit with a reset drop the link */
3854 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3855 mac->get_link_status = true;
3857 if (!mac->get_link_status)
3860 /* if link status is down no point in checking to see if pf is up */
3861 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3862 if (!(links_reg & IXGBE_LINKS_UP))
3865 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3866 * before the link status is correct
3868 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3871 for (i = 0; i < 5; i++) {
3873 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3875 if (!(links_reg & IXGBE_LINKS_UP))
3880 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3881 case IXGBE_LINKS_SPEED_10G_82599:
3882 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3883 if (hw->mac.type >= ixgbe_mac_X550) {
3884 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3885 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3888 case IXGBE_LINKS_SPEED_1G_82599:
3889 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3891 case IXGBE_LINKS_SPEED_100_82599:
3892 *speed = IXGBE_LINK_SPEED_100_FULL;
3893 if (hw->mac.type == ixgbe_mac_X550) {
3894 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3895 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3898 case IXGBE_LINKS_SPEED_10_X550EM_A:
3899 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3900 /* Since Reserved in older MAC's */
3901 if (hw->mac.type >= ixgbe_mac_X550)
3902 *speed = IXGBE_LINK_SPEED_10_FULL;
3905 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3908 if (no_pflink_check) {
3909 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3910 mac->get_link_status = true;
3912 mac->get_link_status = false;
3916 /* if the read failed it could just be a mailbox collision, best wait
3917 * until we are called again and don't report an error
3919 if (mbx->ops.read(hw, &in_msg, 1, 0))
3922 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3923 /* msg is not CTS and is NACK we must have lost CTS status */
3924 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3929 /* the pf is talking, if we timed out in the past we reinit */
3930 if (!mbx->timeout) {
3935 /* if we passed all the tests above then the link is up and we no
3936 * longer need to check for link
3938 mac->get_link_status = false;
3941 *link_up = !mac->get_link_status;
3945 /* return 0 means link status changed, -1 means not changed */
3947 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3948 int wait_to_complete, int vf)
3950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951 struct rte_eth_link link;
3952 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3953 struct ixgbe_interrupt *intr =
3954 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3959 bool autoneg = false;
3961 memset(&link, 0, sizeof(link));
3962 link.link_status = ETH_LINK_DOWN;
3963 link.link_speed = ETH_SPEED_NUM_NONE;
3964 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3965 link.link_autoneg = ETH_LINK_AUTONEG;
3967 hw->mac.get_link_status = true;
3969 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3970 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3971 speed = hw->phy.autoneg_advertised;
3973 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3974 ixgbe_setup_link(hw, speed, true);
3977 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3978 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3982 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3984 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3987 link.link_speed = ETH_SPEED_NUM_100M;
3988 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3989 return rte_eth_linkstatus_set(dev, &link);
3993 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3994 return rte_eth_linkstatus_set(dev, &link);
3997 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3998 link.link_status = ETH_LINK_UP;
3999 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4001 switch (link_speed) {
4003 case IXGBE_LINK_SPEED_UNKNOWN:
4004 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4005 link.link_speed = ETH_SPEED_NUM_100M;
4008 case IXGBE_LINK_SPEED_100_FULL:
4009 link.link_speed = ETH_SPEED_NUM_100M;
4012 case IXGBE_LINK_SPEED_1GB_FULL:
4013 link.link_speed = ETH_SPEED_NUM_1G;
4016 case IXGBE_LINK_SPEED_2_5GB_FULL:
4017 link.link_speed = ETH_SPEED_NUM_2_5G;
4020 case IXGBE_LINK_SPEED_5GB_FULL:
4021 link.link_speed = ETH_SPEED_NUM_5G;
4024 case IXGBE_LINK_SPEED_10GB_FULL:
4025 link.link_speed = ETH_SPEED_NUM_10G;
4029 return rte_eth_linkstatus_set(dev, &link);
4033 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4035 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4039 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4041 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4045 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4047 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4050 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4051 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4052 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4056 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4061 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4062 fctrl &= (~IXGBE_FCTRL_UPE);
4063 if (dev->data->all_multicast == 1)
4064 fctrl |= IXGBE_FCTRL_MPE;
4066 fctrl &= (~IXGBE_FCTRL_MPE);
4067 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4071 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4073 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4076 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4077 fctrl |= IXGBE_FCTRL_MPE;
4078 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4082 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4084 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4087 if (dev->data->promiscuous == 1)
4088 return; /* must remain in all_multicast mode */
4090 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4091 fctrl &= (~IXGBE_FCTRL_MPE);
4092 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4096 * It clears the interrupt causes and enables the interrupt.
4097 * It will be called once only during nic initialized.
4100 * Pointer to struct rte_eth_dev.
4102 * Enable or Disable.
4105 * - On success, zero.
4106 * - On failure, a negative value.
4109 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4111 struct ixgbe_interrupt *intr =
4112 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4114 ixgbe_dev_link_status_print(dev);
4116 intr->mask |= IXGBE_EICR_LSC;
4118 intr->mask &= ~IXGBE_EICR_LSC;
4124 * It clears the interrupt causes and enables the interrupt.
4125 * It will be called once only during nic initialized.
4128 * Pointer to struct rte_eth_dev.
4131 * - On success, zero.
4132 * - On failure, a negative value.
4135 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4137 struct ixgbe_interrupt *intr =
4138 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4140 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4146 * It clears the interrupt causes and enables the interrupt.
4147 * It will be called once only during nic initialized.
4150 * Pointer to struct rte_eth_dev.
4153 * - On success, zero.
4154 * - On failure, a negative value.
4157 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4159 struct ixgbe_interrupt *intr =
4160 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4162 intr->mask |= IXGBE_EICR_LINKSEC;
4168 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4171 * Pointer to struct rte_eth_dev.
4174 * - On success, zero.
4175 * - On failure, a negative value.
4178 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4181 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4182 struct ixgbe_interrupt *intr =
4183 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4185 /* clear all cause mask */
4186 ixgbe_disable_intr(hw);
4188 /* read-on-clear nic registers here */
4189 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4190 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4194 /* set flag for async link update */
4195 if (eicr & IXGBE_EICR_LSC)
4196 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4198 if (eicr & IXGBE_EICR_MAILBOX)
4199 intr->flags |= IXGBE_FLAG_MAILBOX;
4201 if (eicr & IXGBE_EICR_LINKSEC)
4202 intr->flags |= IXGBE_FLAG_MACSEC;
4204 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4205 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4206 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4207 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4213 * It gets and then prints the link status.
4216 * Pointer to struct rte_eth_dev.
4219 * - On success, zero.
4220 * - On failure, a negative value.
4223 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4225 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4226 struct rte_eth_link link;
4228 rte_eth_linkstatus_get(dev, &link);
4230 if (link.link_status) {
4231 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4232 (int)(dev->data->port_id),
4233 (unsigned)link.link_speed,
4234 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4235 "full-duplex" : "half-duplex");
4237 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4238 (int)(dev->data->port_id));
4240 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4241 pci_dev->addr.domain,
4243 pci_dev->addr.devid,
4244 pci_dev->addr.function);
4248 * It executes link_update after knowing an interrupt occurred.
4251 * Pointer to struct rte_eth_dev.
4254 * - On success, zero.
4255 * - On failure, a negative value.
4258 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4259 struct rte_intr_handle *intr_handle)
4261 struct ixgbe_interrupt *intr =
4262 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4264 struct ixgbe_hw *hw =
4265 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4267 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4269 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4270 ixgbe_pf_mbx_process(dev);
4271 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4274 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4275 ixgbe_handle_lasi(hw);
4276 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4279 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4280 struct rte_eth_link link;
4282 /* get the link status before link update, for predicting later */
4283 rte_eth_linkstatus_get(dev, &link);
4285 ixgbe_dev_link_update(dev, 0);
4288 if (!link.link_status)
4289 /* handle it 1 sec later, wait it being stable */
4290 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4291 /* likely to down */
4293 /* handle it 4 sec later, wait it being stable */
4294 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4296 ixgbe_dev_link_status_print(dev);
4297 if (rte_eal_alarm_set(timeout * 1000,
4298 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4299 PMD_DRV_LOG(ERR, "Error setting alarm");
4301 /* remember original mask */
4302 intr->mask_original = intr->mask;
4303 /* only disable lsc interrupt */
4304 intr->mask &= ~IXGBE_EIMS_LSC;
4308 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4309 ixgbe_enable_intr(dev);
4310 rte_intr_enable(intr_handle);
4316 * Interrupt handler which shall be registered for alarm callback for delayed
4317 * handling specific interrupt to wait for the stable nic state. As the
4318 * NIC interrupt state is not stable for ixgbe after link is just down,
4319 * it needs to wait 4 seconds to get the stable status.
4322 * Pointer to interrupt handle.
4324 * The address of parameter (struct rte_eth_dev *) regsitered before.
4330 ixgbe_dev_interrupt_delayed_handler(void *param)
4332 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4333 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4334 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4335 struct ixgbe_interrupt *intr =
4336 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4337 struct ixgbe_hw *hw =
4338 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4341 ixgbe_disable_intr(hw);
4343 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4344 if (eicr & IXGBE_EICR_MAILBOX)
4345 ixgbe_pf_mbx_process(dev);
4347 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4348 ixgbe_handle_lasi(hw);
4349 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4352 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4353 ixgbe_dev_link_update(dev, 0);
4354 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4355 ixgbe_dev_link_status_print(dev);
4356 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4360 if (intr->flags & IXGBE_FLAG_MACSEC) {
4361 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4363 intr->flags &= ~IXGBE_FLAG_MACSEC;
4366 /* restore original mask */
4367 intr->mask = intr->mask_original;
4368 intr->mask_original = 0;
4370 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4371 ixgbe_enable_intr(dev);
4372 rte_intr_enable(intr_handle);
4376 * Interrupt handler triggered by NIC for handling
4377 * specific interrupt.
4380 * Pointer to interrupt handle.
4382 * The address of parameter (struct rte_eth_dev *) regsitered before.
4388 ixgbe_dev_interrupt_handler(void *param)
4390 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4392 ixgbe_dev_interrupt_get_status(dev);
4393 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4397 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4399 struct ixgbe_hw *hw;
4401 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4402 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4406 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4408 struct ixgbe_hw *hw;
4410 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4411 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4415 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4417 struct ixgbe_hw *hw;
4423 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4425 fc_conf->pause_time = hw->fc.pause_time;
4426 fc_conf->high_water = hw->fc.high_water[0];
4427 fc_conf->low_water = hw->fc.low_water[0];
4428 fc_conf->send_xon = hw->fc.send_xon;
4429 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4432 * Return rx_pause status according to actual setting of
4435 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4436 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4442 * Return tx_pause status according to actual setting of
4445 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4446 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4451 if (rx_pause && tx_pause)
4452 fc_conf->mode = RTE_FC_FULL;
4454 fc_conf->mode = RTE_FC_RX_PAUSE;
4456 fc_conf->mode = RTE_FC_TX_PAUSE;
4458 fc_conf->mode = RTE_FC_NONE;
4464 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4466 struct ixgbe_hw *hw;
4468 uint32_t rx_buf_size;
4469 uint32_t max_high_water;
4471 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4478 PMD_INIT_FUNC_TRACE();
4480 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4482 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4485 * At least reserve one Ethernet frame for watermark
4486 * high_water/low_water in kilo bytes for ixgbe
4488 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4489 if ((fc_conf->high_water > max_high_water) ||
4490 (fc_conf->high_water < fc_conf->low_water)) {
4491 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4492 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4496 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4497 hw->fc.pause_time = fc_conf->pause_time;
4498 hw->fc.high_water[0] = fc_conf->high_water;
4499 hw->fc.low_water[0] = fc_conf->low_water;
4500 hw->fc.send_xon = fc_conf->send_xon;
4501 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4503 err = ixgbe_fc_enable(hw);
4505 /* Not negotiated is not an error case */
4506 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4508 /* check if we want to forward MAC frames - driver doesn't have native
4509 * capability to do that, so we'll write the registers ourselves */
4511 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4513 /* set or clear MFLCN.PMCF bit depending on configuration */
4514 if (fc_conf->mac_ctrl_frame_fwd != 0)
4515 mflcn |= IXGBE_MFLCN_PMCF;
4517 mflcn &= ~IXGBE_MFLCN_PMCF;
4519 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4520 IXGBE_WRITE_FLUSH(hw);
4525 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4530 * ixgbe_pfc_enable_generic - Enable flow control
4531 * @hw: pointer to hardware structure
4532 * @tc_num: traffic class number
4533 * Enable flow control according to the current settings.
4536 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4539 uint32_t mflcn_reg, fccfg_reg;
4541 uint32_t fcrtl, fcrth;
4545 /* Validate the water mark configuration */
4546 if (!hw->fc.pause_time) {
4547 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4551 /* Low water mark of zero causes XOFF floods */
4552 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4553 /* High/Low water can not be 0 */
4554 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4555 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4556 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4560 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4561 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4562 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4566 /* Negotiate the fc mode to use */
4567 ixgbe_fc_autoneg(hw);
4569 /* Disable any previous flow control settings */
4570 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4571 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4573 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4574 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4576 switch (hw->fc.current_mode) {
4579 * If the count of enabled RX Priority Flow control >1,
4580 * and the TX pause can not be disabled
4583 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4584 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4585 if (reg & IXGBE_FCRTH_FCEN)
4589 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4591 case ixgbe_fc_rx_pause:
4593 * Rx Flow control is enabled and Tx Flow control is
4594 * disabled by software override. Since there really
4595 * isn't a way to advertise that we are capable of RX
4596 * Pause ONLY, we will advertise that we support both
4597 * symmetric and asymmetric Rx PAUSE. Later, we will
4598 * disable the adapter's ability to send PAUSE frames.
4600 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4602 * If the count of enabled RX Priority Flow control >1,
4603 * and the TX pause can not be disabled
4606 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4607 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4608 if (reg & IXGBE_FCRTH_FCEN)
4612 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4614 case ixgbe_fc_tx_pause:
4616 * Tx Flow control is enabled, and Rx Flow control is
4617 * disabled by software override.
4619 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4622 /* Flow control (both Rx and Tx) is enabled by SW override. */
4623 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4624 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4627 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4628 ret_val = IXGBE_ERR_CONFIG;
4632 /* Set 802.3x based flow control settings. */
4633 mflcn_reg |= IXGBE_MFLCN_DPF;
4634 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4635 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4637 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4638 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4639 hw->fc.high_water[tc_num]) {
4640 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4641 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4642 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4644 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4646 * In order to prevent Tx hangs when the internal Tx
4647 * switch is enabled we must set the high water mark
4648 * to the maximum FCRTH value. This allows the Tx
4649 * switch to function even under heavy Rx workloads.
4651 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4653 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4655 /* Configure pause time (2 TCs per register) */
4656 reg = hw->fc.pause_time * 0x00010001;
4657 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4658 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4660 /* Configure flow control refresh threshold value */
4661 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4668 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4670 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4673 if (hw->mac.type != ixgbe_mac_82598EB) {
4674 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4680 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4683 uint32_t rx_buf_size;
4684 uint32_t max_high_water;
4686 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4687 struct ixgbe_hw *hw =
4688 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4689 struct ixgbe_dcb_config *dcb_config =
4690 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4692 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4699 PMD_INIT_FUNC_TRACE();
4701 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4702 tc_num = map[pfc_conf->priority];
4703 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4704 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4706 * At least reserve one Ethernet frame for watermark
4707 * high_water/low_water in kilo bytes for ixgbe
4709 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4710 if ((pfc_conf->fc.high_water > max_high_water) ||
4711 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4712 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4713 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4717 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4718 hw->fc.pause_time = pfc_conf->fc.pause_time;
4719 hw->fc.send_xon = pfc_conf->fc.send_xon;
4720 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4721 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4723 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4725 /* Not negotiated is not an error case */
4726 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4729 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4734 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4735 struct rte_eth_rss_reta_entry64 *reta_conf,
4738 uint16_t i, sp_reta_size;
4741 uint16_t idx, shift;
4742 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4745 PMD_INIT_FUNC_TRACE();
4747 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4748 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4753 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4754 if (reta_size != sp_reta_size) {
4755 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4756 "(%d) doesn't match the number hardware can supported "
4757 "(%d)", reta_size, sp_reta_size);
4761 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4762 idx = i / RTE_RETA_GROUP_SIZE;
4763 shift = i % RTE_RETA_GROUP_SIZE;
4764 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4768 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4769 if (mask == IXGBE_4_BIT_MASK)
4772 r = IXGBE_READ_REG(hw, reta_reg);
4773 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4774 if (mask & (0x1 << j))
4775 reta |= reta_conf[idx].reta[shift + j] <<
4778 reta |= r & (IXGBE_8_BIT_MASK <<
4781 IXGBE_WRITE_REG(hw, reta_reg, reta);
4788 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4789 struct rte_eth_rss_reta_entry64 *reta_conf,
4792 uint16_t i, sp_reta_size;
4795 uint16_t idx, shift;
4796 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4799 PMD_INIT_FUNC_TRACE();
4800 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4801 if (reta_size != sp_reta_size) {
4802 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4803 "(%d) doesn't match the number hardware can supported "
4804 "(%d)", reta_size, sp_reta_size);
4808 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4809 idx = i / RTE_RETA_GROUP_SIZE;
4810 shift = i % RTE_RETA_GROUP_SIZE;
4811 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4816 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4817 reta = IXGBE_READ_REG(hw, reta_reg);
4818 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4819 if (mask & (0x1 << j))
4820 reta_conf[idx].reta[shift + j] =
4821 ((reta >> (CHAR_BIT * j)) &
4830 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4831 uint32_t index, uint32_t pool)
4833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4834 uint32_t enable_addr = 1;
4836 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4841 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4845 ixgbe_clear_rar(hw, index);
4849 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4851 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4853 ixgbe_remove_rar(dev, 0);
4854 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4860 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4862 if (strcmp(dev->device->driver->name, drv->driver.name))
4869 is_ixgbe_supported(struct rte_eth_dev *dev)
4871 return is_device_supported(dev, &rte_ixgbe_pmd);
4875 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4879 struct ixgbe_hw *hw;
4880 struct rte_eth_dev_info dev_info;
4881 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4882 struct rte_eth_dev_data *dev_data = dev->data;
4884 ixgbe_dev_info_get(dev, &dev_info);
4886 /* check that mtu is within the allowed range */
4887 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4890 /* If device is started, refuse mtu that requires the support of
4891 * scattered packets when this feature has not been enabled before.
4893 if (dev_data->dev_started && !dev_data->scattered_rx &&
4894 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4895 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4896 PMD_INIT_LOG(ERR, "Stop port first.");
4900 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4901 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4903 /* switch to jumbo mode if needed */
4904 if (frame_size > ETHER_MAX_LEN) {
4905 dev->data->dev_conf.rxmode.offloads |=
4906 DEV_RX_OFFLOAD_JUMBO_FRAME;
4907 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4909 dev->data->dev_conf.rxmode.offloads &=
4910 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4911 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4913 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4915 /* update max frame size */
4916 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4918 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4919 maxfrs &= 0x0000FFFF;
4920 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4921 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4927 * Virtual Function operations
4930 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4932 struct ixgbe_interrupt *intr =
4933 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4934 struct ixgbe_hw *hw =
4935 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4937 PMD_INIT_FUNC_TRACE();
4939 /* Clear interrupt mask to stop from interrupts being generated */
4940 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4942 IXGBE_WRITE_FLUSH(hw);
4944 /* Clear mask value. */
4949 ixgbevf_intr_enable(struct rte_eth_dev *dev)
4951 struct ixgbe_interrupt *intr =
4952 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4953 struct ixgbe_hw *hw =
4954 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4956 PMD_INIT_FUNC_TRACE();
4958 /* VF enable interrupt autoclean */
4959 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4960 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4961 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4963 IXGBE_WRITE_FLUSH(hw);
4965 /* Save IXGBE_VTEIMS value to mask. */
4966 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
4970 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4972 struct rte_eth_conf *conf = &dev->data->dev_conf;
4973 struct ixgbe_adapter *adapter =
4974 (struct ixgbe_adapter *)dev->data->dev_private;
4975 struct rte_eth_dev_info dev_info;
4976 uint64_t rx_offloads;
4977 uint64_t tx_offloads;
4979 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4980 dev->data->port_id);
4982 ixgbevf_dev_info_get(dev, &dev_info);
4983 rx_offloads = dev->data->dev_conf.rxmode.offloads;
4984 if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4985 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4986 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4987 rx_offloads, dev_info.rx_offload_capa);
4990 tx_offloads = dev->data->dev_conf.txmode.offloads;
4991 if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4992 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4993 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4994 tx_offloads, dev_info.tx_offload_capa);
4999 * VF has no ability to enable/disable HW CRC
5000 * Keep the persistent behavior the same as Host PF
5002 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5003 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
5004 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5005 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
5008 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
5009 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5010 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
5015 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5016 * allocation or vector Rx preconditions we will reset it.
5018 adapter->rx_bulk_alloc_allowed = true;
5019 adapter->rx_vec_allowed = true;
5025 ixgbevf_dev_start(struct rte_eth_dev *dev)
5027 struct ixgbe_hw *hw =
5028 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029 uint32_t intr_vector = 0;
5030 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5031 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5035 PMD_INIT_FUNC_TRACE();
5037 err = hw->mac.ops.reset_hw(hw);
5039 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5042 hw->mac.get_link_status = true;
5044 /* negotiate mailbox API version to use with the PF. */
5045 ixgbevf_negotiate_api(hw);
5047 ixgbevf_dev_tx_init(dev);
5049 /* This can fail when allocating mbufs for descriptor rings */
5050 err = ixgbevf_dev_rx_init(dev);
5052 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5053 ixgbe_dev_clear_queues(dev);
5058 ixgbevf_set_vfta_all(dev, 1);
5061 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5062 ETH_VLAN_EXTEND_MASK;
5063 err = ixgbevf_vlan_offload_set(dev, mask);
5065 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5066 ixgbe_dev_clear_queues(dev);
5070 ixgbevf_dev_rxtx_start(dev);
5072 ixgbevf_dev_link_update(dev, 0);
5074 /* check and configure queue intr-vector mapping */
5075 if (rte_intr_cap_multiple(intr_handle) &&
5076 dev->data->dev_conf.intr_conf.rxq) {
5077 /* According to datasheet, only vector 0/1/2 can be used,
5078 * now only one vector is used for Rx queue
5081 if (rte_intr_efd_enable(intr_handle, intr_vector))
5085 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5086 intr_handle->intr_vec =
5087 rte_zmalloc("intr_vec",
5088 dev->data->nb_rx_queues * sizeof(int), 0);
5089 if (intr_handle->intr_vec == NULL) {
5090 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5091 " intr_vec", dev->data->nb_rx_queues);
5095 ixgbevf_configure_msix(dev);
5097 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5098 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5099 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5100 * is not cleared, it will fail when following rte_intr_enable( ) tries
5101 * to map Rx queue interrupt to other VFIO vectors.
5102 * So clear uio/vfio intr/evevnfd first to avoid failure.
5104 rte_intr_disable(intr_handle);
5106 rte_intr_enable(intr_handle);
5108 /* Re-enable interrupt for VF */
5109 ixgbevf_intr_enable(dev);
5115 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5117 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5118 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5119 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5121 PMD_INIT_FUNC_TRACE();
5123 ixgbevf_intr_disable(dev);
5125 hw->adapter_stopped = 1;
5126 ixgbe_stop_adapter(hw);
5129 * Clear what we set, but we still keep shadow_vfta to
5130 * restore after device starts
5132 ixgbevf_set_vfta_all(dev, 0);
5134 /* Clear stored conf */
5135 dev->data->scattered_rx = 0;
5137 ixgbe_dev_clear_queues(dev);
5139 /* Clean datapath event and queue/vec mapping */
5140 rte_intr_efd_disable(intr_handle);
5141 if (intr_handle->intr_vec != NULL) {
5142 rte_free(intr_handle->intr_vec);
5143 intr_handle->intr_vec = NULL;
5148 ixgbevf_dev_close(struct rte_eth_dev *dev)
5150 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5152 PMD_INIT_FUNC_TRACE();
5156 ixgbevf_dev_stop(dev);
5158 ixgbe_dev_free_queues(dev);
5161 * Remove the VF MAC address ro ensure
5162 * that the VF traffic goes to the PF
5163 * after stop, close and detach of the VF
5165 ixgbevf_remove_mac_addr(dev, 0);
5172 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5176 ret = eth_ixgbevf_dev_uninit(dev);
5180 ret = eth_ixgbevf_dev_init(dev);
5185 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5187 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5188 struct ixgbe_vfta *shadow_vfta =
5189 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5190 int i = 0, j = 0, vfta = 0, mask = 1;
5192 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5193 vfta = shadow_vfta->vfta[i];
5196 for (j = 0; j < 32; j++) {
5198 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5208 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5210 struct ixgbe_hw *hw =
5211 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5212 struct ixgbe_vfta *shadow_vfta =
5213 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5214 uint32_t vid_idx = 0;
5215 uint32_t vid_bit = 0;
5218 PMD_INIT_FUNC_TRACE();
5220 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5221 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5223 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5226 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5227 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5229 /* Save what we set and retore it after device reset */
5231 shadow_vfta->vfta[vid_idx] |= vid_bit;
5233 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5239 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5241 struct ixgbe_hw *hw =
5242 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245 PMD_INIT_FUNC_TRACE();
5247 if (queue >= hw->mac.max_rx_queues)
5250 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5252 ctrl |= IXGBE_RXDCTL_VME;
5254 ctrl &= ~IXGBE_RXDCTL_VME;
5255 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5257 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5261 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5263 struct ixgbe_rx_queue *rxq;
5267 /* VF function only support hw strip feature, others are not support */
5268 if (mask & ETH_VLAN_STRIP_MASK) {
5269 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5270 rxq = dev->data->rx_queues[i];
5271 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5272 ixgbevf_vlan_strip_queue_set(dev, i, on);
5280 ixgbe_vt_check(struct ixgbe_hw *hw)
5284 /* if Virtualization Technology is enabled */
5285 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5286 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5287 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5295 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5297 uint32_t vector = 0;
5299 switch (hw->mac.mc_filter_type) {
5300 case 0: /* use bits [47:36] of the address */
5301 vector = ((uc_addr->addr_bytes[4] >> 4) |
5302 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5304 case 1: /* use bits [46:35] of the address */
5305 vector = ((uc_addr->addr_bytes[4] >> 3) |
5306 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5308 case 2: /* use bits [45:34] of the address */
5309 vector = ((uc_addr->addr_bytes[4] >> 2) |
5310 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5312 case 3: /* use bits [43:32] of the address */
5313 vector = ((uc_addr->addr_bytes[4]) |
5314 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5316 default: /* Invalid mc_filter_type */
5320 /* vector can only be 12-bits or boundary will be exceeded */
5326 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5334 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5335 const uint32_t ixgbe_uta_bit_shift = 5;
5336 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5337 const uint32_t bit1 = 0x1;
5339 struct ixgbe_hw *hw =
5340 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341 struct ixgbe_uta_info *uta_info =
5342 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5344 /* The UTA table only exists on 82599 hardware and newer */
5345 if (hw->mac.type < ixgbe_mac_82599EB)
5348 vector = ixgbe_uta_vector(hw, mac_addr);
5349 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5350 uta_shift = vector & ixgbe_uta_bit_mask;
5352 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5356 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5358 uta_info->uta_in_use++;
5359 reg_val |= (bit1 << uta_shift);
5360 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5362 uta_info->uta_in_use--;
5363 reg_val &= ~(bit1 << uta_shift);
5364 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5367 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5369 if (uta_info->uta_in_use > 0)
5370 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5371 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5373 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5379 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5382 struct ixgbe_hw *hw =
5383 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5384 struct ixgbe_uta_info *uta_info =
5385 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5387 /* The UTA table only exists on 82599 hardware and newer */
5388 if (hw->mac.type < ixgbe_mac_82599EB)
5392 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5393 uta_info->uta_shadow[i] = ~0;
5394 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5397 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5398 uta_info->uta_shadow[i] = 0;
5399 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5407 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5409 uint32_t new_val = orig_val;
5411 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5412 new_val |= IXGBE_VMOLR_AUPE;
5413 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5414 new_val |= IXGBE_VMOLR_ROMPE;
5415 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5416 new_val |= IXGBE_VMOLR_ROPE;
5417 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5418 new_val |= IXGBE_VMOLR_BAM;
5419 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5420 new_val |= IXGBE_VMOLR_MPE;
5425 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5426 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5427 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5428 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5429 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5430 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5431 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5434 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5435 struct rte_eth_mirror_conf *mirror_conf,
5436 uint8_t rule_id, uint8_t on)
5438 uint32_t mr_ctl, vlvf;
5439 uint32_t mp_lsb = 0;
5440 uint32_t mv_msb = 0;
5441 uint32_t mv_lsb = 0;
5442 uint32_t mp_msb = 0;
5445 uint64_t vlan_mask = 0;
5447 const uint8_t pool_mask_offset = 32;
5448 const uint8_t vlan_mask_offset = 32;
5449 const uint8_t dst_pool_offset = 8;
5450 const uint8_t rule_mr_offset = 4;
5451 const uint8_t mirror_rule_mask = 0x0F;
5453 struct ixgbe_mirror_info *mr_info =
5454 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5455 struct ixgbe_hw *hw =
5456 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5457 uint8_t mirror_type = 0;
5459 if (ixgbe_vt_check(hw) < 0)
5462 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5465 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5466 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5467 mirror_conf->rule_type);
5471 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5472 mirror_type |= IXGBE_MRCTL_VLME;
5473 /* Check if vlan id is valid and find conresponding VLAN ID
5476 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5477 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5478 /* search vlan id related pool vlan filter
5481 reg_index = ixgbe_find_vlvf_slot(
5483 mirror_conf->vlan.vlan_id[i],
5487 vlvf = IXGBE_READ_REG(hw,
5488 IXGBE_VLVF(reg_index));
5489 if ((vlvf & IXGBE_VLVF_VIEN) &&
5490 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5491 mirror_conf->vlan.vlan_id[i]))
5492 vlan_mask |= (1ULL << reg_index);
5499 mv_lsb = vlan_mask & 0xFFFFFFFF;
5500 mv_msb = vlan_mask >> vlan_mask_offset;
5502 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5503 mirror_conf->vlan.vlan_mask;
5504 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5505 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5506 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5507 mirror_conf->vlan.vlan_id[i];
5512 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5513 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5514 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5519 * if enable pool mirror, write related pool mask register,if disable
5520 * pool mirror, clear PFMRVM register
5522 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5523 mirror_type |= IXGBE_MRCTL_VPME;
5525 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5526 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5527 mr_info->mr_conf[rule_id].pool_mask =
5528 mirror_conf->pool_mask;
5533 mr_info->mr_conf[rule_id].pool_mask = 0;
5536 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5537 mirror_type |= IXGBE_MRCTL_UPME;
5538 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5539 mirror_type |= IXGBE_MRCTL_DPME;
5541 /* read mirror control register and recalculate it */
5542 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5545 mr_ctl |= mirror_type;
5546 mr_ctl &= mirror_rule_mask;
5547 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5549 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5552 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5553 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5555 /* write mirrror control register */
5556 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5558 /* write pool mirrror control register */
5559 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5560 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5561 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5564 /* write VLAN mirrror control register */
5565 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5566 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5567 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5575 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5578 uint32_t lsb_val = 0;
5579 uint32_t msb_val = 0;
5580 const uint8_t rule_mr_offset = 4;
5582 struct ixgbe_hw *hw =
5583 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5584 struct ixgbe_mirror_info *mr_info =
5585 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5587 if (ixgbe_vt_check(hw) < 0)
5590 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5593 memset(&mr_info->mr_conf[rule_id], 0,
5594 sizeof(struct rte_eth_mirror_conf));
5596 /* clear PFVMCTL register */
5597 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5599 /* clear pool mask register */
5600 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5601 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5603 /* clear vlan mask register */
5604 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5605 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5611 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5613 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5614 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5615 struct ixgbe_interrupt *intr =
5616 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5617 struct ixgbe_hw *hw =
5618 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5619 uint32_t vec = IXGBE_MISC_VEC_ID;
5621 if (rte_intr_allow_others(intr_handle))
5622 vec = IXGBE_RX_VEC_START;
5623 intr->mask |= (1 << vec);
5624 RTE_SET_USED(queue_id);
5625 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5627 rte_intr_enable(intr_handle);
5633 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5635 struct ixgbe_interrupt *intr =
5636 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5637 struct ixgbe_hw *hw =
5638 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5639 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5640 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5641 uint32_t vec = IXGBE_MISC_VEC_ID;
5643 if (rte_intr_allow_others(intr_handle))
5644 vec = IXGBE_RX_VEC_START;
5645 intr->mask &= ~(1 << vec);
5646 RTE_SET_USED(queue_id);
5647 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5653 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5655 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5656 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5658 struct ixgbe_hw *hw =
5659 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5660 struct ixgbe_interrupt *intr =
5661 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5663 if (queue_id < 16) {
5664 ixgbe_disable_intr(hw);
5665 intr->mask |= (1 << queue_id);
5666 ixgbe_enable_intr(dev);
5667 } else if (queue_id < 32) {
5668 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5669 mask &= (1 << queue_id);
5670 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5671 } else if (queue_id < 64) {
5672 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5673 mask &= (1 << (queue_id - 32));
5674 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5676 rte_intr_enable(intr_handle);
5682 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5685 struct ixgbe_hw *hw =
5686 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5687 struct ixgbe_interrupt *intr =
5688 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5690 if (queue_id < 16) {
5691 ixgbe_disable_intr(hw);
5692 intr->mask &= ~(1 << queue_id);
5693 ixgbe_enable_intr(dev);
5694 } else if (queue_id < 32) {
5695 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5696 mask &= ~(1 << queue_id);
5697 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5698 } else if (queue_id < 64) {
5699 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5700 mask &= ~(1 << (queue_id - 32));
5701 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5708 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5709 uint8_t queue, uint8_t msix_vector)
5713 if (direction == -1) {
5715 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5716 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5719 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5721 /* rx or tx cause */
5722 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5723 idx = ((16 * (queue & 1)) + (8 * direction));
5724 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5725 tmp &= ~(0xFF << idx);
5726 tmp |= (msix_vector << idx);
5727 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5732 * set the IVAR registers, mapping interrupt causes to vectors
5734 * pointer to ixgbe_hw struct
5736 * 0 for Rx, 1 for Tx, -1 for other causes
5738 * queue to map the corresponding interrupt to
5740 * the vector to map to the corresponding queue
5743 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5744 uint8_t queue, uint8_t msix_vector)
5748 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5749 if (hw->mac.type == ixgbe_mac_82598EB) {
5750 if (direction == -1)
5752 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5753 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5754 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5755 tmp |= (msix_vector << (8 * (queue & 0x3)));
5756 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5757 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5758 (hw->mac.type == ixgbe_mac_X540) ||
5759 (hw->mac.type == ixgbe_mac_X550)) {
5760 if (direction == -1) {
5762 idx = ((queue & 1) * 8);
5763 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5764 tmp &= ~(0xFF << idx);
5765 tmp |= (msix_vector << idx);
5766 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5768 /* rx or tx causes */
5769 idx = ((16 * (queue & 1)) + (8 * direction));
5770 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5771 tmp &= ~(0xFF << idx);
5772 tmp |= (msix_vector << idx);
5773 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5779 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5781 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5782 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5783 struct ixgbe_hw *hw =
5784 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5786 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5787 uint32_t base = IXGBE_MISC_VEC_ID;
5789 /* Configure VF other cause ivar */
5790 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5792 /* won't configure msix register if no mapping is done
5793 * between intr vector and event fd.
5795 if (!rte_intr_dp_is_en(intr_handle))
5798 if (rte_intr_allow_others(intr_handle)) {
5799 base = IXGBE_RX_VEC_START;
5800 vector_idx = IXGBE_RX_VEC_START;
5803 /* Configure all RX queues of VF */
5804 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5805 /* Force all queue use vector 0,
5806 * as IXGBE_VF_MAXMSIVECOTR = 1
5808 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5809 intr_handle->intr_vec[q_idx] = vector_idx;
5810 if (vector_idx < base + intr_handle->nb_efd - 1)
5814 /* As RX queue setting above show, all queues use the vector 0.
5815 * Set only the ITR value of IXGBE_MISC_VEC_ID.
5817 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5818 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5819 | IXGBE_EITR_CNT_WDIS);
5823 * Sets up the hardware to properly generate MSI-X interrupts
5825 * board private structure
5828 ixgbe_configure_msix(struct rte_eth_dev *dev)
5830 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5831 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5832 struct ixgbe_hw *hw =
5833 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5834 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5835 uint32_t vec = IXGBE_MISC_VEC_ID;
5839 /* won't configure msix register if no mapping is done
5840 * between intr vector and event fd
5842 if (!rte_intr_dp_is_en(intr_handle))
5845 if (rte_intr_allow_others(intr_handle))
5846 vec = base = IXGBE_RX_VEC_START;
5848 /* setup GPIE for MSI-x mode */
5849 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5850 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5851 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5852 /* auto clearing and auto setting corresponding bits in EIMS
5853 * when MSI-X interrupt is triggered
5855 if (hw->mac.type == ixgbe_mac_82598EB) {
5856 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5858 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5859 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5861 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5863 /* Populate the IVAR table and set the ITR values to the
5864 * corresponding register.
5866 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5868 /* by default, 1:1 mapping */
5869 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5870 intr_handle->intr_vec[queue_id] = vec;
5871 if (vec < base + intr_handle->nb_efd - 1)
5875 switch (hw->mac.type) {
5876 case ixgbe_mac_82598EB:
5877 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5880 case ixgbe_mac_82599EB:
5881 case ixgbe_mac_X540:
5882 case ixgbe_mac_X550:
5883 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5888 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5889 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5890 | IXGBE_EITR_CNT_WDIS);
5892 /* set up to autoclear timer, and the vectors */
5893 mask = IXGBE_EIMS_ENABLE_MASK;
5894 mask &= ~(IXGBE_EIMS_OTHER |
5895 IXGBE_EIMS_MAILBOX |
5898 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5902 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5903 uint16_t queue_idx, uint16_t tx_rate)
5905 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906 struct rte_eth_rxmode *rxmode;
5907 uint32_t rf_dec, rf_int;
5909 uint16_t link_speed = dev->data->dev_link.link_speed;
5911 if (queue_idx >= hw->mac.max_tx_queues)
5915 /* Calculate the rate factor values to set */
5916 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5917 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5918 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5920 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5921 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5922 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5923 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5928 rxmode = &dev->data->dev_conf.rxmode;
5930 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5931 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5934 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5935 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5936 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5937 IXGBE_MMW_SIZE_JUMBO_FRAME);
5939 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5940 IXGBE_MMW_SIZE_DEFAULT);
5942 /* Set RTTBCNRC of queue X */
5943 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5944 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5945 IXGBE_WRITE_FLUSH(hw);
5951 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5952 __attribute__((unused)) uint32_t index,
5953 __attribute__((unused)) uint32_t pool)
5955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5960 * operation. Trap this case to avoid exhausting the [very limited]
5961 * set of PF resources used to store VF MAC addresses.
5963 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5965 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5967 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5968 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5969 mac_addr->addr_bytes[0],
5970 mac_addr->addr_bytes[1],
5971 mac_addr->addr_bytes[2],
5972 mac_addr->addr_bytes[3],
5973 mac_addr->addr_bytes[4],
5974 mac_addr->addr_bytes[5],
5980 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5982 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5983 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5984 struct ether_addr *mac_addr;
5989 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5990 * not support the deletion of a given MAC address.
5991 * Instead, it imposes to delete all MAC addresses, then to add again
5992 * all MAC addresses with the exception of the one to be deleted.
5994 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5997 * Add again all MAC addresses, with the exception of the deleted one
5998 * and of the permanent MAC address.
6000 for (i = 0, mac_addr = dev->data->mac_addrs;
6001 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6002 /* Skip the deleted MAC address */
6005 /* Skip NULL MAC addresses */
6006 if (is_zero_ether_addr(mac_addr))
6008 /* Skip the permanent MAC address */
6009 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6011 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6014 "Adding again MAC address "
6015 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6017 mac_addr->addr_bytes[0],
6018 mac_addr->addr_bytes[1],
6019 mac_addr->addr_bytes[2],
6020 mac_addr->addr_bytes[3],
6021 mac_addr->addr_bytes[4],
6022 mac_addr->addr_bytes[5],
6028 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6032 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6038 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6039 struct rte_eth_syn_filter *filter,
6042 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6043 struct ixgbe_filter_info *filter_info =
6044 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6048 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6051 syn_info = filter_info->syn_info;
6054 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6056 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6057 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6059 if (filter->hig_pri)
6060 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6062 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6064 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6065 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6067 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6070 filter_info->syn_info = synqf;
6071 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6072 IXGBE_WRITE_FLUSH(hw);
6077 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6078 struct rte_eth_syn_filter *filter)
6080 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6081 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6083 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6084 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6085 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6092 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6093 enum rte_filter_op filter_op,
6096 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6099 MAC_TYPE_FILTER_SUP(hw->mac.type);
6101 if (filter_op == RTE_ETH_FILTER_NOP)
6105 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6110 switch (filter_op) {
6111 case RTE_ETH_FILTER_ADD:
6112 ret = ixgbe_syn_filter_set(dev,
6113 (struct rte_eth_syn_filter *)arg,
6116 case RTE_ETH_FILTER_DELETE:
6117 ret = ixgbe_syn_filter_set(dev,
6118 (struct rte_eth_syn_filter *)arg,
6121 case RTE_ETH_FILTER_GET:
6122 ret = ixgbe_syn_filter_get(dev,
6123 (struct rte_eth_syn_filter *)arg);
6126 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6135 static inline enum ixgbe_5tuple_protocol
6136 convert_protocol_type(uint8_t protocol_value)
6138 if (protocol_value == IPPROTO_TCP)
6139 return IXGBE_FILTER_PROTOCOL_TCP;
6140 else if (protocol_value == IPPROTO_UDP)
6141 return IXGBE_FILTER_PROTOCOL_UDP;
6142 else if (protocol_value == IPPROTO_SCTP)
6143 return IXGBE_FILTER_PROTOCOL_SCTP;
6145 return IXGBE_FILTER_PROTOCOL_NONE;
6148 /* inject a 5-tuple filter to HW */
6150 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6151 struct ixgbe_5tuple_filter *filter)
6153 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155 uint32_t ftqf, sdpqf;
6156 uint32_t l34timir = 0;
6157 uint8_t mask = 0xff;
6161 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6162 IXGBE_SDPQF_DSTPORT_SHIFT);
6163 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6165 ftqf = (uint32_t)(filter->filter_info.proto &
6166 IXGBE_FTQF_PROTOCOL_MASK);
6167 ftqf |= (uint32_t)((filter->filter_info.priority &
6168 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6169 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6170 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6171 if (filter->filter_info.dst_ip_mask == 0)
6172 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6173 if (filter->filter_info.src_port_mask == 0)
6174 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6175 if (filter->filter_info.dst_port_mask == 0)
6176 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6177 if (filter->filter_info.proto_mask == 0)
6178 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6179 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6180 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6181 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6183 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6184 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6185 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6186 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6188 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6189 l34timir |= (uint32_t)(filter->queue <<
6190 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6191 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6195 * add a 5tuple filter
6198 * dev: Pointer to struct rte_eth_dev.
6199 * index: the index the filter allocates.
6200 * filter: ponter to the filter that will be added.
6201 * rx_queue: the queue id the filter assigned to.
6204 * - On success, zero.
6205 * - On failure, a negative value.
6208 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6209 struct ixgbe_5tuple_filter *filter)
6211 struct ixgbe_filter_info *filter_info =
6212 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6216 * look for an unused 5tuple filter index,
6217 * and insert the filter to list.
6219 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6220 idx = i / (sizeof(uint32_t) * NBBY);
6221 shift = i % (sizeof(uint32_t) * NBBY);
6222 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6223 filter_info->fivetuple_mask[idx] |= 1 << shift;
6225 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6231 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6232 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6236 ixgbe_inject_5tuple_filter(dev, filter);
6242 * remove a 5tuple filter
6245 * dev: Pointer to struct rte_eth_dev.
6246 * filter: the pointer of the filter will be removed.
6249 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6250 struct ixgbe_5tuple_filter *filter)
6252 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6253 struct ixgbe_filter_info *filter_info =
6254 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6255 uint16_t index = filter->index;
6257 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6258 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6259 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6262 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6263 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6264 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6265 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6266 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6270 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6272 struct ixgbe_hw *hw;
6273 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6274 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6276 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6278 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6281 /* refuse mtu that requires the support of scattered packets when this
6282 * feature has not been enabled before.
6284 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6285 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6286 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6290 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6291 * request of the version 2.0 of the mailbox API.
6292 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6293 * of the mailbox API.
6294 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6295 * prior to 3.11.33 which contains the following change:
6296 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6298 ixgbevf_rlpml_set_vf(hw, max_frame);
6300 /* update max frame size */
6301 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6305 static inline struct ixgbe_5tuple_filter *
6306 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6307 struct ixgbe_5tuple_filter_info *key)
6309 struct ixgbe_5tuple_filter *it;
6311 TAILQ_FOREACH(it, filter_list, entries) {
6312 if (memcmp(key, &it->filter_info,
6313 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6320 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6322 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6323 struct ixgbe_5tuple_filter_info *filter_info)
6325 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6326 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6327 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6330 switch (filter->dst_ip_mask) {
6332 filter_info->dst_ip_mask = 0;
6333 filter_info->dst_ip = filter->dst_ip;
6336 filter_info->dst_ip_mask = 1;
6339 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6343 switch (filter->src_ip_mask) {
6345 filter_info->src_ip_mask = 0;
6346 filter_info->src_ip = filter->src_ip;
6349 filter_info->src_ip_mask = 1;
6352 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6356 switch (filter->dst_port_mask) {
6358 filter_info->dst_port_mask = 0;
6359 filter_info->dst_port = filter->dst_port;
6362 filter_info->dst_port_mask = 1;
6365 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6369 switch (filter->src_port_mask) {
6371 filter_info->src_port_mask = 0;
6372 filter_info->src_port = filter->src_port;
6375 filter_info->src_port_mask = 1;
6378 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6382 switch (filter->proto_mask) {
6384 filter_info->proto_mask = 0;
6385 filter_info->proto =
6386 convert_protocol_type(filter->proto);
6389 filter_info->proto_mask = 1;
6392 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6396 filter_info->priority = (uint8_t)filter->priority;
6401 * add or delete a ntuple filter
6404 * dev: Pointer to struct rte_eth_dev.
6405 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6406 * add: if true, add filter, if false, remove filter
6409 * - On success, zero.
6410 * - On failure, a negative value.
6413 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6414 struct rte_eth_ntuple_filter *ntuple_filter,
6417 struct ixgbe_filter_info *filter_info =
6418 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6419 struct ixgbe_5tuple_filter_info filter_5tuple;
6420 struct ixgbe_5tuple_filter *filter;
6423 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6424 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6428 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6429 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6433 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6435 if (filter != NULL && add) {
6436 PMD_DRV_LOG(ERR, "filter exists.");
6439 if (filter == NULL && !add) {
6440 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6445 filter = rte_zmalloc("ixgbe_5tuple_filter",
6446 sizeof(struct ixgbe_5tuple_filter), 0);
6449 rte_memcpy(&filter->filter_info,
6451 sizeof(struct ixgbe_5tuple_filter_info));
6452 filter->queue = ntuple_filter->queue;
6453 ret = ixgbe_add_5tuple_filter(dev, filter);
6459 ixgbe_remove_5tuple_filter(dev, filter);
6465 * get a ntuple filter
6468 * dev: Pointer to struct rte_eth_dev.
6469 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6472 * - On success, zero.
6473 * - On failure, a negative value.
6476 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6477 struct rte_eth_ntuple_filter *ntuple_filter)
6479 struct ixgbe_filter_info *filter_info =
6480 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6481 struct ixgbe_5tuple_filter_info filter_5tuple;
6482 struct ixgbe_5tuple_filter *filter;
6485 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6486 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6490 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6491 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6495 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6497 if (filter == NULL) {
6498 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6501 ntuple_filter->queue = filter->queue;
6506 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6507 * @dev: pointer to rte_eth_dev structure
6508 * @filter_op:operation will be taken.
6509 * @arg: a pointer to specific structure corresponding to the filter_op
6512 * - On success, zero.
6513 * - On failure, a negative value.
6516 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6517 enum rte_filter_op filter_op,
6520 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6523 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6525 if (filter_op == RTE_ETH_FILTER_NOP)
6529 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6534 switch (filter_op) {
6535 case RTE_ETH_FILTER_ADD:
6536 ret = ixgbe_add_del_ntuple_filter(dev,
6537 (struct rte_eth_ntuple_filter *)arg,
6540 case RTE_ETH_FILTER_DELETE:
6541 ret = ixgbe_add_del_ntuple_filter(dev,
6542 (struct rte_eth_ntuple_filter *)arg,
6545 case RTE_ETH_FILTER_GET:
6546 ret = ixgbe_get_ntuple_filter(dev,
6547 (struct rte_eth_ntuple_filter *)arg);
6550 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6558 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6559 struct rte_eth_ethertype_filter *filter,
6562 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6563 struct ixgbe_filter_info *filter_info =
6564 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6568 struct ixgbe_ethertype_filter ethertype_filter;
6570 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6573 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6574 filter->ether_type == ETHER_TYPE_IPv6) {
6575 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6576 " ethertype filter.", filter->ether_type);
6580 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6581 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6584 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6585 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6589 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6590 if (ret >= 0 && add) {
6591 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6592 filter->ether_type);
6595 if (ret < 0 && !add) {
6596 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6597 filter->ether_type);
6602 etqf = IXGBE_ETQF_FILTER_EN;
6603 etqf |= (uint32_t)filter->ether_type;
6604 etqs |= (uint32_t)((filter->queue <<
6605 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6606 IXGBE_ETQS_RX_QUEUE);
6607 etqs |= IXGBE_ETQS_QUEUE_EN;
6609 ethertype_filter.ethertype = filter->ether_type;
6610 ethertype_filter.etqf = etqf;
6611 ethertype_filter.etqs = etqs;
6612 ethertype_filter.conf = FALSE;
6613 ret = ixgbe_ethertype_filter_insert(filter_info,
6616 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6620 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6624 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6625 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6626 IXGBE_WRITE_FLUSH(hw);
6632 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6633 struct rte_eth_ethertype_filter *filter)
6635 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6636 struct ixgbe_filter_info *filter_info =
6637 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6638 uint32_t etqf, etqs;
6641 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6643 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6644 filter->ether_type);
6648 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6649 if (etqf & IXGBE_ETQF_FILTER_EN) {
6650 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6651 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6653 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6654 IXGBE_ETQS_RX_QUEUE_SHIFT;
6661 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6662 * @dev: pointer to rte_eth_dev structure
6663 * @filter_op:operation will be taken.
6664 * @arg: a pointer to specific structure corresponding to the filter_op
6667 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6668 enum rte_filter_op filter_op,
6671 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6674 MAC_TYPE_FILTER_SUP(hw->mac.type);
6676 if (filter_op == RTE_ETH_FILTER_NOP)
6680 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6685 switch (filter_op) {
6686 case RTE_ETH_FILTER_ADD:
6687 ret = ixgbe_add_del_ethertype_filter(dev,
6688 (struct rte_eth_ethertype_filter *)arg,
6691 case RTE_ETH_FILTER_DELETE:
6692 ret = ixgbe_add_del_ethertype_filter(dev,
6693 (struct rte_eth_ethertype_filter *)arg,
6696 case RTE_ETH_FILTER_GET:
6697 ret = ixgbe_get_ethertype_filter(dev,
6698 (struct rte_eth_ethertype_filter *)arg);
6701 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6709 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6710 enum rte_filter_type filter_type,
6711 enum rte_filter_op filter_op,
6716 switch (filter_type) {
6717 case RTE_ETH_FILTER_NTUPLE:
6718 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6720 case RTE_ETH_FILTER_ETHERTYPE:
6721 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6723 case RTE_ETH_FILTER_SYN:
6724 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6726 case RTE_ETH_FILTER_FDIR:
6727 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6729 case RTE_ETH_FILTER_L2_TUNNEL:
6730 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6732 case RTE_ETH_FILTER_GENERIC:
6733 if (filter_op != RTE_ETH_FILTER_GET)
6735 *(const void **)arg = &ixgbe_flow_ops;
6738 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6748 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6749 u8 **mc_addr_ptr, u32 *vmdq)
6754 mc_addr = *mc_addr_ptr;
6755 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6760 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6761 struct ether_addr *mc_addr_set,
6762 uint32_t nb_mc_addr)
6764 struct ixgbe_hw *hw;
6767 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6768 mc_addr_list = (u8 *)mc_addr_set;
6769 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6770 ixgbe_dev_addr_list_itr, TRUE);
6774 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6776 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6777 uint64_t systime_cycles;
6779 switch (hw->mac.type) {
6780 case ixgbe_mac_X550:
6781 case ixgbe_mac_X550EM_x:
6782 case ixgbe_mac_X550EM_a:
6783 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6784 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6785 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6789 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6790 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6794 return systime_cycles;
6798 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6800 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6801 uint64_t rx_tstamp_cycles;
6803 switch (hw->mac.type) {
6804 case ixgbe_mac_X550:
6805 case ixgbe_mac_X550EM_x:
6806 case ixgbe_mac_X550EM_a:
6807 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6808 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6809 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6813 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6814 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6815 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6819 return rx_tstamp_cycles;
6823 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6825 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6826 uint64_t tx_tstamp_cycles;
6828 switch (hw->mac.type) {
6829 case ixgbe_mac_X550:
6830 case ixgbe_mac_X550EM_x:
6831 case ixgbe_mac_X550EM_a:
6832 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6833 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6834 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6838 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6839 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6840 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6844 return tx_tstamp_cycles;
6848 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6850 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6851 struct ixgbe_adapter *adapter =
6852 (struct ixgbe_adapter *)dev->data->dev_private;
6853 struct rte_eth_link link;
6854 uint32_t incval = 0;
6857 /* Get current link speed. */
6858 ixgbe_dev_link_update(dev, 1);
6859 rte_eth_linkstatus_get(dev, &link);
6861 switch (link.link_speed) {
6862 case ETH_SPEED_NUM_100M:
6863 incval = IXGBE_INCVAL_100;
6864 shift = IXGBE_INCVAL_SHIFT_100;
6866 case ETH_SPEED_NUM_1G:
6867 incval = IXGBE_INCVAL_1GB;
6868 shift = IXGBE_INCVAL_SHIFT_1GB;
6870 case ETH_SPEED_NUM_10G:
6872 incval = IXGBE_INCVAL_10GB;
6873 shift = IXGBE_INCVAL_SHIFT_10GB;
6877 switch (hw->mac.type) {
6878 case ixgbe_mac_X550:
6879 case ixgbe_mac_X550EM_x:
6880 case ixgbe_mac_X550EM_a:
6881 /* Independent of link speed. */
6883 /* Cycles read will be interpreted as ns. */
6886 case ixgbe_mac_X540:
6887 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6889 case ixgbe_mac_82599EB:
6890 incval >>= IXGBE_INCVAL_SHIFT_82599;
6891 shift -= IXGBE_INCVAL_SHIFT_82599;
6892 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6893 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6896 /* Not supported. */
6900 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6901 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6902 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6904 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6905 adapter->systime_tc.cc_shift = shift;
6906 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6908 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6909 adapter->rx_tstamp_tc.cc_shift = shift;
6910 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6912 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6913 adapter->tx_tstamp_tc.cc_shift = shift;
6914 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6918 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6920 struct ixgbe_adapter *adapter =
6921 (struct ixgbe_adapter *)dev->data->dev_private;
6923 adapter->systime_tc.nsec += delta;
6924 adapter->rx_tstamp_tc.nsec += delta;
6925 adapter->tx_tstamp_tc.nsec += delta;
6931 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6934 struct ixgbe_adapter *adapter =
6935 (struct ixgbe_adapter *)dev->data->dev_private;
6937 ns = rte_timespec_to_ns(ts);
6938 /* Set the timecounters to a new value. */
6939 adapter->systime_tc.nsec = ns;
6940 adapter->rx_tstamp_tc.nsec = ns;
6941 adapter->tx_tstamp_tc.nsec = ns;
6947 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6949 uint64_t ns, systime_cycles;
6950 struct ixgbe_adapter *adapter =
6951 (struct ixgbe_adapter *)dev->data->dev_private;
6953 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6954 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6955 *ts = rte_ns_to_timespec(ns);
6961 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6963 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6967 /* Stop the timesync system time. */
6968 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6969 /* Reset the timesync system time value. */
6970 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6971 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6973 /* Enable system time for platforms where it isn't on by default. */
6974 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6975 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6976 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6978 ixgbe_start_timecounters(dev);
6980 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6981 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6983 IXGBE_ETQF_FILTER_EN |
6986 /* Enable timestamping of received PTP packets. */
6987 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6988 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6989 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6991 /* Enable timestamping of transmitted PTP packets. */
6992 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6993 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6994 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6996 IXGBE_WRITE_FLUSH(hw);
7002 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7004 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7007 /* Disable timestamping of transmitted PTP packets. */
7008 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7009 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7010 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7012 /* Disable timestamping of received PTP packets. */
7013 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7014 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7015 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7017 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7018 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7020 /* Stop incrementating the System Time registers. */
7021 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7027 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7028 struct timespec *timestamp,
7029 uint32_t flags __rte_unused)
7031 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7032 struct ixgbe_adapter *adapter =
7033 (struct ixgbe_adapter *)dev->data->dev_private;
7034 uint32_t tsync_rxctl;
7035 uint64_t rx_tstamp_cycles;
7038 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7039 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7042 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7043 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7044 *timestamp = rte_ns_to_timespec(ns);
7050 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7051 struct timespec *timestamp)
7053 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7054 struct ixgbe_adapter *adapter =
7055 (struct ixgbe_adapter *)dev->data->dev_private;
7056 uint32_t tsync_txctl;
7057 uint64_t tx_tstamp_cycles;
7060 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7061 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7064 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7065 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7066 *timestamp = rte_ns_to_timespec(ns);
7072 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7074 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7077 const struct reg_info *reg_group;
7078 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7079 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7081 while ((reg_group = reg_set[g_ind++]))
7082 count += ixgbe_regs_group_count(reg_group);
7088 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7092 const struct reg_info *reg_group;
7094 while ((reg_group = ixgbevf_regs[g_ind++]))
7095 count += ixgbe_regs_group_count(reg_group);
7101 ixgbe_get_regs(struct rte_eth_dev *dev,
7102 struct rte_dev_reg_info *regs)
7104 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7105 uint32_t *data = regs->data;
7108 const struct reg_info *reg_group;
7109 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7110 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7113 regs->length = ixgbe_get_reg_length(dev);
7114 regs->width = sizeof(uint32_t);
7118 /* Support only full register dump */
7119 if ((regs->length == 0) ||
7120 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7121 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7123 while ((reg_group = reg_set[g_ind++]))
7124 count += ixgbe_read_regs_group(dev, &data[count],
7133 ixgbevf_get_regs(struct rte_eth_dev *dev,
7134 struct rte_dev_reg_info *regs)
7136 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7137 uint32_t *data = regs->data;
7140 const struct reg_info *reg_group;
7143 regs->length = ixgbevf_get_reg_length(dev);
7144 regs->width = sizeof(uint32_t);
7148 /* Support only full register dump */
7149 if ((regs->length == 0) ||
7150 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7151 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7153 while ((reg_group = ixgbevf_regs[g_ind++]))
7154 count += ixgbe_read_regs_group(dev, &data[count],
7163 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7165 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7167 /* Return unit is byte count */
7168 return hw->eeprom.word_size * 2;
7172 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7173 struct rte_dev_eeprom_info *in_eeprom)
7175 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7176 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7177 uint16_t *data = in_eeprom->data;
7180 first = in_eeprom->offset >> 1;
7181 length = in_eeprom->length >> 1;
7182 if ((first > hw->eeprom.word_size) ||
7183 ((first + length) > hw->eeprom.word_size))
7186 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7188 return eeprom->ops.read_buffer(hw, first, length, data);
7192 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7193 struct rte_dev_eeprom_info *in_eeprom)
7195 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7196 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7197 uint16_t *data = in_eeprom->data;
7200 first = in_eeprom->offset >> 1;
7201 length = in_eeprom->length >> 1;
7202 if ((first > hw->eeprom.word_size) ||
7203 ((first + length) > hw->eeprom.word_size))
7206 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7208 return eeprom->ops.write_buffer(hw, first, length, data);
7212 ixgbe_get_module_info(struct rte_eth_dev *dev,
7213 struct rte_eth_dev_module_info *modinfo)
7215 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7217 uint8_t sff8472_rev, addr_mode;
7218 bool page_swap = false;
7220 /* Check whether we support SFF-8472 or not */
7221 status = hw->phy.ops.read_i2c_eeprom(hw,
7222 IXGBE_SFF_SFF_8472_COMP,
7227 /* addressing mode is not supported */
7228 status = hw->phy.ops.read_i2c_eeprom(hw,
7229 IXGBE_SFF_SFF_8472_SWAP,
7234 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7236 "Address change required to access page 0xA2, "
7237 "but not supported. Please report the module "
7238 "type to the driver maintainers.");
7242 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7243 /* We have a SFP, but it does not support SFF-8472 */
7244 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7245 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7247 /* We have a SFP which supports a revision of SFF-8472. */
7248 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7249 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7256 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7257 struct rte_dev_eeprom_info *info)
7259 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7260 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7261 uint8_t databyte = 0xFF;
7262 uint8_t *data = info->data;
7265 if (info->length == 0)
7268 for (i = info->offset; i < info->offset + info->length; i++) {
7269 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7270 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7272 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7277 data[i - info->offset] = databyte;
7284 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7286 case ixgbe_mac_X550:
7287 case ixgbe_mac_X550EM_x:
7288 case ixgbe_mac_X550EM_a:
7289 return ETH_RSS_RETA_SIZE_512;
7290 case ixgbe_mac_X550_vf:
7291 case ixgbe_mac_X550EM_x_vf:
7292 case ixgbe_mac_X550EM_a_vf:
7293 return ETH_RSS_RETA_SIZE_64;
7295 return ETH_RSS_RETA_SIZE_128;
7300 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7302 case ixgbe_mac_X550:
7303 case ixgbe_mac_X550EM_x:
7304 case ixgbe_mac_X550EM_a:
7305 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7306 return IXGBE_RETA(reta_idx >> 2);
7308 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7309 case ixgbe_mac_X550_vf:
7310 case ixgbe_mac_X550EM_x_vf:
7311 case ixgbe_mac_X550EM_a_vf:
7312 return IXGBE_VFRETA(reta_idx >> 2);
7314 return IXGBE_RETA(reta_idx >> 2);
7319 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7321 case ixgbe_mac_X550_vf:
7322 case ixgbe_mac_X550EM_x_vf:
7323 case ixgbe_mac_X550EM_a_vf:
7324 return IXGBE_VFMRQC;
7331 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7333 case ixgbe_mac_X550_vf:
7334 case ixgbe_mac_X550EM_x_vf:
7335 case ixgbe_mac_X550EM_a_vf:
7336 return IXGBE_VFRSSRK(i);
7338 return IXGBE_RSSRK(i);
7343 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7345 case ixgbe_mac_82599_vf:
7346 case ixgbe_mac_X540_vf:
7354 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7355 struct rte_eth_dcb_info *dcb_info)
7357 struct ixgbe_dcb_config *dcb_config =
7358 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7359 struct ixgbe_dcb_tc_config *tc;
7360 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7364 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7365 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7367 dcb_info->nb_tcs = 1;
7369 tc_queue = &dcb_info->tc_queue;
7370 nb_tcs = dcb_info->nb_tcs;
7372 if (dcb_config->vt_mode) { /* vt is enabled*/
7373 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7374 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7375 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7376 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7377 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7378 for (j = 0; j < nb_tcs; j++) {
7379 tc_queue->tc_rxq[0][j].base = j;
7380 tc_queue->tc_rxq[0][j].nb_queue = 1;
7381 tc_queue->tc_txq[0][j].base = j;
7382 tc_queue->tc_txq[0][j].nb_queue = 1;
7385 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7386 for (j = 0; j < nb_tcs; j++) {
7387 tc_queue->tc_rxq[i][j].base =
7389 tc_queue->tc_rxq[i][j].nb_queue = 1;
7390 tc_queue->tc_txq[i][j].base =
7392 tc_queue->tc_txq[i][j].nb_queue = 1;
7396 } else { /* vt is disabled*/
7397 struct rte_eth_dcb_rx_conf *rx_conf =
7398 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7399 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7400 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7401 if (dcb_info->nb_tcs == ETH_4_TCS) {
7402 for (i = 0; i < dcb_info->nb_tcs; i++) {
7403 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7404 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7406 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7407 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7408 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7409 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7410 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7411 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7412 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7413 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7414 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7415 for (i = 0; i < dcb_info->nb_tcs; i++) {
7416 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7417 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7419 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7420 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7421 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7422 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7423 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7424 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7425 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7426 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7427 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7428 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7429 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7430 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7431 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7432 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7433 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7434 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7437 for (i = 0; i < dcb_info->nb_tcs; i++) {
7438 tc = &dcb_config->tc_config[i];
7439 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7444 /* Update e-tag ether type */
7446 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7447 uint16_t ether_type)
7449 uint32_t etag_etype;
7451 if (hw->mac.type != ixgbe_mac_X550 &&
7452 hw->mac.type != ixgbe_mac_X550EM_x &&
7453 hw->mac.type != ixgbe_mac_X550EM_a) {
7457 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7458 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7459 etag_etype |= ether_type;
7460 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7461 IXGBE_WRITE_FLUSH(hw);
7466 /* Config l2 tunnel ether type */
7468 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7469 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7472 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7473 struct ixgbe_l2_tn_info *l2_tn_info =
7474 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7476 if (l2_tunnel == NULL)
7479 switch (l2_tunnel->l2_tunnel_type) {
7480 case RTE_L2_TUNNEL_TYPE_E_TAG:
7481 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7482 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7485 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7493 /* Enable e-tag tunnel */
7495 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7497 uint32_t etag_etype;
7499 if (hw->mac.type != ixgbe_mac_X550 &&
7500 hw->mac.type != ixgbe_mac_X550EM_x &&
7501 hw->mac.type != ixgbe_mac_X550EM_a) {
7505 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7506 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7507 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7508 IXGBE_WRITE_FLUSH(hw);
7513 /* Enable l2 tunnel */
7515 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7516 enum rte_eth_tunnel_type l2_tunnel_type)
7519 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7520 struct ixgbe_l2_tn_info *l2_tn_info =
7521 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7523 switch (l2_tunnel_type) {
7524 case RTE_L2_TUNNEL_TYPE_E_TAG:
7525 l2_tn_info->e_tag_en = TRUE;
7526 ret = ixgbe_e_tag_enable(hw);
7529 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7537 /* Disable e-tag tunnel */
7539 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7541 uint32_t etag_etype;
7543 if (hw->mac.type != ixgbe_mac_X550 &&
7544 hw->mac.type != ixgbe_mac_X550EM_x &&
7545 hw->mac.type != ixgbe_mac_X550EM_a) {
7549 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7550 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7551 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7552 IXGBE_WRITE_FLUSH(hw);
7557 /* Disable l2 tunnel */
7559 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7560 enum rte_eth_tunnel_type l2_tunnel_type)
7563 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7564 struct ixgbe_l2_tn_info *l2_tn_info =
7565 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7567 switch (l2_tunnel_type) {
7568 case RTE_L2_TUNNEL_TYPE_E_TAG:
7569 l2_tn_info->e_tag_en = FALSE;
7570 ret = ixgbe_e_tag_disable(hw);
7573 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7582 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7583 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7587 uint32_t i, rar_entries;
7588 uint32_t rar_low, rar_high;
7590 if (hw->mac.type != ixgbe_mac_X550 &&
7591 hw->mac.type != ixgbe_mac_X550EM_x &&
7592 hw->mac.type != ixgbe_mac_X550EM_a) {
7596 rar_entries = ixgbe_get_num_rx_addrs(hw);
7598 for (i = 1; i < rar_entries; i++) {
7599 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7600 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7601 if ((rar_high & IXGBE_RAH_AV) &&
7602 (rar_high & IXGBE_RAH_ADTYPE) &&
7603 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7604 l2_tunnel->tunnel_id)) {
7605 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7606 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7608 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7618 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7619 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7622 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7623 uint32_t i, rar_entries;
7624 uint32_t rar_low, rar_high;
7626 if (hw->mac.type != ixgbe_mac_X550 &&
7627 hw->mac.type != ixgbe_mac_X550EM_x &&
7628 hw->mac.type != ixgbe_mac_X550EM_a) {
7632 /* One entry for one tunnel. Try to remove potential existing entry. */
7633 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7635 rar_entries = ixgbe_get_num_rx_addrs(hw);
7637 for (i = 1; i < rar_entries; i++) {
7638 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7639 if (rar_high & IXGBE_RAH_AV) {
7642 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7643 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7644 rar_low = l2_tunnel->tunnel_id;
7646 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7647 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7653 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7654 " Please remove a rule before adding a new one.");
7658 static inline struct ixgbe_l2_tn_filter *
7659 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7660 struct ixgbe_l2_tn_key *key)
7664 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7668 return l2_tn_info->hash_map[ret];
7672 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7673 struct ixgbe_l2_tn_filter *l2_tn_filter)
7677 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7678 &l2_tn_filter->key);
7682 "Failed to insert L2 tunnel filter"
7683 " to hash table %d!",
7688 l2_tn_info->hash_map[ret] = l2_tn_filter;
7690 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7696 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7697 struct ixgbe_l2_tn_key *key)
7700 struct ixgbe_l2_tn_filter *l2_tn_filter;
7702 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7706 "No such L2 tunnel filter to delete %d!",
7711 l2_tn_filter = l2_tn_info->hash_map[ret];
7712 l2_tn_info->hash_map[ret] = NULL;
7714 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7715 rte_free(l2_tn_filter);
7720 /* Add l2 tunnel filter */
7722 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7723 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7727 struct ixgbe_l2_tn_info *l2_tn_info =
7728 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7729 struct ixgbe_l2_tn_key key;
7730 struct ixgbe_l2_tn_filter *node;
7733 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7734 key.tn_id = l2_tunnel->tunnel_id;
7736 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7740 "The L2 tunnel filter already exists!");
7744 node = rte_zmalloc("ixgbe_l2_tn",
7745 sizeof(struct ixgbe_l2_tn_filter),
7750 rte_memcpy(&node->key,
7752 sizeof(struct ixgbe_l2_tn_key));
7753 node->pool = l2_tunnel->pool;
7754 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7761 switch (l2_tunnel->l2_tunnel_type) {
7762 case RTE_L2_TUNNEL_TYPE_E_TAG:
7763 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7766 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7771 if ((!restore) && (ret < 0))
7772 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7777 /* Delete l2 tunnel filter */
7779 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7780 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7783 struct ixgbe_l2_tn_info *l2_tn_info =
7784 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7785 struct ixgbe_l2_tn_key key;
7787 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7788 key.tn_id = l2_tunnel->tunnel_id;
7789 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7793 switch (l2_tunnel->l2_tunnel_type) {
7794 case RTE_L2_TUNNEL_TYPE_E_TAG:
7795 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7798 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7807 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7808 * @dev: pointer to rte_eth_dev structure
7809 * @filter_op:operation will be taken.
7810 * @arg: a pointer to specific structure corresponding to the filter_op
7813 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7814 enum rte_filter_op filter_op,
7819 if (filter_op == RTE_ETH_FILTER_NOP)
7823 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7828 switch (filter_op) {
7829 case RTE_ETH_FILTER_ADD:
7830 ret = ixgbe_dev_l2_tunnel_filter_add
7832 (struct rte_eth_l2_tunnel_conf *)arg,
7835 case RTE_ETH_FILTER_DELETE:
7836 ret = ixgbe_dev_l2_tunnel_filter_del
7838 (struct rte_eth_l2_tunnel_conf *)arg);
7841 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7849 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7853 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7855 if (hw->mac.type != ixgbe_mac_X550 &&
7856 hw->mac.type != ixgbe_mac_X550EM_x &&
7857 hw->mac.type != ixgbe_mac_X550EM_a) {
7861 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7862 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7864 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7865 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7870 /* Enable l2 tunnel forwarding */
7872 ixgbe_dev_l2_tunnel_forwarding_enable
7873 (struct rte_eth_dev *dev,
7874 enum rte_eth_tunnel_type l2_tunnel_type)
7876 struct ixgbe_l2_tn_info *l2_tn_info =
7877 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7880 switch (l2_tunnel_type) {
7881 case RTE_L2_TUNNEL_TYPE_E_TAG:
7882 l2_tn_info->e_tag_fwd_en = TRUE;
7883 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7886 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7894 /* Disable l2 tunnel forwarding */
7896 ixgbe_dev_l2_tunnel_forwarding_disable
7897 (struct rte_eth_dev *dev,
7898 enum rte_eth_tunnel_type l2_tunnel_type)
7900 struct ixgbe_l2_tn_info *l2_tn_info =
7901 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7904 switch (l2_tunnel_type) {
7905 case RTE_L2_TUNNEL_TYPE_E_TAG:
7906 l2_tn_info->e_tag_fwd_en = FALSE;
7907 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7910 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7919 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7920 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7923 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7925 uint32_t vmtir, vmvir;
7926 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7928 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7930 "VF id %u should be less than %u",
7936 if (hw->mac.type != ixgbe_mac_X550 &&
7937 hw->mac.type != ixgbe_mac_X550EM_x &&
7938 hw->mac.type != ixgbe_mac_X550EM_a) {
7943 vmtir = l2_tunnel->tunnel_id;
7947 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7949 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7950 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7952 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7953 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7958 /* Enable l2 tunnel tag insertion */
7960 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7961 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7965 switch (l2_tunnel->l2_tunnel_type) {
7966 case RTE_L2_TUNNEL_TYPE_E_TAG:
7967 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7970 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7978 /* Disable l2 tunnel tag insertion */
7980 ixgbe_dev_l2_tunnel_insertion_disable
7981 (struct rte_eth_dev *dev,
7982 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7986 switch (l2_tunnel->l2_tunnel_type) {
7987 case RTE_L2_TUNNEL_TYPE_E_TAG:
7988 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7991 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8000 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8007 if (hw->mac.type != ixgbe_mac_X550 &&
8008 hw->mac.type != ixgbe_mac_X550EM_x &&
8009 hw->mac.type != ixgbe_mac_X550EM_a) {
8013 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8015 qde |= IXGBE_QDE_STRIP_TAG;
8017 qde &= ~IXGBE_QDE_STRIP_TAG;
8018 qde &= ~IXGBE_QDE_READ;
8019 qde |= IXGBE_QDE_WRITE;
8020 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8025 /* Enable l2 tunnel tag stripping */
8027 ixgbe_dev_l2_tunnel_stripping_enable
8028 (struct rte_eth_dev *dev,
8029 enum rte_eth_tunnel_type l2_tunnel_type)
8033 switch (l2_tunnel_type) {
8034 case RTE_L2_TUNNEL_TYPE_E_TAG:
8035 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8038 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8046 /* Disable l2 tunnel tag stripping */
8048 ixgbe_dev_l2_tunnel_stripping_disable
8049 (struct rte_eth_dev *dev,
8050 enum rte_eth_tunnel_type l2_tunnel_type)
8054 switch (l2_tunnel_type) {
8055 case RTE_L2_TUNNEL_TYPE_E_TAG:
8056 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8059 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8067 /* Enable/disable l2 tunnel offload functions */
8069 ixgbe_dev_l2_tunnel_offload_set
8070 (struct rte_eth_dev *dev,
8071 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8077 if (l2_tunnel == NULL)
8081 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8083 ret = ixgbe_dev_l2_tunnel_enable(
8085 l2_tunnel->l2_tunnel_type);
8087 ret = ixgbe_dev_l2_tunnel_disable(
8089 l2_tunnel->l2_tunnel_type);
8092 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8094 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8098 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8103 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8105 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8107 l2_tunnel->l2_tunnel_type);
8109 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8111 l2_tunnel->l2_tunnel_type);
8114 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8116 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8118 l2_tunnel->l2_tunnel_type);
8120 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8122 l2_tunnel->l2_tunnel_type);
8129 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8132 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8133 IXGBE_WRITE_FLUSH(hw);
8138 /* There's only one register for VxLAN UDP port.
8139 * So, we cannot add several ports. Will update it.
8142 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8146 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8150 return ixgbe_update_vxlan_port(hw, port);
8153 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8154 * UDP port, it must have a value.
8155 * So, will reset it to the original value 0.
8158 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8163 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8165 if (cur_port != port) {
8166 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8170 return ixgbe_update_vxlan_port(hw, 0);
8173 /* Add UDP tunneling port */
8175 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8176 struct rte_eth_udp_tunnel *udp_tunnel)
8179 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8181 if (hw->mac.type != ixgbe_mac_X550 &&
8182 hw->mac.type != ixgbe_mac_X550EM_x &&
8183 hw->mac.type != ixgbe_mac_X550EM_a) {
8187 if (udp_tunnel == NULL)
8190 switch (udp_tunnel->prot_type) {
8191 case RTE_TUNNEL_TYPE_VXLAN:
8192 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8195 case RTE_TUNNEL_TYPE_GENEVE:
8196 case RTE_TUNNEL_TYPE_TEREDO:
8197 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8202 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8210 /* Remove UDP tunneling port */
8212 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8213 struct rte_eth_udp_tunnel *udp_tunnel)
8216 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8218 if (hw->mac.type != ixgbe_mac_X550 &&
8219 hw->mac.type != ixgbe_mac_X550EM_x &&
8220 hw->mac.type != ixgbe_mac_X550EM_a) {
8224 if (udp_tunnel == NULL)
8227 switch (udp_tunnel->prot_type) {
8228 case RTE_TUNNEL_TYPE_VXLAN:
8229 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8231 case RTE_TUNNEL_TYPE_GENEVE:
8232 case RTE_TUNNEL_TYPE_TEREDO:
8233 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8237 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8246 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8248 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8250 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8254 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8256 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8258 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8261 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8263 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8266 /* peek the message first */
8267 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8269 /* PF reset VF event */
8270 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8271 /* dummy mbx read to ack pf */
8272 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8274 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8280 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8283 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8284 struct ixgbe_interrupt *intr =
8285 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8286 ixgbevf_intr_disable(dev);
8288 /* read-on-clear nic registers here */
8289 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8292 /* only one misc vector supported - mailbox */
8293 eicr &= IXGBE_VTEICR_MASK;
8294 if (eicr == IXGBE_MISC_VEC_ID)
8295 intr->flags |= IXGBE_FLAG_MAILBOX;
8301 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8303 struct ixgbe_interrupt *intr =
8304 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8306 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8307 ixgbevf_mbx_process(dev);
8308 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8311 ixgbevf_intr_enable(dev);
8317 ixgbevf_dev_interrupt_handler(void *param)
8319 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8321 ixgbevf_dev_interrupt_get_status(dev);
8322 ixgbevf_dev_interrupt_action(dev);
8326 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8327 * @hw: pointer to hardware structure
8329 * Stops the transmit data path and waits for the HW to internally empty
8330 * the Tx security block
8332 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8334 #define IXGBE_MAX_SECTX_POLL 40
8339 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8340 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8341 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8342 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8343 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8344 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8346 /* Use interrupt-safe sleep just in case */
8350 /* For informational purposes only */
8351 if (i >= IXGBE_MAX_SECTX_POLL)
8352 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8353 "path fully disabled. Continuing with init.");
8355 return IXGBE_SUCCESS;
8359 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8360 * @hw: pointer to hardware structure
8362 * Enables the transmit data path.
8364 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8368 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8369 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8370 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8371 IXGBE_WRITE_FLUSH(hw);
8373 return IXGBE_SUCCESS;
8376 /* restore n-tuple filter */
8378 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8380 struct ixgbe_filter_info *filter_info =
8381 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8382 struct ixgbe_5tuple_filter *node;
8384 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8385 ixgbe_inject_5tuple_filter(dev, node);
8389 /* restore ethernet type filter */
8391 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8393 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8394 struct ixgbe_filter_info *filter_info =
8395 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8398 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8399 if (filter_info->ethertype_mask & (1 << i)) {
8400 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8401 filter_info->ethertype_filters[i].etqf);
8402 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8403 filter_info->ethertype_filters[i].etqs);
8404 IXGBE_WRITE_FLUSH(hw);
8409 /* restore SYN filter */
8411 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8413 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8414 struct ixgbe_filter_info *filter_info =
8415 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8418 synqf = filter_info->syn_info;
8420 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8421 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8422 IXGBE_WRITE_FLUSH(hw);
8426 /* restore L2 tunnel filter */
8428 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8430 struct ixgbe_l2_tn_info *l2_tn_info =
8431 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8432 struct ixgbe_l2_tn_filter *node;
8433 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8435 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8436 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8437 l2_tn_conf.tunnel_id = node->key.tn_id;
8438 l2_tn_conf.pool = node->pool;
8439 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8443 /* restore rss filter */
8445 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8447 struct ixgbe_filter_info *filter_info =
8448 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8450 if (filter_info->rss_info.conf.queue_num)
8451 ixgbe_config_rss_filter(dev,
8452 &filter_info->rss_info, TRUE);
8456 ixgbe_filter_restore(struct rte_eth_dev *dev)
8458 ixgbe_ntuple_filter_restore(dev);
8459 ixgbe_ethertype_filter_restore(dev);
8460 ixgbe_syn_filter_restore(dev);
8461 ixgbe_fdir_filter_restore(dev);
8462 ixgbe_l2_tn_filter_restore(dev);
8463 ixgbe_rss_filter_restore(dev);
8469 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8471 struct ixgbe_l2_tn_info *l2_tn_info =
8472 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8473 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8475 if (l2_tn_info->e_tag_en)
8476 (void)ixgbe_e_tag_enable(hw);
8478 if (l2_tn_info->e_tag_fwd_en)
8479 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8481 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8484 /* remove all the n-tuple filters */
8486 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8488 struct ixgbe_filter_info *filter_info =
8489 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8490 struct ixgbe_5tuple_filter *p_5tuple;
8492 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8493 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8496 /* remove all the ether type filters */
8498 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8500 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8501 struct ixgbe_filter_info *filter_info =
8502 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8505 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8506 if (filter_info->ethertype_mask & (1 << i) &&
8507 !filter_info->ethertype_filters[i].conf) {
8508 (void)ixgbe_ethertype_filter_remove(filter_info,
8510 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8511 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8512 IXGBE_WRITE_FLUSH(hw);
8517 /* remove the SYN filter */
8519 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8521 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8522 struct ixgbe_filter_info *filter_info =
8523 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8525 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8526 filter_info->syn_info = 0;
8528 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8529 IXGBE_WRITE_FLUSH(hw);
8533 /* remove all the L2 tunnel filters */
8535 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8537 struct ixgbe_l2_tn_info *l2_tn_info =
8538 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8539 struct ixgbe_l2_tn_filter *l2_tn_filter;
8540 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8543 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8544 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8545 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8546 l2_tn_conf.pool = l2_tn_filter->pool;
8547 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8555 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8556 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8557 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8558 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8559 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8560 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8562 RTE_INIT(ixgbe_init_log);
8564 ixgbe_init_log(void)
8566 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8567 if (ixgbe_logtype_init >= 0)
8568 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8569 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8570 if (ixgbe_logtype_driver >= 0)
8571 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);