drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 233
 234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 235                         struct rte_ether_addr *mac_addr,
 236                         uint32_t index, uint32_t pool);
 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 239                                            struct rte_ether_addr *mac_addr);
 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 241 static bool is_device_supported(struct rte_eth_dev *dev,
 242                                 struct rte_pci_driver *drv);
 243
 244 /* For Virtual Function support */
 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 248 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 250                                    int wait_to_complete);
 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 277
 278 /* For Eth VMDQ APIs support */
 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 280                 rte_ether_addr * mac_addr, uint8_t on);
 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 283                 struct rte_eth_mirror_conf *mirror_conf,
 284                 uint8_t rule_id, uint8_t on);
 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 286                 uint8_t rule_id);
 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 288                                           uint16_t queue_id);
 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 290                                            uint16_t queue_id);
 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 292                                uint8_t queue, uint8_t msix_vector);
 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 294
 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 296                                 struct rte_ether_addr *mac_addr,
 297                                 uint32_t index, uint32_t pool);
 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 300                                              struct rte_ether_addr *mac_addr);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 311                                 enum rte_filter_op filter_op,
 312                                 void *arg);
 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 314                         struct rte_eth_ntuple_filter *filter);
 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter);
 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 321                      enum rte_filter_type filter_type,
 322                      enum rte_filter_op filter_op,
 323                      void *arg);
 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 325
 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 327                                       struct rte_ether_addr *mc_addr_set,
 328                                       uint32_t nb_mc_addr);
 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                    struct rte_eth_dcb_info *dcb_info);
 331
 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 334                             struct rte_dev_reg_info *regs);
 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340
 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 342                                  struct rte_eth_dev_module_info *modinfo);
 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 344                                    struct rte_dev_eeprom_info *info);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381
 382 /*
 383  * Define VF Stats MACRO for Non "cleared on read" register
 384  */
 385 #define UPDATE_VF_STAT(reg, last, cur)                          \
 386 {                                                               \
 387         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 388         cur += (latest - last) & UINT_MAX;                      \
 389         last = latest;                                          \
 390 }
 391
 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 393 {                                                                \
 394         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 395         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 396         u64 latest = ((new_msb << 32) | new_lsb);                \
 397         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 398         last = latest;                                           \
 399 }
 400
 401 #define IXGBE_SET_HWSTRIP(h, q) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (h)->bitmap[idx] |= 1 << bit;\
 405         } while (0)
 406
 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] &= ~(1 << bit);\
 411         } while (0)
 412
 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (r) = (h)->bitmap[idx] >> bit & 1;\
 417         } while (0)
 418
 419 int ixgbe_logtype_init;
 420 int ixgbe_logtype_driver;
 421
 422 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
 423 int ixgbe_logtype_rx;
 424 #endif
 425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
 426 int ixgbe_logtype_tx;
 427 #endif
 428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 429 int ixgbe_logtype_tx_free;
 430 #endif
 431
 432 /*
 433  * The set of PCI devices this driver supports
 434  */
 435 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 486 #endif
 487         { .vendor_id = 0, /* sentinel */ },
 488 };
 489
 490 /*
 491  * The set of PCI devices this driver supports (for 82599 VF)
 492  */
 493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct rte_eth_desc_lim rx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_RXD_ALIGN,
 511 };
 512
 513 static const struct rte_eth_desc_lim tx_desc_lim = {
 514         .nb_max = IXGBE_MAX_RING_DESC,
 515         .nb_min = IXGBE_MIN_RING_DESC,
 516         .nb_align = IXGBE_TXD_ALIGN,
 517         .nb_seg_max = IXGBE_TX_MAX_SEG,
 518         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 519 };
 520
 521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 522         .dev_configure        = ixgbe_dev_configure,
 523         .dev_start            = ixgbe_dev_start,
 524         .dev_stop             = ixgbe_dev_stop,
 525         .dev_set_link_up    = ixgbe_dev_set_link_up,
 526         .dev_set_link_down  = ixgbe_dev_set_link_down,
 527         .dev_close            = ixgbe_dev_close,
 528         .dev_reset            = ixgbe_dev_reset,
 529         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 530         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 531         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 532         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 533         .link_update          = ixgbe_dev_link_update,
 534         .stats_get            = ixgbe_dev_stats_get,
 535         .xstats_get           = ixgbe_dev_xstats_get,
 536         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 537         .stats_reset          = ixgbe_dev_stats_reset,
 538         .xstats_reset         = ixgbe_dev_xstats_reset,
 539         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 540         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 541         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 542         .fw_version_get       = ixgbe_fw_version_get,
 543         .dev_infos_get        = ixgbe_dev_info_get,
 544         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 545         .mtu_set              = ixgbe_dev_mtu_set,
 546         .vlan_filter_set      = ixgbe_vlan_filter_set,
 547         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 548         .vlan_offload_set     = ixgbe_vlan_offload_set,
 549         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 550         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 551         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 552         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 553         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 556         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 557         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 558         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 559         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 560         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 561         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 562         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 563         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 564         .dev_led_on           = ixgbe_dev_led_on,
 565         .dev_led_off          = ixgbe_dev_led_off,
 566         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 567         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 568         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 569         .mac_addr_add         = ixgbe_add_rar,
 570         .mac_addr_remove      = ixgbe_remove_rar,
 571         .mac_addr_set         = ixgbe_set_default_mac_addr,
 572         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 573         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 574         .mirror_rule_set      = ixgbe_mirror_rule_set,
 575         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 576         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 577         .reta_update          = ixgbe_dev_rss_reta_update,
 578         .reta_query           = ixgbe_dev_rss_reta_query,
 579         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 580         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 581         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 582         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 583         .rxq_info_get         = ixgbe_rxq_info_get,
 584         .txq_info_get         = ixgbe_txq_info_get,
 585         .timesync_enable      = ixgbe_timesync_enable,
 586         .timesync_disable     = ixgbe_timesync_disable,
 587         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 588         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 589         .get_reg              = ixgbe_get_regs,
 590         .get_eeprom_length    = ixgbe_get_eeprom_length,
 591         .get_eeprom           = ixgbe_get_eeprom,
 592         .set_eeprom           = ixgbe_set_eeprom,
 593         .get_module_info      = ixgbe_get_module_info,
 594         .get_module_eeprom    = ixgbe_get_module_eeprom,
 595         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 596         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 597         .timesync_read_time   = ixgbe_timesync_read_time,
 598         .timesync_write_time  = ixgbe_timesync_write_time,
 599         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 600         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 601         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 602         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 603         .tm_ops_get           = ixgbe_tm_ops_get,
 604 };
 605
 606 /*
 607  * dev_ops for virtual function, bare necessities for basic vf
 608  * operation have been implemented
 609  */
 610 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 611         .dev_configure        = ixgbevf_dev_configure,
 612         .dev_start            = ixgbevf_dev_start,
 613         .dev_stop             = ixgbevf_dev_stop,
 614         .link_update          = ixgbevf_dev_link_update,
 615         .stats_get            = ixgbevf_dev_stats_get,
 616         .xstats_get           = ixgbevf_dev_xstats_get,
 617         .stats_reset          = ixgbevf_dev_stats_reset,
 618         .xstats_reset         = ixgbevf_dev_stats_reset,
 619         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 620         .dev_close            = ixgbevf_dev_close,
 621         .dev_reset            = ixgbevf_dev_reset,
 622         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 623         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 624         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 625         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 626         .dev_infos_get        = ixgbevf_dev_info_get,
 627         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 628         .mtu_set              = ixgbevf_dev_set_mtu,
 629         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 630         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 631         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 632         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 633         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 634         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 635         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 636         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 637         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 638         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 639         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 640         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 641         .mac_addr_add         = ixgbevf_add_mac_addr,
 642         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 643         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 644         .rxq_info_get         = ixgbe_rxq_info_get,
 645         .txq_info_get         = ixgbe_txq_info_get,
 646         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 647         .get_reg              = ixgbevf_get_regs,
 648         .reta_update          = ixgbe_dev_rss_reta_update,
 649         .reta_query           = ixgbe_dev_rss_reta_query,
 650         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 651         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 652 };
 653
 654 /* store statistics names and its offset in stats structure */
 655 struct rte_ixgbe_xstats_name_off {
 656         char name[RTE_ETH_XSTATS_NAME_SIZE];
 657         unsigned offset;
 658 };
 659
 660 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 661         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 662         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 663         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 664         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 665         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 666         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 667         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 668         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 669         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 670         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 671         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 672         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 673         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 674         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 675         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 676                 prc1023)},
 677         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 678                 prc1522)},
 679         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 680         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 681         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 682         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 683         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 684         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 685         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 686         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 687         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 688         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 689         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 690         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 691         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 692         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 693         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 694         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 695         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 696                 ptc1023)},
 697         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 698                 ptc1522)},
 699         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 700         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 701         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 702         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 703
 704         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirustat_add)},
 706         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirustat_remove)},
 708         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 709                 fdirfstat_fadd)},
 710         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 711                 fdirfstat_fremove)},
 712         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 713                 fdirmatch)},
 714         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 715                 fdirmiss)},
 716
 717         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 718         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 719         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 720                 fclast)},
 721         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 722         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 723         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 724         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 725         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 726                 fcoe_noddp)},
 727         {"rx_fcoe_no_direct_data_placement_ext_buff",
 728                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 729
 730         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxontxc)},
 732         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxonrxc)},
 734         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 735                 lxofftxc)},
 736         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 737                 lxoffrxc)},
 738         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 739 };
 740
 741 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 742                            sizeof(rte_ixgbe_stats_strings[0]))
 743
 744 /* MACsec statistics */
 745 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 746         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_untagged)},
 748         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 749                 out_pkts_encrypted)},
 750         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 751                 out_pkts_protected)},
 752         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 753                 out_octets_encrypted)},
 754         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 755                 out_octets_protected)},
 756         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_untagged)},
 758         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_badtag)},
 760         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_nosci)},
 762         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_unknownsci)},
 764         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 765                 in_octets_decrypted)},
 766         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 767                 in_octets_validated)},
 768         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_unchecked)},
 770         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_delayed)},
 772         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_late)},
 774         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_ok)},
 776         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_invalid)},
 778         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_notvalid)},
 780         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_unusedsa)},
 782         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_notusingsa)},
 784 };
 785
 786 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 787                            sizeof(rte_ixgbe_macsec_strings[0]))
 788
 789 /* Per-queue statistics */
 790 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 791         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 792         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 793         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 794         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 795 };
 796
 797 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 798                            sizeof(rte_ixgbe_rxq_strings[0]))
 799 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 800
 801 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 802         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 803         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 804         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 805                 pxon2offc)},
 806 };
 807
 808 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 809                            sizeof(rte_ixgbe_txq_strings[0]))
 810 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 811
 812 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 813         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 814 };
 815
 816 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 817                 sizeof(rte_ixgbevf_stats_strings[0]))
 818
 819 /*
 820  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 821  */
 822 static inline int
 823 ixgbe_is_sfp(struct ixgbe_hw *hw)
 824 {
 825         switch (hw->phy.type) {
 826         case ixgbe_phy_sfp_avago:
 827         case ixgbe_phy_sfp_ftl:
 828         case ixgbe_phy_sfp_intel:
 829         case ixgbe_phy_sfp_unknown:
 830         case ixgbe_phy_sfp_passive_tyco:
 831         case ixgbe_phy_sfp_passive_unknown:
 832                 return 1;
 833         default:
 834                 return 0;
 835         }
 836 }
 837
 838 static inline int32_t
 839 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 840 {
 841         uint32_t ctrl_ext;
 842         int32_t status;
 843
 844         status = ixgbe_reset_hw(hw);
 845
 846         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 847         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 848         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 849         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 850         IXGBE_WRITE_FLUSH(hw);
 851
 852         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 853                 status = IXGBE_SUCCESS;
 854         return status;
 855 }
 856
 857 static inline void
 858 ixgbe_enable_intr(struct rte_eth_dev *dev)
 859 {
 860         struct ixgbe_interrupt *intr =
 861                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 862         struct ixgbe_hw *hw =
 863                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 864
 865         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 866         IXGBE_WRITE_FLUSH(hw);
 867 }
 868
 869 /*
 870  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 871  */
 872 static void
 873 ixgbe_disable_intr(struct ixgbe_hw *hw)
 874 {
 875         PMD_INIT_FUNC_TRACE();
 876
 877         if (hw->mac.type == ixgbe_mac_82598EB) {
 878                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 879         } else {
 880                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 881                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 882                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 883         }
 884         IXGBE_WRITE_FLUSH(hw);
 885 }
 886
 887 /*
 888  * This function resets queue statistics mapping registers.
 889  * From Niantic datasheet, Initialization of Statistics section:
 890  * "...if software requires the queue counters, the RQSMR and TQSM registers
 891  * must be re-programmed following a device reset.
 892  */
 893 static void
 894 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 895 {
 896         uint32_t i;
 897
 898         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 899                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 900                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 901         }
 902 }
 903
 904
 905 static int
 906 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 907                                   uint16_t queue_id,
 908                                   uint8_t stat_idx,
 909                                   uint8_t is_rx)
 910 {
 911 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 912 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 913 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 914
 915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 916         struct ixgbe_stat_mapping_registers *stat_mappings =
 917                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 918         uint32_t qsmr_mask = 0;
 919         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 920         uint32_t q_map;
 921         uint8_t n, offset;
 922
 923         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 924                 (hw->mac.type != ixgbe_mac_X540) &&
 925                 (hw->mac.type != ixgbe_mac_X550) &&
 926                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 927                 (hw->mac.type != ixgbe_mac_X550EM_a))
 928                 return -ENOSYS;
 929
 930         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 931                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 932                      queue_id, stat_idx);
 933
 934         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 935         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 936                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 937                 return -EIO;
 938         }
 939         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 940
 941         /* Now clear any previous stat_idx set */
 942         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 943         if (!is_rx)
 944                 stat_mappings->tqsm[n] &= ~clearing_mask;
 945         else
 946                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 947
 948         q_map = (uint32_t)stat_idx;
 949         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 950         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 951         if (!is_rx)
 952                 stat_mappings->tqsm[n] |= qsmr_mask;
 953         else
 954                 stat_mappings->rqsmr[n] |= qsmr_mask;
 955
 956         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 957                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 958                      queue_id, stat_idx);
 959         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 960                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 961
 962         /* Now write the mapping in the appropriate register */
 963         if (is_rx) {
 964                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 965                              stat_mappings->rqsmr[n], n);
 966                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 967         } else {
 968                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 969                              stat_mappings->tqsm[n], n);
 970                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 971         }
 972         return 0;
 973 }
 974
 975 static void
 976 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 977 {
 978         struct ixgbe_stat_mapping_registers *stat_mappings =
 979                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         int i;
 982
 983         /* write whatever was in stat mapping table to the NIC */
 984         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 985                 /* rx */
 986                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 987
 988                 /* tx */
 989                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 990         }
 991 }
 992
 993 static void
 994 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 995 {
 996         uint8_t i;
 997         struct ixgbe_dcb_tc_config *tc;
 998         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 999
1000         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1001         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1002         for (i = 0; i < dcb_max_tc; i++) {
1003                 tc = &dcb_config->tc_config[i];
1004                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1005                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1006                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1007                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1008                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1009                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1010                 tc->pfc = ixgbe_dcb_pfc_disabled;
1011         }
1012
1013         /* Initialize default user to priority mapping, UPx->TC0 */
1014         tc = &dcb_config->tc_config[0];
1015         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1016         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1017         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1018                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1019                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1020         }
1021         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1022         dcb_config->pfc_mode_enable = false;
1023         dcb_config->vt_mode = true;
1024         dcb_config->round_robin_enable = false;
1025         /* support all DCB capabilities in 82599 */
1026         dcb_config->support.capabilities = 0xFF;
1027
1028         /*we only support 4 Tcs for X540, X550 */
1029         if (hw->mac.type == ixgbe_mac_X540 ||
1030                 hw->mac.type == ixgbe_mac_X550 ||
1031                 hw->mac.type == ixgbe_mac_X550EM_x ||
1032                 hw->mac.type == ixgbe_mac_X550EM_a) {
1033                 dcb_config->num_tcs.pg_tcs = 4;
1034                 dcb_config->num_tcs.pfc_tcs = 4;
1035         }
1036 }
1037
1038 /*
1039  * Ensure that all locks are released before first NVM or PHY access
1040  */
1041 static void
1042 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1043 {
1044         uint16_t mask;
1045
1046         /*
1047          * Phy lock should not fail in this early stage. If this is the case,
1048          * it is due to an improper exit of the application.
1049          * So force the release of the faulty lock. Release of common lock
1050          * is done automatically by swfw_sync function.
1051          */
1052         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1053         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1054                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1055         }
1056         ixgbe_release_swfw_semaphore(hw, mask);
1057
1058         /*
1059          * These ones are more tricky since they are common to all ports; but
1060          * swfw_sync retries last long enough (1s) to be almost sure that if
1061          * lock can not be taken it is due to an improper lock of the
1062          * semaphore.
1063          */
1064         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1065         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1066                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1067         }
1068         ixgbe_release_swfw_semaphore(hw, mask);
1069 }
1070
1071 /*
1072  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1073  * It returns 0 on success.
1074  */
1075 static int
1076 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1077 {
1078         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1079         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1080         struct ixgbe_hw *hw =
1081                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1082         struct ixgbe_vfta *shadow_vfta =
1083                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1084         struct ixgbe_hwstrip *hwstrip =
1085                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1086         struct ixgbe_dcb_config *dcb_config =
1087                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1088         struct ixgbe_filter_info *filter_info =
1089                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1090         struct ixgbe_bw_conf *bw_conf =
1091                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1092         uint32_t ctrl_ext;
1093         uint16_t csum;
1094         int diag, i;
1095
1096         PMD_INIT_FUNC_TRACE();
1097
1098         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1099         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1100         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1101         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1102
1103         /*
1104          * For secondary processes, we don't initialise any further as primary
1105          * has already done this work. Only check we don't need a different
1106          * RX and TX function.
1107          */
1108         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1109                 struct ixgbe_tx_queue *txq;
1110                 /* TX queue function in primary, set by last queue initialized
1111                  * Tx queue may not initialized by primary process
1112                  */
1113                 if (eth_dev->data->tx_queues) {
1114                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1115                         ixgbe_set_tx_function(eth_dev, txq);
1116                 } else {
1117                         /* Use default TX function if we get here */
1118                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1119                                      "Using default TX function.");
1120                 }
1121
1122                 ixgbe_set_rx_function(eth_dev);
1123
1124                 return 0;
1125         }
1126
1127         rte_eth_copy_pci_info(eth_dev, pci_dev);
1128
1129         /* Vendor and Device ID need to be set before init of shared code */
1130         hw->device_id = pci_dev->id.device_id;
1131         hw->vendor_id = pci_dev->id.vendor_id;
1132         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1133         hw->allow_unsupported_sfp = 1;
1134
1135         /* Initialize the shared code (base driver) */
1136 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1137         diag = ixgbe_bypass_init_shared_code(hw);
1138 #else
1139         diag = ixgbe_init_shared_code(hw);
1140 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1141
1142         if (diag != IXGBE_SUCCESS) {
1143                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1144                 return -EIO;
1145         }
1146
1147         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1148                 PMD_INIT_LOG(ERR, "\nERROR: "
1149                         "Firmware recovery mode detected. Limiting functionality.\n"
1150                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1151                         "User Guide for details on firmware recovery mode.");
1152                 return -EIO;
1153         }
1154
1155         /* pick up the PCI bus settings for reporting later */
1156         ixgbe_get_bus_info(hw);
1157
1158         /* Unlock any pending hardware semaphore */
1159         ixgbe_swfw_lock_reset(hw);
1160
1161 #ifdef RTE_LIBRTE_SECURITY
1162         /* Initialize security_ctx only for primary process*/
1163         if (ixgbe_ipsec_ctx_create(eth_dev))
1164                 return -ENOMEM;
1165 #endif
1166
1167         /* Initialize DCB configuration*/
1168         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1169         ixgbe_dcb_init(hw, dcb_config);
1170         /* Get Hardware Flow Control setting */
1171         hw->fc.requested_mode = ixgbe_fc_full;
1172         hw->fc.current_mode = ixgbe_fc_full;
1173         hw->fc.pause_time = IXGBE_FC_PAUSE;
1174         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1175                 hw->fc.low_water[i] = IXGBE_FC_LO;
1176                 hw->fc.high_water[i] = IXGBE_FC_HI;
1177         }
1178         hw->fc.send_xon = 1;
1179
1180         /* Make sure we have a good EEPROM before we read from it */
1181         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1182         if (diag != IXGBE_SUCCESS) {
1183                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1184                 return -EIO;
1185         }
1186
1187 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1188         diag = ixgbe_bypass_init_hw(hw);
1189 #else
1190         diag = ixgbe_init_hw(hw);
1191 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1192
1193         /*
1194          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1195          * is called too soon after the kernel driver unbinding/binding occurs.
1196          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1197          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1198          * also called. See ixgbe_identify_phy_82599(). The reason for the
1199          * failure is not known, and only occuts when virtualisation features
1200          * are disabled in the bios. A delay of 100ms  was found to be enough by
1201          * trial-and-error, and is doubled to be safe.
1202          */
1203         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1204                 rte_delay_ms(200);
1205                 diag = ixgbe_init_hw(hw);
1206         }
1207
1208         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1209                 diag = IXGBE_SUCCESS;
1210
1211         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1212                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1213                              "LOM.  Please be aware there may be issues associated "
1214                              "with your hardware.");
1215                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1216                              "please contact your Intel or hardware representative "
1217                              "who provided you with this hardware.");
1218         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1219                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1220         if (diag) {
1221                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1222                 return -EIO;
1223         }
1224
1225         /* Reset the hw statistics */
1226         ixgbe_dev_stats_reset(eth_dev);
1227
1228         /* disable interrupt */
1229         ixgbe_disable_intr(hw);
1230
1231         /* reset mappings for queue statistics hw counters*/
1232         ixgbe_reset_qstat_mappings(hw);
1233
1234         /* Allocate memory for storing MAC addresses */
1235         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1236                                                hw->mac.num_rar_entries, 0);
1237         if (eth_dev->data->mac_addrs == NULL) {
1238                 PMD_INIT_LOG(ERR,
1239                              "Failed to allocate %u bytes needed to store "
1240                              "MAC addresses",
1241                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1242                 return -ENOMEM;
1243         }
1244         /* Copy the permanent MAC address */
1245         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1246                         &eth_dev->data->mac_addrs[0]);
1247
1248         /* Allocate memory for storing hash filter MAC addresses */
1249         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1250                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1251         if (eth_dev->data->hash_mac_addrs == NULL) {
1252                 PMD_INIT_LOG(ERR,
1253                              "Failed to allocate %d bytes needed to store MAC addresses",
1254                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1255                 return -ENOMEM;
1256         }
1257
1258         /* Pass the information to the rte_eth_dev_close() that it should also
1259          * release the private port resources.
1260          */
1261         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1262
1263         /* initialize the vfta */
1264         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1265
1266         /* initialize the hw strip bitmap*/
1267         memset(hwstrip, 0, sizeof(*hwstrip));
1268
1269         /* initialize PF if max_vfs not zero */
1270         ixgbe_pf_host_init(eth_dev);
1271
1272         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1273         /* let hardware know driver is loaded */
1274         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1275         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1276         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1277         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1278         IXGBE_WRITE_FLUSH(hw);
1279
1280         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1281                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1282                              (int) hw->mac.type, (int) hw->phy.type,
1283                              (int) hw->phy.sfp_type);
1284         else
1285                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1286                              (int) hw->mac.type, (int) hw->phy.type);
1287
1288         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1289                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1290                      pci_dev->id.device_id);
1291
1292         rte_intr_callback_register(intr_handle,
1293                                    ixgbe_dev_interrupt_handler, eth_dev);
1294
1295         /* enable uio/vfio intr/eventfd mapping */
1296         rte_intr_enable(intr_handle);
1297
1298         /* enable support intr */
1299         ixgbe_enable_intr(eth_dev);
1300
1301         /* initialize filter info */
1302         memset(filter_info, 0,
1303                sizeof(struct ixgbe_filter_info));
1304
1305         /* initialize 5tuple filter list */
1306         TAILQ_INIT(&filter_info->fivetuple_list);
1307
1308         /* initialize flow director filter list & hash */
1309         ixgbe_fdir_filter_init(eth_dev);
1310
1311         /* initialize l2 tunnel filter list & hash */
1312         ixgbe_l2_tn_filter_init(eth_dev);
1313
1314         /* initialize flow filter lists */
1315         ixgbe_filterlist_init();
1316
1317         /* initialize bandwidth configuration info */
1318         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1319
1320         /* initialize Traffic Manager configuration */
1321         ixgbe_tm_conf_init(eth_dev);
1322
1323         return 0;
1324 }
1325
1326 static int
1327 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1328 {
1329         PMD_INIT_FUNC_TRACE();
1330
1331         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1332                 return 0;
1333
1334         ixgbe_dev_close(eth_dev);
1335
1336         return 0;
1337 }
1338
1339 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1340 {
1341         struct ixgbe_filter_info *filter_info =
1342                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1343         struct ixgbe_5tuple_filter *p_5tuple;
1344
1345         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1346                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1347                              p_5tuple,
1348                              entries);
1349                 rte_free(p_5tuple);
1350         }
1351         memset(filter_info->fivetuple_mask, 0,
1352                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1353
1354         return 0;
1355 }
1356
1357 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1358 {
1359         struct ixgbe_hw_fdir_info *fdir_info =
1360                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1361         struct ixgbe_fdir_filter *fdir_filter;
1362
1363                 if (fdir_info->hash_map)
1364                 rte_free(fdir_info->hash_map);
1365         if (fdir_info->hash_handle)
1366                 rte_hash_free(fdir_info->hash_handle);
1367
1368         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1369                 TAILQ_REMOVE(&fdir_info->fdir_list,
1370                              fdir_filter,
1371                              entries);
1372                 rte_free(fdir_filter);
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1379 {
1380         struct ixgbe_l2_tn_info *l2_tn_info =
1381                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1382         struct ixgbe_l2_tn_filter *l2_tn_filter;
1383
1384         if (l2_tn_info->hash_map)
1385                 rte_free(l2_tn_info->hash_map);
1386         if (l2_tn_info->hash_handle)
1387                 rte_hash_free(l2_tn_info->hash_handle);
1388
1389         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1390                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1391                              l2_tn_filter,
1392                              entries);
1393                 rte_free(l2_tn_filter);
1394         }
1395
1396         return 0;
1397 }
1398
1399 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1400 {
1401         struct ixgbe_hw_fdir_info *fdir_info =
1402                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1403         char fdir_hash_name[RTE_HASH_NAMESIZE];
1404         struct rte_hash_parameters fdir_hash_params = {
1405                 .name = fdir_hash_name,
1406                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1407                 .key_len = sizeof(union ixgbe_atr_input),
1408                 .hash_func = rte_hash_crc,
1409                 .hash_func_init_val = 0,
1410                 .socket_id = rte_socket_id(),
1411         };
1412
1413         TAILQ_INIT(&fdir_info->fdir_list);
1414         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1415                  "fdir_%s", eth_dev->device->name);
1416         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1417         if (!fdir_info->hash_handle) {
1418                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1419                 return -EINVAL;
1420         }
1421         fdir_info->hash_map = rte_zmalloc("ixgbe",
1422                                           sizeof(struct ixgbe_fdir_filter *) *
1423                                           IXGBE_MAX_FDIR_FILTER_NUM,
1424                                           0);
1425         if (!fdir_info->hash_map) {
1426                 PMD_INIT_LOG(ERR,
1427                              "Failed to allocate memory for fdir hash map!");
1428                 return -ENOMEM;
1429         }
1430         fdir_info->mask_added = FALSE;
1431
1432         return 0;
1433 }
1434
1435 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1436 {
1437         struct ixgbe_l2_tn_info *l2_tn_info =
1438                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1439         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1440         struct rte_hash_parameters l2_tn_hash_params = {
1441                 .name = l2_tn_hash_name,
1442                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1443                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1444                 .hash_func = rte_hash_crc,
1445                 .hash_func_init_val = 0,
1446                 .socket_id = rte_socket_id(),
1447         };
1448
1449         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1450         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1451                  "l2_tn_%s", eth_dev->device->name);
1452         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1453         if (!l2_tn_info->hash_handle) {
1454                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1455                 return -EINVAL;
1456         }
1457         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1458                                    sizeof(struct ixgbe_l2_tn_filter *) *
1459                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1460                                    0);
1461         if (!l2_tn_info->hash_map) {
1462                 PMD_INIT_LOG(ERR,
1463                         "Failed to allocate memory for L2 TN hash map!");
1464                 return -ENOMEM;
1465         }
1466         l2_tn_info->e_tag_en = FALSE;
1467         l2_tn_info->e_tag_fwd_en = FALSE;
1468         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1469
1470         return 0;
1471 }
1472 /*
1473  * Negotiate mailbox API version with the PF.
1474  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1475  * Then we try to negotiate starting with the most recent one.
1476  * If all negotiation attempts fail, then we will proceed with
1477  * the default one (ixgbe_mbox_api_10).
1478  */
1479 static void
1480 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1481 {
1482         int32_t i;
1483
1484         /* start with highest supported, proceed down */
1485         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1486                 ixgbe_mbox_api_13,
1487                 ixgbe_mbox_api_12,
1488                 ixgbe_mbox_api_11,
1489                 ixgbe_mbox_api_10,
1490         };
1491
1492         for (i = 0;
1493                         i != RTE_DIM(sup_ver) &&
1494                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1495                         i++)
1496                 ;
1497 }
1498
1499 static void
1500 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1501 {
1502         uint64_t random;
1503
1504         /* Set Organizationally Unique Identifier (OUI) prefix. */
1505         mac_addr->addr_bytes[0] = 0x00;
1506         mac_addr->addr_bytes[1] = 0x09;
1507         mac_addr->addr_bytes[2] = 0xC0;
1508         /* Force indication of locally assigned MAC address. */
1509         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1510         /* Generate the last 3 bytes of the MAC address with a random number. */
1511         random = rte_rand();
1512         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1513 }
1514
1515 static int
1516 devarg_handle_int(__rte_unused const char *key, const char *value,
1517                   void *extra_args)
1518 {
1519         uint16_t *n = extra_args;
1520
1521         if (value == NULL || extra_args == NULL)
1522                 return -EINVAL;
1523
1524         *n = (uint16_t)strtoul(value, NULL, 0);
1525         if (*n == USHRT_MAX && errno == ERANGE)
1526                 return -1;
1527
1528         return 0;
1529 }
1530
1531 static void
1532 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1533                       struct rte_devargs *devargs)
1534 {
1535         struct rte_kvargs *kvlist;
1536         uint16_t pflink_fullchk;
1537
1538         if (devargs == NULL)
1539                 return;
1540
1541         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1542         if (kvlist == NULL)
1543                 return;
1544
1545         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1546             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1547                                devarg_handle_int, &pflink_fullchk) == 0 &&
1548             pflink_fullchk == 1)
1549                 adapter->pflink_fullchk = 1;
1550
1551         rte_kvargs_free(kvlist);
1552 }
1553
1554 /*
1555  * Virtual Function device init
1556  */
1557 static int
1558 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1559 {
1560         int diag;
1561         uint32_t tc, tcs;
1562         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1563         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1564         struct ixgbe_hw *hw =
1565                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1566         struct ixgbe_vfta *shadow_vfta =
1567                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1568         struct ixgbe_hwstrip *hwstrip =
1569                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1570         struct rte_ether_addr *perm_addr =
1571                 (struct rte_ether_addr *)hw->mac.perm_addr;
1572
1573         PMD_INIT_FUNC_TRACE();
1574
1575         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1576         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1577         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1578
1579         /* for secondary processes, we don't initialise any further as primary
1580          * has already done this work. Only check we don't need a different
1581          * RX function
1582          */
1583         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1584                 struct ixgbe_tx_queue *txq;
1585                 /* TX queue function in primary, set by last queue initialized
1586                  * Tx queue may not initialized by primary process
1587                  */
1588                 if (eth_dev->data->tx_queues) {
1589                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1590                         ixgbe_set_tx_function(eth_dev, txq);
1591                 } else {
1592                         /* Use default TX function if we get here */
1593                         PMD_INIT_LOG(NOTICE,
1594                                      "No TX queues configured yet. Using default TX function.");
1595                 }
1596
1597                 ixgbe_set_rx_function(eth_dev);
1598
1599                 return 0;
1600         }
1601
1602         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1603                               pci_dev->device.devargs);
1604
1605         rte_eth_copy_pci_info(eth_dev, pci_dev);
1606
1607         hw->device_id = pci_dev->id.device_id;
1608         hw->vendor_id = pci_dev->id.vendor_id;
1609         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1610
1611         /* initialize the vfta */
1612         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1613
1614         /* initialize the hw strip bitmap*/
1615         memset(hwstrip, 0, sizeof(*hwstrip));
1616
1617         /* Initialize the shared code (base driver) */
1618         diag = ixgbe_init_shared_code(hw);
1619         if (diag != IXGBE_SUCCESS) {
1620                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1621                 return -EIO;
1622         }
1623
1624         /* init_mailbox_params */
1625         hw->mbx.ops.init_params(hw);
1626
1627         /* Reset the hw statistics */
1628         ixgbevf_dev_stats_reset(eth_dev);
1629
1630         /* Disable the interrupts for VF */
1631         ixgbevf_intr_disable(eth_dev);
1632
1633         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1634         diag = hw->mac.ops.reset_hw(hw);
1635
1636         /*
1637          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1638          * the underlying PF driver has not assigned a MAC address to the VF.
1639          * In this case, assign a random MAC address.
1640          */
1641         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1642                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1643                 /*
1644                  * This error code will be propagated to the app by
1645                  * rte_eth_dev_reset, so use a public error code rather than
1646                  * the internal-only IXGBE_ERR_RESET_FAILED
1647                  */
1648                 return -EAGAIN;
1649         }
1650
1651         /* negotiate mailbox API version to use with the PF. */
1652         ixgbevf_negotiate_api(hw);
1653
1654         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1655         ixgbevf_get_queues(hw, &tcs, &tc);
1656
1657         /* Allocate memory for storing MAC addresses */
1658         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1659                                                hw->mac.num_rar_entries, 0);
1660         if (eth_dev->data->mac_addrs == NULL) {
1661                 PMD_INIT_LOG(ERR,
1662                              "Failed to allocate %u bytes needed to store "
1663                              "MAC addresses",
1664                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1665                 return -ENOMEM;
1666         }
1667
1668         /* Pass the information to the rte_eth_dev_close() that it should also
1669          * release the private port resources.
1670          */
1671         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1672
1673         /* Generate a random MAC address, if none was assigned by PF. */
1674         if (rte_is_zero_ether_addr(perm_addr)) {
1675                 generate_random_mac_addr(perm_addr);
1676                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1677                 if (diag) {
1678                         rte_free(eth_dev->data->mac_addrs);
1679                         eth_dev->data->mac_addrs = NULL;
1680                         return diag;
1681                 }
1682                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1683                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1684                              "%02x:%02x:%02x:%02x:%02x:%02x",
1685                              perm_addr->addr_bytes[0],
1686                              perm_addr->addr_bytes[1],
1687                              perm_addr->addr_bytes[2],
1688                              perm_addr->addr_bytes[3],
1689                              perm_addr->addr_bytes[4],
1690                              perm_addr->addr_bytes[5]);
1691         }
1692
1693         /* Copy the permanent MAC address */
1694         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1695
1696         /* reset the hardware with the new settings */
1697         diag = hw->mac.ops.start_hw(hw);
1698         switch (diag) {
1699         case  0:
1700                 break;
1701
1702         default:
1703                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1704                 return -EIO;
1705         }
1706
1707         rte_intr_callback_register(intr_handle,
1708                                    ixgbevf_dev_interrupt_handler, eth_dev);
1709         rte_intr_enable(intr_handle);
1710         ixgbevf_intr_enable(eth_dev);
1711
1712         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1713                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1714                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1715
1716         return 0;
1717 }
1718
1719 /* Virtual Function device uninit */
1720
1721 static int
1722 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1723 {
1724         PMD_INIT_FUNC_TRACE();
1725
1726         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1727                 return 0;
1728
1729         ixgbevf_dev_close(eth_dev);
1730
1731         return 0;
1732 }
1733
1734 static int
1735 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1736                 struct rte_pci_device *pci_dev)
1737 {
1738         char name[RTE_ETH_NAME_MAX_LEN];
1739         struct rte_eth_dev *pf_ethdev;
1740         struct rte_eth_devargs eth_da;
1741         int i, retval;
1742
1743         if (pci_dev->device.devargs) {
1744                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1745                                 &eth_da);
1746                 if (retval)
1747                         return retval;
1748         } else
1749                 memset(&eth_da, 0, sizeof(eth_da));
1750
1751         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1752                 sizeof(struct ixgbe_adapter),
1753                 eth_dev_pci_specific_init, pci_dev,
1754                 eth_ixgbe_dev_init, NULL);
1755
1756         if (retval || eth_da.nb_representor_ports < 1)
1757                 return retval;
1758
1759         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1760         if (pf_ethdev == NULL)
1761                 return -ENODEV;
1762
1763         /* probe VF representor ports */
1764         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1765                 struct ixgbe_vf_info *vfinfo;
1766                 struct ixgbe_vf_representor representor;
1767
1768                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1769                         pf_ethdev->data->dev_private);
1770                 if (vfinfo == NULL) {
1771                         PMD_DRV_LOG(ERR,
1772                                 "no virtual functions supported by PF");
1773                         break;
1774                 }
1775
1776                 representor.vf_id = eth_da.representor_ports[i];
1777                 representor.switch_domain_id = vfinfo->switch_domain_id;
1778                 representor.pf_ethdev = pf_ethdev;
1779
1780                 /* representor port net_bdf_port */
1781                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1782                         pci_dev->device.name,
1783                         eth_da.representor_ports[i]);
1784
1785                 retval = rte_eth_dev_create(&pci_dev->device, name,
1786                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1787                         ixgbe_vf_representor_init, &representor);
1788
1789                 if (retval)
1790                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1791                                 "representor %s.", name);
1792         }
1793
1794         return 0;
1795 }
1796
1797 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1798 {
1799         struct rte_eth_dev *ethdev;
1800
1801         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1802         if (!ethdev)
1803                 return -ENODEV;
1804
1805         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1806                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1807         else
1808                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1809 }
1810
1811 static struct rte_pci_driver rte_ixgbe_pmd = {
1812         .id_table = pci_id_ixgbe_map,
1813         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1814         .probe = eth_ixgbe_pci_probe,
1815         .remove = eth_ixgbe_pci_remove,
1816 };
1817
1818 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1819         struct rte_pci_device *pci_dev)
1820 {
1821         return rte_eth_dev_pci_generic_probe(pci_dev,
1822                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1823 }
1824
1825 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1826 {
1827         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1828 }
1829
1830 /*
1831  * virtual function driver struct
1832  */
1833 static struct rte_pci_driver rte_ixgbevf_pmd = {
1834         .id_table = pci_id_ixgbevf_map,
1835         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1836         .probe = eth_ixgbevf_pci_probe,
1837         .remove = eth_ixgbevf_pci_remove,
1838 };
1839
1840 static int
1841 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1842 {
1843         struct ixgbe_hw *hw =
1844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct ixgbe_vfta *shadow_vfta =
1846                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1847         uint32_t vfta;
1848         uint32_t vid_idx;
1849         uint32_t vid_bit;
1850
1851         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1852         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1853         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1854         if (on)
1855                 vfta |= vid_bit;
1856         else
1857                 vfta &= ~vid_bit;
1858         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1859
1860         /* update local VFTA copy */
1861         shadow_vfta->vfta[vid_idx] = vfta;
1862
1863         return 0;
1864 }
1865
1866 static void
1867 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1868 {
1869         if (on)
1870                 ixgbe_vlan_hw_strip_enable(dev, queue);
1871         else
1872                 ixgbe_vlan_hw_strip_disable(dev, queue);
1873 }
1874
1875 static int
1876 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1877                     enum rte_vlan_type vlan_type,
1878                     uint16_t tpid)
1879 {
1880         struct ixgbe_hw *hw =
1881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         int ret = 0;
1883         uint32_t reg;
1884         uint32_t qinq;
1885
1886         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887         qinq &= IXGBE_DMATXCTL_GDV;
1888
1889         switch (vlan_type) {
1890         case ETH_VLAN_TYPE_INNER:
1891                 if (qinq) {
1892                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1893                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1894                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1895                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1896                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1897                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1898                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1899                 } else {
1900                         ret = -ENOTSUP;
1901                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1902                                     " by single VLAN");
1903                 }
1904                 break;
1905         case ETH_VLAN_TYPE_OUTER:
1906                 if (qinq) {
1907                         /* Only the high 16-bits is valid */
1908                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1909                                         IXGBE_EXVET_VET_EXT_SHIFT);
1910                 } else {
1911                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1913                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1914                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1915                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1916                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1917                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1918                 }
1919
1920                 break;
1921         default:
1922                 ret = -EINVAL;
1923                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1924                 break;
1925         }
1926
1927         return ret;
1928 }
1929
1930 void
1931 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1932 {
1933         struct ixgbe_hw *hw =
1934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         uint32_t vlnctrl;
1936
1937         PMD_INIT_FUNC_TRACE();
1938
1939         /* Filter Table Disable */
1940         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1941         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1942
1943         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1944 }
1945
1946 void
1947 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1948 {
1949         struct ixgbe_hw *hw =
1950                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct ixgbe_vfta *shadow_vfta =
1952                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1953         uint32_t vlnctrl;
1954         uint16_t i;
1955
1956         PMD_INIT_FUNC_TRACE();
1957
1958         /* Filter Table Enable */
1959         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1960         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1961         vlnctrl |= IXGBE_VLNCTRL_VFE;
1962
1963         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1964
1965         /* write whatever is in local vfta copy */
1966         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1967                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1968 }
1969
1970 static void
1971 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1972 {
1973         struct ixgbe_hwstrip *hwstrip =
1974                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1975         struct ixgbe_rx_queue *rxq;
1976
1977         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1978                 return;
1979
1980         if (on)
1981                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1982         else
1983                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1984
1985         if (queue >= dev->data->nb_rx_queues)
1986                 return;
1987
1988         rxq = dev->data->rx_queues[queue];
1989
1990         if (on) {
1991                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1992                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1993         } else {
1994                 rxq->vlan_flags = PKT_RX_VLAN;
1995                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1996         }
1997 }
1998
1999 static void
2000 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005
2006         PMD_INIT_FUNC_TRACE();
2007
2008         if (hw->mac.type == ixgbe_mac_82598EB) {
2009                 /* No queue level support */
2010                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2011                 return;
2012         }
2013
2014         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2015         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2016         ctrl &= ~IXGBE_RXDCTL_VME;
2017         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018
2019         /* record those setting for HW strip per queue */
2020         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2021 }
2022
2023 static void
2024 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2025 {
2026         struct ixgbe_hw *hw =
2027                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t ctrl;
2029
2030         PMD_INIT_FUNC_TRACE();
2031
2032         if (hw->mac.type == ixgbe_mac_82598EB) {
2033                 /* No queue level supported */
2034                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2035                 return;
2036         }
2037
2038         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2040         ctrl |= IXGBE_RXDCTL_VME;
2041         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2042
2043         /* record those setting for HW strip per queue */
2044         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2045 }
2046
2047 static void
2048 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2049 {
2050         struct ixgbe_hw *hw =
2051                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         uint32_t ctrl;
2053
2054         PMD_INIT_FUNC_TRACE();
2055
2056         /* DMATXCTRL: Geric Double VLAN Disable */
2057         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2058         ctrl &= ~IXGBE_DMATXCTL_GDV;
2059         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2060
2061         /* CTRL_EXT: Global Double VLAN Disable */
2062         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2063         ctrl &= ~IXGBE_EXTENDED_VLAN;
2064         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2065
2066 }
2067
2068 static void
2069 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2070 {
2071         struct ixgbe_hw *hw =
2072                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         uint32_t ctrl;
2074
2075         PMD_INIT_FUNC_TRACE();
2076
2077         /* DMATXCTRL: Geric Double VLAN Enable */
2078         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2079         ctrl |= IXGBE_DMATXCTL_GDV;
2080         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2081
2082         /* CTRL_EXT: Global Double VLAN Enable */
2083         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2084         ctrl |= IXGBE_EXTENDED_VLAN;
2085         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2086
2087         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2088         if (hw->mac.type == ixgbe_mac_X550 ||
2089             hw->mac.type == ixgbe_mac_X550EM_x ||
2090             hw->mac.type == ixgbe_mac_X550EM_a) {
2091                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2092                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2093                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2094         }
2095
2096         /*
2097          * VET EXT field in the EXVET register = 0x8100 by default
2098          * So no need to change. Same to VT field of DMATXCTL register
2099          */
2100 }
2101
2102 void
2103 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2104 {
2105         struct ixgbe_hw *hw =
2106                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2108         uint32_t ctrl;
2109         uint16_t i;
2110         struct ixgbe_rx_queue *rxq;
2111         bool on;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         if (hw->mac.type == ixgbe_mac_82598EB) {
2116                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2117                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2118                         ctrl |= IXGBE_VLNCTRL_VME;
2119                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2120                 } else {
2121                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2122                         ctrl &= ~IXGBE_VLNCTRL_VME;
2123                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2124                 }
2125         } else {
2126                 /*
2127                  * Other 10G NIC, the VLAN strip can be setup
2128                  * per queue in RXDCTL
2129                  */
2130                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2131                         rxq = dev->data->rx_queues[i];
2132                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2133                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2134                                 ctrl |= IXGBE_RXDCTL_VME;
2135                                 on = TRUE;
2136                         } else {
2137                                 ctrl &= ~IXGBE_RXDCTL_VME;
2138                                 on = FALSE;
2139                         }
2140                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2141
2142                         /* record those setting for HW strip per queue */
2143                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2144                 }
2145         }
2146 }
2147
2148 static void
2149 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2150 {
2151         uint16_t i;
2152         struct rte_eth_rxmode *rxmode;
2153         struct ixgbe_rx_queue *rxq;
2154
2155         if (mask & ETH_VLAN_STRIP_MASK) {
2156                 rxmode = &dev->data->dev_conf.rxmode;
2157                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2158                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                                 rxq = dev->data->rx_queues[i];
2160                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2161                         }
2162                 else
2163                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2164                                 rxq = dev->data->rx_queues[i];
2165                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2166                         }
2167         }
2168 }
2169
2170 static int
2171 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2172 {
2173         struct rte_eth_rxmode *rxmode;
2174         rxmode = &dev->data->dev_conf.rxmode;
2175
2176         if (mask & ETH_VLAN_STRIP_MASK) {
2177                 ixgbe_vlan_hw_strip_config(dev);
2178         }
2179
2180         if (mask & ETH_VLAN_FILTER_MASK) {
2181                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2182                         ixgbe_vlan_hw_filter_enable(dev);
2183                 else
2184                         ixgbe_vlan_hw_filter_disable(dev);
2185         }
2186
2187         if (mask & ETH_VLAN_EXTEND_MASK) {
2188                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2189                         ixgbe_vlan_hw_extend_enable(dev);
2190                 else
2191                         ixgbe_vlan_hw_extend_disable(dev);
2192         }
2193
2194         return 0;
2195 }
2196
2197 static int
2198 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2199 {
2200         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2201
2202         ixgbe_vlan_offload_config(dev, mask);
2203
2204         return 0;
2205 }
2206
2207 static void
2208 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw =
2211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2213         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2214
2215         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2216         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2217 }
2218
2219 static int
2220 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2221 {
2222         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2223
2224         switch (nb_rx_q) {
2225         case 1:
2226         case 2:
2227                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2228                 break;
2229         case 4:
2230                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2231                 break;
2232         default:
2233                 return -EINVAL;
2234         }
2235
2236         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2237                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2238         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2239                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2240         return 0;
2241 }
2242
2243 static int
2244 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2245 {
2246         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2249         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2250
2251         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2252                 /* check multi-queue mode */
2253                 switch (dev_conf->rxmode.mq_mode) {
2254                 case ETH_MQ_RX_VMDQ_DCB:
2255                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2256                         break;
2257                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2258                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2259                         PMD_INIT_LOG(ERR, "SRIOV active,"
2260                                         " unsupported mq_mode rx %d.",
2261                                         dev_conf->rxmode.mq_mode);
2262                         return -EINVAL;
2263                 case ETH_MQ_RX_RSS:
2264                 case ETH_MQ_RX_VMDQ_RSS:
2265                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2266                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2267                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2268                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2269                                                 " invalid queue number"
2270                                                 " for VMDQ RSS, allowed"
2271                                                 " value are 1, 2 or 4.");
2272                                         return -EINVAL;
2273                                 }
2274                         break;
2275                 case ETH_MQ_RX_VMDQ_ONLY:
2276                 case ETH_MQ_RX_NONE:
2277                         /* if nothing mq mode configure, use default scheme */
2278                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2279                         break;
2280                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2281                         /* SRIOV only works in VMDq enable mode */
2282                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2283                                         " wrong mq_mode rx %d.",
2284                                         dev_conf->rxmode.mq_mode);
2285                         return -EINVAL;
2286                 }
2287
2288                 switch (dev_conf->txmode.mq_mode) {
2289                 case ETH_MQ_TX_VMDQ_DCB:
2290                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2291                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2292                         break;
2293                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2294                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2295                         break;
2296                 }
2297
2298                 /* check valid queue number */
2299                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2300                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2301                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2302                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2303                                         " must be less than or equal to %d.",
2304                                         nb_rx_q, nb_tx_q,
2305                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2306                         return -EINVAL;
2307                 }
2308         } else {
2309                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2310                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2311                                           " not supported.");
2312                         return -EINVAL;
2313                 }
2314                 /* check configuration for vmdb+dcb mode */
2315                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2316                         const struct rte_eth_vmdq_dcb_conf *conf;
2317
2318                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2319                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2320                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2321                                 return -EINVAL;
2322                         }
2323                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2324                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2325                                conf->nb_queue_pools == ETH_32_POOLS)) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2327                                                 " nb_queue_pools must be %d or %d.",
2328                                                 ETH_16_POOLS, ETH_32_POOLS);
2329                                 return -EINVAL;
2330                         }
2331                 }
2332                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2333                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2334
2335                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2336                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2337                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2338                                 return -EINVAL;
2339                         }
2340                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2341                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2342                                conf->nb_queue_pools == ETH_32_POOLS)) {
2343                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2344                                                 " nb_queue_pools != %d and"
2345                                                 " nb_queue_pools != %d.",
2346                                                 ETH_16_POOLS, ETH_32_POOLS);
2347                                 return -EINVAL;
2348                         }
2349                 }
2350
2351                 /* For DCB mode check our configuration before we go further */
2352                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2353                         const struct rte_eth_dcb_rx_conf *conf;
2354
2355                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2356                         if (!(conf->nb_tcs == ETH_4_TCS ||
2357                                conf->nb_tcs == ETH_8_TCS)) {
2358                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2359                                                 " and nb_tcs != %d.",
2360                                                 ETH_4_TCS, ETH_8_TCS);
2361                                 return -EINVAL;
2362                         }
2363                 }
2364
2365                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2366                         const struct rte_eth_dcb_tx_conf *conf;
2367
2368                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2369                         if (!(conf->nb_tcs == ETH_4_TCS ||
2370                                conf->nb_tcs == ETH_8_TCS)) {
2371                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372                                                 " and nb_tcs != %d.",
2373                                                 ETH_4_TCS, ETH_8_TCS);
2374                                 return -EINVAL;
2375                         }
2376                 }
2377
2378                 /*
2379                  * When DCB/VT is off, maximum number of queues changes,
2380                  * except for 82598EB, which remains constant.
2381                  */
2382                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2383                                 hw->mac.type != ixgbe_mac_82598EB) {
2384                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2385                                 PMD_INIT_LOG(ERR,
2386                                              "Neither VT nor DCB are enabled, "
2387                                              "nb_tx_q > %d.",
2388                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2389                                 return -EINVAL;
2390                         }
2391                 }
2392         }
2393         return 0;
2394 }
2395
2396 static int
2397 ixgbe_dev_configure(struct rte_eth_dev *dev)
2398 {
2399         struct ixgbe_interrupt *intr =
2400                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2401         struct ixgbe_adapter *adapter = dev->data->dev_private;
2402         int ret;
2403
2404         PMD_INIT_FUNC_TRACE();
2405
2406         dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2407
2408         /* multipe queue mode checking */
2409         ret  = ixgbe_check_mq_mode(dev);
2410         if (ret != 0) {
2411                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2412                             ret);
2413                 return ret;
2414         }
2415
2416         /* set flag to update link status after init */
2417         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2418
2419         /*
2420          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2421          * allocation or vector Rx preconditions we will reset it.
2422          */
2423         adapter->rx_bulk_alloc_allowed = true;
2424         adapter->rx_vec_allowed = true;
2425
2426         return 0;
2427 }
2428
2429 static void
2430 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2431 {
2432         struct ixgbe_hw *hw =
2433                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2434         struct ixgbe_interrupt *intr =
2435                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2436         uint32_t gpie;
2437
2438         /* only set up it on X550EM_X */
2439         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2440                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2441                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2442                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2443                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2444                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2445         }
2446 }
2447
2448 int
2449 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2450                         uint16_t tx_rate, uint64_t q_msk)
2451 {
2452         struct ixgbe_hw *hw;
2453         struct ixgbe_vf_info *vfinfo;
2454         struct rte_eth_link link;
2455         uint8_t  nb_q_per_pool;
2456         uint32_t queue_stride;
2457         uint32_t queue_idx, idx = 0, vf_idx;
2458         uint32_t queue_end;
2459         uint16_t total_rate = 0;
2460         struct rte_pci_device *pci_dev;
2461         int ret;
2462
2463         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2464         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2465         if (ret < 0)
2466                 return ret;
2467
2468         if (vf >= pci_dev->max_vfs)
2469                 return -EINVAL;
2470
2471         if (tx_rate > link.link_speed)
2472                 return -EINVAL;
2473
2474         if (q_msk == 0)
2475                 return 0;
2476
2477         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2478         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2479         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2480         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2481         queue_idx = vf * queue_stride;
2482         queue_end = queue_idx + nb_q_per_pool - 1;
2483         if (queue_end >= hw->mac.max_tx_queues)
2484                 return -EINVAL;
2485
2486         if (vfinfo) {
2487                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2488                         if (vf_idx == vf)
2489                                 continue;
2490                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2491                                 idx++)
2492                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2493                 }
2494         } else {
2495                 return -EINVAL;
2496         }
2497
2498         /* Store tx_rate for this vf. */
2499         for (idx = 0; idx < nb_q_per_pool; idx++) {
2500                 if (((uint64_t)0x1 << idx) & q_msk) {
2501                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2502                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2503                         total_rate += tx_rate;
2504                 }
2505         }
2506
2507         if (total_rate > dev->data->dev_link.link_speed) {
2508                 /* Reset stored TX rate of the VF if it causes exceed
2509                  * link speed.
2510                  */
2511                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2512                 return -EINVAL;
2513         }
2514
2515         /* Set RTTBCNRC of each queue/pool for vf X  */
2516         for (; queue_idx <= queue_end; queue_idx++) {
2517                 if (0x1 & q_msk)
2518                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2519                 q_msk = q_msk >> 1;
2520         }
2521
2522         return 0;
2523 }
2524
2525 /*
2526  * Configure device link speed and setup link.
2527  * It returns 0 on success.
2528  */
2529 static int
2530 ixgbe_dev_start(struct rte_eth_dev *dev)
2531 {
2532         struct ixgbe_hw *hw =
2533                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534         struct ixgbe_vf_info *vfinfo =
2535                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2536         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2537         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2538         uint32_t intr_vector = 0;
2539         int err, link_up = 0, negotiate = 0;
2540         uint32_t speed = 0;
2541         uint32_t allowed_speeds = 0;
2542         int mask = 0;
2543         int status;
2544         uint16_t vf, idx;
2545         uint32_t *link_speeds;
2546         struct ixgbe_tm_conf *tm_conf =
2547                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2548         struct ixgbe_macsec_setting *macsec_ctrl =
2549                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2550
2551         PMD_INIT_FUNC_TRACE();
2552
2553         /* IXGBE devices don't support:
2554         *    - half duplex (checked afterwards for valid speeds)
2555         *    - fixed speed: TODO implement
2556         */
2557         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2558                 PMD_INIT_LOG(ERR,
2559                 "Invalid link_speeds for port %u, fix speed not supported",
2560                                 dev->data->port_id);
2561                 return -EINVAL;
2562         }
2563
2564         /* Stop the link setup handler before resetting the HW. */
2565         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2566
2567         /* disable uio/vfio intr/eventfd mapping */
2568         rte_intr_disable(intr_handle);
2569
2570         /* stop adapter */
2571         hw->adapter_stopped = 0;
2572         ixgbe_stop_adapter(hw);
2573
2574         /* reinitialize adapter
2575          * this calls reset and start
2576          */
2577         status = ixgbe_pf_reset_hw(hw);
2578         if (status != 0)
2579                 return -1;
2580         hw->mac.ops.start_hw(hw);
2581         hw->mac.get_link_status = true;
2582
2583         /* configure PF module if SRIOV enabled */
2584         ixgbe_pf_host_configure(dev);
2585
2586         ixgbe_dev_phy_intr_setup(dev);
2587
2588         /* check and configure queue intr-vector mapping */
2589         if ((rte_intr_cap_multiple(intr_handle) ||
2590              !RTE_ETH_DEV_SRIOV(dev).active) &&
2591             dev->data->dev_conf.intr_conf.rxq != 0) {
2592                 intr_vector = dev->data->nb_rx_queues;
2593                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2594                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2595                                         IXGBE_MAX_INTR_QUEUE_NUM);
2596                         return -ENOTSUP;
2597                 }
2598                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2599                         return -1;
2600         }
2601
2602         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2603                 intr_handle->intr_vec =
2604                         rte_zmalloc("intr_vec",
2605                                     dev->data->nb_rx_queues * sizeof(int), 0);
2606                 if (intr_handle->intr_vec == NULL) {
2607                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2608                                      " intr_vec", dev->data->nb_rx_queues);
2609                         return -ENOMEM;
2610                 }
2611         }
2612
2613         /* confiugre msix for sleep until rx interrupt */
2614         ixgbe_configure_msix(dev);
2615
2616         /* initialize transmission unit */
2617         ixgbe_dev_tx_init(dev);
2618
2619         /* This can fail when allocating mbufs for descriptor rings */
2620         err = ixgbe_dev_rx_init(dev);
2621         if (err) {
2622                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2623                 goto error;
2624         }
2625
2626         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2627                 ETH_VLAN_EXTEND_MASK;
2628         err = ixgbe_vlan_offload_config(dev, mask);
2629         if (err) {
2630                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2631                 goto error;
2632         }
2633
2634         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2635                 /* Enable vlan filtering for VMDq */
2636                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2637         }
2638
2639         /* Configure DCB hw */
2640         ixgbe_configure_dcb(dev);
2641
2642         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2643                 err = ixgbe_fdir_configure(dev);
2644                 if (err)
2645                         goto error;
2646         }
2647
2648         /* Restore vf rate limit */
2649         if (vfinfo != NULL) {
2650                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2651                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2652                                 if (vfinfo[vf].tx_rate[idx] != 0)
2653                                         ixgbe_set_vf_rate_limit(
2654                                                 dev, vf,
2655                                                 vfinfo[vf].tx_rate[idx],
2656                                                 1 << idx);
2657         }
2658
2659         ixgbe_restore_statistics_mapping(dev);
2660
2661         err = ixgbe_dev_rxtx_start(dev);
2662         if (err < 0) {
2663                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2664                 goto error;
2665         }
2666
2667         /* Skip link setup if loopback mode is enabled. */
2668         if (dev->data->dev_conf.lpbk_mode != 0) {
2669                 err = ixgbe_check_supported_loopback_mode(dev);
2670                 if (err < 0) {
2671                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2672                         goto error;
2673                 } else {
2674                         goto skip_link_setup;
2675                 }
2676         }
2677
2678         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2679                 err = hw->mac.ops.setup_sfp(hw);
2680                 if (err)
2681                         goto error;
2682         }
2683
2684         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2685                 /* Turn on the copper */
2686                 ixgbe_set_phy_power(hw, true);
2687         } else {
2688                 /* Turn on the laser */
2689                 ixgbe_enable_tx_laser(hw);
2690         }
2691
2692         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2693         if (err)
2694                 goto error;
2695         dev->data->dev_link.link_status = link_up;
2696
2697         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2698         if (err)
2699                 goto error;
2700
2701         switch (hw->mac.type) {
2702         case ixgbe_mac_X550:
2703         case ixgbe_mac_X550EM_x:
2704         case ixgbe_mac_X550EM_a:
2705                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2706                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2707                         ETH_LINK_SPEED_10G;
2708                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2709                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2710                         allowed_speeds = ETH_LINK_SPEED_10M |
2711                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2712                 break;
2713         default:
2714                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2715                         ETH_LINK_SPEED_10G;
2716         }
2717
2718         link_speeds = &dev->data->dev_conf.link_speeds;
2719         if (*link_speeds & ~allowed_speeds) {
2720                 PMD_INIT_LOG(ERR, "Invalid link setting");
2721                 goto error;
2722         }
2723
2724         speed = 0x0;
2725         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2726                 switch (hw->mac.type) {
2727                 case ixgbe_mac_82598EB:
2728                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2729                         break;
2730                 case ixgbe_mac_82599EB:
2731                 case ixgbe_mac_X540:
2732                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2733                         break;
2734                 case ixgbe_mac_X550:
2735                 case ixgbe_mac_X550EM_x:
2736                 case ixgbe_mac_X550EM_a:
2737                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2738                         break;
2739                 default:
2740                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2741                 }
2742         } else {
2743                 if (*link_speeds & ETH_LINK_SPEED_10G)
2744                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2745                 if (*link_speeds & ETH_LINK_SPEED_5G)
2746                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2747                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2748                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2749                 if (*link_speeds & ETH_LINK_SPEED_1G)
2750                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2751                 if (*link_speeds & ETH_LINK_SPEED_100M)
2752                         speed |= IXGBE_LINK_SPEED_100_FULL;
2753                 if (*link_speeds & ETH_LINK_SPEED_10M)
2754                         speed |= IXGBE_LINK_SPEED_10_FULL;
2755         }
2756
2757         err = ixgbe_setup_link(hw, speed, link_up);
2758         if (err)
2759                 goto error;
2760
2761 skip_link_setup:
2762
2763         if (rte_intr_allow_others(intr_handle)) {
2764                 /* check if lsc interrupt is enabled */
2765                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2766                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2767                 else
2768                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2769                 ixgbe_dev_macsec_interrupt_setup(dev);
2770         } else {
2771                 rte_intr_callback_unregister(intr_handle,
2772                                              ixgbe_dev_interrupt_handler, dev);
2773                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2774                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2775                                      " no intr multiplex");
2776         }
2777
2778         /* check if rxq interrupt is enabled */
2779         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2780             rte_intr_dp_is_en(intr_handle))
2781                 ixgbe_dev_rxq_interrupt_setup(dev);
2782
2783         /* enable uio/vfio intr/eventfd mapping */
2784         rte_intr_enable(intr_handle);
2785
2786         /* resume enabled intr since hw reset */
2787         ixgbe_enable_intr(dev);
2788         ixgbe_l2_tunnel_conf(dev);
2789         ixgbe_filter_restore(dev);
2790
2791         if (tm_conf->root && !tm_conf->committed)
2792                 PMD_DRV_LOG(WARNING,
2793                             "please call hierarchy_commit() "
2794                             "before starting the port");
2795
2796         /*
2797          * Update link status right before return, because it may
2798          * start link configuration process in a separate thread.
2799          */
2800         ixgbe_dev_link_update(dev, 0);
2801
2802         /* setup the macsec ctrl register */
2803         ixgbe_dev_macsec_register_enable(dev, macsec_ctrl);
2804
2805         return 0;
2806
2807 error:
2808         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2809         ixgbe_dev_clear_queues(dev);
2810         return -EIO;
2811 }
2812
2813 /*
2814  * Stop device: disable rx and tx functions to allow for reconfiguring.
2815  */
2816 static void
2817 ixgbe_dev_stop(struct rte_eth_dev *dev)
2818 {
2819         struct rte_eth_link link;
2820         struct ixgbe_adapter *adapter = dev->data->dev_private;
2821         struct ixgbe_hw *hw =
2822                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2823         struct ixgbe_vf_info *vfinfo =
2824                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2825         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2826         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2827         int vf;
2828         struct ixgbe_tm_conf *tm_conf =
2829                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2830
2831         if (hw->adapter_stopped)
2832                 return;
2833
2834         PMD_INIT_FUNC_TRACE();
2835
2836         /* disable mecsec register */
2837         ixgbe_dev_macsec_register_disable(dev);
2838
2839         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2840
2841         /* disable interrupts */
2842         ixgbe_disable_intr(hw);
2843
2844         /* reset the NIC */
2845         ixgbe_pf_reset_hw(hw);
2846         hw->adapter_stopped = 0;
2847
2848         /* stop adapter */
2849         ixgbe_stop_adapter(hw);
2850
2851         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2852                 vfinfo[vf].clear_to_send = false;
2853
2854         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2855                 /* Turn off the copper */
2856                 ixgbe_set_phy_power(hw, false);
2857         } else {
2858                 /* Turn off the laser */
2859                 ixgbe_disable_tx_laser(hw);
2860         }
2861
2862         ixgbe_dev_clear_queues(dev);
2863
2864         /* Clear stored conf */
2865         dev->data->scattered_rx = 0;
2866         dev->data->lro = 0;
2867
2868         /* Clear recorded link status */
2869         memset(&link, 0, sizeof(link));
2870         rte_eth_linkstatus_set(dev, &link);
2871
2872         if (!rte_intr_allow_others(intr_handle))
2873                 /* resume to the default handler */
2874                 rte_intr_callback_register(intr_handle,
2875                                            ixgbe_dev_interrupt_handler,
2876                                            (void *)dev);
2877
2878         /* Clean datapath event and queue/vec mapping */
2879         rte_intr_efd_disable(intr_handle);
2880         if (intr_handle->intr_vec != NULL) {
2881                 rte_free(intr_handle->intr_vec);
2882                 intr_handle->intr_vec = NULL;
2883         }
2884
2885         /* reset hierarchy commit */
2886         tm_conf->committed = false;
2887
2888         adapter->rss_reta_updated = 0;
2889
2890         hw->adapter_stopped = true;
2891 }
2892
2893 /*
2894  * Set device link up: enable tx.
2895  */
2896 static int
2897 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2898 {
2899         struct ixgbe_hw *hw =
2900                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901         if (hw->mac.type == ixgbe_mac_82599EB) {
2902 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2903                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2904                         /* Not suported in bypass mode */
2905                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2906                                      "by device id 0x%x", hw->device_id);
2907                         return -ENOTSUP;
2908                 }
2909 #endif
2910         }
2911
2912         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2913                 /* Turn on the copper */
2914                 ixgbe_set_phy_power(hw, true);
2915         } else {
2916                 /* Turn on the laser */
2917                 ixgbe_enable_tx_laser(hw);
2918                 ixgbe_dev_link_update(dev, 0);
2919         }
2920
2921         return 0;
2922 }
2923
2924 /*
2925  * Set device link down: disable tx.
2926  */
2927 static int
2928 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2929 {
2930         struct ixgbe_hw *hw =
2931                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2932         if (hw->mac.type == ixgbe_mac_82599EB) {
2933 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2934                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2935                         /* Not suported in bypass mode */
2936                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2937                                      "by device id 0x%x", hw->device_id);
2938                         return -ENOTSUP;
2939                 }
2940 #endif
2941         }
2942
2943         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2944                 /* Turn off the copper */
2945                 ixgbe_set_phy_power(hw, false);
2946         } else {
2947                 /* Turn off the laser */
2948                 ixgbe_disable_tx_laser(hw);
2949                 ixgbe_dev_link_update(dev, 0);
2950         }
2951
2952         return 0;
2953 }
2954
2955 /*
2956  * Reset and stop device.
2957  */
2958 static void
2959 ixgbe_dev_close(struct rte_eth_dev *dev)
2960 {
2961         struct ixgbe_hw *hw =
2962                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2963         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2964         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2965         int retries = 0;
2966         int ret;
2967
2968         PMD_INIT_FUNC_TRACE();
2969
2970         ixgbe_pf_reset_hw(hw);
2971
2972         ixgbe_dev_stop(dev);
2973
2974         ixgbe_dev_free_queues(dev);
2975
2976         ixgbe_disable_pcie_master(hw);
2977
2978         /* reprogram the RAR[0] in case user changed it. */
2979         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2980
2981         dev->dev_ops = NULL;
2982         dev->rx_pkt_burst = NULL;
2983         dev->tx_pkt_burst = NULL;
2984
2985         /* Unlock any pending hardware semaphore */
2986         ixgbe_swfw_lock_reset(hw);
2987
2988         /* disable uio intr before callback unregister */
2989         rte_intr_disable(intr_handle);
2990
2991         do {
2992                 ret = rte_intr_callback_unregister(intr_handle,
2993                                 ixgbe_dev_interrupt_handler, dev);
2994                 if (ret >= 0 || ret == -ENOENT) {
2995                         break;
2996                 } else if (ret != -EAGAIN) {
2997                         PMD_INIT_LOG(ERR,
2998                                 "intr callback unregister failed: %d",
2999                                 ret);
3000                 }
3001                 rte_delay_ms(100);
3002         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3003
3004         /* cancel the delay handler before remove dev */
3005         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3006
3007         /* uninitialize PF if max_vfs not zero */
3008         ixgbe_pf_host_uninit(dev);
3009
3010         /* remove all the fdir filters & hash */
3011         ixgbe_fdir_filter_uninit(dev);
3012
3013         /* remove all the L2 tunnel filters & hash */
3014         ixgbe_l2_tn_filter_uninit(dev);
3015
3016         /* Remove all ntuple filters of the device */
3017         ixgbe_ntuple_filter_uninit(dev);
3018
3019         /* clear all the filters list */
3020         ixgbe_filterlist_flush();
3021
3022         /* Remove all Traffic Manager configuration */
3023         ixgbe_tm_conf_uninit(dev);
3024
3025 #ifdef RTE_LIBRTE_SECURITY
3026         rte_free(dev->security_ctx);
3027 #endif
3028
3029 }
3030
3031 /*
3032  * Reset PF device.
3033  */
3034 static int
3035 ixgbe_dev_reset(struct rte_eth_dev *dev)
3036 {
3037         int ret;
3038
3039         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3040          * its VF to make them align with it. The detailed notification
3041          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3042          * To avoid unexpected behavior in VF, currently reset of PF with
3043          * SR-IOV activation is not supported. It might be supported later.
3044          */
3045         if (dev->data->sriov.active)
3046                 return -ENOTSUP;
3047
3048         ret = eth_ixgbe_dev_uninit(dev);
3049         if (ret)
3050                 return ret;
3051
3052         ret = eth_ixgbe_dev_init(dev, NULL);
3053
3054         return ret;
3055 }
3056
3057 static void
3058 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3059                            struct ixgbe_hw_stats *hw_stats,
3060                            struct ixgbe_macsec_stats *macsec_stats,
3061                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3062                            uint64_t *total_qprc, uint64_t *total_qprdc)
3063 {
3064         uint32_t bprc, lxon, lxoff, total;
3065         uint32_t delta_gprc = 0;
3066         unsigned i;
3067         /* Workaround for RX byte count not including CRC bytes when CRC
3068          * strip is enabled. CRC bytes are removed from counters when crc_strip
3069          * is disabled.
3070          */
3071         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3072                         IXGBE_HLREG0_RXCRCSTRP);
3073
3074         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3075         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3076         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3077         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3078
3079         for (i = 0; i < 8; i++) {
3080                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3081
3082                 /* global total per queue */
3083                 hw_stats->mpc[i] += mp;
3084                 /* Running comprehensive total for stats display */
3085                 *total_missed_rx += hw_stats->mpc[i];
3086                 if (hw->mac.type == ixgbe_mac_82598EB) {
3087                         hw_stats->rnbc[i] +=
3088                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3089                         hw_stats->pxonrxc[i] +=
3090                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3091                         hw_stats->pxoffrxc[i] +=
3092                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3093                 } else {
3094                         hw_stats->pxonrxc[i] +=
3095                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3096                         hw_stats->pxoffrxc[i] +=
3097                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3098                         hw_stats->pxon2offc[i] +=
3099                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3100                 }
3101                 hw_stats->pxontxc[i] +=
3102                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3103                 hw_stats->pxofftxc[i] +=
3104                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3105         }
3106         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3107                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3108                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3109                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3110
3111                 delta_gprc += delta_qprc;
3112
3113                 hw_stats->qprc[i] += delta_qprc;
3114                 hw_stats->qptc[i] += delta_qptc;
3115
3116                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3117                 hw_stats->qbrc[i] +=
3118                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3119                 if (crc_strip == 0)
3120                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3121
3122                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3123                 hw_stats->qbtc[i] +=
3124                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3125
3126                 hw_stats->qprdc[i] += delta_qprdc;
3127                 *total_qprdc += hw_stats->qprdc[i];
3128
3129                 *total_qprc += hw_stats->qprc[i];
3130                 *total_qbrc += hw_stats->qbrc[i];
3131         }
3132         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3133         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3134         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3135
3136         /*
3137          * An errata states that gprc actually counts good + missed packets:
3138          * Workaround to set gprc to summated queue packet receives
3139          */
3140         hw_stats->gprc = *total_qprc;
3141
3142         if (hw->mac.type != ixgbe_mac_82598EB) {
3143                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3144                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3145                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3146                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3147                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3148                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3149                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3150                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3151         } else {
3152                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3153                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3154                 /* 82598 only has a counter in the high register */
3155                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3156                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3157                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3158         }
3159         uint64_t old_tpr = hw_stats->tpr;
3160
3161         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3162         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3163
3164         if (crc_strip == 0)
3165                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3166
3167         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3168         hw_stats->gptc += delta_gptc;
3169         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3170         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3171
3172         /*
3173          * Workaround: mprc hardware is incorrectly counting
3174          * broadcasts, so for now we subtract those.
3175          */
3176         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3177         hw_stats->bprc += bprc;
3178         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3179         if (hw->mac.type == ixgbe_mac_82598EB)
3180                 hw_stats->mprc -= bprc;
3181
3182         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3183         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3184         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3185         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3186         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3187         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3188
3189         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3190         hw_stats->lxontxc += lxon;
3191         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3192         hw_stats->lxofftxc += lxoff;
3193         total = lxon + lxoff;
3194
3195         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3196         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3197         hw_stats->gptc -= total;
3198         hw_stats->mptc -= total;
3199         hw_stats->ptc64 -= total;
3200         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3201
3202         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3203         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3204         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3205         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3206         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3207         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3208         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3209         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3210         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3211         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3212         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3213         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3214         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3215         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3216         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3217         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3218         /* Only read FCOE on 82599 */
3219         if (hw->mac.type != ixgbe_mac_82598EB) {
3220                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3221                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3222                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3223                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3224                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3225         }
3226
3227         /* Flow Director Stats registers */
3228         if (hw->mac.type != ixgbe_mac_82598EB) {
3229                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3230                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3231                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3232                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3233                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3234                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3235                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3236                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3237                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3238                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3239         }
3240         /* MACsec Stats registers */
3241         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3242         macsec_stats->out_pkts_encrypted +=
3243                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3244         macsec_stats->out_pkts_protected +=
3245                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3246         macsec_stats->out_octets_encrypted +=
3247                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3248         macsec_stats->out_octets_protected +=
3249                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3250         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3251         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3252         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3253         macsec_stats->in_pkts_unknownsci +=
3254                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3255         macsec_stats->in_octets_decrypted +=
3256                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3257         macsec_stats->in_octets_validated +=
3258                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3259         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3260         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3261         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3262         for (i = 0; i < 2; i++) {
3263                 macsec_stats->in_pkts_ok +=
3264                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3265                 macsec_stats->in_pkts_invalid +=
3266                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3267                 macsec_stats->in_pkts_notvalid +=
3268                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3269         }
3270         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3271         macsec_stats->in_pkts_notusingsa +=
3272                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3273 }
3274
3275 /*
3276  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3277  */
3278 static int
3279 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3280 {
3281         struct ixgbe_hw *hw =
3282                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3283         struct ixgbe_hw_stats *hw_stats =
3284                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3285         struct ixgbe_macsec_stats *macsec_stats =
3286                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3287                                 dev->data->dev_private);
3288         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3289         unsigned i;
3290
3291         total_missed_rx = 0;
3292         total_qbrc = 0;
3293         total_qprc = 0;
3294         total_qprdc = 0;
3295
3296         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3297                         &total_qbrc, &total_qprc, &total_qprdc);
3298
3299         if (stats == NULL)
3300                 return -EINVAL;
3301
3302         /* Fill out the rte_eth_stats statistics structure */
3303         stats->ipackets = total_qprc;
3304         stats->ibytes = total_qbrc;
3305         stats->opackets = hw_stats->gptc;
3306         stats->obytes = hw_stats->gotc;
3307
3308         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3309                 stats->q_ipackets[i] = hw_stats->qprc[i];
3310                 stats->q_opackets[i] = hw_stats->qptc[i];
3311                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3312                 stats->q_obytes[i] = hw_stats->qbtc[i];
3313                 stats->q_errors[i] = hw_stats->qprdc[i];
3314         }
3315
3316         /* Rx Errors */
3317         stats->imissed  = total_missed_rx;
3318         stats->ierrors  = hw_stats->crcerrs +
3319                           hw_stats->mspdc +
3320                           hw_stats->rlec +
3321                           hw_stats->ruc +
3322                           hw_stats->roc +
3323                           hw_stats->illerrc +
3324                           hw_stats->errbc +
3325                           hw_stats->rfc +
3326                           hw_stats->fccrc +
3327                           hw_stats->fclast;
3328
3329         /* Tx Errors */
3330         stats->oerrors  = 0;
3331         return 0;
3332 }
3333
3334 static int
3335 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3336 {
3337         struct ixgbe_hw_stats *stats =
3338                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3339
3340         /* HW registers are cleared on read */
3341         ixgbe_dev_stats_get(dev, NULL);
3342
3343         /* Reset software totals */
3344         memset(stats, 0, sizeof(*stats));
3345
3346         return 0;
3347 }
3348
3349 /* This function calculates the number of xstats based on the current config */
3350 static unsigned
3351 ixgbe_xstats_calc_num(void) {
3352         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3353                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3354                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3355 }
3356
3357 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3358         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3359 {
3360         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3361         unsigned stat, i, count;
3362
3363         if (xstats_names != NULL) {
3364                 count = 0;
3365
3366                 /* Note: limit >= cnt_stats checked upstream
3367                  * in rte_eth_xstats_names()
3368                  */
3369
3370                 /* Extended stats from ixgbe_hw_stats */
3371                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3372                         strlcpy(xstats_names[count].name,
3373                                 rte_ixgbe_stats_strings[i].name,
3374                                 sizeof(xstats_names[count].name));
3375                         count++;
3376                 }
3377
3378                 /* MACsec Stats */
3379                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3380                         strlcpy(xstats_names[count].name,
3381                                 rte_ixgbe_macsec_strings[i].name,
3382                                 sizeof(xstats_names[count].name));
3383                         count++;
3384                 }
3385
3386                 /* RX Priority Stats */
3387                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3388                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3389                                 snprintf(xstats_names[count].name,
3390                                         sizeof(xstats_names[count].name),
3391                                         "rx_priority%u_%s", i,
3392                                         rte_ixgbe_rxq_strings[stat].name);
3393                                 count++;
3394                         }
3395                 }
3396
3397                 /* TX Priority Stats */
3398                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3399                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3400                                 snprintf(xstats_names[count].name,
3401                                         sizeof(xstats_names[count].name),
3402                                         "tx_priority%u_%s", i,
3403                                         rte_ixgbe_txq_strings[stat].name);
3404                                 count++;
3405                         }
3406                 }
3407         }
3408         return cnt_stats;
3409 }
3410
3411 static int ixgbe_dev_xstats_get_names_by_id(
3412         struct rte_eth_dev *dev,
3413         struct rte_eth_xstat_name *xstats_names,
3414         const uint64_t *ids,
3415         unsigned int limit)
3416 {
3417         if (!ids) {
3418                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3419                 unsigned int stat, i, count;
3420
3421                 if (xstats_names != NULL) {
3422                         count = 0;
3423
3424                         /* Note: limit >= cnt_stats checked upstream
3425                          * in rte_eth_xstats_names()
3426                          */
3427
3428                         /* Extended stats from ixgbe_hw_stats */
3429                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3430                                 strlcpy(xstats_names[count].name,
3431                                         rte_ixgbe_stats_strings[i].name,
3432                                         sizeof(xstats_names[count].name));
3433                                 count++;
3434                         }
3435
3436                         /* MACsec Stats */
3437                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3438                                 strlcpy(xstats_names[count].name,
3439                                         rte_ixgbe_macsec_strings[i].name,
3440                                         sizeof(xstats_names[count].name));
3441                                 count++;
3442                         }
3443
3444                         /* RX Priority Stats */
3445                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3446                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3447                                         snprintf(xstats_names[count].name,
3448                                             sizeof(xstats_names[count].name),
3449                                             "rx_priority%u_%s", i,
3450                                             rte_ixgbe_rxq_strings[stat].name);
3451                                         count++;
3452                                 }
3453                         }
3454
3455                         /* TX Priority Stats */
3456                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3457                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3458                                         snprintf(xstats_names[count].name,
3459                                             sizeof(xstats_names[count].name),
3460                                             "tx_priority%u_%s", i,
3461                                             rte_ixgbe_txq_strings[stat].name);
3462                                         count++;
3463                                 }
3464                         }
3465                 }
3466                 return cnt_stats;
3467         }
3468
3469         uint16_t i;
3470         uint16_t size = ixgbe_xstats_calc_num();
3471         struct rte_eth_xstat_name xstats_names_copy[size];
3472
3473         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3474                         size);
3475
3476         for (i = 0; i < limit; i++) {
3477                 if (ids[i] >= size) {
3478                         PMD_INIT_LOG(ERR, "id value isn't valid");
3479                         return -1;
3480                 }
3481                 strcpy(xstats_names[i].name,
3482                                 xstats_names_copy[ids[i]].name);
3483         }
3484         return limit;
3485 }
3486
3487 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3488         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3489 {
3490         unsigned i;
3491
3492         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3493                 return -ENOMEM;
3494
3495         if (xstats_names != NULL)
3496                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3497                         strlcpy(xstats_names[i].name,
3498                                 rte_ixgbevf_stats_strings[i].name,
3499                                 sizeof(xstats_names[i].name));
3500         return IXGBEVF_NB_XSTATS;
3501 }
3502
3503 static int
3504 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3505                                          unsigned n)
3506 {
3507         struct ixgbe_hw *hw =
3508                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509         struct ixgbe_hw_stats *hw_stats =
3510                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3511         struct ixgbe_macsec_stats *macsec_stats =
3512                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3513                                 dev->data->dev_private);
3514         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3515         unsigned i, stat, count = 0;
3516
3517         count = ixgbe_xstats_calc_num();
3518
3519         if (n < count)
3520                 return count;
3521
3522         total_missed_rx = 0;
3523         total_qbrc = 0;
3524         total_qprc = 0;
3525         total_qprdc = 0;
3526
3527         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3528                         &total_qbrc, &total_qprc, &total_qprdc);
3529
3530         /* If this is a reset xstats is NULL, and we have cleared the
3531          * registers by reading them.
3532          */
3533         if (!xstats)
3534                 return 0;
3535
3536         /* Extended stats from ixgbe_hw_stats */
3537         count = 0;
3538         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3539                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3540                                 rte_ixgbe_stats_strings[i].offset);
3541                 xstats[count].id = count;
3542                 count++;
3543         }
3544
3545         /* MACsec Stats */
3546         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3547                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3548                                 rte_ixgbe_macsec_strings[i].offset);
3549                 xstats[count].id = count;
3550                 count++;
3551         }
3552
3553         /* RX Priority Stats */
3554         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3555                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3556                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3557                                         rte_ixgbe_rxq_strings[stat].offset +
3558                                         (sizeof(uint64_t) * i));
3559                         xstats[count].id = count;
3560                         count++;
3561                 }
3562         }
3563
3564         /* TX Priority Stats */
3565         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3566                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3567                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3568                                         rte_ixgbe_txq_strings[stat].offset +
3569                                         (sizeof(uint64_t) * i));
3570                         xstats[count].id = count;
3571                         count++;
3572                 }
3573         }
3574         return count;
3575 }
3576
3577 static int
3578 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3579                 uint64_t *values, unsigned int n)
3580 {
3581         if (!ids) {
3582                 struct ixgbe_hw *hw =
3583                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584                 struct ixgbe_hw_stats *hw_stats =
3585                                 IXGBE_DEV_PRIVATE_TO_STATS(
3586                                                 dev->data->dev_private);
3587                 struct ixgbe_macsec_stats *macsec_stats =
3588                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3589                                         dev->data->dev_private);
3590                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3591                 unsigned int i, stat, count = 0;
3592
3593                 count = ixgbe_xstats_calc_num();
3594
3595                 if (!ids && n < count)
3596                         return count;
3597
3598                 total_missed_rx = 0;
3599                 total_qbrc = 0;
3600                 total_qprc = 0;
3601                 total_qprdc = 0;
3602
3603                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3604                                 &total_missed_rx, &total_qbrc, &total_qprc,
3605                                 &total_qprdc);
3606
3607                 /* If this is a reset xstats is NULL, and we have cleared the
3608                  * registers by reading them.
3609                  */
3610                 if (!ids && !values)
3611                         return 0;
3612
3613                 /* Extended stats from ixgbe_hw_stats */
3614                 count = 0;
3615                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3616                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3617                                         rte_ixgbe_stats_strings[i].offset);
3618                         count++;
3619                 }
3620
3621                 /* MACsec Stats */
3622                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3623                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3624                                         rte_ixgbe_macsec_strings[i].offset);
3625                         count++;
3626                 }
3627
3628                 /* RX Priority Stats */
3629                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3630                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3631                                 values[count] =
3632                                         *(uint64_t *)(((char *)hw_stats) +
3633                                         rte_ixgbe_rxq_strings[stat].offset +
3634                                         (sizeof(uint64_t) * i));
3635                                 count++;
3636                         }
3637                 }
3638
3639                 /* TX Priority Stats */
3640                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3641                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3642                                 values[count] =
3643                                         *(uint64_t *)(((char *)hw_stats) +
3644                                         rte_ixgbe_txq_strings[stat].offset +
3645                                         (sizeof(uint64_t) * i));
3646                                 count++;
3647                         }
3648                 }
3649                 return count;
3650         }
3651
3652         uint16_t i;
3653         uint16_t size = ixgbe_xstats_calc_num();
3654         uint64_t values_copy[size];
3655
3656         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3657
3658         for (i = 0; i < n; i++) {
3659                 if (ids[i] >= size) {
3660                         PMD_INIT_LOG(ERR, "id value isn't valid");
3661                         return -1;
3662                 }
3663                 values[i] = values_copy[ids[i]];
3664         }
3665         return n;
3666 }
3667
3668 static int
3669 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3670 {
3671         struct ixgbe_hw_stats *stats =
3672                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3673         struct ixgbe_macsec_stats *macsec_stats =
3674                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3675                                 dev->data->dev_private);
3676
3677         unsigned count = ixgbe_xstats_calc_num();
3678
3679         /* HW registers are cleared on read */
3680         ixgbe_dev_xstats_get(dev, NULL, count);
3681
3682         /* Reset software totals */
3683         memset(stats, 0, sizeof(*stats));
3684         memset(macsec_stats, 0, sizeof(*macsec_stats));
3685
3686         return 0;
3687 }
3688
3689 static void
3690 ixgbevf_update_stats(struct rte_eth_dev *dev)
3691 {
3692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3693         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3694                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3695
3696         /* Good Rx packet, include VF loopback */
3697         UPDATE_VF_STAT(IXGBE_VFGPRC,
3698             hw_stats->last_vfgprc, hw_stats->vfgprc);
3699
3700         /* Good Rx octets, include VF loopback */
3701         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3702             hw_stats->last_vfgorc, hw_stats->vfgorc);
3703
3704         /* Good Tx packet, include VF loopback */
3705         UPDATE_VF_STAT(IXGBE_VFGPTC,
3706             hw_stats->last_vfgptc, hw_stats->vfgptc);
3707
3708         /* Good Tx octets, include VF loopback */
3709         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3710             hw_stats->last_vfgotc, hw_stats->vfgotc);
3711
3712         /* Rx Multicst Packet */
3713         UPDATE_VF_STAT(IXGBE_VFMPRC,
3714             hw_stats->last_vfmprc, hw_stats->vfmprc);
3715 }
3716
3717 static int
3718 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3719                        unsigned n)
3720 {
3721         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3722                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3723         unsigned i;
3724
3725         if (n < IXGBEVF_NB_XSTATS)
3726                 return IXGBEVF_NB_XSTATS;
3727
3728         ixgbevf_update_stats(dev);
3729
3730         if (!xstats)
3731                 return 0;
3732
3733         /* Extended stats */
3734         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3735                 xstats[i].id = i;
3736                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3737                         rte_ixgbevf_stats_strings[i].offset);
3738         }
3739
3740         return IXGBEVF_NB_XSTATS;
3741 }
3742
3743 static int
3744 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3745 {
3746         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3747                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3748
3749         ixgbevf_update_stats(dev);
3750
3751         if (stats == NULL)
3752                 return -EINVAL;
3753
3754         stats->ipackets = hw_stats->vfgprc;
3755         stats->ibytes = hw_stats->vfgorc;
3756         stats->opackets = hw_stats->vfgptc;
3757         stats->obytes = hw_stats->vfgotc;
3758         return 0;
3759 }
3760
3761 static int
3762 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3763 {
3764         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3765                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3766
3767         /* Sync HW register to the last stats */
3768         ixgbevf_dev_stats_get(dev, NULL);
3769
3770         /* reset HW current stats*/
3771         hw_stats->vfgprc = 0;
3772         hw_stats->vfgorc = 0;
3773         hw_stats->vfgptc = 0;
3774         hw_stats->vfgotc = 0;
3775
3776         return 0;
3777 }
3778
3779 static int
3780 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3781 {
3782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3783         u16 eeprom_verh, eeprom_verl;
3784         u32 etrack_id;
3785         int ret;
3786
3787         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3788         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3789
3790         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3791         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3792
3793         ret += 1; /* add the size of '\0' */
3794         if (fw_size < (u32)ret)
3795                 return ret;
3796         else
3797                 return 0;
3798 }
3799
3800 static int
3801 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3802 {
3803         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3805         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3806
3807         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3808         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3809         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3810                 /*
3811                  * When DCB/VT is off, maximum number of queues changes,
3812                  * except for 82598EB, which remains constant.
3813                  */
3814                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3815                                 hw->mac.type != ixgbe_mac_82598EB)
3816                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3817         }
3818         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3819         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3820         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3821         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3822         dev_info->max_vfs = pci_dev->max_vfs;
3823         if (hw->mac.type == ixgbe_mac_82598EB)
3824                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3825         else
3826                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3827         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3828         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3829         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3830         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3831         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3832                                      dev_info->rx_queue_offload_capa);
3833         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3834         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3835
3836         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3837                 .rx_thresh = {
3838                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3839                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3840                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3841                 },
3842                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3843                 .rx_drop_en = 0,
3844                 .offloads = 0,
3845         };
3846
3847         dev_info->default_txconf = (struct rte_eth_txconf) {
3848                 .tx_thresh = {
3849                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3850                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3851                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3852                 },
3853                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3854                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3855                 .offloads = 0,
3856         };
3857
3858         dev_info->rx_desc_lim = rx_desc_lim;
3859         dev_info->tx_desc_lim = tx_desc_lim;
3860
3861         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3862         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3863         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3864
3865         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3866         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3867                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3868                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3869                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3870
3871         if (hw->mac.type == ixgbe_mac_X540 ||
3872             hw->mac.type == ixgbe_mac_X540_vf ||
3873             hw->mac.type == ixgbe_mac_X550 ||
3874             hw->mac.type == ixgbe_mac_X550_vf) {
3875                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3876         }
3877         if (hw->mac.type == ixgbe_mac_X550) {
3878                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3879                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3880         }
3881
3882         /* Driver-preferred Rx/Tx parameters */
3883         dev_info->default_rxportconf.burst_size = 32;
3884         dev_info->default_txportconf.burst_size = 32;
3885         dev_info->default_rxportconf.nb_queues = 1;
3886         dev_info->default_txportconf.nb_queues = 1;
3887         dev_info->default_rxportconf.ring_size = 256;
3888         dev_info->default_txportconf.ring_size = 256;
3889
3890         return 0;
3891 }
3892
3893 static const uint32_t *
3894 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3895 {
3896         static const uint32_t ptypes[] = {
3897                 /* For non-vec functions,
3898                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3899                  * for vec functions,
3900                  * refers to _recv_raw_pkts_vec().
3901                  */
3902                 RTE_PTYPE_L2_ETHER,
3903                 RTE_PTYPE_L3_IPV4,
3904                 RTE_PTYPE_L3_IPV4_EXT,
3905                 RTE_PTYPE_L3_IPV6,
3906                 RTE_PTYPE_L3_IPV6_EXT,
3907                 RTE_PTYPE_L4_SCTP,
3908                 RTE_PTYPE_L4_TCP,
3909                 RTE_PTYPE_L4_UDP,
3910                 RTE_PTYPE_TUNNEL_IP,
3911                 RTE_PTYPE_INNER_L3_IPV6,
3912                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3913                 RTE_PTYPE_INNER_L4_TCP,
3914                 RTE_PTYPE_INNER_L4_UDP,
3915                 RTE_PTYPE_UNKNOWN
3916         };
3917
3918         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3919             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3920             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3921             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3922                 return ptypes;
3923
3924 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3925         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3926             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3927                 return ptypes;
3928 #endif
3929         return NULL;
3930 }
3931
3932 static int
3933 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3934                      struct rte_eth_dev_info *dev_info)
3935 {
3936         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938
3939         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3940         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3941         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3942         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3943         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3944         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3945         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3946         dev_info->max_vfs = pci_dev->max_vfs;
3947         if (hw->mac.type == ixgbe_mac_82598EB)
3948                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3949         else
3950                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3951         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3952         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3953                                      dev_info->rx_queue_offload_capa);
3954         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3955         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3956         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3957         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3958         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3959
3960         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3961                 .rx_thresh = {
3962                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3963                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3964                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3965                 },
3966                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3967                 .rx_drop_en = 0,
3968                 .offloads = 0,
3969         };
3970
3971         dev_info->default_txconf = (struct rte_eth_txconf) {
3972                 .tx_thresh = {
3973                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3974                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3975                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3976                 },
3977                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3978                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3979                 .offloads = 0,
3980         };
3981
3982         dev_info->rx_desc_lim = rx_desc_lim;
3983         dev_info->tx_desc_lim = tx_desc_lim;
3984
3985         return 0;
3986 }
3987
3988 static int
3989 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3990                    int *link_up, int wait_to_complete)
3991 {
3992         struct ixgbe_adapter *adapter = container_of(hw,
3993                                                      struct ixgbe_adapter, hw);
3994         struct ixgbe_mbx_info *mbx = &hw->mbx;
3995         struct ixgbe_mac_info *mac = &hw->mac;
3996         uint32_t links_reg, in_msg;
3997         int ret_val = 0;
3998
3999         /* If we were hit with a reset drop the link */
4000         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4001                 mac->get_link_status = true;
4002
4003         if (!mac->get_link_status)
4004                 goto out;
4005
4006         /* if link status is down no point in checking to see if pf is up */
4007         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4008         if (!(links_reg & IXGBE_LINKS_UP))
4009                 goto out;
4010
4011         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4012          * before the link status is correct
4013          */
4014         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4015                 int i;
4016
4017                 for (i = 0; i < 5; i++) {
4018                         rte_delay_us(100);
4019                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4020
4021                         if (!(links_reg & IXGBE_LINKS_UP))
4022                                 goto out;
4023                 }
4024         }
4025
4026         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4027         case IXGBE_LINKS_SPEED_10G_82599:
4028                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4029                 if (hw->mac.type >= ixgbe_mac_X550) {
4030                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4031                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4032                 }
4033                 break;
4034         case IXGBE_LINKS_SPEED_1G_82599:
4035                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4036                 break;
4037         case IXGBE_LINKS_SPEED_100_82599:
4038                 *speed = IXGBE_LINK_SPEED_100_FULL;
4039                 if (hw->mac.type == ixgbe_mac_X550) {
4040                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4041                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4042                 }
4043                 break;
4044         case IXGBE_LINKS_SPEED_10_X550EM_A:
4045                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4046                 /* Since Reserved in older MAC's */
4047                 if (hw->mac.type >= ixgbe_mac_X550)
4048                         *speed = IXGBE_LINK_SPEED_10_FULL;
4049                 break;
4050         default:
4051                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4052         }
4053
4054         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4055                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4056                         mac->get_link_status = true;
4057                 else
4058                         mac->get_link_status = false;
4059
4060                 goto out;
4061         }
4062
4063         /* if the read failed it could just be a mailbox collision, best wait
4064          * until we are called again and don't report an error
4065          */
4066         if (mbx->ops.read(hw, &in_msg, 1, 0))
4067                 goto out;
4068
4069         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4070                 /* msg is not CTS and is NACK we must have lost CTS status */
4071                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4072                         mac->get_link_status = false;
4073                 goto out;
4074         }
4075
4076         /* the pf is talking, if we timed out in the past we reinit */
4077         if (!mbx->timeout) {
4078                 ret_val = -1;
4079                 goto out;
4080         }
4081
4082         /* if we passed all the tests above then the link is up and we no
4083          * longer need to check for link
4084          */
4085         mac->get_link_status = false;
4086
4087 out:
4088         *link_up = !mac->get_link_status;
4089         return ret_val;
4090 }
4091
4092 static void
4093 ixgbe_dev_setup_link_alarm_handler(void *param)
4094 {
4095         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097         struct ixgbe_interrupt *intr =
4098                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4099         u32 speed;
4100         bool autoneg = false;
4101
4102         speed = hw->phy.autoneg_advertised;
4103         if (!speed)
4104                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4105
4106         ixgbe_setup_link(hw, speed, true);
4107
4108         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4109 }
4110
4111 /* return 0 means link status changed, -1 means not changed */
4112 int
4113 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4114                             int wait_to_complete, int vf)
4115 {
4116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4117         struct rte_eth_link link;
4118         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4119         struct ixgbe_interrupt *intr =
4120                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4121         int link_up;
4122         int diag;
4123         int wait = 1;
4124         u32 esdp_reg;
4125
4126         memset(&link, 0, sizeof(link));
4127         link.link_status = ETH_LINK_DOWN;
4128         link.link_speed = ETH_SPEED_NUM_NONE;
4129         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4130         link.link_autoneg = ETH_LINK_AUTONEG;
4131
4132         hw->mac.get_link_status = true;
4133
4134         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4135                 return rte_eth_linkstatus_set(dev, &link);
4136
4137         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4138         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4139                 wait = 0;
4140
4141         if (vf)
4142                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4143         else
4144                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4145
4146         if (diag != 0) {
4147                 link.link_speed = ETH_SPEED_NUM_100M;
4148                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4149                 return rte_eth_linkstatus_set(dev, &link);
4150         }
4151
4152         esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4153         if ((esdp_reg & IXGBE_ESDP_SDP3))
4154                 link_up = 0;
4155
4156         if (link_up == 0) {
4157                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4158                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4159                         rte_eal_alarm_set(10,
4160                                 ixgbe_dev_setup_link_alarm_handler, dev);
4161                 }
4162                 return rte_eth_linkstatus_set(dev, &link);
4163         }
4164
4165         link.link_status = ETH_LINK_UP;
4166         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4167
4168         switch (link_speed) {
4169         default:
4170         case IXGBE_LINK_SPEED_UNKNOWN:
4171                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4172                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4173                         link.link_speed = ETH_SPEED_NUM_10M;
4174                 else
4175                         link.link_speed = ETH_SPEED_NUM_100M;
4176                 break;
4177
4178         case IXGBE_LINK_SPEED_100_FULL:
4179                 link.link_speed = ETH_SPEED_NUM_100M;
4180                 break;
4181
4182         case IXGBE_LINK_SPEED_1GB_FULL:
4183                 link.link_speed = ETH_SPEED_NUM_1G;
4184                 break;
4185
4186         case IXGBE_LINK_SPEED_2_5GB_FULL:
4187                 link.link_speed = ETH_SPEED_NUM_2_5G;
4188                 break;
4189
4190         case IXGBE_LINK_SPEED_5GB_FULL:
4191                 link.link_speed = ETH_SPEED_NUM_5G;
4192                 break;
4193
4194         case IXGBE_LINK_SPEED_10GB_FULL:
4195                 link.link_speed = ETH_SPEED_NUM_10G;
4196                 break;
4197         }
4198
4199         return rte_eth_linkstatus_set(dev, &link);
4200 }
4201
4202 static int
4203 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4204 {
4205         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4206 }
4207
4208 static int
4209 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4210 {
4211         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4212 }
4213
4214 static int
4215 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4216 {
4217         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4218         uint32_t fctrl;
4219
4220         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4221         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4222         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4223
4224         return 0;
4225 }
4226
4227 static int
4228 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4229 {
4230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4231         uint32_t fctrl;
4232
4233         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4234         fctrl &= (~IXGBE_FCTRL_UPE);
4235         if (dev->data->all_multicast == 1)
4236                 fctrl |= IXGBE_FCTRL_MPE;
4237         else
4238                 fctrl &= (~IXGBE_FCTRL_MPE);
4239         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4240
4241         return 0;
4242 }
4243
4244 static int
4245 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4246 {
4247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4248         uint32_t fctrl;
4249
4250         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4251         fctrl |= IXGBE_FCTRL_MPE;
4252         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4253
4254         return 0;
4255 }
4256
4257 static int
4258 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4259 {
4260         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4261         uint32_t fctrl;
4262
4263         if (dev->data->promiscuous == 1)
4264                 return 0; /* must remain in all_multicast mode */
4265
4266         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4267         fctrl &= (~IXGBE_FCTRL_MPE);
4268         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4269
4270         return 0;
4271 }
4272
4273 /**
4274  * It clears the interrupt causes and enables the interrupt.
4275  * It will be called once only during nic initialized.
4276  *
4277  * @param dev
4278  *  Pointer to struct rte_eth_dev.
4279  * @param on
4280  *  Enable or Disable.
4281  *
4282  * @return
4283  *  - On success, zero.
4284  *  - On failure, a negative value.
4285  */
4286 static int
4287 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4288 {
4289         struct ixgbe_interrupt *intr =
4290                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4291
4292         ixgbe_dev_link_status_print(dev);
4293         if (on)
4294                 intr->mask |= IXGBE_EICR_LSC;
4295         else
4296                 intr->mask &= ~IXGBE_EICR_LSC;
4297
4298         return 0;
4299 }
4300
4301 /**
4302  * It clears the interrupt causes and enables the interrupt.
4303  * It will be called once only during nic initialized.
4304  *
4305  * @param dev
4306  *  Pointer to struct rte_eth_dev.
4307  *
4308  * @return
4309  *  - On success, zero.
4310  *  - On failure, a negative value.
4311  */
4312 static int
4313 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4314 {
4315         struct ixgbe_interrupt *intr =
4316                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4317
4318         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4319
4320         return 0;
4321 }
4322
4323 /**
4324  * It clears the interrupt causes and enables the interrupt.
4325  * It will be called once only during nic initialized.
4326  *
4327  * @param dev
4328  *  Pointer to struct rte_eth_dev.
4329  *
4330  * @return
4331  *  - On success, zero.
4332  *  - On failure, a negative value.
4333  */
4334 static int
4335 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4336 {
4337         struct ixgbe_interrupt *intr =
4338                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4339
4340         intr->mask |= IXGBE_EICR_LINKSEC;
4341
4342         return 0;
4343 }
4344
4345 /*
4346  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4347  *
4348  * @param dev
4349  *  Pointer to struct rte_eth_dev.
4350  *
4351  * @return
4352  *  - On success, zero.
4353  *  - On failure, a negative value.
4354  */
4355 static int
4356 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4357 {
4358         uint32_t eicr;
4359         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360         struct ixgbe_interrupt *intr =
4361                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4362
4363         /* clear all cause mask */
4364         ixgbe_disable_intr(hw);
4365
4366         /* read-on-clear nic registers here */
4367         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4368         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4369
4370         intr->flags = 0;
4371
4372         /* set flag for async link update */
4373         if (eicr & IXGBE_EICR_LSC)
4374                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4375
4376         if (eicr & IXGBE_EICR_MAILBOX)
4377                 intr->flags |= IXGBE_FLAG_MAILBOX;
4378
4379         if (eicr & IXGBE_EICR_LINKSEC)
4380                 intr->flags |= IXGBE_FLAG_MACSEC;
4381
4382         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4383             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4384             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4385                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4386
4387         return 0;
4388 }
4389
4390 /**
4391  * It gets and then prints the link status.
4392  *
4393  * @param dev
4394  *  Pointer to struct rte_eth_dev.
4395  *
4396  * @return
4397  *  - On success, zero.
4398  *  - On failure, a negative value.
4399  */
4400 static void
4401 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4402 {
4403         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4404         struct rte_eth_link link;
4405
4406         rte_eth_linkstatus_get(dev, &link);
4407
4408         if (link.link_status) {
4409                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4410                                         (int)(dev->data->port_id),
4411                                         (unsigned)link.link_speed,
4412                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4413                                         "full-duplex" : "half-duplex");
4414         } else {
4415                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4416                                 (int)(dev->data->port_id));
4417         }
4418         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4419                                 pci_dev->addr.domain,
4420                                 pci_dev->addr.bus,
4421                                 pci_dev->addr.devid,
4422                                 pci_dev->addr.function);
4423 }
4424
4425 /*
4426  * It executes link_update after knowing an interrupt occurred.
4427  *
4428  * @param dev
4429  *  Pointer to struct rte_eth_dev.
4430  *
4431  * @return
4432  *  - On success, zero.
4433  *  - On failure, a negative value.
4434  */
4435 static int
4436 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4437 {
4438         struct ixgbe_interrupt *intr =
4439                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4440         int64_t timeout;
4441         struct ixgbe_hw *hw =
4442                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4443
4444         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4445
4446         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4447                 ixgbe_pf_mbx_process(dev);
4448                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4449         }
4450
4451         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4452                 ixgbe_handle_lasi(hw);
4453                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4454         }
4455
4456         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4457                 struct rte_eth_link link;
4458
4459                 /* get the link status before link update, for predicting later */
4460                 rte_eth_linkstatus_get(dev, &link);
4461
4462                 ixgbe_dev_link_update(dev, 0);
4463
4464                 /* likely to up */
4465                 if (!link.link_status)
4466                         /* handle it 1 sec later, wait it being stable */
4467                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4468                 /* likely to down */
4469                 else
4470                         /* handle it 4 sec later, wait it being stable */
4471                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4472
4473                 ixgbe_dev_link_status_print(dev);
4474                 if (rte_eal_alarm_set(timeout * 1000,
4475                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4476                         PMD_DRV_LOG(ERR, "Error setting alarm");
4477                 else {
4478                         /* remember original mask */
4479                         intr->mask_original = intr->mask;
4480                         /* only disable lsc interrupt */
4481                         intr->mask &= ~IXGBE_EIMS_LSC;
4482                 }
4483         }
4484
4485         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4486         ixgbe_enable_intr(dev);
4487
4488         return 0;
4489 }
4490
4491 /**
4492  * Interrupt handler which shall be registered for alarm callback for delayed
4493  * handling specific interrupt to wait for the stable nic state. As the
4494  * NIC interrupt state is not stable for ixgbe after link is just down,
4495  * it needs to wait 4 seconds to get the stable status.
4496  *
4497  * @param handle
4498  *  Pointer to interrupt handle.
4499  * @param param
4500  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4501  *
4502  * @return
4503  *  void
4504  */
4505 static void
4506 ixgbe_dev_interrupt_delayed_handler(void *param)
4507 {
4508         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4509         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4510         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4511         struct ixgbe_interrupt *intr =
4512                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4513         struct ixgbe_hw *hw =
4514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4515         uint32_t eicr;
4516
4517         ixgbe_disable_intr(hw);
4518
4519         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4520         if (eicr & IXGBE_EICR_MAILBOX)
4521                 ixgbe_pf_mbx_process(dev);
4522
4523         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4524                 ixgbe_handle_lasi(hw);
4525                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4526         }
4527
4528         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4529                 ixgbe_dev_link_update(dev, 0);
4530                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4531                 ixgbe_dev_link_status_print(dev);
4532                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4533                                               NULL);
4534         }
4535
4536         if (intr->flags & IXGBE_FLAG_MACSEC) {
4537                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4538                                               NULL);
4539                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4540         }
4541
4542         /* restore original mask */
4543         intr->mask = intr->mask_original;
4544         intr->mask_original = 0;
4545
4546         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4547         ixgbe_enable_intr(dev);
4548         rte_intr_ack(intr_handle);
4549 }
4550
4551 /**
4552  * Interrupt handler triggered by NIC  for handling
4553  * specific interrupt.
4554  *
4555  * @param handle
4556  *  Pointer to interrupt handle.
4557  * @param param
4558  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4559  *
4560  * @return
4561  *  void
4562  */
4563 static void
4564 ixgbe_dev_interrupt_handler(void *param)
4565 {
4566         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4567
4568         ixgbe_dev_interrupt_get_status(dev);
4569         ixgbe_dev_interrupt_action(dev);
4570 }
4571
4572 static int
4573 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4574 {
4575         struct ixgbe_hw *hw;
4576
4577         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4578         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4579 }
4580
4581 static int
4582 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4583 {
4584         struct ixgbe_hw *hw;
4585
4586         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4587         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4588 }
4589
4590 static int
4591 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4592 {
4593         struct ixgbe_hw *hw;
4594         uint32_t mflcn_reg;
4595         uint32_t fccfg_reg;
4596         int rx_pause;
4597         int tx_pause;
4598
4599         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4600
4601         fc_conf->pause_time = hw->fc.pause_time;
4602         fc_conf->high_water = hw->fc.high_water[0];
4603         fc_conf->low_water = hw->fc.low_water[0];
4604         fc_conf->send_xon = hw->fc.send_xon;
4605         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4606
4607         /*
4608          * Return rx_pause status according to actual setting of
4609          * MFLCN register.
4610          */
4611         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4612         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4613                 rx_pause = 1;
4614         else
4615                 rx_pause = 0;
4616
4617         /*
4618          * Return tx_pause status according to actual setting of
4619          * FCCFG register.
4620          */
4621         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4622         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4623                 tx_pause = 1;
4624         else
4625                 tx_pause = 0;
4626
4627         if (rx_pause && tx_pause)
4628                 fc_conf->mode = RTE_FC_FULL;
4629         else if (rx_pause)
4630                 fc_conf->mode = RTE_FC_RX_PAUSE;
4631         else if (tx_pause)
4632                 fc_conf->mode = RTE_FC_TX_PAUSE;
4633         else
4634                 fc_conf->mode = RTE_FC_NONE;
4635
4636         return 0;
4637 }
4638
4639 static int
4640 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4641 {
4642         struct ixgbe_hw *hw;
4643         int err;
4644         uint32_t rx_buf_size;
4645         uint32_t max_high_water;
4646         uint32_t mflcn;
4647         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4648                 ixgbe_fc_none,
4649                 ixgbe_fc_rx_pause,
4650                 ixgbe_fc_tx_pause,
4651                 ixgbe_fc_full
4652         };
4653
4654         PMD_INIT_FUNC_TRACE();
4655
4656         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4657         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4658         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4659
4660         /*
4661          * At least reserve one Ethernet frame for watermark
4662          * high_water/low_water in kilo bytes for ixgbe
4663          */
4664         max_high_water = (rx_buf_size -
4665                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4666         if ((fc_conf->high_water > max_high_water) ||
4667                 (fc_conf->high_water < fc_conf->low_water)) {
4668                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4669                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4670                 return -EINVAL;
4671         }
4672
4673         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4674         hw->fc.pause_time     = fc_conf->pause_time;
4675         hw->fc.high_water[0]  = fc_conf->high_water;
4676         hw->fc.low_water[0]   = fc_conf->low_water;
4677         hw->fc.send_xon       = fc_conf->send_xon;
4678         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4679
4680         err = ixgbe_fc_enable(hw);
4681
4682         /* Not negotiated is not an error case */
4683         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4684
4685                 /* check if we want to forward MAC frames - driver doesn't have native
4686                  * capability to do that, so we'll write the registers ourselves */
4687
4688                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4689
4690                 /* set or clear MFLCN.PMCF bit depending on configuration */
4691                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4692                         mflcn |= IXGBE_MFLCN_PMCF;
4693                 else
4694                         mflcn &= ~IXGBE_MFLCN_PMCF;
4695
4696                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4697                 IXGBE_WRITE_FLUSH(hw);
4698
4699                 return 0;
4700         }
4701
4702         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4703         return -EIO;
4704 }
4705
4706 /**
4707  *  ixgbe_pfc_enable_generic - Enable flow control
4708  *  @hw: pointer to hardware structure
4709  *  @tc_num: traffic class number
4710  *  Enable flow control according to the current settings.
4711  */
4712 static int
4713 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4714 {
4715         int ret_val = 0;
4716         uint32_t mflcn_reg, fccfg_reg;
4717         uint32_t reg;
4718         uint32_t fcrtl, fcrth;
4719         uint8_t i;
4720         uint8_t nb_rx_en;
4721
4722         /* Validate the water mark configuration */
4723         if (!hw->fc.pause_time) {
4724                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4725                 goto out;
4726         }
4727
4728         /* Low water mark of zero causes XOFF floods */
4729         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4730                  /* High/Low water can not be 0 */
4731                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4732                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4733                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4734                         goto out;
4735                 }
4736
4737                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4738                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4739                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4740                         goto out;
4741                 }
4742         }
4743         /* Negotiate the fc mode to use */
4744         ixgbe_fc_autoneg(hw);
4745
4746         /* Disable any previous flow control settings */
4747         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4748         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4749
4750         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4751         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4752
4753         switch (hw->fc.current_mode) {
4754         case ixgbe_fc_none:
4755                 /*
4756                  * If the count of enabled RX Priority Flow control >1,
4757                  * and the TX pause can not be disabled
4758                  */
4759                 nb_rx_en = 0;
4760                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4761                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4762                         if (reg & IXGBE_FCRTH_FCEN)
4763                                 nb_rx_en++;
4764                 }
4765                 if (nb_rx_en > 1)
4766                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4767                 break;
4768         case ixgbe_fc_rx_pause:
4769                 /*
4770                  * Rx Flow control is enabled and Tx Flow control is
4771                  * disabled by software override. Since there really
4772                  * isn't a way to advertise that we are capable of RX
4773                  * Pause ONLY, we will advertise that we support both
4774                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4775                  * disable the adapter's ability to send PAUSE frames.
4776                  */
4777                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4778                 /*
4779                  * If the count of enabled RX Priority Flow control >1,
4780                  * and the TX pause can not be disabled
4781                  */
4782                 nb_rx_en = 0;
4783                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4784                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4785                         if (reg & IXGBE_FCRTH_FCEN)
4786                                 nb_rx_en++;
4787                 }
4788                 if (nb_rx_en > 1)
4789                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4790                 break;
4791         case ixgbe_fc_tx_pause:
4792                 /*
4793                  * Tx Flow control is enabled, and Rx Flow control is
4794                  * disabled by software override.
4795                  */
4796                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4797                 break;
4798         case ixgbe_fc_full:
4799                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4800                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4801                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4802                 break;
4803         default:
4804                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4805                 ret_val = IXGBE_ERR_CONFIG;
4806                 goto out;
4807         }
4808
4809         /* Set 802.3x based flow control settings. */
4810         mflcn_reg |= IXGBE_MFLCN_DPF;
4811         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4812         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4813
4814         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4815         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4816                 hw->fc.high_water[tc_num]) {
4817                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4818                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4819                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4820         } else {
4821                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4822                 /*
4823                  * In order to prevent Tx hangs when the internal Tx
4824                  * switch is enabled we must set the high water mark
4825                  * to the maximum FCRTH value.  This allows the Tx
4826                  * switch to function even under heavy Rx workloads.
4827                  */
4828                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4829         }
4830         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4831
4832         /* Configure pause time (2 TCs per register) */
4833         reg = hw->fc.pause_time * 0x00010001;
4834         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4835                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4836
4837         /* Configure flow control refresh threshold value */
4838         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4839
4840 out:
4841         return ret_val;
4842 }
4843
4844 static int
4845 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4846 {
4847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4849
4850         if (hw->mac.type != ixgbe_mac_82598EB) {
4851                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4852         }
4853         return ret_val;
4854 }
4855
4856 static int
4857 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4858 {
4859         int err;
4860         uint32_t rx_buf_size;
4861         uint32_t max_high_water;
4862         uint8_t tc_num;
4863         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4864         struct ixgbe_hw *hw =
4865                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4866         struct ixgbe_dcb_config *dcb_config =
4867                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4868
4869         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4870                 ixgbe_fc_none,
4871                 ixgbe_fc_rx_pause,
4872                 ixgbe_fc_tx_pause,
4873                 ixgbe_fc_full
4874         };
4875
4876         PMD_INIT_FUNC_TRACE();
4877
4878         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4879         tc_num = map[pfc_conf->priority];
4880         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4881         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4882         /*
4883          * At least reserve one Ethernet frame for watermark
4884          * high_water/low_water in kilo bytes for ixgbe
4885          */
4886         max_high_water = (rx_buf_size -
4887                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4888         if ((pfc_conf->fc.high_water > max_high_water) ||
4889             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4890                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4891                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4892                 return -EINVAL;
4893         }
4894
4895         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4896         hw->fc.pause_time = pfc_conf->fc.pause_time;
4897         hw->fc.send_xon = pfc_conf->fc.send_xon;
4898         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4899         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4900
4901         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4902
4903         /* Not negotiated is not an error case */
4904         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4905                 return 0;
4906
4907         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4908         return -EIO;
4909 }
4910
4911 static int
4912 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4913                           struct rte_eth_rss_reta_entry64 *reta_conf,
4914                           uint16_t reta_size)
4915 {
4916         uint16_t i, sp_reta_size;
4917         uint8_t j, mask;
4918         uint32_t reta, r;
4919         uint16_t idx, shift;
4920         struct ixgbe_adapter *adapter = dev->data->dev_private;
4921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4922         uint32_t reta_reg;
4923
4924         PMD_INIT_FUNC_TRACE();
4925
4926         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4927                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4928                         "NIC.");
4929                 return -ENOTSUP;
4930         }
4931
4932         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4933         if (reta_size != sp_reta_size) {
4934                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4935                         "(%d) doesn't match the number hardware can supported "
4936                         "(%d)", reta_size, sp_reta_size);
4937                 return -EINVAL;
4938         }
4939
4940         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4941                 idx = i / RTE_RETA_GROUP_SIZE;
4942                 shift = i % RTE_RETA_GROUP_SIZE;
4943                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4944                                                 IXGBE_4_BIT_MASK);
4945                 if (!mask)
4946                         continue;
4947                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4948                 if (mask == IXGBE_4_BIT_MASK)
4949                         r = 0;
4950                 else
4951                         r = IXGBE_READ_REG(hw, reta_reg);
4952                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4953                         if (mask & (0x1 << j))
4954                                 reta |= reta_conf[idx].reta[shift + j] <<
4955                                                         (CHAR_BIT * j);
4956                         else
4957                                 reta |= r & (IXGBE_8_BIT_MASK <<
4958                                                 (CHAR_BIT * j));
4959                 }
4960                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4961         }
4962         adapter->rss_reta_updated = 1;
4963
4964         return 0;
4965 }
4966
4967 static int
4968 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4969                          struct rte_eth_rss_reta_entry64 *reta_conf,
4970                          uint16_t reta_size)
4971 {
4972         uint16_t i, sp_reta_size;
4973         uint8_t j, mask;
4974         uint32_t reta;
4975         uint16_t idx, shift;
4976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4977         uint32_t reta_reg;
4978
4979         PMD_INIT_FUNC_TRACE();
4980         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4981         if (reta_size != sp_reta_size) {
4982                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4983                         "(%d) doesn't match the number hardware can supported "
4984                         "(%d)", reta_size, sp_reta_size);
4985                 return -EINVAL;
4986         }
4987
4988         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4989                 idx = i / RTE_RETA_GROUP_SIZE;
4990                 shift = i % RTE_RETA_GROUP_SIZE;
4991                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4992                                                 IXGBE_4_BIT_MASK);
4993                 if (!mask)
4994                         continue;
4995
4996                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4997                 reta = IXGBE_READ_REG(hw, reta_reg);
4998                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4999                         if (mask & (0x1 << j))
5000                                 reta_conf[idx].reta[shift + j] =
5001                                         ((reta >> (CHAR_BIT * j)) &
5002                                                 IXGBE_8_BIT_MASK);
5003                 }
5004         }
5005
5006         return 0;
5007 }
5008
5009 static int
5010 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5011                                 uint32_t index, uint32_t pool)
5012 {
5013         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5014         uint32_t enable_addr = 1;
5015
5016         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5017                              pool, enable_addr);
5018 }
5019
5020 static void
5021 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5022 {
5023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5024
5025         ixgbe_clear_rar(hw, index);
5026 }
5027
5028 static int
5029 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5030 {
5031         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5032
5033         ixgbe_remove_rar(dev, 0);
5034         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5035
5036         return 0;
5037 }
5038
5039 static bool
5040 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5041 {
5042         if (strcmp(dev->device->driver->name, drv->driver.name))
5043                 return false;
5044
5045         return true;
5046 }
5047
5048 bool
5049 is_ixgbe_supported(struct rte_eth_dev *dev)
5050 {
5051         return is_device_supported(dev, &rte_ixgbe_pmd);
5052 }
5053
5054 static int
5055 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5056 {
5057         uint32_t hlreg0;
5058         uint32_t maxfrs;
5059         struct ixgbe_hw *hw;
5060         struct rte_eth_dev_info dev_info;
5061         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5062         struct rte_eth_dev_data *dev_data = dev->data;
5063         int ret;
5064
5065         ret = ixgbe_dev_info_get(dev, &dev_info);
5066         if (ret != 0)
5067                 return ret;
5068
5069         /* check that mtu is within the allowed range */
5070         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5071                 return -EINVAL;
5072
5073         /* If device is started, refuse mtu that requires the support of
5074          * scattered packets when this feature has not been enabled before.
5075          */
5076         if (dev_data->dev_started && !dev_data->scattered_rx &&
5077             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5078              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5079                 PMD_INIT_LOG(ERR, "Stop port first.");
5080                 return -EINVAL;
5081         }
5082
5083         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5084         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5085
5086         /* switch to jumbo mode if needed */
5087         if (frame_size > RTE_ETHER_MAX_LEN) {
5088                 dev->data->dev_conf.rxmode.offloads |=
5089                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5090                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5091         } else {
5092                 dev->data->dev_conf.rxmode.offloads &=
5093                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5094                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5095         }
5096         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5097
5098         /* update max frame size */
5099         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5100
5101         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5102         maxfrs &= 0x0000FFFF;
5103         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5104         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5105
5106         return 0;
5107 }
5108
5109 /*
5110  * Virtual Function operations
5111  */
5112 static void
5113 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5114 {
5115         struct ixgbe_interrupt *intr =
5116                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5117         struct ixgbe_hw *hw =
5118                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5119
5120         PMD_INIT_FUNC_TRACE();
5121
5122         /* Clear interrupt mask to stop from interrupts being generated */
5123         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5124
5125         IXGBE_WRITE_FLUSH(hw);
5126
5127         /* Clear mask value. */
5128         intr->mask = 0;
5129 }
5130
5131 static void
5132 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5133 {
5134         struct ixgbe_interrupt *intr =
5135                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5136         struct ixgbe_hw *hw =
5137                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5138
5139         PMD_INIT_FUNC_TRACE();
5140
5141         /* VF enable interrupt autoclean */
5142         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5143         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5144         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5145
5146         IXGBE_WRITE_FLUSH(hw);
5147
5148         /* Save IXGBE_VTEIMS value to mask. */
5149         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5150 }
5151
5152 static int
5153 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5154 {
5155         struct rte_eth_conf *conf = &dev->data->dev_conf;
5156         struct ixgbe_adapter *adapter = dev->data->dev_private;
5157
5158         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5159                      dev->data->port_id);
5160
5161         dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5162
5163         /*
5164          * VF has no ability to enable/disable HW CRC
5165          * Keep the persistent behavior the same as Host PF
5166          */
5167 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5168         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5169                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5170                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5171         }
5172 #else
5173         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5174                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5175                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5176         }
5177 #endif
5178
5179         /*
5180          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5181          * allocation or vector Rx preconditions we will reset it.
5182          */
5183         adapter->rx_bulk_alloc_allowed = true;
5184         adapter->rx_vec_allowed = true;
5185
5186         return 0;
5187 }
5188
5189 static int
5190 ixgbevf_dev_start(struct rte_eth_dev *dev)
5191 {
5192         struct ixgbe_hw *hw =
5193                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194         uint32_t intr_vector = 0;
5195         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5196         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5197
5198         int err, mask = 0;
5199
5200         PMD_INIT_FUNC_TRACE();
5201
5202         /* Stop the link setup handler before resetting the HW. */
5203         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5204
5205         err = hw->mac.ops.reset_hw(hw);
5206         if (err) {
5207                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5208                 return err;
5209         }
5210         hw->mac.get_link_status = true;
5211
5212         /* negotiate mailbox API version to use with the PF. */
5213         ixgbevf_negotiate_api(hw);
5214
5215         ixgbevf_dev_tx_init(dev);
5216
5217         /* This can fail when allocating mbufs for descriptor rings */
5218         err = ixgbevf_dev_rx_init(dev);
5219         if (err) {
5220                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5221                 ixgbe_dev_clear_queues(dev);
5222                 return err;
5223         }
5224
5225         /* Set vfta */
5226         ixgbevf_set_vfta_all(dev, 1);
5227
5228         /* Set HW strip */
5229         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5230                 ETH_VLAN_EXTEND_MASK;
5231         err = ixgbevf_vlan_offload_config(dev, mask);
5232         if (err) {
5233                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5234                 ixgbe_dev_clear_queues(dev);
5235                 return err;
5236         }
5237
5238         ixgbevf_dev_rxtx_start(dev);
5239
5240         /* check and configure queue intr-vector mapping */
5241         if (rte_intr_cap_multiple(intr_handle) &&
5242             dev->data->dev_conf.intr_conf.rxq) {
5243                 /* According to datasheet, only vector 0/1/2 can be used,
5244                  * now only one vector is used for Rx queue
5245                  */
5246                 intr_vector = 1;
5247                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5248                         return -1;
5249         }
5250
5251         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5252                 intr_handle->intr_vec =
5253                         rte_zmalloc("intr_vec",
5254                                     dev->data->nb_rx_queues * sizeof(int), 0);
5255                 if (intr_handle->intr_vec == NULL) {
5256                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5257                                      " intr_vec", dev->data->nb_rx_queues);
5258                         return -ENOMEM;
5259                 }
5260         }
5261         ixgbevf_configure_msix(dev);
5262
5263         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5264          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5265          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5266          * is not cleared, it will fail when following rte_intr_enable( ) tries
5267          * to map Rx queue interrupt to other VFIO vectors.
5268          * So clear uio/vfio intr/evevnfd first to avoid failure.
5269          */
5270         rte_intr_disable(intr_handle);
5271
5272         rte_intr_enable(intr_handle);
5273
5274         /* Re-enable interrupt for VF */
5275         ixgbevf_intr_enable(dev);
5276
5277         /*
5278          * Update link status right before return, because it may
5279          * start link configuration process in a separate thread.
5280          */
5281         ixgbevf_dev_link_update(dev, 0);
5282
5283         hw->adapter_stopped = false;
5284
5285         return 0;
5286 }
5287
5288 static void
5289 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5290 {
5291         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292         struct ixgbe_adapter *adapter = dev->data->dev_private;
5293         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5294         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5295
5296         if (hw->adapter_stopped)
5297                 return;
5298
5299         PMD_INIT_FUNC_TRACE();
5300
5301         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5302
5303         ixgbevf_intr_disable(dev);
5304
5305         hw->adapter_stopped = 1;
5306         ixgbe_stop_adapter(hw);
5307
5308         /*
5309           * Clear what we set, but we still keep shadow_vfta to
5310           * restore after device starts
5311           */
5312         ixgbevf_set_vfta_all(dev, 0);
5313
5314         /* Clear stored conf */
5315         dev->data->scattered_rx = 0;
5316
5317         ixgbe_dev_clear_queues(dev);
5318
5319         /* Clean datapath event and queue/vec mapping */
5320         rte_intr_efd_disable(intr_handle);
5321         if (intr_handle->intr_vec != NULL) {
5322                 rte_free(intr_handle->intr_vec);
5323                 intr_handle->intr_vec = NULL;
5324         }
5325
5326         adapter->rss_reta_updated = 0;
5327 }
5328
5329 static void
5330 ixgbevf_dev_close(struct rte_eth_dev *dev)
5331 {
5332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5333         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5334         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5335
5336         PMD_INIT_FUNC_TRACE();
5337
5338         ixgbe_reset_hw(hw);
5339
5340         ixgbevf_dev_stop(dev);
5341
5342         ixgbe_dev_free_queues(dev);
5343
5344         /**
5345          * Remove the VF MAC address ro ensure
5346          * that the VF traffic goes to the PF
5347          * after stop, close and detach of the VF
5348          **/
5349         ixgbevf_remove_mac_addr(dev, 0);
5350
5351         dev->dev_ops = NULL;
5352         dev->rx_pkt_burst = NULL;
5353         dev->tx_pkt_burst = NULL;
5354
5355         rte_intr_disable(intr_handle);
5356         rte_intr_callback_unregister(intr_handle,
5357                                      ixgbevf_dev_interrupt_handler, dev);
5358 }
5359
5360 /*
5361  * Reset VF device
5362  */
5363 static int
5364 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5365 {
5366         int ret;
5367
5368         ret = eth_ixgbevf_dev_uninit(dev);
5369         if (ret)
5370                 return ret;
5371
5372         ret = eth_ixgbevf_dev_init(dev);
5373
5374         return ret;
5375 }
5376
5377 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5378 {
5379         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5380         struct ixgbe_vfta *shadow_vfta =
5381                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5382         int i = 0, j = 0, vfta = 0, mask = 1;
5383
5384         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5385                 vfta = shadow_vfta->vfta[i];
5386                 if (vfta) {
5387                         mask = 1;
5388                         for (j = 0; j < 32; j++) {
5389                                 if (vfta & mask)
5390                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5391                                                        on, false);
5392                                 mask <<= 1;
5393                         }
5394                 }
5395         }
5396
5397 }
5398
5399 static int
5400 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5401 {
5402         struct ixgbe_hw *hw =
5403                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5404         struct ixgbe_vfta *shadow_vfta =
5405                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5406         uint32_t vid_idx = 0;
5407         uint32_t vid_bit = 0;
5408         int ret = 0;
5409
5410         PMD_INIT_FUNC_TRACE();
5411
5412         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5413         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5414         if (ret) {
5415                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5416                 return ret;
5417         }
5418         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5419         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5420
5421         /* Save what we set and retore it after device reset */
5422         if (on)
5423                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5424         else
5425                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5426
5427         return 0;
5428 }
5429
5430 static void
5431 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5432 {
5433         struct ixgbe_hw *hw =
5434                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5435         uint32_t ctrl;
5436
5437         PMD_INIT_FUNC_TRACE();
5438
5439         if (queue >= hw->mac.max_rx_queues)
5440                 return;
5441
5442         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5443         if (on)
5444                 ctrl |= IXGBE_RXDCTL_VME;
5445         else
5446                 ctrl &= ~IXGBE_RXDCTL_VME;
5447         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5448
5449         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5450 }
5451
5452 static int
5453 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5454 {
5455         struct ixgbe_rx_queue *rxq;
5456         uint16_t i;
5457         int on = 0;
5458
5459         /* VF function only support hw strip feature, others are not support */
5460         if (mask & ETH_VLAN_STRIP_MASK) {
5461                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5462                         rxq = dev->data->rx_queues[i];
5463                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5464                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5465                 }
5466         }
5467
5468         return 0;
5469 }
5470
5471 static int
5472 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5473 {
5474         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5475
5476         ixgbevf_vlan_offload_config(dev, mask);
5477
5478         return 0;
5479 }
5480
5481 int
5482 ixgbe_vt_check(struct ixgbe_hw *hw)
5483 {
5484         uint32_t reg_val;
5485
5486         /* if Virtualization Technology is enabled */
5487         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5488         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5489                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5490                 return -1;
5491         }
5492
5493         return 0;
5494 }
5495
5496 static uint32_t
5497 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5498 {
5499         uint32_t vector = 0;
5500
5501         switch (hw->mac.mc_filter_type) {
5502         case 0:   /* use bits [47:36] of the address */
5503                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5504                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5505                 break;
5506         case 1:   /* use bits [46:35] of the address */
5507                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5508                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5509                 break;
5510         case 2:   /* use bits [45:34] of the address */
5511                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5512                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5513                 break;
5514         case 3:   /* use bits [43:32] of the address */
5515                 vector = ((uc_addr->addr_bytes[4]) |
5516                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5517                 break;
5518         default:  /* Invalid mc_filter_type */
5519                 break;
5520         }
5521
5522         /* vector can only be 12-bits or boundary will be exceeded */
5523         vector &= 0xFFF;
5524         return vector;
5525 }
5526
5527 static int
5528 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5529                         struct rte_ether_addr *mac_addr, uint8_t on)
5530 {
5531         uint32_t vector;
5532         uint32_t uta_idx;
5533         uint32_t reg_val;
5534         uint32_t uta_shift;
5535         uint32_t rc;
5536         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5537         const uint32_t ixgbe_uta_bit_shift = 5;
5538         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5539         const uint32_t bit1 = 0x1;
5540
5541         struct ixgbe_hw *hw =
5542                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5543         struct ixgbe_uta_info *uta_info =
5544                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5545
5546         /* The UTA table only exists on 82599 hardware and newer */
5547         if (hw->mac.type < ixgbe_mac_82599EB)
5548                 return -ENOTSUP;
5549
5550         vector = ixgbe_uta_vector(hw, mac_addr);
5551         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5552         uta_shift = vector & ixgbe_uta_bit_mask;
5553
5554         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5555         if (rc == on)
5556                 return 0;
5557
5558         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5559         if (on) {
5560                 uta_info->uta_in_use++;
5561                 reg_val |= (bit1 << uta_shift);
5562                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5563         } else {
5564                 uta_info->uta_in_use--;
5565                 reg_val &= ~(bit1 << uta_shift);
5566                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5567         }
5568
5569         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5570
5571         if (uta_info->uta_in_use > 0)
5572                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5573                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5574         else
5575                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5576
5577         return 0;
5578 }
5579
5580 static int
5581 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5582 {
5583         int i;
5584         struct ixgbe_hw *hw =
5585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5586         struct ixgbe_uta_info *uta_info =
5587                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5588
5589         /* The UTA table only exists on 82599 hardware and newer */
5590         if (hw->mac.type < ixgbe_mac_82599EB)
5591                 return -ENOTSUP;
5592
5593         if (on) {
5594                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5595                         uta_info->uta_shadow[i] = ~0;
5596                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5597                 }
5598         } else {
5599                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5600                         uta_info->uta_shadow[i] = 0;
5601                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5602                 }
5603         }
5604         return 0;
5605
5606 }
5607
5608 uint32_t
5609 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5610 {
5611         uint32_t new_val = orig_val;
5612
5613         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5614                 new_val |= IXGBE_VMOLR_AUPE;
5615         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5616                 new_val |= IXGBE_VMOLR_ROMPE;
5617         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5618                 new_val |= IXGBE_VMOLR_ROPE;
5619         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5620                 new_val |= IXGBE_VMOLR_BAM;
5621         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5622                 new_val |= IXGBE_VMOLR_MPE;
5623
5624         return new_val;
5625 }
5626
5627 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5628 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5629 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5630 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5631 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5632         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5633         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5634
5635 static int
5636 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5637                       struct rte_eth_mirror_conf *mirror_conf,
5638                       uint8_t rule_id, uint8_t on)
5639 {
5640         uint32_t mr_ctl, vlvf;
5641         uint32_t mp_lsb = 0;
5642         uint32_t mv_msb = 0;
5643         uint32_t mv_lsb = 0;
5644         uint32_t mp_msb = 0;
5645         uint8_t i = 0;
5646         int reg_index = 0;
5647         uint64_t vlan_mask = 0;
5648
5649         const uint8_t pool_mask_offset = 32;
5650         const uint8_t vlan_mask_offset = 32;
5651         const uint8_t dst_pool_offset = 8;
5652         const uint8_t rule_mr_offset  = 4;
5653         const uint8_t mirror_rule_mask = 0x0F;
5654
5655         struct ixgbe_mirror_info *mr_info =
5656                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5657         struct ixgbe_hw *hw =
5658                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5659         uint8_t mirror_type = 0;
5660
5661         if (ixgbe_vt_check(hw) < 0)
5662                 return -ENOTSUP;
5663
5664         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5665                 return -EINVAL;
5666
5667         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5668                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5669                             mirror_conf->rule_type);
5670                 return -EINVAL;
5671         }
5672
5673         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5674                 mirror_type |= IXGBE_MRCTL_VLME;
5675                 /* Check if vlan id is valid and find conresponding VLAN ID
5676                  * index in VLVF
5677                  */
5678                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5679                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5680                                 /* search vlan id related pool vlan filter
5681                                  * index
5682                                  */
5683                                 reg_index = ixgbe_find_vlvf_slot(
5684                                                 hw,
5685                                                 mirror_conf->vlan.vlan_id[i],
5686                                                 false);
5687                                 if (reg_index < 0)
5688                                         return -EINVAL;
5689                                 vlvf = IXGBE_READ_REG(hw,
5690                                                       IXGBE_VLVF(reg_index));
5691                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5692                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5693                                       mirror_conf->vlan.vlan_id[i]))
5694                                         vlan_mask |= (1ULL << reg_index);
5695                                 else
5696                                         return -EINVAL;
5697                         }
5698                 }
5699
5700                 if (on) {
5701                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5702                         mv_msb = vlan_mask >> vlan_mask_offset;
5703
5704                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5705                                                 mirror_conf->vlan.vlan_mask;
5706                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5707                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5708                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5709                                                 mirror_conf->vlan.vlan_id[i];
5710                         }
5711                 } else {
5712                         mv_lsb = 0;
5713                         mv_msb = 0;
5714                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5715                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5716                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5717                 }
5718         }
5719
5720         /**
5721          * if enable pool mirror, write related pool mask register,if disable
5722          * pool mirror, clear PFMRVM register
5723          */
5724         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5725                 mirror_type |= IXGBE_MRCTL_VPME;
5726                 if (on) {
5727                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5728                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5729                         mr_info->mr_conf[rule_id].pool_mask =
5730                                         mirror_conf->pool_mask;
5731
5732                 } else {
5733                         mp_lsb = 0;
5734                         mp_msb = 0;
5735                         mr_info->mr_conf[rule_id].pool_mask = 0;
5736                 }
5737         }
5738         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5739                 mirror_type |= IXGBE_MRCTL_UPME;
5740         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5741                 mirror_type |= IXGBE_MRCTL_DPME;
5742
5743         /* read  mirror control register and recalculate it */
5744         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5745
5746         if (on) {
5747                 mr_ctl |= mirror_type;
5748                 mr_ctl &= mirror_rule_mask;
5749                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5750         } else {
5751                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5752         }
5753
5754         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5755         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5756
5757         /* write mirrror control  register */
5758         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5759
5760         /* write pool mirrror control  register */
5761         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5762                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5763                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5764                                 mp_msb);
5765         }
5766         /* write VLAN mirrror control  register */
5767         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5768                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5769                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5770                                 mv_msb);
5771         }
5772
5773         return 0;
5774 }
5775
5776 static int
5777 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5778 {
5779         int mr_ctl = 0;
5780         uint32_t lsb_val = 0;
5781         uint32_t msb_val = 0;
5782         const uint8_t rule_mr_offset = 4;
5783
5784         struct ixgbe_hw *hw =
5785                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5786         struct ixgbe_mirror_info *mr_info =
5787                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5788
5789         if (ixgbe_vt_check(hw) < 0)
5790                 return -ENOTSUP;
5791
5792         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5793                 return -EINVAL;
5794
5795         memset(&mr_info->mr_conf[rule_id], 0,
5796                sizeof(struct rte_eth_mirror_conf));
5797
5798         /* clear PFVMCTL register */
5799         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5800
5801         /* clear pool mask register */
5802         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5803         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5804
5805         /* clear vlan mask register */
5806         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5807         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5808
5809         return 0;
5810 }
5811
5812 static int
5813 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5814 {
5815         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5816         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5817         struct ixgbe_interrupt *intr =
5818                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5819         struct ixgbe_hw *hw =
5820                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5821         uint32_t vec = IXGBE_MISC_VEC_ID;
5822
5823         if (rte_intr_allow_others(intr_handle))
5824                 vec = IXGBE_RX_VEC_START;
5825         intr->mask |= (1 << vec);
5826         RTE_SET_USED(queue_id);
5827         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5828
5829         rte_intr_ack(intr_handle);
5830
5831         return 0;
5832 }
5833
5834 static int
5835 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5836 {
5837         struct ixgbe_interrupt *intr =
5838                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5839         struct ixgbe_hw *hw =
5840                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5841         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5842         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5843         uint32_t vec = IXGBE_MISC_VEC_ID;
5844
5845         if (rte_intr_allow_others(intr_handle))
5846                 vec = IXGBE_RX_VEC_START;
5847         intr->mask &= ~(1 << vec);
5848         RTE_SET_USED(queue_id);
5849         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5850
5851         return 0;
5852 }
5853
5854 static int
5855 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5856 {
5857         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5858         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5859         uint32_t mask;
5860         struct ixgbe_hw *hw =
5861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5862         struct ixgbe_interrupt *intr =
5863                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5864
5865         if (queue_id < 16) {
5866                 ixgbe_disable_intr(hw);
5867                 intr->mask |= (1 << queue_id);
5868                 ixgbe_enable_intr(dev);
5869         } else if (queue_id < 32) {
5870                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5871                 mask &= (1 << queue_id);
5872                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5873         } else if (queue_id < 64) {
5874                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5875                 mask &= (1 << (queue_id - 32));
5876                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5877         }
5878         rte_intr_ack(intr_handle);
5879
5880         return 0;
5881 }
5882
5883 static int
5884 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5885 {
5886         uint32_t mask;
5887         struct ixgbe_hw *hw =
5888                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5889         struct ixgbe_interrupt *intr =
5890                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5891
5892         if (queue_id < 16) {
5893                 ixgbe_disable_intr(hw);
5894                 intr->mask &= ~(1 << queue_id);
5895                 ixgbe_enable_intr(dev);
5896         } else if (queue_id < 32) {
5897                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5898                 mask &= ~(1 << queue_id);
5899                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5900         } else if (queue_id < 64) {
5901                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5902                 mask &= ~(1 << (queue_id - 32));
5903                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5904         }
5905
5906         return 0;
5907 }
5908
5909 static void
5910 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5911                      uint8_t queue, uint8_t msix_vector)
5912 {
5913         uint32_t tmp, idx;
5914
5915         if (direction == -1) {
5916                 /* other causes */
5917                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5918                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5919                 tmp &= ~0xFF;
5920                 tmp |= msix_vector;
5921                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5922         } else {
5923                 /* rx or tx cause */
5924                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5925                 idx = ((16 * (queue & 1)) + (8 * direction));
5926                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5927                 tmp &= ~(0xFF << idx);
5928                 tmp |= (msix_vector << idx);
5929                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5930         }
5931 }
5932
5933 /**
5934  * set the IVAR registers, mapping interrupt causes to vectors
5935  * @param hw
5936  *  pointer to ixgbe_hw struct
5937  * @direction
5938  *  0 for Rx, 1 for Tx, -1 for other causes
5939  * @queue
5940  *  queue to map the corresponding interrupt to
5941  * @msix_vector
5942  *  the vector to map to the corresponding queue
5943  */
5944 static void
5945 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5946                    uint8_t queue, uint8_t msix_vector)
5947 {
5948         uint32_t tmp, idx;
5949
5950         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5951         if (hw->mac.type == ixgbe_mac_82598EB) {
5952                 if (direction == -1)
5953                         direction = 0;
5954                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5955                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5956                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5957                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5958                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5959         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5960                         (hw->mac.type == ixgbe_mac_X540) ||
5961                         (hw->mac.type == ixgbe_mac_X550) ||
5962                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5963                 if (direction == -1) {
5964                         /* other causes */
5965                         idx = ((queue & 1) * 8);
5966                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5967                         tmp &= ~(0xFF << idx);
5968                         tmp |= (msix_vector << idx);
5969                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5970                 } else {
5971                         /* rx or tx causes */
5972                         idx = ((16 * (queue & 1)) + (8 * direction));
5973                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5974                         tmp &= ~(0xFF << idx);
5975                         tmp |= (msix_vector << idx);
5976                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5977                 }
5978         }
5979 }
5980
5981 static void
5982 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5983 {
5984         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5985         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5986         struct ixgbe_hw *hw =
5987                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5988         uint32_t q_idx;
5989         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5990         uint32_t base = IXGBE_MISC_VEC_ID;
5991
5992         /* Configure VF other cause ivar */
5993         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5994
5995         /* won't configure msix register if no mapping is done
5996          * between intr vector and event fd.
5997          */
5998         if (!rte_intr_dp_is_en(intr_handle))
5999                 return;
6000
6001         if (rte_intr_allow_others(intr_handle)) {
6002                 base = IXGBE_RX_VEC_START;
6003                 vector_idx = IXGBE_RX_VEC_START;
6004         }
6005
6006         /* Configure all RX queues of VF */
6007         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6008                 /* Force all queue use vector 0,
6009                  * as IXGBE_VF_MAXMSIVECOTR = 1
6010                  */
6011                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6012                 intr_handle->intr_vec[q_idx] = vector_idx;
6013                 if (vector_idx < base + intr_handle->nb_efd - 1)
6014                         vector_idx++;
6015         }
6016
6017         /* As RX queue setting above show, all queues use the vector 0.
6018          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6019          */
6020         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6021                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6022                         | IXGBE_EITR_CNT_WDIS);
6023 }
6024
6025 /**
6026  * Sets up the hardware to properly generate MSI-X interrupts
6027  * @hw
6028  *  board private structure
6029  */
6030 static void
6031 ixgbe_configure_msix(struct rte_eth_dev *dev)
6032 {
6033         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6034         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6035         struct ixgbe_hw *hw =
6036                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6037         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6038         uint32_t vec = IXGBE_MISC_VEC_ID;
6039         uint32_t mask;
6040         uint32_t gpie;
6041
6042         /* won't configure msix register if no mapping is done
6043          * between intr vector and event fd
6044          * but if misx has been enabled already, need to configure
6045          * auto clean, auto mask and throttling.
6046          */
6047         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6048         if (!rte_intr_dp_is_en(intr_handle) &&
6049             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6050                 return;
6051
6052         if (rte_intr_allow_others(intr_handle))
6053                 vec = base = IXGBE_RX_VEC_START;
6054
6055         /* setup GPIE for MSI-x mode */
6056         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6057         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6058                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6059         /* auto clearing and auto setting corresponding bits in EIMS
6060          * when MSI-X interrupt is triggered
6061          */
6062         if (hw->mac.type == ixgbe_mac_82598EB) {
6063                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6064         } else {
6065                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6066                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6067         }
6068         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6069
6070         /* Populate the IVAR table and set the ITR values to the
6071          * corresponding register.
6072          */
6073         if (rte_intr_dp_is_en(intr_handle)) {
6074                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6075                         queue_id++) {
6076                         /* by default, 1:1 mapping */
6077                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6078                         intr_handle->intr_vec[queue_id] = vec;
6079                         if (vec < base + intr_handle->nb_efd - 1)
6080                                 vec++;
6081                 }
6082
6083                 switch (hw->mac.type) {
6084                 case ixgbe_mac_82598EB:
6085                         ixgbe_set_ivar_map(hw, -1,
6086                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6087                                            IXGBE_MISC_VEC_ID);
6088                         break;
6089                 case ixgbe_mac_82599EB:
6090                 case ixgbe_mac_X540:
6091                 case ixgbe_mac_X550:
6092                 case ixgbe_mac_X550EM_x:
6093                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6094                         break;
6095                 default:
6096                         break;
6097                 }
6098         }
6099         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6100                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6101                         | IXGBE_EITR_CNT_WDIS);
6102
6103         /* set up to autoclear timer, and the vectors */
6104         mask = IXGBE_EIMS_ENABLE_MASK;
6105         mask &= ~(IXGBE_EIMS_OTHER |
6106                   IXGBE_EIMS_MAILBOX |
6107                   IXGBE_EIMS_LSC);
6108
6109         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6110 }
6111
6112 int
6113 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6114                            uint16_t queue_idx, uint16_t tx_rate)
6115 {
6116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6117         struct rte_eth_rxmode *rxmode;
6118         uint32_t rf_dec, rf_int;
6119         uint32_t bcnrc_val;
6120         uint16_t link_speed = dev->data->dev_link.link_speed;
6121
6122         if (queue_idx >= hw->mac.max_tx_queues)
6123                 return -EINVAL;
6124
6125         if (tx_rate != 0) {
6126                 /* Calculate the rate factor values to set */
6127                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6128                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6129                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6130
6131                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6132                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6133                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6134                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6135         } else {
6136                 bcnrc_val = 0;
6137         }
6138
6139         rxmode = &dev->data->dev_conf.rxmode;
6140         /*
6141          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6142          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6143          * set as 0x4.
6144          */
6145         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6146             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6147                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6148                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6149         else
6150                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6151                         IXGBE_MMW_SIZE_DEFAULT);
6152
6153         /* Set RTTBCNRC of queue X */
6154         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6155         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6156         IXGBE_WRITE_FLUSH(hw);
6157
6158         return 0;
6159 }
6160
6161 static int
6162 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6163                      __attribute__((unused)) uint32_t index,
6164                      __attribute__((unused)) uint32_t pool)
6165 {
6166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6167         int diag;
6168
6169         /*
6170          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6171          * operation. Trap this case to avoid exhausting the [very limited]
6172          * set of PF resources used to store VF MAC addresses.
6173          */
6174         if (memcmp(hw->mac.perm_addr, mac_addr,
6175                         sizeof(struct rte_ether_addr)) == 0)
6176                 return -1;
6177         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6178         if (diag != 0)
6179                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6180                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6181                             mac_addr->addr_bytes[0],
6182                             mac_addr->addr_bytes[1],
6183                             mac_addr->addr_bytes[2],
6184                             mac_addr->addr_bytes[3],
6185                             mac_addr->addr_bytes[4],
6186                             mac_addr->addr_bytes[5],
6187                             diag);
6188         return diag;
6189 }
6190
6191 static void
6192 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6193 {
6194         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6195         struct rte_ether_addr *perm_addr =
6196                 (struct rte_ether_addr *)hw->mac.perm_addr;
6197         struct rte_ether_addr *mac_addr;
6198         uint32_t i;
6199         int diag;
6200
6201         /*
6202          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6203          * not support the deletion of a given MAC address.
6204          * Instead, it imposes to delete all MAC addresses, then to add again
6205          * all MAC addresses with the exception of the one to be deleted.
6206          */
6207         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6208
6209         /*
6210          * Add again all MAC addresses, with the exception of the deleted one
6211          * and of the permanent MAC address.
6212          */
6213         for (i = 0, mac_addr = dev->data->mac_addrs;
6214              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6215                 /* Skip the deleted MAC address */
6216                 if (i == index)
6217                         continue;
6218                 /* Skip NULL MAC addresses */
6219                 if (rte_is_zero_ether_addr(mac_addr))
6220                         continue;
6221                 /* Skip the permanent MAC address */
6222                 if (memcmp(perm_addr, mac_addr,
6223                                 sizeof(struct rte_ether_addr)) == 0)
6224                         continue;
6225                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6226                 if (diag != 0)
6227                         PMD_DRV_LOG(ERR,
6228                                     "Adding again MAC address "
6229                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6230                                     "diag=%d",
6231                                     mac_addr->addr_bytes[0],
6232                                     mac_addr->addr_bytes[1],
6233                                     mac_addr->addr_bytes[2],
6234                                     mac_addr->addr_bytes[3],
6235                                     mac_addr->addr_bytes[4],
6236                                     mac_addr->addr_bytes[5],
6237                                     diag);
6238         }
6239 }
6240
6241 static int
6242 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6243                         struct rte_ether_addr *addr)
6244 {
6245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6246
6247         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6248
6249         return 0;
6250 }
6251
6252 int
6253 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6254                         struct rte_eth_syn_filter *filter,
6255                         bool add)
6256 {
6257         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6258         struct ixgbe_filter_info *filter_info =
6259                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6260         uint32_t syn_info;
6261         uint32_t synqf;
6262
6263         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6264                 return -EINVAL;
6265
6266         syn_info = filter_info->syn_info;
6267
6268         if (add) {
6269                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6270                         return -EINVAL;
6271                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6272                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6273
6274                 if (filter->hig_pri)
6275                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6276                 else
6277                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6278         } else {
6279                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6280                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6281                         return -ENOENT;
6282                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6283         }
6284
6285         filter_info->syn_info = synqf;
6286         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6287         IXGBE_WRITE_FLUSH(hw);
6288         return 0;
6289 }
6290
6291 static int
6292 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6293                         struct rte_eth_syn_filter *filter)
6294 {
6295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6296         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6297
6298         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6299                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6300                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6301                 return 0;
6302         }
6303         return -ENOENT;
6304 }
6305
6306 static int
6307 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6308                         enum rte_filter_op filter_op,
6309                         void *arg)
6310 {
6311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6312         int ret;
6313
6314         MAC_TYPE_FILTER_SUP(hw->mac.type);
6315
6316         if (filter_op == RTE_ETH_FILTER_NOP)
6317                 return 0;
6318
6319         if (arg == NULL) {
6320                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6321                             filter_op);
6322                 return -EINVAL;
6323         }
6324
6325         switch (filter_op) {
6326         case RTE_ETH_FILTER_ADD:
6327                 ret = ixgbe_syn_filter_set(dev,
6328                                 (struct rte_eth_syn_filter *)arg,
6329                                 TRUE);
6330                 break;
6331         case RTE_ETH_FILTER_DELETE:
6332                 ret = ixgbe_syn_filter_set(dev,
6333                                 (struct rte_eth_syn_filter *)arg,
6334                                 FALSE);
6335                 break;
6336         case RTE_ETH_FILTER_GET:
6337                 ret = ixgbe_syn_filter_get(dev,
6338                                 (struct rte_eth_syn_filter *)arg);
6339                 break;
6340         default:
6341                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6342                 ret = -EINVAL;
6343                 break;
6344         }
6345
6346         return ret;
6347 }
6348
6349
6350 static inline enum ixgbe_5tuple_protocol
6351 convert_protocol_type(uint8_t protocol_value)
6352 {
6353         if (protocol_value == IPPROTO_TCP)
6354                 return IXGBE_FILTER_PROTOCOL_TCP;
6355         else if (protocol_value == IPPROTO_UDP)
6356                 return IXGBE_FILTER_PROTOCOL_UDP;
6357         else if (protocol_value == IPPROTO_SCTP)
6358                 return IXGBE_FILTER_PROTOCOL_SCTP;
6359         else
6360                 return IXGBE_FILTER_PROTOCOL_NONE;
6361 }
6362
6363 /* inject a 5-tuple filter to HW */
6364 static inline void
6365 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6366                            struct ixgbe_5tuple_filter *filter)
6367 {
6368         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6369         int i;
6370         uint32_t ftqf, sdpqf;
6371         uint32_t l34timir = 0;
6372         uint8_t mask = 0xff;
6373
6374         i = filter->index;
6375
6376         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6377                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6378         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6379
6380         ftqf = (uint32_t)(filter->filter_info.proto &
6381                 IXGBE_FTQF_PROTOCOL_MASK);
6382         ftqf |= (uint32_t)((filter->filter_info.priority &
6383                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6384         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6385                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6386         if (filter->filter_info.dst_ip_mask == 0)
6387                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6388         if (filter->filter_info.src_port_mask == 0)
6389                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6390         if (filter->filter_info.dst_port_mask == 0)
6391                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6392         if (filter->filter_info.proto_mask == 0)
6393                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6394         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6395         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6396         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6397
6398         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6399         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6400         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6401         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6402
6403         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6404         l34timir |= (uint32_t)(filter->queue <<
6405                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6406         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6407 }
6408
6409 /*
6410  * add a 5tuple filter
6411  *
6412  * @param
6413  * dev: Pointer to struct rte_eth_dev.
6414  * index: the index the filter allocates.
6415  * filter: ponter to the filter that will be added.
6416  * rx_queue: the queue id the filter assigned to.
6417  *
6418  * @return
6419  *    - On success, zero.
6420  *    - On failure, a negative value.
6421  */
6422 static int
6423 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6424                         struct ixgbe_5tuple_filter *filter)
6425 {
6426         struct ixgbe_filter_info *filter_info =
6427                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6428         int i, idx, shift;
6429
6430         /*
6431          * look for an unused 5tuple filter index,
6432          * and insert the filter to list.
6433          */
6434         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6435                 idx = i / (sizeof(uint32_t) * NBBY);
6436                 shift = i % (sizeof(uint32_t) * NBBY);
6437                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6438                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6439                         filter->index = i;
6440                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6441                                           filter,
6442                                           entries);
6443                         break;
6444                 }
6445         }
6446         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6447                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6448                 return -ENOSYS;
6449         }
6450
6451         ixgbe_inject_5tuple_filter(dev, filter);
6452
6453         return 0;
6454 }
6455
6456 /*
6457  * remove a 5tuple filter
6458  *
6459  * @param
6460  * dev: Pointer to struct rte_eth_dev.
6461  * filter: the pointer of the filter will be removed.
6462  */
6463 static void
6464 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6465                         struct ixgbe_5tuple_filter *filter)
6466 {
6467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6468         struct ixgbe_filter_info *filter_info =
6469                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6470         uint16_t index = filter->index;
6471
6472         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6473                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6474         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6475         rte_free(filter);
6476
6477         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6478         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6479         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6480         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6481         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6482 }
6483
6484 static int
6485 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6486 {
6487         struct ixgbe_hw *hw;
6488         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6489         struct rte_eth_dev_data *dev_data = dev->data;
6490
6491         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6492
6493         if (mtu < RTE_ETHER_MIN_MTU ||
6494                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6495                 return -EINVAL;
6496
6497         /* If device is started, refuse mtu that requires the support of
6498          * scattered packets when this feature has not been enabled before.
6499          */
6500         if (dev_data->dev_started && !dev_data->scattered_rx &&
6501             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6502              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6503                 PMD_INIT_LOG(ERR, "Stop port first.");
6504                 return -EINVAL;
6505         }
6506
6507         /*
6508          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6509          * request of the version 2.0 of the mailbox API.
6510          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6511          * of the mailbox API.
6512          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6513          * prior to 3.11.33 which contains the following change:
6514          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6515          */
6516         ixgbevf_rlpml_set_vf(hw, max_frame);
6517
6518         /* update max frame size */
6519         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6520         return 0;
6521 }
6522
6523 static inline struct ixgbe_5tuple_filter *
6524 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6525                         struct ixgbe_5tuple_filter_info *key)
6526 {
6527         struct ixgbe_5tuple_filter *it;
6528
6529         TAILQ_FOREACH(it, filter_list, entries) {
6530                 if (memcmp(key, &it->filter_info,
6531                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6532                         return it;
6533                 }
6534         }
6535         return NULL;
6536 }
6537
6538 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6539 static inline int
6540 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6541                         struct ixgbe_5tuple_filter_info *filter_info)
6542 {
6543         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6544                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6545                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6546                 return -EINVAL;
6547
6548         switch (filter->dst_ip_mask) {
6549         case UINT32_MAX:
6550                 filter_info->dst_ip_mask = 0;
6551                 filter_info->dst_ip = filter->dst_ip;
6552                 break;
6553         case 0:
6554                 filter_info->dst_ip_mask = 1;
6555                 break;
6556         default:
6557                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6558                 return -EINVAL;
6559         }
6560
6561         switch (filter->src_ip_mask) {
6562         case UINT32_MAX:
6563                 filter_info->src_ip_mask = 0;
6564                 filter_info->src_ip = filter->src_ip;
6565                 break;
6566         case 0:
6567                 filter_info->src_ip_mask = 1;
6568                 break;
6569         default:
6570                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6571                 return -EINVAL;
6572         }
6573
6574         switch (filter->dst_port_mask) {
6575         case UINT16_MAX:
6576                 filter_info->dst_port_mask = 0;
6577                 filter_info->dst_port = filter->dst_port;
6578                 break;
6579         case 0:
6580                 filter_info->dst_port_mask = 1;
6581                 break;
6582         default:
6583                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6584                 return -EINVAL;
6585         }
6586
6587         switch (filter->src_port_mask) {
6588         case UINT16_MAX:
6589                 filter_info->src_port_mask = 0;
6590                 filter_info->src_port = filter->src_port;
6591                 break;
6592         case 0:
6593                 filter_info->src_port_mask = 1;
6594                 break;
6595         default:
6596                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6597                 return -EINVAL;
6598         }
6599
6600         switch (filter->proto_mask) {
6601         case UINT8_MAX:
6602                 filter_info->proto_mask = 0;
6603                 filter_info->proto =
6604                         convert_protocol_type(filter->proto);
6605                 break;
6606         case 0:
6607                 filter_info->proto_mask = 1;
6608                 break;
6609         default:
6610                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6611                 return -EINVAL;
6612         }
6613
6614         filter_info->priority = (uint8_t)filter->priority;
6615         return 0;
6616 }
6617
6618 /*
6619  * add or delete a ntuple filter
6620  *
6621  * @param
6622  * dev: Pointer to struct rte_eth_dev.
6623  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6624  * add: if true, add filter, if false, remove filter
6625  *
6626  * @return
6627  *    - On success, zero.
6628  *    - On failure, a negative value.
6629  */
6630 int
6631 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6632                         struct rte_eth_ntuple_filter *ntuple_filter,
6633                         bool add)
6634 {
6635         struct ixgbe_filter_info *filter_info =
6636                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6637         struct ixgbe_5tuple_filter_info filter_5tuple;
6638         struct ixgbe_5tuple_filter *filter;
6639         int ret;
6640
6641         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6642                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6643                 return -EINVAL;
6644         }
6645
6646         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6647         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6648         if (ret < 0)
6649                 return ret;
6650
6651         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6652                                          &filter_5tuple);
6653         if (filter != NULL && add) {
6654                 PMD_DRV_LOG(ERR, "filter exists.");
6655                 return -EEXIST;
6656         }
6657         if (filter == NULL && !add) {
6658                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6659                 return -ENOENT;
6660         }
6661
6662         if (add) {
6663                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6664                                 sizeof(struct ixgbe_5tuple_filter), 0);
6665                 if (filter == NULL)
6666                         return -ENOMEM;
6667                 rte_memcpy(&filter->filter_info,
6668                                  &filter_5tuple,
6669                                  sizeof(struct ixgbe_5tuple_filter_info));
6670                 filter->queue = ntuple_filter->queue;
6671                 ret = ixgbe_add_5tuple_filter(dev, filter);
6672                 if (ret < 0) {
6673                         rte_free(filter);
6674                         return ret;
6675                 }
6676         } else
6677                 ixgbe_remove_5tuple_filter(dev, filter);
6678
6679         return 0;
6680 }
6681
6682 /*
6683  * get a ntuple filter
6684  *
6685  * @param
6686  * dev: Pointer to struct rte_eth_dev.
6687  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6688  *
6689  * @return
6690  *    - On success, zero.
6691  *    - On failure, a negative value.
6692  */
6693 static int
6694 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6695                         struct rte_eth_ntuple_filter *ntuple_filter)
6696 {
6697         struct ixgbe_filter_info *filter_info =
6698                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6699         struct ixgbe_5tuple_filter_info filter_5tuple;
6700         struct ixgbe_5tuple_filter *filter;
6701         int ret;
6702
6703         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6704                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6705                 return -EINVAL;
6706         }
6707
6708         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6709         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6710         if (ret < 0)
6711                 return ret;
6712
6713         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6714                                          &filter_5tuple);
6715         if (filter == NULL) {
6716                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6717                 return -ENOENT;
6718         }
6719         ntuple_filter->queue = filter->queue;
6720         return 0;
6721 }
6722
6723 /*
6724  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6725  * @dev: pointer to rte_eth_dev structure
6726  * @filter_op:operation will be taken.
6727  * @arg: a pointer to specific structure corresponding to the filter_op
6728  *
6729  * @return
6730  *    - On success, zero.
6731  *    - On failure, a negative value.
6732  */
6733 static int
6734 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6735                                 enum rte_filter_op filter_op,
6736                                 void *arg)
6737 {
6738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6739         int ret;
6740
6741         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6742
6743         if (filter_op == RTE_ETH_FILTER_NOP)
6744                 return 0;
6745
6746         if (arg == NULL) {
6747                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6748                             filter_op);
6749                 return -EINVAL;
6750         }
6751
6752         switch (filter_op) {
6753         case RTE_ETH_FILTER_ADD:
6754                 ret = ixgbe_add_del_ntuple_filter(dev,
6755                         (struct rte_eth_ntuple_filter *)arg,
6756                         TRUE);
6757                 break;
6758         case RTE_ETH_FILTER_DELETE:
6759                 ret = ixgbe_add_del_ntuple_filter(dev,
6760                         (struct rte_eth_ntuple_filter *)arg,
6761                         FALSE);
6762                 break;
6763         case RTE_ETH_FILTER_GET:
6764                 ret = ixgbe_get_ntuple_filter(dev,
6765                         (struct rte_eth_ntuple_filter *)arg);
6766                 break;
6767         default:
6768                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6769                 ret = -EINVAL;
6770                 break;
6771         }
6772         return ret;
6773 }
6774
6775 int
6776 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6777                         struct rte_eth_ethertype_filter *filter,
6778                         bool add)
6779 {
6780         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6781         struct ixgbe_filter_info *filter_info =
6782                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6783         uint32_t etqf = 0;
6784         uint32_t etqs = 0;
6785         int ret;
6786         struct ixgbe_ethertype_filter ethertype_filter;
6787
6788         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6789                 return -EINVAL;
6790
6791         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6792                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6793                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6794                         " ethertype filter.", filter->ether_type);
6795                 return -EINVAL;
6796         }
6797
6798         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6799                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6800                 return -EINVAL;
6801         }
6802         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6803                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6804                 return -EINVAL;
6805         }
6806
6807         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6808         if (ret >= 0 && add) {
6809                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6810                             filter->ether_type);
6811                 return -EEXIST;
6812         }
6813         if (ret < 0 && !add) {
6814                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6815                             filter->ether_type);
6816                 return -ENOENT;
6817         }
6818
6819         if (add) {
6820                 etqf = IXGBE_ETQF_FILTER_EN;
6821                 etqf |= (uint32_t)filter->ether_type;
6822                 etqs |= (uint32_t)((filter->queue <<
6823                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6824                                     IXGBE_ETQS_RX_QUEUE);
6825                 etqs |= IXGBE_ETQS_QUEUE_EN;
6826
6827                 ethertype_filter.ethertype = filter->ether_type;
6828                 ethertype_filter.etqf = etqf;
6829                 ethertype_filter.etqs = etqs;
6830                 ethertype_filter.conf = FALSE;
6831                 ret = ixgbe_ethertype_filter_insert(filter_info,
6832                                                     &ethertype_filter);
6833                 if (ret < 0) {
6834                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6835                         return -ENOSPC;
6836                 }
6837         } else {
6838                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6839                 if (ret < 0)
6840                         return -ENOSYS;
6841         }
6842         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6843         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6844         IXGBE_WRITE_FLUSH(hw);
6845
6846         return 0;
6847 }
6848
6849 static int
6850 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6851                         struct rte_eth_ethertype_filter *filter)
6852 {
6853         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6854         struct ixgbe_filter_info *filter_info =
6855                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6856         uint32_t etqf, etqs;
6857         int ret;
6858
6859         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6860         if (ret < 0) {
6861                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6862                             filter->ether_type);
6863                 return -ENOENT;
6864         }
6865
6866         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6867         if (etqf & IXGBE_ETQF_FILTER_EN) {
6868                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6869                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6870                 filter->flags = 0;
6871                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6872                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6873                 return 0;
6874         }
6875         return -ENOENT;
6876 }
6877
6878 /*
6879  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6880  * @dev: pointer to rte_eth_dev structure
6881  * @filter_op:operation will be taken.
6882  * @arg: a pointer to specific structure corresponding to the filter_op
6883  */
6884 static int
6885 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6886                                 enum rte_filter_op filter_op,
6887                                 void *arg)
6888 {
6889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6890         int ret;
6891
6892         MAC_TYPE_FILTER_SUP(hw->mac.type);
6893
6894         if (filter_op == RTE_ETH_FILTER_NOP)
6895                 return 0;
6896
6897         if (arg == NULL) {
6898                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6899                             filter_op);
6900                 return -EINVAL;
6901         }
6902
6903         switch (filter_op) {
6904         case RTE_ETH_FILTER_ADD:
6905                 ret = ixgbe_add_del_ethertype_filter(dev,
6906                         (struct rte_eth_ethertype_filter *)arg,
6907                         TRUE);
6908                 break;
6909         case RTE_ETH_FILTER_DELETE:
6910                 ret = ixgbe_add_del_ethertype_filter(dev,
6911                         (struct rte_eth_ethertype_filter *)arg,
6912                         FALSE);
6913                 break;
6914         case RTE_ETH_FILTER_GET:
6915                 ret = ixgbe_get_ethertype_filter(dev,
6916                         (struct rte_eth_ethertype_filter *)arg);
6917                 break;
6918         default:
6919                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6920                 ret = -EINVAL;
6921                 break;
6922         }
6923         return ret;
6924 }
6925
6926 static int
6927 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6928                      enum rte_filter_type filter_type,
6929                      enum rte_filter_op filter_op,
6930                      void *arg)
6931 {
6932         int ret = 0;
6933
6934         switch (filter_type) {
6935         case RTE_ETH_FILTER_NTUPLE:
6936                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6937                 break;
6938         case RTE_ETH_FILTER_ETHERTYPE:
6939                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6940                 break;
6941         case RTE_ETH_FILTER_SYN:
6942                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6943                 break;
6944         case RTE_ETH_FILTER_FDIR:
6945                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6946                 break;
6947         case RTE_ETH_FILTER_L2_TUNNEL:
6948                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6949                 break;
6950         case RTE_ETH_FILTER_GENERIC:
6951                 if (filter_op != RTE_ETH_FILTER_GET)
6952                         return -EINVAL;
6953                 *(const void **)arg = &ixgbe_flow_ops;
6954                 break;
6955         default:
6956                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6957                                                         filter_type);
6958                 ret = -EINVAL;
6959                 break;
6960         }
6961
6962         return ret;
6963 }
6964
6965 static u8 *
6966 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6967                         u8 **mc_addr_ptr, u32 *vmdq)
6968 {
6969         u8 *mc_addr;
6970
6971         *vmdq = 0;
6972         mc_addr = *mc_addr_ptr;
6973         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6974         return mc_addr;
6975 }
6976
6977 static int
6978 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6979                           struct rte_ether_addr *mc_addr_set,
6980                           uint32_t nb_mc_addr)
6981 {
6982         struct ixgbe_hw *hw;
6983         u8 *mc_addr_list;
6984
6985         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6986         mc_addr_list = (u8 *)mc_addr_set;
6987         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6988                                          ixgbe_dev_addr_list_itr, TRUE);
6989 }
6990
6991 static uint64_t
6992 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6993 {
6994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6995         uint64_t systime_cycles;
6996
6997         switch (hw->mac.type) {
6998         case ixgbe_mac_X550:
6999         case ixgbe_mac_X550EM_x:
7000         case ixgbe_mac_X550EM_a:
7001                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7002                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7003                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7004                                 * NSEC_PER_SEC;
7005                 break;
7006         default:
7007                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7008                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7009                                 << 32;
7010         }
7011
7012         return systime_cycles;
7013 }
7014
7015 static uint64_t
7016 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7017 {
7018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7019         uint64_t rx_tstamp_cycles;
7020
7021         switch (hw->mac.type) {
7022         case ixgbe_mac_X550:
7023         case ixgbe_mac_X550EM_x:
7024         case ixgbe_mac_X550EM_a:
7025                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7026                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7027                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7028                                 * NSEC_PER_SEC;
7029                 break;
7030         default:
7031                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7032                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7033                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7034                                 << 32;
7035         }
7036
7037         return rx_tstamp_cycles;
7038 }
7039
7040 static uint64_t
7041 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7042 {
7043         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7044         uint64_t tx_tstamp_cycles;
7045
7046         switch (hw->mac.type) {
7047         case ixgbe_mac_X550:
7048         case ixgbe_mac_X550EM_x:
7049         case ixgbe_mac_X550EM_a:
7050                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7051                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7052                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7053                                 * NSEC_PER_SEC;
7054                 break;
7055         default:
7056                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7057                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7058                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7059                                 << 32;
7060         }
7061
7062         return tx_tstamp_cycles;
7063 }
7064
7065 static void
7066 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7067 {
7068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7069         struct ixgbe_adapter *adapter = dev->data->dev_private;
7070         struct rte_eth_link link;
7071         uint32_t incval = 0;
7072         uint32_t shift = 0;
7073
7074         /* Get current link speed. */
7075         ixgbe_dev_link_update(dev, 1);
7076         rte_eth_linkstatus_get(dev, &link);
7077
7078         switch (link.link_speed) {
7079         case ETH_SPEED_NUM_100M:
7080                 incval = IXGBE_INCVAL_100;
7081                 shift = IXGBE_INCVAL_SHIFT_100;
7082                 break;
7083         case ETH_SPEED_NUM_1G:
7084                 incval = IXGBE_INCVAL_1GB;
7085                 shift = IXGBE_INCVAL_SHIFT_1GB;
7086                 break;
7087         case ETH_SPEED_NUM_10G:
7088         default:
7089                 incval = IXGBE_INCVAL_10GB;
7090                 shift = IXGBE_INCVAL_SHIFT_10GB;
7091                 break;
7092         }
7093
7094         switch (hw->mac.type) {
7095         case ixgbe_mac_X550:
7096         case ixgbe_mac_X550EM_x:
7097         case ixgbe_mac_X550EM_a:
7098                 /* Independent of link speed. */
7099                 incval = 1;
7100                 /* Cycles read will be interpreted as ns. */
7101                 shift = 0;
7102                 /* Fall-through */
7103         case ixgbe_mac_X540:
7104                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7105                 break;
7106         case ixgbe_mac_82599EB:
7107                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7108                 shift -= IXGBE_INCVAL_SHIFT_82599;
7109                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7110                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7111                 break;
7112         default:
7113                 /* Not supported. */
7114                 return;
7115         }
7116
7117         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7118         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7119         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7120
7121         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7122         adapter->systime_tc.cc_shift = shift;
7123         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7124
7125         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7126         adapter->rx_tstamp_tc.cc_shift = shift;
7127         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7128
7129         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7130         adapter->tx_tstamp_tc.cc_shift = shift;
7131         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7132 }
7133
7134 static int
7135 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7136 {
7137         struct ixgbe_adapter *adapter = dev->data->dev_private;
7138
7139         adapter->systime_tc.nsec += delta;
7140         adapter->rx_tstamp_tc.nsec += delta;
7141         adapter->tx_tstamp_tc.nsec += delta;
7142
7143         return 0;
7144 }
7145
7146 static int
7147 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7148 {
7149         uint64_t ns;
7150         struct ixgbe_adapter *adapter = dev->data->dev_private;
7151
7152         ns = rte_timespec_to_ns(ts);
7153         /* Set the timecounters to a new value. */
7154         adapter->systime_tc.nsec = ns;
7155         adapter->rx_tstamp_tc.nsec = ns;
7156         adapter->tx_tstamp_tc.nsec = ns;
7157
7158         return 0;
7159 }
7160
7161 static int
7162 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7163 {
7164         uint64_t ns, systime_cycles;
7165         struct ixgbe_adapter *adapter = dev->data->dev_private;
7166
7167         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7168         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7169         *ts = rte_ns_to_timespec(ns);
7170
7171         return 0;
7172 }
7173
7174 static int
7175 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7176 {
7177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7178         uint32_t tsync_ctl;
7179         uint32_t tsauxc;
7180
7181         /* Stop the timesync system time. */
7182         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7183         /* Reset the timesync system time value. */
7184         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7185         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7186
7187         /* Enable system time for platforms where it isn't on by default. */
7188         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7189         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7190         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7191
7192         ixgbe_start_timecounters(dev);
7193
7194         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7195         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7196                         (RTE_ETHER_TYPE_1588 |
7197                          IXGBE_ETQF_FILTER_EN |
7198                          IXGBE_ETQF_1588));
7199
7200         /* Enable timestamping of received PTP packets. */
7201         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7202         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7203         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7204
7205         /* Enable timestamping of transmitted PTP packets. */
7206         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7207         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7208         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7209
7210         IXGBE_WRITE_FLUSH(hw);
7211
7212         return 0;
7213 }
7214
7215 static int
7216 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7217 {
7218         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7219         uint32_t tsync_ctl;
7220
7221         /* Disable timestamping of transmitted PTP packets. */
7222         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7223         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7224         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7225
7226         /* Disable timestamping of received PTP packets. */
7227         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7228         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7229         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7230
7231         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7232         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7233
7234         /* Stop incrementating the System Time registers. */
7235         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7236
7237         return 0;
7238 }
7239
7240 static int
7241 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7242                                  struct timespec *timestamp,
7243                                  uint32_t flags __rte_unused)
7244 {
7245         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7246         struct ixgbe_adapter *adapter = dev->data->dev_private;
7247         uint32_t tsync_rxctl;
7248         uint64_t rx_tstamp_cycles;
7249         uint64_t ns;
7250
7251         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7252         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7253                 return -EINVAL;
7254
7255         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7256         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7257         *timestamp = rte_ns_to_timespec(ns);
7258
7259         return  0;
7260 }
7261
7262 static int
7263 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7264                                  struct timespec *timestamp)
7265 {
7266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7267         struct ixgbe_adapter *adapter = dev->data->dev_private;
7268         uint32_t tsync_txctl;
7269         uint64_t tx_tstamp_cycles;
7270         uint64_t ns;
7271
7272         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7273         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7274                 return -EINVAL;
7275
7276         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7277         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7278         *timestamp = rte_ns_to_timespec(ns);
7279
7280         return 0;
7281 }
7282
7283 static int
7284 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7285 {
7286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7287         int count = 0;
7288         int g_ind = 0;
7289         const struct reg_info *reg_group;
7290         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7291                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7292
7293         while ((reg_group = reg_set[g_ind++]))
7294                 count += ixgbe_regs_group_count(reg_group);
7295
7296         return count;
7297 }
7298
7299 static int
7300 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7301 {
7302         int count = 0;
7303         int g_ind = 0;
7304         const struct reg_info *reg_group;
7305
7306         while ((reg_group = ixgbevf_regs[g_ind++]))
7307                 count += ixgbe_regs_group_count(reg_group);
7308
7309         return count;
7310 }
7311
7312 static int
7313 ixgbe_get_regs(struct rte_eth_dev *dev,
7314               struct rte_dev_reg_info *regs)
7315 {
7316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7317         uint32_t *data = regs->data;
7318         int g_ind = 0;
7319         int count = 0;
7320         const struct reg_info *reg_group;
7321         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7322                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7323
7324         if (data == NULL) {
7325                 regs->length = ixgbe_get_reg_length(dev);
7326                 regs->width = sizeof(uint32_t);
7327                 return 0;
7328         }
7329
7330         /* Support only full register dump */
7331         if ((regs->length == 0) ||
7332             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7333                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7334                         hw->device_id;
7335                 while ((reg_group = reg_set[g_ind++]))
7336                         count += ixgbe_read_regs_group(dev, &data[count],
7337                                 reg_group);
7338                 return 0;
7339         }
7340
7341         return -ENOTSUP;
7342 }
7343
7344 static int
7345 ixgbevf_get_regs(struct rte_eth_dev *dev,
7346                 struct rte_dev_reg_info *regs)
7347 {
7348         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7349         uint32_t *data = regs->data;
7350         int g_ind = 0;
7351         int count = 0;
7352         const struct reg_info *reg_group;
7353
7354         if (data == NULL) {
7355                 regs->length = ixgbevf_get_reg_length(dev);
7356                 regs->width = sizeof(uint32_t);
7357                 return 0;
7358         }
7359
7360         /* Support only full register dump */
7361         if ((regs->length == 0) ||
7362             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7363                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7364                         hw->device_id;
7365                 while ((reg_group = ixgbevf_regs[g_ind++]))
7366                         count += ixgbe_read_regs_group(dev, &data[count],
7367                                                       reg_group);
7368                 return 0;
7369         }
7370
7371         return -ENOTSUP;
7372 }
7373
7374 static int
7375 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7376 {
7377         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7378
7379         /* Return unit is byte count */
7380         return hw->eeprom.word_size * 2;
7381 }
7382
7383 static int
7384 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7385                 struct rte_dev_eeprom_info *in_eeprom)
7386 {
7387         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7388         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7389         uint16_t *data = in_eeprom->data;
7390         int first, length;
7391
7392         first = in_eeprom->offset >> 1;
7393         length = in_eeprom->length >> 1;
7394         if ((first > hw->eeprom.word_size) ||
7395             ((first + length) > hw->eeprom.word_size))
7396                 return -EINVAL;
7397
7398         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7399
7400         return eeprom->ops.read_buffer(hw, first, length, data);
7401 }
7402
7403 static int
7404 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7405                 struct rte_dev_eeprom_info *in_eeprom)
7406 {
7407         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7408         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7409         uint16_t *data = in_eeprom->data;
7410         int first, length;
7411
7412         first = in_eeprom->offset >> 1;
7413         length = in_eeprom->length >> 1;
7414         if ((first > hw->eeprom.word_size) ||
7415             ((first + length) > hw->eeprom.word_size))
7416                 return -EINVAL;
7417
7418         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7419
7420         return eeprom->ops.write_buffer(hw,  first, length, data);
7421 }
7422
7423 static int
7424 ixgbe_get_module_info(struct rte_eth_dev *dev,
7425                       struct rte_eth_dev_module_info *modinfo)
7426 {
7427         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7428         uint32_t status;
7429         uint8_t sff8472_rev, addr_mode;
7430         bool page_swap = false;
7431
7432         /* Check whether we support SFF-8472 or not */
7433         status = hw->phy.ops.read_i2c_eeprom(hw,
7434                                              IXGBE_SFF_SFF_8472_COMP,
7435                                              &sff8472_rev);
7436         if (status != 0)
7437                 return -EIO;
7438
7439         /* addressing mode is not supported */
7440         status = hw->phy.ops.read_i2c_eeprom(hw,
7441                                              IXGBE_SFF_SFF_8472_SWAP,
7442                                              &addr_mode);
7443         if (status != 0)
7444                 return -EIO;
7445
7446         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7447                 PMD_DRV_LOG(ERR,
7448                             "Address change required to access page 0xA2, "
7449                             "but not supported. Please report the module "
7450                             "type to the driver maintainers.");
7451                 page_swap = true;
7452         }
7453
7454         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7455                 /* We have a SFP, but it does not support SFF-8472 */
7456                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7457                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7458         } else {
7459                 /* We have a SFP which supports a revision of SFF-8472. */
7460                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7461                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7462         }
7463
7464         return 0;
7465 }
7466
7467 static int
7468 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7469                         struct rte_dev_eeprom_info *info)
7470 {
7471         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7472         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7473         uint8_t databyte = 0xFF;
7474         uint8_t *data = info->data;
7475         uint32_t i = 0;
7476
7477         if (info->length == 0)
7478                 return -EINVAL;
7479
7480         for (i = info->offset; i < info->offset + info->length; i++) {
7481                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7482                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7483                 else
7484                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7485
7486                 if (status != 0)
7487                         return -EIO;
7488
7489                 data[i - info->offset] = databyte;
7490         }
7491
7492         return 0;
7493 }
7494
7495 uint16_t
7496 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7497         switch (mac_type) {
7498         case ixgbe_mac_X550:
7499         case ixgbe_mac_X550EM_x:
7500         case ixgbe_mac_X550EM_a:
7501                 return ETH_RSS_RETA_SIZE_512;
7502         case ixgbe_mac_X550_vf:
7503         case ixgbe_mac_X550EM_x_vf:
7504         case ixgbe_mac_X550EM_a_vf:
7505                 return ETH_RSS_RETA_SIZE_64;
7506         case ixgbe_mac_X540_vf:
7507         case ixgbe_mac_82599_vf:
7508                 return 0;
7509         default:
7510                 return ETH_RSS_RETA_SIZE_128;
7511         }
7512 }
7513
7514 uint32_t
7515 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7516         switch (mac_type) {
7517         case ixgbe_mac_X550:
7518         case ixgbe_mac_X550EM_x:
7519         case ixgbe_mac_X550EM_a:
7520                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7521                         return IXGBE_RETA(reta_idx >> 2);
7522                 else
7523                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7524         case ixgbe_mac_X550_vf:
7525         case ixgbe_mac_X550EM_x_vf:
7526         case ixgbe_mac_X550EM_a_vf:
7527                 return IXGBE_VFRETA(reta_idx >> 2);
7528         default:
7529                 return IXGBE_RETA(reta_idx >> 2);
7530         }
7531 }
7532
7533 uint32_t
7534 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7535         switch (mac_type) {
7536         case ixgbe_mac_X550_vf:
7537         case ixgbe_mac_X550EM_x_vf:
7538         case ixgbe_mac_X550EM_a_vf:
7539                 return IXGBE_VFMRQC;
7540         default:
7541                 return IXGBE_MRQC;
7542         }
7543 }
7544
7545 uint32_t
7546 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7547         switch (mac_type) {
7548         case ixgbe_mac_X550_vf:
7549         case ixgbe_mac_X550EM_x_vf:
7550         case ixgbe_mac_X550EM_a_vf:
7551                 return IXGBE_VFRSSRK(i);
7552         default:
7553                 return IXGBE_RSSRK(i);
7554         }
7555 }
7556
7557 bool
7558 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7559         switch (mac_type) {
7560         case ixgbe_mac_82599_vf:
7561         case ixgbe_mac_X540_vf:
7562                 return 0;
7563         default:
7564                 return 1;
7565         }
7566 }
7567
7568 static int
7569 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7570                         struct rte_eth_dcb_info *dcb_info)
7571 {
7572         struct ixgbe_dcb_config *dcb_config =
7573                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7574         struct ixgbe_dcb_tc_config *tc;
7575         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7576         uint8_t nb_tcs;
7577         uint8_t i, j;
7578
7579         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7580                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7581         else
7582                 dcb_info->nb_tcs = 1;
7583
7584         tc_queue = &dcb_info->tc_queue;
7585         nb_tcs = dcb_info->nb_tcs;
7586
7587         if (dcb_config->vt_mode) { /* vt is enabled*/
7588                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7589                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7590                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7591                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7592                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7593                         for (j = 0; j < nb_tcs; j++) {
7594                                 tc_queue->tc_rxq[0][j].base = j;
7595                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7596                                 tc_queue->tc_txq[0][j].base = j;
7597                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7598                         }
7599                 } else {
7600                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7601                                 for (j = 0; j < nb_tcs; j++) {
7602                                         tc_queue->tc_rxq[i][j].base =
7603                                                 i * nb_tcs + j;
7604                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7605                                         tc_queue->tc_txq[i][j].base =
7606                                                 i * nb_tcs + j;
7607                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7608                                 }
7609                         }
7610                 }
7611         } else { /* vt is disabled*/
7612                 struct rte_eth_dcb_rx_conf *rx_conf =
7613                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7614                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7615                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7616                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7617                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7618                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7619                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7620                         }
7621                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7622                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7623                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7624                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7625                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7626                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7627                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7628                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7629                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7630                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7631                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7632                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7633                         }
7634                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7635                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7636                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7637                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7638                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7639                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7640                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7641                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7642                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7643                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7644                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7645                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7646                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7647                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7648                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7649                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7650                 }
7651         }
7652         for (i = 0; i < dcb_info->nb_tcs; i++) {
7653                 tc = &dcb_config->tc_config[i];
7654                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7655         }
7656         return 0;
7657 }
7658
7659 /* Update e-tag ether type */
7660 static int
7661 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7662                             uint16_t ether_type)
7663 {
7664         uint32_t etag_etype;
7665
7666         if (hw->mac.type != ixgbe_mac_X550 &&
7667             hw->mac.type != ixgbe_mac_X550EM_x &&
7668             hw->mac.type != ixgbe_mac_X550EM_a) {
7669                 return -ENOTSUP;
7670         }
7671
7672         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7673         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7674         etag_etype |= ether_type;
7675         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7676         IXGBE_WRITE_FLUSH(hw);
7677
7678         return 0;
7679 }
7680
7681 /* Config l2 tunnel ether type */
7682 static int
7683 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7684                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7685 {
7686         int ret = 0;
7687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7688         struct ixgbe_l2_tn_info *l2_tn_info =
7689                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7690
7691         if (l2_tunnel == NULL)
7692                 return -EINVAL;
7693
7694         switch (l2_tunnel->l2_tunnel_type) {
7695         case RTE_L2_TUNNEL_TYPE_E_TAG:
7696                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7697                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7698                 break;
7699         default:
7700                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7701                 ret = -EINVAL;
7702                 break;
7703         }
7704
7705         return ret;
7706 }
7707
7708 /* Enable e-tag tunnel */
7709 static int
7710 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7711 {
7712         uint32_t etag_etype;
7713
7714         if (hw->mac.type != ixgbe_mac_X550 &&
7715             hw->mac.type != ixgbe_mac_X550EM_x &&
7716             hw->mac.type != ixgbe_mac_X550EM_a) {
7717                 return -ENOTSUP;
7718         }
7719
7720         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7721         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7722         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7723         IXGBE_WRITE_FLUSH(hw);
7724
7725         return 0;
7726 }
7727
7728 /* Enable l2 tunnel */
7729 static int
7730 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7731                            enum rte_eth_tunnel_type l2_tunnel_type)
7732 {
7733         int ret = 0;
7734         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7735         struct ixgbe_l2_tn_info *l2_tn_info =
7736                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7737
7738         switch (l2_tunnel_type) {
7739         case RTE_L2_TUNNEL_TYPE_E_TAG:
7740                 l2_tn_info->e_tag_en = TRUE;
7741                 ret = ixgbe_e_tag_enable(hw);
7742                 break;
7743         default:
7744                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7745                 ret = -EINVAL;
7746                 break;
7747         }
7748
7749         return ret;
7750 }
7751
7752 /* Disable e-tag tunnel */
7753 static int
7754 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7755 {
7756         uint32_t etag_etype;
7757
7758         if (hw->mac.type != ixgbe_mac_X550 &&
7759             hw->mac.type != ixgbe_mac_X550EM_x &&
7760             hw->mac.type != ixgbe_mac_X550EM_a) {
7761                 return -ENOTSUP;
7762         }
7763
7764         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7765         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7766         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7767         IXGBE_WRITE_FLUSH(hw);
7768
7769         return 0;
7770 }
7771
7772 /* Disable l2 tunnel */
7773 static int
7774 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7775                             enum rte_eth_tunnel_type l2_tunnel_type)
7776 {
7777         int ret = 0;
7778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7779         struct ixgbe_l2_tn_info *l2_tn_info =
7780                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7781
7782         switch (l2_tunnel_type) {
7783         case RTE_L2_TUNNEL_TYPE_E_TAG:
7784                 l2_tn_info->e_tag_en = FALSE;
7785                 ret = ixgbe_e_tag_disable(hw);
7786                 break;
7787         default:
7788                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7789                 ret = -EINVAL;
7790                 break;
7791         }
7792
7793         return ret;
7794 }
7795
7796 static int
7797 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7798                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7799 {
7800         int ret = 0;
7801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7802         uint32_t i, rar_entries;
7803         uint32_t rar_low, rar_high;
7804
7805         if (hw->mac.type != ixgbe_mac_X550 &&
7806             hw->mac.type != ixgbe_mac_X550EM_x &&
7807             hw->mac.type != ixgbe_mac_X550EM_a) {
7808                 return -ENOTSUP;
7809         }
7810
7811         rar_entries = ixgbe_get_num_rx_addrs(hw);
7812
7813         for (i = 1; i < rar_entries; i++) {
7814                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7815                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7816                 if ((rar_high & IXGBE_RAH_AV) &&
7817                     (rar_high & IXGBE_RAH_ADTYPE) &&
7818                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7819                      l2_tunnel->tunnel_id)) {
7820                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7821                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7822
7823                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7824
7825                         return ret;
7826                 }
7827         }
7828
7829         return ret;
7830 }
7831
7832 static int
7833 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7834                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7835 {
7836         int ret = 0;
7837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7838         uint32_t i, rar_entries;
7839         uint32_t rar_low, rar_high;
7840
7841         if (hw->mac.type != ixgbe_mac_X550 &&
7842             hw->mac.type != ixgbe_mac_X550EM_x &&
7843             hw->mac.type != ixgbe_mac_X550EM_a) {
7844                 return -ENOTSUP;
7845         }
7846
7847         /* One entry for one tunnel. Try to remove potential existing entry. */
7848         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7849
7850         rar_entries = ixgbe_get_num_rx_addrs(hw);
7851
7852         for (i = 1; i < rar_entries; i++) {
7853                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7854                 if (rar_high & IXGBE_RAH_AV) {
7855                         continue;
7856                 } else {
7857                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7858                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7859                         rar_low = l2_tunnel->tunnel_id;
7860
7861                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7862                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7863
7864                         return ret;
7865                 }
7866         }
7867
7868         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7869                      " Please remove a rule before adding a new one.");
7870         return -EINVAL;
7871 }
7872
7873 static inline struct ixgbe_l2_tn_filter *
7874 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7875                           struct ixgbe_l2_tn_key *key)
7876 {
7877         int ret;
7878
7879         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7880         if (ret < 0)
7881                 return NULL;
7882
7883         return l2_tn_info->hash_map[ret];
7884 }
7885
7886 static inline int
7887 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7888                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7889 {
7890         int ret;
7891
7892         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7893                                &l2_tn_filter->key);
7894
7895         if (ret < 0) {
7896                 PMD_DRV_LOG(ERR,
7897                             "Failed to insert L2 tunnel filter"
7898                             " to hash table %d!",
7899                             ret);
7900                 return ret;
7901         }
7902
7903         l2_tn_info->hash_map[ret] = l2_tn_filter;
7904
7905         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7906
7907         return 0;
7908 }
7909
7910 static inline int
7911 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7912                           struct ixgbe_l2_tn_key *key)
7913 {
7914         int ret;
7915         struct ixgbe_l2_tn_filter *l2_tn_filter;
7916
7917         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7918
7919         if (ret < 0) {
7920                 PMD_DRV_LOG(ERR,
7921                             "No such L2 tunnel filter to delete %d!",
7922                             ret);
7923                 return ret;
7924         }
7925
7926         l2_tn_filter = l2_tn_info->hash_map[ret];
7927         l2_tn_info->hash_map[ret] = NULL;
7928
7929         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7930         rte_free(l2_tn_filter);
7931
7932         return 0;
7933 }
7934
7935 /* Add l2 tunnel filter */
7936 int
7937 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7938                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7939                                bool restore)
7940 {
7941         int ret;
7942         struct ixgbe_l2_tn_info *l2_tn_info =
7943                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7944         struct ixgbe_l2_tn_key key;
7945         struct ixgbe_l2_tn_filter *node;
7946
7947         if (!restore) {
7948                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7949                 key.tn_id = l2_tunnel->tunnel_id;
7950
7951                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7952
7953                 if (node) {
7954                         PMD_DRV_LOG(ERR,
7955                                     "The L2 tunnel filter already exists!");
7956                         return -EINVAL;
7957                 }
7958
7959                 node = rte_zmalloc("ixgbe_l2_tn",
7960                                    sizeof(struct ixgbe_l2_tn_filter),
7961                                    0);
7962                 if (!node)
7963                         return -ENOMEM;
7964
7965                 rte_memcpy(&node->key,
7966                                  &key,
7967                                  sizeof(struct ixgbe_l2_tn_key));
7968                 node->pool = l2_tunnel->pool;
7969                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7970                 if (ret < 0) {
7971                         rte_free(node);
7972                         return ret;
7973                 }
7974         }
7975
7976         switch (l2_tunnel->l2_tunnel_type) {
7977         case RTE_L2_TUNNEL_TYPE_E_TAG:
7978                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7979                 break;
7980         default:
7981                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7982                 ret = -EINVAL;
7983                 break;
7984         }
7985
7986         if ((!restore) && (ret < 0))
7987                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7988
7989         return ret;
7990 }
7991
7992 /* Delete l2 tunnel filter */
7993 int
7994 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7995                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7996 {
7997         int ret;
7998         struct ixgbe_l2_tn_info *l2_tn_info =
7999                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8000         struct ixgbe_l2_tn_key key;
8001
8002         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8003         key.tn_id = l2_tunnel->tunnel_id;
8004         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8005         if (ret < 0)
8006                 return ret;
8007
8008         switch (l2_tunnel->l2_tunnel_type) {
8009         case RTE_L2_TUNNEL_TYPE_E_TAG:
8010                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8011                 break;
8012         default:
8013                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8014                 ret = -EINVAL;
8015                 break;
8016         }
8017
8018         return ret;
8019 }
8020
8021 /**
8022  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8023  * @dev: pointer to rte_eth_dev structure
8024  * @filter_op:operation will be taken.
8025  * @arg: a pointer to specific structure corresponding to the filter_op
8026  */
8027 static int
8028 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8029                                   enum rte_filter_op filter_op,
8030                                   void *arg)
8031 {
8032         int ret;
8033
8034         if (filter_op == RTE_ETH_FILTER_NOP)
8035                 return 0;
8036
8037         if (arg == NULL) {
8038                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8039                             filter_op);
8040                 return -EINVAL;
8041         }
8042
8043         switch (filter_op) {
8044         case RTE_ETH_FILTER_ADD:
8045                 ret = ixgbe_dev_l2_tunnel_filter_add
8046                         (dev,
8047                          (struct rte_eth_l2_tunnel_conf *)arg,
8048                          FALSE);
8049                 break;
8050         case RTE_ETH_FILTER_DELETE:
8051                 ret = ixgbe_dev_l2_tunnel_filter_del
8052                         (dev,
8053                          (struct rte_eth_l2_tunnel_conf *)arg);
8054                 break;
8055         default:
8056                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8057                 ret = -EINVAL;
8058                 break;
8059         }
8060         return ret;
8061 }
8062
8063 static int
8064 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8065 {
8066         int ret = 0;
8067         uint32_t ctrl;
8068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8069
8070         if (hw->mac.type != ixgbe_mac_X550 &&
8071             hw->mac.type != ixgbe_mac_X550EM_x &&
8072             hw->mac.type != ixgbe_mac_X550EM_a) {
8073                 return -ENOTSUP;
8074         }
8075
8076         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8077         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8078         if (en)
8079                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8080         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8081
8082         return ret;
8083 }
8084
8085 /* Enable l2 tunnel forwarding */
8086 static int
8087 ixgbe_dev_l2_tunnel_forwarding_enable
8088         (struct rte_eth_dev *dev,
8089          enum rte_eth_tunnel_type l2_tunnel_type)
8090 {
8091         struct ixgbe_l2_tn_info *l2_tn_info =
8092                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8093         int ret = 0;
8094
8095         switch (l2_tunnel_type) {
8096         case RTE_L2_TUNNEL_TYPE_E_TAG:
8097                 l2_tn_info->e_tag_fwd_en = TRUE;
8098                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8099                 break;
8100         default:
8101                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8102                 ret = -EINVAL;
8103                 break;
8104         }
8105
8106         return ret;
8107 }
8108
8109 /* Disable l2 tunnel forwarding */
8110 static int
8111 ixgbe_dev_l2_tunnel_forwarding_disable
8112         (struct rte_eth_dev *dev,
8113          enum rte_eth_tunnel_type l2_tunnel_type)
8114 {
8115         struct ixgbe_l2_tn_info *l2_tn_info =
8116                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8117         int ret = 0;
8118
8119         switch (l2_tunnel_type) {
8120         case RTE_L2_TUNNEL_TYPE_E_TAG:
8121                 l2_tn_info->e_tag_fwd_en = FALSE;
8122                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8123                 break;
8124         default:
8125                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8126                 ret = -EINVAL;
8127                 break;
8128         }
8129
8130         return ret;
8131 }
8132
8133 static int
8134 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8135                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8136                              bool en)
8137 {
8138         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8139         int ret = 0;
8140         uint32_t vmtir, vmvir;
8141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8142
8143         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8144                 PMD_DRV_LOG(ERR,
8145                             "VF id %u should be less than %u",
8146                             l2_tunnel->vf_id,
8147                             pci_dev->max_vfs);
8148                 return -EINVAL;
8149         }
8150
8151         if (hw->mac.type != ixgbe_mac_X550 &&
8152             hw->mac.type != ixgbe_mac_X550EM_x &&
8153             hw->mac.type != ixgbe_mac_X550EM_a) {
8154                 return -ENOTSUP;
8155         }
8156
8157         if (en)
8158                 vmtir = l2_tunnel->tunnel_id;
8159         else
8160                 vmtir = 0;
8161
8162         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8163
8164         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8165         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8166         if (en)
8167                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8168         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8169
8170         return ret;
8171 }
8172
8173 /* Enable l2 tunnel tag insertion */
8174 static int
8175 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8176                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8177 {
8178         int ret = 0;
8179
8180         switch (l2_tunnel->l2_tunnel_type) {
8181         case RTE_L2_TUNNEL_TYPE_E_TAG:
8182                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8183                 break;
8184         default:
8185                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8186                 ret = -EINVAL;
8187                 break;
8188         }
8189
8190         return ret;
8191 }
8192
8193 /* Disable l2 tunnel tag insertion */
8194 static int
8195 ixgbe_dev_l2_tunnel_insertion_disable
8196         (struct rte_eth_dev *dev,
8197          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8198 {
8199         int ret = 0;
8200
8201         switch (l2_tunnel->l2_tunnel_type) {
8202         case RTE_L2_TUNNEL_TYPE_E_TAG:
8203                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8204                 break;
8205         default:
8206                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8207                 ret = -EINVAL;
8208                 break;
8209         }
8210
8211         return ret;
8212 }
8213
8214 static int
8215 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8216                              bool en)
8217 {
8218         int ret = 0;
8219         uint32_t qde;
8220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8221
8222         if (hw->mac.type != ixgbe_mac_X550 &&
8223             hw->mac.type != ixgbe_mac_X550EM_x &&
8224             hw->mac.type != ixgbe_mac_X550EM_a) {
8225                 return -ENOTSUP;
8226         }
8227
8228         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8229         if (en)
8230                 qde |= IXGBE_QDE_STRIP_TAG;
8231         else
8232                 qde &= ~IXGBE_QDE_STRIP_TAG;
8233         qde &= ~IXGBE_QDE_READ;
8234         qde |= IXGBE_QDE_WRITE;
8235         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8236
8237         return ret;
8238 }
8239
8240 /* Enable l2 tunnel tag stripping */
8241 static int
8242 ixgbe_dev_l2_tunnel_stripping_enable
8243         (struct rte_eth_dev *dev,
8244          enum rte_eth_tunnel_type l2_tunnel_type)
8245 {
8246         int ret = 0;
8247
8248         switch (l2_tunnel_type) {
8249         case RTE_L2_TUNNEL_TYPE_E_TAG:
8250                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8251                 break;
8252         default:
8253                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8254                 ret = -EINVAL;
8255                 break;
8256         }
8257
8258         return ret;
8259 }
8260
8261 /* Disable l2 tunnel tag stripping */
8262 static int
8263 ixgbe_dev_l2_tunnel_stripping_disable
8264         (struct rte_eth_dev *dev,
8265          enum rte_eth_tunnel_type l2_tunnel_type)
8266 {
8267         int ret = 0;
8268
8269         switch (l2_tunnel_type) {
8270         case RTE_L2_TUNNEL_TYPE_E_TAG:
8271                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8272                 break;
8273         default:
8274                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8275                 ret = -EINVAL;
8276                 break;
8277         }
8278
8279         return ret;
8280 }
8281
8282 /* Enable/disable l2 tunnel offload functions */
8283 static int
8284 ixgbe_dev_l2_tunnel_offload_set
8285         (struct rte_eth_dev *dev,
8286          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8287          uint32_t mask,
8288          uint8_t en)
8289 {
8290         int ret = 0;
8291
8292         if (l2_tunnel == NULL)
8293                 return -EINVAL;
8294
8295         ret = -EINVAL;
8296         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8297                 if (en)
8298                         ret = ixgbe_dev_l2_tunnel_enable(
8299                                 dev,
8300                                 l2_tunnel->l2_tunnel_type);
8301                 else
8302                         ret = ixgbe_dev_l2_tunnel_disable(
8303                                 dev,
8304                                 l2_tunnel->l2_tunnel_type);
8305         }
8306
8307         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8308                 if (en)
8309                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8310                                 dev,
8311                                 l2_tunnel);
8312                 else
8313                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8314                                 dev,
8315                                 l2_tunnel);
8316         }
8317
8318         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8319                 if (en)
8320                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8321                                 dev,
8322                                 l2_tunnel->l2_tunnel_type);
8323                 else
8324                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8325                                 dev,
8326                                 l2_tunnel->l2_tunnel_type);
8327         }
8328
8329         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8330                 if (en)
8331                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8332                                 dev,
8333                                 l2_tunnel->l2_tunnel_type);
8334                 else
8335                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8336                                 dev,
8337                                 l2_tunnel->l2_tunnel_type);
8338         }
8339
8340         return ret;
8341 }
8342
8343 static int
8344 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8345                         uint16_t port)
8346 {
8347         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8348         IXGBE_WRITE_FLUSH(hw);
8349
8350         return 0;
8351 }
8352
8353 /* There's only one register for VxLAN UDP port.
8354  * So, we cannot add several ports. Will update it.
8355  */
8356 static int
8357 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8358                      uint16_t port)
8359 {
8360         if (port == 0) {
8361                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8362                 return -EINVAL;
8363         }
8364
8365         return ixgbe_update_vxlan_port(hw, port);
8366 }
8367
8368 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8369  * UDP port, it must have a value.
8370  * So, will reset it to the original value 0.
8371  */
8372 static int
8373 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8374                      uint16_t port)
8375 {
8376         uint16_t cur_port;
8377
8378         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8379
8380         if (cur_port != port) {
8381                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8382                 return -EINVAL;
8383         }
8384
8385         return ixgbe_update_vxlan_port(hw, 0);
8386 }
8387
8388 /* Add UDP tunneling port */
8389 static int
8390 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8391                               struct rte_eth_udp_tunnel *udp_tunnel)
8392 {
8393         int ret = 0;
8394         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8395
8396         if (hw->mac.type != ixgbe_mac_X550 &&
8397             hw->mac.type != ixgbe_mac_X550EM_x &&
8398             hw->mac.type != ixgbe_mac_X550EM_a) {
8399                 return -ENOTSUP;
8400         }
8401
8402         if (udp_tunnel == NULL)
8403                 return -EINVAL;
8404
8405         switch (udp_tunnel->prot_type) {
8406         case RTE_TUNNEL_TYPE_VXLAN:
8407                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8408                 break;
8409
8410         case RTE_TUNNEL_TYPE_GENEVE:
8411         case RTE_TUNNEL_TYPE_TEREDO:
8412                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8413                 ret = -EINVAL;
8414                 break;
8415
8416         default:
8417                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8418                 ret = -EINVAL;
8419                 break;
8420         }
8421
8422         return ret;
8423 }
8424
8425 /* Remove UDP tunneling port */
8426 static int
8427 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8428                               struct rte_eth_udp_tunnel *udp_tunnel)
8429 {
8430         int ret = 0;
8431         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8432
8433         if (hw->mac.type != ixgbe_mac_X550 &&
8434             hw->mac.type != ixgbe_mac_X550EM_x &&
8435             hw->mac.type != ixgbe_mac_X550EM_a) {
8436                 return -ENOTSUP;
8437         }
8438
8439         if (udp_tunnel == NULL)
8440                 return -EINVAL;
8441
8442         switch (udp_tunnel->prot_type) {
8443         case RTE_TUNNEL_TYPE_VXLAN:
8444                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8445                 break;
8446         case RTE_TUNNEL_TYPE_GENEVE:
8447         case RTE_TUNNEL_TYPE_TEREDO:
8448                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8449                 ret = -EINVAL;
8450                 break;
8451         default:
8452                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8453                 ret = -EINVAL;
8454                 break;
8455         }
8456
8457         return ret;
8458 }
8459
8460 static int
8461 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8462 {
8463         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8464         int ret;
8465
8466         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8467         case IXGBE_SUCCESS:
8468                 ret = 0;
8469                 break;
8470         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8471                 ret = -ENOTSUP;
8472                 break;
8473         default:
8474                 ret = -EAGAIN;
8475                 break;
8476         }
8477
8478         return ret;
8479 }
8480
8481 static int
8482 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8483 {
8484         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8485         int ret;
8486
8487         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8488         case IXGBE_SUCCESS:
8489                 ret = 0;
8490                 break;
8491         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8492                 ret = -ENOTSUP;
8493                 break;
8494         default:
8495                 ret = -EAGAIN;
8496                 break;
8497         }
8498
8499         return ret;
8500 }
8501
8502 static int
8503 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8504 {
8505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8506         int ret;
8507         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8508
8509         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8510         case IXGBE_SUCCESS:
8511                 ret = 0;
8512                 break;
8513         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8514                 ret = -ENOTSUP;
8515                 break;
8516         default:
8517                 ret = -EAGAIN;
8518                 break;
8519         }
8520
8521         return ret;
8522 }
8523
8524 static int
8525 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8526 {
8527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8528         int ret;
8529
8530         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8531         case IXGBE_SUCCESS:
8532                 ret = 0;
8533                 break;
8534         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8535                 ret = -ENOTSUP;
8536                 break;
8537         default:
8538                 ret = -EAGAIN;
8539                 break;
8540         }
8541
8542         return ret;
8543 }
8544
8545 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8546 {
8547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8548         u32 in_msg = 0;
8549
8550         /* peek the message first */
8551         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8552
8553         /* PF reset VF event */
8554         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8555                 /* dummy mbx read to ack pf */
8556                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8557                         return;
8558                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8559                                               NULL);
8560         }
8561 }
8562
8563 static int
8564 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8565 {
8566         uint32_t eicr;
8567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8568         struct ixgbe_interrupt *intr =
8569                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8570         ixgbevf_intr_disable(dev);
8571
8572         /* read-on-clear nic registers here */
8573         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8574         intr->flags = 0;
8575
8576         /* only one misc vector supported - mailbox */
8577         eicr &= IXGBE_VTEICR_MASK;
8578         if (eicr == IXGBE_MISC_VEC_ID)
8579                 intr->flags |= IXGBE_FLAG_MAILBOX;
8580
8581         return 0;
8582 }
8583
8584 static int
8585 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8586 {
8587         struct ixgbe_interrupt *intr =
8588                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8589
8590         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8591                 ixgbevf_mbx_process(dev);
8592                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8593         }
8594
8595         ixgbevf_intr_enable(dev);
8596
8597         return 0;
8598 }
8599
8600 static void
8601 ixgbevf_dev_interrupt_handler(void *param)
8602 {
8603         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8604
8605         ixgbevf_dev_interrupt_get_status(dev);
8606         ixgbevf_dev_interrupt_action(dev);
8607 }
8608
8609 /**
8610  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8611  *  @hw: pointer to hardware structure
8612  *
8613  *  Stops the transmit data path and waits for the HW to internally empty
8614  *  the Tx security block
8615  **/
8616 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8617 {
8618 #define IXGBE_MAX_SECTX_POLL 40
8619
8620         int i;
8621         int sectxreg;
8622
8623         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8624         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8625         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8626         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8627                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8628                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8629                         break;
8630                 /* Use interrupt-safe sleep just in case */
8631                 usec_delay(1000);
8632         }
8633
8634         /* For informational purposes only */
8635         if (i >= IXGBE_MAX_SECTX_POLL)
8636                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8637                          "path fully disabled.  Continuing with init.");
8638
8639         return IXGBE_SUCCESS;
8640 }
8641
8642 /**
8643  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8644  *  @hw: pointer to hardware structure
8645  *
8646  *  Enables the transmit data path.
8647  **/
8648 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8649 {
8650         uint32_t sectxreg;
8651
8652         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8653         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8654         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8655         IXGBE_WRITE_FLUSH(hw);
8656
8657         return IXGBE_SUCCESS;
8658 }
8659
8660 /* restore n-tuple filter */
8661 static inline void
8662 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8663 {
8664         struct ixgbe_filter_info *filter_info =
8665                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8666         struct ixgbe_5tuple_filter *node;
8667
8668         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8669                 ixgbe_inject_5tuple_filter(dev, node);
8670         }
8671 }
8672
8673 /* restore ethernet type filter */
8674 static inline void
8675 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8676 {
8677         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8678         struct ixgbe_filter_info *filter_info =
8679                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8680         int i;
8681
8682         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8683                 if (filter_info->ethertype_mask & (1 << i)) {
8684                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8685                                         filter_info->ethertype_filters[i].etqf);
8686                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8687                                         filter_info->ethertype_filters[i].etqs);
8688                         IXGBE_WRITE_FLUSH(hw);
8689                 }
8690         }
8691 }
8692
8693 /* restore SYN filter */
8694 static inline void
8695 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8696 {
8697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8698         struct ixgbe_filter_info *filter_info =
8699                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8700         uint32_t synqf;
8701
8702         synqf = filter_info->syn_info;
8703
8704         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8705                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8706                 IXGBE_WRITE_FLUSH(hw);
8707         }
8708 }
8709
8710 /* restore L2 tunnel filter */
8711 static inline void
8712 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8713 {
8714         struct ixgbe_l2_tn_info *l2_tn_info =
8715                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8716         struct ixgbe_l2_tn_filter *node;
8717         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8718
8719         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8720                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8721                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8722                 l2_tn_conf.pool           = node->pool;
8723                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8724         }
8725 }
8726
8727 /* restore rss filter */
8728 static inline void
8729 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8730 {
8731         struct ixgbe_filter_info *filter_info =
8732                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8733
8734         if (filter_info->rss_info.conf.queue_num)
8735                 ixgbe_config_rss_filter(dev,
8736                         &filter_info->rss_info, TRUE);
8737 }
8738
8739 static int
8740 ixgbe_filter_restore(struct rte_eth_dev *dev)
8741 {
8742         ixgbe_ntuple_filter_restore(dev);
8743         ixgbe_ethertype_filter_restore(dev);
8744         ixgbe_syn_filter_restore(dev);
8745         ixgbe_fdir_filter_restore(dev);
8746         ixgbe_l2_tn_filter_restore(dev);
8747         ixgbe_rss_filter_restore(dev);
8748
8749         return 0;
8750 }
8751
8752 static void
8753 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8754 {
8755         struct ixgbe_l2_tn_info *l2_tn_info =
8756                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8758
8759         if (l2_tn_info->e_tag_en)
8760                 (void)ixgbe_e_tag_enable(hw);
8761
8762         if (l2_tn_info->e_tag_fwd_en)
8763                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8764
8765         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8766 }
8767
8768 /* remove all the n-tuple filters */
8769 void
8770 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8771 {
8772         struct ixgbe_filter_info *filter_info =
8773                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8774         struct ixgbe_5tuple_filter *p_5tuple;
8775
8776         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8777                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8778 }
8779
8780 /* remove all the ether type filters */
8781 void
8782 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8783 {
8784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8785         struct ixgbe_filter_info *filter_info =
8786                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8787         int i;
8788
8789         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8790                 if (filter_info->ethertype_mask & (1 << i) &&
8791                     !filter_info->ethertype_filters[i].conf) {
8792                         (void)ixgbe_ethertype_filter_remove(filter_info,
8793                                                             (uint8_t)i);
8794                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8795                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8796                         IXGBE_WRITE_FLUSH(hw);
8797                 }
8798         }
8799 }
8800
8801 /* remove the SYN filter */
8802 void
8803 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8804 {
8805         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8806         struct ixgbe_filter_info *filter_info =
8807                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8808
8809         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8810                 filter_info->syn_info = 0;
8811
8812                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8813                 IXGBE_WRITE_FLUSH(hw);
8814         }
8815 }
8816
8817 /* remove all the L2 tunnel filters */
8818 int
8819 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8820 {
8821         struct ixgbe_l2_tn_info *l2_tn_info =
8822                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8823         struct ixgbe_l2_tn_filter *l2_tn_filter;
8824         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8825         int ret = 0;
8826
8827         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8828                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8829                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8830                 l2_tn_conf.pool           = l2_tn_filter->pool;
8831                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8832                 if (ret < 0)
8833                         return ret;
8834         }
8835
8836         return 0;
8837 }
8838
8839 void
8840 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8841                                 struct ixgbe_macsec_setting *macsec_setting)
8842 {
8843         struct ixgbe_macsec_setting *macsec =
8844                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8845
8846         macsec->encrypt_en = macsec_setting->encrypt_en;
8847         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8848 }
8849
8850 void
8851 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8852 {
8853         struct ixgbe_macsec_setting *macsec =
8854                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8855
8856         macsec->encrypt_en = 0;
8857         macsec->replayprotect_en = 0;
8858 }
8859
8860 void
8861 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8862                                 struct ixgbe_macsec_setting *macsec_setting)
8863 {
8864         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8865         uint32_t ctrl;
8866         uint8_t en = macsec_setting->encrypt_en;
8867         uint8_t rp = macsec_setting->replayprotect_en;
8868
8869         /**
8870          * Workaround:
8871          * As no ixgbe_disable_sec_rx_path equivalent is
8872          * implemented for tx in the base code, and we are
8873          * not allowed to modify the base code in DPDK, so
8874          * just call the hand-written one directly for now.
8875          * The hardware support has been checked by
8876          * ixgbe_disable_sec_rx_path().
8877          */
8878         ixgbe_disable_sec_tx_path_generic(hw);
8879
8880         /* Enable Ethernet CRC (required by MACsec offload) */
8881         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8882         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8883         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8884
8885         /* Enable the TX and RX crypto engines */
8886         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8887         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8888         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8889
8890         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8891         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8892         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8893
8894         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8895         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8896         ctrl |= 0x3;
8897         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8898
8899         /* Enable SA lookup */
8900         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8901         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8902         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8903                      IXGBE_LSECTXCTRL_AUTH;
8904         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8905         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8906         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8907         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8908
8909         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8910         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8911         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8912         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8913         if (rp)
8914                 ctrl |= IXGBE_LSECRXCTRL_RP;
8915         else
8916                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8917         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8918
8919         /* Start the data paths */
8920         ixgbe_enable_sec_rx_path(hw);
8921         /**
8922          * Workaround:
8923          * As no ixgbe_enable_sec_rx_path equivalent is
8924          * implemented for tx in the base code, and we are
8925          * not allowed to modify the base code in DPDK, so
8926          * just call the hand-written one directly for now.
8927          */
8928         ixgbe_enable_sec_tx_path_generic(hw);
8929 }
8930
8931 void
8932 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8933 {
8934         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8935         uint32_t ctrl;
8936
8937         /**
8938          * Workaround:
8939          * As no ixgbe_disable_sec_rx_path equivalent is
8940          * implemented for tx in the base code, and we are
8941          * not allowed to modify the base code in DPDK, so
8942          * just call the hand-written one directly for now.
8943          * The hardware support has been checked by
8944          * ixgbe_disable_sec_rx_path().
8945          */
8946         ixgbe_disable_sec_tx_path_generic(hw);
8947
8948         /* Disable the TX and RX crypto engines */
8949         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8950         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8951         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8952
8953         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8954         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8955         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8956
8957         /* Disable SA lookup */
8958         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8959         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8960         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8961         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8962
8963         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8964         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8965         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8966         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8967
8968         /* Start the data paths */
8969         ixgbe_enable_sec_rx_path(hw);
8970         /**
8971          * Workaround:
8972          * As no ixgbe_enable_sec_rx_path equivalent is
8973          * implemented for tx in the base code, and we are
8974          * not allowed to modify the base code in DPDK, so
8975          * just call the hand-written one directly for now.
8976          */
8977         ixgbe_enable_sec_tx_path_generic(hw);
8978 }
8979
8980 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8981 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8982 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8983 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8984 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8985 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8986 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8987                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8988
8989 RTE_INIT(ixgbe_init_log)
8990 {
8991         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8992         if (ixgbe_logtype_init >= 0)
8993                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8994         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8995         if (ixgbe_logtype_driver >= 0)
8996                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8997 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8998         ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
8999         if (ixgbe_logtype_rx >= 0)
9000                 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9001 #endif
9002
9003 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9004         ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9005         if (ixgbe_logtype_tx >= 0)
9006                 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9007 #endif
9008
9009 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9010         ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9011         if (ixgbe_logtype_tx_free >= 0)
9012                 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);
9013 #endif
9014 }