drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Timer value included in XOFF frames. */
  63 #define IXGBE_FC_PAUSE 0x680
  64
  65 /*Default value of Max Rx Queue*/
  66 #define IXGBE_MAX_RX_QUEUE_NUM 128
  67
  68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  69 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  70 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  71
  72 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  73 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  74 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  75
  76 /*
  77  *  Default values for RX/TX configuration
  78  */
  79 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  80 #define IXGBE_DEFAULT_RX_PTHRESH      8
  81 #define IXGBE_DEFAULT_RX_HTHRESH      8
  82 #define IXGBE_DEFAULT_RX_WTHRESH      0
  83
  84 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  85 #define IXGBE_DEFAULT_TX_PTHRESH      32
  86 #define IXGBE_DEFAULT_TX_HTHRESH      0
  87 #define IXGBE_DEFAULT_TX_WTHRESH      0
  88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  89
  90 /* Bit shift and mask */
  91 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  92 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  93 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  94 #define IXGBE_8_BIT_MASK   UINT8_MAX
  95
  96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  97
  98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
  99
 100 /* Additional timesync values. */
 101 #define NSEC_PER_SEC             1000000000L
 102 #define IXGBE_INCVAL_10GB        0x66666666
 103 #define IXGBE_INCVAL_1GB         0x40000000
 104 #define IXGBE_INCVAL_100         0x50000000
 105 #define IXGBE_INCVAL_SHIFT_10GB  28
 106 #define IXGBE_INCVAL_SHIFT_1GB   24
 107 #define IXGBE_INCVAL_SHIFT_100   21
 108 #define IXGBE_INCVAL_SHIFT_82599 7
 109 #define IXGBE_INCPER_SHIFT_82599 24
 110
 111 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 115 #define IXGBE_ETAG_ETYPE                       0x00005084
 116 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 117 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 118 #define IXGBE_RAH_ADTYPE                       0x40000000
 119 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 120 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 123 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 124 #define IXGBE_VTEICR_MASK                      0x07
 125
 126 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 127 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 128
 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 148                                 int wait_to_complete);
 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 150                                 struct rte_eth_stats *stats);
 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 152                                 struct rte_eth_xstat *xstats, unsigned n);
 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 154                                   struct rte_eth_xstat *xstats, unsigned n);
 155 static int
 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 157                 uint64_t *values, unsigned int n);
 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 161         struct rte_eth_xstat_name *xstats_names,
 162         unsigned int size);
 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 164         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 165 static int ixgbe_dev_xstats_get_names_by_id(
 166         struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         const uint64_t *ids,
 169         unsigned int limit);
 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 171                                              uint16_t queue_id,
 172                                              uint8_t stat_idx,
 173                                              uint8_t is_rx);
 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 175                                  size_t fw_size);
 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 177                                struct rte_eth_dev_info *dev_info);
 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 180                                  struct rte_eth_dev_info *dev_info);
 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 182
 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 184                 uint16_t vlan_id, int on);
 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 186                                enum rte_vlan_type vlan_type,
 187                                uint16_t tpid_id);
 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 189                 uint16_t queue, bool on);
 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 191                 int on);
 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 193                                                   int mask);
 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 221 static void ixgbe_dev_interrupt_handler(void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 224
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                             uint16_t queue_id);
 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                              uint16_t queue_id);
 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                  uint8_t queue, uint8_t msix_vector);
 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 265
 266 /* For Eth VMDQ APIs support */
 267 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 268                 ether_addr * mac_addr, uint8_t on);
 269 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 270 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 271                 struct rte_eth_mirror_conf *mirror_conf,
 272                 uint8_t rule_id, uint8_t on);
 273 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 274                 uint8_t rule_id);
 275 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 276                                           uint16_t queue_id);
 277 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 278                                            uint16_t queue_id);
 279 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 280                                uint8_t queue, uint8_t msix_vector);
 281 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 282
 283 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 284                                 struct ether_addr *mac_addr,
 285                                 uint32_t index, uint32_t pool);
 286 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 287 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 288                                              struct ether_addr *mac_addr);
 289 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 290                         struct rte_eth_syn_filter *filter);
 291 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 292                         enum rte_filter_op filter_op,
 293                         void *arg);
 294 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 295                         struct ixgbe_5tuple_filter *filter);
 296 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 297                         struct ixgbe_5tuple_filter *filter);
 298 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ntuple_filter *filter);
 303 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 304                                 enum rte_filter_op filter_op,
 305                                 void *arg);
 306 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 307                         struct rte_eth_ethertype_filter *filter);
 308 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 309                      enum rte_filter_type filter_type,
 310                      enum rte_filter_op filter_op,
 311                      void *arg);
 312 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 313
 314 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 315                                       struct ether_addr *mc_addr_set,
 316                                       uint32_t nb_mc_addr);
 317 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 318                                    struct rte_eth_dcb_info *dcb_info);
 319
 320 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 321 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 322                             struct rte_dev_reg_info *regs);
 323 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 324 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 325                                 struct rte_dev_eeprom_info *eeprom);
 326 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 327                                 struct rte_dev_eeprom_info *eeprom);
 328
 329 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 330                                  struct rte_eth_dev_module_info *modinfo);
 331 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 332                                    struct rte_dev_eeprom_info *info);
 333
 334 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 336                                 struct rte_dev_reg_info *regs);
 337
 338 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 340 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 341                                             struct timespec *timestamp,
 342                                             uint32_t flags);
 343 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 344                                             struct timespec *timestamp);
 345 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 346 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 347                                    struct timespec *timestamp);
 348 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 349                                    const struct timespec *timestamp);
 350 static void ixgbevf_dev_interrupt_handler(void *param);
 351
 352 static int ixgbe_dev_l2_tunnel_eth_type_conf
 353         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 354 static int ixgbe_dev_l2_tunnel_offload_set
 355         (struct rte_eth_dev *dev,
 356          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 357          uint32_t mask,
 358          uint8_t en);
 359 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 360                                              enum rte_filter_op filter_op,
 361                                              void *arg);
 362
 363 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 364                                          struct rte_eth_udp_tunnel *udp_tunnel);
 365 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 366                                          struct rte_eth_udp_tunnel *udp_tunnel);
 367 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 368 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 369
 370 /*
 371  * Define VF Stats MACRO for Non "cleared on read" register
 372  */
 373 #define UPDATE_VF_STAT(reg, last, cur)                          \
 374 {                                                               \
 375         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 376         cur += (latest - last) & UINT_MAX;                      \
 377         last = latest;                                          \
 378 }
 379
 380 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 381 {                                                                \
 382         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 383         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 384         u64 latest = ((new_msb << 32) | new_lsb);                \
 385         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 386         last = latest;                                           \
 387 }
 388
 389 #define IXGBE_SET_HWSTRIP(h, q) do {\
 390                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 391                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 392                 (h)->bitmap[idx] |= 1 << bit;\
 393         } while (0)
 394
 395 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 396                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 397                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 398                 (h)->bitmap[idx] &= ~(1 << bit);\
 399         } while (0)
 400
 401 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (r) = (h)->bitmap[idx] >> bit & 1;\
 405         } while (0)
 406
 407 int ixgbe_logtype_init;
 408 int ixgbe_logtype_driver;
 409
 410 /*
 411  * The set of PCI devices this driver supports
 412  */
 413 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 463 #endif
 464         { .vendor_id = 0, /* sentinel */ },
 465 };
 466
 467 /*
 468  * The set of PCI devices this driver supports (for 82599 VF)
 469  */
 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 static const struct rte_eth_desc_lim rx_desc_lim = {
 485         .nb_max = IXGBE_MAX_RING_DESC,
 486         .nb_min = IXGBE_MIN_RING_DESC,
 487         .nb_align = IXGBE_RXD_ALIGN,
 488 };
 489
 490 static const struct rte_eth_desc_lim tx_desc_lim = {
 491         .nb_max = IXGBE_MAX_RING_DESC,
 492         .nb_min = IXGBE_MIN_RING_DESC,
 493         .nb_align = IXGBE_TXD_ALIGN,
 494         .nb_seg_max = IXGBE_TX_MAX_SEG,
 495         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 496 };
 497
 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 499         .dev_configure        = ixgbe_dev_configure,
 500         .dev_start            = ixgbe_dev_start,
 501         .dev_stop             = ixgbe_dev_stop,
 502         .dev_set_link_up    = ixgbe_dev_set_link_up,
 503         .dev_set_link_down  = ixgbe_dev_set_link_down,
 504         .dev_close            = ixgbe_dev_close,
 505         .dev_reset            = ixgbe_dev_reset,
 506         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 507         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 508         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 509         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 510         .link_update          = ixgbe_dev_link_update,
 511         .stats_get            = ixgbe_dev_stats_get,
 512         .xstats_get           = ixgbe_dev_xstats_get,
 513         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 514         .stats_reset          = ixgbe_dev_stats_reset,
 515         .xstats_reset         = ixgbe_dev_xstats_reset,
 516         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 517         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 518         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 519         .fw_version_get       = ixgbe_fw_version_get,
 520         .dev_infos_get        = ixgbe_dev_info_get,
 521         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 522         .mtu_set              = ixgbe_dev_mtu_set,
 523         .vlan_filter_set      = ixgbe_vlan_filter_set,
 524         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 525         .vlan_offload_set     = ixgbe_vlan_offload_set,
 526         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 527         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 528         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 529         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 530         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 531         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 532         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 533         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 534         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 535         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 536         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 537         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 538         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 539         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 540         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 541         .dev_led_on           = ixgbe_dev_led_on,
 542         .dev_led_off          = ixgbe_dev_led_off,
 543         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 544         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 545         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 546         .mac_addr_add         = ixgbe_add_rar,
 547         .mac_addr_remove      = ixgbe_remove_rar,
 548         .mac_addr_set         = ixgbe_set_default_mac_addr,
 549         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 550         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 551         .mirror_rule_set      = ixgbe_mirror_rule_set,
 552         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 553         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 554         .reta_update          = ixgbe_dev_rss_reta_update,
 555         .reta_query           = ixgbe_dev_rss_reta_query,
 556         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 557         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 558         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 559         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 560         .rxq_info_get         = ixgbe_rxq_info_get,
 561         .txq_info_get         = ixgbe_txq_info_get,
 562         .timesync_enable      = ixgbe_timesync_enable,
 563         .timesync_disable     = ixgbe_timesync_disable,
 564         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 566         .get_reg              = ixgbe_get_regs,
 567         .get_eeprom_length    = ixgbe_get_eeprom_length,
 568         .get_eeprom           = ixgbe_get_eeprom,
 569         .set_eeprom           = ixgbe_set_eeprom,
 570         .get_module_info      = ixgbe_get_module_info,
 571         .get_module_eeprom    = ixgbe_get_module_eeprom,
 572         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 573         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 574         .timesync_read_time   = ixgbe_timesync_read_time,
 575         .timesync_write_time  = ixgbe_timesync_write_time,
 576         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 577         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 578         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 579         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 580         .tm_ops_get           = ixgbe_tm_ops_get,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 600         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 601         .dev_infos_get        = ixgbevf_dev_info_get,
 602         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 603         .mtu_set              = ixgbevf_dev_set_mtu,
 604         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 605         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 606         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 607         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 608         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 609         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 610         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 611         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 612         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 613         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 614         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 615         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 616         .mac_addr_add         = ixgbevf_add_mac_addr,
 617         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 618         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 619         .rxq_info_get         = ixgbe_rxq_info_get,
 620         .txq_info_get         = ixgbe_txq_info_get,
 621         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 622         .get_reg              = ixgbevf_get_regs,
 623         .reta_update          = ixgbe_dev_rss_reta_update,
 624         .reta_query           = ixgbe_dev_rss_reta_query,
 625         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 626         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1052 {
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055         struct ixgbe_hw *hw =
1056                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057         struct ixgbe_vfta *shadow_vfta =
1058                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059         struct ixgbe_hwstrip *hwstrip =
1060                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061         struct ixgbe_dcb_config *dcb_config =
1062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063         struct ixgbe_filter_info *filter_info =
1064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065         struct ixgbe_bw_conf *bw_conf =
1066                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067         uint32_t ctrl_ext;
1068         uint16_t csum;
1069         int diag, i;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077
1078         /*
1079          * For secondary processes, we don't initialise any further as primary
1080          * has already done this work. Only check we don't need a different
1081          * RX and TX function.
1082          */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084                 struct ixgbe_tx_queue *txq;
1085                 /* TX queue function in primary, set by last queue initialized
1086                  * Tx queue may not initialized by primary process
1087                  */
1088                 if (eth_dev->data->tx_queues) {
1089                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090                         ixgbe_set_tx_function(eth_dev, txq);
1091                 } else {
1092                         /* Use default TX function if we get here */
1093                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094                                      "Using default TX function.");
1095                 }
1096
1097                 ixgbe_set_rx_function(eth_dev);
1098
1099                 return 0;
1100         }
1101
1102         rte_eth_copy_pci_info(eth_dev, pci_dev);
1103
1104         /* Vendor and Device ID need to be set before init of shared code */
1105         hw->device_id = pci_dev->id.device_id;
1106         hw->vendor_id = pci_dev->id.vendor_id;
1107         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108         hw->allow_unsupported_sfp = 1;
1109
1110         /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112         diag = ixgbe_bypass_init_shared_code(hw);
1113 #else
1114         diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116
1117         if (diag != IXGBE_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1119                 return -EIO;
1120         }
1121
1122         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1123                 PMD_INIT_LOG(ERR, "\nERROR: "
1124                         "Firmware recovery mode detected. Limiting functionality.\n"
1125                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1126                         "User Guide for details on firmware recovery mode.");
1127                 return -EIO;
1128         }
1129
1130         /* pick up the PCI bus settings for reporting later */
1131         ixgbe_get_bus_info(hw);
1132
1133         /* Unlock any pending hardware semaphore */
1134         ixgbe_swfw_lock_reset(hw);
1135
1136 #ifdef RTE_LIBRTE_SECURITY
1137         /* Initialize security_ctx only for primary process*/
1138         if (ixgbe_ipsec_ctx_create(eth_dev))
1139                 return -ENOMEM;
1140 #endif
1141
1142         /* Initialize DCB configuration*/
1143         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1144         ixgbe_dcb_init(hw, dcb_config);
1145         /* Get Hardware Flow Control setting */
1146         hw->fc.requested_mode = ixgbe_fc_full;
1147         hw->fc.current_mode = ixgbe_fc_full;
1148         hw->fc.pause_time = IXGBE_FC_PAUSE;
1149         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1150                 hw->fc.low_water[i] = IXGBE_FC_LO;
1151                 hw->fc.high_water[i] = IXGBE_FC_HI;
1152         }
1153         hw->fc.send_xon = 1;
1154
1155         /* Make sure we have a good EEPROM before we read from it */
1156         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1157         if (diag != IXGBE_SUCCESS) {
1158                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1159                 return -EIO;
1160         }
1161
1162 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1163         diag = ixgbe_bypass_init_hw(hw);
1164 #else
1165         diag = ixgbe_init_hw(hw);
1166 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1167
1168         /*
1169          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1170          * is called too soon after the kernel driver unbinding/binding occurs.
1171          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1172          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1173          * also called. See ixgbe_identify_phy_82599(). The reason for the
1174          * failure is not known, and only occuts when virtualisation features
1175          * are disabled in the bios. A delay of 100ms  was found to be enough by
1176          * trial-and-error, and is doubled to be safe.
1177          */
1178         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1179                 rte_delay_ms(200);
1180                 diag = ixgbe_init_hw(hw);
1181         }
1182
1183         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1184                 diag = IXGBE_SUCCESS;
1185
1186         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1187                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1188                              "LOM.  Please be aware there may be issues associated "
1189                              "with your hardware.");
1190                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1191                              "please contact your Intel or hardware representative "
1192                              "who provided you with this hardware.");
1193         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1194                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1195         if (diag) {
1196                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1197                 return -EIO;
1198         }
1199
1200         /* Reset the hw statistics */
1201         ixgbe_dev_stats_reset(eth_dev);
1202
1203         /* disable interrupt */
1204         ixgbe_disable_intr(hw);
1205
1206         /* reset mappings for queue statistics hw counters*/
1207         ixgbe_reset_qstat_mappings(hw);
1208
1209         /* Allocate memory for storing MAC addresses */
1210         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1211                                                hw->mac.num_rar_entries, 0);
1212         if (eth_dev->data->mac_addrs == NULL) {
1213                 PMD_INIT_LOG(ERR,
1214                              "Failed to allocate %u bytes needed to store "
1215                              "MAC addresses",
1216                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1217                 return -ENOMEM;
1218         }
1219         /* Copy the permanent MAC address */
1220         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1221                         &eth_dev->data->mac_addrs[0]);
1222
1223         /* Allocate memory for storing hash filter MAC addresses */
1224         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1225                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1226         if (eth_dev->data->hash_mac_addrs == NULL) {
1227                 PMD_INIT_LOG(ERR,
1228                              "Failed to allocate %d bytes needed to store MAC addresses",
1229                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1230                 return -ENOMEM;
1231         }
1232
1233         /* initialize the vfta */
1234         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1235
1236         /* initialize the hw strip bitmap*/
1237         memset(hwstrip, 0, sizeof(*hwstrip));
1238
1239         /* initialize PF if max_vfs not zero */
1240         ixgbe_pf_host_init(eth_dev);
1241
1242         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1243         /* let hardware know driver is loaded */
1244         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1245         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1246         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1247         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1248         IXGBE_WRITE_FLUSH(hw);
1249
1250         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1251                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1252                              (int) hw->mac.type, (int) hw->phy.type,
1253                              (int) hw->phy.sfp_type);
1254         else
1255                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1256                              (int) hw->mac.type, (int) hw->phy.type);
1257
1258         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1259                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1260                      pci_dev->id.device_id);
1261
1262         rte_intr_callback_register(intr_handle,
1263                                    ixgbe_dev_interrupt_handler, eth_dev);
1264
1265         /* enable uio/vfio intr/eventfd mapping */
1266         rte_intr_enable(intr_handle);
1267
1268         /* enable support intr */
1269         ixgbe_enable_intr(eth_dev);
1270
1271         /* initialize filter info */
1272         memset(filter_info, 0,
1273                sizeof(struct ixgbe_filter_info));
1274
1275         /* initialize 5tuple filter list */
1276         TAILQ_INIT(&filter_info->fivetuple_list);
1277
1278         /* initialize flow director filter list & hash */
1279         ixgbe_fdir_filter_init(eth_dev);
1280
1281         /* initialize l2 tunnel filter list & hash */
1282         ixgbe_l2_tn_filter_init(eth_dev);
1283
1284         /* initialize flow filter lists */
1285         ixgbe_filterlist_init();
1286
1287         /* initialize bandwidth configuration info */
1288         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1289
1290         /* initialize Traffic Manager configuration */
1291         ixgbe_tm_conf_init(eth_dev);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1298 {
1299         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1300         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1301         struct ixgbe_hw *hw;
1302         int retries = 0;
1303         int ret;
1304
1305         PMD_INIT_FUNC_TRACE();
1306
1307         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1308                 return 0;
1309
1310         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1311
1312         if (hw->adapter_stopped == 0)
1313                 ixgbe_dev_close(eth_dev);
1314
1315         eth_dev->dev_ops = NULL;
1316         eth_dev->rx_pkt_burst = NULL;
1317         eth_dev->tx_pkt_burst = NULL;
1318
1319         /* Unlock any pending hardware semaphore */
1320         ixgbe_swfw_lock_reset(hw);
1321
1322         /* disable uio intr before callback unregister */
1323         rte_intr_disable(intr_handle);
1324
1325         do {
1326                 ret = rte_intr_callback_unregister(intr_handle,
1327                                 ixgbe_dev_interrupt_handler, eth_dev);
1328                 if (ret >= 0) {
1329                         break;
1330                 } else if (ret != -EAGAIN) {
1331                         PMD_INIT_LOG(ERR,
1332                                 "intr callback unregister failed: %d",
1333                                 ret);
1334                         return ret;
1335                 }
1336                 rte_delay_ms(100);
1337         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1338
1339         /* uninitialize PF if max_vfs not zero */
1340         ixgbe_pf_host_uninit(eth_dev);
1341
1342         /* remove all the fdir filters & hash */
1343         ixgbe_fdir_filter_uninit(eth_dev);
1344
1345         /* remove all the L2 tunnel filters & hash */
1346         ixgbe_l2_tn_filter_uninit(eth_dev);
1347
1348         /* Remove all ntuple filters of the device */
1349         ixgbe_ntuple_filter_uninit(eth_dev);
1350
1351         /* clear all the filters list */
1352         ixgbe_filterlist_flush();
1353
1354         /* Remove all Traffic Manager configuration */
1355         ixgbe_tm_conf_uninit(eth_dev);
1356
1357 #ifdef RTE_LIBRTE_SECURITY
1358         rte_free(eth_dev->security_ctx);
1359 #endif
1360
1361         return 0;
1362 }
1363
1364 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1365 {
1366         struct ixgbe_filter_info *filter_info =
1367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1368         struct ixgbe_5tuple_filter *p_5tuple;
1369
1370         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1371                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1372                              p_5tuple,
1373                              entries);
1374                 rte_free(p_5tuple);
1375         }
1376         memset(filter_info->fivetuple_mask, 0,
1377                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1378
1379         return 0;
1380 }
1381
1382 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1383 {
1384         struct ixgbe_hw_fdir_info *fdir_info =
1385                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1386         struct ixgbe_fdir_filter *fdir_filter;
1387
1388                 if (fdir_info->hash_map)
1389                 rte_free(fdir_info->hash_map);
1390         if (fdir_info->hash_handle)
1391                 rte_hash_free(fdir_info->hash_handle);
1392
1393         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1394                 TAILQ_REMOVE(&fdir_info->fdir_list,
1395                              fdir_filter,
1396                              entries);
1397                 rte_free(fdir_filter);
1398         }
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_l2_tn_info *l2_tn_info =
1406                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1407         struct ixgbe_l2_tn_filter *l2_tn_filter;
1408
1409         if (l2_tn_info->hash_map)
1410                 rte_free(l2_tn_info->hash_map);
1411         if (l2_tn_info->hash_handle)
1412                 rte_hash_free(l2_tn_info->hash_handle);
1413
1414         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1415                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1416                              l2_tn_filter,
1417                              entries);
1418                 rte_free(l2_tn_filter);
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_hw_fdir_info *fdir_info =
1427                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1428         char fdir_hash_name[RTE_HASH_NAMESIZE];
1429         struct rte_hash_parameters fdir_hash_params = {
1430                 .name = fdir_hash_name,
1431                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1432                 .key_len = sizeof(union ixgbe_atr_input),
1433                 .hash_func = rte_hash_crc,
1434                 .hash_func_init_val = 0,
1435                 .socket_id = rte_socket_id(),
1436         };
1437
1438         TAILQ_INIT(&fdir_info->fdir_list);
1439         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1440                  "fdir_%s", eth_dev->device->name);
1441         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1442         if (!fdir_info->hash_handle) {
1443                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1444                 return -EINVAL;
1445         }
1446         fdir_info->hash_map = rte_zmalloc("ixgbe",
1447                                           sizeof(struct ixgbe_fdir_filter *) *
1448                                           IXGBE_MAX_FDIR_FILTER_NUM,
1449                                           0);
1450         if (!fdir_info->hash_map) {
1451                 PMD_INIT_LOG(ERR,
1452                              "Failed to allocate memory for fdir hash map!");
1453                 return -ENOMEM;
1454         }
1455         fdir_info->mask_added = FALSE;
1456
1457         return 0;
1458 }
1459
1460 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1461 {
1462         struct ixgbe_l2_tn_info *l2_tn_info =
1463                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1464         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1465         struct rte_hash_parameters l2_tn_hash_params = {
1466                 .name = l2_tn_hash_name,
1467                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1468                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1469                 .hash_func = rte_hash_crc,
1470                 .hash_func_init_val = 0,
1471                 .socket_id = rte_socket_id(),
1472         };
1473
1474         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1475         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1476                  "l2_tn_%s", eth_dev->device->name);
1477         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1478         if (!l2_tn_info->hash_handle) {
1479                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1480                 return -EINVAL;
1481         }
1482         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1483                                    sizeof(struct ixgbe_l2_tn_filter *) *
1484                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1485                                    0);
1486         if (!l2_tn_info->hash_map) {
1487                 PMD_INIT_LOG(ERR,
1488                         "Failed to allocate memory for L2 TN hash map!");
1489                 return -ENOMEM;
1490         }
1491         l2_tn_info->e_tag_en = FALSE;
1492         l2_tn_info->e_tag_fwd_en = FALSE;
1493         l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1494
1495         return 0;
1496 }
1497 /*
1498  * Negotiate mailbox API version with the PF.
1499  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1500  * Then we try to negotiate starting with the most recent one.
1501  * If all negotiation attempts fail, then we will proceed with
1502  * the default one (ixgbe_mbox_api_10).
1503  */
1504 static void
1505 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1506 {
1507         int32_t i;
1508
1509         /* start with highest supported, proceed down */
1510         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1511                 ixgbe_mbox_api_12,
1512                 ixgbe_mbox_api_11,
1513                 ixgbe_mbox_api_10,
1514         };
1515
1516         for (i = 0;
1517                         i != RTE_DIM(sup_ver) &&
1518                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1519                         i++)
1520                 ;
1521 }
1522
1523 static void
1524 generate_random_mac_addr(struct ether_addr *mac_addr)
1525 {
1526         uint64_t random;
1527
1528         /* Set Organizationally Unique Identifier (OUI) prefix. */
1529         mac_addr->addr_bytes[0] = 0x00;
1530         mac_addr->addr_bytes[1] = 0x09;
1531         mac_addr->addr_bytes[2] = 0xC0;
1532         /* Force indication of locally assigned MAC address. */
1533         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1534         /* Generate the last 3 bytes of the MAC address with a random number. */
1535         random = rte_rand();
1536         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1537 }
1538
1539 /*
1540  * Virtual Function device init
1541  */
1542 static int
1543 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1544 {
1545         int diag;
1546         uint32_t tc, tcs;
1547         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1549         struct ixgbe_hw *hw =
1550                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1551         struct ixgbe_vfta *shadow_vfta =
1552                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1553         struct ixgbe_hwstrip *hwstrip =
1554                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1555         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1556
1557         PMD_INIT_FUNC_TRACE();
1558
1559         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1560         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1561         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1562
1563         /* for secondary processes, we don't initialise any further as primary
1564          * has already done this work. Only check we don't need a different
1565          * RX function
1566          */
1567         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1568                 struct ixgbe_tx_queue *txq;
1569                 /* TX queue function in primary, set by last queue initialized
1570                  * Tx queue may not initialized by primary process
1571                  */
1572                 if (eth_dev->data->tx_queues) {
1573                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1574                         ixgbe_set_tx_function(eth_dev, txq);
1575                 } else {
1576                         /* Use default TX function if we get here */
1577                         PMD_INIT_LOG(NOTICE,
1578                                      "No TX queues configured yet. Using default TX function.");
1579                 }
1580
1581                 ixgbe_set_rx_function(eth_dev);
1582
1583                 return 0;
1584         }
1585
1586         rte_eth_copy_pci_info(eth_dev, pci_dev);
1587
1588         hw->device_id = pci_dev->id.device_id;
1589         hw->vendor_id = pci_dev->id.vendor_id;
1590         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1591
1592         /* initialize the vfta */
1593         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1594
1595         /* initialize the hw strip bitmap*/
1596         memset(hwstrip, 0, sizeof(*hwstrip));
1597
1598         /* Initialize the shared code (base driver) */
1599         diag = ixgbe_init_shared_code(hw);
1600         if (diag != IXGBE_SUCCESS) {
1601                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1602                 return -EIO;
1603         }
1604
1605         /* init_mailbox_params */
1606         hw->mbx.ops.init_params(hw);
1607
1608         /* Reset the hw statistics */
1609         ixgbevf_dev_stats_reset(eth_dev);
1610
1611         /* Disable the interrupts for VF */
1612         ixgbevf_intr_disable(eth_dev);
1613
1614         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1615         diag = hw->mac.ops.reset_hw(hw);
1616
1617         /*
1618          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1619          * the underlying PF driver has not assigned a MAC address to the VF.
1620          * In this case, assign a random MAC address.
1621          */
1622         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1623                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1624                 /*
1625                  * This error code will be propagated to the app by
1626                  * rte_eth_dev_reset, so use a public error code rather than
1627                  * the internal-only IXGBE_ERR_RESET_FAILED
1628                  */
1629                 return -EAGAIN;
1630         }
1631
1632         /* negotiate mailbox API version to use with the PF. */
1633         ixgbevf_negotiate_api(hw);
1634
1635         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1636         ixgbevf_get_queues(hw, &tcs, &tc);
1637
1638         /* Allocate memory for storing MAC addresses */
1639         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1640                                                hw->mac.num_rar_entries, 0);
1641         if (eth_dev->data->mac_addrs == NULL) {
1642                 PMD_INIT_LOG(ERR,
1643                              "Failed to allocate %u bytes needed to store "
1644                              "MAC addresses",
1645                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1646                 return -ENOMEM;
1647         }
1648
1649         /* Generate a random MAC address, if none was assigned by PF. */
1650         if (is_zero_ether_addr(perm_addr)) {
1651                 generate_random_mac_addr(perm_addr);
1652                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1653                 if (diag) {
1654                         rte_free(eth_dev->data->mac_addrs);
1655                         eth_dev->data->mac_addrs = NULL;
1656                         return diag;
1657                 }
1658                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1659                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1660                              "%02x:%02x:%02x:%02x:%02x:%02x",
1661                              perm_addr->addr_bytes[0],
1662                              perm_addr->addr_bytes[1],
1663                              perm_addr->addr_bytes[2],
1664                              perm_addr->addr_bytes[3],
1665                              perm_addr->addr_bytes[4],
1666                              perm_addr->addr_bytes[5]);
1667         }
1668
1669         /* Copy the permanent MAC address */
1670         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1671
1672         /* reset the hardware with the new settings */
1673         diag = hw->mac.ops.start_hw(hw);
1674         switch (diag) {
1675         case  0:
1676                 break;
1677
1678         default:
1679                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1680                 return -EIO;
1681         }
1682
1683         rte_intr_callback_register(intr_handle,
1684                                    ixgbevf_dev_interrupt_handler, eth_dev);
1685         rte_intr_enable(intr_handle);
1686         ixgbevf_intr_enable(eth_dev);
1687
1688         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1689                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1690                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1691
1692         return 0;
1693 }
1694
1695 /* Virtual Function device uninit */
1696
1697 static int
1698 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1699 {
1700         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1701         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1702         struct ixgbe_hw *hw;
1703
1704         PMD_INIT_FUNC_TRACE();
1705
1706         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1707                 return 0;
1708
1709         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1710
1711         if (hw->adapter_stopped == 0)
1712                 ixgbevf_dev_close(eth_dev);
1713
1714         eth_dev->dev_ops = NULL;
1715         eth_dev->rx_pkt_burst = NULL;
1716         eth_dev->tx_pkt_burst = NULL;
1717
1718         /* Disable the interrupts for VF */
1719         ixgbevf_intr_disable(eth_dev);
1720
1721         rte_intr_disable(intr_handle);
1722         rte_intr_callback_unregister(intr_handle,
1723                                      ixgbevf_dev_interrupt_handler, eth_dev);
1724
1725         return 0;
1726 }
1727
1728 static int
1729 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1730                 struct rte_pci_device *pci_dev)
1731 {
1732         char name[RTE_ETH_NAME_MAX_LEN];
1733         struct rte_eth_dev *pf_ethdev;
1734         struct rte_eth_devargs eth_da;
1735         int i, retval;
1736
1737         if (pci_dev->device.devargs) {
1738                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1739                                 &eth_da);
1740                 if (retval)
1741                         return retval;
1742         } else
1743                 memset(&eth_da, 0, sizeof(eth_da));
1744
1745         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1746                 sizeof(struct ixgbe_adapter),
1747                 eth_dev_pci_specific_init, pci_dev,
1748                 eth_ixgbe_dev_init, NULL);
1749
1750         if (retval || eth_da.nb_representor_ports < 1)
1751                 return retval;
1752
1753         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1754         if (pf_ethdev == NULL)
1755                 return -ENODEV;
1756
1757         /* probe VF representor ports */
1758         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1759                 struct ixgbe_vf_info *vfinfo;
1760                 struct ixgbe_vf_representor representor;
1761
1762                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1763                         pf_ethdev->data->dev_private);
1764                 if (vfinfo == NULL) {
1765                         PMD_DRV_LOG(ERR,
1766                                 "no virtual functions supported by PF");
1767                         break;
1768                 }
1769
1770                 representor.vf_id = eth_da.representor_ports[i];
1771                 representor.switch_domain_id = vfinfo->switch_domain_id;
1772                 representor.pf_ethdev = pf_ethdev;
1773
1774                 /* representor port net_bdf_port */
1775                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1776                         pci_dev->device.name,
1777                         eth_da.representor_ports[i]);
1778
1779                 retval = rte_eth_dev_create(&pci_dev->device, name,
1780                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1781                         ixgbe_vf_representor_init, &representor);
1782
1783                 if (retval)
1784                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1785                                 "representor %s.", name);
1786         }
1787
1788         return 0;
1789 }
1790
1791 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1792 {
1793         struct rte_eth_dev *ethdev;
1794
1795         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1796         if (!ethdev)
1797                 return -ENODEV;
1798
1799         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1800                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1801         else
1802                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1803 }
1804
1805 static struct rte_pci_driver rte_ixgbe_pmd = {
1806         .id_table = pci_id_ixgbe_map,
1807         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1808                      RTE_PCI_DRV_IOVA_AS_VA,
1809         .probe = eth_ixgbe_pci_probe,
1810         .remove = eth_ixgbe_pci_remove,
1811 };
1812
1813 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1814         struct rte_pci_device *pci_dev)
1815 {
1816         return rte_eth_dev_pci_generic_probe(pci_dev,
1817                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1818 }
1819
1820 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1821 {
1822         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1823 }
1824
1825 /*
1826  * virtual function driver struct
1827  */
1828 static struct rte_pci_driver rte_ixgbevf_pmd = {
1829         .id_table = pci_id_ixgbevf_map,
1830         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1831         .probe = eth_ixgbevf_pci_probe,
1832         .remove = eth_ixgbevf_pci_remove,
1833 };
1834
1835 static int
1836 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1837 {
1838         struct ixgbe_hw *hw =
1839                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         struct ixgbe_vfta *shadow_vfta =
1841                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1842         uint32_t vfta;
1843         uint32_t vid_idx;
1844         uint32_t vid_bit;
1845
1846         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1847         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1848         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1849         if (on)
1850                 vfta |= vid_bit;
1851         else
1852                 vfta &= ~vid_bit;
1853         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1854
1855         /* update local VFTA copy */
1856         shadow_vfta->vfta[vid_idx] = vfta;
1857
1858         return 0;
1859 }
1860
1861 static void
1862 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1863 {
1864         if (on)
1865                 ixgbe_vlan_hw_strip_enable(dev, queue);
1866         else
1867                 ixgbe_vlan_hw_strip_disable(dev, queue);
1868 }
1869
1870 static int
1871 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1872                     enum rte_vlan_type vlan_type,
1873                     uint16_t tpid)
1874 {
1875         struct ixgbe_hw *hw =
1876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877         int ret = 0;
1878         uint32_t reg;
1879         uint32_t qinq;
1880
1881         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1882         qinq &= IXGBE_DMATXCTL_GDV;
1883
1884         switch (vlan_type) {
1885         case ETH_VLAN_TYPE_INNER:
1886                 if (qinq) {
1887                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1888                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1889                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1890                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1891                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1892                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1893                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1894                 } else {
1895                         ret = -ENOTSUP;
1896                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1897                                     " by single VLAN");
1898                 }
1899                 break;
1900         case ETH_VLAN_TYPE_OUTER:
1901                 if (qinq) {
1902                         /* Only the high 16-bits is valid */
1903                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1904                                         IXGBE_EXVET_VET_EXT_SHIFT);
1905                 } else {
1906                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1907                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1908                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1909                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1910                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1911                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1912                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1913                 }
1914
1915                 break;
1916         default:
1917                 ret = -EINVAL;
1918                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1919                 break;
1920         }
1921
1922         return ret;
1923 }
1924
1925 void
1926 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1927 {
1928         struct ixgbe_hw *hw =
1929                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         uint32_t vlnctrl;
1931
1932         PMD_INIT_FUNC_TRACE();
1933
1934         /* Filter Table Disable */
1935         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1936         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1937
1938         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1939 }
1940
1941 void
1942 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1943 {
1944         struct ixgbe_hw *hw =
1945                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1946         struct ixgbe_vfta *shadow_vfta =
1947                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1948         uint32_t vlnctrl;
1949         uint16_t i;
1950
1951         PMD_INIT_FUNC_TRACE();
1952
1953         /* Filter Table Enable */
1954         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1955         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1956         vlnctrl |= IXGBE_VLNCTRL_VFE;
1957
1958         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1959
1960         /* write whatever is in local vfta copy */
1961         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1962                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1963 }
1964
1965 static void
1966 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1967 {
1968         struct ixgbe_hwstrip *hwstrip =
1969                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1970         struct ixgbe_rx_queue *rxq;
1971
1972         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1973                 return;
1974
1975         if (on)
1976                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1977         else
1978                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1979
1980         if (queue >= dev->data->nb_rx_queues)
1981                 return;
1982
1983         rxq = dev->data->rx_queues[queue];
1984
1985         if (on) {
1986                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1987                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1988         } else {
1989                 rxq->vlan_flags = PKT_RX_VLAN;
1990                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1991         }
1992 }
1993
1994 static void
1995 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1996 {
1997         struct ixgbe_hw *hw =
1998                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999         uint32_t ctrl;
2000
2001         PMD_INIT_FUNC_TRACE();
2002
2003         if (hw->mac.type == ixgbe_mac_82598EB) {
2004                 /* No queue level support */
2005                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2006                 return;
2007         }
2008
2009         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2010         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2011         ctrl &= ~IXGBE_RXDCTL_VME;
2012         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2013
2014         /* record those setting for HW strip per queue */
2015         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2016 }
2017
2018 static void
2019 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2020 {
2021         struct ixgbe_hw *hw =
2022                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023         uint32_t ctrl;
2024
2025         PMD_INIT_FUNC_TRACE();
2026
2027         if (hw->mac.type == ixgbe_mac_82598EB) {
2028                 /* No queue level supported */
2029                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2030                 return;
2031         }
2032
2033         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2034         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2035         ctrl |= IXGBE_RXDCTL_VME;
2036         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2037
2038         /* record those setting for HW strip per queue */
2039         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2040 }
2041
2042 static void
2043 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2044 {
2045         struct ixgbe_hw *hw =
2046                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2047         uint32_t ctrl;
2048
2049         PMD_INIT_FUNC_TRACE();
2050
2051         /* DMATXCTRL: Geric Double VLAN Disable */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2053         ctrl &= ~IXGBE_DMATXCTL_GDV;
2054         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2055
2056         /* CTRL_EXT: Global Double VLAN Disable */
2057         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2058         ctrl &= ~IXGBE_EXTENDED_VLAN;
2059         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2060
2061 }
2062
2063 static void
2064 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2065 {
2066         struct ixgbe_hw *hw =
2067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2068         uint32_t ctrl;
2069
2070         PMD_INIT_FUNC_TRACE();
2071
2072         /* DMATXCTRL: Geric Double VLAN Enable */
2073         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2074         ctrl |= IXGBE_DMATXCTL_GDV;
2075         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2076
2077         /* CTRL_EXT: Global Double VLAN Enable */
2078         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2079         ctrl |= IXGBE_EXTENDED_VLAN;
2080         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2081
2082         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2083         if (hw->mac.type == ixgbe_mac_X550 ||
2084             hw->mac.type == ixgbe_mac_X550EM_x ||
2085             hw->mac.type == ixgbe_mac_X550EM_a) {
2086                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2087                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2088                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2089         }
2090
2091         /*
2092          * VET EXT field in the EXVET register = 0x8100 by default
2093          * So no need to change. Same to VT field of DMATXCTL register
2094          */
2095 }
2096
2097 void
2098 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2099 {
2100         struct ixgbe_hw *hw =
2101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2103         uint32_t ctrl;
2104         uint16_t i;
2105         struct ixgbe_rx_queue *rxq;
2106         bool on;
2107
2108         PMD_INIT_FUNC_TRACE();
2109
2110         if (hw->mac.type == ixgbe_mac_82598EB) {
2111                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2112                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2113                         ctrl |= IXGBE_VLNCTRL_VME;
2114                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2115                 } else {
2116                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2117                         ctrl &= ~IXGBE_VLNCTRL_VME;
2118                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2119                 }
2120         } else {
2121                 /*
2122                  * Other 10G NIC, the VLAN strip can be setup
2123                  * per queue in RXDCTL
2124                  */
2125                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2126                         rxq = dev->data->rx_queues[i];
2127                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2128                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2129                                 ctrl |= IXGBE_RXDCTL_VME;
2130                                 on = TRUE;
2131                         } else {
2132                                 ctrl &= ~IXGBE_RXDCTL_VME;
2133                                 on = FALSE;
2134                         }
2135                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2136
2137                         /* record those setting for HW strip per queue */
2138                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2139                 }
2140         }
2141 }
2142
2143 static void
2144 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2145 {
2146         uint16_t i;
2147         struct rte_eth_rxmode *rxmode;
2148         struct ixgbe_rx_queue *rxq;
2149
2150         if (mask & ETH_VLAN_STRIP_MASK) {
2151                 rxmode = &dev->data->dev_conf.rxmode;
2152                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2153                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2154                                 rxq = dev->data->rx_queues[i];
2155                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2156                         }
2157                 else
2158                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                                 rxq = dev->data->rx_queues[i];
2160                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2161                         }
2162         }
2163 }
2164
2165 static int
2166 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2167 {
2168         struct rte_eth_rxmode *rxmode;
2169         rxmode = &dev->data->dev_conf.rxmode;
2170
2171         if (mask & ETH_VLAN_STRIP_MASK) {
2172                 ixgbe_vlan_hw_strip_config(dev);
2173         }
2174
2175         if (mask & ETH_VLAN_FILTER_MASK) {
2176                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2177                         ixgbe_vlan_hw_filter_enable(dev);
2178                 else
2179                         ixgbe_vlan_hw_filter_disable(dev);
2180         }
2181
2182         if (mask & ETH_VLAN_EXTEND_MASK) {
2183                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2184                         ixgbe_vlan_hw_extend_enable(dev);
2185                 else
2186                         ixgbe_vlan_hw_extend_disable(dev);
2187         }
2188
2189         return 0;
2190 }
2191
2192 static int
2193 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2194 {
2195         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2196
2197         ixgbe_vlan_offload_config(dev, mask);
2198
2199         return 0;
2200 }
2201
2202 static void
2203 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2204 {
2205         struct ixgbe_hw *hw =
2206                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2208         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2209
2210         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2211         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2212 }
2213
2214 static int
2215 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2216 {
2217         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2218
2219         switch (nb_rx_q) {
2220         case 1:
2221         case 2:
2222                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2223                 break;
2224         case 4:
2225                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2226                 break;
2227         default:
2228                 return -EINVAL;
2229         }
2230
2231         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2232                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2233         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2234                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2235         return 0;
2236 }
2237
2238 static int
2239 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2240 {
2241         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2243         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2244         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2245
2246         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2247                 /* check multi-queue mode */
2248                 switch (dev_conf->rxmode.mq_mode) {
2249                 case ETH_MQ_RX_VMDQ_DCB:
2250                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2251                         break;
2252                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2253                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2254                         PMD_INIT_LOG(ERR, "SRIOV active,"
2255                                         " unsupported mq_mode rx %d.",
2256                                         dev_conf->rxmode.mq_mode);
2257                         return -EINVAL;
2258                 case ETH_MQ_RX_RSS:
2259                 case ETH_MQ_RX_VMDQ_RSS:
2260                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2261                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2262                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2263                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2264                                                 " invalid queue number"
2265                                                 " for VMDQ RSS, allowed"
2266                                                 " value are 1, 2 or 4.");
2267                                         return -EINVAL;
2268                                 }
2269                         break;
2270                 case ETH_MQ_RX_VMDQ_ONLY:
2271                 case ETH_MQ_RX_NONE:
2272                         /* if nothing mq mode configure, use default scheme */
2273                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2274                         break;
2275                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2276                         /* SRIOV only works in VMDq enable mode */
2277                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2278                                         " wrong mq_mode rx %d.",
2279                                         dev_conf->rxmode.mq_mode);
2280                         return -EINVAL;
2281                 }
2282
2283                 switch (dev_conf->txmode.mq_mode) {
2284                 case ETH_MQ_TX_VMDQ_DCB:
2285                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2286                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2287                         break;
2288                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2289                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2290                         break;
2291                 }
2292
2293                 /* check valid queue number */
2294                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2295                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2296                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2297                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2298                                         " must be less than or equal to %d.",
2299                                         nb_rx_q, nb_tx_q,
2300                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2301                         return -EINVAL;
2302                 }
2303         } else {
2304                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2305                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2306                                           " not supported.");
2307                         return -EINVAL;
2308                 }
2309                 /* check configuration for vmdb+dcb mode */
2310                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2311                         const struct rte_eth_vmdq_dcb_conf *conf;
2312
2313                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2315                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2319                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2320                                conf->nb_queue_pools == ETH_32_POOLS)) {
2321                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2322                                                 " nb_queue_pools must be %d or %d.",
2323                                                 ETH_16_POOLS, ETH_32_POOLS);
2324                                 return -EINVAL;
2325                         }
2326                 }
2327                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2328                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2329
2330                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2331                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2332                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2333                                 return -EINVAL;
2334                         }
2335                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2336                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2337                                conf->nb_queue_pools == ETH_32_POOLS)) {
2338                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2339                                                 " nb_queue_pools != %d and"
2340                                                 " nb_queue_pools != %d.",
2341                                                 ETH_16_POOLS, ETH_32_POOLS);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345
2346                 /* For DCB mode check our configuration before we go further */
2347                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2348                         const struct rte_eth_dcb_rx_conf *conf;
2349
2350                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2351                         if (!(conf->nb_tcs == ETH_4_TCS ||
2352                                conf->nb_tcs == ETH_8_TCS)) {
2353                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2354                                                 " and nb_tcs != %d.",
2355                                                 ETH_4_TCS, ETH_8_TCS);
2356                                 return -EINVAL;
2357                         }
2358                 }
2359
2360                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2361                         const struct rte_eth_dcb_tx_conf *conf;
2362
2363                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2364                         if (!(conf->nb_tcs == ETH_4_TCS ||
2365                                conf->nb_tcs == ETH_8_TCS)) {
2366                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2367                                                 " and nb_tcs != %d.",
2368                                                 ETH_4_TCS, ETH_8_TCS);
2369                                 return -EINVAL;
2370                         }
2371                 }
2372
2373                 /*
2374                  * When DCB/VT is off, maximum number of queues changes,
2375                  * except for 82598EB, which remains constant.
2376                  */
2377                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2378                                 hw->mac.type != ixgbe_mac_82598EB) {
2379                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2380                                 PMD_INIT_LOG(ERR,
2381                                              "Neither VT nor DCB are enabled, "
2382                                              "nb_tx_q > %d.",
2383                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2384                                 return -EINVAL;
2385                         }
2386                 }
2387         }
2388         return 0;
2389 }
2390
2391 static int
2392 ixgbe_dev_configure(struct rte_eth_dev *dev)
2393 {
2394         struct ixgbe_interrupt *intr =
2395                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2396         struct ixgbe_adapter *adapter =
2397                 (struct ixgbe_adapter *)dev->data->dev_private;
2398         int ret;
2399
2400         PMD_INIT_FUNC_TRACE();
2401         /* multipe queue mode checking */
2402         ret  = ixgbe_check_mq_mode(dev);
2403         if (ret != 0) {
2404                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2405                             ret);
2406                 return ret;
2407         }
2408
2409         /* set flag to update link status after init */
2410         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2411
2412         /*
2413          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2414          * allocation or vector Rx preconditions we will reset it.
2415          */
2416         adapter->rx_bulk_alloc_allowed = true;
2417         adapter->rx_vec_allowed = true;
2418
2419         return 0;
2420 }
2421
2422 static void
2423 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2424 {
2425         struct ixgbe_hw *hw =
2426                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2427         struct ixgbe_interrupt *intr =
2428                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2429         uint32_t gpie;
2430
2431         /* only set up it on X550EM_X */
2432         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2433                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2434                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2435                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2436                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2437                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2438         }
2439 }
2440
2441 int
2442 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2443                         uint16_t tx_rate, uint64_t q_msk)
2444 {
2445         struct ixgbe_hw *hw;
2446         struct ixgbe_vf_info *vfinfo;
2447         struct rte_eth_link link;
2448         uint8_t  nb_q_per_pool;
2449         uint32_t queue_stride;
2450         uint32_t queue_idx, idx = 0, vf_idx;
2451         uint32_t queue_end;
2452         uint16_t total_rate = 0;
2453         struct rte_pci_device *pci_dev;
2454
2455         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2456         rte_eth_link_get_nowait(dev->data->port_id, &link);
2457
2458         if (vf >= pci_dev->max_vfs)
2459                 return -EINVAL;
2460
2461         if (tx_rate > link.link_speed)
2462                 return -EINVAL;
2463
2464         if (q_msk == 0)
2465                 return 0;
2466
2467         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2469         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2470         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2471         queue_idx = vf * queue_stride;
2472         queue_end = queue_idx + nb_q_per_pool - 1;
2473         if (queue_end >= hw->mac.max_tx_queues)
2474                 return -EINVAL;
2475
2476         if (vfinfo) {
2477                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2478                         if (vf_idx == vf)
2479                                 continue;
2480                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2481                                 idx++)
2482                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2483                 }
2484         } else {
2485                 return -EINVAL;
2486         }
2487
2488         /* Store tx_rate for this vf. */
2489         for (idx = 0; idx < nb_q_per_pool; idx++) {
2490                 if (((uint64_t)0x1 << idx) & q_msk) {
2491                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2492                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2493                         total_rate += tx_rate;
2494                 }
2495         }
2496
2497         if (total_rate > dev->data->dev_link.link_speed) {
2498                 /* Reset stored TX rate of the VF if it causes exceed
2499                  * link speed.
2500                  */
2501                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2502                 return -EINVAL;
2503         }
2504
2505         /* Set RTTBCNRC of each queue/pool for vf X  */
2506         for (; queue_idx <= queue_end; queue_idx++) {
2507                 if (0x1 & q_msk)
2508                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2509                 q_msk = q_msk >> 1;
2510         }
2511
2512         return 0;
2513 }
2514
2515 /*
2516  * Configure device link speed and setup link.
2517  * It returns 0 on success.
2518  */
2519 static int
2520 ixgbe_dev_start(struct rte_eth_dev *dev)
2521 {
2522         struct ixgbe_hw *hw =
2523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2524         struct ixgbe_vf_info *vfinfo =
2525                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2526         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2527         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2528         uint32_t intr_vector = 0;
2529         int err, link_up = 0, negotiate = 0;
2530         uint32_t speed = 0;
2531         uint32_t allowed_speeds = 0;
2532         int mask = 0;
2533         int status;
2534         uint16_t vf, idx;
2535         uint32_t *link_speeds;
2536         struct ixgbe_tm_conf *tm_conf =
2537                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2538
2539         PMD_INIT_FUNC_TRACE();
2540
2541         /* IXGBE devices don't support:
2542         *    - half duplex (checked afterwards for valid speeds)
2543         *    - fixed speed: TODO implement
2544         */
2545         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2546                 PMD_INIT_LOG(ERR,
2547                 "Invalid link_speeds for port %u, fix speed not supported",
2548                                 dev->data->port_id);
2549                 return -EINVAL;
2550         }
2551
2552         /* Stop the link setup handler before resetting the HW. */
2553         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2554
2555         /* disable uio/vfio intr/eventfd mapping */
2556         rte_intr_disable(intr_handle);
2557
2558         /* stop adapter */
2559         hw->adapter_stopped = 0;
2560         ixgbe_stop_adapter(hw);
2561
2562         /* reinitialize adapter
2563          * this calls reset and start
2564          */
2565         status = ixgbe_pf_reset_hw(hw);
2566         if (status != 0)
2567                 return -1;
2568         hw->mac.ops.start_hw(hw);
2569         hw->mac.get_link_status = true;
2570
2571         /* configure PF module if SRIOV enabled */
2572         ixgbe_pf_host_configure(dev);
2573
2574         ixgbe_dev_phy_intr_setup(dev);
2575
2576         /* check and configure queue intr-vector mapping */
2577         if ((rte_intr_cap_multiple(intr_handle) ||
2578              !RTE_ETH_DEV_SRIOV(dev).active) &&
2579             dev->data->dev_conf.intr_conf.rxq != 0) {
2580                 intr_vector = dev->data->nb_rx_queues;
2581                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2582                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2583                                         IXGBE_MAX_INTR_QUEUE_NUM);
2584                         return -ENOTSUP;
2585                 }
2586                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2587                         return -1;
2588         }
2589
2590         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2591                 intr_handle->intr_vec =
2592                         rte_zmalloc("intr_vec",
2593                                     dev->data->nb_rx_queues * sizeof(int), 0);
2594                 if (intr_handle->intr_vec == NULL) {
2595                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2596                                      " intr_vec", dev->data->nb_rx_queues);
2597                         return -ENOMEM;
2598                 }
2599         }
2600
2601         /* confiugre msix for sleep until rx interrupt */
2602         ixgbe_configure_msix(dev);
2603
2604         /* initialize transmission unit */
2605         ixgbe_dev_tx_init(dev);
2606
2607         /* This can fail when allocating mbufs for descriptor rings */
2608         err = ixgbe_dev_rx_init(dev);
2609         if (err) {
2610                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2611                 goto error;
2612         }
2613
2614         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2615                 ETH_VLAN_EXTEND_MASK;
2616         err = ixgbe_vlan_offload_config(dev, mask);
2617         if (err) {
2618                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2619                 goto error;
2620         }
2621
2622         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2623                 /* Enable vlan filtering for VMDq */
2624                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2625         }
2626
2627         /* Configure DCB hw */
2628         ixgbe_configure_dcb(dev);
2629
2630         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2631                 err = ixgbe_fdir_configure(dev);
2632                 if (err)
2633                         goto error;
2634         }
2635
2636         /* Restore vf rate limit */
2637         if (vfinfo != NULL) {
2638                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2639                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2640                                 if (vfinfo[vf].tx_rate[idx] != 0)
2641                                         ixgbe_set_vf_rate_limit(
2642                                                 dev, vf,
2643                                                 vfinfo[vf].tx_rate[idx],
2644                                                 1 << idx);
2645         }
2646
2647         ixgbe_restore_statistics_mapping(dev);
2648
2649         err = ixgbe_dev_rxtx_start(dev);
2650         if (err < 0) {
2651                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2652                 goto error;
2653         }
2654
2655         /* Skip link setup if loopback mode is enabled for 82599. */
2656         if (hw->mac.type == ixgbe_mac_82599EB &&
2657                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2658                 goto skip_link_setup;
2659
2660         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2661                 err = hw->mac.ops.setup_sfp(hw);
2662                 if (err)
2663                         goto error;
2664         }
2665
2666         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2667                 /* Turn on the copper */
2668                 ixgbe_set_phy_power(hw, true);
2669         } else {
2670                 /* Turn on the laser */
2671                 ixgbe_enable_tx_laser(hw);
2672         }
2673
2674         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2675         if (err)
2676                 goto error;
2677         dev->data->dev_link.link_status = link_up;
2678
2679         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2680         if (err)
2681                 goto error;
2682
2683         switch (hw->mac.type) {
2684         case ixgbe_mac_X550:
2685         case ixgbe_mac_X550EM_x:
2686         case ixgbe_mac_X550EM_a:
2687                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2688                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2689                         ETH_LINK_SPEED_10G;
2690                 break;
2691         default:
2692                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2693                         ETH_LINK_SPEED_10G;
2694         }
2695
2696         link_speeds = &dev->data->dev_conf.link_speeds;
2697         if (*link_speeds & ~allowed_speeds) {
2698                 PMD_INIT_LOG(ERR, "Invalid link setting");
2699                 goto error;
2700         }
2701
2702         speed = 0x0;
2703         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2704                 switch (hw->mac.type) {
2705                 case ixgbe_mac_82598EB:
2706                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2707                         break;
2708                 case ixgbe_mac_82599EB:
2709                 case ixgbe_mac_X540:
2710                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2711                         break;
2712                 case ixgbe_mac_X550:
2713                 case ixgbe_mac_X550EM_x:
2714                 case ixgbe_mac_X550EM_a:
2715                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2716                         break;
2717                 default:
2718                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2719                 }
2720         } else {
2721                 if (*link_speeds & ETH_LINK_SPEED_10G)
2722                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2723                 if (*link_speeds & ETH_LINK_SPEED_5G)
2724                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2725                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2726                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2727                 if (*link_speeds & ETH_LINK_SPEED_1G)
2728                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2729                 if (*link_speeds & ETH_LINK_SPEED_100M)
2730                         speed |= IXGBE_LINK_SPEED_100_FULL;
2731         }
2732
2733         err = ixgbe_setup_link(hw, speed, link_up);
2734         if (err)
2735                 goto error;
2736
2737 skip_link_setup:
2738
2739         if (rte_intr_allow_others(intr_handle)) {
2740                 /* check if lsc interrupt is enabled */
2741                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2742                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2743                 else
2744                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2745                 ixgbe_dev_macsec_interrupt_setup(dev);
2746         } else {
2747                 rte_intr_callback_unregister(intr_handle,
2748                                              ixgbe_dev_interrupt_handler, dev);
2749                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2750                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2751                                      " no intr multiplex");
2752         }
2753
2754         /* check if rxq interrupt is enabled */
2755         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2756             rte_intr_dp_is_en(intr_handle))
2757                 ixgbe_dev_rxq_interrupt_setup(dev);
2758
2759         /* enable uio/vfio intr/eventfd mapping */
2760         rte_intr_enable(intr_handle);
2761
2762         /* resume enabled intr since hw reset */
2763         ixgbe_enable_intr(dev);
2764         ixgbe_l2_tunnel_conf(dev);
2765         ixgbe_filter_restore(dev);
2766
2767         if (tm_conf->root && !tm_conf->committed)
2768                 PMD_DRV_LOG(WARNING,
2769                             "please call hierarchy_commit() "
2770                             "before starting the port");
2771
2772         /*
2773          * Update link status right before return, because it may
2774          * start link configuration process in a separate thread.
2775          */
2776         ixgbe_dev_link_update(dev, 0);
2777
2778         return 0;
2779
2780 error:
2781         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2782         ixgbe_dev_clear_queues(dev);
2783         return -EIO;
2784 }
2785
2786 /*
2787  * Stop device: disable rx and tx functions to allow for reconfiguring.
2788  */
2789 static void
2790 ixgbe_dev_stop(struct rte_eth_dev *dev)
2791 {
2792         struct rte_eth_link link;
2793         struct ixgbe_hw *hw =
2794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795         struct ixgbe_vf_info *vfinfo =
2796                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2797         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2798         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2799         int vf;
2800         struct ixgbe_tm_conf *tm_conf =
2801                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2802
2803         PMD_INIT_FUNC_TRACE();
2804
2805         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2806
2807         /* disable interrupts */
2808         ixgbe_disable_intr(hw);
2809
2810         /* reset the NIC */
2811         ixgbe_pf_reset_hw(hw);
2812         hw->adapter_stopped = 0;
2813
2814         /* stop adapter */
2815         ixgbe_stop_adapter(hw);
2816
2817         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2818                 vfinfo[vf].clear_to_send = false;
2819
2820         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2821                 /* Turn off the copper */
2822                 ixgbe_set_phy_power(hw, false);
2823         } else {
2824                 /* Turn off the laser */
2825                 ixgbe_disable_tx_laser(hw);
2826         }
2827
2828         ixgbe_dev_clear_queues(dev);
2829
2830         /* Clear stored conf */
2831         dev->data->scattered_rx = 0;
2832         dev->data->lro = 0;
2833
2834         /* Clear recorded link status */
2835         memset(&link, 0, sizeof(link));
2836         rte_eth_linkstatus_set(dev, &link);
2837
2838         if (!rte_intr_allow_others(intr_handle))
2839                 /* resume to the default handler */
2840                 rte_intr_callback_register(intr_handle,
2841                                            ixgbe_dev_interrupt_handler,
2842                                            (void *)dev);
2843
2844         /* Clean datapath event and queue/vec mapping */
2845         rte_intr_efd_disable(intr_handle);
2846         if (intr_handle->intr_vec != NULL) {
2847                 rte_free(intr_handle->intr_vec);
2848                 intr_handle->intr_vec = NULL;
2849         }
2850
2851         /* reset hierarchy commit */
2852         tm_conf->committed = false;
2853 }
2854
2855 /*
2856  * Set device link up: enable tx.
2857  */
2858 static int
2859 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2860 {
2861         struct ixgbe_hw *hw =
2862                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2863         if (hw->mac.type == ixgbe_mac_82599EB) {
2864 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2865                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2866                         /* Not suported in bypass mode */
2867                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2868                                      "by device id 0x%x", hw->device_id);
2869                         return -ENOTSUP;
2870                 }
2871 #endif
2872         }
2873
2874         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2875                 /* Turn on the copper */
2876                 ixgbe_set_phy_power(hw, true);
2877         } else {
2878                 /* Turn on the laser */
2879                 ixgbe_enable_tx_laser(hw);
2880         }
2881
2882         return 0;
2883 }
2884
2885 /*
2886  * Set device link down: disable tx.
2887  */
2888 static int
2889 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2890 {
2891         struct ixgbe_hw *hw =
2892                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2893         if (hw->mac.type == ixgbe_mac_82599EB) {
2894 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2895                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2896                         /* Not suported in bypass mode */
2897                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2898                                      "by device id 0x%x", hw->device_id);
2899                         return -ENOTSUP;
2900                 }
2901 #endif
2902         }
2903
2904         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2905                 /* Turn off the copper */
2906                 ixgbe_set_phy_power(hw, false);
2907         } else {
2908                 /* Turn off the laser */
2909                 ixgbe_disable_tx_laser(hw);
2910         }
2911
2912         return 0;
2913 }
2914
2915 /*
2916  * Reset and stop device.
2917  */
2918 static void
2919 ixgbe_dev_close(struct rte_eth_dev *dev)
2920 {
2921         struct ixgbe_hw *hw =
2922                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923
2924         PMD_INIT_FUNC_TRACE();
2925
2926         ixgbe_pf_reset_hw(hw);
2927
2928         ixgbe_dev_stop(dev);
2929         hw->adapter_stopped = 1;
2930
2931         ixgbe_dev_free_queues(dev);
2932
2933         ixgbe_disable_pcie_master(hw);
2934
2935         /* reprogram the RAR[0] in case user changed it. */
2936         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2937 }
2938
2939 /*
2940  * Reset PF device.
2941  */
2942 static int
2943 ixgbe_dev_reset(struct rte_eth_dev *dev)
2944 {
2945         int ret;
2946
2947         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2948          * its VF to make them align with it. The detailed notification
2949          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2950          * To avoid unexpected behavior in VF, currently reset of PF with
2951          * SR-IOV activation is not supported. It might be supported later.
2952          */
2953         if (dev->data->sriov.active)
2954                 return -ENOTSUP;
2955
2956         ret = eth_ixgbe_dev_uninit(dev);
2957         if (ret)
2958                 return ret;
2959
2960         ret = eth_ixgbe_dev_init(dev, NULL);
2961
2962         return ret;
2963 }
2964
2965 static void
2966 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2967                            struct ixgbe_hw_stats *hw_stats,
2968                            struct ixgbe_macsec_stats *macsec_stats,
2969                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2970                            uint64_t *total_qprc, uint64_t *total_qprdc)
2971 {
2972         uint32_t bprc, lxon, lxoff, total;
2973         uint32_t delta_gprc = 0;
2974         unsigned i;
2975         /* Workaround for RX byte count not including CRC bytes when CRC
2976          * strip is enabled. CRC bytes are removed from counters when crc_strip
2977          * is disabled.
2978          */
2979         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2980                         IXGBE_HLREG0_RXCRCSTRP);
2981
2982         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2983         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2984         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2985         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2986
2987         for (i = 0; i < 8; i++) {
2988                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2989
2990                 /* global total per queue */
2991                 hw_stats->mpc[i] += mp;
2992                 /* Running comprehensive total for stats display */
2993                 *total_missed_rx += hw_stats->mpc[i];
2994                 if (hw->mac.type == ixgbe_mac_82598EB) {
2995                         hw_stats->rnbc[i] +=
2996                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2997                         hw_stats->pxonrxc[i] +=
2998                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2999                         hw_stats->pxoffrxc[i] +=
3000                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3001                 } else {
3002                         hw_stats->pxonrxc[i] +=
3003                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3004                         hw_stats->pxoffrxc[i] +=
3005                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3006                         hw_stats->pxon2offc[i] +=
3007                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3008                 }
3009                 hw_stats->pxontxc[i] +=
3010                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3011                 hw_stats->pxofftxc[i] +=
3012                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3013         }
3014         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3015                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3016                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3017                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3018
3019                 delta_gprc += delta_qprc;
3020
3021                 hw_stats->qprc[i] += delta_qprc;
3022                 hw_stats->qptc[i] += delta_qptc;
3023
3024                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3025                 hw_stats->qbrc[i] +=
3026                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3027                 if (crc_strip == 0)
3028                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3029
3030                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3031                 hw_stats->qbtc[i] +=
3032                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3033
3034                 hw_stats->qprdc[i] += delta_qprdc;
3035                 *total_qprdc += hw_stats->qprdc[i];
3036
3037                 *total_qprc += hw_stats->qprc[i];
3038                 *total_qbrc += hw_stats->qbrc[i];
3039         }
3040         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3041         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3042         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3043
3044         /*
3045          * An errata states that gprc actually counts good + missed packets:
3046          * Workaround to set gprc to summated queue packet receives
3047          */
3048         hw_stats->gprc = *total_qprc;
3049
3050         if (hw->mac.type != ixgbe_mac_82598EB) {
3051                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3052                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3053                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3054                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3055                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3056                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3057                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3058                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3059         } else {
3060                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3061                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3062                 /* 82598 only has a counter in the high register */
3063                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3064                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3065                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3066         }
3067         uint64_t old_tpr = hw_stats->tpr;
3068
3069         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3070         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3071
3072         if (crc_strip == 0)
3073                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3074
3075         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3076         hw_stats->gptc += delta_gptc;
3077         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3078         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3079
3080         /*
3081          * Workaround: mprc hardware is incorrectly counting
3082          * broadcasts, so for now we subtract those.
3083          */
3084         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3085         hw_stats->bprc += bprc;
3086         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3087         if (hw->mac.type == ixgbe_mac_82598EB)
3088                 hw_stats->mprc -= bprc;
3089
3090         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3091         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3092         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3093         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3094         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3095         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3096
3097         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3098         hw_stats->lxontxc += lxon;
3099         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3100         hw_stats->lxofftxc += lxoff;
3101         total = lxon + lxoff;
3102
3103         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3104         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3105         hw_stats->gptc -= total;
3106         hw_stats->mptc -= total;
3107         hw_stats->ptc64 -= total;
3108         hw_stats->gotc -= total * ETHER_MIN_LEN;
3109
3110         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3111         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3112         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3113         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3114         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3115         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3116         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3117         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3118         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3119         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3120         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3121         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3122         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3123         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3124         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3125         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3126         /* Only read FCOE on 82599 */
3127         if (hw->mac.type != ixgbe_mac_82598EB) {
3128                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3129                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3130                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3131                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3132                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3133         }
3134
3135         /* Flow Director Stats registers */
3136         if (hw->mac.type != ixgbe_mac_82598EB) {
3137                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3138                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3139                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3140                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3141                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3142                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3143                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3144                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3145                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3146                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3147         }
3148         /* MACsec Stats registers */
3149         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3150         macsec_stats->out_pkts_encrypted +=
3151                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3152         macsec_stats->out_pkts_protected +=
3153                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3154         macsec_stats->out_octets_encrypted +=
3155                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3156         macsec_stats->out_octets_protected +=
3157                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3158         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3159         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3160         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3161         macsec_stats->in_pkts_unknownsci +=
3162                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3163         macsec_stats->in_octets_decrypted +=
3164                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3165         macsec_stats->in_octets_validated +=
3166                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3167         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3168         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3169         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3170         for (i = 0; i < 2; i++) {
3171                 macsec_stats->in_pkts_ok +=
3172                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3173                 macsec_stats->in_pkts_invalid +=
3174                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3175                 macsec_stats->in_pkts_notvalid +=
3176                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3177         }
3178         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3179         macsec_stats->in_pkts_notusingsa +=
3180                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3181 }
3182
3183 /*
3184  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3185  */
3186 static int
3187 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3188 {
3189         struct ixgbe_hw *hw =
3190                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191         struct ixgbe_hw_stats *hw_stats =
3192                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3193         struct ixgbe_macsec_stats *macsec_stats =
3194                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3195                                 dev->data->dev_private);
3196         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3197         unsigned i;
3198
3199         total_missed_rx = 0;
3200         total_qbrc = 0;
3201         total_qprc = 0;
3202         total_qprdc = 0;
3203
3204         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3205                         &total_qbrc, &total_qprc, &total_qprdc);
3206
3207         if (stats == NULL)
3208                 return -EINVAL;
3209
3210         /* Fill out the rte_eth_stats statistics structure */
3211         stats->ipackets = total_qprc;
3212         stats->ibytes = total_qbrc;
3213         stats->opackets = hw_stats->gptc;
3214         stats->obytes = hw_stats->gotc;
3215
3216         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3217                 stats->q_ipackets[i] = hw_stats->qprc[i];
3218                 stats->q_opackets[i] = hw_stats->qptc[i];
3219                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3220                 stats->q_obytes[i] = hw_stats->qbtc[i];
3221                 stats->q_errors[i] = hw_stats->qprdc[i];
3222         }
3223
3224         /* Rx Errors */
3225         stats->imissed  = total_missed_rx;
3226         stats->ierrors  = hw_stats->crcerrs +
3227                           hw_stats->mspdc +
3228                           hw_stats->rlec +
3229                           hw_stats->ruc +
3230                           hw_stats->roc +
3231                           hw_stats->illerrc +
3232                           hw_stats->errbc +
3233                           hw_stats->rfc +
3234                           hw_stats->fccrc +
3235                           hw_stats->fclast;
3236
3237         /* Tx Errors */
3238         stats->oerrors  = 0;
3239         return 0;
3240 }
3241
3242 static void
3243 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3244 {
3245         struct ixgbe_hw_stats *stats =
3246                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3247
3248         /* HW registers are cleared on read */
3249         ixgbe_dev_stats_get(dev, NULL);
3250
3251         /* Reset software totals */
3252         memset(stats, 0, sizeof(*stats));
3253 }
3254
3255 /* This function calculates the number of xstats based on the current config */
3256 static unsigned
3257 ixgbe_xstats_calc_num(void) {
3258         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3259                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3260                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3261 }
3262
3263 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3264         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3265 {
3266         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3267         unsigned stat, i, count;
3268
3269         if (xstats_names != NULL) {
3270                 count = 0;
3271
3272                 /* Note: limit >= cnt_stats checked upstream
3273                  * in rte_eth_xstats_names()
3274                  */
3275
3276                 /* Extended stats from ixgbe_hw_stats */
3277                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3278                         snprintf(xstats_names[count].name,
3279                                 sizeof(xstats_names[count].name),
3280                                 "%s",
3281                                 rte_ixgbe_stats_strings[i].name);
3282                         count++;
3283                 }
3284
3285                 /* MACsec Stats */
3286                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3287                         snprintf(xstats_names[count].name,
3288                                 sizeof(xstats_names[count].name),
3289                                 "%s",
3290                                 rte_ixgbe_macsec_strings[i].name);
3291                         count++;
3292                 }
3293
3294                 /* RX Priority Stats */
3295                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3296                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3297                                 snprintf(xstats_names[count].name,
3298                                         sizeof(xstats_names[count].name),
3299                                         "rx_priority%u_%s", i,
3300                                         rte_ixgbe_rxq_strings[stat].name);
3301                                 count++;
3302                         }
3303                 }
3304
3305                 /* TX Priority Stats */
3306                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3307                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3308                                 snprintf(xstats_names[count].name,
3309                                         sizeof(xstats_names[count].name),
3310                                         "tx_priority%u_%s", i,
3311                                         rte_ixgbe_txq_strings[stat].name);
3312                                 count++;
3313                         }
3314                 }
3315         }
3316         return cnt_stats;
3317 }
3318
3319 static int ixgbe_dev_xstats_get_names_by_id(
3320         struct rte_eth_dev *dev,
3321         struct rte_eth_xstat_name *xstats_names,
3322         const uint64_t *ids,
3323         unsigned int limit)
3324 {
3325         if (!ids) {
3326                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3327                 unsigned int stat, i, count;
3328
3329                 if (xstats_names != NULL) {
3330                         count = 0;
3331
3332                         /* Note: limit >= cnt_stats checked upstream
3333                          * in rte_eth_xstats_names()
3334                          */
3335
3336                         /* Extended stats from ixgbe_hw_stats */
3337                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3338                                 snprintf(xstats_names[count].name,
3339                                         sizeof(xstats_names[count].name),
3340                                         "%s",
3341                                         rte_ixgbe_stats_strings[i].name);
3342                                 count++;
3343                         }
3344
3345                         /* MACsec Stats */
3346                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3347                                 snprintf(xstats_names[count].name,
3348                                         sizeof(xstats_names[count].name),
3349                                         "%s",
3350                                         rte_ixgbe_macsec_strings[i].name);
3351                                 count++;
3352                         }
3353
3354                         /* RX Priority Stats */
3355                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3356                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3357                                         snprintf(xstats_names[count].name,
3358                                             sizeof(xstats_names[count].name),
3359                                             "rx_priority%u_%s", i,
3360                                             rte_ixgbe_rxq_strings[stat].name);
3361                                         count++;
3362                                 }
3363                         }
3364
3365                         /* TX Priority Stats */
3366                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3367                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3368                                         snprintf(xstats_names[count].name,
3369                                             sizeof(xstats_names[count].name),
3370                                             "tx_priority%u_%s", i,
3371                                             rte_ixgbe_txq_strings[stat].name);
3372                                         count++;
3373                                 }
3374                         }
3375                 }
3376                 return cnt_stats;
3377         }
3378
3379         uint16_t i;
3380         uint16_t size = ixgbe_xstats_calc_num();
3381         struct rte_eth_xstat_name xstats_names_copy[size];
3382
3383         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3384                         size);
3385
3386         for (i = 0; i < limit; i++) {
3387                 if (ids[i] >= size) {
3388                         PMD_INIT_LOG(ERR, "id value isn't valid");
3389                         return -1;
3390                 }
3391                 strcpy(xstats_names[i].name,
3392                                 xstats_names_copy[ids[i]].name);
3393         }
3394         return limit;
3395 }
3396
3397 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3398         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3399 {
3400         unsigned i;
3401
3402         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3403                 return -ENOMEM;
3404
3405         if (xstats_names != NULL)
3406                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3407                         snprintf(xstats_names[i].name,
3408                                 sizeof(xstats_names[i].name),
3409                                 "%s", rte_ixgbevf_stats_strings[i].name);
3410         return IXGBEVF_NB_XSTATS;
3411 }
3412
3413 static int
3414 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3415                                          unsigned n)
3416 {
3417         struct ixgbe_hw *hw =
3418                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419         struct ixgbe_hw_stats *hw_stats =
3420                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3421         struct ixgbe_macsec_stats *macsec_stats =
3422                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3423                                 dev->data->dev_private);
3424         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3425         unsigned i, stat, count = 0;
3426
3427         count = ixgbe_xstats_calc_num();
3428
3429         if (n < count)
3430                 return count;
3431
3432         total_missed_rx = 0;
3433         total_qbrc = 0;
3434         total_qprc = 0;
3435         total_qprdc = 0;
3436
3437         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3438                         &total_qbrc, &total_qprc, &total_qprdc);
3439
3440         /* If this is a reset xstats is NULL, and we have cleared the
3441          * registers by reading them.
3442          */
3443         if (!xstats)
3444                 return 0;
3445
3446         /* Extended stats from ixgbe_hw_stats */
3447         count = 0;
3448         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3449                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3450                                 rte_ixgbe_stats_strings[i].offset);
3451                 xstats[count].id = count;
3452                 count++;
3453         }
3454
3455         /* MACsec Stats */
3456         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3457                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3458                                 rte_ixgbe_macsec_strings[i].offset);
3459                 xstats[count].id = count;
3460                 count++;
3461         }
3462
3463         /* RX Priority Stats */
3464         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3465                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3466                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3467                                         rte_ixgbe_rxq_strings[stat].offset +
3468                                         (sizeof(uint64_t) * i));
3469                         xstats[count].id = count;
3470                         count++;
3471                 }
3472         }
3473
3474         /* TX Priority Stats */
3475         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3476                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3477                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3478                                         rte_ixgbe_txq_strings[stat].offset +
3479                                         (sizeof(uint64_t) * i));
3480                         xstats[count].id = count;
3481                         count++;
3482                 }
3483         }
3484         return count;
3485 }
3486
3487 static int
3488 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3489                 uint64_t *values, unsigned int n)
3490 {
3491         if (!ids) {
3492                 struct ixgbe_hw *hw =
3493                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3494                 struct ixgbe_hw_stats *hw_stats =
3495                                 IXGBE_DEV_PRIVATE_TO_STATS(
3496                                                 dev->data->dev_private);
3497                 struct ixgbe_macsec_stats *macsec_stats =
3498                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3499                                         dev->data->dev_private);
3500                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3501                 unsigned int i, stat, count = 0;
3502
3503                 count = ixgbe_xstats_calc_num();
3504
3505                 if (!ids && n < count)
3506                         return count;
3507
3508                 total_missed_rx = 0;
3509                 total_qbrc = 0;
3510                 total_qprc = 0;
3511                 total_qprdc = 0;
3512
3513                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3514                                 &total_missed_rx, &total_qbrc, &total_qprc,
3515                                 &total_qprdc);
3516
3517                 /* If this is a reset xstats is NULL, and we have cleared the
3518                  * registers by reading them.
3519                  */
3520                 if (!ids && !values)
3521                         return 0;
3522
3523                 /* Extended stats from ixgbe_hw_stats */
3524                 count = 0;
3525                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3526                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3527                                         rte_ixgbe_stats_strings[i].offset);
3528                         count++;
3529                 }
3530
3531                 /* MACsec Stats */
3532                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3533                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3534                                         rte_ixgbe_macsec_strings[i].offset);
3535                         count++;
3536                 }
3537
3538                 /* RX Priority Stats */
3539                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3540                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3541                                 values[count] =
3542                                         *(uint64_t *)(((char *)hw_stats) +
3543                                         rte_ixgbe_rxq_strings[stat].offset +
3544                                         (sizeof(uint64_t) * i));
3545                                 count++;
3546                         }
3547                 }
3548
3549                 /* TX Priority Stats */
3550                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3551                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3552                                 values[count] =
3553                                         *(uint64_t *)(((char *)hw_stats) +
3554                                         rte_ixgbe_txq_strings[stat].offset +
3555                                         (sizeof(uint64_t) * i));
3556                                 count++;
3557                         }
3558                 }
3559                 return count;
3560         }
3561
3562         uint16_t i;
3563         uint16_t size = ixgbe_xstats_calc_num();
3564         uint64_t values_copy[size];
3565
3566         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3567
3568         for (i = 0; i < n; i++) {
3569                 if (ids[i] >= size) {
3570                         PMD_INIT_LOG(ERR, "id value isn't valid");
3571                         return -1;
3572                 }
3573                 values[i] = values_copy[ids[i]];
3574         }
3575         return n;
3576 }
3577
3578 static void
3579 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3580 {
3581         struct ixgbe_hw_stats *stats =
3582                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3583         struct ixgbe_macsec_stats *macsec_stats =
3584                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3585                                 dev->data->dev_private);
3586
3587         unsigned count = ixgbe_xstats_calc_num();
3588
3589         /* HW registers are cleared on read */
3590         ixgbe_dev_xstats_get(dev, NULL, count);
3591
3592         /* Reset software totals */
3593         memset(stats, 0, sizeof(*stats));
3594         memset(macsec_stats, 0, sizeof(*macsec_stats));
3595 }
3596
3597 static void
3598 ixgbevf_update_stats(struct rte_eth_dev *dev)
3599 {
3600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3601         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3602                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3603
3604         /* Good Rx packet, include VF loopback */
3605         UPDATE_VF_STAT(IXGBE_VFGPRC,
3606             hw_stats->last_vfgprc, hw_stats->vfgprc);
3607
3608         /* Good Rx octets, include VF loopback */
3609         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3610             hw_stats->last_vfgorc, hw_stats->vfgorc);
3611
3612         /* Good Tx packet, include VF loopback */
3613         UPDATE_VF_STAT(IXGBE_VFGPTC,
3614             hw_stats->last_vfgptc, hw_stats->vfgptc);
3615
3616         /* Good Tx octets, include VF loopback */
3617         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3618             hw_stats->last_vfgotc, hw_stats->vfgotc);
3619
3620         /* Rx Multicst Packet */
3621         UPDATE_VF_STAT(IXGBE_VFMPRC,
3622             hw_stats->last_vfmprc, hw_stats->vfmprc);
3623 }
3624
3625 static int
3626 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3627                        unsigned n)
3628 {
3629         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3630                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3631         unsigned i;
3632
3633         if (n < IXGBEVF_NB_XSTATS)
3634                 return IXGBEVF_NB_XSTATS;
3635
3636         ixgbevf_update_stats(dev);
3637
3638         if (!xstats)
3639                 return 0;
3640
3641         /* Extended stats */
3642         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3643                 xstats[i].id = i;
3644                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3645                         rte_ixgbevf_stats_strings[i].offset);
3646         }
3647
3648         return IXGBEVF_NB_XSTATS;
3649 }
3650
3651 static int
3652 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3653 {
3654         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3655                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3656
3657         ixgbevf_update_stats(dev);
3658
3659         if (stats == NULL)
3660                 return -EINVAL;
3661
3662         stats->ipackets = hw_stats->vfgprc;
3663         stats->ibytes = hw_stats->vfgorc;
3664         stats->opackets = hw_stats->vfgptc;
3665         stats->obytes = hw_stats->vfgotc;
3666         return 0;
3667 }
3668
3669 static void
3670 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3671 {
3672         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3673                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3674
3675         /* Sync HW register to the last stats */
3676         ixgbevf_dev_stats_get(dev, NULL);
3677
3678         /* reset HW current stats*/
3679         hw_stats->vfgprc = 0;
3680         hw_stats->vfgorc = 0;
3681         hw_stats->vfgptc = 0;
3682         hw_stats->vfgotc = 0;
3683 }
3684
3685 static int
3686 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3687 {
3688         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3689         u16 eeprom_verh, eeprom_verl;
3690         u32 etrack_id;
3691         int ret;
3692
3693         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3694         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3695
3696         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3697         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3698
3699         ret += 1; /* add the size of '\0' */
3700         if (fw_size < (u32)ret)
3701                 return ret;
3702         else
3703                 return 0;
3704 }
3705
3706 static void
3707 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3708 {
3709         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3710         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3711         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3712
3713         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3714         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3715         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3716                 /*
3717                  * When DCB/VT is off, maximum number of queues changes,
3718                  * except for 82598EB, which remains constant.
3719                  */
3720                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3721                                 hw->mac.type != ixgbe_mac_82598EB)
3722                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3723         }
3724         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3725         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3726         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3727         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3728         dev_info->max_vfs = pci_dev->max_vfs;
3729         if (hw->mac.type == ixgbe_mac_82598EB)
3730                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3731         else
3732                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3733         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3734         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3735         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3736                                      dev_info->rx_queue_offload_capa);
3737         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3738         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3739
3740         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3741                 .rx_thresh = {
3742                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3743                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3744                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3745                 },
3746                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3747                 .rx_drop_en = 0,
3748                 .offloads = 0,
3749         };
3750
3751         dev_info->default_txconf = (struct rte_eth_txconf) {
3752                 .tx_thresh = {
3753                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3754                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3755                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3756                 },
3757                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3758                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3759                 .offloads = 0,
3760         };
3761
3762         dev_info->rx_desc_lim = rx_desc_lim;
3763         dev_info->tx_desc_lim = tx_desc_lim;
3764
3765         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3766         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3767         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3768
3769         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3770         if (hw->mac.type == ixgbe_mac_X540 ||
3771             hw->mac.type == ixgbe_mac_X540_vf ||
3772             hw->mac.type == ixgbe_mac_X550 ||
3773             hw->mac.type == ixgbe_mac_X550_vf) {
3774                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3775         }
3776         if (hw->mac.type == ixgbe_mac_X550) {
3777                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3778                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3779         }
3780
3781         /* Driver-preferred Rx/Tx parameters */
3782         dev_info->default_rxportconf.burst_size = 32;
3783         dev_info->default_txportconf.burst_size = 32;
3784         dev_info->default_rxportconf.nb_queues = 1;
3785         dev_info->default_txportconf.nb_queues = 1;
3786         dev_info->default_rxportconf.ring_size = 256;
3787         dev_info->default_txportconf.ring_size = 256;
3788 }
3789
3790 static const uint32_t *
3791 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3792 {
3793         static const uint32_t ptypes[] = {
3794                 /* For non-vec functions,
3795                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3796                  * for vec functions,
3797                  * refers to _recv_raw_pkts_vec().
3798                  */
3799                 RTE_PTYPE_L2_ETHER,
3800                 RTE_PTYPE_L3_IPV4,
3801                 RTE_PTYPE_L3_IPV4_EXT,
3802                 RTE_PTYPE_L3_IPV6,
3803                 RTE_PTYPE_L3_IPV6_EXT,
3804                 RTE_PTYPE_L4_SCTP,
3805                 RTE_PTYPE_L4_TCP,
3806                 RTE_PTYPE_L4_UDP,
3807                 RTE_PTYPE_TUNNEL_IP,
3808                 RTE_PTYPE_INNER_L3_IPV6,
3809                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3810                 RTE_PTYPE_INNER_L4_TCP,
3811                 RTE_PTYPE_INNER_L4_UDP,
3812                 RTE_PTYPE_UNKNOWN
3813         };
3814
3815         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3816             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3817             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3818             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3819                 return ptypes;
3820
3821 #if defined(RTE_ARCH_X86)
3822         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3823             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3824                 return ptypes;
3825 #endif
3826         return NULL;
3827 }
3828
3829 static void
3830 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3831                      struct rte_eth_dev_info *dev_info)
3832 {
3833         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835
3836         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3837         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3838         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3839         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3840         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3841         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3842         dev_info->max_vfs = pci_dev->max_vfs;
3843         if (hw->mac.type == ixgbe_mac_82598EB)
3844                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3845         else
3846                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3847         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3848         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3849                                      dev_info->rx_queue_offload_capa);
3850         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3851         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3852
3853         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3854                 .rx_thresh = {
3855                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3856                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3857                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3858                 },
3859                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3860                 .rx_drop_en = 0,
3861                 .offloads = 0,
3862         };
3863
3864         dev_info->default_txconf = (struct rte_eth_txconf) {
3865                 .tx_thresh = {
3866                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3867                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3868                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3869                 },
3870                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3871                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3872                 .offloads = 0,
3873         };
3874
3875         dev_info->rx_desc_lim = rx_desc_lim;
3876         dev_info->tx_desc_lim = tx_desc_lim;
3877 }
3878
3879 static int
3880 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3881                    int *link_up, int wait_to_complete)
3882 {
3883         /**
3884          * for a quick link status checking, wait_to_compelet == 0,
3885          * skip PF link status checking
3886          */
3887         bool no_pflink_check = wait_to_complete == 0;
3888         struct ixgbe_mbx_info *mbx = &hw->mbx;
3889         struct ixgbe_mac_info *mac = &hw->mac;
3890         uint32_t links_reg, in_msg;
3891         int ret_val = 0;
3892
3893         /* If we were hit with a reset drop the link */
3894         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3895                 mac->get_link_status = true;
3896
3897         if (!mac->get_link_status)
3898                 goto out;
3899
3900         /* if link status is down no point in checking to see if pf is up */
3901         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3902         if (!(links_reg & IXGBE_LINKS_UP))
3903                 goto out;
3904
3905         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3906          * before the link status is correct
3907          */
3908         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3909                 int i;
3910
3911                 for (i = 0; i < 5; i++) {
3912                         rte_delay_us(100);
3913                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3914
3915                         if (!(links_reg & IXGBE_LINKS_UP))
3916                                 goto out;
3917                 }
3918         }
3919
3920         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3921         case IXGBE_LINKS_SPEED_10G_82599:
3922                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3923                 if (hw->mac.type >= ixgbe_mac_X550) {
3924                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3925                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3926                 }
3927                 break;
3928         case IXGBE_LINKS_SPEED_1G_82599:
3929                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3930                 break;
3931         case IXGBE_LINKS_SPEED_100_82599:
3932                 *speed = IXGBE_LINK_SPEED_100_FULL;
3933                 if (hw->mac.type == ixgbe_mac_X550) {
3934                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3935                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3936                 }
3937                 break;
3938         case IXGBE_LINKS_SPEED_10_X550EM_A:
3939                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3940                 /* Since Reserved in older MAC's */
3941                 if (hw->mac.type >= ixgbe_mac_X550)
3942                         *speed = IXGBE_LINK_SPEED_10_FULL;
3943                 break;
3944         default:
3945                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3946         }
3947
3948         if (no_pflink_check) {
3949                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3950                         mac->get_link_status = true;
3951                 else
3952                         mac->get_link_status = false;
3953
3954                 goto out;
3955         }
3956         /* if the read failed it could just be a mailbox collision, best wait
3957          * until we are called again and don't report an error
3958          */
3959         if (mbx->ops.read(hw, &in_msg, 1, 0))
3960                 goto out;
3961
3962         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3963                 /* msg is not CTS and is NACK we must have lost CTS status */
3964                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3965                         ret_val = -1;
3966                 goto out;
3967         }
3968
3969         /* the pf is talking, if we timed out in the past we reinit */
3970         if (!mbx->timeout) {
3971                 ret_val = -1;
3972                 goto out;
3973         }
3974
3975         /* if we passed all the tests above then the link is up and we no
3976          * longer need to check for link
3977          */
3978         mac->get_link_status = false;
3979
3980 out:
3981         *link_up = !mac->get_link_status;
3982         return ret_val;
3983 }
3984
3985 static void
3986 ixgbe_dev_setup_link_alarm_handler(void *param)
3987 {
3988         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3990         struct ixgbe_interrupt *intr =
3991                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3992         u32 speed;
3993         bool autoneg = false;
3994
3995         speed = hw->phy.autoneg_advertised;
3996         if (!speed)
3997                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3998
3999         ixgbe_setup_link(hw, speed, true);
4000
4001         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4002 }
4003
4004 /* return 0 means link status changed, -1 means not changed */
4005 int
4006 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4007                             int wait_to_complete, int vf)
4008 {
4009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4010         struct rte_eth_link link;
4011         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4012         struct ixgbe_interrupt *intr =
4013                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4014         int link_up;
4015         int diag;
4016         int wait = 1;
4017
4018         memset(&link, 0, sizeof(link));
4019         link.link_status = ETH_LINK_DOWN;
4020         link.link_speed = ETH_SPEED_NUM_NONE;
4021         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4022         link.link_autoneg = ETH_LINK_AUTONEG;
4023
4024         hw->mac.get_link_status = true;
4025
4026         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4027                 return rte_eth_linkstatus_set(dev, &link);
4028
4029         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4030         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4031                 wait = 0;
4032
4033         if (vf)
4034                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4035         else
4036                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4037
4038         if (diag != 0) {
4039                 link.link_speed = ETH_SPEED_NUM_100M;
4040                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4041                 return rte_eth_linkstatus_set(dev, &link);
4042         }
4043
4044         if (link_up == 0) {
4045                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4046                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4047                         rte_eal_alarm_set(10,
4048                                 ixgbe_dev_setup_link_alarm_handler, dev);
4049                 }
4050                 return rte_eth_linkstatus_set(dev, &link);
4051         }
4052
4053         link.link_status = ETH_LINK_UP;
4054         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4055
4056         switch (link_speed) {
4057         default:
4058         case IXGBE_LINK_SPEED_UNKNOWN:
4059                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4060                 link.link_speed = ETH_SPEED_NUM_100M;
4061                 break;
4062
4063         case IXGBE_LINK_SPEED_100_FULL:
4064                 link.link_speed = ETH_SPEED_NUM_100M;
4065                 break;
4066
4067         case IXGBE_LINK_SPEED_1GB_FULL:
4068                 link.link_speed = ETH_SPEED_NUM_1G;
4069                 break;
4070
4071         case IXGBE_LINK_SPEED_2_5GB_FULL:
4072                 link.link_speed = ETH_SPEED_NUM_2_5G;
4073                 break;
4074
4075         case IXGBE_LINK_SPEED_5GB_FULL:
4076                 link.link_speed = ETH_SPEED_NUM_5G;
4077                 break;
4078
4079         case IXGBE_LINK_SPEED_10GB_FULL:
4080                 link.link_speed = ETH_SPEED_NUM_10G;
4081                 break;
4082         }
4083
4084         return rte_eth_linkstatus_set(dev, &link);
4085 }
4086
4087 static int
4088 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4089 {
4090         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4091 }
4092
4093 static int
4094 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4095 {
4096         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4097 }
4098
4099 static void
4100 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4101 {
4102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4103         uint32_t fctrl;
4104
4105         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4106         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4107         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4108 }
4109
4110 static void
4111 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4112 {
4113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         uint32_t fctrl;
4115
4116         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4117         fctrl &= (~IXGBE_FCTRL_UPE);
4118         if (dev->data->all_multicast == 1)
4119                 fctrl |= IXGBE_FCTRL_MPE;
4120         else
4121                 fctrl &= (~IXGBE_FCTRL_MPE);
4122         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4123 }
4124
4125 static void
4126 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4127 {
4128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         uint32_t fctrl;
4130
4131         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4132         fctrl |= IXGBE_FCTRL_MPE;
4133         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4134 }
4135
4136 static void
4137 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4138 {
4139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4140         uint32_t fctrl;
4141
4142         if (dev->data->promiscuous == 1)
4143                 return; /* must remain in all_multicast mode */
4144
4145         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4146         fctrl &= (~IXGBE_FCTRL_MPE);
4147         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4148 }
4149
4150 /**
4151  * It clears the interrupt causes and enables the interrupt.
4152  * It will be called once only during nic initialized.
4153  *
4154  * @param dev
4155  *  Pointer to struct rte_eth_dev.
4156  * @param on
4157  *  Enable or Disable.
4158  *
4159  * @return
4160  *  - On success, zero.
4161  *  - On failure, a negative value.
4162  */
4163 static int
4164 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4165 {
4166         struct ixgbe_interrupt *intr =
4167                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4168
4169         ixgbe_dev_link_status_print(dev);
4170         if (on)
4171                 intr->mask |= IXGBE_EICR_LSC;
4172         else
4173                 intr->mask &= ~IXGBE_EICR_LSC;
4174
4175         return 0;
4176 }
4177
4178 /**
4179  * It clears the interrupt causes and enables the interrupt.
4180  * It will be called once only during nic initialized.
4181  *
4182  * @param dev
4183  *  Pointer to struct rte_eth_dev.
4184  *
4185  * @return
4186  *  - On success, zero.
4187  *  - On failure, a negative value.
4188  */
4189 static int
4190 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4191 {
4192         struct ixgbe_interrupt *intr =
4193                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4194
4195         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4196
4197         return 0;
4198 }
4199
4200 /**
4201  * It clears the interrupt causes and enables the interrupt.
4202  * It will be called once only during nic initialized.
4203  *
4204  * @param dev
4205  *  Pointer to struct rte_eth_dev.
4206  *
4207  * @return
4208  *  - On success, zero.
4209  *  - On failure, a negative value.
4210  */
4211 static int
4212 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4213 {
4214         struct ixgbe_interrupt *intr =
4215                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4216
4217         intr->mask |= IXGBE_EICR_LINKSEC;
4218
4219         return 0;
4220 }
4221
4222 /*
4223  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4224  *
4225  * @param dev
4226  *  Pointer to struct rte_eth_dev.
4227  *
4228  * @return
4229  *  - On success, zero.
4230  *  - On failure, a negative value.
4231  */
4232 static int
4233 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4234 {
4235         uint32_t eicr;
4236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4237         struct ixgbe_interrupt *intr =
4238                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4239
4240         /* clear all cause mask */
4241         ixgbe_disable_intr(hw);
4242
4243         /* read-on-clear nic registers here */
4244         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4245         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4246
4247         intr->flags = 0;
4248
4249         /* set flag for async link update */
4250         if (eicr & IXGBE_EICR_LSC)
4251                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4252
4253         if (eicr & IXGBE_EICR_MAILBOX)
4254                 intr->flags |= IXGBE_FLAG_MAILBOX;
4255
4256         if (eicr & IXGBE_EICR_LINKSEC)
4257                 intr->flags |= IXGBE_FLAG_MACSEC;
4258
4259         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4260             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4261             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4262                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4263
4264         return 0;
4265 }
4266
4267 /**
4268  * It gets and then prints the link status.
4269  *
4270  * @param dev
4271  *  Pointer to struct rte_eth_dev.
4272  *
4273  * @return
4274  *  - On success, zero.
4275  *  - On failure, a negative value.
4276  */
4277 static void
4278 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4279 {
4280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4281         struct rte_eth_link link;
4282
4283         rte_eth_linkstatus_get(dev, &link);
4284
4285         if (link.link_status) {
4286                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4287                                         (int)(dev->data->port_id),
4288                                         (unsigned)link.link_speed,
4289                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4290                                         "full-duplex" : "half-duplex");
4291         } else {
4292                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4293                                 (int)(dev->data->port_id));
4294         }
4295         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4296                                 pci_dev->addr.domain,
4297                                 pci_dev->addr.bus,
4298                                 pci_dev->addr.devid,
4299                                 pci_dev->addr.function);
4300 }
4301
4302 /*
4303  * It executes link_update after knowing an interrupt occurred.
4304  *
4305  * @param dev
4306  *  Pointer to struct rte_eth_dev.
4307  *
4308  * @return
4309  *  - On success, zero.
4310  *  - On failure, a negative value.
4311  */
4312 static int
4313 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4314 {
4315         struct ixgbe_interrupt *intr =
4316                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4317         int64_t timeout;
4318         struct ixgbe_hw *hw =
4319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320
4321         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4322
4323         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4324                 ixgbe_pf_mbx_process(dev);
4325                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4326         }
4327
4328         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4329                 ixgbe_handle_lasi(hw);
4330                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4331         }
4332
4333         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4334                 struct rte_eth_link link;
4335
4336                 /* get the link status before link update, for predicting later */
4337                 rte_eth_linkstatus_get(dev, &link);
4338
4339                 ixgbe_dev_link_update(dev, 0);
4340
4341                 /* likely to up */
4342                 if (!link.link_status)
4343                         /* handle it 1 sec later, wait it being stable */
4344                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4345                 /* likely to down */
4346                 else
4347                         /* handle it 4 sec later, wait it being stable */
4348                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4349
4350                 ixgbe_dev_link_status_print(dev);
4351                 if (rte_eal_alarm_set(timeout * 1000,
4352                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4353                         PMD_DRV_LOG(ERR, "Error setting alarm");
4354                 else {
4355                         /* remember original mask */
4356                         intr->mask_original = intr->mask;
4357                         /* only disable lsc interrupt */
4358                         intr->mask &= ~IXGBE_EIMS_LSC;
4359                 }
4360         }
4361
4362         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4363         ixgbe_enable_intr(dev);
4364
4365         return 0;
4366 }
4367
4368 /**
4369  * Interrupt handler which shall be registered for alarm callback for delayed
4370  * handling specific interrupt to wait for the stable nic state. As the
4371  * NIC interrupt state is not stable for ixgbe after link is just down,
4372  * it needs to wait 4 seconds to get the stable status.
4373  *
4374  * @param handle
4375  *  Pointer to interrupt handle.
4376  * @param param
4377  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4378  *
4379  * @return
4380  *  void
4381  */
4382 static void
4383 ixgbe_dev_interrupt_delayed_handler(void *param)
4384 {
4385         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4388         struct ixgbe_interrupt *intr =
4389                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4390         struct ixgbe_hw *hw =
4391                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4392         uint32_t eicr;
4393
4394         ixgbe_disable_intr(hw);
4395
4396         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4397         if (eicr & IXGBE_EICR_MAILBOX)
4398                 ixgbe_pf_mbx_process(dev);
4399
4400         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4401                 ixgbe_handle_lasi(hw);
4402                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4403         }
4404
4405         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4406                 ixgbe_dev_link_update(dev, 0);
4407                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4408                 ixgbe_dev_link_status_print(dev);
4409                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4410                                               NULL);
4411         }
4412
4413         if (intr->flags & IXGBE_FLAG_MACSEC) {
4414                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4415                                               NULL);
4416                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4417         }
4418
4419         /* restore original mask */
4420         intr->mask = intr->mask_original;
4421         intr->mask_original = 0;
4422
4423         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4424         ixgbe_enable_intr(dev);
4425         rte_intr_enable(intr_handle);
4426 }
4427
4428 /**
4429  * Interrupt handler triggered by NIC  for handling
4430  * specific interrupt.
4431  *
4432  * @param handle
4433  *  Pointer to interrupt handle.
4434  * @param param
4435  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4436  *
4437  * @return
4438  *  void
4439  */
4440 static void
4441 ixgbe_dev_interrupt_handler(void *param)
4442 {
4443         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4444
4445         ixgbe_dev_interrupt_get_status(dev);
4446         ixgbe_dev_interrupt_action(dev);
4447 }
4448
4449 static int
4450 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4451 {
4452         struct ixgbe_hw *hw;
4453
4454         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4455         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4456 }
4457
4458 static int
4459 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4460 {
4461         struct ixgbe_hw *hw;
4462
4463         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4465 }
4466
4467 static int
4468 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4469 {
4470         struct ixgbe_hw *hw;
4471         uint32_t mflcn_reg;
4472         uint32_t fccfg_reg;
4473         int rx_pause;
4474         int tx_pause;
4475
4476         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4477
4478         fc_conf->pause_time = hw->fc.pause_time;
4479         fc_conf->high_water = hw->fc.high_water[0];
4480         fc_conf->low_water = hw->fc.low_water[0];
4481         fc_conf->send_xon = hw->fc.send_xon;
4482         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4483
4484         /*
4485          * Return rx_pause status according to actual setting of
4486          * MFLCN register.
4487          */
4488         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4489         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4490                 rx_pause = 1;
4491         else
4492                 rx_pause = 0;
4493
4494         /*
4495          * Return tx_pause status according to actual setting of
4496          * FCCFG register.
4497          */
4498         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4499         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4500                 tx_pause = 1;
4501         else
4502                 tx_pause = 0;
4503
4504         if (rx_pause && tx_pause)
4505                 fc_conf->mode = RTE_FC_FULL;
4506         else if (rx_pause)
4507                 fc_conf->mode = RTE_FC_RX_PAUSE;
4508         else if (tx_pause)
4509                 fc_conf->mode = RTE_FC_TX_PAUSE;
4510         else
4511                 fc_conf->mode = RTE_FC_NONE;
4512
4513         return 0;
4514 }
4515
4516 static int
4517 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4518 {
4519         struct ixgbe_hw *hw;
4520         int err;
4521         uint32_t rx_buf_size;
4522         uint32_t max_high_water;
4523         uint32_t mflcn;
4524         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4525                 ixgbe_fc_none,
4526                 ixgbe_fc_rx_pause,
4527                 ixgbe_fc_tx_pause,
4528                 ixgbe_fc_full
4529         };
4530
4531         PMD_INIT_FUNC_TRACE();
4532
4533         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4534         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4535         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4536
4537         /*
4538          * At least reserve one Ethernet frame for watermark
4539          * high_water/low_water in kilo bytes for ixgbe
4540          */
4541         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4542         if ((fc_conf->high_water > max_high_water) ||
4543                 (fc_conf->high_water < fc_conf->low_water)) {
4544                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4545                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4546                 return -EINVAL;
4547         }
4548
4549         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4550         hw->fc.pause_time     = fc_conf->pause_time;
4551         hw->fc.high_water[0]  = fc_conf->high_water;
4552         hw->fc.low_water[0]   = fc_conf->low_water;
4553         hw->fc.send_xon       = fc_conf->send_xon;
4554         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4555
4556         err = ixgbe_fc_enable(hw);
4557
4558         /* Not negotiated is not an error case */
4559         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4560
4561                 /* check if we want to forward MAC frames - driver doesn't have native
4562                  * capability to do that, so we'll write the registers ourselves */
4563
4564                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4565
4566                 /* set or clear MFLCN.PMCF bit depending on configuration */
4567                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4568                         mflcn |= IXGBE_MFLCN_PMCF;
4569                 else
4570                         mflcn &= ~IXGBE_MFLCN_PMCF;
4571
4572                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4573                 IXGBE_WRITE_FLUSH(hw);
4574
4575                 return 0;
4576         }
4577
4578         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4579         return -EIO;
4580 }
4581
4582 /**
4583  *  ixgbe_pfc_enable_generic - Enable flow control
4584  *  @hw: pointer to hardware structure
4585  *  @tc_num: traffic class number
4586  *  Enable flow control according to the current settings.
4587  */
4588 static int
4589 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4590 {
4591         int ret_val = 0;
4592         uint32_t mflcn_reg, fccfg_reg;
4593         uint32_t reg;
4594         uint32_t fcrtl, fcrth;
4595         uint8_t i;
4596         uint8_t nb_rx_en;
4597
4598         /* Validate the water mark configuration */
4599         if (!hw->fc.pause_time) {
4600                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4601                 goto out;
4602         }
4603
4604         /* Low water mark of zero causes XOFF floods */
4605         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4606                  /* High/Low water can not be 0 */
4607                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4608                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4609                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4610                         goto out;
4611                 }
4612
4613                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4614                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4615                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4616                         goto out;
4617                 }
4618         }
4619         /* Negotiate the fc mode to use */
4620         ixgbe_fc_autoneg(hw);
4621
4622         /* Disable any previous flow control settings */
4623         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4624         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4625
4626         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4627         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4628
4629         switch (hw->fc.current_mode) {
4630         case ixgbe_fc_none:
4631                 /*
4632                  * If the count of enabled RX Priority Flow control >1,
4633                  * and the TX pause can not be disabled
4634                  */
4635                 nb_rx_en = 0;
4636                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4637                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4638                         if (reg & IXGBE_FCRTH_FCEN)
4639                                 nb_rx_en++;
4640                 }
4641                 if (nb_rx_en > 1)
4642                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4643                 break;
4644         case ixgbe_fc_rx_pause:
4645                 /*
4646                  * Rx Flow control is enabled and Tx Flow control is
4647                  * disabled by software override. Since there really
4648                  * isn't a way to advertise that we are capable of RX
4649                  * Pause ONLY, we will advertise that we support both
4650                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4651                  * disable the adapter's ability to send PAUSE frames.
4652                  */
4653                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4654                 /*
4655                  * If the count of enabled RX Priority Flow control >1,
4656                  * and the TX pause can not be disabled
4657                  */
4658                 nb_rx_en = 0;
4659                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4660                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4661                         if (reg & IXGBE_FCRTH_FCEN)
4662                                 nb_rx_en++;
4663                 }
4664                 if (nb_rx_en > 1)
4665                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4666                 break;
4667         case ixgbe_fc_tx_pause:
4668                 /*
4669                  * Tx Flow control is enabled, and Rx Flow control is
4670                  * disabled by software override.
4671                  */
4672                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4673                 break;
4674         case ixgbe_fc_full:
4675                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4676                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4677                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4678                 break;
4679         default:
4680                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4681                 ret_val = IXGBE_ERR_CONFIG;
4682                 goto out;
4683         }
4684
4685         /* Set 802.3x based flow control settings. */
4686         mflcn_reg |= IXGBE_MFLCN_DPF;
4687         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4688         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4689
4690         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4691         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4692                 hw->fc.high_water[tc_num]) {
4693                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4694                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4695                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4696         } else {
4697                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4698                 /*
4699                  * In order to prevent Tx hangs when the internal Tx
4700                  * switch is enabled we must set the high water mark
4701                  * to the maximum FCRTH value.  This allows the Tx
4702                  * switch to function even under heavy Rx workloads.
4703                  */
4704                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4705         }
4706         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4707
4708         /* Configure pause time (2 TCs per register) */
4709         reg = hw->fc.pause_time * 0x00010001;
4710         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4711                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4712
4713         /* Configure flow control refresh threshold value */
4714         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4715
4716 out:
4717         return ret_val;
4718 }
4719
4720 static int
4721 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4722 {
4723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4725
4726         if (hw->mac.type != ixgbe_mac_82598EB) {
4727                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4728         }
4729         return ret_val;
4730 }
4731
4732 static int
4733 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4734 {
4735         int err;
4736         uint32_t rx_buf_size;
4737         uint32_t max_high_water;
4738         uint8_t tc_num;
4739         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4740         struct ixgbe_hw *hw =
4741                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         struct ixgbe_dcb_config *dcb_config =
4743                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4744
4745         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4746                 ixgbe_fc_none,
4747                 ixgbe_fc_rx_pause,
4748                 ixgbe_fc_tx_pause,
4749                 ixgbe_fc_full
4750         };
4751
4752         PMD_INIT_FUNC_TRACE();
4753
4754         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4755         tc_num = map[pfc_conf->priority];
4756         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4757         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4758         /*
4759          * At least reserve one Ethernet frame for watermark
4760          * high_water/low_water in kilo bytes for ixgbe
4761          */
4762         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4763         if ((pfc_conf->fc.high_water > max_high_water) ||
4764             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4765                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4766                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4767                 return -EINVAL;
4768         }
4769
4770         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4771         hw->fc.pause_time = pfc_conf->fc.pause_time;
4772         hw->fc.send_xon = pfc_conf->fc.send_xon;
4773         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4774         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4775
4776         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4777
4778         /* Not negotiated is not an error case */
4779         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4780                 return 0;
4781
4782         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4783         return -EIO;
4784 }
4785
4786 static int
4787 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4788                           struct rte_eth_rss_reta_entry64 *reta_conf,
4789                           uint16_t reta_size)
4790 {
4791         uint16_t i, sp_reta_size;
4792         uint8_t j, mask;
4793         uint32_t reta, r;
4794         uint16_t idx, shift;
4795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4796         uint32_t reta_reg;
4797
4798         PMD_INIT_FUNC_TRACE();
4799
4800         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4801                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4802                         "NIC.");
4803                 return -ENOTSUP;
4804         }
4805
4806         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4807         if (reta_size != sp_reta_size) {
4808                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4809                         "(%d) doesn't match the number hardware can supported "
4810                         "(%d)", reta_size, sp_reta_size);
4811                 return -EINVAL;
4812         }
4813
4814         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4815                 idx = i / RTE_RETA_GROUP_SIZE;
4816                 shift = i % RTE_RETA_GROUP_SIZE;
4817                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4818                                                 IXGBE_4_BIT_MASK);
4819                 if (!mask)
4820                         continue;
4821                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4822                 if (mask == IXGBE_4_BIT_MASK)
4823                         r = 0;
4824                 else
4825                         r = IXGBE_READ_REG(hw, reta_reg);
4826                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4827                         if (mask & (0x1 << j))
4828                                 reta |= reta_conf[idx].reta[shift + j] <<
4829                                                         (CHAR_BIT * j);
4830                         else
4831                                 reta |= r & (IXGBE_8_BIT_MASK <<
4832                                                 (CHAR_BIT * j));
4833                 }
4834                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4835         }
4836
4837         return 0;
4838 }
4839
4840 static int
4841 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4842                          struct rte_eth_rss_reta_entry64 *reta_conf,
4843                          uint16_t reta_size)
4844 {
4845         uint16_t i, sp_reta_size;
4846         uint8_t j, mask;
4847         uint32_t reta;
4848         uint16_t idx, shift;
4849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4850         uint32_t reta_reg;
4851
4852         PMD_INIT_FUNC_TRACE();
4853         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4854         if (reta_size != sp_reta_size) {
4855                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4856                         "(%d) doesn't match the number hardware can supported "
4857                         "(%d)", reta_size, sp_reta_size);
4858                 return -EINVAL;
4859         }
4860
4861         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4862                 idx = i / RTE_RETA_GROUP_SIZE;
4863                 shift = i % RTE_RETA_GROUP_SIZE;
4864                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4865                                                 IXGBE_4_BIT_MASK);
4866                 if (!mask)
4867                         continue;
4868
4869                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4870                 reta = IXGBE_READ_REG(hw, reta_reg);
4871                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4872                         if (mask & (0x1 << j))
4873                                 reta_conf[idx].reta[shift + j] =
4874                                         ((reta >> (CHAR_BIT * j)) &
4875                                                 IXGBE_8_BIT_MASK);
4876                 }
4877         }
4878
4879         return 0;
4880 }
4881
4882 static int
4883 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4884                                 uint32_t index, uint32_t pool)
4885 {
4886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4887         uint32_t enable_addr = 1;
4888
4889         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4890                              pool, enable_addr);
4891 }
4892
4893 static void
4894 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4895 {
4896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4897
4898         ixgbe_clear_rar(hw, index);
4899 }
4900
4901 static int
4902 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4903 {
4904         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4905
4906         ixgbe_remove_rar(dev, 0);
4907         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4908
4909         return 0;
4910 }
4911
4912 static bool
4913 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4914 {
4915         if (strcmp(dev->device->driver->name, drv->driver.name))
4916                 return false;
4917
4918         return true;
4919 }
4920
4921 bool
4922 is_ixgbe_supported(struct rte_eth_dev *dev)
4923 {
4924         return is_device_supported(dev, &rte_ixgbe_pmd);
4925 }
4926
4927 static int
4928 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4929 {
4930         uint32_t hlreg0;
4931         uint32_t maxfrs;
4932         struct ixgbe_hw *hw;
4933         struct rte_eth_dev_info dev_info;
4934         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4935         struct rte_eth_dev_data *dev_data = dev->data;
4936
4937         ixgbe_dev_info_get(dev, &dev_info);
4938
4939         /* check that mtu is within the allowed range */
4940         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4941                 return -EINVAL;
4942
4943         /* If device is started, refuse mtu that requires the support of
4944          * scattered packets when this feature has not been enabled before.
4945          */
4946         if (dev_data->dev_started && !dev_data->scattered_rx &&
4947             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4948              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4949                 PMD_INIT_LOG(ERR, "Stop port first.");
4950                 return -EINVAL;
4951         }
4952
4953         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4955
4956         /* switch to jumbo mode if needed */
4957         if (frame_size > ETHER_MAX_LEN) {
4958                 dev->data->dev_conf.rxmode.offloads |=
4959                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4960                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4961         } else {
4962                 dev->data->dev_conf.rxmode.offloads &=
4963                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4964                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4965         }
4966         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4967
4968         /* update max frame size */
4969         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4970
4971         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4972         maxfrs &= 0x0000FFFF;
4973         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4974         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4975
4976         return 0;
4977 }
4978
4979 /*
4980  * Virtual Function operations
4981  */
4982 static void
4983 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4984 {
4985         struct ixgbe_interrupt *intr =
4986                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4987         struct ixgbe_hw *hw =
4988                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4989
4990         PMD_INIT_FUNC_TRACE();
4991
4992         /* Clear interrupt mask to stop from interrupts being generated */
4993         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4994
4995         IXGBE_WRITE_FLUSH(hw);
4996
4997         /* Clear mask value. */
4998         intr->mask = 0;
4999 }
5000
5001 static void
5002 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5003 {
5004         struct ixgbe_interrupt *intr =
5005                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5006         struct ixgbe_hw *hw =
5007                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008
5009         PMD_INIT_FUNC_TRACE();
5010
5011         /* VF enable interrupt autoclean */
5012         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5013         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5014         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5015
5016         IXGBE_WRITE_FLUSH(hw);
5017
5018         /* Save IXGBE_VTEIMS value to mask. */
5019         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5020 }
5021
5022 static int
5023 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5024 {
5025         struct rte_eth_conf *conf = &dev->data->dev_conf;
5026         struct ixgbe_adapter *adapter =
5027                         (struct ixgbe_adapter *)dev->data->dev_private;
5028
5029         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5030                      dev->data->port_id);
5031
5032         /*
5033          * VF has no ability to enable/disable HW CRC
5034          * Keep the persistent behavior the same as Host PF
5035          */
5036 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5037         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5038                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5039                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5040         }
5041 #else
5042         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5043                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5044                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5045         }
5046 #endif
5047
5048         /*
5049          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5050          * allocation or vector Rx preconditions we will reset it.
5051          */
5052         adapter->rx_bulk_alloc_allowed = true;
5053         adapter->rx_vec_allowed = true;
5054
5055         return 0;
5056 }
5057
5058 static int
5059 ixgbevf_dev_start(struct rte_eth_dev *dev)
5060 {
5061         struct ixgbe_hw *hw =
5062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5063         uint32_t intr_vector = 0;
5064         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5065         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5066
5067         int err, mask = 0;
5068
5069         PMD_INIT_FUNC_TRACE();
5070
5071         /* Stop the link setup handler before resetting the HW. */
5072         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5073
5074         err = hw->mac.ops.reset_hw(hw);
5075         if (err) {
5076                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5077                 return err;
5078         }
5079         hw->mac.get_link_status = true;
5080
5081         /* negotiate mailbox API version to use with the PF. */
5082         ixgbevf_negotiate_api(hw);
5083
5084         ixgbevf_dev_tx_init(dev);
5085
5086         /* This can fail when allocating mbufs for descriptor rings */
5087         err = ixgbevf_dev_rx_init(dev);
5088         if (err) {
5089                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5090                 ixgbe_dev_clear_queues(dev);
5091                 return err;
5092         }
5093
5094         /* Set vfta */
5095         ixgbevf_set_vfta_all(dev, 1);
5096
5097         /* Set HW strip */
5098         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5099                 ETH_VLAN_EXTEND_MASK;
5100         err = ixgbevf_vlan_offload_config(dev, mask);
5101         if (err) {
5102                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5103                 ixgbe_dev_clear_queues(dev);
5104                 return err;
5105         }
5106
5107         ixgbevf_dev_rxtx_start(dev);
5108
5109         /* check and configure queue intr-vector mapping */
5110         if (rte_intr_cap_multiple(intr_handle) &&
5111             dev->data->dev_conf.intr_conf.rxq) {
5112                 /* According to datasheet, only vector 0/1/2 can be used,
5113                  * now only one vector is used for Rx queue
5114                  */
5115                 intr_vector = 1;
5116                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5117                         return -1;
5118         }
5119
5120         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5121                 intr_handle->intr_vec =
5122                         rte_zmalloc("intr_vec",
5123                                     dev->data->nb_rx_queues * sizeof(int), 0);
5124                 if (intr_handle->intr_vec == NULL) {
5125                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5126                                      " intr_vec", dev->data->nb_rx_queues);
5127                         return -ENOMEM;
5128                 }
5129         }
5130         ixgbevf_configure_msix(dev);
5131
5132         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5133          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5134          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5135          * is not cleared, it will fail when following rte_intr_enable( ) tries
5136          * to map Rx queue interrupt to other VFIO vectors.
5137          * So clear uio/vfio intr/evevnfd first to avoid failure.
5138          */
5139         rte_intr_disable(intr_handle);
5140
5141         rte_intr_enable(intr_handle);
5142
5143         /* Re-enable interrupt for VF */
5144         ixgbevf_intr_enable(dev);
5145
5146         /*
5147          * Update link status right before return, because it may
5148          * start link configuration process in a separate thread.
5149          */
5150         ixgbevf_dev_link_update(dev, 0);
5151
5152         return 0;
5153 }
5154
5155 static void
5156 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5157 {
5158         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5159         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5160         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5161
5162         PMD_INIT_FUNC_TRACE();
5163
5164         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5165
5166         ixgbevf_intr_disable(dev);
5167
5168         hw->adapter_stopped = 1;
5169         ixgbe_stop_adapter(hw);
5170
5171         /*
5172           * Clear what we set, but we still keep shadow_vfta to
5173           * restore after device starts
5174           */
5175         ixgbevf_set_vfta_all(dev, 0);
5176
5177         /* Clear stored conf */
5178         dev->data->scattered_rx = 0;
5179
5180         ixgbe_dev_clear_queues(dev);
5181
5182         /* Clean datapath event and queue/vec mapping */
5183         rte_intr_efd_disable(intr_handle);
5184         if (intr_handle->intr_vec != NULL) {
5185                 rte_free(intr_handle->intr_vec);
5186                 intr_handle->intr_vec = NULL;
5187         }
5188 }
5189
5190 static void
5191 ixgbevf_dev_close(struct rte_eth_dev *dev)
5192 {
5193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5194
5195         PMD_INIT_FUNC_TRACE();
5196
5197         ixgbe_reset_hw(hw);
5198
5199         ixgbevf_dev_stop(dev);
5200
5201         ixgbe_dev_free_queues(dev);
5202
5203         /**
5204          * Remove the VF MAC address ro ensure
5205          * that the VF traffic goes to the PF
5206          * after stop, close and detach of the VF
5207          **/
5208         ixgbevf_remove_mac_addr(dev, 0);
5209 }
5210
5211 /*
5212  * Reset VF device
5213  */
5214 static int
5215 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5216 {
5217         int ret;
5218
5219         ret = eth_ixgbevf_dev_uninit(dev);
5220         if (ret)
5221                 return ret;
5222
5223         ret = eth_ixgbevf_dev_init(dev);
5224
5225         return ret;
5226 }
5227
5228 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5229 {
5230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5231         struct ixgbe_vfta *shadow_vfta =
5232                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5233         int i = 0, j = 0, vfta = 0, mask = 1;
5234
5235         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5236                 vfta = shadow_vfta->vfta[i];
5237                 if (vfta) {
5238                         mask = 1;
5239                         for (j = 0; j < 32; j++) {
5240                                 if (vfta & mask)
5241                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5242                                                        on, false);
5243                                 mask <<= 1;
5244                         }
5245                 }
5246         }
5247
5248 }
5249
5250 static int
5251 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5252 {
5253         struct ixgbe_hw *hw =
5254                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255         struct ixgbe_vfta *shadow_vfta =
5256                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5257         uint32_t vid_idx = 0;
5258         uint32_t vid_bit = 0;
5259         int ret = 0;
5260
5261         PMD_INIT_FUNC_TRACE();
5262
5263         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5264         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5265         if (ret) {
5266                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5267                 return ret;
5268         }
5269         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5270         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5271
5272         /* Save what we set and retore it after device reset */
5273         if (on)
5274                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5275         else
5276                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5277
5278         return 0;
5279 }
5280
5281 static void
5282 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5283 {
5284         struct ixgbe_hw *hw =
5285                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5286         uint32_t ctrl;
5287
5288         PMD_INIT_FUNC_TRACE();
5289
5290         if (queue >= hw->mac.max_rx_queues)
5291                 return;
5292
5293         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5294         if (on)
5295                 ctrl |= IXGBE_RXDCTL_VME;
5296         else
5297                 ctrl &= ~IXGBE_RXDCTL_VME;
5298         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5299
5300         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5301 }
5302
5303 static int
5304 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5305 {
5306         struct ixgbe_rx_queue *rxq;
5307         uint16_t i;
5308         int on = 0;
5309
5310         /* VF function only support hw strip feature, others are not support */
5311         if (mask & ETH_VLAN_STRIP_MASK) {
5312                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5313                         rxq = dev->data->rx_queues[i];
5314                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5315                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5316                 }
5317         }
5318
5319         return 0;
5320 }
5321
5322 static int
5323 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5324 {
5325         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5326
5327         ixgbevf_vlan_offload_config(dev, mask);
5328
5329         return 0;
5330 }
5331
5332 int
5333 ixgbe_vt_check(struct ixgbe_hw *hw)
5334 {
5335         uint32_t reg_val;
5336
5337         /* if Virtualization Technology is enabled */
5338         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5339         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5340                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5341                 return -1;
5342         }
5343
5344         return 0;
5345 }
5346
5347 static uint32_t
5348 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5349 {
5350         uint32_t vector = 0;
5351
5352         switch (hw->mac.mc_filter_type) {
5353         case 0:   /* use bits [47:36] of the address */
5354                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5355                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5356                 break;
5357         case 1:   /* use bits [46:35] of the address */
5358                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5359                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5360                 break;
5361         case 2:   /* use bits [45:34] of the address */
5362                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5363                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5364                 break;
5365         case 3:   /* use bits [43:32] of the address */
5366                 vector = ((uc_addr->addr_bytes[4]) |
5367                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5368                 break;
5369         default:  /* Invalid mc_filter_type */
5370                 break;
5371         }
5372
5373         /* vector can only be 12-bits or boundary will be exceeded */
5374         vector &= 0xFFF;
5375         return vector;
5376 }
5377
5378 static int
5379 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5380                         uint8_t on)
5381 {
5382         uint32_t vector;
5383         uint32_t uta_idx;
5384         uint32_t reg_val;
5385         uint32_t uta_shift;
5386         uint32_t rc;
5387         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5388         const uint32_t ixgbe_uta_bit_shift = 5;
5389         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5390         const uint32_t bit1 = 0x1;
5391
5392         struct ixgbe_hw *hw =
5393                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5394         struct ixgbe_uta_info *uta_info =
5395                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5396
5397         /* The UTA table only exists on 82599 hardware and newer */
5398         if (hw->mac.type < ixgbe_mac_82599EB)
5399                 return -ENOTSUP;
5400
5401         vector = ixgbe_uta_vector(hw, mac_addr);
5402         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5403         uta_shift = vector & ixgbe_uta_bit_mask;
5404
5405         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5406         if (rc == on)
5407                 return 0;
5408
5409         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5410         if (on) {
5411                 uta_info->uta_in_use++;
5412                 reg_val |= (bit1 << uta_shift);
5413                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5414         } else {
5415                 uta_info->uta_in_use--;
5416                 reg_val &= ~(bit1 << uta_shift);
5417                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5418         }
5419
5420         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5421
5422         if (uta_info->uta_in_use > 0)
5423                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5424                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5425         else
5426                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5427
5428         return 0;
5429 }
5430
5431 static int
5432 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5433 {
5434         int i;
5435         struct ixgbe_hw *hw =
5436                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5437         struct ixgbe_uta_info *uta_info =
5438                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5439
5440         /* The UTA table only exists on 82599 hardware and newer */
5441         if (hw->mac.type < ixgbe_mac_82599EB)
5442                 return -ENOTSUP;
5443
5444         if (on) {
5445                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5446                         uta_info->uta_shadow[i] = ~0;
5447                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5448                 }
5449         } else {
5450                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5451                         uta_info->uta_shadow[i] = 0;
5452                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5453                 }
5454         }
5455         return 0;
5456
5457 }
5458
5459 uint32_t
5460 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5461 {
5462         uint32_t new_val = orig_val;
5463
5464         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5465                 new_val |= IXGBE_VMOLR_AUPE;
5466         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5467                 new_val |= IXGBE_VMOLR_ROMPE;
5468         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5469                 new_val |= IXGBE_VMOLR_ROPE;
5470         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5471                 new_val |= IXGBE_VMOLR_BAM;
5472         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5473                 new_val |= IXGBE_VMOLR_MPE;
5474
5475         return new_val;
5476 }
5477
5478 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5479 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5480 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5481 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5482 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5483         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5484         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5485
5486 static int
5487 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5488                       struct rte_eth_mirror_conf *mirror_conf,
5489                       uint8_t rule_id, uint8_t on)
5490 {
5491         uint32_t mr_ctl, vlvf;
5492         uint32_t mp_lsb = 0;
5493         uint32_t mv_msb = 0;
5494         uint32_t mv_lsb = 0;
5495         uint32_t mp_msb = 0;
5496         uint8_t i = 0;
5497         int reg_index = 0;
5498         uint64_t vlan_mask = 0;
5499
5500         const uint8_t pool_mask_offset = 32;
5501         const uint8_t vlan_mask_offset = 32;
5502         const uint8_t dst_pool_offset = 8;
5503         const uint8_t rule_mr_offset  = 4;
5504         const uint8_t mirror_rule_mask = 0x0F;
5505
5506         struct ixgbe_mirror_info *mr_info =
5507                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5508         struct ixgbe_hw *hw =
5509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5510         uint8_t mirror_type = 0;
5511
5512         if (ixgbe_vt_check(hw) < 0)
5513                 return -ENOTSUP;
5514
5515         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5516                 return -EINVAL;
5517
5518         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5519                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5520                             mirror_conf->rule_type);
5521                 return -EINVAL;
5522         }
5523
5524         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5525                 mirror_type |= IXGBE_MRCTL_VLME;
5526                 /* Check if vlan id is valid and find conresponding VLAN ID
5527                  * index in VLVF
5528                  */
5529                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5530                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5531                                 /* search vlan id related pool vlan filter
5532                                  * index
5533                                  */
5534                                 reg_index = ixgbe_find_vlvf_slot(
5535                                                 hw,
5536                                                 mirror_conf->vlan.vlan_id[i],
5537                                                 false);
5538                                 if (reg_index < 0)
5539                                         return -EINVAL;
5540                                 vlvf = IXGBE_READ_REG(hw,
5541                                                       IXGBE_VLVF(reg_index));
5542                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5543                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5544                                       mirror_conf->vlan.vlan_id[i]))
5545                                         vlan_mask |= (1ULL << reg_index);
5546                                 else
5547                                         return -EINVAL;
5548                         }
5549                 }
5550
5551                 if (on) {
5552                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5553                         mv_msb = vlan_mask >> vlan_mask_offset;
5554
5555                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5556                                                 mirror_conf->vlan.vlan_mask;
5557                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5558                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5559                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5560                                                 mirror_conf->vlan.vlan_id[i];
5561                         }
5562                 } else {
5563                         mv_lsb = 0;
5564                         mv_msb = 0;
5565                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5566                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5567                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5568                 }
5569         }
5570
5571         /**
5572          * if enable pool mirror, write related pool mask register,if disable
5573          * pool mirror, clear PFMRVM register
5574          */
5575         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5576                 mirror_type |= IXGBE_MRCTL_VPME;
5577                 if (on) {
5578                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5579                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5580                         mr_info->mr_conf[rule_id].pool_mask =
5581                                         mirror_conf->pool_mask;
5582
5583                 } else {
5584                         mp_lsb = 0;
5585                         mp_msb = 0;
5586                         mr_info->mr_conf[rule_id].pool_mask = 0;
5587                 }
5588         }
5589         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5590                 mirror_type |= IXGBE_MRCTL_UPME;
5591         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5592                 mirror_type |= IXGBE_MRCTL_DPME;
5593
5594         /* read  mirror control register and recalculate it */
5595         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5596
5597         if (on) {
5598                 mr_ctl |= mirror_type;
5599                 mr_ctl &= mirror_rule_mask;
5600                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5601         } else {
5602                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5603         }
5604
5605         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5606         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5607
5608         /* write mirrror control  register */
5609         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5610
5611         /* write pool mirrror control  register */
5612         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5613                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5614                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5615                                 mp_msb);
5616         }
5617         /* write VLAN mirrror control  register */
5618         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5619                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5620                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5621                                 mv_msb);
5622         }
5623
5624         return 0;
5625 }
5626
5627 static int
5628 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5629 {
5630         int mr_ctl = 0;
5631         uint32_t lsb_val = 0;
5632         uint32_t msb_val = 0;
5633         const uint8_t rule_mr_offset = 4;
5634
5635         struct ixgbe_hw *hw =
5636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5637         struct ixgbe_mirror_info *mr_info =
5638                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5639
5640         if (ixgbe_vt_check(hw) < 0)
5641                 return -ENOTSUP;
5642
5643         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5644                 return -EINVAL;
5645
5646         memset(&mr_info->mr_conf[rule_id], 0,
5647                sizeof(struct rte_eth_mirror_conf));
5648
5649         /* clear PFVMCTL register */
5650         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5651
5652         /* clear pool mask register */
5653         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5654         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5655
5656         /* clear vlan mask register */
5657         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5658         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5659
5660         return 0;
5661 }
5662
5663 static int
5664 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5665 {
5666         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5667         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5668         struct ixgbe_interrupt *intr =
5669                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5670         struct ixgbe_hw *hw =
5671                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5672         uint32_t vec = IXGBE_MISC_VEC_ID;
5673
5674         if (rte_intr_allow_others(intr_handle))
5675                 vec = IXGBE_RX_VEC_START;
5676         intr->mask |= (1 << vec);
5677         RTE_SET_USED(queue_id);
5678         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5679
5680         rte_intr_enable(intr_handle);
5681
5682         return 0;
5683 }
5684
5685 static int
5686 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5687 {
5688         struct ixgbe_interrupt *intr =
5689                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5690         struct ixgbe_hw *hw =
5691                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5694         uint32_t vec = IXGBE_MISC_VEC_ID;
5695
5696         if (rte_intr_allow_others(intr_handle))
5697                 vec = IXGBE_RX_VEC_START;
5698         intr->mask &= ~(1 << vec);
5699         RTE_SET_USED(queue_id);
5700         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5701
5702         return 0;
5703 }
5704
5705 static int
5706 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5707 {
5708         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5709         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5710         uint32_t mask;
5711         struct ixgbe_hw *hw =
5712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5713         struct ixgbe_interrupt *intr =
5714                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5715
5716         if (queue_id < 16) {
5717                 ixgbe_disable_intr(hw);
5718                 intr->mask |= (1 << queue_id);
5719                 ixgbe_enable_intr(dev);
5720         } else if (queue_id < 32) {
5721                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5722                 mask &= (1 << queue_id);
5723                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5724         } else if (queue_id < 64) {
5725                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5726                 mask &= (1 << (queue_id - 32));
5727                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5728         }
5729         rte_intr_enable(intr_handle);
5730
5731         return 0;
5732 }
5733
5734 static int
5735 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5736 {
5737         uint32_t mask;
5738         struct ixgbe_hw *hw =
5739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5740         struct ixgbe_interrupt *intr =
5741                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5742
5743         if (queue_id < 16) {
5744                 ixgbe_disable_intr(hw);
5745                 intr->mask &= ~(1 << queue_id);
5746                 ixgbe_enable_intr(dev);
5747         } else if (queue_id < 32) {
5748                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5749                 mask &= ~(1 << queue_id);
5750                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5751         } else if (queue_id < 64) {
5752                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5753                 mask &= ~(1 << (queue_id - 32));
5754                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5755         }
5756
5757         return 0;
5758 }
5759
5760 static void
5761 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5762                      uint8_t queue, uint8_t msix_vector)
5763 {
5764         uint32_t tmp, idx;
5765
5766         if (direction == -1) {
5767                 /* other causes */
5768                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5769                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5770                 tmp &= ~0xFF;
5771                 tmp |= msix_vector;
5772                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5773         } else {
5774                 /* rx or tx cause */
5775                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5776                 idx = ((16 * (queue & 1)) + (8 * direction));
5777                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5778                 tmp &= ~(0xFF << idx);
5779                 tmp |= (msix_vector << idx);
5780                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5781         }
5782 }
5783
5784 /**
5785  * set the IVAR registers, mapping interrupt causes to vectors
5786  * @param hw
5787  *  pointer to ixgbe_hw struct
5788  * @direction
5789  *  0 for Rx, 1 for Tx, -1 for other causes
5790  * @queue
5791  *  queue to map the corresponding interrupt to
5792  * @msix_vector
5793  *  the vector to map to the corresponding queue
5794  */
5795 static void
5796 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5797                    uint8_t queue, uint8_t msix_vector)
5798 {
5799         uint32_t tmp, idx;
5800
5801         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5802         if (hw->mac.type == ixgbe_mac_82598EB) {
5803                 if (direction == -1)
5804                         direction = 0;
5805                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5806                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5807                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5808                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5809                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5810         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5811                         (hw->mac.type == ixgbe_mac_X540) ||
5812                         (hw->mac.type == ixgbe_mac_X550)) {
5813                 if (direction == -1) {
5814                         /* other causes */
5815                         idx = ((queue & 1) * 8);
5816                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5817                         tmp &= ~(0xFF << idx);
5818                         tmp |= (msix_vector << idx);
5819                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5820                 } else {
5821                         /* rx or tx causes */
5822                         idx = ((16 * (queue & 1)) + (8 * direction));
5823                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5824                         tmp &= ~(0xFF << idx);
5825                         tmp |= (msix_vector << idx);
5826                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5827                 }
5828         }
5829 }
5830
5831 static void
5832 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5833 {
5834         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5835         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5836         struct ixgbe_hw *hw =
5837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5838         uint32_t q_idx;
5839         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5840         uint32_t base = IXGBE_MISC_VEC_ID;
5841
5842         /* Configure VF other cause ivar */
5843         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5844
5845         /* won't configure msix register if no mapping is done
5846          * between intr vector and event fd.
5847          */
5848         if (!rte_intr_dp_is_en(intr_handle))
5849                 return;
5850
5851         if (rte_intr_allow_others(intr_handle)) {
5852                 base = IXGBE_RX_VEC_START;
5853                 vector_idx = IXGBE_RX_VEC_START;
5854         }
5855
5856         /* Configure all RX queues of VF */
5857         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5858                 /* Force all queue use vector 0,
5859                  * as IXGBE_VF_MAXMSIVECOTR = 1
5860                  */
5861                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5862                 intr_handle->intr_vec[q_idx] = vector_idx;
5863                 if (vector_idx < base + intr_handle->nb_efd - 1)
5864                         vector_idx++;
5865         }
5866
5867         /* As RX queue setting above show, all queues use the vector 0.
5868          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5869          */
5870         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5871                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5872                         | IXGBE_EITR_CNT_WDIS);
5873 }
5874
5875 /**
5876  * Sets up the hardware to properly generate MSI-X interrupts
5877  * @hw
5878  *  board private structure
5879  */
5880 static void
5881 ixgbe_configure_msix(struct rte_eth_dev *dev)
5882 {
5883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5884         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5885         struct ixgbe_hw *hw =
5886                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5887         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5888         uint32_t vec = IXGBE_MISC_VEC_ID;
5889         uint32_t mask;
5890         uint32_t gpie;
5891
5892         /* won't configure msix register if no mapping is done
5893          * between intr vector and event fd
5894          * but if misx has been enabled already, need to configure
5895          * auto clean, auto mask and throttling.
5896          */
5897         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5898         if (!rte_intr_dp_is_en(intr_handle) &&
5899             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5900                 return;
5901
5902         if (rte_intr_allow_others(intr_handle))
5903                 vec = base = IXGBE_RX_VEC_START;
5904
5905         /* setup GPIE for MSI-x mode */
5906         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5907         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5908                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5909         /* auto clearing and auto setting corresponding bits in EIMS
5910          * when MSI-X interrupt is triggered
5911          */
5912         if (hw->mac.type == ixgbe_mac_82598EB) {
5913                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5914         } else {
5915                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5916                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5917         }
5918         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5919
5920         /* Populate the IVAR table and set the ITR values to the
5921          * corresponding register.
5922          */
5923         if (rte_intr_dp_is_en(intr_handle)) {
5924                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5925                         queue_id++) {
5926                         /* by default, 1:1 mapping */
5927                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5928                         intr_handle->intr_vec[queue_id] = vec;
5929                         if (vec < base + intr_handle->nb_efd - 1)
5930                                 vec++;
5931                 }
5932
5933                 switch (hw->mac.type) {
5934                 case ixgbe_mac_82598EB:
5935                         ixgbe_set_ivar_map(hw, -1,
5936                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
5937                                            IXGBE_MISC_VEC_ID);
5938                         break;
5939                 case ixgbe_mac_82599EB:
5940                 case ixgbe_mac_X540:
5941                 case ixgbe_mac_X550:
5942                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5943                         break;
5944                 default:
5945                         break;
5946                 }
5947         }
5948         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5949                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5950                         | IXGBE_EITR_CNT_WDIS);
5951
5952         /* set up to autoclear timer, and the vectors */
5953         mask = IXGBE_EIMS_ENABLE_MASK;
5954         mask &= ~(IXGBE_EIMS_OTHER |
5955                   IXGBE_EIMS_MAILBOX |
5956                   IXGBE_EIMS_LSC);
5957
5958         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5959 }
5960
5961 int
5962 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5963                            uint16_t queue_idx, uint16_t tx_rate)
5964 {
5965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5966         struct rte_eth_rxmode *rxmode;
5967         uint32_t rf_dec, rf_int;
5968         uint32_t bcnrc_val;
5969         uint16_t link_speed = dev->data->dev_link.link_speed;
5970
5971         if (queue_idx >= hw->mac.max_tx_queues)
5972                 return -EINVAL;
5973
5974         if (tx_rate != 0) {
5975                 /* Calculate the rate factor values to set */
5976                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5977                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5978                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5979
5980                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5981                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5982                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5983                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5984         } else {
5985                 bcnrc_val = 0;
5986         }
5987
5988         rxmode = &dev->data->dev_conf.rxmode;
5989         /*
5990          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5991          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5992          * set as 0x4.
5993          */
5994         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5995             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5996                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5997                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5998         else
5999                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6000                         IXGBE_MMW_SIZE_DEFAULT);
6001
6002         /* Set RTTBCNRC of queue X */
6003         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6004         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6005         IXGBE_WRITE_FLUSH(hw);
6006
6007         return 0;
6008 }
6009
6010 static int
6011 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
6012                      __attribute__((unused)) uint32_t index,
6013                      __attribute__((unused)) uint32_t pool)
6014 {
6015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6016         int diag;
6017
6018         /*
6019          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6020          * operation. Trap this case to avoid exhausting the [very limited]
6021          * set of PF resources used to store VF MAC addresses.
6022          */
6023         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6024                 return -1;
6025         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6026         if (diag != 0)
6027                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6028                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6029                             mac_addr->addr_bytes[0],
6030                             mac_addr->addr_bytes[1],
6031                             mac_addr->addr_bytes[2],
6032                             mac_addr->addr_bytes[3],
6033                             mac_addr->addr_bytes[4],
6034                             mac_addr->addr_bytes[5],
6035                             diag);
6036         return diag;
6037 }
6038
6039 static void
6040 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6041 {
6042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6043         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6044         struct ether_addr *mac_addr;
6045         uint32_t i;
6046         int diag;
6047
6048         /*
6049          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6050          * not support the deletion of a given MAC address.
6051          * Instead, it imposes to delete all MAC addresses, then to add again
6052          * all MAC addresses with the exception of the one to be deleted.
6053          */
6054         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6055
6056         /*
6057          * Add again all MAC addresses, with the exception of the deleted one
6058          * and of the permanent MAC address.
6059          */
6060         for (i = 0, mac_addr = dev->data->mac_addrs;
6061              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6062                 /* Skip the deleted MAC address */
6063                 if (i == index)
6064                         continue;
6065                 /* Skip NULL MAC addresses */
6066                 if (is_zero_ether_addr(mac_addr))
6067                         continue;
6068                 /* Skip the permanent MAC address */
6069                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6070                         continue;
6071                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6072                 if (diag != 0)
6073                         PMD_DRV_LOG(ERR,
6074                                     "Adding again MAC address "
6075                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6076                                     "diag=%d",
6077                                     mac_addr->addr_bytes[0],
6078                                     mac_addr->addr_bytes[1],
6079                                     mac_addr->addr_bytes[2],
6080                                     mac_addr->addr_bytes[3],
6081                                     mac_addr->addr_bytes[4],
6082                                     mac_addr->addr_bytes[5],
6083                                     diag);
6084         }
6085 }
6086
6087 static int
6088 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6089 {
6090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6091
6092         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6093
6094         return 0;
6095 }
6096
6097 int
6098 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6099                         struct rte_eth_syn_filter *filter,
6100                         bool add)
6101 {
6102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6103         struct ixgbe_filter_info *filter_info =
6104                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6105         uint32_t syn_info;
6106         uint32_t synqf;
6107
6108         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6109                 return -EINVAL;
6110
6111         syn_info = filter_info->syn_info;
6112
6113         if (add) {
6114                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6115                         return -EINVAL;
6116                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6117                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6118
6119                 if (filter->hig_pri)
6120                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6121                 else
6122                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6123         } else {
6124                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6125                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6126                         return -ENOENT;
6127                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6128         }
6129
6130         filter_info->syn_info = synqf;
6131         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6132         IXGBE_WRITE_FLUSH(hw);
6133         return 0;
6134 }
6135
6136 static int
6137 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6138                         struct rte_eth_syn_filter *filter)
6139 {
6140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6141         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6142
6143         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6144                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6145                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6146                 return 0;
6147         }
6148         return -ENOENT;
6149 }
6150
6151 static int
6152 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6153                         enum rte_filter_op filter_op,
6154                         void *arg)
6155 {
6156         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6157         int ret;
6158
6159         MAC_TYPE_FILTER_SUP(hw->mac.type);
6160
6161         if (filter_op == RTE_ETH_FILTER_NOP)
6162                 return 0;
6163
6164         if (arg == NULL) {
6165                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6166                             filter_op);
6167                 return -EINVAL;
6168         }
6169
6170         switch (filter_op) {
6171         case RTE_ETH_FILTER_ADD:
6172                 ret = ixgbe_syn_filter_set(dev,
6173                                 (struct rte_eth_syn_filter *)arg,
6174                                 TRUE);
6175                 break;
6176         case RTE_ETH_FILTER_DELETE:
6177                 ret = ixgbe_syn_filter_set(dev,
6178                                 (struct rte_eth_syn_filter *)arg,
6179                                 FALSE);
6180                 break;
6181         case RTE_ETH_FILTER_GET:
6182                 ret = ixgbe_syn_filter_get(dev,
6183                                 (struct rte_eth_syn_filter *)arg);
6184                 break;
6185         default:
6186                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6187                 ret = -EINVAL;
6188                 break;
6189         }
6190
6191         return ret;
6192 }
6193
6194
6195 static inline enum ixgbe_5tuple_protocol
6196 convert_protocol_type(uint8_t protocol_value)
6197 {
6198         if (protocol_value == IPPROTO_TCP)
6199                 return IXGBE_FILTER_PROTOCOL_TCP;
6200         else if (protocol_value == IPPROTO_UDP)
6201                 return IXGBE_FILTER_PROTOCOL_UDP;
6202         else if (protocol_value == IPPROTO_SCTP)
6203                 return IXGBE_FILTER_PROTOCOL_SCTP;
6204         else
6205                 return IXGBE_FILTER_PROTOCOL_NONE;
6206 }
6207
6208 /* inject a 5-tuple filter to HW */
6209 static inline void
6210 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6211                            struct ixgbe_5tuple_filter *filter)
6212 {
6213         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6214         int i;
6215         uint32_t ftqf, sdpqf;
6216         uint32_t l34timir = 0;
6217         uint8_t mask = 0xff;
6218
6219         i = filter->index;
6220
6221         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6222                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6223         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6224
6225         ftqf = (uint32_t)(filter->filter_info.proto &
6226                 IXGBE_FTQF_PROTOCOL_MASK);
6227         ftqf |= (uint32_t)((filter->filter_info.priority &
6228                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6229         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6230                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6231         if (filter->filter_info.dst_ip_mask == 0)
6232                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6233         if (filter->filter_info.src_port_mask == 0)
6234                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6235         if (filter->filter_info.dst_port_mask == 0)
6236                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6237         if (filter->filter_info.proto_mask == 0)
6238                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6239         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6240         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6241         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6242
6243         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6244         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6245         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6246         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6247
6248         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6249         l34timir |= (uint32_t)(filter->queue <<
6250                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6251         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6252 }
6253
6254 /*
6255  * add a 5tuple filter
6256  *
6257  * @param
6258  * dev: Pointer to struct rte_eth_dev.
6259  * index: the index the filter allocates.
6260  * filter: ponter to the filter that will be added.
6261  * rx_queue: the queue id the filter assigned to.
6262  *
6263  * @return
6264  *    - On success, zero.
6265  *    - On failure, a negative value.
6266  */
6267 static int
6268 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6269                         struct ixgbe_5tuple_filter *filter)
6270 {
6271         struct ixgbe_filter_info *filter_info =
6272                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6273         int i, idx, shift;
6274
6275         /*
6276          * look for an unused 5tuple filter index,
6277          * and insert the filter to list.
6278          */
6279         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6280                 idx = i / (sizeof(uint32_t) * NBBY);
6281                 shift = i % (sizeof(uint32_t) * NBBY);
6282                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6283                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6284                         filter->index = i;
6285                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6286                                           filter,
6287                                           entries);
6288                         break;
6289                 }
6290         }
6291         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6292                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6293                 return -ENOSYS;
6294         }
6295
6296         ixgbe_inject_5tuple_filter(dev, filter);
6297
6298         return 0;
6299 }
6300
6301 /*
6302  * remove a 5tuple filter
6303  *
6304  * @param
6305  * dev: Pointer to struct rte_eth_dev.
6306  * filter: the pointer of the filter will be removed.
6307  */
6308 static void
6309 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6310                         struct ixgbe_5tuple_filter *filter)
6311 {
6312         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6313         struct ixgbe_filter_info *filter_info =
6314                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6315         uint16_t index = filter->index;
6316
6317         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6318                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6319         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6320         rte_free(filter);
6321
6322         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6323         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6324         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6325         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6326         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6327 }
6328
6329 static int
6330 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6331 {
6332         struct ixgbe_hw *hw;
6333         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6334         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6335
6336         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6337
6338         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6339                 return -EINVAL;
6340
6341         /* refuse mtu that requires the support of scattered packets when this
6342          * feature has not been enabled before.
6343          */
6344         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6345             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6346              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6347                 return -EINVAL;
6348
6349         /*
6350          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6351          * request of the version 2.0 of the mailbox API.
6352          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6353          * of the mailbox API.
6354          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6355          * prior to 3.11.33 which contains the following change:
6356          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6357          */
6358         ixgbevf_rlpml_set_vf(hw, max_frame);
6359
6360         /* update max frame size */
6361         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6362         return 0;
6363 }
6364
6365 static inline struct ixgbe_5tuple_filter *
6366 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6367                         struct ixgbe_5tuple_filter_info *key)
6368 {
6369         struct ixgbe_5tuple_filter *it;
6370
6371         TAILQ_FOREACH(it, filter_list, entries) {
6372                 if (memcmp(key, &it->filter_info,
6373                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6374                         return it;
6375                 }
6376         }
6377         return NULL;
6378 }
6379
6380 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6381 static inline int
6382 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6383                         struct ixgbe_5tuple_filter_info *filter_info)
6384 {
6385         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6386                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6387                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6388                 return -EINVAL;
6389
6390         switch (filter->dst_ip_mask) {
6391         case UINT32_MAX:
6392                 filter_info->dst_ip_mask = 0;
6393                 filter_info->dst_ip = filter->dst_ip;
6394                 break;
6395         case 0:
6396                 filter_info->dst_ip_mask = 1;
6397                 break;
6398         default:
6399                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6400                 return -EINVAL;
6401         }
6402
6403         switch (filter->src_ip_mask) {
6404         case UINT32_MAX:
6405                 filter_info->src_ip_mask = 0;
6406                 filter_info->src_ip = filter->src_ip;
6407                 break;
6408         case 0:
6409                 filter_info->src_ip_mask = 1;
6410                 break;
6411         default:
6412                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6413                 return -EINVAL;
6414         }
6415
6416         switch (filter->dst_port_mask) {
6417         case UINT16_MAX:
6418                 filter_info->dst_port_mask = 0;
6419                 filter_info->dst_port = filter->dst_port;
6420                 break;
6421         case 0:
6422                 filter_info->dst_port_mask = 1;
6423                 break;
6424         default:
6425                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6426                 return -EINVAL;
6427         }
6428
6429         switch (filter->src_port_mask) {
6430         case UINT16_MAX:
6431                 filter_info->src_port_mask = 0;
6432                 filter_info->src_port = filter->src_port;
6433                 break;
6434         case 0:
6435                 filter_info->src_port_mask = 1;
6436                 break;
6437         default:
6438                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6439                 return -EINVAL;
6440         }
6441
6442         switch (filter->proto_mask) {
6443         case UINT8_MAX:
6444                 filter_info->proto_mask = 0;
6445                 filter_info->proto =
6446                         convert_protocol_type(filter->proto);
6447                 break;
6448         case 0:
6449                 filter_info->proto_mask = 1;
6450                 break;
6451         default:
6452                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6453                 return -EINVAL;
6454         }
6455
6456         filter_info->priority = (uint8_t)filter->priority;
6457         return 0;
6458 }
6459
6460 /*
6461  * add or delete a ntuple filter
6462  *
6463  * @param
6464  * dev: Pointer to struct rte_eth_dev.
6465  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6466  * add: if true, add filter, if false, remove filter
6467  *
6468  * @return
6469  *    - On success, zero.
6470  *    - On failure, a negative value.
6471  */
6472 int
6473 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6474                         struct rte_eth_ntuple_filter *ntuple_filter,
6475                         bool add)
6476 {
6477         struct ixgbe_filter_info *filter_info =
6478                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6479         struct ixgbe_5tuple_filter_info filter_5tuple;
6480         struct ixgbe_5tuple_filter *filter;
6481         int ret;
6482
6483         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6484                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6485                 return -EINVAL;
6486         }
6487
6488         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6489         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6490         if (ret < 0)
6491                 return ret;
6492
6493         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6494                                          &filter_5tuple);
6495         if (filter != NULL && add) {
6496                 PMD_DRV_LOG(ERR, "filter exists.");
6497                 return -EEXIST;
6498         }
6499         if (filter == NULL && !add) {
6500                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6501                 return -ENOENT;
6502         }
6503
6504         if (add) {
6505                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6506                                 sizeof(struct ixgbe_5tuple_filter), 0);
6507                 if (filter == NULL)
6508                         return -ENOMEM;
6509                 rte_memcpy(&filter->filter_info,
6510                                  &filter_5tuple,
6511                                  sizeof(struct ixgbe_5tuple_filter_info));
6512                 filter->queue = ntuple_filter->queue;
6513                 ret = ixgbe_add_5tuple_filter(dev, filter);
6514                 if (ret < 0) {
6515                         rte_free(filter);
6516                         return ret;
6517                 }
6518         } else
6519                 ixgbe_remove_5tuple_filter(dev, filter);
6520
6521         return 0;
6522 }
6523
6524 /*
6525  * get a ntuple filter
6526  *
6527  * @param
6528  * dev: Pointer to struct rte_eth_dev.
6529  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6530  *
6531  * @return
6532  *    - On success, zero.
6533  *    - On failure, a negative value.
6534  */
6535 static int
6536 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6537                         struct rte_eth_ntuple_filter *ntuple_filter)
6538 {
6539         struct ixgbe_filter_info *filter_info =
6540                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6541         struct ixgbe_5tuple_filter_info filter_5tuple;
6542         struct ixgbe_5tuple_filter *filter;
6543         int ret;
6544
6545         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6546                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6547                 return -EINVAL;
6548         }
6549
6550         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6551         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6552         if (ret < 0)
6553                 return ret;
6554
6555         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6556                                          &filter_5tuple);
6557         if (filter == NULL) {
6558                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6559                 return -ENOENT;
6560         }
6561         ntuple_filter->queue = filter->queue;
6562         return 0;
6563 }
6564
6565 /*
6566  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6567  * @dev: pointer to rte_eth_dev structure
6568  * @filter_op:operation will be taken.
6569  * @arg: a pointer to specific structure corresponding to the filter_op
6570  *
6571  * @return
6572  *    - On success, zero.
6573  *    - On failure, a negative value.
6574  */
6575 static int
6576 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6577                                 enum rte_filter_op filter_op,
6578                                 void *arg)
6579 {
6580         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6581         int ret;
6582
6583         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6584
6585         if (filter_op == RTE_ETH_FILTER_NOP)
6586                 return 0;
6587
6588         if (arg == NULL) {
6589                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6590                             filter_op);
6591                 return -EINVAL;
6592         }
6593
6594         switch (filter_op) {
6595         case RTE_ETH_FILTER_ADD:
6596                 ret = ixgbe_add_del_ntuple_filter(dev,
6597                         (struct rte_eth_ntuple_filter *)arg,
6598                         TRUE);
6599                 break;
6600         case RTE_ETH_FILTER_DELETE:
6601                 ret = ixgbe_add_del_ntuple_filter(dev,
6602                         (struct rte_eth_ntuple_filter *)arg,
6603                         FALSE);
6604                 break;
6605         case RTE_ETH_FILTER_GET:
6606                 ret = ixgbe_get_ntuple_filter(dev,
6607                         (struct rte_eth_ntuple_filter *)arg);
6608                 break;
6609         default:
6610                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6611                 ret = -EINVAL;
6612                 break;
6613         }
6614         return ret;
6615 }
6616
6617 int
6618 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6619                         struct rte_eth_ethertype_filter *filter,
6620                         bool add)
6621 {
6622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6623         struct ixgbe_filter_info *filter_info =
6624                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6625         uint32_t etqf = 0;
6626         uint32_t etqs = 0;
6627         int ret;
6628         struct ixgbe_ethertype_filter ethertype_filter;
6629
6630         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6631                 return -EINVAL;
6632
6633         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6634                 filter->ether_type == ETHER_TYPE_IPv6) {
6635                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6636                         " ethertype filter.", filter->ether_type);
6637                 return -EINVAL;
6638         }
6639
6640         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6641                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6642                 return -EINVAL;
6643         }
6644         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6645                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6646                 return -EINVAL;
6647         }
6648
6649         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6650         if (ret >= 0 && add) {
6651                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6652                             filter->ether_type);
6653                 return -EEXIST;
6654         }
6655         if (ret < 0 && !add) {
6656                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6657                             filter->ether_type);
6658                 return -ENOENT;
6659         }
6660
6661         if (add) {
6662                 etqf = IXGBE_ETQF_FILTER_EN;
6663                 etqf |= (uint32_t)filter->ether_type;
6664                 etqs |= (uint32_t)((filter->queue <<
6665                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6666                                     IXGBE_ETQS_RX_QUEUE);
6667                 etqs |= IXGBE_ETQS_QUEUE_EN;
6668
6669                 ethertype_filter.ethertype = filter->ether_type;
6670                 ethertype_filter.etqf = etqf;
6671                 ethertype_filter.etqs = etqs;
6672                 ethertype_filter.conf = FALSE;
6673                 ret = ixgbe_ethertype_filter_insert(filter_info,
6674                                                     &ethertype_filter);
6675                 if (ret < 0) {
6676                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6677                         return -ENOSPC;
6678                 }
6679         } else {
6680                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6681                 if (ret < 0)
6682                         return -ENOSYS;
6683         }
6684         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6685         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6686         IXGBE_WRITE_FLUSH(hw);
6687
6688         return 0;
6689 }
6690
6691 static int
6692 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6693                         struct rte_eth_ethertype_filter *filter)
6694 {
6695         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6696         struct ixgbe_filter_info *filter_info =
6697                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6698         uint32_t etqf, etqs;
6699         int ret;
6700
6701         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6702         if (ret < 0) {
6703                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6704                             filter->ether_type);
6705                 return -ENOENT;
6706         }
6707
6708         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6709         if (etqf & IXGBE_ETQF_FILTER_EN) {
6710                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6711                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6712                 filter->flags = 0;
6713                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6714                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6715                 return 0;
6716         }
6717         return -ENOENT;
6718 }
6719
6720 /*
6721  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6722  * @dev: pointer to rte_eth_dev structure
6723  * @filter_op:operation will be taken.
6724  * @arg: a pointer to specific structure corresponding to the filter_op
6725  */
6726 static int
6727 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6728                                 enum rte_filter_op filter_op,
6729                                 void *arg)
6730 {
6731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6732         int ret;
6733
6734         MAC_TYPE_FILTER_SUP(hw->mac.type);
6735
6736         if (filter_op == RTE_ETH_FILTER_NOP)
6737                 return 0;
6738
6739         if (arg == NULL) {
6740                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6741                             filter_op);
6742                 return -EINVAL;
6743         }
6744
6745         switch (filter_op) {
6746         case RTE_ETH_FILTER_ADD:
6747                 ret = ixgbe_add_del_ethertype_filter(dev,
6748                         (struct rte_eth_ethertype_filter *)arg,
6749                         TRUE);
6750                 break;
6751         case RTE_ETH_FILTER_DELETE:
6752                 ret = ixgbe_add_del_ethertype_filter(dev,
6753                         (struct rte_eth_ethertype_filter *)arg,
6754                         FALSE);
6755                 break;
6756         case RTE_ETH_FILTER_GET:
6757                 ret = ixgbe_get_ethertype_filter(dev,
6758                         (struct rte_eth_ethertype_filter *)arg);
6759                 break;
6760         default:
6761                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6762                 ret = -EINVAL;
6763                 break;
6764         }
6765         return ret;
6766 }
6767
6768 static int
6769 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6770                      enum rte_filter_type filter_type,
6771                      enum rte_filter_op filter_op,
6772                      void *arg)
6773 {
6774         int ret = 0;
6775
6776         switch (filter_type) {
6777         case RTE_ETH_FILTER_NTUPLE:
6778                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6779                 break;
6780         case RTE_ETH_FILTER_ETHERTYPE:
6781                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6782                 break;
6783         case RTE_ETH_FILTER_SYN:
6784                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6785                 break;
6786         case RTE_ETH_FILTER_FDIR:
6787                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6788                 break;
6789         case RTE_ETH_FILTER_L2_TUNNEL:
6790                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6791                 break;
6792         case RTE_ETH_FILTER_GENERIC:
6793                 if (filter_op != RTE_ETH_FILTER_GET)
6794                         return -EINVAL;
6795                 *(const void **)arg = &ixgbe_flow_ops;
6796                 break;
6797         default:
6798                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6799                                                         filter_type);
6800                 ret = -EINVAL;
6801                 break;
6802         }
6803
6804         return ret;
6805 }
6806
6807 static u8 *
6808 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6809                         u8 **mc_addr_ptr, u32 *vmdq)
6810 {
6811         u8 *mc_addr;
6812
6813         *vmdq = 0;
6814         mc_addr = *mc_addr_ptr;
6815         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6816         return mc_addr;
6817 }
6818
6819 static int
6820 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6821                           struct ether_addr *mc_addr_set,
6822                           uint32_t nb_mc_addr)
6823 {
6824         struct ixgbe_hw *hw;
6825         u8 *mc_addr_list;
6826
6827         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6828         mc_addr_list = (u8 *)mc_addr_set;
6829         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6830                                          ixgbe_dev_addr_list_itr, TRUE);
6831 }
6832
6833 static uint64_t
6834 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6835 {
6836         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6837         uint64_t systime_cycles;
6838
6839         switch (hw->mac.type) {
6840         case ixgbe_mac_X550:
6841         case ixgbe_mac_X550EM_x:
6842         case ixgbe_mac_X550EM_a:
6843                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6844                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6845                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6846                                 * NSEC_PER_SEC;
6847                 break;
6848         default:
6849                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6850                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6851                                 << 32;
6852         }
6853
6854         return systime_cycles;
6855 }
6856
6857 static uint64_t
6858 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6859 {
6860         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6861         uint64_t rx_tstamp_cycles;
6862
6863         switch (hw->mac.type) {
6864         case ixgbe_mac_X550:
6865         case ixgbe_mac_X550EM_x:
6866         case ixgbe_mac_X550EM_a:
6867                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6868                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6869                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6870                                 * NSEC_PER_SEC;
6871                 break;
6872         default:
6873                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6874                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6875                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6876                                 << 32;
6877         }
6878
6879         return rx_tstamp_cycles;
6880 }
6881
6882 static uint64_t
6883 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6884 {
6885         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886         uint64_t tx_tstamp_cycles;
6887
6888         switch (hw->mac.type) {
6889         case ixgbe_mac_X550:
6890         case ixgbe_mac_X550EM_x:
6891         case ixgbe_mac_X550EM_a:
6892                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6893                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6894                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6895                                 * NSEC_PER_SEC;
6896                 break;
6897         default:
6898                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6899                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6900                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6901                                 << 32;
6902         }
6903
6904         return tx_tstamp_cycles;
6905 }
6906
6907 static void
6908 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6909 {
6910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6911         struct ixgbe_adapter *adapter =
6912                 (struct ixgbe_adapter *)dev->data->dev_private;
6913         struct rte_eth_link link;
6914         uint32_t incval = 0;
6915         uint32_t shift = 0;
6916
6917         /* Get current link speed. */
6918         ixgbe_dev_link_update(dev, 1);
6919         rte_eth_linkstatus_get(dev, &link);
6920
6921         switch (link.link_speed) {
6922         case ETH_SPEED_NUM_100M:
6923                 incval = IXGBE_INCVAL_100;
6924                 shift = IXGBE_INCVAL_SHIFT_100;
6925                 break;
6926         case ETH_SPEED_NUM_1G:
6927                 incval = IXGBE_INCVAL_1GB;
6928                 shift = IXGBE_INCVAL_SHIFT_1GB;
6929                 break;
6930         case ETH_SPEED_NUM_10G:
6931         default:
6932                 incval = IXGBE_INCVAL_10GB;
6933                 shift = IXGBE_INCVAL_SHIFT_10GB;
6934                 break;
6935         }
6936
6937         switch (hw->mac.type) {
6938         case ixgbe_mac_X550:
6939         case ixgbe_mac_X550EM_x:
6940         case ixgbe_mac_X550EM_a:
6941                 /* Independent of link speed. */
6942                 incval = 1;
6943                 /* Cycles read will be interpreted as ns. */
6944                 shift = 0;
6945                 /* Fall-through */
6946         case ixgbe_mac_X540:
6947                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6948                 break;
6949         case ixgbe_mac_82599EB:
6950                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6951                 shift -= IXGBE_INCVAL_SHIFT_82599;
6952                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6953                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6954                 break;
6955         default:
6956                 /* Not supported. */
6957                 return;
6958         }
6959
6960         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6961         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6962         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6963
6964         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6965         adapter->systime_tc.cc_shift = shift;
6966         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6967
6968         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6969         adapter->rx_tstamp_tc.cc_shift = shift;
6970         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6971
6972         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6973         adapter->tx_tstamp_tc.cc_shift = shift;
6974         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6975 }
6976
6977 static int
6978 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6979 {
6980         struct ixgbe_adapter *adapter =
6981                         (struct ixgbe_adapter *)dev->data->dev_private;
6982
6983         adapter->systime_tc.nsec += delta;
6984         adapter->rx_tstamp_tc.nsec += delta;
6985         adapter->tx_tstamp_tc.nsec += delta;
6986
6987         return 0;
6988 }
6989
6990 static int
6991 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6992 {
6993         uint64_t ns;
6994         struct ixgbe_adapter *adapter =
6995                         (struct ixgbe_adapter *)dev->data->dev_private;
6996
6997         ns = rte_timespec_to_ns(ts);
6998         /* Set the timecounters to a new value. */
6999         adapter->systime_tc.nsec = ns;
7000         adapter->rx_tstamp_tc.nsec = ns;
7001         adapter->tx_tstamp_tc.nsec = ns;
7002
7003         return 0;
7004 }
7005
7006 static int
7007 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7008 {
7009         uint64_t ns, systime_cycles;
7010         struct ixgbe_adapter *adapter =
7011                         (struct ixgbe_adapter *)dev->data->dev_private;
7012
7013         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7014         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7015         *ts = rte_ns_to_timespec(ns);
7016
7017         return 0;
7018 }
7019
7020 static int
7021 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7022 {
7023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7024         uint32_t tsync_ctl;
7025         uint32_t tsauxc;
7026
7027         /* Stop the timesync system time. */
7028         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7029         /* Reset the timesync system time value. */
7030         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7031         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7032
7033         /* Enable system time for platforms where it isn't on by default. */
7034         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7035         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7036         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7037
7038         ixgbe_start_timecounters(dev);
7039
7040         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7041         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7042                         (ETHER_TYPE_1588 |
7043                          IXGBE_ETQF_FILTER_EN |
7044                          IXGBE_ETQF_1588));
7045
7046         /* Enable timestamping of received PTP packets. */
7047         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7048         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7049         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7050
7051         /* Enable timestamping of transmitted PTP packets. */
7052         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7053         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7054         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7055
7056         IXGBE_WRITE_FLUSH(hw);
7057
7058         return 0;
7059 }
7060
7061 static int
7062 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7063 {
7064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7065         uint32_t tsync_ctl;
7066
7067         /* Disable timestamping of transmitted PTP packets. */
7068         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7069         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7070         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7071
7072         /* Disable timestamping of received PTP packets. */
7073         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7074         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7075         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7076
7077         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7078         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7079
7080         /* Stop incrementating the System Time registers. */
7081         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7082
7083         return 0;
7084 }
7085
7086 static int
7087 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7088                                  struct timespec *timestamp,
7089                                  uint32_t flags __rte_unused)
7090 {
7091         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7092         struct ixgbe_adapter *adapter =
7093                 (struct ixgbe_adapter *)dev->data->dev_private;
7094         uint32_t tsync_rxctl;
7095         uint64_t rx_tstamp_cycles;
7096         uint64_t ns;
7097
7098         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7099         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7100                 return -EINVAL;
7101
7102         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7103         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7104         *timestamp = rte_ns_to_timespec(ns);
7105
7106         return  0;
7107 }
7108
7109 static int
7110 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7111                                  struct timespec *timestamp)
7112 {
7113         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7114         struct ixgbe_adapter *adapter =
7115                 (struct ixgbe_adapter *)dev->data->dev_private;
7116         uint32_t tsync_txctl;
7117         uint64_t tx_tstamp_cycles;
7118         uint64_t ns;
7119
7120         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7121         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7122                 return -EINVAL;
7123
7124         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7125         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7126         *timestamp = rte_ns_to_timespec(ns);
7127
7128         return 0;
7129 }
7130
7131 static int
7132 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7133 {
7134         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135         int count = 0;
7136         int g_ind = 0;
7137         const struct reg_info *reg_group;
7138         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7139                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7140
7141         while ((reg_group = reg_set[g_ind++]))
7142                 count += ixgbe_regs_group_count(reg_group);
7143
7144         return count;
7145 }
7146
7147 static int
7148 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7149 {
7150         int count = 0;
7151         int g_ind = 0;
7152         const struct reg_info *reg_group;
7153
7154         while ((reg_group = ixgbevf_regs[g_ind++]))
7155                 count += ixgbe_regs_group_count(reg_group);
7156
7157         return count;
7158 }
7159
7160 static int
7161 ixgbe_get_regs(struct rte_eth_dev *dev,
7162               struct rte_dev_reg_info *regs)
7163 {
7164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7165         uint32_t *data = regs->data;
7166         int g_ind = 0;
7167         int count = 0;
7168         const struct reg_info *reg_group;
7169         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7170                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7171
7172         if (data == NULL) {
7173                 regs->length = ixgbe_get_reg_length(dev);
7174                 regs->width = sizeof(uint32_t);
7175                 return 0;
7176         }
7177
7178         /* Support only full register dump */
7179         if ((regs->length == 0) ||
7180             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7181                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7182                         hw->device_id;
7183                 while ((reg_group = reg_set[g_ind++]))
7184                         count += ixgbe_read_regs_group(dev, &data[count],
7185                                 reg_group);
7186                 return 0;
7187         }
7188
7189         return -ENOTSUP;
7190 }
7191
7192 static int
7193 ixgbevf_get_regs(struct rte_eth_dev *dev,
7194                 struct rte_dev_reg_info *regs)
7195 {
7196         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7197         uint32_t *data = regs->data;
7198         int g_ind = 0;
7199         int count = 0;
7200         const struct reg_info *reg_group;
7201
7202         if (data == NULL) {
7203                 regs->length = ixgbevf_get_reg_length(dev);
7204                 regs->width = sizeof(uint32_t);
7205                 return 0;
7206         }
7207
7208         /* Support only full register dump */
7209         if ((regs->length == 0) ||
7210             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7211                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7212                         hw->device_id;
7213                 while ((reg_group = ixgbevf_regs[g_ind++]))
7214                         count += ixgbe_read_regs_group(dev, &data[count],
7215                                                       reg_group);
7216                 return 0;
7217         }
7218
7219         return -ENOTSUP;
7220 }
7221
7222 static int
7223 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7224 {
7225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7226
7227         /* Return unit is byte count */
7228         return hw->eeprom.word_size * 2;
7229 }
7230
7231 static int
7232 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7233                 struct rte_dev_eeprom_info *in_eeprom)
7234 {
7235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7236         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7237         uint16_t *data = in_eeprom->data;
7238         int first, length;
7239
7240         first = in_eeprom->offset >> 1;
7241         length = in_eeprom->length >> 1;
7242         if ((first > hw->eeprom.word_size) ||
7243             ((first + length) > hw->eeprom.word_size))
7244                 return -EINVAL;
7245
7246         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7247
7248         return eeprom->ops.read_buffer(hw, first, length, data);
7249 }
7250
7251 static int
7252 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7253                 struct rte_dev_eeprom_info *in_eeprom)
7254 {
7255         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7256         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7257         uint16_t *data = in_eeprom->data;
7258         int first, length;
7259
7260         first = in_eeprom->offset >> 1;
7261         length = in_eeprom->length >> 1;
7262         if ((first > hw->eeprom.word_size) ||
7263             ((first + length) > hw->eeprom.word_size))
7264                 return -EINVAL;
7265
7266         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7267
7268         return eeprom->ops.write_buffer(hw,  first, length, data);
7269 }
7270
7271 static int
7272 ixgbe_get_module_info(struct rte_eth_dev *dev,
7273                       struct rte_eth_dev_module_info *modinfo)
7274 {
7275         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7276         uint32_t status;
7277         uint8_t sff8472_rev, addr_mode;
7278         bool page_swap = false;
7279
7280         /* Check whether we support SFF-8472 or not */
7281         status = hw->phy.ops.read_i2c_eeprom(hw,
7282                                              IXGBE_SFF_SFF_8472_COMP,
7283                                              &sff8472_rev);
7284         if (status != 0)
7285                 return -EIO;
7286
7287         /* addressing mode is not supported */
7288         status = hw->phy.ops.read_i2c_eeprom(hw,
7289                                              IXGBE_SFF_SFF_8472_SWAP,
7290                                              &addr_mode);
7291         if (status != 0)
7292                 return -EIO;
7293
7294         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7295                 PMD_DRV_LOG(ERR,
7296                             "Address change required to access page 0xA2, "
7297                             "but not supported. Please report the module "
7298                             "type to the driver maintainers.");
7299                 page_swap = true;
7300         }
7301
7302         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7303                 /* We have a SFP, but it does not support SFF-8472 */
7304                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7305                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7306         } else {
7307                 /* We have a SFP which supports a revision of SFF-8472. */
7308                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7309                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7310         }
7311
7312         return 0;
7313 }
7314
7315 static int
7316 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7317                         struct rte_dev_eeprom_info *info)
7318 {
7319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7320         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7321         uint8_t databyte = 0xFF;
7322         uint8_t *data = info->data;
7323         uint32_t i = 0;
7324
7325         if (info->length == 0)
7326                 return -EINVAL;
7327
7328         for (i = info->offset; i < info->offset + info->length; i++) {
7329                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7330                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7331                 else
7332                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7333
7334                 if (status != 0)
7335                         return -EIO;
7336
7337                 data[i - info->offset] = databyte;
7338         }
7339
7340         return 0;
7341 }
7342
7343 uint16_t
7344 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7345         switch (mac_type) {
7346         case ixgbe_mac_X550:
7347         case ixgbe_mac_X550EM_x:
7348         case ixgbe_mac_X550EM_a:
7349                 return ETH_RSS_RETA_SIZE_512;
7350         case ixgbe_mac_X550_vf:
7351         case ixgbe_mac_X550EM_x_vf:
7352         case ixgbe_mac_X550EM_a_vf:
7353                 return ETH_RSS_RETA_SIZE_64;
7354         default:
7355                 return ETH_RSS_RETA_SIZE_128;
7356         }
7357 }
7358
7359 uint32_t
7360 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7361         switch (mac_type) {
7362         case ixgbe_mac_X550:
7363         case ixgbe_mac_X550EM_x:
7364         case ixgbe_mac_X550EM_a:
7365                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7366                         return IXGBE_RETA(reta_idx >> 2);
7367                 else
7368                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7369         case ixgbe_mac_X550_vf:
7370         case ixgbe_mac_X550EM_x_vf:
7371         case ixgbe_mac_X550EM_a_vf:
7372                 return IXGBE_VFRETA(reta_idx >> 2);
7373         default:
7374                 return IXGBE_RETA(reta_idx >> 2);
7375         }
7376 }
7377
7378 uint32_t
7379 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7380         switch (mac_type) {
7381         case ixgbe_mac_X550_vf:
7382         case ixgbe_mac_X550EM_x_vf:
7383         case ixgbe_mac_X550EM_a_vf:
7384                 return IXGBE_VFMRQC;
7385         default:
7386                 return IXGBE_MRQC;
7387         }
7388 }
7389
7390 uint32_t
7391 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7392         switch (mac_type) {
7393         case ixgbe_mac_X550_vf:
7394         case ixgbe_mac_X550EM_x_vf:
7395         case ixgbe_mac_X550EM_a_vf:
7396                 return IXGBE_VFRSSRK(i);
7397         default:
7398                 return IXGBE_RSSRK(i);
7399         }
7400 }
7401
7402 bool
7403 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7404         switch (mac_type) {
7405         case ixgbe_mac_82599_vf:
7406         case ixgbe_mac_X540_vf:
7407                 return 0;
7408         default:
7409                 return 1;
7410         }
7411 }
7412
7413 static int
7414 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7415                         struct rte_eth_dcb_info *dcb_info)
7416 {
7417         struct ixgbe_dcb_config *dcb_config =
7418                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7419         struct ixgbe_dcb_tc_config *tc;
7420         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7421         uint8_t nb_tcs;
7422         uint8_t i, j;
7423
7424         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7425                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7426         else
7427                 dcb_info->nb_tcs = 1;
7428
7429         tc_queue = &dcb_info->tc_queue;
7430         nb_tcs = dcb_info->nb_tcs;
7431
7432         if (dcb_config->vt_mode) { /* vt is enabled*/
7433                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7434                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7435                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7436                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7437                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7438                         for (j = 0; j < nb_tcs; j++) {
7439                                 tc_queue->tc_rxq[0][j].base = j;
7440                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7441                                 tc_queue->tc_txq[0][j].base = j;
7442                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7443                         }
7444                 } else {
7445                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7446                                 for (j = 0; j < nb_tcs; j++) {
7447                                         tc_queue->tc_rxq[i][j].base =
7448                                                 i * nb_tcs + j;
7449                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7450                                         tc_queue->tc_txq[i][j].base =
7451                                                 i * nb_tcs + j;
7452                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7453                                 }
7454                         }
7455                 }
7456         } else { /* vt is disabled*/
7457                 struct rte_eth_dcb_rx_conf *rx_conf =
7458                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7459                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7460                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7461                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7462                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7463                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7464                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7465                         }
7466                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7467                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7468                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7469                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7470                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7471                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7472                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7473                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7474                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7475                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7476                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7477                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7478                         }
7479                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7480                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7481                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7482                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7483                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7484                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7485                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7486                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7487                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7488                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7489                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7490                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7491                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7492                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7493                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7494                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7495                 }
7496         }
7497         for (i = 0; i < dcb_info->nb_tcs; i++) {
7498                 tc = &dcb_config->tc_config[i];
7499                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7500         }
7501         return 0;
7502 }
7503
7504 /* Update e-tag ether type */
7505 static int
7506 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7507                             uint16_t ether_type)
7508 {
7509         uint32_t etag_etype;
7510
7511         if (hw->mac.type != ixgbe_mac_X550 &&
7512             hw->mac.type != ixgbe_mac_X550EM_x &&
7513             hw->mac.type != ixgbe_mac_X550EM_a) {
7514                 return -ENOTSUP;
7515         }
7516
7517         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7518         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7519         etag_etype |= ether_type;
7520         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7521         IXGBE_WRITE_FLUSH(hw);
7522
7523         return 0;
7524 }
7525
7526 /* Config l2 tunnel ether type */
7527 static int
7528 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7529                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7530 {
7531         int ret = 0;
7532         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7533         struct ixgbe_l2_tn_info *l2_tn_info =
7534                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7535
7536         if (l2_tunnel == NULL)
7537                 return -EINVAL;
7538
7539         switch (l2_tunnel->l2_tunnel_type) {
7540         case RTE_L2_TUNNEL_TYPE_E_TAG:
7541                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7542                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7543                 break;
7544         default:
7545                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7546                 ret = -EINVAL;
7547                 break;
7548         }
7549
7550         return ret;
7551 }
7552
7553 /* Enable e-tag tunnel */
7554 static int
7555 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7556 {
7557         uint32_t etag_etype;
7558
7559         if (hw->mac.type != ixgbe_mac_X550 &&
7560             hw->mac.type != ixgbe_mac_X550EM_x &&
7561             hw->mac.type != ixgbe_mac_X550EM_a) {
7562                 return -ENOTSUP;
7563         }
7564
7565         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7566         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7567         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7568         IXGBE_WRITE_FLUSH(hw);
7569
7570         return 0;
7571 }
7572
7573 /* Enable l2 tunnel */
7574 static int
7575 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7576                            enum rte_eth_tunnel_type l2_tunnel_type)
7577 {
7578         int ret = 0;
7579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7580         struct ixgbe_l2_tn_info *l2_tn_info =
7581                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7582
7583         switch (l2_tunnel_type) {
7584         case RTE_L2_TUNNEL_TYPE_E_TAG:
7585                 l2_tn_info->e_tag_en = TRUE;
7586                 ret = ixgbe_e_tag_enable(hw);
7587                 break;
7588         default:
7589                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7590                 ret = -EINVAL;
7591                 break;
7592         }
7593
7594         return ret;
7595 }
7596
7597 /* Disable e-tag tunnel */
7598 static int
7599 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7600 {
7601         uint32_t etag_etype;
7602
7603         if (hw->mac.type != ixgbe_mac_X550 &&
7604             hw->mac.type != ixgbe_mac_X550EM_x &&
7605             hw->mac.type != ixgbe_mac_X550EM_a) {
7606                 return -ENOTSUP;
7607         }
7608
7609         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7610         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7611         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7612         IXGBE_WRITE_FLUSH(hw);
7613
7614         return 0;
7615 }
7616
7617 /* Disable l2 tunnel */
7618 static int
7619 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7620                             enum rte_eth_tunnel_type l2_tunnel_type)
7621 {
7622         int ret = 0;
7623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7624         struct ixgbe_l2_tn_info *l2_tn_info =
7625                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7626
7627         switch (l2_tunnel_type) {
7628         case RTE_L2_TUNNEL_TYPE_E_TAG:
7629                 l2_tn_info->e_tag_en = FALSE;
7630                 ret = ixgbe_e_tag_disable(hw);
7631                 break;
7632         default:
7633                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7634                 ret = -EINVAL;
7635                 break;
7636         }
7637
7638         return ret;
7639 }
7640
7641 static int
7642 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7643                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7644 {
7645         int ret = 0;
7646         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7647         uint32_t i, rar_entries;
7648         uint32_t rar_low, rar_high;
7649
7650         if (hw->mac.type != ixgbe_mac_X550 &&
7651             hw->mac.type != ixgbe_mac_X550EM_x &&
7652             hw->mac.type != ixgbe_mac_X550EM_a) {
7653                 return -ENOTSUP;
7654         }
7655
7656         rar_entries = ixgbe_get_num_rx_addrs(hw);
7657
7658         for (i = 1; i < rar_entries; i++) {
7659                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7660                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7661                 if ((rar_high & IXGBE_RAH_AV) &&
7662                     (rar_high & IXGBE_RAH_ADTYPE) &&
7663                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7664                      l2_tunnel->tunnel_id)) {
7665                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7666                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7667
7668                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7669
7670                         return ret;
7671                 }
7672         }
7673
7674         return ret;
7675 }
7676
7677 static int
7678 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7679                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7680 {
7681         int ret = 0;
7682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7683         uint32_t i, rar_entries;
7684         uint32_t rar_low, rar_high;
7685
7686         if (hw->mac.type != ixgbe_mac_X550 &&
7687             hw->mac.type != ixgbe_mac_X550EM_x &&
7688             hw->mac.type != ixgbe_mac_X550EM_a) {
7689                 return -ENOTSUP;
7690         }
7691
7692         /* One entry for one tunnel. Try to remove potential existing entry. */
7693         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7694
7695         rar_entries = ixgbe_get_num_rx_addrs(hw);
7696
7697         for (i = 1; i < rar_entries; i++) {
7698                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7699                 if (rar_high & IXGBE_RAH_AV) {
7700                         continue;
7701                 } else {
7702                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7703                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7704                         rar_low = l2_tunnel->tunnel_id;
7705
7706                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7707                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7708
7709                         return ret;
7710                 }
7711         }
7712
7713         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7714                      " Please remove a rule before adding a new one.");
7715         return -EINVAL;
7716 }
7717
7718 static inline struct ixgbe_l2_tn_filter *
7719 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7720                           struct ixgbe_l2_tn_key *key)
7721 {
7722         int ret;
7723
7724         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7725         if (ret < 0)
7726                 return NULL;
7727
7728         return l2_tn_info->hash_map[ret];
7729 }
7730
7731 static inline int
7732 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7733                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7734 {
7735         int ret;
7736
7737         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7738                                &l2_tn_filter->key);
7739
7740         if (ret < 0) {
7741                 PMD_DRV_LOG(ERR,
7742                             "Failed to insert L2 tunnel filter"
7743                             " to hash table %d!",
7744                             ret);
7745                 return ret;
7746         }
7747
7748         l2_tn_info->hash_map[ret] = l2_tn_filter;
7749
7750         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7751
7752         return 0;
7753 }
7754
7755 static inline int
7756 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7757                           struct ixgbe_l2_tn_key *key)
7758 {
7759         int ret;
7760         struct ixgbe_l2_tn_filter *l2_tn_filter;
7761
7762         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7763
7764         if (ret < 0) {
7765                 PMD_DRV_LOG(ERR,
7766                             "No such L2 tunnel filter to delete %d!",
7767                             ret);
7768                 return ret;
7769         }
7770
7771         l2_tn_filter = l2_tn_info->hash_map[ret];
7772         l2_tn_info->hash_map[ret] = NULL;
7773
7774         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7775         rte_free(l2_tn_filter);
7776
7777         return 0;
7778 }
7779
7780 /* Add l2 tunnel filter */
7781 int
7782 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7783                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7784                                bool restore)
7785 {
7786         int ret;
7787         struct ixgbe_l2_tn_info *l2_tn_info =
7788                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7789         struct ixgbe_l2_tn_key key;
7790         struct ixgbe_l2_tn_filter *node;
7791
7792         if (!restore) {
7793                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7794                 key.tn_id = l2_tunnel->tunnel_id;
7795
7796                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7797
7798                 if (node) {
7799                         PMD_DRV_LOG(ERR,
7800                                     "The L2 tunnel filter already exists!");
7801                         return -EINVAL;
7802                 }
7803
7804                 node = rte_zmalloc("ixgbe_l2_tn",
7805                                    sizeof(struct ixgbe_l2_tn_filter),
7806                                    0);
7807                 if (!node)
7808                         return -ENOMEM;
7809
7810                 rte_memcpy(&node->key,
7811                                  &key,
7812                                  sizeof(struct ixgbe_l2_tn_key));
7813                 node->pool = l2_tunnel->pool;
7814                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7815                 if (ret < 0) {
7816                         rte_free(node);
7817                         return ret;
7818                 }
7819         }
7820
7821         switch (l2_tunnel->l2_tunnel_type) {
7822         case RTE_L2_TUNNEL_TYPE_E_TAG:
7823                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7824                 break;
7825         default:
7826                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7827                 ret = -EINVAL;
7828                 break;
7829         }
7830
7831         if ((!restore) && (ret < 0))
7832                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7833
7834         return ret;
7835 }
7836
7837 /* Delete l2 tunnel filter */
7838 int
7839 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7840                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7841 {
7842         int ret;
7843         struct ixgbe_l2_tn_info *l2_tn_info =
7844                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7845         struct ixgbe_l2_tn_key key;
7846
7847         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7848         key.tn_id = l2_tunnel->tunnel_id;
7849         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7850         if (ret < 0)
7851                 return ret;
7852
7853         switch (l2_tunnel->l2_tunnel_type) {
7854         case RTE_L2_TUNNEL_TYPE_E_TAG:
7855                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7856                 break;
7857         default:
7858                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7859                 ret = -EINVAL;
7860                 break;
7861         }
7862
7863         return ret;
7864 }
7865
7866 /**
7867  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7868  * @dev: pointer to rte_eth_dev structure
7869  * @filter_op:operation will be taken.
7870  * @arg: a pointer to specific structure corresponding to the filter_op
7871  */
7872 static int
7873 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7874                                   enum rte_filter_op filter_op,
7875                                   void *arg)
7876 {
7877         int ret;
7878
7879         if (filter_op == RTE_ETH_FILTER_NOP)
7880                 return 0;
7881
7882         if (arg == NULL) {
7883                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7884                             filter_op);
7885                 return -EINVAL;
7886         }
7887
7888         switch (filter_op) {
7889         case RTE_ETH_FILTER_ADD:
7890                 ret = ixgbe_dev_l2_tunnel_filter_add
7891                         (dev,
7892                          (struct rte_eth_l2_tunnel_conf *)arg,
7893                          FALSE);
7894                 break;
7895         case RTE_ETH_FILTER_DELETE:
7896                 ret = ixgbe_dev_l2_tunnel_filter_del
7897                         (dev,
7898                          (struct rte_eth_l2_tunnel_conf *)arg);
7899                 break;
7900         default:
7901                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7902                 ret = -EINVAL;
7903                 break;
7904         }
7905         return ret;
7906 }
7907
7908 static int
7909 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7910 {
7911         int ret = 0;
7912         uint32_t ctrl;
7913         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7914
7915         if (hw->mac.type != ixgbe_mac_X550 &&
7916             hw->mac.type != ixgbe_mac_X550EM_x &&
7917             hw->mac.type != ixgbe_mac_X550EM_a) {
7918                 return -ENOTSUP;
7919         }
7920
7921         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7922         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7923         if (en)
7924                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7925         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7926
7927         return ret;
7928 }
7929
7930 /* Enable l2 tunnel forwarding */
7931 static int
7932 ixgbe_dev_l2_tunnel_forwarding_enable
7933         (struct rte_eth_dev *dev,
7934          enum rte_eth_tunnel_type l2_tunnel_type)
7935 {
7936         struct ixgbe_l2_tn_info *l2_tn_info =
7937                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7938         int ret = 0;
7939
7940         switch (l2_tunnel_type) {
7941         case RTE_L2_TUNNEL_TYPE_E_TAG:
7942                 l2_tn_info->e_tag_fwd_en = TRUE;
7943                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7944                 break;
7945         default:
7946                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7947                 ret = -EINVAL;
7948                 break;
7949         }
7950
7951         return ret;
7952 }
7953
7954 /* Disable l2 tunnel forwarding */
7955 static int
7956 ixgbe_dev_l2_tunnel_forwarding_disable
7957         (struct rte_eth_dev *dev,
7958          enum rte_eth_tunnel_type l2_tunnel_type)
7959 {
7960         struct ixgbe_l2_tn_info *l2_tn_info =
7961                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7962         int ret = 0;
7963
7964         switch (l2_tunnel_type) {
7965         case RTE_L2_TUNNEL_TYPE_E_TAG:
7966                 l2_tn_info->e_tag_fwd_en = FALSE;
7967                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7968                 break;
7969         default:
7970                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7971                 ret = -EINVAL;
7972                 break;
7973         }
7974
7975         return ret;
7976 }
7977
7978 static int
7979 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7980                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7981                              bool en)
7982 {
7983         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7984         int ret = 0;
7985         uint32_t vmtir, vmvir;
7986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7987
7988         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7989                 PMD_DRV_LOG(ERR,
7990                             "VF id %u should be less than %u",
7991                             l2_tunnel->vf_id,
7992                             pci_dev->max_vfs);
7993                 return -EINVAL;
7994         }
7995
7996         if (hw->mac.type != ixgbe_mac_X550 &&
7997             hw->mac.type != ixgbe_mac_X550EM_x &&
7998             hw->mac.type != ixgbe_mac_X550EM_a) {
7999                 return -ENOTSUP;
8000         }
8001
8002         if (en)
8003                 vmtir = l2_tunnel->tunnel_id;
8004         else
8005                 vmtir = 0;
8006
8007         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8008
8009         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8010         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8011         if (en)
8012                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8013         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8014
8015         return ret;
8016 }
8017
8018 /* Enable l2 tunnel tag insertion */
8019 static int
8020 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8021                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8022 {
8023         int ret = 0;
8024
8025         switch (l2_tunnel->l2_tunnel_type) {
8026         case RTE_L2_TUNNEL_TYPE_E_TAG:
8027                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8028                 break;
8029         default:
8030                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8031                 ret = -EINVAL;
8032                 break;
8033         }
8034
8035         return ret;
8036 }
8037
8038 /* Disable l2 tunnel tag insertion */
8039 static int
8040 ixgbe_dev_l2_tunnel_insertion_disable
8041         (struct rte_eth_dev *dev,
8042          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8043 {
8044         int ret = 0;
8045
8046         switch (l2_tunnel->l2_tunnel_type) {
8047         case RTE_L2_TUNNEL_TYPE_E_TAG:
8048                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8049                 break;
8050         default:
8051                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8052                 ret = -EINVAL;
8053                 break;
8054         }
8055
8056         return ret;
8057 }
8058
8059 static int
8060 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8061                              bool en)
8062 {
8063         int ret = 0;
8064         uint32_t qde;
8065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8066
8067         if (hw->mac.type != ixgbe_mac_X550 &&
8068             hw->mac.type != ixgbe_mac_X550EM_x &&
8069             hw->mac.type != ixgbe_mac_X550EM_a) {
8070                 return -ENOTSUP;
8071         }
8072
8073         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8074         if (en)
8075                 qde |= IXGBE_QDE_STRIP_TAG;
8076         else
8077                 qde &= ~IXGBE_QDE_STRIP_TAG;
8078         qde &= ~IXGBE_QDE_READ;
8079         qde |= IXGBE_QDE_WRITE;
8080         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8081
8082         return ret;
8083 }
8084
8085 /* Enable l2 tunnel tag stripping */
8086 static int
8087 ixgbe_dev_l2_tunnel_stripping_enable
8088         (struct rte_eth_dev *dev,
8089          enum rte_eth_tunnel_type l2_tunnel_type)
8090 {
8091         int ret = 0;
8092
8093         switch (l2_tunnel_type) {
8094         case RTE_L2_TUNNEL_TYPE_E_TAG:
8095                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8096                 break;
8097         default:
8098                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8099                 ret = -EINVAL;
8100                 break;
8101         }
8102
8103         return ret;
8104 }
8105
8106 /* Disable l2 tunnel tag stripping */
8107 static int
8108 ixgbe_dev_l2_tunnel_stripping_disable
8109         (struct rte_eth_dev *dev,
8110          enum rte_eth_tunnel_type l2_tunnel_type)
8111 {
8112         int ret = 0;
8113
8114         switch (l2_tunnel_type) {
8115         case RTE_L2_TUNNEL_TYPE_E_TAG:
8116                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8117                 break;
8118         default:
8119                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8120                 ret = -EINVAL;
8121                 break;
8122         }
8123
8124         return ret;
8125 }
8126
8127 /* Enable/disable l2 tunnel offload functions */
8128 static int
8129 ixgbe_dev_l2_tunnel_offload_set
8130         (struct rte_eth_dev *dev,
8131          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8132          uint32_t mask,
8133          uint8_t en)
8134 {
8135         int ret = 0;
8136
8137         if (l2_tunnel == NULL)
8138                 return -EINVAL;
8139
8140         ret = -EINVAL;
8141         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8142                 if (en)
8143                         ret = ixgbe_dev_l2_tunnel_enable(
8144                                 dev,
8145                                 l2_tunnel->l2_tunnel_type);
8146                 else
8147                         ret = ixgbe_dev_l2_tunnel_disable(
8148                                 dev,
8149                                 l2_tunnel->l2_tunnel_type);
8150         }
8151
8152         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8153                 if (en)
8154                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8155                                 dev,
8156                                 l2_tunnel);
8157                 else
8158                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8159                                 dev,
8160                                 l2_tunnel);
8161         }
8162
8163         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8164                 if (en)
8165                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8166                                 dev,
8167                                 l2_tunnel->l2_tunnel_type);
8168                 else
8169                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8170                                 dev,
8171                                 l2_tunnel->l2_tunnel_type);
8172         }
8173
8174         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8175                 if (en)
8176                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8177                                 dev,
8178                                 l2_tunnel->l2_tunnel_type);
8179                 else
8180                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8181                                 dev,
8182                                 l2_tunnel->l2_tunnel_type);
8183         }
8184
8185         return ret;
8186 }
8187
8188 static int
8189 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8190                         uint16_t port)
8191 {
8192         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8193         IXGBE_WRITE_FLUSH(hw);
8194
8195         return 0;
8196 }
8197
8198 /* There's only one register for VxLAN UDP port.
8199  * So, we cannot add several ports. Will update it.
8200  */
8201 static int
8202 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8203                      uint16_t port)
8204 {
8205         if (port == 0) {
8206                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8207                 return -EINVAL;
8208         }
8209
8210         return ixgbe_update_vxlan_port(hw, port);
8211 }
8212
8213 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8214  * UDP port, it must have a value.
8215  * So, will reset it to the original value 0.
8216  */
8217 static int
8218 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8219                      uint16_t port)
8220 {
8221         uint16_t cur_port;
8222
8223         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8224
8225         if (cur_port != port) {
8226                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8227                 return -EINVAL;
8228         }
8229
8230         return ixgbe_update_vxlan_port(hw, 0);
8231 }
8232
8233 /* Add UDP tunneling port */
8234 static int
8235 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8236                               struct rte_eth_udp_tunnel *udp_tunnel)
8237 {
8238         int ret = 0;
8239         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8240
8241         if (hw->mac.type != ixgbe_mac_X550 &&
8242             hw->mac.type != ixgbe_mac_X550EM_x &&
8243             hw->mac.type != ixgbe_mac_X550EM_a) {
8244                 return -ENOTSUP;
8245         }
8246
8247         if (udp_tunnel == NULL)
8248                 return -EINVAL;
8249
8250         switch (udp_tunnel->prot_type) {
8251         case RTE_TUNNEL_TYPE_VXLAN:
8252                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8253                 break;
8254
8255         case RTE_TUNNEL_TYPE_GENEVE:
8256         case RTE_TUNNEL_TYPE_TEREDO:
8257                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8258                 ret = -EINVAL;
8259                 break;
8260
8261         default:
8262                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8263                 ret = -EINVAL;
8264                 break;
8265         }
8266
8267         return ret;
8268 }
8269
8270 /* Remove UDP tunneling port */
8271 static int
8272 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8273                               struct rte_eth_udp_tunnel *udp_tunnel)
8274 {
8275         int ret = 0;
8276         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8277
8278         if (hw->mac.type != ixgbe_mac_X550 &&
8279             hw->mac.type != ixgbe_mac_X550EM_x &&
8280             hw->mac.type != ixgbe_mac_X550EM_a) {
8281                 return -ENOTSUP;
8282         }
8283
8284         if (udp_tunnel == NULL)
8285                 return -EINVAL;
8286
8287         switch (udp_tunnel->prot_type) {
8288         case RTE_TUNNEL_TYPE_VXLAN:
8289                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8290                 break;
8291         case RTE_TUNNEL_TYPE_GENEVE:
8292         case RTE_TUNNEL_TYPE_TEREDO:
8293                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8294                 ret = -EINVAL;
8295                 break;
8296         default:
8297                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8298                 ret = -EINVAL;
8299                 break;
8300         }
8301
8302         return ret;
8303 }
8304
8305 static void
8306 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8307 {
8308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8309
8310         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8311 }
8312
8313 static void
8314 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8315 {
8316         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8317
8318         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8319 }
8320
8321 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8322 {
8323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8324         u32 in_msg = 0;
8325
8326         /* peek the message first */
8327         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8328
8329         /* PF reset VF event */
8330         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8331                 /* dummy mbx read to ack pf */
8332                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8333                         return;
8334                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8335                                               NULL);
8336         }
8337 }
8338
8339 static int
8340 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8341 {
8342         uint32_t eicr;
8343         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8344         struct ixgbe_interrupt *intr =
8345                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8346         ixgbevf_intr_disable(dev);
8347
8348         /* read-on-clear nic registers here */
8349         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8350         intr->flags = 0;
8351
8352         /* only one misc vector supported - mailbox */
8353         eicr &= IXGBE_VTEICR_MASK;
8354         if (eicr == IXGBE_MISC_VEC_ID)
8355                 intr->flags |= IXGBE_FLAG_MAILBOX;
8356
8357         return 0;
8358 }
8359
8360 static int
8361 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8362 {
8363         struct ixgbe_interrupt *intr =
8364                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8365
8366         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8367                 ixgbevf_mbx_process(dev);
8368                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8369         }
8370
8371         ixgbevf_intr_enable(dev);
8372
8373         return 0;
8374 }
8375
8376 static void
8377 ixgbevf_dev_interrupt_handler(void *param)
8378 {
8379         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8380
8381         ixgbevf_dev_interrupt_get_status(dev);
8382         ixgbevf_dev_interrupt_action(dev);
8383 }
8384
8385 /**
8386  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8387  *  @hw: pointer to hardware structure
8388  *
8389  *  Stops the transmit data path and waits for the HW to internally empty
8390  *  the Tx security block
8391  **/
8392 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8393 {
8394 #define IXGBE_MAX_SECTX_POLL 40
8395
8396         int i;
8397         int sectxreg;
8398
8399         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8400         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8401         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8402         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8403                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8404                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8405                         break;
8406                 /* Use interrupt-safe sleep just in case */
8407                 usec_delay(1000);
8408         }
8409
8410         /* For informational purposes only */
8411         if (i >= IXGBE_MAX_SECTX_POLL)
8412                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8413                          "path fully disabled.  Continuing with init.");
8414
8415         return IXGBE_SUCCESS;
8416 }
8417
8418 /**
8419  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8420  *  @hw: pointer to hardware structure
8421  *
8422  *  Enables the transmit data path.
8423  **/
8424 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8425 {
8426         uint32_t sectxreg;
8427
8428         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8429         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8430         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8431         IXGBE_WRITE_FLUSH(hw);
8432
8433         return IXGBE_SUCCESS;
8434 }
8435
8436 /* restore n-tuple filter */
8437 static inline void
8438 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8439 {
8440         struct ixgbe_filter_info *filter_info =
8441                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8442         struct ixgbe_5tuple_filter *node;
8443
8444         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8445                 ixgbe_inject_5tuple_filter(dev, node);
8446         }
8447 }
8448
8449 /* restore ethernet type filter */
8450 static inline void
8451 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8452 {
8453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8454         struct ixgbe_filter_info *filter_info =
8455                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8456         int i;
8457
8458         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8459                 if (filter_info->ethertype_mask & (1 << i)) {
8460                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8461                                         filter_info->ethertype_filters[i].etqf);
8462                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8463                                         filter_info->ethertype_filters[i].etqs);
8464                         IXGBE_WRITE_FLUSH(hw);
8465                 }
8466         }
8467 }
8468
8469 /* restore SYN filter */
8470 static inline void
8471 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8472 {
8473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8474         struct ixgbe_filter_info *filter_info =
8475                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8476         uint32_t synqf;
8477
8478         synqf = filter_info->syn_info;
8479
8480         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8481                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8482                 IXGBE_WRITE_FLUSH(hw);
8483         }
8484 }
8485
8486 /* restore L2 tunnel filter */
8487 static inline void
8488 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8489 {
8490         struct ixgbe_l2_tn_info *l2_tn_info =
8491                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8492         struct ixgbe_l2_tn_filter *node;
8493         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8494
8495         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8496                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8497                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8498                 l2_tn_conf.pool           = node->pool;
8499                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8500         }
8501 }
8502
8503 /* restore rss filter */
8504 static inline void
8505 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8506 {
8507         struct ixgbe_filter_info *filter_info =
8508                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8509
8510         if (filter_info->rss_info.conf.queue_num)
8511                 ixgbe_config_rss_filter(dev,
8512                         &filter_info->rss_info, TRUE);
8513 }
8514
8515 static int
8516 ixgbe_filter_restore(struct rte_eth_dev *dev)
8517 {
8518         ixgbe_ntuple_filter_restore(dev);
8519         ixgbe_ethertype_filter_restore(dev);
8520         ixgbe_syn_filter_restore(dev);
8521         ixgbe_fdir_filter_restore(dev);
8522         ixgbe_l2_tn_filter_restore(dev);
8523         ixgbe_rss_filter_restore(dev);
8524
8525         return 0;
8526 }
8527
8528 static void
8529 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8530 {
8531         struct ixgbe_l2_tn_info *l2_tn_info =
8532                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8533         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8534
8535         if (l2_tn_info->e_tag_en)
8536                 (void)ixgbe_e_tag_enable(hw);
8537
8538         if (l2_tn_info->e_tag_fwd_en)
8539                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8540
8541         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8542 }
8543
8544 /* remove all the n-tuple filters */
8545 void
8546 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8547 {
8548         struct ixgbe_filter_info *filter_info =
8549                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8550         struct ixgbe_5tuple_filter *p_5tuple;
8551
8552         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8553                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8554 }
8555
8556 /* remove all the ether type filters */
8557 void
8558 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8559 {
8560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8561         struct ixgbe_filter_info *filter_info =
8562                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8563         int i;
8564
8565         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8566                 if (filter_info->ethertype_mask & (1 << i) &&
8567                     !filter_info->ethertype_filters[i].conf) {
8568                         (void)ixgbe_ethertype_filter_remove(filter_info,
8569                                                             (uint8_t)i);
8570                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8571                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8572                         IXGBE_WRITE_FLUSH(hw);
8573                 }
8574         }
8575 }
8576
8577 /* remove the SYN filter */
8578 void
8579 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8580 {
8581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8582         struct ixgbe_filter_info *filter_info =
8583                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8584
8585         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8586                 filter_info->syn_info = 0;
8587
8588                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8589                 IXGBE_WRITE_FLUSH(hw);
8590         }
8591 }
8592
8593 /* remove all the L2 tunnel filters */
8594 int
8595 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8596 {
8597         struct ixgbe_l2_tn_info *l2_tn_info =
8598                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8599         struct ixgbe_l2_tn_filter *l2_tn_filter;
8600         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8601         int ret = 0;
8602
8603         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8604                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8605                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8606                 l2_tn_conf.pool           = l2_tn_filter->pool;
8607                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8608                 if (ret < 0)
8609                         return ret;
8610         }
8611
8612         return 0;
8613 }
8614
8615 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8616 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8617 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8618 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8619 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8620 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8621
8622 RTE_INIT(ixgbe_init_log)
8623 {
8624         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8625         if (ixgbe_logtype_init >= 0)
8626                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8627         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8628         if (ixgbe_logtype_driver >= 0)
8629                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8630 }