drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 #define IXGBE_HKEY_MAX_INDEX 10
 120
 121 /* Additional timesync values. */
 122 #define IXGBE_TIMINCA_16NS_SHIFT 24
 123 #define IXGBE_TIMINCA_INCVALUE   16000000
 124 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 125                                   | IXGBE_TIMINCA_INCVALUE)
 126
 127 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 128 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 129 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 131 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 132 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 133 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 134 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 135 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 136 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 137 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 138 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 139                                 int wait_to_complete);
 140 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 141                                 struct rte_eth_stats *stats);
 142 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 143 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 144                                              uint16_t queue_id,
 145                                              uint8_t stat_idx,
 146                                              uint8_t is_rx);
 147 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 148                                struct rte_eth_dev_info *dev_info);
 149 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 150                                  struct rte_eth_dev_info *dev_info);
 151 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 152
 153 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 154                 uint16_t vlan_id, int on);
 155 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 156 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 157                 uint16_t queue, bool on);
 158 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 159                 int on);
 160 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 162 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 163 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 164 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 165
 166 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 167 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 168 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 169                                struct rte_eth_fc_conf *fc_conf);
 170 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 171                                struct rte_eth_fc_conf *fc_conf);
 172 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 173                 struct rte_eth_pfc_conf *pfc_conf);
 174 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 175                         struct rte_eth_rss_reta_entry64 *reta_conf,
 176                         uint16_t reta_size);
 177 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 178                         struct rte_eth_rss_reta_entry64 *reta_conf,
 179                         uint16_t reta_size);
 180 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 181 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 183 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 184 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 185                 void *param);
 186 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 187 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 188                 uint32_t index, uint32_t pool);
 189 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 190 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 191
 192 /* For Virtual Function support */
 193 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 194 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 195 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 196 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 197 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 198 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 199 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 200                 struct rte_eth_stats *stats);
 201 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 202 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 203                 uint16_t vlan_id, int on);
 204 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 205                 uint16_t queue, int on);
 206 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 207 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 208
 209 /* For Eth VMDQ APIs support */
 210 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 211                 ether_addr* mac_addr,uint8_t on);
 212 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 213 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 214                 uint16_t rx_mask, uint8_t on);
 215 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 216 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 217 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 218                 uint64_t pool_mask,uint8_t vlan_on);
 219 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 220                 struct rte_eth_mirror_conf *mirror_conf,
 221                 uint8_t rule_id, uint8_t on);
 222 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 223                 uint8_t rule_id);
 224
 225 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 226                 uint16_t queue_idx, uint16_t tx_rate);
 227 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 228                 uint16_t tx_rate, uint64_t q_msk);
 229
 230 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 231                                  struct ether_addr *mac_addr,
 232                                  uint32_t index, uint32_t pool);
 233 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 234 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 235                         struct rte_eth_syn_filter *filter,
 236                         bool add);
 237 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 238                         struct rte_eth_syn_filter *filter);
 239 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 240                         enum rte_filter_op filter_op,
 241                         void *arg);
 242 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 243                         struct ixgbe_5tuple_filter *filter);
 244 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 245                         struct ixgbe_5tuple_filter *filter);
 246 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ntuple_filter *filter,
 248                         bool add);
 249 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 250                                 enum rte_filter_op filter_op,
 251                                 void *arg);
 252 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 253                         struct rte_eth_ntuple_filter *filter);
 254 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 255                         struct rte_eth_ethertype_filter *filter,
 256                         bool add);
 257 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 258                                 enum rte_filter_op filter_op,
 259                                 void *arg);
 260 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 261                         struct rte_eth_ethertype_filter *filter);
 262 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 263                      enum rte_filter_type filter_type,
 264                      enum rte_filter_op filter_op,
 265                      void *arg);
 266 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 267
 268 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 269                                       struct ether_addr *mc_addr_set,
 270                                       uint32_t nb_mc_addr);
 271
 272 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 273 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 274 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 275                                             struct timespec *timestamp,
 276                                             uint32_t flags);
 277 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 278                                             struct timespec *timestamp);
 279
 280 /*
 281  * Define VF Stats MACRO for Non "cleared on read" register
 282  */
 283 #define UPDATE_VF_STAT(reg, last, cur)                          \
 284 {                                                               \
 285         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 286         cur += latest - last;                                   \
 287         last = latest;                                          \
 288 }
 289
 290 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 291 {                                                                \
 292         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 293         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 294         u64 latest = ((new_msb << 32) | new_lsb);                \
 295         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 296         last = latest;                                           \
 297 }
 298
 299 #define IXGBE_SET_HWSTRIP(h, q) do{\
 300                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 301                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 302                 (h)->bitmap[idx] |= 1 << bit;\
 303         }while(0)
 304
 305 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 306                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 307                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 308                 (h)->bitmap[idx] &= ~(1 << bit);\
 309         }while(0)
 310
 311 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 312                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 313                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 314                 (r) = (h)->bitmap[idx] >> bit & 1;\
 315         }while(0)
 316
 317 /*
 318  * The set of PCI devices this driver supports
 319  */
 320 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 321
 322 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 323 #include "rte_pci_dev_ids.h"
 324
 325 { .vendor_id = 0, /* sentinel */ },
 326 };
 327
 328
 329 /*
 330  * The set of PCI devices this driver supports (for 82599 VF)
 331  */
 332 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 333
 334 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 335 #include "rte_pci_dev_ids.h"
 336 { .vendor_id = 0, /* sentinel */ },
 337
 338 };
 339
 340 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 341         .dev_configure        = ixgbe_dev_configure,
 342         .dev_start            = ixgbe_dev_start,
 343         .dev_stop             = ixgbe_dev_stop,
 344         .dev_set_link_up    = ixgbe_dev_set_link_up,
 345         .dev_set_link_down  = ixgbe_dev_set_link_down,
 346         .dev_close            = ixgbe_dev_close,
 347         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 348         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 349         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 350         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 351         .link_update          = ixgbe_dev_link_update,
 352         .stats_get            = ixgbe_dev_stats_get,
 353         .stats_reset          = ixgbe_dev_stats_reset,
 354         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 355         .dev_infos_get        = ixgbe_dev_info_get,
 356         .mtu_set              = ixgbe_dev_mtu_set,
 357         .vlan_filter_set      = ixgbe_vlan_filter_set,
 358         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 359         .vlan_offload_set     = ixgbe_vlan_offload_set,
 360         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 361         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 362         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 363         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 364         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 365         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 366         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 367         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 368         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 369         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 370         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 371         .dev_led_on           = ixgbe_dev_led_on,
 372         .dev_led_off          = ixgbe_dev_led_off,
 373         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 374         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 375         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 376         .mac_addr_add         = ixgbe_add_rar,
 377         .mac_addr_remove      = ixgbe_remove_rar,
 378         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 379         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 380         .mirror_rule_set      = ixgbe_mirror_rule_set,
 381         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 382         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 383         .set_vf_rx            = ixgbe_set_pool_rx,
 384         .set_vf_tx            = ixgbe_set_pool_tx,
 385         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 386         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 387         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 388         .reta_update          = ixgbe_dev_rss_reta_update,
 389         .reta_query           = ixgbe_dev_rss_reta_query,
 390 #ifdef RTE_NIC_BYPASS
 391         .bypass_init          = ixgbe_bypass_init,
 392         .bypass_state_set     = ixgbe_bypass_state_store,
 393         .bypass_state_show    = ixgbe_bypass_state_show,
 394         .bypass_event_set     = ixgbe_bypass_event_store,
 395         .bypass_event_show    = ixgbe_bypass_event_show,
 396         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 397         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 398         .bypass_ver_show      = ixgbe_bypass_ver_show,
 399         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 400 #endif /* RTE_NIC_BYPASS */
 401         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 402         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 403         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 404         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 405         .timesync_enable      = ixgbe_timesync_enable,
 406         .timesync_disable     = ixgbe_timesync_disable,
 407         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 408         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 409 };
 410
 411 /*
 412  * dev_ops for virtual function, bare necessities for basic vf
 413  * operation have been implemented
 414  */
 415 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 416         .dev_configure        = ixgbevf_dev_configure,
 417         .dev_start            = ixgbevf_dev_start,
 418         .dev_stop             = ixgbevf_dev_stop,
 419         .link_update          = ixgbe_dev_link_update,
 420         .stats_get            = ixgbevf_dev_stats_get,
 421         .stats_reset          = ixgbevf_dev_stats_reset,
 422         .dev_close            = ixgbevf_dev_close,
 423         .dev_infos_get        = ixgbevf_dev_info_get,
 424         .mtu_set              = ixgbevf_dev_set_mtu,
 425         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 426         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 427         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 428         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 429         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 430         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 431         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 432         .mac_addr_add         = ixgbevf_add_mac_addr,
 433         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 434         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 435 };
 436
 437 /**
 438  * Atomically reads the link status information from global
 439  * structure rte_eth_dev.
 440  *
 441  * @param dev
 442  *   - Pointer to the structure rte_eth_dev to read from.
 443  *   - Pointer to the buffer to be saved with the link status.
 444  *
 445  * @return
 446  *   - On success, zero.
 447  *   - On failure, negative value.
 448  */
 449 static inline int
 450 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 451                                 struct rte_eth_link *link)
 452 {
 453         struct rte_eth_link *dst = link;
 454         struct rte_eth_link *src = &(dev->data->dev_link);
 455
 456         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 457                                         *(uint64_t *)src) == 0)
 458                 return -1;
 459
 460         return 0;
 461 }
 462
 463 /**
 464  * Atomically writes the link status information into global
 465  * structure rte_eth_dev.
 466  *
 467  * @param dev
 468  *   - Pointer to the structure rte_eth_dev to read from.
 469  *   - Pointer to the buffer to be saved with the link status.
 470  *
 471  * @return
 472  *   - On success, zero.
 473  *   - On failure, negative value.
 474  */
 475 static inline int
 476 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 477                                 struct rte_eth_link *link)
 478 {
 479         struct rte_eth_link *dst = &(dev->data->dev_link);
 480         struct rte_eth_link *src = link;
 481
 482         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 483                                         *(uint64_t *)src) == 0)
 484                 return -1;
 485
 486         return 0;
 487 }
 488
 489 /*
 490  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 491  */
 492 static inline int
 493 ixgbe_is_sfp(struct ixgbe_hw *hw)
 494 {
 495         switch (hw->phy.type) {
 496         case ixgbe_phy_sfp_avago:
 497         case ixgbe_phy_sfp_ftl:
 498         case ixgbe_phy_sfp_intel:
 499         case ixgbe_phy_sfp_unknown:
 500         case ixgbe_phy_sfp_passive_tyco:
 501         case ixgbe_phy_sfp_passive_unknown:
 502                 return 1;
 503         default:
 504                 return 0;
 505         }
 506 }
 507
 508 static inline int32_t
 509 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 510 {
 511         uint32_t ctrl_ext;
 512         int32_t status;
 513
 514         status = ixgbe_reset_hw(hw);
 515
 516         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 517         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 518         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 519         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 520         IXGBE_WRITE_FLUSH(hw);
 521
 522         return status;
 523 }
 524
 525 static inline void
 526 ixgbe_enable_intr(struct rte_eth_dev *dev)
 527 {
 528         struct ixgbe_interrupt *intr =
 529                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 530         struct ixgbe_hw *hw =
 531                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 532
 533         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 534         IXGBE_WRITE_FLUSH(hw);
 535 }
 536
 537 /*
 538  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 539  */
 540 static void
 541 ixgbe_disable_intr(struct ixgbe_hw *hw)
 542 {
 543         PMD_INIT_FUNC_TRACE();
 544
 545         if (hw->mac.type == ixgbe_mac_82598EB) {
 546                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 547         } else {
 548                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 549                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 550                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 551         }
 552         IXGBE_WRITE_FLUSH(hw);
 553 }
 554
 555 /*
 556  * This function resets queue statistics mapping registers.
 557  * From Niantic datasheet, Initialization of Statistics section:
 558  * "...if software requires the queue counters, the RQSMR and TQSM registers
 559  * must be re-programmed following a device reset.
 560  */
 561 static void
 562 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 563 {
 564         uint32_t i;
 565
 566         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 567                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 568                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 569         }
 570 }
 571
 572
 573 static int
 574 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 575                                   uint16_t queue_id,
 576                                   uint8_t stat_idx,
 577                                   uint8_t is_rx)
 578 {
 579 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 580 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 581 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 582
 583         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 584         struct ixgbe_stat_mapping_registers *stat_mappings =
 585                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 586         uint32_t qsmr_mask = 0;
 587         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 588         uint32_t q_map;
 589         uint8_t n, offset;
 590
 591         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 592                 (hw->mac.type != ixgbe_mac_X540) &&
 593                 (hw->mac.type != ixgbe_mac_X550) &&
 594                 (hw->mac.type != ixgbe_mac_X550EM_x))
 595                 return -ENOSYS;
 596
 597         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 598                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 599                      queue_id, stat_idx);
 600
 601         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 602         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 603                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 604                 return -EIO;
 605         }
 606         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 607
 608         /* Now clear any previous stat_idx set */
 609         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 610         if (!is_rx)
 611                 stat_mappings->tqsm[n] &= ~clearing_mask;
 612         else
 613                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 614
 615         q_map = (uint32_t)stat_idx;
 616         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 617         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 618         if (!is_rx)
 619                 stat_mappings->tqsm[n] |= qsmr_mask;
 620         else
 621                 stat_mappings->rqsmr[n] |= qsmr_mask;
 622
 623         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 624                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 625                      queue_id, stat_idx);
 626         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 627                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 628
 629         /* Now write the mapping in the appropriate register */
 630         if (is_rx) {
 631                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 632                              stat_mappings->rqsmr[n], n);
 633                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 634         }
 635         else {
 636                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 637                              stat_mappings->tqsm[n], n);
 638                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 639         }
 640         return 0;
 641 }
 642
 643 static void
 644 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 645 {
 646         struct ixgbe_stat_mapping_registers *stat_mappings =
 647                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 649         int i;
 650
 651         /* write whatever was in stat mapping table to the NIC */
 652         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 653                 /* rx */
 654                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 655
 656                 /* tx */
 657                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 658         }
 659 }
 660
 661 static void
 662 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 663 {
 664         uint8_t i;
 665         struct ixgbe_dcb_tc_config *tc;
 666         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 667
 668         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 669         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 670         for (i = 0; i < dcb_max_tc; i++) {
 671                 tc = &dcb_config->tc_config[i];
 672                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 673                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 674                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 675                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 676                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 677                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 678                 tc->pfc = ixgbe_dcb_pfc_disabled;
 679         }
 680
 681         /* Initialize default user to priority mapping, UPx->TC0 */
 682         tc = &dcb_config->tc_config[0];
 683         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 684         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 685         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 686                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 687                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 688         }
 689         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 690         dcb_config->pfc_mode_enable = false;
 691         dcb_config->vt_mode = true;
 692         dcb_config->round_robin_enable = false;
 693         /* support all DCB capabilities in 82599 */
 694         dcb_config->support.capabilities = 0xFF;
 695
 696         /*we only support 4 Tcs for X540, X550 */
 697         if (hw->mac.type == ixgbe_mac_X540 ||
 698                 hw->mac.type == ixgbe_mac_X550 ||
 699                 hw->mac.type == ixgbe_mac_X550EM_x) {
 700                 dcb_config->num_tcs.pg_tcs = 4;
 701                 dcb_config->num_tcs.pfc_tcs = 4;
 702         }
 703 }
 704
 705 /*
 706  * Ensure that all locks are released before first NVM or PHY access
 707  */
 708 static void
 709 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 710 {
 711         uint16_t mask;
 712
 713         /*
 714          * Phy lock should not fail in this early stage. If this is the case,
 715          * it is due to an improper exit of the application.
 716          * So force the release of the faulty lock. Release of common lock
 717          * is done automatically by swfw_sync function.
 718          */
 719         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 720         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 721                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 722         }
 723         ixgbe_release_swfw_semaphore(hw, mask);
 724
 725         /*
 726          * These ones are more tricky since they are common to all ports; but
 727          * swfw_sync retries last long enough (1s) to be almost sure that if
 728          * lock can not be taken it is due to an improper lock of the
 729          * semaphore.
 730          */
 731         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 732         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 733                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 734         }
 735         ixgbe_release_swfw_semaphore(hw, mask);
 736 }
 737
 738 /*
 739  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 740  * It returns 0 on success.
 741  */
 742 static int
 743 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 744 {
 745         struct rte_pci_device *pci_dev;
 746         struct ixgbe_hw *hw =
 747                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 748         struct ixgbe_vfta * shadow_vfta =
 749                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 750         struct ixgbe_hwstrip *hwstrip =
 751                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 752         struct ixgbe_dcb_config *dcb_config =
 753                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 754         struct ixgbe_filter_info *filter_info =
 755                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 756         uint32_t ctrl_ext;
 757         uint16_t csum;
 758         int diag, i;
 759
 760         PMD_INIT_FUNC_TRACE();
 761
 762         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 763         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 764         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 765
 766         /*
 767          * For secondary processes, we don't initialise any further as primary
 768          * has already done this work. Only check we don't need a different
 769          * RX and TX function.
 770          */
 771         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 772                 struct ixgbe_tx_queue *txq;
 773                 /* TX queue function in primary, set by last queue initialized
 774                  * Tx queue may not initialized by primary process */
 775                 if (eth_dev->data->tx_queues) {
 776                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 777                         ixgbe_set_tx_function(eth_dev, txq);
 778                 } else {
 779                         /* Use default TX function if we get here */
 780                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 781                                            "Using default TX function.");
 782                 }
 783
 784                 ixgbe_set_rx_function(eth_dev);
 785
 786                 return 0;
 787         }
 788         pci_dev = eth_dev->pci_dev;
 789
 790         /* Vendor and Device ID need to be set before init of shared code */
 791         hw->device_id = pci_dev->id.device_id;
 792         hw->vendor_id = pci_dev->id.vendor_id;
 793         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 794         hw->allow_unsupported_sfp = 1;
 795
 796         /* Initialize the shared code (base driver) */
 797 #ifdef RTE_NIC_BYPASS
 798         diag = ixgbe_bypass_init_shared_code(hw);
 799 #else
 800         diag = ixgbe_init_shared_code(hw);
 801 #endif /* RTE_NIC_BYPASS */
 802
 803         if (diag != IXGBE_SUCCESS) {
 804                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 805                 return -EIO;
 806         }
 807
 808         /* pick up the PCI bus settings for reporting later */
 809         ixgbe_get_bus_info(hw);
 810
 811         /* Unlock any pending hardware semaphore */
 812         ixgbe_swfw_lock_reset(hw);
 813
 814         /* Initialize DCB configuration*/
 815         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 816         ixgbe_dcb_init(hw,dcb_config);
 817         /* Get Hardware Flow Control setting */
 818         hw->fc.requested_mode = ixgbe_fc_full;
 819         hw->fc.current_mode = ixgbe_fc_full;
 820         hw->fc.pause_time = IXGBE_FC_PAUSE;
 821         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 822                 hw->fc.low_water[i] = IXGBE_FC_LO;
 823                 hw->fc.high_water[i] = IXGBE_FC_HI;
 824         }
 825         hw->fc.send_xon = 1;
 826
 827         /* Make sure we have a good EEPROM before we read from it */
 828         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 829         if (diag != IXGBE_SUCCESS) {
 830                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 831                 return -EIO;
 832         }
 833
 834 #ifdef RTE_NIC_BYPASS
 835         diag = ixgbe_bypass_init_hw(hw);
 836 #else
 837         diag = ixgbe_init_hw(hw);
 838 #endif /* RTE_NIC_BYPASS */
 839
 840         /*
 841          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 842          * is called too soon after the kernel driver unbinding/binding occurs.
 843          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 844          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 845          * also called. See ixgbe_identify_phy_82599(). The reason for the
 846          * failure is not known, and only occuts when virtualisation features
 847          * are disabled in the bios. A delay of 100ms  was found to be enough by
 848          * trial-and-error, and is doubled to be safe.
 849          */
 850         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 851                 rte_delay_ms(200);
 852                 diag = ixgbe_init_hw(hw);
 853         }
 854
 855         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 856                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 857                     "LOM.  Please be aware there may be issues associated "
 858                     "with your hardware.");
 859                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 860                     "please contact your Intel or hardware representative "
 861                     "who provided you with this hardware.");
 862         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 863                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 864         if (diag) {
 865                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 866                 return -EIO;
 867         }
 868
 869         /* disable interrupt */
 870         ixgbe_disable_intr(hw);
 871
 872         /* reset mappings for queue statistics hw counters*/
 873         ixgbe_reset_qstat_mappings(hw);
 874
 875         /* Allocate memory for storing MAC addresses */
 876         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 877                         hw->mac.num_rar_entries, 0);
 878         if (eth_dev->data->mac_addrs == NULL) {
 879                 PMD_INIT_LOG(ERR,
 880                         "Failed to allocate %u bytes needed to store "
 881                         "MAC addresses",
 882                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 883                 return -ENOMEM;
 884         }
 885         /* Copy the permanent MAC address */
 886         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 887                         &eth_dev->data->mac_addrs[0]);
 888
 889         /* Allocate memory for storing hash filter MAC addresses */
 890         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 891                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 892         if (eth_dev->data->hash_mac_addrs == NULL) {
 893                 PMD_INIT_LOG(ERR,
 894                         "Failed to allocate %d bytes needed to store MAC addresses",
 895                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 896                 return -ENOMEM;
 897         }
 898
 899         /* initialize the vfta */
 900         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 901
 902         /* initialize the hw strip bitmap*/
 903         memset(hwstrip, 0, sizeof(*hwstrip));
 904
 905         /* initialize PF if max_vfs not zero */
 906         ixgbe_pf_host_init(eth_dev);
 907
 908         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 909         /* let hardware know driver is loaded */
 910         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 911         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 912         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 913         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 914         IXGBE_WRITE_FLUSH(hw);
 915
 916         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 917                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 918                              (int) hw->mac.type, (int) hw->phy.type,
 919                              (int) hw->phy.sfp_type);
 920         else
 921                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 922                              (int) hw->mac.type, (int) hw->phy.type);
 923
 924         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 925                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 926                         pci_dev->id.device_id);
 927
 928         rte_intr_callback_register(&(pci_dev->intr_handle),
 929                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 930
 931         /* enable uio intr after callback register */
 932         rte_intr_enable(&(pci_dev->intr_handle));
 933
 934         /* enable support intr */
 935         ixgbe_enable_intr(eth_dev);
 936
 937         /* initialize 5tuple filter list */
 938         TAILQ_INIT(&filter_info->fivetuple_list);
 939         memset(filter_info->fivetuple_mask, 0,
 940                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 941
 942         return 0;
 943 }
 944
 945
 946 /*
 947  * Negotiate mailbox API version with the PF.
 948  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 949  * Then we try to negotiate starting with the most recent one.
 950  * If all negotiation attempts fail, then we will proceed with
 951  * the default one (ixgbe_mbox_api_10).
 952  */
 953 static void
 954 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 955 {
 956         int32_t i;
 957
 958         /* start with highest supported, proceed down */
 959         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 960                 ixgbe_mbox_api_11,
 961                 ixgbe_mbox_api_10,
 962         };
 963
 964         for (i = 0;
 965                         i != RTE_DIM(sup_ver) &&
 966                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 967                         i++)
 968                 ;
 969 }
 970
 971 static void
 972 generate_random_mac_addr(struct ether_addr *mac_addr)
 973 {
 974         uint64_t random;
 975
 976         /* Set Organizationally Unique Identifier (OUI) prefix. */
 977         mac_addr->addr_bytes[0] = 0x00;
 978         mac_addr->addr_bytes[1] = 0x09;
 979         mac_addr->addr_bytes[2] = 0xC0;
 980         /* Force indication of locally assigned MAC address. */
 981         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 982         /* Generate the last 3 bytes of the MAC address with a random number. */
 983         random = rte_rand();
 984         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 985 }
 986
 987 /*
 988  * Virtual Function device init
 989  */
 990 static int
 991 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 992 {
 993         int diag;
 994         uint32_t tc, tcs;
 995         struct rte_pci_device *pci_dev;
 996         struct ixgbe_hw *hw =
 997                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 998         struct ixgbe_vfta * shadow_vfta =
 999                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1000         struct ixgbe_hwstrip *hwstrip =
1001                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1002         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1003
1004         PMD_INIT_FUNC_TRACE();
1005
1006         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1007         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1008         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1009
1010         /* for secondary processes, we don't initialise any further as primary
1011          * has already done this work. Only check we don't need a different
1012          * RX function */
1013         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1014                 if (eth_dev->data->scattered_rx)
1015                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1016                 return 0;
1017         }
1018
1019         pci_dev = eth_dev->pci_dev;
1020
1021         hw->device_id = pci_dev->id.device_id;
1022         hw->vendor_id = pci_dev->id.vendor_id;
1023         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1024
1025         /* initialize the vfta */
1026         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1027
1028         /* initialize the hw strip bitmap*/
1029         memset(hwstrip, 0, sizeof(*hwstrip));
1030
1031         /* Initialize the shared code (base driver) */
1032         diag = ixgbe_init_shared_code(hw);
1033         if (diag != IXGBE_SUCCESS) {
1034                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1035                 return -EIO;
1036         }
1037
1038         /* init_mailbox_params */
1039         hw->mbx.ops.init_params(hw);
1040
1041         /* Disable the interrupts for VF */
1042         ixgbevf_intr_disable(hw);
1043
1044         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1045         diag = hw->mac.ops.reset_hw(hw);
1046
1047         /*
1048          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1049          * the underlying PF driver has not assigned a MAC address to the VF.
1050          * In this case, assign a random MAC address.
1051          */
1052         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1053                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1054                 return (diag);
1055         }
1056
1057         /* negotiate mailbox API version to use with the PF. */
1058         ixgbevf_negotiate_api(hw);
1059
1060         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1061         ixgbevf_get_queues(hw, &tcs, &tc);
1062
1063         /* Allocate memory for storing MAC addresses */
1064         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1065                         hw->mac.num_rar_entries, 0);
1066         if (eth_dev->data->mac_addrs == NULL) {
1067                 PMD_INIT_LOG(ERR,
1068                         "Failed to allocate %u bytes needed to store "
1069                         "MAC addresses",
1070                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1071                 return -ENOMEM;
1072         }
1073
1074         /* Generate a random MAC address, if none was assigned by PF. */
1075         if (is_zero_ether_addr(perm_addr)) {
1076                 generate_random_mac_addr(perm_addr);
1077                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1078                 if (diag) {
1079                         rte_free(eth_dev->data->mac_addrs);
1080                         eth_dev->data->mac_addrs = NULL;
1081                         return diag;
1082                 }
1083                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1084                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1085                              "%02x:%02x:%02x:%02x:%02x:%02x",
1086                              perm_addr->addr_bytes[0],
1087                              perm_addr->addr_bytes[1],
1088                              perm_addr->addr_bytes[2],
1089                              perm_addr->addr_bytes[3],
1090                              perm_addr->addr_bytes[4],
1091                              perm_addr->addr_bytes[5]);
1092         }
1093
1094         /* Copy the permanent MAC address */
1095         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1096
1097         /* reset the hardware with the new settings */
1098         diag = hw->mac.ops.start_hw(hw);
1099         switch (diag) {
1100                 case  0:
1101                         break;
1102
1103                 default:
1104                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1105                         return (-EIO);
1106         }
1107
1108         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1109                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1110                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1111
1112         return 0;
1113 }
1114
1115 static struct eth_driver rte_ixgbe_pmd = {
1116         .pci_drv = {
1117                 .name = "rte_ixgbe_pmd",
1118                 .id_table = pci_id_ixgbe_map,
1119                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1120         },
1121         .eth_dev_init = eth_ixgbe_dev_init,
1122         .dev_private_size = sizeof(struct ixgbe_adapter),
1123 };
1124
1125 /*
1126  * virtual function driver struct
1127  */
1128 static struct eth_driver rte_ixgbevf_pmd = {
1129         .pci_drv = {
1130                 .name = "rte_ixgbevf_pmd",
1131                 .id_table = pci_id_ixgbevf_map,
1132                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1133         },
1134         .eth_dev_init = eth_ixgbevf_dev_init,
1135         .dev_private_size = sizeof(struct ixgbe_adapter),
1136 };
1137
1138 /*
1139  * Driver initialization routine.
1140  * Invoked once at EAL init time.
1141  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1142  */
1143 static int
1144 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1145 {
1146         PMD_INIT_FUNC_TRACE();
1147
1148         rte_eth_driver_register(&rte_ixgbe_pmd);
1149         return 0;
1150 }
1151
1152 /*
1153  * VF Driver initialization routine.
1154  * Invoked one at EAL init time.
1155  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1156  */
1157 static int
1158 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1159 {
1160         PMD_INIT_FUNC_TRACE();
1161
1162         rte_eth_driver_register(&rte_ixgbevf_pmd);
1163         return (0);
1164 }
1165
1166 static int
1167 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1168 {
1169         struct ixgbe_hw *hw =
1170                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1171         struct ixgbe_vfta * shadow_vfta =
1172                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1173         uint32_t vfta;
1174         uint32_t vid_idx;
1175         uint32_t vid_bit;
1176
1177         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1178         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1179         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1180         if (on)
1181                 vfta |= vid_bit;
1182         else
1183                 vfta &= ~vid_bit;
1184         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1185
1186         /* update local VFTA copy */
1187         shadow_vfta->vfta[vid_idx] = vfta;
1188
1189         return 0;
1190 }
1191
1192 static void
1193 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1194 {
1195         if (on)
1196                 ixgbe_vlan_hw_strip_enable(dev, queue);
1197         else
1198                 ixgbe_vlan_hw_strip_disable(dev, queue);
1199 }
1200
1201 static void
1202 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1203 {
1204         struct ixgbe_hw *hw =
1205                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1206
1207         /* Only the high 16-bits is valid */
1208         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1209 }
1210
1211 void
1212 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1213 {
1214         struct ixgbe_hw *hw =
1215                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1216         uint32_t vlnctrl;
1217
1218         PMD_INIT_FUNC_TRACE();
1219
1220         /* Filter Table Disable */
1221         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1222         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1223
1224         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1225 }
1226
1227 void
1228 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1229 {
1230         struct ixgbe_hw *hw =
1231                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         struct ixgbe_vfta * shadow_vfta =
1233                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1234         uint32_t vlnctrl;
1235         uint16_t i;
1236
1237         PMD_INIT_FUNC_TRACE();
1238
1239         /* Filter Table Enable */
1240         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1241         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1242         vlnctrl |= IXGBE_VLNCTRL_VFE;
1243
1244         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1245
1246         /* write whatever is in local vfta copy */
1247         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1248                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1249 }
1250
1251 static void
1252 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1253 {
1254         struct ixgbe_hwstrip *hwstrip =
1255                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1256
1257         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1258                 return;
1259
1260         if (on)
1261                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1262         else
1263                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1264 }
1265
1266 static void
1267 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1268 {
1269         struct ixgbe_hw *hw =
1270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271         uint32_t ctrl;
1272
1273         PMD_INIT_FUNC_TRACE();
1274
1275         if (hw->mac.type == ixgbe_mac_82598EB) {
1276                 /* No queue level support */
1277                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1278                 return;
1279         }
1280         else {
1281                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1282                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1283                 ctrl &= ~IXGBE_RXDCTL_VME;
1284                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1285         }
1286         /* record those setting for HW strip per queue */
1287         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1288 }
1289
1290 static void
1291 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1292 {
1293         struct ixgbe_hw *hw =
1294                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295         uint32_t ctrl;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (hw->mac.type == ixgbe_mac_82598EB) {
1300                 /* No queue level supported */
1301                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1302                 return;
1303         }
1304         else {
1305                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1306                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1307                 ctrl |= IXGBE_RXDCTL_VME;
1308                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1309         }
1310         /* record those setting for HW strip per queue */
1311         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1312 }
1313
1314 void
1315 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1316 {
1317         struct ixgbe_hw *hw =
1318                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319         uint32_t ctrl;
1320         uint16_t i;
1321
1322         PMD_INIT_FUNC_TRACE();
1323
1324         if (hw->mac.type == ixgbe_mac_82598EB) {
1325                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1326                 ctrl &= ~IXGBE_VLNCTRL_VME;
1327                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1328         }
1329         else {
1330                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1331                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1332                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1333                         ctrl &= ~IXGBE_RXDCTL_VME;
1334                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1335
1336                         /* record those setting for HW strip per queue */
1337                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1338                 }
1339         }
1340 }
1341
1342 void
1343 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1344 {
1345         struct ixgbe_hw *hw =
1346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1347         uint32_t ctrl;
1348         uint16_t i;
1349
1350         PMD_INIT_FUNC_TRACE();
1351
1352         if (hw->mac.type == ixgbe_mac_82598EB) {
1353                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1354                 ctrl |= IXGBE_VLNCTRL_VME;
1355                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1356         }
1357         else {
1358                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1359                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1360                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1361                         ctrl |= IXGBE_RXDCTL_VME;
1362                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1363
1364                         /* record those setting for HW strip per queue */
1365                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1366                 }
1367         }
1368 }
1369
1370 static void
1371 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1372 {
1373         struct ixgbe_hw *hw =
1374                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1375         uint32_t ctrl;
1376
1377         PMD_INIT_FUNC_TRACE();
1378
1379         /* DMATXCTRL: Geric Double VLAN Disable */
1380         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1381         ctrl &= ~IXGBE_DMATXCTL_GDV;
1382         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1383
1384         /* CTRL_EXT: Global Double VLAN Disable */
1385         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1386         ctrl &= ~IXGBE_EXTENDED_VLAN;
1387         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1388
1389 }
1390
1391 static void
1392 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1393 {
1394         struct ixgbe_hw *hw =
1395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396         uint32_t ctrl;
1397
1398         PMD_INIT_FUNC_TRACE();
1399
1400         /* DMATXCTRL: Geric Double VLAN Enable */
1401         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1402         ctrl |= IXGBE_DMATXCTL_GDV;
1403         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1404
1405         /* CTRL_EXT: Global Double VLAN Enable */
1406         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1407         ctrl |= IXGBE_EXTENDED_VLAN;
1408         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1409
1410         /*
1411          * VET EXT field in the EXVET register = 0x8100 by default
1412          * So no need to change. Same to VT field of DMATXCTL register
1413          */
1414 }
1415
1416 static void
1417 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1418 {
1419         if(mask & ETH_VLAN_STRIP_MASK){
1420                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1421                         ixgbe_vlan_hw_strip_enable_all(dev);
1422                 else
1423                         ixgbe_vlan_hw_strip_disable_all(dev);
1424         }
1425
1426         if(mask & ETH_VLAN_FILTER_MASK){
1427                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1428                         ixgbe_vlan_hw_filter_enable(dev);
1429                 else
1430                         ixgbe_vlan_hw_filter_disable(dev);
1431         }
1432
1433         if(mask & ETH_VLAN_EXTEND_MASK){
1434                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1435                         ixgbe_vlan_hw_extend_enable(dev);
1436                 else
1437                         ixgbe_vlan_hw_extend_disable(dev);
1438         }
1439 }
1440
1441 static void
1442 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1443 {
1444         struct ixgbe_hw *hw =
1445                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1446         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1447         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1448         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1449         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1450 }
1451
1452 static int
1453 ixgbe_dev_configure(struct rte_eth_dev *dev)
1454 {
1455         struct ixgbe_interrupt *intr =
1456                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1457         struct ixgbe_adapter *adapter =
1458                 (struct ixgbe_adapter *)dev->data->dev_private;
1459
1460         PMD_INIT_FUNC_TRACE();
1461
1462         /* set flag to update link status after init */
1463         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1464
1465         /*
1466          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1467          * allocation or vector Rx preconditions we will reset it.
1468          */
1469         adapter->rx_bulk_alloc_allowed = true;
1470         adapter->rx_vec_allowed = true;
1471
1472         return 0;
1473 }
1474
1475 /*
1476  * Configure device link speed and setup link.
1477  * It returns 0 on success.
1478  */
1479 static int
1480 ixgbe_dev_start(struct rte_eth_dev *dev)
1481 {
1482         struct ixgbe_hw *hw =
1483                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484         struct ixgbe_vf_info *vfinfo =
1485                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1486         int err, link_up = 0, negotiate = 0;
1487         uint32_t speed = 0;
1488         int mask = 0;
1489         int status;
1490         uint16_t vf, idx;
1491
1492         PMD_INIT_FUNC_TRACE();
1493
1494         /* IXGBE devices don't support half duplex */
1495         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1496                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1497                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1498                              dev->data->dev_conf.link_duplex,
1499                              dev->data->port_id);
1500                 return -EINVAL;
1501         }
1502
1503         /* stop adapter */
1504         hw->adapter_stopped = FALSE;
1505         ixgbe_stop_adapter(hw);
1506
1507         /* reinitialize adapter
1508          * this calls reset and start */
1509         status = ixgbe_pf_reset_hw(hw);
1510         if (status != 0)
1511                 return -1;
1512         hw->mac.ops.start_hw(hw);
1513         hw->mac.get_link_status = true;
1514
1515         /* configure PF module if SRIOV enabled */
1516         ixgbe_pf_host_configure(dev);
1517
1518         /* initialize transmission unit */
1519         ixgbe_dev_tx_init(dev);
1520
1521         /* This can fail when allocating mbufs for descriptor rings */
1522         err = ixgbe_dev_rx_init(dev);
1523         if (err) {
1524                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1525                 goto error;
1526         }
1527
1528         err = ixgbe_dev_rxtx_start(dev);
1529         if (err < 0) {
1530                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1531                 goto error;
1532         }
1533
1534         /* Skip link setup if loopback mode is enabled for 82599. */
1535         if (hw->mac.type == ixgbe_mac_82599EB &&
1536                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1537                 goto skip_link_setup;
1538
1539         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1540                 err = hw->mac.ops.setup_sfp(hw);
1541                 if (err)
1542                         goto error;
1543         }
1544
1545         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1546                 /* Turn on the copper */
1547                 ixgbe_set_phy_power(hw, true);
1548         } else {
1549                 /* Turn on the laser */
1550                 ixgbe_enable_tx_laser(hw);
1551         }
1552
1553         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1554         if (err)
1555                 goto error;
1556         dev->data->dev_link.link_status = link_up;
1557
1558         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1559         if (err)
1560                 goto error;
1561
1562         switch(dev->data->dev_conf.link_speed) {
1563         case ETH_LINK_SPEED_AUTONEG:
1564                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1565                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1566                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1567                 break;
1568         case ETH_LINK_SPEED_100:
1569                 /*
1570                  * Invalid for 82598 but error will be detected by
1571                  * ixgbe_setup_link()
1572                  */
1573                 speed = IXGBE_LINK_SPEED_100_FULL;
1574                 break;
1575         case ETH_LINK_SPEED_1000:
1576                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1577                 break;
1578         case ETH_LINK_SPEED_10000:
1579                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1580                 break;
1581         default:
1582                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1583                              dev->data->dev_conf.link_speed,
1584                              dev->data->port_id);
1585                 goto error;
1586         }
1587
1588         err = ixgbe_setup_link(hw, speed, link_up);
1589         if (err)
1590                 goto error;
1591
1592 skip_link_setup:
1593
1594         /* check if lsc interrupt is enabled */
1595         if (dev->data->dev_conf.intr_conf.lsc != 0)
1596                 ixgbe_dev_lsc_interrupt_setup(dev);
1597
1598         /* resume enabled intr since hw reset */
1599         ixgbe_enable_intr(dev);
1600
1601         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1602                 ETH_VLAN_EXTEND_MASK;
1603         ixgbe_vlan_offload_set(dev, mask);
1604
1605         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1606                 /* Enable vlan filtering for VMDq */
1607                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1608         }
1609
1610         /* Configure DCB hw */
1611         ixgbe_configure_dcb(dev);
1612
1613         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1614                 err = ixgbe_fdir_configure(dev);
1615                 if (err)
1616                         goto error;
1617         }
1618
1619         /* Restore vf rate limit */
1620         if (vfinfo != NULL) {
1621                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1622                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1623                                 if (vfinfo[vf].tx_rate[idx] != 0)
1624                                         ixgbe_set_vf_rate_limit(dev, vf,
1625                                                 vfinfo[vf].tx_rate[idx],
1626                                                 1 << idx);
1627         }
1628
1629         ixgbe_restore_statistics_mapping(dev);
1630
1631         return (0);
1632
1633 error:
1634         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1635         ixgbe_dev_clear_queues(dev);
1636         return -EIO;
1637 }
1638
1639 /*
1640  * Stop device: disable rx and tx functions to allow for reconfiguring.
1641  */
1642 static void
1643 ixgbe_dev_stop(struct rte_eth_dev *dev)
1644 {
1645         struct rte_eth_link link;
1646         struct ixgbe_hw *hw =
1647                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         struct ixgbe_vf_info *vfinfo =
1649                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1650         struct ixgbe_filter_info *filter_info =
1651                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1652         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1653         int vf;
1654
1655         PMD_INIT_FUNC_TRACE();
1656
1657         /* disable interrupts */
1658         ixgbe_disable_intr(hw);
1659
1660         /* reset the NIC */
1661         ixgbe_pf_reset_hw(hw);
1662         hw->adapter_stopped = FALSE;
1663
1664         /* stop adapter */
1665         ixgbe_stop_adapter(hw);
1666
1667         for (vf = 0; vfinfo != NULL &&
1668                      vf < dev->pci_dev->max_vfs; vf++)
1669                 vfinfo[vf].clear_to_send = false;
1670
1671         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1672                 /* Turn off the copper */
1673                 ixgbe_set_phy_power(hw, false);
1674         } else {
1675                 /* Turn off the laser */
1676                 ixgbe_disable_tx_laser(hw);
1677         }
1678
1679         ixgbe_dev_clear_queues(dev);
1680
1681         /* Clear stored conf */
1682         dev->data->scattered_rx = 0;
1683         dev->data->lro = 0;
1684
1685         /* Clear recorded link status */
1686         memset(&link, 0, sizeof(link));
1687         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1688
1689         /* Remove all ntuple filters of the device */
1690         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1691              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1692                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1693                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1694                              p_5tuple, entries);
1695                 rte_free(p_5tuple);
1696         }
1697         memset(filter_info->fivetuple_mask, 0,
1698                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1699
1700 }
1701
1702 /*
1703  * Set device link up: enable tx.
1704  */
1705 static int
1706 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1707 {
1708         struct ixgbe_hw *hw =
1709                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710         if (hw->mac.type == ixgbe_mac_82599EB) {
1711 #ifdef RTE_NIC_BYPASS
1712                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1713                         /* Not suported in bypass mode */
1714                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1715                                      "by device id 0x%x", hw->device_id);
1716                         return -ENOTSUP;
1717                 }
1718 #endif
1719         }
1720
1721         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1722                 /* Turn on the copper */
1723                 ixgbe_set_phy_power(hw, true);
1724         } else {
1725                 /* Turn on the laser */
1726                 ixgbe_enable_tx_laser(hw);
1727         }
1728
1729         return 0;
1730 }
1731
1732 /*
1733  * Set device link down: disable tx.
1734  */
1735 static int
1736 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1737 {
1738         struct ixgbe_hw *hw =
1739                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1740         if (hw->mac.type == ixgbe_mac_82599EB) {
1741 #ifdef RTE_NIC_BYPASS
1742                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1743                         /* Not suported in bypass mode */
1744                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1745                                      "by device id 0x%x", hw->device_id);
1746                         return -ENOTSUP;
1747                 }
1748 #endif
1749         }
1750
1751         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1752                 /* Turn off the copper */
1753                 ixgbe_set_phy_power(hw, false);
1754         } else {
1755                 /* Turn off the laser */
1756                 ixgbe_disable_tx_laser(hw);
1757         }
1758
1759         return 0;
1760 }
1761
1762 /*
1763  * Reest and stop device.
1764  */
1765 static void
1766 ixgbe_dev_close(struct rte_eth_dev *dev)
1767 {
1768         struct ixgbe_hw *hw =
1769                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770
1771         PMD_INIT_FUNC_TRACE();
1772
1773         ixgbe_pf_reset_hw(hw);
1774
1775         ixgbe_dev_stop(dev);
1776         hw->adapter_stopped = 1;
1777
1778         ixgbe_disable_pcie_master(hw);
1779
1780         /* reprogram the RAR[0] in case user changed it. */
1781         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1782 }
1783
1784 /*
1785  * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1786  */
1787 static void
1788 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1789 {
1790         struct ixgbe_hw *hw =
1791                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1792         struct ixgbe_hw_stats *hw_stats =
1793                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1794         uint32_t bprc, lxon, lxoff, total;
1795         uint64_t total_missed_rx, total_qbrc, total_qprc;
1796         unsigned i;
1797
1798         total_missed_rx = 0;
1799         total_qbrc = 0;
1800         total_qprc = 0;
1801
1802         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1803         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1804         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1805         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1806
1807         for (i = 0; i < 8; i++) {
1808                 uint32_t mp;
1809                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1810                 /* global total per queue */
1811                 hw_stats->mpc[i] += mp;
1812                 /* Running comprehensive total for stats display */
1813                 total_missed_rx += hw_stats->mpc[i];
1814                 if (hw->mac.type == ixgbe_mac_82598EB)
1815                         hw_stats->rnbc[i] +=
1816                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1817                 hw_stats->pxontxc[i] +=
1818                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1819                 hw_stats->pxonrxc[i] +=
1820                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1821                 hw_stats->pxofftxc[i] +=
1822                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1823                 hw_stats->pxoffrxc[i] +=
1824                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1825                 hw_stats->pxon2offc[i] +=
1826                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1827         }
1828         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1829                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1830                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1831                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1832                 hw_stats->qbrc[i] +=
1833                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1834                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1835                 hw_stats->qbtc[i] +=
1836                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1837                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1838
1839                 total_qprc += hw_stats->qprc[i];
1840                 total_qbrc += hw_stats->qbrc[i];
1841         }
1842         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1843         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1844         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1845
1846         /* Note that gprc counts missed packets */
1847         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1848
1849         if (hw->mac.type != ixgbe_mac_82598EB) {
1850                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1851                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1852                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1853                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1854                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1855                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1856                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1857                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1858         } else {
1859                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1860                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1861                 /* 82598 only has a counter in the high register */
1862                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1863                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1864                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1865         }
1866
1867         /*
1868          * Workaround: mprc hardware is incorrectly counting
1869          * broadcasts, so for now we subtract those.
1870          */
1871         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1872         hw_stats->bprc += bprc;
1873         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1874         if (hw->mac.type == ixgbe_mac_82598EB)
1875                 hw_stats->mprc -= bprc;
1876
1877         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1878         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1879         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1880         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1881         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1882         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1883
1884         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1885         hw_stats->lxontxc += lxon;
1886         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1887         hw_stats->lxofftxc += lxoff;
1888         total = lxon + lxoff;
1889
1890         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1891         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1892         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1893         hw_stats->gptc -= total;
1894         hw_stats->mptc -= total;
1895         hw_stats->ptc64 -= total;
1896         hw_stats->gotc -= total * ETHER_MIN_LEN;
1897
1898         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1899         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1900         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1901         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1902         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1903         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1904         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1905         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1906         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1907         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1908         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1909         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1910         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1911         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1912         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1913         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1914         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1915         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1916         /* Only read FCOE on 82599 */
1917         if (hw->mac.type != ixgbe_mac_82598EB) {
1918                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1919                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1920                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1921                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1922                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1923         }
1924
1925         if (stats == NULL)
1926                 return;
1927
1928         /* Fill out the rte_eth_stats statistics structure */
1929         stats->ipackets = total_qprc;
1930         stats->ibytes = total_qbrc;
1931         stats->opackets = hw_stats->gptc;
1932         stats->obytes = hw_stats->gotc;
1933         stats->imcasts = hw_stats->mprc;
1934
1935         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1936                 stats->q_ipackets[i] = hw_stats->qprc[i];
1937                 stats->q_opackets[i] = hw_stats->qptc[i];
1938                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1939                 stats->q_obytes[i] = hw_stats->qbtc[i];
1940                 stats->q_errors[i] = hw_stats->qprdc[i];
1941         }
1942
1943         /* Rx Errors */
1944         stats->ibadcrc  = hw_stats->crcerrs;
1945         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1946         stats->imissed  = total_missed_rx;
1947         stats->ierrors  = stats->ibadcrc +
1948                           stats->ibadlen +
1949                           stats->imissed +
1950                           hw_stats->illerrc + hw_stats->errbc;
1951
1952         /* Tx Errors */
1953         stats->oerrors  = 0;
1954
1955         /* XON/XOFF pause frames */
1956         stats->tx_pause_xon  = hw_stats->lxontxc;
1957         stats->rx_pause_xon  = hw_stats->lxonrxc;
1958         stats->tx_pause_xoff = hw_stats->lxofftxc;
1959         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1960
1961         /* Flow Director Stats registers */
1962         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1963         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1964         stats->fdirmatch = hw_stats->fdirmatch;
1965         stats->fdirmiss = hw_stats->fdirmiss;
1966 }
1967
1968 static void
1969 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1970 {
1971         struct ixgbe_hw_stats *stats =
1972                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1973
1974         /* HW registers are cleared on read */
1975         ixgbe_dev_stats_get(dev, NULL);
1976
1977         /* Reset software totals */
1978         memset(stats, 0, sizeof(*stats));
1979 }
1980
1981 static void
1982 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1983 {
1984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1985         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1986                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1987
1988         /* Good Rx packet, include VF loopback */
1989         UPDATE_VF_STAT(IXGBE_VFGPRC,
1990             hw_stats->last_vfgprc, hw_stats->vfgprc);
1991
1992         /* Good Rx octets, include VF loopback */
1993         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1994             hw_stats->last_vfgorc, hw_stats->vfgorc);
1995
1996         /* Good Tx packet, include VF loopback */
1997         UPDATE_VF_STAT(IXGBE_VFGPTC,
1998             hw_stats->last_vfgptc, hw_stats->vfgptc);
1999
2000         /* Good Tx octets, include VF loopback */
2001         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2002             hw_stats->last_vfgotc, hw_stats->vfgotc);
2003
2004         /* Rx Multicst Packet */
2005         UPDATE_VF_STAT(IXGBE_VFMPRC,
2006             hw_stats->last_vfmprc, hw_stats->vfmprc);
2007
2008         if (stats == NULL)
2009                 return;
2010
2011         stats->ipackets = hw_stats->vfgprc;
2012         stats->ibytes = hw_stats->vfgorc;
2013         stats->opackets = hw_stats->vfgptc;
2014         stats->obytes = hw_stats->vfgotc;
2015         stats->imcasts = hw_stats->vfmprc;
2016 }
2017
2018 static void
2019 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2020 {
2021         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2022                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2023
2024         /* Sync HW register to the last stats */
2025         ixgbevf_dev_stats_get(dev, NULL);
2026
2027         /* reset HW current stats*/
2028         hw_stats->vfgprc = 0;
2029         hw_stats->vfgorc = 0;
2030         hw_stats->vfgptc = 0;
2031         hw_stats->vfgotc = 0;
2032         hw_stats->vfmprc = 0;
2033
2034 }
2035
2036 static void
2037 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2038 {
2039         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2040
2041         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2042         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2043         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2044         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2045         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2046         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2047         dev_info->max_vfs = dev->pci_dev->max_vfs;
2048         if (hw->mac.type == ixgbe_mac_82598EB)
2049                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2050         else
2051                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2052         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2053         dev_info->rx_offload_capa =
2054                 DEV_RX_OFFLOAD_VLAN_STRIP |
2055                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2056                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2057                 DEV_RX_OFFLOAD_TCP_CKSUM;
2058
2059         /*
2060          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2061          * mode.
2062          */
2063         if ((hw->mac.type == ixgbe_mac_82599EB ||
2064              hw->mac.type == ixgbe_mac_X540) &&
2065             !RTE_ETH_DEV_SRIOV(dev).active)
2066                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2067
2068         dev_info->tx_offload_capa =
2069                 DEV_TX_OFFLOAD_VLAN_INSERT |
2070                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2071                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2072                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2073                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2074                 DEV_TX_OFFLOAD_TCP_TSO;
2075
2076         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2077                 .rx_thresh = {
2078                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2079                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2080                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2081                 },
2082                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2083                 .rx_drop_en = 0,
2084         };
2085
2086         dev_info->default_txconf = (struct rte_eth_txconf) {
2087                 .tx_thresh = {
2088                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2089                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2090                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2091                 },
2092                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2093                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2094                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2095                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2096         };
2097         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2098         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2099         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2100 }
2101
2102 static void
2103 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2104                      struct rte_eth_dev_info *dev_info)
2105 {
2106         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107
2108         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2109         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2110         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2111         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2112         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2113         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2114         dev_info->max_vfs = dev->pci_dev->max_vfs;
2115         if (hw->mac.type == ixgbe_mac_82598EB)
2116                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2117         else
2118                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2119         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2120                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2121                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2122                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2123         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2124                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2125                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2126                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2127                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2128
2129         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2130                 .rx_thresh = {
2131                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2132                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2133                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2134                 },
2135                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2136                 .rx_drop_en = 0,
2137         };
2138
2139         dev_info->default_txconf = (struct rte_eth_txconf) {
2140                 .tx_thresh = {
2141                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2142                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2143                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2144                 },
2145                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2146                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2147                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2148                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2149         };
2150 }
2151
2152 /* return 0 means link status changed, -1 means not changed */
2153 static int
2154 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2155 {
2156         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157         struct rte_eth_link link, old;
2158         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2159         int link_up;
2160         int diag;
2161
2162         link.link_status = 0;
2163         link.link_speed = 0;
2164         link.link_duplex = 0;
2165         memset(&old, 0, sizeof(old));
2166         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2167
2168         hw->mac.get_link_status = true;
2169
2170         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2171         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2172                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2173         else
2174                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2175
2176         if (diag != 0) {
2177                 link.link_speed = ETH_LINK_SPEED_100;
2178                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2179                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2180                 if (link.link_status == old.link_status)
2181                         return -1;
2182                 return 0;
2183         }
2184
2185         if (link_up == 0) {
2186                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2187                 if (link.link_status == old.link_status)
2188                         return -1;
2189                 return 0;
2190         }
2191         link.link_status = 1;
2192         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2193
2194         switch (link_speed) {
2195         default:
2196         case IXGBE_LINK_SPEED_UNKNOWN:
2197                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2198                 link.link_speed = ETH_LINK_SPEED_100;
2199                 break;
2200
2201         case IXGBE_LINK_SPEED_100_FULL:
2202                 link.link_speed = ETH_LINK_SPEED_100;
2203                 break;
2204
2205         case IXGBE_LINK_SPEED_1GB_FULL:
2206                 link.link_speed = ETH_LINK_SPEED_1000;
2207                 break;
2208
2209         case IXGBE_LINK_SPEED_10GB_FULL:
2210                 link.link_speed = ETH_LINK_SPEED_10000;
2211                 break;
2212         }
2213         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2214
2215         if (link.link_status == old.link_status)
2216                 return -1;
2217
2218         return 0;
2219 }
2220
2221 static void
2222 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2223 {
2224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225         uint32_t fctrl;
2226
2227         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2228         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2229         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2230 }
2231
2232 static void
2233 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2234 {
2235         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2236         uint32_t fctrl;
2237
2238         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2239         fctrl &= (~IXGBE_FCTRL_UPE);
2240         if (dev->data->all_multicast == 1)
2241                 fctrl |= IXGBE_FCTRL_MPE;
2242         else
2243                 fctrl &= (~IXGBE_FCTRL_MPE);
2244         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2245 }
2246
2247 static void
2248 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2249 {
2250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         uint32_t fctrl;
2252
2253         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2254         fctrl |= IXGBE_FCTRL_MPE;
2255         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2256 }
2257
2258 static void
2259 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2260 {
2261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         uint32_t fctrl;
2263
2264         if (dev->data->promiscuous == 1)
2265                 return; /* must remain in all_multicast mode */
2266
2267         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2268         fctrl &= (~IXGBE_FCTRL_MPE);
2269         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2270 }
2271
2272 /**
2273  * It clears the interrupt causes and enables the interrupt.
2274  * It will be called once only during nic initialized.
2275  *
2276  * @param dev
2277  *  Pointer to struct rte_eth_dev.
2278  *
2279  * @return
2280  *  - On success, zero.
2281  *  - On failure, a negative value.
2282  */
2283 static int
2284 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2285 {
2286         struct ixgbe_interrupt *intr =
2287                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2288
2289         ixgbe_dev_link_status_print(dev);
2290         intr->mask |= IXGBE_EICR_LSC;
2291
2292         return 0;
2293 }
2294
2295 /*
2296  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2297  *
2298  * @param dev
2299  *  Pointer to struct rte_eth_dev.
2300  *
2301  * @return
2302  *  - On success, zero.
2303  *  - On failure, a negative value.
2304  */
2305 static int
2306 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2307 {
2308         uint32_t eicr;
2309         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2310         struct ixgbe_interrupt *intr =
2311                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2312
2313         /* clear all cause mask */
2314         ixgbe_disable_intr(hw);
2315
2316         /* read-on-clear nic registers here */
2317         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2318         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2319
2320         intr->flags = 0;
2321         if (eicr & IXGBE_EICR_LSC) {
2322                 /* set flag for async link update */
2323                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2324         }
2325
2326         if (eicr & IXGBE_EICR_MAILBOX)
2327                 intr->flags |= IXGBE_FLAG_MAILBOX;
2328
2329         return 0;
2330 }
2331
2332 /**
2333  * It gets and then prints the link status.
2334  *
2335  * @param dev
2336  *  Pointer to struct rte_eth_dev.
2337  *
2338  * @return
2339  *  - On success, zero.
2340  *  - On failure, a negative value.
2341  */
2342 static void
2343 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2344 {
2345         struct rte_eth_link link;
2346
2347         memset(&link, 0, sizeof(link));
2348         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2349         if (link.link_status) {
2350                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2351                                         (int)(dev->data->port_id),
2352                                         (unsigned)link.link_speed,
2353                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2354                                         "full-duplex" : "half-duplex");
2355         } else {
2356                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2357                                 (int)(dev->data->port_id));
2358         }
2359         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2360                                 dev->pci_dev->addr.domain,
2361                                 dev->pci_dev->addr.bus,
2362                                 dev->pci_dev->addr.devid,
2363                                 dev->pci_dev->addr.function);
2364 }
2365
2366 /*
2367  * It executes link_update after knowing an interrupt occurred.
2368  *
2369  * @param dev
2370  *  Pointer to struct rte_eth_dev.
2371  *
2372  * @return
2373  *  - On success, zero.
2374  *  - On failure, a negative value.
2375  */
2376 static int
2377 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2378 {
2379         struct ixgbe_interrupt *intr =
2380                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2381         int64_t timeout;
2382         struct rte_eth_link link;
2383         int intr_enable_delay = false;
2384
2385         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2386
2387         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2388                 ixgbe_pf_mbx_process(dev);
2389                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2390         }
2391
2392         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2393                 /* get the link status before link update, for predicting later */
2394                 memset(&link, 0, sizeof(link));
2395                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2396
2397                 ixgbe_dev_link_update(dev, 0);
2398
2399                 /* likely to up */
2400                 if (!link.link_status)
2401                         /* handle it 1 sec later, wait it being stable */
2402                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2403                 /* likely to down */
2404                 else
2405                         /* handle it 4 sec later, wait it being stable */
2406                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2407
2408                 ixgbe_dev_link_status_print(dev);
2409
2410                 intr_enable_delay = true;
2411         }
2412
2413         if (intr_enable_delay) {
2414                 if (rte_eal_alarm_set(timeout * 1000,
2415                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2416                         PMD_DRV_LOG(ERR, "Error setting alarm");
2417         } else {
2418                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2419                 ixgbe_enable_intr(dev);
2420                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2421         }
2422
2423
2424         return 0;
2425 }
2426
2427 /**
2428  * Interrupt handler which shall be registered for alarm callback for delayed
2429  * handling specific interrupt to wait for the stable nic state. As the
2430  * NIC interrupt state is not stable for ixgbe after link is just down,
2431  * it needs to wait 4 seconds to get the stable status.
2432  *
2433  * @param handle
2434  *  Pointer to interrupt handle.
2435  * @param param
2436  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2437  *
2438  * @return
2439  *  void
2440  */
2441 static void
2442 ixgbe_dev_interrupt_delayed_handler(void *param)
2443 {
2444         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2445         struct ixgbe_interrupt *intr =
2446                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2447         struct ixgbe_hw *hw =
2448                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2449         uint32_t eicr;
2450
2451         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2452         if (eicr & IXGBE_EICR_MAILBOX)
2453                 ixgbe_pf_mbx_process(dev);
2454
2455         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2456                 ixgbe_dev_link_update(dev, 0);
2457                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2458                 ixgbe_dev_link_status_print(dev);
2459                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2460         }
2461
2462         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2463         ixgbe_enable_intr(dev);
2464         rte_intr_enable(&(dev->pci_dev->intr_handle));
2465 }
2466
2467 /**
2468  * Interrupt handler triggered by NIC  for handling
2469  * specific interrupt.
2470  *
2471  * @param handle
2472  *  Pointer to interrupt handle.
2473  * @param param
2474  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2475  *
2476  * @return
2477  *  void
2478  */
2479 static void
2480 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2481                                                         void *param)
2482 {
2483         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2484         ixgbe_dev_interrupt_get_status(dev);
2485         ixgbe_dev_interrupt_action(dev);
2486 }
2487
2488 static int
2489 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2490 {
2491         struct ixgbe_hw *hw;
2492
2493         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2494         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2495 }
2496
2497 static int
2498 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2499 {
2500         struct ixgbe_hw *hw;
2501
2502         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2503         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2504 }
2505
2506 static int
2507 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2508 {
2509         struct ixgbe_hw *hw;
2510         uint32_t mflcn_reg;
2511         uint32_t fccfg_reg;
2512         int rx_pause;
2513         int tx_pause;
2514
2515         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516
2517         fc_conf->pause_time = hw->fc.pause_time;
2518         fc_conf->high_water = hw->fc.high_water[0];
2519         fc_conf->low_water = hw->fc.low_water[0];
2520         fc_conf->send_xon = hw->fc.send_xon;
2521         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2522
2523         /*
2524          * Return rx_pause status according to actual setting of
2525          * MFLCN register.
2526          */
2527         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2528         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2529                 rx_pause = 1;
2530         else
2531                 rx_pause = 0;
2532
2533         /*
2534          * Return tx_pause status according to actual setting of
2535          * FCCFG register.
2536          */
2537         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2538         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2539                 tx_pause = 1;
2540         else
2541                 tx_pause = 0;
2542
2543         if (rx_pause && tx_pause)
2544                 fc_conf->mode = RTE_FC_FULL;
2545         else if (rx_pause)
2546                 fc_conf->mode = RTE_FC_RX_PAUSE;
2547         else if (tx_pause)
2548                 fc_conf->mode = RTE_FC_TX_PAUSE;
2549         else
2550                 fc_conf->mode = RTE_FC_NONE;
2551
2552         return 0;
2553 }
2554
2555 static int
2556 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2557 {
2558         struct ixgbe_hw *hw;
2559         int err;
2560         uint32_t rx_buf_size;
2561         uint32_t max_high_water;
2562         uint32_t mflcn;
2563         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2564                 ixgbe_fc_none,
2565                 ixgbe_fc_rx_pause,
2566                 ixgbe_fc_tx_pause,
2567                 ixgbe_fc_full
2568         };
2569
2570         PMD_INIT_FUNC_TRACE();
2571
2572         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2574                 return -ENOTSUP;
2575         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2576         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2577
2578         /*
2579          * At least reserve one Ethernet frame for watermark
2580          * high_water/low_water in kilo bytes for ixgbe
2581          */
2582         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2583         if ((fc_conf->high_water > max_high_water) ||
2584                 (fc_conf->high_water < fc_conf->low_water)) {
2585                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2586                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2587                 return (-EINVAL);
2588         }
2589
2590         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2591         hw->fc.pause_time     = fc_conf->pause_time;
2592         hw->fc.high_water[0]  = fc_conf->high_water;
2593         hw->fc.low_water[0]   = fc_conf->low_water;
2594         hw->fc.send_xon       = fc_conf->send_xon;
2595
2596         err = ixgbe_fc_enable(hw);
2597
2598         /* Not negotiated is not an error case */
2599         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2600
2601                 /* check if we want to forward MAC frames - driver doesn't have native
2602                  * capability to do that, so we'll write the registers ourselves */
2603
2604                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2605
2606                 /* set or clear MFLCN.PMCF bit depending on configuration */
2607                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2608                         mflcn |= IXGBE_MFLCN_PMCF;
2609                 else
2610                         mflcn &= ~IXGBE_MFLCN_PMCF;
2611
2612                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2613                 IXGBE_WRITE_FLUSH(hw);
2614
2615                 return 0;
2616         }
2617
2618         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2619         return -EIO;
2620 }
2621
2622 /**
2623  *  ixgbe_pfc_enable_generic - Enable flow control
2624  *  @hw: pointer to hardware structure
2625  *  @tc_num: traffic class number
2626  *  Enable flow control according to the current settings.
2627  */
2628 static int
2629 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2630 {
2631         int ret_val = 0;
2632         uint32_t mflcn_reg, fccfg_reg;
2633         uint32_t reg;
2634         uint32_t fcrtl, fcrth;
2635         uint8_t i;
2636         uint8_t nb_rx_en;
2637
2638         /* Validate the water mark configuration */
2639         if (!hw->fc.pause_time) {
2640                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2641                 goto out;
2642         }
2643
2644         /* Low water mark of zero causes XOFF floods */
2645         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2646                  /* High/Low water can not be 0 */
2647                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2648                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2649                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2650                         goto out;
2651                 }
2652
2653                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2654                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2655                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2656                         goto out;
2657                 }
2658         }
2659         /* Negotiate the fc mode to use */
2660         ixgbe_fc_autoneg(hw);
2661
2662         /* Disable any previous flow control settings */
2663         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2664         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2665
2666         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2667         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2668
2669         switch (hw->fc.current_mode) {
2670         case ixgbe_fc_none:
2671                 /*
2672                  * If the count of enabled RX Priority Flow control >1,
2673                  * and the TX pause can not be disabled
2674                  */
2675                 nb_rx_en = 0;
2676                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2677                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2678                         if (reg & IXGBE_FCRTH_FCEN)
2679                                 nb_rx_en++;
2680                 }
2681                 if (nb_rx_en > 1)
2682                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2683                 break;
2684         case ixgbe_fc_rx_pause:
2685                 /*
2686                  * Rx Flow control is enabled and Tx Flow control is
2687                  * disabled by software override. Since there really
2688                  * isn't a way to advertise that we are capable of RX
2689                  * Pause ONLY, we will advertise that we support both
2690                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2691                  * disable the adapter's ability to send PAUSE frames.
2692                  */
2693                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2694                 /*
2695                  * If the count of enabled RX Priority Flow control >1,
2696                  * and the TX pause can not be disabled
2697                  */
2698                 nb_rx_en = 0;
2699                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2700                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2701                         if (reg & IXGBE_FCRTH_FCEN)
2702                                 nb_rx_en++;
2703                 }
2704                 if (nb_rx_en > 1)
2705                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2706                 break;
2707         case ixgbe_fc_tx_pause:
2708                 /*
2709                  * Tx Flow control is enabled, and Rx Flow control is
2710                  * disabled by software override.
2711                  */
2712                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2713                 break;
2714         case ixgbe_fc_full:
2715                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2716                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2717                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2718                 break;
2719         default:
2720                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2721                 ret_val = IXGBE_ERR_CONFIG;
2722                 goto out;
2723                 break;
2724         }
2725
2726         /* Set 802.3x based flow control settings. */
2727         mflcn_reg |= IXGBE_MFLCN_DPF;
2728         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2729         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2730
2731         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2732         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2733                 hw->fc.high_water[tc_num]) {
2734                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2735                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2736                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2737         } else {
2738                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2739                 /*
2740                  * In order to prevent Tx hangs when the internal Tx
2741                  * switch is enabled we must set the high water mark
2742                  * to the maximum FCRTH value.  This allows the Tx
2743                  * switch to function even under heavy Rx workloads.
2744                  */
2745                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2746         }
2747         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2748
2749         /* Configure pause time (2 TCs per register) */
2750         reg = hw->fc.pause_time * 0x00010001;
2751         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2752                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2753
2754         /* Configure flow control refresh threshold value */
2755         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2756
2757 out:
2758         return ret_val;
2759 }
2760
2761 static int
2762 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2763 {
2764         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2766
2767         if(hw->mac.type != ixgbe_mac_82598EB) {
2768                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2769         }
2770         return ret_val;
2771 }
2772
2773 static int
2774 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2775 {
2776         int err;
2777         uint32_t rx_buf_size;
2778         uint32_t max_high_water;
2779         uint8_t tc_num;
2780         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2781         struct ixgbe_hw *hw =
2782                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2783         struct ixgbe_dcb_config *dcb_config =
2784                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2785
2786         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2787                 ixgbe_fc_none,
2788                 ixgbe_fc_rx_pause,
2789                 ixgbe_fc_tx_pause,
2790                 ixgbe_fc_full
2791         };
2792
2793         PMD_INIT_FUNC_TRACE();
2794
2795         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2796         tc_num = map[pfc_conf->priority];
2797         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2798         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2799         /*
2800          * At least reserve one Ethernet frame for watermark
2801          * high_water/low_water in kilo bytes for ixgbe
2802          */
2803         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2804         if ((pfc_conf->fc.high_water > max_high_water) ||
2805             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2806                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2807                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2808                 return (-EINVAL);
2809         }
2810
2811         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2812         hw->fc.pause_time = pfc_conf->fc.pause_time;
2813         hw->fc.send_xon = pfc_conf->fc.send_xon;
2814         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2815         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2816
2817         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2818
2819         /* Not negotiated is not an error case */
2820         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2821                 return 0;
2822
2823         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2824         return -EIO;
2825 }
2826
2827 static int
2828 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2829                           struct rte_eth_rss_reta_entry64 *reta_conf,
2830                           uint16_t reta_size)
2831 {
2832         uint8_t i, j, mask;
2833         uint32_t reta, r;
2834         uint16_t idx, shift;
2835         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2836
2837         PMD_INIT_FUNC_TRACE();
2838         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2839                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2840                         "(%d) doesn't match the number hardware can supported "
2841                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2842                 return -EINVAL;
2843         }
2844
2845         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2846                 idx = i / RTE_RETA_GROUP_SIZE;
2847                 shift = i % RTE_RETA_GROUP_SIZE;
2848                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2849                                                 IXGBE_4_BIT_MASK);
2850                 if (!mask)
2851                         continue;
2852                 if (mask == IXGBE_4_BIT_MASK)
2853                         r = 0;
2854                 else
2855                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2856                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2857                         if (mask & (0x1 << j))
2858                                 reta |= reta_conf[idx].reta[shift + j] <<
2859                                                         (CHAR_BIT * j);
2860                         else
2861                                 reta |= r & (IXGBE_8_BIT_MASK <<
2862                                                 (CHAR_BIT * j));
2863                 }
2864                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2865         }
2866
2867         return 0;
2868 }
2869
2870 static int
2871 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2872                          struct rte_eth_rss_reta_entry64 *reta_conf,
2873                          uint16_t reta_size)
2874 {
2875         uint8_t i, j, mask;
2876         uint32_t reta;
2877         uint16_t idx, shift;
2878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879
2880         PMD_INIT_FUNC_TRACE();
2881         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2882                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2883                         "(%d) doesn't match the number hardware can supported "
2884                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2885                 return -EINVAL;
2886         }
2887
2888         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2889                 idx = i / RTE_RETA_GROUP_SIZE;
2890                 shift = i % RTE_RETA_GROUP_SIZE;
2891                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2892                                                 IXGBE_4_BIT_MASK);
2893                 if (!mask)
2894                         continue;
2895
2896                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2897                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2898                         if (mask & (0x1 << j))
2899                                 reta_conf[idx].reta[shift + j] =
2900                                         ((reta >> (CHAR_BIT * j)) &
2901                                                 IXGBE_8_BIT_MASK);
2902                 }
2903         }
2904
2905         return 0;
2906 }
2907
2908 static void
2909 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2910                                 uint32_t index, uint32_t pool)
2911 {
2912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913         uint32_t enable_addr = 1;
2914
2915         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2916 }
2917
2918 static void
2919 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2920 {
2921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922
2923         ixgbe_clear_rar(hw, index);
2924 }
2925
2926 static int
2927 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2928 {
2929         uint32_t hlreg0;
2930         uint32_t maxfrs;
2931         struct ixgbe_hw *hw;
2932         struct rte_eth_dev_info dev_info;
2933         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2934
2935         ixgbe_dev_info_get(dev, &dev_info);
2936
2937         /* check that mtu is within the allowed range */
2938         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2939                 return -EINVAL;
2940
2941         /* refuse mtu that requires the support of scattered packets when this
2942          * feature has not been enabled before. */
2943         if (!dev->data->scattered_rx &&
2944             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2945              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2946                 return -EINVAL;
2947
2948         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2950
2951         /* switch to jumbo mode if needed */
2952         if (frame_size > ETHER_MAX_LEN) {
2953                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2954                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2955         } else {
2956                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2957                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2958         }
2959         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2960
2961         /* update max frame size */
2962         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2963
2964         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2965         maxfrs &= 0x0000FFFF;
2966         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2967         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2968
2969         return 0;
2970 }
2971
2972 /*
2973  * Virtual Function operations
2974  */
2975 static void
2976 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2977 {
2978         PMD_INIT_FUNC_TRACE();
2979
2980         /* Clear interrupt mask to stop from interrupts being generated */
2981         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2982
2983         IXGBE_WRITE_FLUSH(hw);
2984 }
2985
2986 static int
2987 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2988 {
2989         struct rte_eth_conf* conf = &dev->data->dev_conf;
2990         struct ixgbe_adapter *adapter =
2991                         (struct ixgbe_adapter *)dev->data->dev_private;
2992
2993         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2994                      dev->data->port_id);
2995
2996         /*
2997          * VF has no ability to enable/disable HW CRC
2998          * Keep the persistent behavior the same as Host PF
2999          */
3000 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3001         if (!conf->rxmode.hw_strip_crc) {
3002                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
3003                 conf->rxmode.hw_strip_crc = 1;
3004         }
3005 #else
3006         if (conf->rxmode.hw_strip_crc) {
3007                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
3008                 conf->rxmode.hw_strip_crc = 0;
3009         }
3010 #endif
3011
3012         /*
3013          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3014          * allocation or vector Rx preconditions we will reset it.
3015          */
3016         adapter->rx_bulk_alloc_allowed = true;
3017         adapter->rx_vec_allowed = true;
3018
3019         return 0;
3020 }
3021
3022 static int
3023 ixgbevf_dev_start(struct rte_eth_dev *dev)
3024 {
3025         struct ixgbe_hw *hw =
3026                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027         int err, mask = 0;
3028
3029         PMD_INIT_FUNC_TRACE();
3030
3031         hw->mac.ops.reset_hw(hw);
3032         hw->mac.get_link_status = true;
3033
3034         /* negotiate mailbox API version to use with the PF. */
3035         ixgbevf_negotiate_api(hw);
3036
3037         ixgbevf_dev_tx_init(dev);
3038
3039         /* This can fail when allocating mbufs for descriptor rings */
3040         err = ixgbevf_dev_rx_init(dev);
3041         if (err) {
3042                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3043                 ixgbe_dev_clear_queues(dev);
3044                 return err;
3045         }
3046
3047         /* Set vfta */
3048         ixgbevf_set_vfta_all(dev,1);
3049
3050         /* Set HW strip */
3051         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3052                 ETH_VLAN_EXTEND_MASK;
3053         ixgbevf_vlan_offload_set(dev, mask);
3054
3055         ixgbevf_dev_rxtx_start(dev);
3056
3057         return 0;
3058 }
3059
3060 static void
3061 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3062 {
3063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3064
3065         PMD_INIT_FUNC_TRACE();
3066
3067         hw->adapter_stopped = TRUE;
3068         ixgbe_stop_adapter(hw);
3069
3070         /*
3071           * Clear what we set, but we still keep shadow_vfta to
3072           * restore after device starts
3073           */
3074         ixgbevf_set_vfta_all(dev,0);
3075
3076         /* Clear stored conf */
3077         dev->data->scattered_rx = 0;
3078
3079         ixgbe_dev_clear_queues(dev);
3080 }
3081
3082 static void
3083 ixgbevf_dev_close(struct rte_eth_dev *dev)
3084 {
3085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086
3087         PMD_INIT_FUNC_TRACE();
3088
3089         ixgbe_reset_hw(hw);
3090
3091         ixgbevf_dev_stop(dev);
3092
3093         /* reprogram the RAR[0] in case user changed it. */
3094         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3095 }
3096
3097 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3098 {
3099         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3100         struct ixgbe_vfta * shadow_vfta =
3101                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3102         int i = 0, j = 0, vfta = 0, mask = 1;
3103
3104         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3105                 vfta = shadow_vfta->vfta[i];
3106                 if(vfta){
3107                         mask = 1;
3108                         for (j = 0; j < 32; j++){
3109                                 if(vfta & mask)
3110                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3111                                 mask<<=1;
3112                         }
3113                 }
3114         }
3115
3116 }
3117
3118 static int
3119 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3120 {
3121         struct ixgbe_hw *hw =
3122                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3123         struct ixgbe_vfta * shadow_vfta =
3124                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3125         uint32_t vid_idx = 0;
3126         uint32_t vid_bit = 0;
3127         int ret = 0;
3128
3129         PMD_INIT_FUNC_TRACE();
3130
3131         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3132         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3133         if(ret){
3134                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3135                 return ret;
3136         }
3137         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3138         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3139
3140         /* Save what we set and retore it after device reset */
3141         if (on)
3142                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3143         else
3144                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3145
3146         return 0;
3147 }
3148
3149 static void
3150 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3151 {
3152         struct ixgbe_hw *hw =
3153                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3154         uint32_t ctrl;
3155
3156         PMD_INIT_FUNC_TRACE();
3157
3158         if(queue >= hw->mac.max_rx_queues)
3159                 return;
3160
3161         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3162         if(on)
3163                 ctrl |= IXGBE_RXDCTL_VME;
3164         else
3165                 ctrl &= ~IXGBE_RXDCTL_VME;
3166         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3167
3168         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3169 }
3170
3171 static void
3172 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3173 {
3174         struct ixgbe_hw *hw =
3175                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176         uint16_t i;
3177         int on = 0;
3178
3179         /* VF function only support hw strip feature, others are not support */
3180         if(mask & ETH_VLAN_STRIP_MASK){
3181                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3182
3183                 for(i=0; i < hw->mac.max_rx_queues; i++)
3184                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3185         }
3186 }
3187
3188 static int
3189 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3190 {
3191         uint32_t reg_val;
3192
3193         /* we only need to do this if VMDq is enabled */
3194         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3195         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3196                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3197                 return (-1);
3198         }
3199
3200         return 0;
3201 }
3202
3203 static uint32_t
3204 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3205 {
3206         uint32_t vector = 0;
3207         switch (hw->mac.mc_filter_type) {
3208         case 0:   /* use bits [47:36] of the address */
3209                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3210                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3211                 break;
3212         case 1:   /* use bits [46:35] of the address */
3213                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3214                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3215                 break;
3216         case 2:   /* use bits [45:34] of the address */
3217                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3218                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3219                 break;
3220         case 3:   /* use bits [43:32] of the address */
3221                 vector = ((uc_addr->addr_bytes[4]) |
3222                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3223                 break;
3224         default:  /* Invalid mc_filter_type */
3225                 break;
3226         }
3227
3228         /* vector can only be 12-bits or boundary will be exceeded */
3229         vector &= 0xFFF;
3230         return vector;
3231 }
3232
3233 static int
3234 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3235                                uint8_t on)
3236 {
3237         uint32_t vector;
3238         uint32_t uta_idx;
3239         uint32_t reg_val;
3240         uint32_t uta_shift;
3241         uint32_t rc;
3242         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3243         const uint32_t ixgbe_uta_bit_shift = 5;
3244         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3245         const uint32_t bit1 = 0x1;
3246
3247         struct ixgbe_hw *hw =
3248                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3249         struct ixgbe_uta_info *uta_info =
3250                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3251
3252         /* The UTA table only exists on 82599 hardware and newer */
3253         if (hw->mac.type < ixgbe_mac_82599EB)
3254                 return (-ENOTSUP);
3255
3256         vector = ixgbe_uta_vector(hw,mac_addr);
3257         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3258         uta_shift = vector & ixgbe_uta_bit_mask;
3259
3260         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3261         if(rc == on)
3262                 return 0;
3263
3264         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3265         if (on) {
3266                 uta_info->uta_in_use++;
3267                 reg_val |= (bit1 << uta_shift);
3268                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3269         } else {
3270                 uta_info->uta_in_use--;
3271                 reg_val &= ~(bit1 << uta_shift);
3272                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3273         }
3274
3275         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3276
3277         if (uta_info->uta_in_use > 0)
3278                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3279                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3280         else
3281                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3282
3283         return 0;
3284 }
3285
3286 static int
3287 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3288 {
3289         int i;
3290         struct ixgbe_hw *hw =
3291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3292         struct ixgbe_uta_info *uta_info =
3293                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3294
3295         /* The UTA table only exists on 82599 hardware and newer */
3296         if (hw->mac.type < ixgbe_mac_82599EB)
3297                 return (-ENOTSUP);
3298
3299         if(on) {
3300                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3301                         uta_info->uta_shadow[i] = ~0;
3302                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3303                 }
3304         } else {
3305                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3306                         uta_info->uta_shadow[i] = 0;
3307                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3308                 }
3309         }
3310         return 0;
3311
3312 }
3313
3314 uint32_t
3315 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3316 {
3317         uint32_t new_val = orig_val;
3318
3319         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3320                 new_val |= IXGBE_VMOLR_AUPE;
3321         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3322                 new_val |= IXGBE_VMOLR_ROMPE;
3323         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3324                 new_val |= IXGBE_VMOLR_ROPE;
3325         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3326                 new_val |= IXGBE_VMOLR_BAM;
3327         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3328                 new_val |= IXGBE_VMOLR_MPE;
3329
3330         return new_val;
3331 }
3332
3333 static int
3334 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3335                                uint16_t rx_mask, uint8_t on)
3336 {
3337         int val = 0;
3338
3339         struct ixgbe_hw *hw =
3340                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3341         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3342
3343         if (hw->mac.type == ixgbe_mac_82598EB) {
3344                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3345                              " on 82599 hardware and newer");
3346                 return (-ENOTSUP);
3347         }
3348         if (ixgbe_vmdq_mode_check(hw) < 0)
3349                 return (-ENOTSUP);
3350
3351         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3352
3353         if (on)
3354                 vmolr |= val;
3355         else
3356                 vmolr &= ~val;
3357
3358         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3359
3360         return 0;
3361 }
3362
3363 static int
3364 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3365 {
3366         uint32_t reg,addr;
3367         uint32_t val;
3368         const uint8_t bit1 = 0x1;
3369
3370         struct ixgbe_hw *hw =
3371                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3372
3373         if (ixgbe_vmdq_mode_check(hw) < 0)
3374                 return (-ENOTSUP);
3375
3376         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3377         reg = IXGBE_READ_REG(hw, addr);
3378         val = bit1 << pool;
3379
3380         if (on)
3381                 reg |= val;
3382         else
3383                 reg &= ~val;
3384
3385         IXGBE_WRITE_REG(hw, addr,reg);
3386
3387         return 0;
3388 }
3389
3390 static int
3391 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3392 {
3393         uint32_t reg,addr;
3394         uint32_t val;
3395         const uint8_t bit1 = 0x1;
3396
3397         struct ixgbe_hw *hw =
3398                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3399
3400         if (ixgbe_vmdq_mode_check(hw) < 0)
3401                 return (-ENOTSUP);
3402
3403         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3404         reg = IXGBE_READ_REG(hw, addr);
3405         val = bit1 << pool;
3406
3407         if (on)
3408                 reg |= val;
3409         else
3410                 reg &= ~val;
3411
3412         IXGBE_WRITE_REG(hw, addr,reg);
3413
3414         return 0;
3415 }
3416
3417 static int
3418 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3419                         uint64_t pool_mask, uint8_t vlan_on)
3420 {
3421         int ret = 0;
3422         uint16_t pool_idx;
3423         struct ixgbe_hw *hw =
3424                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3425
3426         if (ixgbe_vmdq_mode_check(hw) < 0)
3427                 return (-ENOTSUP);
3428         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3429                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3430                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3431                         if (ret < 0)
3432                                 return ret;
3433         }
3434
3435         return ret;
3436 }
3437
3438 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
3439 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
3440 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
3441 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
3442 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3443         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3444         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3445
3446 static int
3447 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3448                         struct rte_eth_mirror_conf *mirror_conf,
3449                         uint8_t rule_id, uint8_t on)
3450 {
3451         uint32_t mr_ctl,vlvf;
3452         uint32_t mp_lsb = 0;
3453         uint32_t mv_msb = 0;
3454         uint32_t mv_lsb = 0;
3455         uint32_t mp_msb = 0;
3456         uint8_t i = 0;
3457         int reg_index = 0;
3458         uint64_t vlan_mask = 0;
3459
3460         const uint8_t pool_mask_offset = 32;
3461         const uint8_t vlan_mask_offset = 32;
3462         const uint8_t dst_pool_offset = 8;
3463         const uint8_t rule_mr_offset  = 4;
3464         const uint8_t mirror_rule_mask= 0x0F;
3465
3466         struct ixgbe_mirror_info *mr_info =
3467                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3468         struct ixgbe_hw *hw =
3469                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3470         uint8_t mirror_type = 0;
3471
3472         if (ixgbe_vmdq_mode_check(hw) < 0)
3473                 return -ENOTSUP;
3474
3475         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3476                 return -EINVAL;
3477
3478         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3479                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3480                         mirror_conf->rule_type);
3481                 return -EINVAL;
3482         }
3483
3484         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3485                 mirror_type |= IXGBE_MRCTL_VLME;
3486                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3487                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3488                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3489                                 /* search vlan id related pool vlan filter index */
3490                                 reg_index = ixgbe_find_vlvf_slot(hw,
3491                                                 mirror_conf->vlan.vlan_id[i]);
3492                                 if(reg_index < 0)
3493                                         return -EINVAL;
3494                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3495                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3496                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3497                                       mirror_conf->vlan.vlan_id[i]))
3498                                         vlan_mask |= (1ULL << reg_index);
3499                                 else
3500                                         return -EINVAL;
3501                         }
3502                 }
3503
3504                 if (on) {
3505                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3506                         mv_msb = vlan_mask >> vlan_mask_offset;
3507
3508                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3509                                                 mirror_conf->vlan.vlan_mask;
3510                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3511                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3512                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3513                                                 mirror_conf->vlan.vlan_id[i];
3514                         }
3515                 } else {
3516                         mv_lsb = 0;
3517                         mv_msb = 0;
3518                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3519                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3520                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3521                 }
3522         }
3523
3524         /*
3525          * if enable pool mirror, write related pool mask register,if disable
3526          * pool mirror, clear PFMRVM register
3527          */
3528         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
3529                 mirror_type |= IXGBE_MRCTL_VPME;
3530                 if (on) {
3531                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3532                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3533                         mr_info->mr_conf[rule_id].pool_mask =
3534                                         mirror_conf->pool_mask;
3535
3536                 } else {
3537                         mp_lsb = 0;
3538                         mp_msb = 0;
3539                         mr_info->mr_conf[rule_id].pool_mask = 0;
3540                 }
3541         }
3542         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
3543                 mirror_type |= IXGBE_MRCTL_UPME;
3544         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
3545                 mirror_type |= IXGBE_MRCTL_DPME;
3546
3547         /* read  mirror control register and recalculate it */
3548         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
3549
3550         if (on) {
3551                 mr_ctl |= mirror_type;
3552                 mr_ctl &= mirror_rule_mask;
3553                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3554         } else
3555                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
3556
3557         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
3558         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3559
3560         /* write mirrror control  register */
3561         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3562
3563         /* write pool mirrror control  register */
3564         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
3565                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3566                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3567                                 mp_msb);
3568         }
3569         /* write VLAN mirrror control  register */
3570         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
3571                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3572                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3573                                 mv_msb);
3574         }
3575
3576         return 0;
3577 }
3578
3579 static int
3580 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3581 {
3582         int mr_ctl = 0;
3583         uint32_t lsb_val = 0;
3584         uint32_t msb_val = 0;
3585         const uint8_t rule_mr_offset = 4;
3586
3587         struct ixgbe_hw *hw =
3588                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589         struct ixgbe_mirror_info *mr_info =
3590                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3591
3592         if (ixgbe_vmdq_mode_check(hw) < 0)
3593                 return (-ENOTSUP);
3594
3595         memset(&mr_info->mr_conf[rule_id], 0,
3596                 sizeof(struct rte_eth_mirror_conf));
3597
3598         /* clear PFVMCTL register */
3599         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3600
3601         /* clear pool mask register */
3602         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3603         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3604
3605         /* clear vlan mask register */
3606         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3607         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3608
3609         return 0;
3610 }
3611
3612 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3613         uint16_t queue_idx, uint16_t tx_rate)
3614 {
3615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3616         uint32_t rf_dec, rf_int;
3617         uint32_t bcnrc_val;
3618         uint16_t link_speed = dev->data->dev_link.link_speed;
3619
3620         if (queue_idx >= hw->mac.max_tx_queues)
3621                 return -EINVAL;
3622
3623         if (tx_rate != 0) {
3624                 /* Calculate the rate factor values to set */
3625                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3626                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3627                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3628
3629                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3630                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3631                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3632                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3633         } else {
3634                 bcnrc_val = 0;
3635         }
3636
3637         /*
3638          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3639          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3640          * set as 0x4.
3641          */
3642         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3643                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3644                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3645                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3646                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3647         else
3648                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3649                         IXGBE_MMW_SIZE_DEFAULT);
3650
3651         /* Set RTTBCNRC of queue X */
3652         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3653         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3654         IXGBE_WRITE_FLUSH(hw);
3655
3656         return 0;
3657 }
3658
3659 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3660         uint16_t tx_rate, uint64_t q_msk)
3661 {
3662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3663         struct ixgbe_vf_info *vfinfo =
3664                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3665         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3666         uint32_t queue_stride =
3667                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3668         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3669         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3670         uint16_t total_rate = 0;
3671
3672         if (queue_end >= hw->mac.max_tx_queues)
3673                 return -EINVAL;
3674
3675         if (vfinfo != NULL) {
3676                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3677                         if (vf_idx == vf)
3678                                 continue;
3679                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3680                                 idx++)
3681                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3682                 }
3683         } else
3684                 return -EINVAL;
3685
3686         /* Store tx_rate for this vf. */
3687         for (idx = 0; idx < nb_q_per_pool; idx++) {
3688                 if (((uint64_t)0x1 << idx) & q_msk) {
3689                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3690                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3691                         total_rate += tx_rate;
3692                 }
3693         }
3694
3695         if (total_rate > dev->data->dev_link.link_speed) {
3696                 /*
3697                  * Reset stored TX rate of the VF if it causes exceed
3698                  * link speed.
3699                  */
3700                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3701                 return -EINVAL;
3702         }
3703
3704         /* Set RTTBCNRC of each queue/pool for vf X  */
3705         for (; queue_idx <= queue_end; queue_idx++) {
3706                 if (0x1 & q_msk)
3707                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3708                 q_msk = q_msk >> 1;
3709         }
3710
3711         return 0;
3712 }
3713
3714 static void
3715 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3716                      __attribute__((unused)) uint32_t index,
3717                      __attribute__((unused)) uint32_t pool)
3718 {
3719         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3720         int diag;
3721
3722         /*
3723          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3724          * operation. Trap this case to avoid exhausting the [very limited]
3725          * set of PF resources used to store VF MAC addresses.
3726          */
3727         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3728                 return;
3729         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3730         if (diag == 0)
3731                 return;
3732         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3733 }
3734
3735 static void
3736 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3737 {
3738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3739         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3740         struct ether_addr *mac_addr;
3741         uint32_t i;
3742         int diag;
3743
3744         /*
3745          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3746          * not support the deletion of a given MAC address.
3747          * Instead, it imposes to delete all MAC addresses, then to add again
3748          * all MAC addresses with the exception of the one to be deleted.
3749          */
3750         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3751
3752         /*
3753          * Add again all MAC addresses, with the exception of the deleted one
3754          * and of the permanent MAC address.
3755          */
3756         for (i = 0, mac_addr = dev->data->mac_addrs;
3757              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3758                 /* Skip the deleted MAC address */
3759                 if (i == index)
3760                         continue;
3761                 /* Skip NULL MAC addresses */
3762                 if (is_zero_ether_addr(mac_addr))
3763                         continue;
3764                 /* Skip the permanent MAC address */
3765                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3766                         continue;
3767                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3768                 if (diag != 0)
3769                         PMD_DRV_LOG(ERR,
3770                                     "Adding again MAC address "
3771                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3772                                     "diag=%d",
3773                                     mac_addr->addr_bytes[0],
3774                                     mac_addr->addr_bytes[1],
3775                                     mac_addr->addr_bytes[2],
3776                                     mac_addr->addr_bytes[3],
3777                                     mac_addr->addr_bytes[4],
3778                                     mac_addr->addr_bytes[5],
3779                                     diag);
3780         }
3781 }
3782
3783 #define MAC_TYPE_FILTER_SUP(type)    do {\
3784         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3785                 (type) != ixgbe_mac_X550)\
3786                 return -ENOTSUP;\
3787 } while (0)
3788
3789 static int
3790 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3791                         struct rte_eth_syn_filter *filter,
3792                         bool add)
3793 {
3794         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795         uint32_t synqf;
3796
3797         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3798                 return -EINVAL;
3799
3800         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3801
3802         if (add) {
3803                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3804                         return -EINVAL;
3805                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3806                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3807
3808                 if (filter->hig_pri)
3809                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3810                 else
3811                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3812         } else {
3813                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3814                         return -ENOENT;
3815                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3816         }
3817         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3818         IXGBE_WRITE_FLUSH(hw);
3819         return 0;
3820 }
3821
3822 static int
3823 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3824                         struct rte_eth_syn_filter *filter)
3825 {
3826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3827         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3828
3829         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3830                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3831                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3832                 return 0;
3833         }
3834         return -ENOENT;
3835 }
3836
3837 static int
3838 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3839                         enum rte_filter_op filter_op,
3840                         void *arg)
3841 {
3842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3843         int ret;
3844
3845         MAC_TYPE_FILTER_SUP(hw->mac.type);
3846
3847         if (filter_op == RTE_ETH_FILTER_NOP)
3848                 return 0;
3849
3850         if (arg == NULL) {
3851                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3852                             filter_op);
3853                 return -EINVAL;
3854         }
3855
3856         switch (filter_op) {
3857         case RTE_ETH_FILTER_ADD:
3858                 ret = ixgbe_syn_filter_set(dev,
3859                                 (struct rte_eth_syn_filter *)arg,
3860                                 TRUE);
3861                 break;
3862         case RTE_ETH_FILTER_DELETE:
3863                 ret = ixgbe_syn_filter_set(dev,
3864                                 (struct rte_eth_syn_filter *)arg,
3865                                 FALSE);
3866                 break;
3867         case RTE_ETH_FILTER_GET:
3868                 ret = ixgbe_syn_filter_get(dev,
3869                                 (struct rte_eth_syn_filter *)arg);
3870                 break;
3871         default:
3872                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3873                 ret = -EINVAL;
3874                 break;
3875         }
3876
3877         return ret;
3878 }
3879
3880
3881 static inline enum ixgbe_5tuple_protocol
3882 convert_protocol_type(uint8_t protocol_value)
3883 {
3884         if (protocol_value == IPPROTO_TCP)
3885                 return IXGBE_FILTER_PROTOCOL_TCP;
3886         else if (protocol_value == IPPROTO_UDP)
3887                 return IXGBE_FILTER_PROTOCOL_UDP;
3888         else if (protocol_value == IPPROTO_SCTP)
3889                 return IXGBE_FILTER_PROTOCOL_SCTP;
3890         else
3891                 return IXGBE_FILTER_PROTOCOL_NONE;
3892 }
3893
3894 /*
3895  * add a 5tuple filter
3896  *
3897  * @param
3898  * dev: Pointer to struct rte_eth_dev.
3899  * index: the index the filter allocates.
3900  * filter: ponter to the filter that will be added.
3901  * rx_queue: the queue id the filter assigned to.
3902  *
3903  * @return
3904  *    - On success, zero.
3905  *    - On failure, a negative value.
3906  */
3907 static int
3908 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3909                         struct ixgbe_5tuple_filter *filter)
3910 {
3911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3912         struct ixgbe_filter_info *filter_info =
3913                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3914         int i, idx, shift;
3915         uint32_t ftqf, sdpqf;
3916         uint32_t l34timir = 0;
3917         uint8_t mask = 0xff;
3918
3919         /*
3920          * look for an unused 5tuple filter index,
3921          * and insert the filter to list.
3922          */
3923         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3924                 idx = i / (sizeof(uint32_t) * NBBY);
3925                 shift = i % (sizeof(uint32_t) * NBBY);
3926                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3927                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3928                         filter->index = i;
3929                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3930                                           filter,
3931                                           entries);
3932                         break;
3933                 }
3934         }
3935         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3936                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3937                 return -ENOSYS;
3938         }
3939
3940         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3941                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3942         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3943
3944         ftqf = (uint32_t)(filter->filter_info.proto &
3945                 IXGBE_FTQF_PROTOCOL_MASK);
3946         ftqf |= (uint32_t)((filter->filter_info.priority &
3947                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3948         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3949                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3950         if (filter->filter_info.dst_ip_mask == 0)
3951                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3952         if (filter->filter_info.src_port_mask == 0)
3953                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3954         if (filter->filter_info.dst_port_mask == 0)
3955                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3956         if (filter->filter_info.proto_mask == 0)
3957                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3958         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3959         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3960         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3961
3962         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3963         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3964         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3965         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3966
3967         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3968         l34timir |= (uint32_t)(filter->queue <<
3969                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3970         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3971         return 0;
3972 }
3973
3974 /*
3975  * remove a 5tuple filter
3976  *
3977  * @param
3978  * dev: Pointer to struct rte_eth_dev.
3979  * filter: the pointer of the filter will be removed.
3980  */
3981 static void
3982 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3983                         struct ixgbe_5tuple_filter *filter)
3984 {
3985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3986         struct ixgbe_filter_info *filter_info =
3987                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3988         uint16_t index = filter->index;
3989
3990         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3991                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3992         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3993         rte_free(filter);
3994
3995         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3996         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3997         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3998         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3999         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4000 }
4001
4002 static int
4003 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4004 {
4005         struct ixgbe_hw *hw;
4006         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4007
4008         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4009
4010         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4011                 return -EINVAL;
4012
4013         /* refuse mtu that requires the support of scattered packets when this
4014          * feature has not been enabled before. */
4015         if (!dev->data->scattered_rx &&
4016             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4017              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4018                 return -EINVAL;
4019
4020         /*
4021          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4022          * request of the version 2.0 of the mailbox API.
4023          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4024          * of the mailbox API.
4025          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4026          * prior to 3.11.33 which contains the following change:
4027          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4028          */
4029         ixgbevf_rlpml_set_vf(hw, max_frame);
4030
4031         /* update max frame size */
4032         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4033         return 0;
4034 }
4035
4036 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4037         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4038                 return -ENOTSUP;\
4039 } while (0)
4040
4041 static inline struct ixgbe_5tuple_filter *
4042 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4043                         struct ixgbe_5tuple_filter_info *key)
4044 {
4045         struct ixgbe_5tuple_filter *it;
4046
4047         TAILQ_FOREACH(it, filter_list, entries) {
4048                 if (memcmp(key, &it->filter_info,
4049                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4050                         return it;
4051                 }
4052         }
4053         return NULL;
4054 }
4055
4056 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4057 static inline int
4058 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4059                         struct ixgbe_5tuple_filter_info *filter_info)
4060 {
4061         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4062                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4063                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4064                 return -EINVAL;
4065
4066         switch (filter->dst_ip_mask) {
4067         case UINT32_MAX:
4068                 filter_info->dst_ip_mask = 0;
4069                 filter_info->dst_ip = filter->dst_ip;
4070                 break;
4071         case 0:
4072                 filter_info->dst_ip_mask = 1;
4073                 break;
4074         default:
4075                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4076                 return -EINVAL;
4077         }
4078
4079         switch (filter->src_ip_mask) {
4080         case UINT32_MAX:
4081                 filter_info->src_ip_mask = 0;
4082                 filter_info->src_ip = filter->src_ip;
4083                 break;
4084         case 0:
4085                 filter_info->src_ip_mask = 1;
4086                 break;
4087         default:
4088                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4089                 return -EINVAL;
4090         }
4091
4092         switch (filter->dst_port_mask) {
4093         case UINT16_MAX:
4094                 filter_info->dst_port_mask = 0;
4095                 filter_info->dst_port = filter->dst_port;
4096                 break;
4097         case 0:
4098                 filter_info->dst_port_mask = 1;
4099                 break;
4100         default:
4101                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4102                 return -EINVAL;
4103         }
4104
4105         switch (filter->src_port_mask) {
4106         case UINT16_MAX:
4107                 filter_info->src_port_mask = 0;
4108                 filter_info->src_port = filter->src_port;
4109                 break;
4110         case 0:
4111                 filter_info->src_port_mask = 1;
4112                 break;
4113         default:
4114                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4115                 return -EINVAL;
4116         }
4117
4118         switch (filter->proto_mask) {
4119         case UINT8_MAX:
4120                 filter_info->proto_mask = 0;
4121                 filter_info->proto =
4122                         convert_protocol_type(filter->proto);
4123                 break;
4124         case 0:
4125                 filter_info->proto_mask = 1;
4126                 break;
4127         default:
4128                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4129                 return -EINVAL;
4130         }
4131
4132         filter_info->priority = (uint8_t)filter->priority;
4133         return 0;
4134 }
4135
4136 /*
4137  * add or delete a ntuple filter
4138  *
4139  * @param
4140  * dev: Pointer to struct rte_eth_dev.
4141  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4142  * add: if true, add filter, if false, remove filter
4143  *
4144  * @return
4145  *    - On success, zero.
4146  *    - On failure, a negative value.
4147  */
4148 static int
4149 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4150                         struct rte_eth_ntuple_filter *ntuple_filter,
4151                         bool add)
4152 {
4153         struct ixgbe_filter_info *filter_info =
4154                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4155         struct ixgbe_5tuple_filter_info filter_5tuple;
4156         struct ixgbe_5tuple_filter *filter;
4157         int ret;
4158
4159         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4160                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4161                 return -EINVAL;
4162         }
4163
4164         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4165         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4166         if (ret < 0)
4167                 return ret;
4168
4169         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4170                                          &filter_5tuple);
4171         if (filter != NULL && add) {
4172                 PMD_DRV_LOG(ERR, "filter exists.");
4173                 return -EEXIST;
4174         }
4175         if (filter == NULL && !add) {
4176                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4177                 return -ENOENT;
4178         }
4179
4180         if (add) {
4181                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4182                                 sizeof(struct ixgbe_5tuple_filter), 0);
4183                 if (filter == NULL)
4184                         return -ENOMEM;
4185                 (void)rte_memcpy(&filter->filter_info,
4186                                  &filter_5tuple,
4187                                  sizeof(struct ixgbe_5tuple_filter_info));
4188                 filter->queue = ntuple_filter->queue;
4189                 ret = ixgbe_add_5tuple_filter(dev, filter);
4190                 if (ret < 0) {
4191                         rte_free(filter);
4192                         return ret;
4193                 }
4194         } else
4195                 ixgbe_remove_5tuple_filter(dev, filter);
4196
4197         return 0;
4198 }
4199
4200 /*
4201  * get a ntuple filter
4202  *
4203  * @param
4204  * dev: Pointer to struct rte_eth_dev.
4205  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4206  *
4207  * @return
4208  *    - On success, zero.
4209  *    - On failure, a negative value.
4210  */
4211 static int
4212 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4213                         struct rte_eth_ntuple_filter *ntuple_filter)
4214 {
4215         struct ixgbe_filter_info *filter_info =
4216                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4217         struct ixgbe_5tuple_filter_info filter_5tuple;
4218         struct ixgbe_5tuple_filter *filter;
4219         int ret;
4220
4221         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4222                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4223                 return -EINVAL;
4224         }
4225
4226         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4227         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4228         if (ret < 0)
4229                 return ret;
4230
4231         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4232                                          &filter_5tuple);
4233         if (filter == NULL) {
4234                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4235                 return -ENOENT;
4236         }
4237         ntuple_filter->queue = filter->queue;
4238         return 0;
4239 }
4240
4241 /*
4242  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4243  * @dev: pointer to rte_eth_dev structure
4244  * @filter_op:operation will be taken.
4245  * @arg: a pointer to specific structure corresponding to the filter_op
4246  *
4247  * @return
4248  *    - On success, zero.
4249  *    - On failure, a negative value.
4250  */
4251 static int
4252 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4253                                 enum rte_filter_op filter_op,
4254                                 void *arg)
4255 {
4256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4257         int ret;
4258
4259         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4260
4261         if (filter_op == RTE_ETH_FILTER_NOP)
4262                 return 0;
4263
4264         if (arg == NULL) {
4265                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4266                             filter_op);
4267                 return -EINVAL;
4268         }
4269
4270         switch (filter_op) {
4271         case RTE_ETH_FILTER_ADD:
4272                 ret = ixgbe_add_del_ntuple_filter(dev,
4273                         (struct rte_eth_ntuple_filter *)arg,
4274                         TRUE);
4275                 break;
4276         case RTE_ETH_FILTER_DELETE:
4277                 ret = ixgbe_add_del_ntuple_filter(dev,
4278                         (struct rte_eth_ntuple_filter *)arg,
4279                         FALSE);
4280                 break;
4281         case RTE_ETH_FILTER_GET:
4282                 ret = ixgbe_get_ntuple_filter(dev,
4283                         (struct rte_eth_ntuple_filter *)arg);
4284                 break;
4285         default:
4286                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4287                 ret = -EINVAL;
4288                 break;
4289         }
4290         return ret;
4291 }
4292
4293 static inline int
4294 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4295                         uint16_t ethertype)
4296 {
4297         int i;
4298
4299         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4300                 if (filter_info->ethertype_filters[i] == ethertype &&
4301                     (filter_info->ethertype_mask & (1 << i)))
4302                         return i;
4303         }
4304         return -1;
4305 }
4306
4307 static inline int
4308 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4309                         uint16_t ethertype)
4310 {
4311         int i;
4312
4313         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4314                 if (!(filter_info->ethertype_mask & (1 << i))) {
4315                         filter_info->ethertype_mask |= 1 << i;
4316                         filter_info->ethertype_filters[i] = ethertype;
4317                         return i;
4318                 }
4319         }
4320         return -1;
4321 }
4322
4323 static inline int
4324 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4325                         uint8_t idx)
4326 {
4327         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4328                 return -1;
4329         filter_info->ethertype_mask &= ~(1 << idx);
4330         filter_info->ethertype_filters[idx] = 0;
4331         return idx;
4332 }
4333
4334 static int
4335 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4336                         struct rte_eth_ethertype_filter *filter,
4337                         bool add)
4338 {
4339         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4340         struct ixgbe_filter_info *filter_info =
4341                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4342         uint32_t etqf = 0;
4343         uint32_t etqs = 0;
4344         int ret;
4345
4346         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4347                 return -EINVAL;
4348
4349         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4350                 filter->ether_type == ETHER_TYPE_IPv6) {
4351                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4352                         " ethertype filter.", filter->ether_type);
4353                 return -EINVAL;
4354         }
4355
4356         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4357                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4358                 return -EINVAL;
4359         }
4360         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4361                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4362                 return -EINVAL;
4363         }
4364
4365         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4366         if (ret >= 0 && add) {
4367                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4368                             filter->ether_type);
4369                 return -EEXIST;
4370         }
4371         if (ret < 0 && !add) {
4372                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4373                             filter->ether_type);
4374                 return -ENOENT;
4375         }
4376
4377         if (add) {
4378                 ret = ixgbe_ethertype_filter_insert(filter_info,
4379                         filter->ether_type);
4380                 if (ret < 0) {
4381                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4382                         return -ENOSYS;
4383                 }
4384                 etqf = IXGBE_ETQF_FILTER_EN;
4385                 etqf |= (uint32_t)filter->ether_type;
4386                 etqs |= (uint32_t)((filter->queue <<
4387                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4388                                     IXGBE_ETQS_RX_QUEUE);
4389                 etqs |= IXGBE_ETQS_QUEUE_EN;
4390         } else {
4391                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4392                 if (ret < 0)
4393                         return -ENOSYS;
4394         }
4395         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4396         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4397         IXGBE_WRITE_FLUSH(hw);
4398
4399         return 0;
4400 }
4401
4402 static int
4403 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4404                         struct rte_eth_ethertype_filter *filter)
4405 {
4406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         struct ixgbe_filter_info *filter_info =
4408                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4409         uint32_t etqf, etqs;
4410         int ret;
4411
4412         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4413         if (ret < 0) {
4414                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4415                             filter->ether_type);
4416                 return -ENOENT;
4417         }
4418
4419         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4420         if (etqf & IXGBE_ETQF_FILTER_EN) {
4421                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4422                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4423                 filter->flags = 0;
4424                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4425                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4426                 return 0;
4427         }
4428         return -ENOENT;
4429 }
4430
4431 /*
4432  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4433  * @dev: pointer to rte_eth_dev structure
4434  * @filter_op:operation will be taken.
4435  * @arg: a pointer to specific structure corresponding to the filter_op
4436  */
4437 static int
4438 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4439                                 enum rte_filter_op filter_op,
4440                                 void *arg)
4441 {
4442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4443         int ret;
4444
4445         MAC_TYPE_FILTER_SUP(hw->mac.type);
4446
4447         if (filter_op == RTE_ETH_FILTER_NOP)
4448                 return 0;
4449
4450         if (arg == NULL) {
4451                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4452                             filter_op);
4453                 return -EINVAL;
4454         }
4455
4456         switch (filter_op) {
4457         case RTE_ETH_FILTER_ADD:
4458                 ret = ixgbe_add_del_ethertype_filter(dev,
4459                         (struct rte_eth_ethertype_filter *)arg,
4460                         TRUE);
4461                 break;
4462         case RTE_ETH_FILTER_DELETE:
4463                 ret = ixgbe_add_del_ethertype_filter(dev,
4464                         (struct rte_eth_ethertype_filter *)arg,
4465                         FALSE);
4466                 break;
4467         case RTE_ETH_FILTER_GET:
4468                 ret = ixgbe_get_ethertype_filter(dev,
4469                         (struct rte_eth_ethertype_filter *)arg);
4470                 break;
4471         default:
4472                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4473                 ret = -EINVAL;
4474                 break;
4475         }
4476         return ret;
4477 }
4478
4479 static int
4480 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4481                      enum rte_filter_type filter_type,
4482                      enum rte_filter_op filter_op,
4483                      void *arg)
4484 {
4485         int ret = -EINVAL;
4486
4487         switch (filter_type) {
4488         case RTE_ETH_FILTER_NTUPLE:
4489                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4490                 break;
4491         case RTE_ETH_FILTER_ETHERTYPE:
4492                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4493                 break;
4494         case RTE_ETH_FILTER_SYN:
4495                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4496                 break;
4497         case RTE_ETH_FILTER_FDIR:
4498                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4499                 break;
4500         default:
4501                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4502                                                         filter_type);
4503                 break;
4504         }
4505
4506         return ret;
4507 }
4508
4509 static u8 *
4510 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4511                         u8 **mc_addr_ptr, u32 *vmdq)
4512 {
4513         u8 *mc_addr;
4514
4515         *vmdq = 0;
4516         mc_addr = *mc_addr_ptr;
4517         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4518         return mc_addr;
4519 }
4520
4521 static int
4522 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4523                            struct ether_addr *mc_addr_set,
4524                            uint32_t nb_mc_addr)
4525 {
4526         struct ixgbe_hw *hw;
4527         u8 *mc_addr_list;
4528
4529         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4530         mc_addr_list = (u8 *)mc_addr_set;
4531         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4532                                          ixgbe_dev_addr_list_itr, TRUE);
4533 }
4534
4535 static int
4536 ixgbe_timesync_enable(struct rte_eth_dev *dev)
4537 {
4538         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4539         uint32_t tsync_ctl;
4540         uint32_t tsauxc;
4541
4542         /* Enable system time for platforms where it isn't on by default. */
4543         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
4544         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
4545         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
4546
4547         /* Start incrementing the register used to timestamp PTP packets. */
4548         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
4549
4550         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4551         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
4552                         (ETHER_TYPE_1588 |
4553                          IXGBE_ETQF_FILTER_EN |
4554                          IXGBE_ETQF_1588));
4555
4556         /* Enable timestamping of received PTP packets. */
4557         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4558         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
4559         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4560
4561         /* Enable timestamping of transmitted PTP packets. */
4562         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4563         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
4564         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4565
4566         return 0;
4567 }
4568
4569 static int
4570 ixgbe_timesync_disable(struct rte_eth_dev *dev)
4571 {
4572         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4573         uint32_t tsync_ctl;
4574
4575         /* Disable timestamping of transmitted PTP packets. */
4576         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4577         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
4578         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4579
4580         /* Disable timestamping of received PTP packets. */
4581         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4582         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
4583         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4584
4585         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4586         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
4587
4588         /* Stop incrementating the System Time registers. */
4589         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
4590
4591         return 0;
4592 }
4593
4594 static int
4595 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4596                                  struct timespec *timestamp,
4597                                  uint32_t flags __rte_unused)
4598 {
4599         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4600         uint32_t tsync_rxctl;
4601         uint32_t rx_stmpl;
4602         uint32_t rx_stmph;
4603
4604         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4605         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
4606                 return -EINVAL;
4607
4608         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
4609         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
4610
4611         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4612         timestamp->tv_nsec = 0;
4613
4614         return  0;
4615 }
4616
4617 static int
4618 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4619                                  struct timespec *timestamp)
4620 {
4621         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4622         uint32_t tsync_txctl;
4623         uint32_t tx_stmpl;
4624         uint32_t tx_stmph;
4625
4626         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4627         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
4628                 return -EINVAL;
4629
4630         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
4631         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
4632
4633         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4634         timestamp->tv_nsec = 0;
4635
4636         return  0;
4637 }
4638
4639 static struct rte_driver rte_ixgbe_driver = {
4640         .type = PMD_PDEV,
4641         .init = rte_ixgbe_pmd_init,
4642 };
4643
4644 static struct rte_driver rte_ixgbevf_driver = {
4645         .type = PMD_PDEV,
4646         .init = rte_ixgbevf_pmd_init,
4647 };
4648
4649 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4650 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);