drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 120 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 121 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 122 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 124 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 125 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 126 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 131                                 int wait_to_complete);
 132 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 133                                 struct rte_eth_stats *stats);
 134 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 135 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 136                                              uint16_t queue_id,
 137                                              uint8_t stat_idx,
 138                                              uint8_t is_rx);
 139 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 140                                struct rte_eth_dev_info *dev_info);
 141 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 142                                  struct rte_eth_dev_info *dev_info);
 143 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 144
 145 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 146                 uint16_t vlan_id, int on);
 147 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 148 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 149                 uint16_t queue, bool on);
 150 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 151                 int on);
 152 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 154 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 155 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 156 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 157
 158 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 159 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 160 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_fc_conf *fc_conf);
 162 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 165                 struct rte_eth_pfc_conf *pfc_conf);
 166 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 167                         struct rte_eth_rss_reta_entry64 *reta_conf,
 168                         uint16_t reta_size);
 169 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 170                         struct rte_eth_rss_reta_entry64 *reta_conf,
 171                         uint16_t reta_size);
 172 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 173 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 174 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 177                 void *param);
 178 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 179 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 180                 uint32_t index, uint32_t pool);
 181 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 182 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 183
 184 /* For Virtual Function support */
 185 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 186 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 187 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 188 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 190 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 191 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 192                 struct rte_eth_stats *stats);
 193 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 194 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 195                 uint16_t vlan_id, int on);
 196 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 197                 uint16_t queue, int on);
 198 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 200
 201 /* For Eth VMDQ APIs support */
 202 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 203                 ether_addr* mac_addr,uint8_t on);
 204 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 205 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 206                 uint16_t rx_mask, uint8_t on);
 207 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 208 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 209 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 210                 uint64_t pool_mask,uint8_t vlan_on);
 211 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_vmdq_mirror_conf *mirror_conf,
 213                 uint8_t rule_id, uint8_t on);
 214 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 215                 uint8_t rule_id);
 216
 217 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 218                 uint16_t queue_idx, uint16_t tx_rate);
 219 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 220                 uint16_t tx_rate, uint64_t q_msk);
 221
 222 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 223                                  struct ether_addr *mac_addr,
 224                                  uint32_t index, uint32_t pool);
 225 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 226 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 227                         struct rte_eth_syn_filter *filter,
 228                         bool add);
 229 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 230                         struct rte_eth_syn_filter *filter);
 231 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 232                         enum rte_filter_op filter_op,
 233                         void *arg);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 235                         struct ixgbe_5tuple_filter *filter);
 236 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         struct ixgbe_5tuple_filter *filter);
 238 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *filter,
 240                         bool add);
 241 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 242                                 enum rte_filter_op filter_op,
 243                                 void *arg);
 244 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 245                         struct rte_eth_ntuple_filter *filter);
 246 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter,
 248                         bool add);
 249 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 250                                 enum rte_filter_op filter_op,
 251                                 void *arg);
 252 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 253                         struct rte_eth_ethertype_filter *filter);
 254 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 255                      enum rte_filter_type filter_type,
 256                      enum rte_filter_op filter_op,
 257                      void *arg);
 258 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 259
 260 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 261                                       struct ether_addr *mc_addr_set,
 262                                       uint32_t nb_mc_addr);
 263
 264 /*
 265  * Define VF Stats MACRO for Non "cleared on read" register
 266  */
 267 #define UPDATE_VF_STAT(reg, last, cur)                          \
 268 {                                                               \
 269         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 270         cur += latest - last;                                   \
 271         last = latest;                                          \
 272 }
 273
 274 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 275 {                                                                \
 276         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 277         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 278         u64 latest = ((new_msb << 32) | new_lsb);                \
 279         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 280         last = latest;                                           \
 281 }
 282
 283 #define IXGBE_SET_HWSTRIP(h, q) do{\
 284                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 285                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 286                 (h)->bitmap[idx] |= 1 << bit;\
 287         }while(0)
 288
 289 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 290                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 291                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 292                 (h)->bitmap[idx] &= ~(1 << bit);\
 293         }while(0)
 294
 295 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 296                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 297                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 298                 (r) = (h)->bitmap[idx] >> bit & 1;\
 299         }while(0)
 300
 301 /*
 302  * The set of PCI devices this driver supports
 303  */
 304 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 305
 306 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 307 #include "rte_pci_dev_ids.h"
 308
 309 { .vendor_id = 0, /* sentinel */ },
 310 };
 311
 312
 313 /*
 314  * The set of PCI devices this driver supports (for 82599 VF)
 315  */
 316 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 317
 318 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 319 #include "rte_pci_dev_ids.h"
 320 { .vendor_id = 0, /* sentinel */ },
 321
 322 };
 323
 324 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 325         .dev_configure        = ixgbe_dev_configure,
 326         .dev_start            = ixgbe_dev_start,
 327         .dev_stop             = ixgbe_dev_stop,
 328         .dev_set_link_up    = ixgbe_dev_set_link_up,
 329         .dev_set_link_down  = ixgbe_dev_set_link_down,
 330         .dev_close            = ixgbe_dev_close,
 331         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 332         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 333         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 334         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 335         .link_update          = ixgbe_dev_link_update,
 336         .stats_get            = ixgbe_dev_stats_get,
 337         .stats_reset          = ixgbe_dev_stats_reset,
 338         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 339         .dev_infos_get        = ixgbe_dev_info_get,
 340         .mtu_set              = ixgbe_dev_mtu_set,
 341         .vlan_filter_set      = ixgbe_vlan_filter_set,
 342         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 343         .vlan_offload_set     = ixgbe_vlan_offload_set,
 344         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 345         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 346         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 347         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 348         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 349         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 350         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 351         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 352         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 353         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 354         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 355         .dev_led_on           = ixgbe_dev_led_on,
 356         .dev_led_off          = ixgbe_dev_led_off,
 357         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 358         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 359         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 360         .mac_addr_add         = ixgbe_add_rar,
 361         .mac_addr_remove      = ixgbe_remove_rar,
 362         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 363         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 364         .mirror_rule_set      = ixgbe_mirror_rule_set,
 365         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 366         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 367         .set_vf_rx            = ixgbe_set_pool_rx,
 368         .set_vf_tx            = ixgbe_set_pool_tx,
 369         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 370         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 371         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 372         .reta_update          = ixgbe_dev_rss_reta_update,
 373         .reta_query           = ixgbe_dev_rss_reta_query,
 374 #ifdef RTE_NIC_BYPASS
 375         .bypass_init          = ixgbe_bypass_init,
 376         .bypass_state_set     = ixgbe_bypass_state_store,
 377         .bypass_state_show    = ixgbe_bypass_state_show,
 378         .bypass_event_set     = ixgbe_bypass_event_store,
 379         .bypass_event_show    = ixgbe_bypass_event_show,
 380         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 381         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 382         .bypass_ver_show      = ixgbe_bypass_ver_show,
 383         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 384 #endif /* RTE_NIC_BYPASS */
 385         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 386         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 387         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 388         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 389 };
 390
 391 /*
 392  * dev_ops for virtual function, bare necessities for basic vf
 393  * operation have been implemented
 394  */
 395 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 396         .dev_configure        = ixgbevf_dev_configure,
 397         .dev_start            = ixgbevf_dev_start,
 398         .dev_stop             = ixgbevf_dev_stop,
 399         .link_update          = ixgbe_dev_link_update,
 400         .stats_get            = ixgbevf_dev_stats_get,
 401         .stats_reset          = ixgbevf_dev_stats_reset,
 402         .dev_close            = ixgbevf_dev_close,
 403         .dev_infos_get        = ixgbevf_dev_info_get,
 404         .mtu_set              = ixgbevf_dev_set_mtu,
 405         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 406         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 407         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 408         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 409         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 410         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 411         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 412         .mac_addr_add         = ixgbevf_add_mac_addr,
 413         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 414         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 415 };
 416
 417 /**
 418  * Atomically reads the link status information from global
 419  * structure rte_eth_dev.
 420  *
 421  * @param dev
 422  *   - Pointer to the structure rte_eth_dev to read from.
 423  *   - Pointer to the buffer to be saved with the link status.
 424  *
 425  * @return
 426  *   - On success, zero.
 427  *   - On failure, negative value.
 428  */
 429 static inline int
 430 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 431                                 struct rte_eth_link *link)
 432 {
 433         struct rte_eth_link *dst = link;
 434         struct rte_eth_link *src = &(dev->data->dev_link);
 435
 436         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 437                                         *(uint64_t *)src) == 0)
 438                 return -1;
 439
 440         return 0;
 441 }
 442
 443 /**
 444  * Atomically writes the link status information into global
 445  * structure rte_eth_dev.
 446  *
 447  * @param dev
 448  *   - Pointer to the structure rte_eth_dev to read from.
 449  *   - Pointer to the buffer to be saved with the link status.
 450  *
 451  * @return
 452  *   - On success, zero.
 453  *   - On failure, negative value.
 454  */
 455 static inline int
 456 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 457                                 struct rte_eth_link *link)
 458 {
 459         struct rte_eth_link *dst = &(dev->data->dev_link);
 460         struct rte_eth_link *src = link;
 461
 462         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 463                                         *(uint64_t *)src) == 0)
 464                 return -1;
 465
 466         return 0;
 467 }
 468
 469 /*
 470  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 471  */
 472 static inline int
 473 ixgbe_is_sfp(struct ixgbe_hw *hw)
 474 {
 475         switch (hw->phy.type) {
 476         case ixgbe_phy_sfp_avago:
 477         case ixgbe_phy_sfp_ftl:
 478         case ixgbe_phy_sfp_intel:
 479         case ixgbe_phy_sfp_unknown:
 480         case ixgbe_phy_sfp_passive_tyco:
 481         case ixgbe_phy_sfp_passive_unknown:
 482                 return 1;
 483         default:
 484                 return 0;
 485         }
 486 }
 487
 488 static inline int32_t
 489 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 490 {
 491         uint32_t ctrl_ext;
 492         int32_t status;
 493
 494         status = ixgbe_reset_hw(hw);
 495
 496         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 497         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 498         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 499         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 500         IXGBE_WRITE_FLUSH(hw);
 501
 502         return status;
 503 }
 504
 505 static inline void
 506 ixgbe_enable_intr(struct rte_eth_dev *dev)
 507 {
 508         struct ixgbe_interrupt *intr =
 509                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 510         struct ixgbe_hw *hw =
 511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 512
 513         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 514         IXGBE_WRITE_FLUSH(hw);
 515 }
 516
 517 /*
 518  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 519  */
 520 static void
 521 ixgbe_disable_intr(struct ixgbe_hw *hw)
 522 {
 523         PMD_INIT_FUNC_TRACE();
 524
 525         if (hw->mac.type == ixgbe_mac_82598EB) {
 526                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 527         } else {
 528                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 529                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 530                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 531         }
 532         IXGBE_WRITE_FLUSH(hw);
 533 }
 534
 535 /*
 536  * This function resets queue statistics mapping registers.
 537  * From Niantic datasheet, Initialization of Statistics section:
 538  * "...if software requires the queue counters, the RQSMR and TQSM registers
 539  * must be re-programmed following a device reset.
 540  */
 541 static void
 542 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 543 {
 544         uint32_t i;
 545
 546         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 547                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 548                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 549         }
 550 }
 551
 552
 553 static int
 554 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 555                                   uint16_t queue_id,
 556                                   uint8_t stat_idx,
 557                                   uint8_t is_rx)
 558 {
 559 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 560 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 561 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 562
 563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 564         struct ixgbe_stat_mapping_registers *stat_mappings =
 565                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 566         uint32_t qsmr_mask = 0;
 567         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 568         uint32_t q_map;
 569         uint8_t n, offset;
 570
 571         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 572                 (hw->mac.type != ixgbe_mac_X540) &&
 573                 (hw->mac.type != ixgbe_mac_X550) &&
 574                 (hw->mac.type != ixgbe_mac_X550EM_x))
 575                 return -ENOSYS;
 576
 577         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 578                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 579                      queue_id, stat_idx);
 580
 581         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 582         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 583                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 584                 return -EIO;
 585         }
 586         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 587
 588         /* Now clear any previous stat_idx set */
 589         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 590         if (!is_rx)
 591                 stat_mappings->tqsm[n] &= ~clearing_mask;
 592         else
 593                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 594
 595         q_map = (uint32_t)stat_idx;
 596         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 597         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 598         if (!is_rx)
 599                 stat_mappings->tqsm[n] |= qsmr_mask;
 600         else
 601                 stat_mappings->rqsmr[n] |= qsmr_mask;
 602
 603         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 604                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 605                      queue_id, stat_idx);
 606         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 607                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 608
 609         /* Now write the mapping in the appropriate register */
 610         if (is_rx) {
 611                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 612                              stat_mappings->rqsmr[n], n);
 613                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 614         }
 615         else {
 616                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 617                              stat_mappings->tqsm[n], n);
 618                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 619         }
 620         return 0;
 621 }
 622
 623 static void
 624 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 625 {
 626         struct ixgbe_stat_mapping_registers *stat_mappings =
 627                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 629         int i;
 630
 631         /* write whatever was in stat mapping table to the NIC */
 632         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 633                 /* rx */
 634                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 635
 636                 /* tx */
 637                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 638         }
 639 }
 640
 641 static void
 642 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 643 {
 644         uint8_t i;
 645         struct ixgbe_dcb_tc_config *tc;
 646         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 647
 648         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 649         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 650         for (i = 0; i < dcb_max_tc; i++) {
 651                 tc = &dcb_config->tc_config[i];
 652                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 653                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 654                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 655                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 656                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 657                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 658                 tc->pfc = ixgbe_dcb_pfc_disabled;
 659         }
 660
 661         /* Initialize default user to priority mapping, UPx->TC0 */
 662         tc = &dcb_config->tc_config[0];
 663         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 664         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 665         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 666                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 667                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 668         }
 669         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 670         dcb_config->pfc_mode_enable = false;
 671         dcb_config->vt_mode = true;
 672         dcb_config->round_robin_enable = false;
 673         /* support all DCB capabilities in 82599 */
 674         dcb_config->support.capabilities = 0xFF;
 675
 676         /*we only support 4 Tcs for X540, X550 */
 677         if (hw->mac.type == ixgbe_mac_X540 ||
 678                 hw->mac.type == ixgbe_mac_X550 ||
 679                 hw->mac.type == ixgbe_mac_X550EM_x) {
 680                 dcb_config->num_tcs.pg_tcs = 4;
 681                 dcb_config->num_tcs.pfc_tcs = 4;
 682         }
 683 }
 684
 685 /*
 686  * Ensure that all locks are released before first NVM or PHY access
 687  */
 688 static void
 689 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 690 {
 691         uint16_t mask;
 692
 693         /*
 694          * Phy lock should not fail in this early stage. If this is the case,
 695          * it is due to an improper exit of the application.
 696          * So force the release of the faulty lock. Release of common lock
 697          * is done automatically by swfw_sync function.
 698          */
 699         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 700         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 701                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 702         }
 703         ixgbe_release_swfw_semaphore(hw, mask);
 704
 705         /*
 706          * These ones are more tricky since they are common to all ports; but
 707          * swfw_sync retries last long enough (1s) to be almost sure that if
 708          * lock can not be taken it is due to an improper lock of the
 709          * semaphore.
 710          */
 711         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 712         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 714         }
 715         ixgbe_release_swfw_semaphore(hw, mask);
 716 }
 717
 718 /*
 719  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 720  * It returns 0 on success.
 721  */
 722 static int
 723 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 724 {
 725         struct rte_pci_device *pci_dev;
 726         struct ixgbe_hw *hw =
 727                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 728         struct ixgbe_vfta * shadow_vfta =
 729                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 730         struct ixgbe_hwstrip *hwstrip =
 731                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 732         struct ixgbe_dcb_config *dcb_config =
 733                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 734         struct ixgbe_filter_info *filter_info =
 735                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 736         uint32_t ctrl_ext;
 737         uint16_t csum;
 738         int diag, i;
 739
 740         PMD_INIT_FUNC_TRACE();
 741
 742         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 743         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 744         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 745
 746         /*
 747          * For secondary processes, we don't initialise any further as primary
 748          * has already done this work. Only check we don't need a different
 749          * RX and TX function.
 750          */
 751         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 752                 struct ixgbe_tx_queue *txq;
 753                 /* TX queue function in primary, set by last queue initialized
 754                  * Tx queue may not initialized by primary process */
 755                 if (eth_dev->data->tx_queues) {
 756                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 757                         ixgbe_set_tx_function(eth_dev, txq);
 758                 } else {
 759                         /* Use default TX function if we get here */
 760                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 761                                            "Using default TX function.");
 762                 }
 763
 764                 ixgbe_set_rx_function(eth_dev);
 765
 766                 return 0;
 767         }
 768         pci_dev = eth_dev->pci_dev;
 769
 770         /* Vendor and Device ID need to be set before init of shared code */
 771         hw->device_id = pci_dev->id.device_id;
 772         hw->vendor_id = pci_dev->id.vendor_id;
 773         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 774         hw->allow_unsupported_sfp = 1;
 775
 776         /* Initialize the shared code (base driver) */
 777 #ifdef RTE_NIC_BYPASS
 778         diag = ixgbe_bypass_init_shared_code(hw);
 779 #else
 780         diag = ixgbe_init_shared_code(hw);
 781 #endif /* RTE_NIC_BYPASS */
 782
 783         if (diag != IXGBE_SUCCESS) {
 784                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 785                 return -EIO;
 786         }
 787
 788         /* pick up the PCI bus settings for reporting later */
 789         ixgbe_get_bus_info(hw);
 790
 791         /* Unlock any pending hardware semaphore */
 792         ixgbe_swfw_lock_reset(hw);
 793
 794         /* Initialize DCB configuration*/
 795         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 796         ixgbe_dcb_init(hw,dcb_config);
 797         /* Get Hardware Flow Control setting */
 798         hw->fc.requested_mode = ixgbe_fc_full;
 799         hw->fc.current_mode = ixgbe_fc_full;
 800         hw->fc.pause_time = IXGBE_FC_PAUSE;
 801         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 802                 hw->fc.low_water[i] = IXGBE_FC_LO;
 803                 hw->fc.high_water[i] = IXGBE_FC_HI;
 804         }
 805         hw->fc.send_xon = 1;
 806
 807         /* Make sure we have a good EEPROM before we read from it */
 808         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 809         if (diag != IXGBE_SUCCESS) {
 810                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 811                 return -EIO;
 812         }
 813
 814 #ifdef RTE_NIC_BYPASS
 815         diag = ixgbe_bypass_init_hw(hw);
 816 #else
 817         diag = ixgbe_init_hw(hw);
 818 #endif /* RTE_NIC_BYPASS */
 819
 820         /*
 821          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 822          * is called too soon after the kernel driver unbinding/binding occurs.
 823          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 824          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 825          * also called. See ixgbe_identify_phy_82599(). The reason for the
 826          * failure is not known, and only occuts when virtualisation features
 827          * are disabled in the bios. A delay of 100ms  was found to be enough by
 828          * trial-and-error, and is doubled to be safe.
 829          */
 830         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 831                 rte_delay_ms(200);
 832                 diag = ixgbe_init_hw(hw);
 833         }
 834
 835         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 836                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 837                     "LOM.  Please be aware there may be issues associated "
 838                     "with your hardware.");
 839                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 840                     "please contact your Intel or hardware representative "
 841                     "who provided you with this hardware.");
 842         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 843                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 844         if (diag) {
 845                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 846                 return -EIO;
 847         }
 848
 849         /* disable interrupt */
 850         ixgbe_disable_intr(hw);
 851
 852         /* reset mappings for queue statistics hw counters*/
 853         ixgbe_reset_qstat_mappings(hw);
 854
 855         /* Allocate memory for storing MAC addresses */
 856         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 857                         hw->mac.num_rar_entries, 0);
 858         if (eth_dev->data->mac_addrs == NULL) {
 859                 PMD_INIT_LOG(ERR,
 860                         "Failed to allocate %u bytes needed to store "
 861                         "MAC addresses",
 862                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 863                 return -ENOMEM;
 864         }
 865         /* Copy the permanent MAC address */
 866         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 867                         &eth_dev->data->mac_addrs[0]);
 868
 869         /* Allocate memory for storing hash filter MAC addresses */
 870         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 871                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 872         if (eth_dev->data->hash_mac_addrs == NULL) {
 873                 PMD_INIT_LOG(ERR,
 874                         "Failed to allocate %d bytes needed to store MAC addresses",
 875                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 876                 return -ENOMEM;
 877         }
 878
 879         /* initialize the vfta */
 880         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 881
 882         /* initialize the hw strip bitmap*/
 883         memset(hwstrip, 0, sizeof(*hwstrip));
 884
 885         /* initialize PF if max_vfs not zero */
 886         ixgbe_pf_host_init(eth_dev);
 887
 888         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 889         /* let hardware know driver is loaded */
 890         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 891         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 892         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 893         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 894         IXGBE_WRITE_FLUSH(hw);
 895
 896         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 897                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 898                              (int) hw->mac.type, (int) hw->phy.type,
 899                              (int) hw->phy.sfp_type);
 900         else
 901                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 902                              (int) hw->mac.type, (int) hw->phy.type);
 903
 904         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 905                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 906                         pci_dev->id.device_id);
 907
 908         rte_intr_callback_register(&(pci_dev->intr_handle),
 909                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 910
 911         /* enable uio intr after callback register */
 912         rte_intr_enable(&(pci_dev->intr_handle));
 913
 914         /* enable support intr */
 915         ixgbe_enable_intr(eth_dev);
 916
 917         /* initialize 5tuple filter list */
 918         TAILQ_INIT(&filter_info->fivetuple_list);
 919         memset(filter_info->fivetuple_mask, 0,
 920                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 921
 922         return 0;
 923 }
 924
 925
 926 /*
 927  * Negotiate mailbox API version with the PF.
 928  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 929  * Then we try to negotiate starting with the most recent one.
 930  * If all negotiation attempts fail, then we will proceed with
 931  * the default one (ixgbe_mbox_api_10).
 932  */
 933 static void
 934 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 935 {
 936         int32_t i;
 937
 938         /* start with highest supported, proceed down */
 939         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 940                 ixgbe_mbox_api_11,
 941                 ixgbe_mbox_api_10,
 942         };
 943
 944         for (i = 0;
 945                         i != RTE_DIM(sup_ver) &&
 946                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 947                         i++)
 948                 ;
 949 }
 950
 951 static void
 952 generate_random_mac_addr(struct ether_addr *mac_addr)
 953 {
 954         uint64_t random;
 955
 956         /* Set Organizationally Unique Identifier (OUI) prefix. */
 957         mac_addr->addr_bytes[0] = 0x00;
 958         mac_addr->addr_bytes[1] = 0x09;
 959         mac_addr->addr_bytes[2] = 0xC0;
 960         /* Force indication of locally assigned MAC address. */
 961         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 962         /* Generate the last 3 bytes of the MAC address with a random number. */
 963         random = rte_rand();
 964         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 965 }
 966
 967 /*
 968  * Virtual Function device init
 969  */
 970 static int
 971 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 972 {
 973         int diag;
 974         uint32_t tc, tcs;
 975         struct rte_pci_device *pci_dev;
 976         struct ixgbe_hw *hw =
 977                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 978         struct ixgbe_vfta * shadow_vfta =
 979                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 980         struct ixgbe_hwstrip *hwstrip =
 981                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 982         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 983
 984         PMD_INIT_FUNC_TRACE();
 985
 986         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 987         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 988         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 989
 990         /* for secondary processes, we don't initialise any further as primary
 991          * has already done this work. Only check we don't need a different
 992          * RX function */
 993         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 994                 if (eth_dev->data->scattered_rx)
 995                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
 996                 return 0;
 997         }
 998
 999         pci_dev = eth_dev->pci_dev;
1000
1001         hw->device_id = pci_dev->id.device_id;
1002         hw->vendor_id = pci_dev->id.vendor_id;
1003         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004
1005         /* initialize the vfta */
1006         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1007
1008         /* initialize the hw strip bitmap*/
1009         memset(hwstrip, 0, sizeof(*hwstrip));
1010
1011         /* Initialize the shared code (base driver) */
1012         diag = ixgbe_init_shared_code(hw);
1013         if (diag != IXGBE_SUCCESS) {
1014                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1015                 return -EIO;
1016         }
1017
1018         /* init_mailbox_params */
1019         hw->mbx.ops.init_params(hw);
1020
1021         /* Disable the interrupts for VF */
1022         ixgbevf_intr_disable(hw);
1023
1024         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1025         diag = hw->mac.ops.reset_hw(hw);
1026
1027         /*
1028          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1029          * the underlying PF driver has not assigned a MAC address to the VF.
1030          * In this case, assign a random MAC address.
1031          */
1032         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1033                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1034                 return (diag);
1035         }
1036
1037         /* negotiate mailbox API version to use with the PF. */
1038         ixgbevf_negotiate_api(hw);
1039
1040         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1041         ixgbevf_get_queues(hw, &tcs, &tc);
1042
1043         /* Allocate memory for storing MAC addresses */
1044         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1045                         hw->mac.num_rar_entries, 0);
1046         if (eth_dev->data->mac_addrs == NULL) {
1047                 PMD_INIT_LOG(ERR,
1048                         "Failed to allocate %u bytes needed to store "
1049                         "MAC addresses",
1050                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1051                 return -ENOMEM;
1052         }
1053
1054         /* Generate a random MAC address, if none was assigned by PF. */
1055         if (is_zero_ether_addr(perm_addr)) {
1056                 generate_random_mac_addr(perm_addr);
1057                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1058                 if (diag) {
1059                         rte_free(eth_dev->data->mac_addrs);
1060                         eth_dev->data->mac_addrs = NULL;
1061                         return diag;
1062                 }
1063                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1064                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1065                              "%02x:%02x:%02x:%02x:%02x:%02x",
1066                              perm_addr->addr_bytes[0],
1067                              perm_addr->addr_bytes[1],
1068                              perm_addr->addr_bytes[2],
1069                              perm_addr->addr_bytes[3],
1070                              perm_addr->addr_bytes[4],
1071                              perm_addr->addr_bytes[5]);
1072         }
1073
1074         /* Copy the permanent MAC address */
1075         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1076
1077         /* reset the hardware with the new settings */
1078         diag = hw->mac.ops.start_hw(hw);
1079         switch (diag) {
1080                 case  0:
1081                         break;
1082
1083                 default:
1084                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1085                         return (-EIO);
1086         }
1087
1088         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1089                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1090                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1091
1092         return 0;
1093 }
1094
1095 static struct eth_driver rte_ixgbe_pmd = {
1096         .pci_drv = {
1097                 .name = "rte_ixgbe_pmd",
1098                 .id_table = pci_id_ixgbe_map,
1099                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1100         },
1101         .eth_dev_init = eth_ixgbe_dev_init,
1102         .dev_private_size = sizeof(struct ixgbe_adapter),
1103 };
1104
1105 /*
1106  * virtual function driver struct
1107  */
1108 static struct eth_driver rte_ixgbevf_pmd = {
1109         .pci_drv = {
1110                 .name = "rte_ixgbevf_pmd",
1111                 .id_table = pci_id_ixgbevf_map,
1112                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1113         },
1114         .eth_dev_init = eth_ixgbevf_dev_init,
1115         .dev_private_size = sizeof(struct ixgbe_adapter),
1116 };
1117
1118 /*
1119  * Driver initialization routine.
1120  * Invoked once at EAL init time.
1121  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1122  */
1123 static int
1124 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1125 {
1126         PMD_INIT_FUNC_TRACE();
1127
1128         rte_eth_driver_register(&rte_ixgbe_pmd);
1129         return 0;
1130 }
1131
1132 /*
1133  * VF Driver initialization routine.
1134  * Invoked one at EAL init time.
1135  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1136  */
1137 static int
1138 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1139 {
1140         PMD_INIT_FUNC_TRACE();
1141
1142         rte_eth_driver_register(&rte_ixgbevf_pmd);
1143         return (0);
1144 }
1145
1146 static int
1147 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1148 {
1149         struct ixgbe_hw *hw =
1150                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151         struct ixgbe_vfta * shadow_vfta =
1152                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1153         uint32_t vfta;
1154         uint32_t vid_idx;
1155         uint32_t vid_bit;
1156
1157         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1158         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1159         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1160         if (on)
1161                 vfta |= vid_bit;
1162         else
1163                 vfta &= ~vid_bit;
1164         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1165
1166         /* update local VFTA copy */
1167         shadow_vfta->vfta[vid_idx] = vfta;
1168
1169         return 0;
1170 }
1171
1172 static void
1173 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1174 {
1175         if (on)
1176                 ixgbe_vlan_hw_strip_enable(dev, queue);
1177         else
1178                 ixgbe_vlan_hw_strip_disable(dev, queue);
1179 }
1180
1181 static void
1182 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1183 {
1184         struct ixgbe_hw *hw =
1185                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186
1187         /* Only the high 16-bits is valid */
1188         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1189 }
1190
1191 void
1192 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1193 {
1194         struct ixgbe_hw *hw =
1195                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196         uint32_t vlnctrl;
1197
1198         PMD_INIT_FUNC_TRACE();
1199
1200         /* Filter Table Disable */
1201         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1202         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1203
1204         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1205 }
1206
1207 void
1208 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1209 {
1210         struct ixgbe_hw *hw =
1211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212         struct ixgbe_vfta * shadow_vfta =
1213                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1214         uint32_t vlnctrl;
1215         uint16_t i;
1216
1217         PMD_INIT_FUNC_TRACE();
1218
1219         /* Filter Table Enable */
1220         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1221         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1222         vlnctrl |= IXGBE_VLNCTRL_VFE;
1223
1224         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1225
1226         /* write whatever is in local vfta copy */
1227         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1228                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1229 }
1230
1231 static void
1232 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1233 {
1234         struct ixgbe_hwstrip *hwstrip =
1235                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1236
1237         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1238                 return;
1239
1240         if (on)
1241                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1242         else
1243                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1244 }
1245
1246 static void
1247 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1248 {
1249         struct ixgbe_hw *hw =
1250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251         uint32_t ctrl;
1252
1253         PMD_INIT_FUNC_TRACE();
1254
1255         if (hw->mac.type == ixgbe_mac_82598EB) {
1256                 /* No queue level support */
1257                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1258                 return;
1259         }
1260         else {
1261                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1262                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1263                 ctrl &= ~IXGBE_RXDCTL_VME;
1264                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1265         }
1266         /* record those setting for HW strip per queue */
1267         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1268 }
1269
1270 static void
1271 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1272 {
1273         struct ixgbe_hw *hw =
1274                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275         uint32_t ctrl;
1276
1277         PMD_INIT_FUNC_TRACE();
1278
1279         if (hw->mac.type == ixgbe_mac_82598EB) {
1280                 /* No queue level supported */
1281                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1282                 return;
1283         }
1284         else {
1285                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1286                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1287                 ctrl |= IXGBE_RXDCTL_VME;
1288                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1289         }
1290         /* record those setting for HW strip per queue */
1291         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1292 }
1293
1294 void
1295 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1296 {
1297         struct ixgbe_hw *hw =
1298                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1299         uint32_t ctrl;
1300         uint16_t i;
1301
1302         PMD_INIT_FUNC_TRACE();
1303
1304         if (hw->mac.type == ixgbe_mac_82598EB) {
1305                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1306                 ctrl &= ~IXGBE_VLNCTRL_VME;
1307                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1308         }
1309         else {
1310                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1311                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1312                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1313                         ctrl &= ~IXGBE_RXDCTL_VME;
1314                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1315
1316                         /* record those setting for HW strip per queue */
1317                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1318                 }
1319         }
1320 }
1321
1322 void
1323 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1324 {
1325         struct ixgbe_hw *hw =
1326                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327         uint32_t ctrl;
1328         uint16_t i;
1329
1330         PMD_INIT_FUNC_TRACE();
1331
1332         if (hw->mac.type == ixgbe_mac_82598EB) {
1333                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1334                 ctrl |= IXGBE_VLNCTRL_VME;
1335                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1336         }
1337         else {
1338                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1339                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1340                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1341                         ctrl |= IXGBE_RXDCTL_VME;
1342                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1343
1344                         /* record those setting for HW strip per queue */
1345                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1346                 }
1347         }
1348 }
1349
1350 static void
1351 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1352 {
1353         struct ixgbe_hw *hw =
1354                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1355         uint32_t ctrl;
1356
1357         PMD_INIT_FUNC_TRACE();
1358
1359         /* DMATXCTRL: Geric Double VLAN Disable */
1360         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1361         ctrl &= ~IXGBE_DMATXCTL_GDV;
1362         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1363
1364         /* CTRL_EXT: Global Double VLAN Disable */
1365         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1366         ctrl &= ~IXGBE_EXTENDED_VLAN;
1367         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1368
1369 }
1370
1371 static void
1372 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1373 {
1374         struct ixgbe_hw *hw =
1375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         uint32_t ctrl;
1377
1378         PMD_INIT_FUNC_TRACE();
1379
1380         /* DMATXCTRL: Geric Double VLAN Enable */
1381         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1382         ctrl |= IXGBE_DMATXCTL_GDV;
1383         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1384
1385         /* CTRL_EXT: Global Double VLAN Enable */
1386         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1387         ctrl |= IXGBE_EXTENDED_VLAN;
1388         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1389
1390         /*
1391          * VET EXT field in the EXVET register = 0x8100 by default
1392          * So no need to change. Same to VT field of DMATXCTL register
1393          */
1394 }
1395
1396 static void
1397 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1398 {
1399         if(mask & ETH_VLAN_STRIP_MASK){
1400                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1401                         ixgbe_vlan_hw_strip_enable_all(dev);
1402                 else
1403                         ixgbe_vlan_hw_strip_disable_all(dev);
1404         }
1405
1406         if(mask & ETH_VLAN_FILTER_MASK){
1407                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1408                         ixgbe_vlan_hw_filter_enable(dev);
1409                 else
1410                         ixgbe_vlan_hw_filter_disable(dev);
1411         }
1412
1413         if(mask & ETH_VLAN_EXTEND_MASK){
1414                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1415                         ixgbe_vlan_hw_extend_enable(dev);
1416                 else
1417                         ixgbe_vlan_hw_extend_disable(dev);
1418         }
1419 }
1420
1421 static void
1422 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1423 {
1424         struct ixgbe_hw *hw =
1425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1427         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1428         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1429         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1430 }
1431
1432 static int
1433 ixgbe_dev_configure(struct rte_eth_dev *dev)
1434 {
1435         struct ixgbe_interrupt *intr =
1436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1437         struct ixgbe_adapter *adapter =
1438                 (struct ixgbe_adapter *)dev->data->dev_private;
1439
1440         PMD_INIT_FUNC_TRACE();
1441
1442         /* set flag to update link status after init */
1443         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1444
1445         /*
1446          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1447          * allocation or vector Rx preconditions we will reset it.
1448          */
1449         adapter->rx_bulk_alloc_allowed = true;
1450         adapter->rx_vec_allowed = true;
1451
1452         return 0;
1453 }
1454
1455 /*
1456  * Configure device link speed and setup link.
1457  * It returns 0 on success.
1458  */
1459 static int
1460 ixgbe_dev_start(struct rte_eth_dev *dev)
1461 {
1462         struct ixgbe_hw *hw =
1463                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464         struct ixgbe_vf_info *vfinfo =
1465                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1466         int err, link_up = 0, negotiate = 0;
1467         uint32_t speed = 0;
1468         int mask = 0;
1469         int status;
1470         uint16_t vf, idx;
1471
1472         PMD_INIT_FUNC_TRACE();
1473
1474         /* IXGBE devices don't support half duplex */
1475         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1476                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1477                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1478                              dev->data->dev_conf.link_duplex,
1479                              dev->data->port_id);
1480                 return -EINVAL;
1481         }
1482
1483         /* stop adapter */
1484         hw->adapter_stopped = FALSE;
1485         ixgbe_stop_adapter(hw);
1486
1487         /* reinitialize adapter
1488          * this calls reset and start */
1489         status = ixgbe_pf_reset_hw(hw);
1490         if (status != 0)
1491                 return -1;
1492         hw->mac.ops.start_hw(hw);
1493         hw->mac.get_link_status = true;
1494
1495         /* configure PF module if SRIOV enabled */
1496         ixgbe_pf_host_configure(dev);
1497
1498         /* initialize transmission unit */
1499         ixgbe_dev_tx_init(dev);
1500
1501         /* This can fail when allocating mbufs for descriptor rings */
1502         err = ixgbe_dev_rx_init(dev);
1503         if (err) {
1504                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1505                 goto error;
1506         }
1507
1508         err = ixgbe_dev_rxtx_start(dev);
1509         if (err < 0) {
1510                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1511                 goto error;
1512         }
1513
1514         /* Skip link setup if loopback mode is enabled for 82599. */
1515         if (hw->mac.type == ixgbe_mac_82599EB &&
1516                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1517                 goto skip_link_setup;
1518
1519         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1520                 err = hw->mac.ops.setup_sfp(hw);
1521                 if (err)
1522                         goto error;
1523         }
1524
1525         /* Turn on the laser */
1526         ixgbe_enable_tx_laser(hw);
1527
1528         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1529         if (err)
1530                 goto error;
1531         dev->data->dev_link.link_status = link_up;
1532
1533         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1534         if (err)
1535                 goto error;
1536
1537         switch(dev->data->dev_conf.link_speed) {
1538         case ETH_LINK_SPEED_AUTONEG:
1539                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1540                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1541                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1542                 break;
1543         case ETH_LINK_SPEED_100:
1544                 /*
1545                  * Invalid for 82598 but error will be detected by
1546                  * ixgbe_setup_link()
1547                  */
1548                 speed = IXGBE_LINK_SPEED_100_FULL;
1549                 break;
1550         case ETH_LINK_SPEED_1000:
1551                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1552                 break;
1553         case ETH_LINK_SPEED_10000:
1554                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1555                 break;
1556         default:
1557                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1558                              dev->data->dev_conf.link_speed,
1559                              dev->data->port_id);
1560                 goto error;
1561         }
1562
1563         err = ixgbe_setup_link(hw, speed, link_up);
1564         if (err)
1565                 goto error;
1566
1567 skip_link_setup:
1568
1569         /* check if lsc interrupt is enabled */
1570         if (dev->data->dev_conf.intr_conf.lsc != 0)
1571                 ixgbe_dev_lsc_interrupt_setup(dev);
1572
1573         /* resume enabled intr since hw reset */
1574         ixgbe_enable_intr(dev);
1575
1576         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1577                 ETH_VLAN_EXTEND_MASK;
1578         ixgbe_vlan_offload_set(dev, mask);
1579
1580         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1581                 /* Enable vlan filtering for VMDq */
1582                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1583         }
1584
1585         /* Configure DCB hw */
1586         ixgbe_configure_dcb(dev);
1587
1588         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1589                 err = ixgbe_fdir_configure(dev);
1590                 if (err)
1591                         goto error;
1592         }
1593
1594         /* Restore vf rate limit */
1595         if (vfinfo != NULL) {
1596                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1597                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1598                                 if (vfinfo[vf].tx_rate[idx] != 0)
1599                                         ixgbe_set_vf_rate_limit(dev, vf,
1600                                                 vfinfo[vf].tx_rate[idx],
1601                                                 1 << idx);
1602         }
1603
1604         ixgbe_restore_statistics_mapping(dev);
1605
1606         return (0);
1607
1608 error:
1609         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1610         ixgbe_dev_clear_queues(dev);
1611         return -EIO;
1612 }
1613
1614 /*
1615  * Stop device: disable rx and tx functions to allow for reconfiguring.
1616  */
1617 static void
1618 ixgbe_dev_stop(struct rte_eth_dev *dev)
1619 {
1620         struct rte_eth_link link;
1621         struct ixgbe_hw *hw =
1622                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         struct ixgbe_vf_info *vfinfo =
1624                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1625         struct ixgbe_filter_info *filter_info =
1626                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1627         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1628         int vf;
1629
1630         PMD_INIT_FUNC_TRACE();
1631
1632         /* disable interrupts */
1633         ixgbe_disable_intr(hw);
1634
1635         /* reset the NIC */
1636         ixgbe_pf_reset_hw(hw);
1637         hw->adapter_stopped = FALSE;
1638
1639         /* stop adapter */
1640         ixgbe_stop_adapter(hw);
1641
1642         for (vf = 0; vfinfo != NULL &&
1643                      vf < dev->pci_dev->max_vfs; vf++)
1644                 vfinfo[vf].clear_to_send = false;
1645
1646         /* Turn off the laser */
1647         ixgbe_disable_tx_laser(hw);
1648
1649         ixgbe_dev_clear_queues(dev);
1650
1651         /* Clear stored conf */
1652         dev->data->scattered_rx = 0;
1653         dev->data->lro = 0;
1654
1655         /* Clear recorded link status */
1656         memset(&link, 0, sizeof(link));
1657         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1658
1659         /* Remove all ntuple filters of the device */
1660         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1661              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1662                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1663                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1664                              p_5tuple, entries);
1665                 rte_free(p_5tuple);
1666         }
1667         memset(filter_info->fivetuple_mask, 0,
1668                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1669
1670 }
1671
1672 /*
1673  * Set device link up: enable tx laser.
1674  */
1675 static int
1676 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1677 {
1678         struct ixgbe_hw *hw =
1679                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680         if (hw->mac.type == ixgbe_mac_82599EB) {
1681 #ifdef RTE_NIC_BYPASS
1682                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1683                         /* Not suported in bypass mode */
1684                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1685                                      "by device id 0x%x", hw->device_id);
1686                         return -ENOTSUP;
1687                 }
1688 #endif
1689                 /* Turn on the laser */
1690                 ixgbe_enable_tx_laser(hw);
1691                 return 0;
1692         }
1693
1694         PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1695                      hw->device_id);
1696         return -ENOTSUP;
1697 }
1698
1699 /*
1700  * Set device link down: disable tx laser.
1701  */
1702 static int
1703 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1704 {
1705         struct ixgbe_hw *hw =
1706                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707         if (hw->mac.type == ixgbe_mac_82599EB) {
1708 #ifdef RTE_NIC_BYPASS
1709                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1710                         /* Not suported in bypass mode */
1711                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1712                                      "by device id 0x%x", hw->device_id);
1713                         return -ENOTSUP;
1714                 }
1715 #endif
1716                 /* Turn off the laser */
1717                 ixgbe_disable_tx_laser(hw);
1718                 return 0;
1719         }
1720
1721         PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1722                      hw->device_id);
1723         return -ENOTSUP;
1724 }
1725
1726 /*
1727  * Reest and stop device.
1728  */
1729 static void
1730 ixgbe_dev_close(struct rte_eth_dev *dev)
1731 {
1732         struct ixgbe_hw *hw =
1733                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1734
1735         PMD_INIT_FUNC_TRACE();
1736
1737         ixgbe_pf_reset_hw(hw);
1738
1739         ixgbe_dev_stop(dev);
1740         hw->adapter_stopped = 1;
1741
1742         ixgbe_disable_pcie_master(hw);
1743
1744         /* reprogram the RAR[0] in case user changed it. */
1745         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1746 }
1747
1748 /*
1749  * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1750  */
1751 static void
1752 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1753 {
1754         struct ixgbe_hw *hw =
1755                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756         struct ixgbe_hw_stats *hw_stats =
1757                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1758         uint32_t bprc, lxon, lxoff, total;
1759         uint64_t total_missed_rx, total_qbrc, total_qprc;
1760         unsigned i;
1761
1762         total_missed_rx = 0;
1763         total_qbrc = 0;
1764         total_qprc = 0;
1765
1766         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1767         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1768         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1769         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1770
1771         for (i = 0; i < 8; i++) {
1772                 uint32_t mp;
1773                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1774                 /* global total per queue */
1775                 hw_stats->mpc[i] += mp;
1776                 /* Running comprehensive total for stats display */
1777                 total_missed_rx += hw_stats->mpc[i];
1778                 if (hw->mac.type == ixgbe_mac_82598EB)
1779                         hw_stats->rnbc[i] +=
1780                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1781                 hw_stats->pxontxc[i] +=
1782                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1783                 hw_stats->pxonrxc[i] +=
1784                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1785                 hw_stats->pxofftxc[i] +=
1786                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1787                 hw_stats->pxoffrxc[i] +=
1788                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1789                 hw_stats->pxon2offc[i] +=
1790                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1791         }
1792         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1793                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1794                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1795                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1796                 hw_stats->qbrc[i] +=
1797                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1798                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1799                 hw_stats->qbtc[i] +=
1800                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1801                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1802
1803                 total_qprc += hw_stats->qprc[i];
1804                 total_qbrc += hw_stats->qbrc[i];
1805         }
1806         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1807         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1808         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1809
1810         /* Note that gprc counts missed packets */
1811         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1812
1813         if (hw->mac.type != ixgbe_mac_82598EB) {
1814                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1815                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1816                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1817                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1818                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1819                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1820                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1821                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1822         } else {
1823                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1824                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1825                 /* 82598 only has a counter in the high register */
1826                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1827                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1828                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1829         }
1830
1831         /*
1832          * Workaround: mprc hardware is incorrectly counting
1833          * broadcasts, so for now we subtract those.
1834          */
1835         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1836         hw_stats->bprc += bprc;
1837         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1838         if (hw->mac.type == ixgbe_mac_82598EB)
1839                 hw_stats->mprc -= bprc;
1840
1841         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1842         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1843         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1844         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1845         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1846         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1847
1848         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1849         hw_stats->lxontxc += lxon;
1850         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1851         hw_stats->lxofftxc += lxoff;
1852         total = lxon + lxoff;
1853
1854         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1855         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1856         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1857         hw_stats->gptc -= total;
1858         hw_stats->mptc -= total;
1859         hw_stats->ptc64 -= total;
1860         hw_stats->gotc -= total * ETHER_MIN_LEN;
1861
1862         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1863         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1864         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1865         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1866         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1867         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1868         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1869         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1870         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1871         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1872         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1873         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1874         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1875         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1876         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1877         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1878         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1879         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1880         /* Only read FCOE on 82599 */
1881         if (hw->mac.type != ixgbe_mac_82598EB) {
1882                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1883                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1884                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1885                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1886                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1887         }
1888
1889         if (stats == NULL)
1890                 return;
1891
1892         /* Fill out the rte_eth_stats statistics structure */
1893         stats->ipackets = total_qprc;
1894         stats->ibytes = total_qbrc;
1895         stats->opackets = hw_stats->gptc;
1896         stats->obytes = hw_stats->gotc;
1897         stats->imcasts = hw_stats->mprc;
1898
1899         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1900                 stats->q_ipackets[i] = hw_stats->qprc[i];
1901                 stats->q_opackets[i] = hw_stats->qptc[i];
1902                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1903                 stats->q_obytes[i] = hw_stats->qbtc[i];
1904                 stats->q_errors[i] = hw_stats->qprdc[i];
1905         }
1906
1907         /* Rx Errors */
1908         stats->ibadcrc  = hw_stats->crcerrs;
1909         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1910         stats->imissed  = total_missed_rx;
1911         stats->ierrors  = stats->ibadcrc +
1912                           stats->ibadlen +
1913                           stats->imissed +
1914                           hw_stats->illerrc + hw_stats->errbc;
1915
1916         /* Tx Errors */
1917         stats->oerrors  = 0;
1918
1919         /* XON/XOFF pause frames */
1920         stats->tx_pause_xon  = hw_stats->lxontxc;
1921         stats->rx_pause_xon  = hw_stats->lxonrxc;
1922         stats->tx_pause_xoff = hw_stats->lxofftxc;
1923         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1924
1925         /* Flow Director Stats registers */
1926         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1927         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1928         stats->fdirmatch = hw_stats->fdirmatch;
1929         stats->fdirmiss = hw_stats->fdirmiss;
1930 }
1931
1932 static void
1933 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1934 {
1935         struct ixgbe_hw_stats *stats =
1936                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1937
1938         /* HW registers are cleared on read */
1939         ixgbe_dev_stats_get(dev, NULL);
1940
1941         /* Reset software totals */
1942         memset(stats, 0, sizeof(*stats));
1943 }
1944
1945 static void
1946 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1947 {
1948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1950                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1951
1952         /* Good Rx packet, include VF loopback */
1953         UPDATE_VF_STAT(IXGBE_VFGPRC,
1954             hw_stats->last_vfgprc, hw_stats->vfgprc);
1955
1956         /* Good Rx octets, include VF loopback */
1957         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1958             hw_stats->last_vfgorc, hw_stats->vfgorc);
1959
1960         /* Good Tx packet, include VF loopback */
1961         UPDATE_VF_STAT(IXGBE_VFGPTC,
1962             hw_stats->last_vfgptc, hw_stats->vfgptc);
1963
1964         /* Good Tx octets, include VF loopback */
1965         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1966             hw_stats->last_vfgotc, hw_stats->vfgotc);
1967
1968         /* Rx Multicst Packet */
1969         UPDATE_VF_STAT(IXGBE_VFMPRC,
1970             hw_stats->last_vfmprc, hw_stats->vfmprc);
1971
1972         if (stats == NULL)
1973                 return;
1974
1975         stats->ipackets = hw_stats->vfgprc;
1976         stats->ibytes = hw_stats->vfgorc;
1977         stats->opackets = hw_stats->vfgptc;
1978         stats->obytes = hw_stats->vfgotc;
1979         stats->imcasts = hw_stats->vfmprc;
1980 }
1981
1982 static void
1983 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1984 {
1985         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1986                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1987
1988         /* Sync HW register to the last stats */
1989         ixgbevf_dev_stats_get(dev, NULL);
1990
1991         /* reset HW current stats*/
1992         hw_stats->vfgprc = 0;
1993         hw_stats->vfgorc = 0;
1994         hw_stats->vfgptc = 0;
1995         hw_stats->vfgotc = 0;
1996         hw_stats->vfmprc = 0;
1997
1998 }
1999
2000 static void
2001 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2002 {
2003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004
2005         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2006         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2007         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2008         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2009         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2010         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2011         dev_info->max_vfs = dev->pci_dev->max_vfs;
2012         if (hw->mac.type == ixgbe_mac_82598EB)
2013                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2014         else
2015                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2016         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2017         dev_info->rx_offload_capa =
2018                 DEV_RX_OFFLOAD_VLAN_STRIP |
2019                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2020                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2021                 DEV_RX_OFFLOAD_TCP_CKSUM;
2022
2023         /*
2024          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2025          * mode.
2026          */
2027         if ((hw->mac.type == ixgbe_mac_82599EB ||
2028              hw->mac.type == ixgbe_mac_X540) &&
2029             !RTE_ETH_DEV_SRIOV(dev).active)
2030                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2031
2032         dev_info->tx_offload_capa =
2033                 DEV_TX_OFFLOAD_VLAN_INSERT |
2034                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2035                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2036                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2037                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2038                 DEV_TX_OFFLOAD_TCP_TSO;
2039
2040         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2041                 .rx_thresh = {
2042                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2043                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2044                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2045                 },
2046                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2047                 .rx_drop_en = 0,
2048         };
2049
2050         dev_info->default_txconf = (struct rte_eth_txconf) {
2051                 .tx_thresh = {
2052                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2053                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2054                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2055                 },
2056                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2057                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2058                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2059                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2060         };
2061         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2062         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2063 }
2064
2065 static void
2066 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2067                      struct rte_eth_dev_info *dev_info)
2068 {
2069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2070
2071         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2072         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2073         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2074         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2075         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2076         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2077         dev_info->max_vfs = dev->pci_dev->max_vfs;
2078         if (hw->mac.type == ixgbe_mac_82598EB)
2079                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2080         else
2081                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2082         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2083                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2084                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2085                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2086         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2087                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2088                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2089                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2090                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2091
2092         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2093                 .rx_thresh = {
2094                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2095                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2096                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2097                 },
2098                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2099                 .rx_drop_en = 0,
2100         };
2101
2102         dev_info->default_txconf = (struct rte_eth_txconf) {
2103                 .tx_thresh = {
2104                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2105                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2106                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2107                 },
2108                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2109                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2110                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2111                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2112         };
2113 }
2114
2115 /* return 0 means link status changed, -1 means not changed */
2116 static int
2117 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2118 {
2119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         struct rte_eth_link link, old;
2121         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2122         int link_up;
2123         int diag;
2124
2125         link.link_status = 0;
2126         link.link_speed = 0;
2127         link.link_duplex = 0;
2128         memset(&old, 0, sizeof(old));
2129         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2130
2131         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2132         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2133                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2134         else
2135                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2136         if (diag != 0) {
2137                 link.link_speed = ETH_LINK_SPEED_100;
2138                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2139                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2140                 if (link.link_status == old.link_status)
2141                         return -1;
2142                 return 0;
2143         }
2144
2145         if (link_speed == IXGBE_LINK_SPEED_UNKNOWN &&
2146             !hw->mac.get_link_status) {
2147                 memcpy(&link, &old, sizeof(link));
2148                 return -1;
2149         }
2150
2151         if (link_up == 0) {
2152                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2153                 if (link.link_status == old.link_status)
2154                         return -1;
2155                 return 0;
2156         }
2157         link.link_status = 1;
2158         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2159
2160         switch (link_speed) {
2161         default:
2162         case IXGBE_LINK_SPEED_UNKNOWN:
2163                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2164                 link.link_speed = ETH_LINK_SPEED_100;
2165                 break;
2166
2167         case IXGBE_LINK_SPEED_100_FULL:
2168                 link.link_speed = ETH_LINK_SPEED_100;
2169                 break;
2170
2171         case IXGBE_LINK_SPEED_1GB_FULL:
2172                 link.link_speed = ETH_LINK_SPEED_1000;
2173                 break;
2174
2175         case IXGBE_LINK_SPEED_10GB_FULL:
2176                 link.link_speed = ETH_LINK_SPEED_10000;
2177                 break;
2178         }
2179         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2180
2181         if (link.link_status == old.link_status)
2182                 return -1;
2183
2184         return 0;
2185 }
2186
2187 static void
2188 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2189 {
2190         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2191         uint32_t fctrl;
2192
2193         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2194         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2195         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2196 }
2197
2198 static void
2199 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2200 {
2201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         uint32_t fctrl;
2203
2204         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2205         fctrl &= (~IXGBE_FCTRL_UPE);
2206         if (dev->data->all_multicast == 1)
2207                 fctrl |= IXGBE_FCTRL_MPE;
2208         else
2209                 fctrl &= (~IXGBE_FCTRL_MPE);
2210         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2211 }
2212
2213 static void
2214 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2215 {
2216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         uint32_t fctrl;
2218
2219         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2220         fctrl |= IXGBE_FCTRL_MPE;
2221         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2222 }
2223
2224 static void
2225 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2226 {
2227         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2228         uint32_t fctrl;
2229
2230         if (dev->data->promiscuous == 1)
2231                 return; /* must remain in all_multicast mode */
2232
2233         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2234         fctrl &= (~IXGBE_FCTRL_MPE);
2235         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2236 }
2237
2238 /**
2239  * It clears the interrupt causes and enables the interrupt.
2240  * It will be called once only during nic initialized.
2241  *
2242  * @param dev
2243  *  Pointer to struct rte_eth_dev.
2244  *
2245  * @return
2246  *  - On success, zero.
2247  *  - On failure, a negative value.
2248  */
2249 static int
2250 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2251 {
2252         struct ixgbe_interrupt *intr =
2253                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2254
2255         ixgbe_dev_link_status_print(dev);
2256         intr->mask |= IXGBE_EICR_LSC;
2257
2258         return 0;
2259 }
2260
2261 /*
2262  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2263  *
2264  * @param dev
2265  *  Pointer to struct rte_eth_dev.
2266  *
2267  * @return
2268  *  - On success, zero.
2269  *  - On failure, a negative value.
2270  */
2271 static int
2272 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2273 {
2274         uint32_t eicr;
2275         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276         struct ixgbe_interrupt *intr =
2277                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2278
2279         /* clear all cause mask */
2280         ixgbe_disable_intr(hw);
2281
2282         /* read-on-clear nic registers here */
2283         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2284         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2285
2286         intr->flags = 0;
2287         if (eicr & IXGBE_EICR_LSC) {
2288                 /* set flag for async link update */
2289                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2290         }
2291
2292         if (eicr & IXGBE_EICR_MAILBOX)
2293                 intr->flags |= IXGBE_FLAG_MAILBOX;
2294
2295         return 0;
2296 }
2297
2298 /**
2299  * It gets and then prints the link status.
2300  *
2301  * @param dev
2302  *  Pointer to struct rte_eth_dev.
2303  *
2304  * @return
2305  *  - On success, zero.
2306  *  - On failure, a negative value.
2307  */
2308 static void
2309 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2310 {
2311         struct rte_eth_link link;
2312
2313         memset(&link, 0, sizeof(link));
2314         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2315         if (link.link_status) {
2316                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2317                                         (int)(dev->data->port_id),
2318                                         (unsigned)link.link_speed,
2319                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2320                                         "full-duplex" : "half-duplex");
2321         } else {
2322                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2323                                 (int)(dev->data->port_id));
2324         }
2325         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2326                                 dev->pci_dev->addr.domain,
2327                                 dev->pci_dev->addr.bus,
2328                                 dev->pci_dev->addr.devid,
2329                                 dev->pci_dev->addr.function);
2330 }
2331
2332 /*
2333  * It executes link_update after knowing an interrupt occurred.
2334  *
2335  * @param dev
2336  *  Pointer to struct rte_eth_dev.
2337  *
2338  * @return
2339  *  - On success, zero.
2340  *  - On failure, a negative value.
2341  */
2342 static int
2343 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2344 {
2345         struct ixgbe_interrupt *intr =
2346                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2347         int64_t timeout;
2348         struct rte_eth_link link;
2349         int intr_enable_delay = false;
2350
2351         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2352
2353         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2354                 ixgbe_pf_mbx_process(dev);
2355                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2356         }
2357
2358         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2359                 /* get the link status before link update, for predicting later */
2360                 memset(&link, 0, sizeof(link));
2361                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2362
2363                 ixgbe_dev_link_update(dev, 0);
2364
2365                 /* likely to up */
2366                 if (!link.link_status)
2367                         /* handle it 1 sec later, wait it being stable */
2368                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2369                 /* likely to down */
2370                 else
2371                         /* handle it 4 sec later, wait it being stable */
2372                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2373
2374                 ixgbe_dev_link_status_print(dev);
2375
2376                 intr_enable_delay = true;
2377         }
2378
2379         if (intr_enable_delay) {
2380                 if (rte_eal_alarm_set(timeout * 1000,
2381                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2382                         PMD_DRV_LOG(ERR, "Error setting alarm");
2383         } else {
2384                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2385                 ixgbe_enable_intr(dev);
2386                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2387         }
2388
2389
2390         return 0;
2391 }
2392
2393 /**
2394  * Interrupt handler which shall be registered for alarm callback for delayed
2395  * handling specific interrupt to wait for the stable nic state. As the
2396  * NIC interrupt state is not stable for ixgbe after link is just down,
2397  * it needs to wait 4 seconds to get the stable status.
2398  *
2399  * @param handle
2400  *  Pointer to interrupt handle.
2401  * @param param
2402  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2403  *
2404  * @return
2405  *  void
2406  */
2407 static void
2408 ixgbe_dev_interrupt_delayed_handler(void *param)
2409 {
2410         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2411         struct ixgbe_interrupt *intr =
2412                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2413         struct ixgbe_hw *hw =
2414                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2415         uint32_t eicr;
2416
2417         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2418         if (eicr & IXGBE_EICR_MAILBOX)
2419                 ixgbe_pf_mbx_process(dev);
2420
2421         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2422                 ixgbe_dev_link_update(dev, 0);
2423                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2424                 ixgbe_dev_link_status_print(dev);
2425                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2426         }
2427
2428         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2429         ixgbe_enable_intr(dev);
2430         rte_intr_enable(&(dev->pci_dev->intr_handle));
2431 }
2432
2433 /**
2434  * Interrupt handler triggered by NIC  for handling
2435  * specific interrupt.
2436  *
2437  * @param handle
2438  *  Pointer to interrupt handle.
2439  * @param param
2440  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2441  *
2442  * @return
2443  *  void
2444  */
2445 static void
2446 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2447                                                         void *param)
2448 {
2449         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2450         ixgbe_dev_interrupt_get_status(dev);
2451         ixgbe_dev_interrupt_action(dev);
2452 }
2453
2454 static int
2455 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2456 {
2457         struct ixgbe_hw *hw;
2458
2459         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2461 }
2462
2463 static int
2464 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2465 {
2466         struct ixgbe_hw *hw;
2467
2468         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2470 }
2471
2472 static int
2473 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2474 {
2475         struct ixgbe_hw *hw;
2476         uint32_t mflcn_reg;
2477         uint32_t fccfg_reg;
2478         int rx_pause;
2479         int tx_pause;
2480
2481         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482
2483         fc_conf->pause_time = hw->fc.pause_time;
2484         fc_conf->high_water = hw->fc.high_water[0];
2485         fc_conf->low_water = hw->fc.low_water[0];
2486         fc_conf->send_xon = hw->fc.send_xon;
2487         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2488
2489         /*
2490          * Return rx_pause status according to actual setting of
2491          * MFLCN register.
2492          */
2493         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2494         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2495                 rx_pause = 1;
2496         else
2497                 rx_pause = 0;
2498
2499         /*
2500          * Return tx_pause status according to actual setting of
2501          * FCCFG register.
2502          */
2503         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2504         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2505                 tx_pause = 1;
2506         else
2507                 tx_pause = 0;
2508
2509         if (rx_pause && tx_pause)
2510                 fc_conf->mode = RTE_FC_FULL;
2511         else if (rx_pause)
2512                 fc_conf->mode = RTE_FC_RX_PAUSE;
2513         else if (tx_pause)
2514                 fc_conf->mode = RTE_FC_TX_PAUSE;
2515         else
2516                 fc_conf->mode = RTE_FC_NONE;
2517
2518         return 0;
2519 }
2520
2521 static int
2522 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2523 {
2524         struct ixgbe_hw *hw;
2525         int err;
2526         uint32_t rx_buf_size;
2527         uint32_t max_high_water;
2528         uint32_t mflcn;
2529         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2530                 ixgbe_fc_none,
2531                 ixgbe_fc_rx_pause,
2532                 ixgbe_fc_tx_pause,
2533                 ixgbe_fc_full
2534         };
2535
2536         PMD_INIT_FUNC_TRACE();
2537
2538         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2540                 return -ENOTSUP;
2541         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2542         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2543
2544         /*
2545          * At least reserve one Ethernet frame for watermark
2546          * high_water/low_water in kilo bytes for ixgbe
2547          */
2548         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2549         if ((fc_conf->high_water > max_high_water) ||
2550                 (fc_conf->high_water < fc_conf->low_water)) {
2551                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2552                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2553                 return (-EINVAL);
2554         }
2555
2556         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2557         hw->fc.pause_time     = fc_conf->pause_time;
2558         hw->fc.high_water[0]  = fc_conf->high_water;
2559         hw->fc.low_water[0]   = fc_conf->low_water;
2560         hw->fc.send_xon       = fc_conf->send_xon;
2561
2562         err = ixgbe_fc_enable(hw);
2563
2564         /* Not negotiated is not an error case */
2565         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2566
2567                 /* check if we want to forward MAC frames - driver doesn't have native
2568                  * capability to do that, so we'll write the registers ourselves */
2569
2570                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2571
2572                 /* set or clear MFLCN.PMCF bit depending on configuration */
2573                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2574                         mflcn |= IXGBE_MFLCN_PMCF;
2575                 else
2576                         mflcn &= ~IXGBE_MFLCN_PMCF;
2577
2578                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2579                 IXGBE_WRITE_FLUSH(hw);
2580
2581                 return 0;
2582         }
2583
2584         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2585         return -EIO;
2586 }
2587
2588 /**
2589  *  ixgbe_pfc_enable_generic - Enable flow control
2590  *  @hw: pointer to hardware structure
2591  *  @tc_num: traffic class number
2592  *  Enable flow control according to the current settings.
2593  */
2594 static int
2595 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2596 {
2597         int ret_val = 0;
2598         uint32_t mflcn_reg, fccfg_reg;
2599         uint32_t reg;
2600         uint32_t fcrtl, fcrth;
2601         uint8_t i;
2602         uint8_t nb_rx_en;
2603
2604         /* Validate the water mark configuration */
2605         if (!hw->fc.pause_time) {
2606                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2607                 goto out;
2608         }
2609
2610         /* Low water mark of zero causes XOFF floods */
2611         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2612                  /* High/Low water can not be 0 */
2613                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2614                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2615                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2616                         goto out;
2617                 }
2618
2619                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2620                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2621                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2622                         goto out;
2623                 }
2624         }
2625         /* Negotiate the fc mode to use */
2626         ixgbe_fc_autoneg(hw);
2627
2628         /* Disable any previous flow control settings */
2629         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2630         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2631
2632         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2633         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2634
2635         switch (hw->fc.current_mode) {
2636         case ixgbe_fc_none:
2637                 /*
2638                  * If the count of enabled RX Priority Flow control >1,
2639                  * and the TX pause can not be disabled
2640                  */
2641                 nb_rx_en = 0;
2642                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2643                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2644                         if (reg & IXGBE_FCRTH_FCEN)
2645                                 nb_rx_en++;
2646                 }
2647                 if (nb_rx_en > 1)
2648                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2649                 break;
2650         case ixgbe_fc_rx_pause:
2651                 /*
2652                  * Rx Flow control is enabled and Tx Flow control is
2653                  * disabled by software override. Since there really
2654                  * isn't a way to advertise that we are capable of RX
2655                  * Pause ONLY, we will advertise that we support both
2656                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2657                  * disable the adapter's ability to send PAUSE frames.
2658                  */
2659                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2660                 /*
2661                  * If the count of enabled RX Priority Flow control >1,
2662                  * and the TX pause can not be disabled
2663                  */
2664                 nb_rx_en = 0;
2665                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2666                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2667                         if (reg & IXGBE_FCRTH_FCEN)
2668                                 nb_rx_en++;
2669                 }
2670                 if (nb_rx_en > 1)
2671                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2672                 break;
2673         case ixgbe_fc_tx_pause:
2674                 /*
2675                  * Tx Flow control is enabled, and Rx Flow control is
2676                  * disabled by software override.
2677                  */
2678                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2679                 break;
2680         case ixgbe_fc_full:
2681                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2682                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2683                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2684                 break;
2685         default:
2686                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2687                 ret_val = IXGBE_ERR_CONFIG;
2688                 goto out;
2689                 break;
2690         }
2691
2692         /* Set 802.3x based flow control settings. */
2693         mflcn_reg |= IXGBE_MFLCN_DPF;
2694         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2695         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2696
2697         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2698         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2699                 hw->fc.high_water[tc_num]) {
2700                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2701                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2702                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2703         } else {
2704                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2705                 /*
2706                  * In order to prevent Tx hangs when the internal Tx
2707                  * switch is enabled we must set the high water mark
2708                  * to the maximum FCRTH value.  This allows the Tx
2709                  * switch to function even under heavy Rx workloads.
2710                  */
2711                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2712         }
2713         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2714
2715         /* Configure pause time (2 TCs per register) */
2716         reg = hw->fc.pause_time * 0x00010001;
2717         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2718                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2719
2720         /* Configure flow control refresh threshold value */
2721         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2722
2723 out:
2724         return ret_val;
2725 }
2726
2727 static int
2728 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2729 {
2730         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2731         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2732
2733         if(hw->mac.type != ixgbe_mac_82598EB) {
2734                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2735         }
2736         return ret_val;
2737 }
2738
2739 static int
2740 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2741 {
2742         int err;
2743         uint32_t rx_buf_size;
2744         uint32_t max_high_water;
2745         uint8_t tc_num;
2746         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2747         struct ixgbe_hw *hw =
2748                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2749         struct ixgbe_dcb_config *dcb_config =
2750                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2751
2752         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2753                 ixgbe_fc_none,
2754                 ixgbe_fc_rx_pause,
2755                 ixgbe_fc_tx_pause,
2756                 ixgbe_fc_full
2757         };
2758
2759         PMD_INIT_FUNC_TRACE();
2760
2761         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2762         tc_num = map[pfc_conf->priority];
2763         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2764         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2765         /*
2766          * At least reserve one Ethernet frame for watermark
2767          * high_water/low_water in kilo bytes for ixgbe
2768          */
2769         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2770         if ((pfc_conf->fc.high_water > max_high_water) ||
2771             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2772                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2773                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2774                 return (-EINVAL);
2775         }
2776
2777         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2778         hw->fc.pause_time = pfc_conf->fc.pause_time;
2779         hw->fc.send_xon = pfc_conf->fc.send_xon;
2780         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2781         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2782
2783         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2784
2785         /* Not negotiated is not an error case */
2786         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2787                 return 0;
2788
2789         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2790         return -EIO;
2791 }
2792
2793 static int
2794 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2795                           struct rte_eth_rss_reta_entry64 *reta_conf,
2796                           uint16_t reta_size)
2797 {
2798         uint8_t i, j, mask;
2799         uint32_t reta, r;
2800         uint16_t idx, shift;
2801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2802
2803         PMD_INIT_FUNC_TRACE();
2804         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2805                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2806                         "(%d) doesn't match the number hardware can supported "
2807                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2808                 return -EINVAL;
2809         }
2810
2811         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2812                 idx = i / RTE_RETA_GROUP_SIZE;
2813                 shift = i % RTE_RETA_GROUP_SIZE;
2814                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2815                                                 IXGBE_4_BIT_MASK);
2816                 if (!mask)
2817                         continue;
2818                 if (mask == IXGBE_4_BIT_MASK)
2819                         r = 0;
2820                 else
2821                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2822                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2823                         if (mask & (0x1 << j))
2824                                 reta |= reta_conf[idx].reta[shift + j] <<
2825                                                         (CHAR_BIT * j);
2826                         else
2827                                 reta |= r & (IXGBE_8_BIT_MASK <<
2828                                                 (CHAR_BIT * j));
2829                 }
2830                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2831         }
2832
2833         return 0;
2834 }
2835
2836 static int
2837 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2838                          struct rte_eth_rss_reta_entry64 *reta_conf,
2839                          uint16_t reta_size)
2840 {
2841         uint8_t i, j, mask;
2842         uint32_t reta;
2843         uint16_t idx, shift;
2844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845
2846         PMD_INIT_FUNC_TRACE();
2847         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2848                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2849                         "(%d) doesn't match the number hardware can supported "
2850                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2851                 return -EINVAL;
2852         }
2853
2854         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2855                 idx = i / RTE_RETA_GROUP_SIZE;
2856                 shift = i % RTE_RETA_GROUP_SIZE;
2857                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2858                                                 IXGBE_4_BIT_MASK);
2859                 if (!mask)
2860                         continue;
2861
2862                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2863                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2864                         if (mask & (0x1 << j))
2865                                 reta_conf[idx].reta[shift + j] =
2866                                         ((reta >> (CHAR_BIT * j)) &
2867                                                 IXGBE_8_BIT_MASK);
2868                 }
2869         }
2870
2871         return 0;
2872 }
2873
2874 static void
2875 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2876                                 uint32_t index, uint32_t pool)
2877 {
2878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879         uint32_t enable_addr = 1;
2880
2881         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2882 }
2883
2884 static void
2885 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2886 {
2887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2888
2889         ixgbe_clear_rar(hw, index);
2890 }
2891
2892 static int
2893 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2894 {
2895         uint32_t hlreg0;
2896         uint32_t maxfrs;
2897         struct ixgbe_hw *hw;
2898         struct rte_eth_dev_info dev_info;
2899         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2900
2901         ixgbe_dev_info_get(dev, &dev_info);
2902
2903         /* check that mtu is within the allowed range */
2904         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2905                 return -EINVAL;
2906
2907         /* refuse mtu that requires the support of scattered packets when this
2908          * feature has not been enabled before. */
2909         if (!dev->data->scattered_rx &&
2910             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2911              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2912                 return -EINVAL;
2913
2914         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2915         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2916
2917         /* switch to jumbo mode if needed */
2918         if (frame_size > ETHER_MAX_LEN) {
2919                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2920                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2921         } else {
2922                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2923                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2924         }
2925         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2926
2927         /* update max frame size */
2928         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2929
2930         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2931         maxfrs &= 0x0000FFFF;
2932         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2933         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2934
2935         return 0;
2936 }
2937
2938 /*
2939  * Virtual Function operations
2940  */
2941 static void
2942 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2943 {
2944         PMD_INIT_FUNC_TRACE();
2945
2946         /* Clear interrupt mask to stop from interrupts being generated */
2947         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2948
2949         IXGBE_WRITE_FLUSH(hw);
2950 }
2951
2952 static int
2953 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2954 {
2955         struct rte_eth_conf* conf = &dev->data->dev_conf;
2956         struct ixgbe_adapter *adapter =
2957                         (struct ixgbe_adapter *)dev->data->dev_private;
2958
2959         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2960                      dev->data->port_id);
2961
2962         /*
2963          * VF has no ability to enable/disable HW CRC
2964          * Keep the persistent behavior the same as Host PF
2965          */
2966 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2967         if (!conf->rxmode.hw_strip_crc) {
2968                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2969                 conf->rxmode.hw_strip_crc = 1;
2970         }
2971 #else
2972         if (conf->rxmode.hw_strip_crc) {
2973                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2974                 conf->rxmode.hw_strip_crc = 0;
2975         }
2976 #endif
2977
2978         /*
2979          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2980          * allocation or vector Rx preconditions we will reset it.
2981          */
2982         adapter->rx_bulk_alloc_allowed = true;
2983         adapter->rx_vec_allowed = true;
2984
2985         return 0;
2986 }
2987
2988 static int
2989 ixgbevf_dev_start(struct rte_eth_dev *dev)
2990 {
2991         struct ixgbe_hw *hw =
2992                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993         int err, mask = 0;
2994
2995         PMD_INIT_FUNC_TRACE();
2996
2997         hw->mac.ops.reset_hw(hw);
2998         hw->mac.get_link_status = true;
2999
3000         /* negotiate mailbox API version to use with the PF. */
3001         ixgbevf_negotiate_api(hw);
3002
3003         ixgbevf_dev_tx_init(dev);
3004
3005         /* This can fail when allocating mbufs for descriptor rings */
3006         err = ixgbevf_dev_rx_init(dev);
3007         if (err) {
3008                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3009                 ixgbe_dev_clear_queues(dev);
3010                 return err;
3011         }
3012
3013         /* Set vfta */
3014         ixgbevf_set_vfta_all(dev,1);
3015
3016         /* Set HW strip */
3017         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3018                 ETH_VLAN_EXTEND_MASK;
3019         ixgbevf_vlan_offload_set(dev, mask);
3020
3021         ixgbevf_dev_rxtx_start(dev);
3022
3023         return 0;
3024 }
3025
3026 static void
3027 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3028 {
3029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3030
3031         PMD_INIT_FUNC_TRACE();
3032
3033         hw->adapter_stopped = TRUE;
3034         ixgbe_stop_adapter(hw);
3035
3036         /*
3037           * Clear what we set, but we still keep shadow_vfta to
3038           * restore after device starts
3039           */
3040         ixgbevf_set_vfta_all(dev,0);
3041
3042         /* Clear stored conf */
3043         dev->data->scattered_rx = 0;
3044
3045         ixgbe_dev_clear_queues(dev);
3046 }
3047
3048 static void
3049 ixgbevf_dev_close(struct rte_eth_dev *dev)
3050 {
3051         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3052
3053         PMD_INIT_FUNC_TRACE();
3054
3055         ixgbe_reset_hw(hw);
3056
3057         ixgbevf_dev_stop(dev);
3058
3059         /* reprogram the RAR[0] in case user changed it. */
3060         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3061 }
3062
3063 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3064 {
3065         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066         struct ixgbe_vfta * shadow_vfta =
3067                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3068         int i = 0, j = 0, vfta = 0, mask = 1;
3069
3070         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3071                 vfta = shadow_vfta->vfta[i];
3072                 if(vfta){
3073                         mask = 1;
3074                         for (j = 0; j < 32; j++){
3075                                 if(vfta & mask)
3076                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3077                                 mask<<=1;
3078                         }
3079                 }
3080         }
3081
3082 }
3083
3084 static int
3085 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3086 {
3087         struct ixgbe_hw *hw =
3088                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3089         struct ixgbe_vfta * shadow_vfta =
3090                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3091         uint32_t vid_idx = 0;
3092         uint32_t vid_bit = 0;
3093         int ret = 0;
3094
3095         PMD_INIT_FUNC_TRACE();
3096
3097         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3098         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3099         if(ret){
3100                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3101                 return ret;
3102         }
3103         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3104         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3105
3106         /* Save what we set and retore it after device reset */
3107         if (on)
3108                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3109         else
3110                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3111
3112         return 0;
3113 }
3114
3115 static void
3116 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3117 {
3118         struct ixgbe_hw *hw =
3119                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120         uint32_t ctrl;
3121
3122         PMD_INIT_FUNC_TRACE();
3123
3124         if(queue >= hw->mac.max_rx_queues)
3125                 return;
3126
3127         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3128         if(on)
3129                 ctrl |= IXGBE_RXDCTL_VME;
3130         else
3131                 ctrl &= ~IXGBE_RXDCTL_VME;
3132         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3133
3134         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3135 }
3136
3137 static void
3138 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3139 {
3140         struct ixgbe_hw *hw =
3141                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3142         uint16_t i;
3143         int on = 0;
3144
3145         /* VF function only support hw strip feature, others are not support */
3146         if(mask & ETH_VLAN_STRIP_MASK){
3147                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3148
3149                 for(i=0; i < hw->mac.max_rx_queues; i++)
3150                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3151         }
3152 }
3153
3154 static int
3155 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3156 {
3157         uint32_t reg_val;
3158
3159         /* we only need to do this if VMDq is enabled */
3160         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3161         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3162                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3163                 return (-1);
3164         }
3165
3166         return 0;
3167 }
3168
3169 static uint32_t
3170 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3171 {
3172         uint32_t vector = 0;
3173         switch (hw->mac.mc_filter_type) {
3174         case 0:   /* use bits [47:36] of the address */
3175                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3176                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3177                 break;
3178         case 1:   /* use bits [46:35] of the address */
3179                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3180                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3181                 break;
3182         case 2:   /* use bits [45:34] of the address */
3183                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3184                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3185                 break;
3186         case 3:   /* use bits [43:32] of the address */
3187                 vector = ((uc_addr->addr_bytes[4]) |
3188                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3189                 break;
3190         default:  /* Invalid mc_filter_type */
3191                 break;
3192         }
3193
3194         /* vector can only be 12-bits or boundary will be exceeded */
3195         vector &= 0xFFF;
3196         return vector;
3197 }
3198
3199 static int
3200 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3201                                uint8_t on)
3202 {
3203         uint32_t vector;
3204         uint32_t uta_idx;
3205         uint32_t reg_val;
3206         uint32_t uta_shift;
3207         uint32_t rc;
3208         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3209         const uint32_t ixgbe_uta_bit_shift = 5;
3210         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3211         const uint32_t bit1 = 0x1;
3212
3213         struct ixgbe_hw *hw =
3214                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3215         struct ixgbe_uta_info *uta_info =
3216                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3217
3218         /* The UTA table only exists on 82599 hardware and newer */
3219         if (hw->mac.type < ixgbe_mac_82599EB)
3220                 return (-ENOTSUP);
3221
3222         vector = ixgbe_uta_vector(hw,mac_addr);
3223         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3224         uta_shift = vector & ixgbe_uta_bit_mask;
3225
3226         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3227         if(rc == on)
3228                 return 0;
3229
3230         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3231         if (on) {
3232                 uta_info->uta_in_use++;
3233                 reg_val |= (bit1 << uta_shift);
3234                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3235         } else {
3236                 uta_info->uta_in_use--;
3237                 reg_val &= ~(bit1 << uta_shift);
3238                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3239         }
3240
3241         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3242
3243         if (uta_info->uta_in_use > 0)
3244                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3245                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3246         else
3247                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3248
3249         return 0;
3250 }
3251
3252 static int
3253 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3254 {
3255         int i;
3256         struct ixgbe_hw *hw =
3257                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3258         struct ixgbe_uta_info *uta_info =
3259                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3260
3261         /* The UTA table only exists on 82599 hardware and newer */
3262         if (hw->mac.type < ixgbe_mac_82599EB)
3263                 return (-ENOTSUP);
3264
3265         if(on) {
3266                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3267                         uta_info->uta_shadow[i] = ~0;
3268                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3269                 }
3270         } else {
3271                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3272                         uta_info->uta_shadow[i] = 0;
3273                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3274                 }
3275         }
3276         return 0;
3277
3278 }
3279
3280 uint32_t
3281 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3282 {
3283         uint32_t new_val = orig_val;
3284
3285         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3286                 new_val |= IXGBE_VMOLR_AUPE;
3287         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3288                 new_val |= IXGBE_VMOLR_ROMPE;
3289         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3290                 new_val |= IXGBE_VMOLR_ROPE;
3291         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3292                 new_val |= IXGBE_VMOLR_BAM;
3293         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3294                 new_val |= IXGBE_VMOLR_MPE;
3295
3296         return new_val;
3297 }
3298
3299 static int
3300 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3301                                uint16_t rx_mask, uint8_t on)
3302 {
3303         int val = 0;
3304
3305         struct ixgbe_hw *hw =
3306                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3308
3309         if (hw->mac.type == ixgbe_mac_82598EB) {
3310                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3311                              " on 82599 hardware and newer");
3312                 return (-ENOTSUP);
3313         }
3314         if (ixgbe_vmdq_mode_check(hw) < 0)
3315                 return (-ENOTSUP);
3316
3317         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3318
3319         if (on)
3320                 vmolr |= val;
3321         else
3322                 vmolr &= ~val;
3323
3324         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3325
3326         return 0;
3327 }
3328
3329 static int
3330 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3331 {
3332         uint32_t reg,addr;
3333         uint32_t val;
3334         const uint8_t bit1 = 0x1;
3335
3336         struct ixgbe_hw *hw =
3337                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3338
3339         if (ixgbe_vmdq_mode_check(hw) < 0)
3340                 return (-ENOTSUP);
3341
3342         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3343         reg = IXGBE_READ_REG(hw, addr);
3344         val = bit1 << pool;
3345
3346         if (on)
3347                 reg |= val;
3348         else
3349                 reg &= ~val;
3350
3351         IXGBE_WRITE_REG(hw, addr,reg);
3352
3353         return 0;
3354 }
3355
3356 static int
3357 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3358 {
3359         uint32_t reg,addr;
3360         uint32_t val;
3361         const uint8_t bit1 = 0x1;
3362
3363         struct ixgbe_hw *hw =
3364                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3365
3366         if (ixgbe_vmdq_mode_check(hw) < 0)
3367                 return (-ENOTSUP);
3368
3369         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3370         reg = IXGBE_READ_REG(hw, addr);
3371         val = bit1 << pool;
3372
3373         if (on)
3374                 reg |= val;
3375         else
3376                 reg &= ~val;
3377
3378         IXGBE_WRITE_REG(hw, addr,reg);
3379
3380         return 0;
3381 }
3382
3383 static int
3384 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3385                         uint64_t pool_mask, uint8_t vlan_on)
3386 {
3387         int ret = 0;
3388         uint16_t pool_idx;
3389         struct ixgbe_hw *hw =
3390                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3391
3392         if (ixgbe_vmdq_mode_check(hw) < 0)
3393                 return (-ENOTSUP);
3394         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3395                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3396                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3397                         if (ret < 0)
3398                                 return ret;
3399         }
3400
3401         return ret;
3402 }
3403
3404 static int
3405 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3406                         struct rte_eth_vmdq_mirror_conf *mirror_conf,
3407                         uint8_t rule_id, uint8_t on)
3408 {
3409         uint32_t mr_ctl,vlvf;
3410         uint32_t mp_lsb = 0;
3411         uint32_t mv_msb = 0;
3412         uint32_t mv_lsb = 0;
3413         uint32_t mp_msb = 0;
3414         uint8_t i = 0;
3415         int reg_index = 0;
3416         uint64_t vlan_mask = 0;
3417
3418         const uint8_t pool_mask_offset = 32;
3419         const uint8_t vlan_mask_offset = 32;
3420         const uint8_t dst_pool_offset = 8;
3421         const uint8_t rule_mr_offset  = 4;
3422         const uint8_t mirror_rule_mask= 0x0F;
3423
3424         struct ixgbe_mirror_info *mr_info =
3425                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3426         struct ixgbe_hw *hw =
3427                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428
3429         if (ixgbe_vmdq_mode_check(hw) < 0)
3430                 return (-ENOTSUP);
3431
3432         /* Check if vlan mask is valid */
3433         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3434                 if (mirror_conf->vlan.vlan_mask == 0)
3435                         return (-EINVAL);
3436         }
3437
3438         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3439         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3440                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3441                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3442                                 /* search vlan id related pool vlan filter index */
3443                                 reg_index = ixgbe_find_vlvf_slot(hw,
3444                                                 mirror_conf->vlan.vlan_id[i]);
3445                                 if(reg_index < 0)
3446                                         return (-EINVAL);
3447                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3448                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3449                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3450                                                 == mirror_conf->vlan.vlan_id[i]))
3451                                         vlan_mask |= (1ULL << reg_index);
3452                                 else
3453                                         return (-EINVAL);
3454                         }
3455                 }
3456
3457                 if (on) {
3458                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3459                         mv_msb = vlan_mask >> vlan_mask_offset;
3460
3461                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3462                                                 mirror_conf->vlan.vlan_mask;
3463                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3464                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3465                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3466                                                 mirror_conf->vlan.vlan_id[i];
3467                         }
3468                 } else {
3469                         mv_lsb = 0;
3470                         mv_msb = 0;
3471                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3472                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3473                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3474                 }
3475         }
3476
3477         /*
3478          * if enable pool mirror, write related pool mask register,if disable
3479          * pool mirror, clear PFMRVM register
3480          */
3481         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3482                 if (on) {
3483                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3484                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3485                         mr_info->mr_conf[rule_id].pool_mask =
3486                                         mirror_conf->pool_mask;
3487
3488                 } else {
3489                         mp_lsb = 0;
3490                         mp_msb = 0;
3491                         mr_info->mr_conf[rule_id].pool_mask = 0;
3492                 }
3493         }
3494
3495         /* read  mirror control register and recalculate it */
3496         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3497
3498         if (on) {
3499                 mr_ctl |= mirror_conf->rule_type_mask;
3500                 mr_ctl &= mirror_rule_mask;
3501                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3502         } else
3503                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3504
3505         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3506         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3507
3508         /* write mirrror control  register */
3509         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3510
3511         /* write pool mirrror control  register */
3512         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3513                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3514                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3515                                 mp_msb);
3516         }
3517         /* write VLAN mirrror control  register */
3518         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3519                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3520                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3521                                 mv_msb);
3522         }
3523
3524         return 0;
3525 }
3526
3527 static int
3528 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3529 {
3530         int mr_ctl = 0;
3531         uint32_t lsb_val = 0;
3532         uint32_t msb_val = 0;
3533         const uint8_t rule_mr_offset = 4;
3534
3535         struct ixgbe_hw *hw =
3536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3537         struct ixgbe_mirror_info *mr_info =
3538                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3539
3540         if (ixgbe_vmdq_mode_check(hw) < 0)
3541                 return (-ENOTSUP);
3542
3543         memset(&mr_info->mr_conf[rule_id], 0,
3544                 sizeof(struct rte_eth_vmdq_mirror_conf));
3545
3546         /* clear PFVMCTL register */
3547         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3548
3549         /* clear pool mask register */
3550         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3551         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3552
3553         /* clear vlan mask register */
3554         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3555         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3556
3557         return 0;
3558 }
3559
3560 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3561         uint16_t queue_idx, uint16_t tx_rate)
3562 {
3563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564         uint32_t rf_dec, rf_int;
3565         uint32_t bcnrc_val;
3566         uint16_t link_speed = dev->data->dev_link.link_speed;
3567
3568         if (queue_idx >= hw->mac.max_tx_queues)
3569                 return -EINVAL;
3570
3571         if (tx_rate != 0) {
3572                 /* Calculate the rate factor values to set */
3573                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3574                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3575                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3576
3577                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3578                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3579                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3580                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3581         } else {
3582                 bcnrc_val = 0;
3583         }
3584
3585         /*
3586          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3587          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3588          * set as 0x4.
3589          */
3590         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3591                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3592                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3593                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3594                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3595         else
3596                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3597                         IXGBE_MMW_SIZE_DEFAULT);
3598
3599         /* Set RTTBCNRC of queue X */
3600         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3601         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3602         IXGBE_WRITE_FLUSH(hw);
3603
3604         return 0;
3605 }
3606
3607 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3608         uint16_t tx_rate, uint64_t q_msk)
3609 {
3610         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3611         struct ixgbe_vf_info *vfinfo =
3612                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3613         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3614         uint32_t queue_stride =
3615                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3616         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3617         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3618         uint16_t total_rate = 0;
3619
3620         if (queue_end >= hw->mac.max_tx_queues)
3621                 return -EINVAL;
3622
3623         if (vfinfo != NULL) {
3624                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3625                         if (vf_idx == vf)
3626                                 continue;
3627                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3628                                 idx++)
3629                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3630                 }
3631         } else
3632                 return -EINVAL;
3633
3634         /* Store tx_rate for this vf. */
3635         for (idx = 0; idx < nb_q_per_pool; idx++) {
3636                 if (((uint64_t)0x1 << idx) & q_msk) {
3637                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3638                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3639                         total_rate += tx_rate;
3640                 }
3641         }
3642
3643         if (total_rate > dev->data->dev_link.link_speed) {
3644                 /*
3645                  * Reset stored TX rate of the VF if it causes exceed
3646                  * link speed.
3647                  */
3648                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3649                 return -EINVAL;
3650         }
3651
3652         /* Set RTTBCNRC of each queue/pool for vf X  */
3653         for (; queue_idx <= queue_end; queue_idx++) {
3654                 if (0x1 & q_msk)
3655                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3656                 q_msk = q_msk >> 1;
3657         }
3658
3659         return 0;
3660 }
3661
3662 static void
3663 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3664                      __attribute__((unused)) uint32_t index,
3665                      __attribute__((unused)) uint32_t pool)
3666 {
3667         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668         int diag;
3669
3670         /*
3671          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3672          * operation. Trap this case to avoid exhausting the [very limited]
3673          * set of PF resources used to store VF MAC addresses.
3674          */
3675         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3676                 return;
3677         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3678         if (diag == 0)
3679                 return;
3680         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3681 }
3682
3683 static void
3684 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3685 {
3686         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3687         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3688         struct ether_addr *mac_addr;
3689         uint32_t i;
3690         int diag;
3691
3692         /*
3693          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3694          * not support the deletion of a given MAC address.
3695          * Instead, it imposes to delete all MAC addresses, then to add again
3696          * all MAC addresses with the exception of the one to be deleted.
3697          */
3698         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3699
3700         /*
3701          * Add again all MAC addresses, with the exception of the deleted one
3702          * and of the permanent MAC address.
3703          */
3704         for (i = 0, mac_addr = dev->data->mac_addrs;
3705              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3706                 /* Skip the deleted MAC address */
3707                 if (i == index)
3708                         continue;
3709                 /* Skip NULL MAC addresses */
3710                 if (is_zero_ether_addr(mac_addr))
3711                         continue;
3712                 /* Skip the permanent MAC address */
3713                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3714                         continue;
3715                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3716                 if (diag != 0)
3717                         PMD_DRV_LOG(ERR,
3718                                     "Adding again MAC address "
3719                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3720                                     "diag=%d",
3721                                     mac_addr->addr_bytes[0],
3722                                     mac_addr->addr_bytes[1],
3723                                     mac_addr->addr_bytes[2],
3724                                     mac_addr->addr_bytes[3],
3725                                     mac_addr->addr_bytes[4],
3726                                     mac_addr->addr_bytes[5],
3727                                     diag);
3728         }
3729 }
3730
3731 #define MAC_TYPE_FILTER_SUP(type)    do {\
3732         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3733                 (type) != ixgbe_mac_X550)\
3734                 return -ENOTSUP;\
3735 } while (0)
3736
3737 static int
3738 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3739                         struct rte_eth_syn_filter *filter,
3740                         bool add)
3741 {
3742         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3743         uint32_t synqf;
3744
3745         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3746                 return -EINVAL;
3747
3748         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3749
3750         if (add) {
3751                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3752                         return -EINVAL;
3753                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3754                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3755
3756                 if (filter->hig_pri)
3757                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3758                 else
3759                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3760         } else {
3761                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3762                         return -ENOENT;
3763                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3764         }
3765         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3766         IXGBE_WRITE_FLUSH(hw);
3767         return 0;
3768 }
3769
3770 static int
3771 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3772                         struct rte_eth_syn_filter *filter)
3773 {
3774         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3775         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3776
3777         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3778                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3779                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3780                 return 0;
3781         }
3782         return -ENOENT;
3783 }
3784
3785 static int
3786 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3787                         enum rte_filter_op filter_op,
3788                         void *arg)
3789 {
3790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791         int ret;
3792
3793         MAC_TYPE_FILTER_SUP(hw->mac.type);
3794
3795         if (filter_op == RTE_ETH_FILTER_NOP)
3796                 return 0;
3797
3798         if (arg == NULL) {
3799                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3800                             filter_op);
3801                 return -EINVAL;
3802         }
3803
3804         switch (filter_op) {
3805         case RTE_ETH_FILTER_ADD:
3806                 ret = ixgbe_syn_filter_set(dev,
3807                                 (struct rte_eth_syn_filter *)arg,
3808                                 TRUE);
3809                 break;
3810         case RTE_ETH_FILTER_DELETE:
3811                 ret = ixgbe_syn_filter_set(dev,
3812                                 (struct rte_eth_syn_filter *)arg,
3813                                 FALSE);
3814                 break;
3815         case RTE_ETH_FILTER_GET:
3816                 ret = ixgbe_syn_filter_get(dev,
3817                                 (struct rte_eth_syn_filter *)arg);
3818                 break;
3819         default:
3820                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3821                 ret = -EINVAL;
3822                 break;
3823         }
3824
3825         return ret;
3826 }
3827
3828
3829 static inline enum ixgbe_5tuple_protocol
3830 convert_protocol_type(uint8_t protocol_value)
3831 {
3832         if (protocol_value == IPPROTO_TCP)
3833                 return IXGBE_FILTER_PROTOCOL_TCP;
3834         else if (protocol_value == IPPROTO_UDP)
3835                 return IXGBE_FILTER_PROTOCOL_UDP;
3836         else if (protocol_value == IPPROTO_SCTP)
3837                 return IXGBE_FILTER_PROTOCOL_SCTP;
3838         else
3839                 return IXGBE_FILTER_PROTOCOL_NONE;
3840 }
3841
3842 /*
3843  * add a 5tuple filter
3844  *
3845  * @param
3846  * dev: Pointer to struct rte_eth_dev.
3847  * index: the index the filter allocates.
3848  * filter: ponter to the filter that will be added.
3849  * rx_queue: the queue id the filter assigned to.
3850  *
3851  * @return
3852  *    - On success, zero.
3853  *    - On failure, a negative value.
3854  */
3855 static int
3856 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3857                         struct ixgbe_5tuple_filter *filter)
3858 {
3859         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3860         struct ixgbe_filter_info *filter_info =
3861                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3862         int i, idx, shift;
3863         uint32_t ftqf, sdpqf;
3864         uint32_t l34timir = 0;
3865         uint8_t mask = 0xff;
3866
3867         /*
3868          * look for an unused 5tuple filter index,
3869          * and insert the filter to list.
3870          */
3871         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3872                 idx = i / (sizeof(uint32_t) * NBBY);
3873                 shift = i % (sizeof(uint32_t) * NBBY);
3874                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3875                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3876                         filter->index = i;
3877                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3878                                           filter,
3879                                           entries);
3880                         break;
3881                 }
3882         }
3883         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3884                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3885                 return -ENOSYS;
3886         }
3887
3888         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3889                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3890         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3891
3892         ftqf = (uint32_t)(filter->filter_info.proto &
3893                 IXGBE_FTQF_PROTOCOL_MASK);
3894         ftqf |= (uint32_t)((filter->filter_info.priority &
3895                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3896         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3897                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3898         if (filter->filter_info.dst_ip_mask == 0)
3899                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3900         if (filter->filter_info.src_port_mask == 0)
3901                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3902         if (filter->filter_info.dst_port_mask == 0)
3903                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3904         if (filter->filter_info.proto_mask == 0)
3905                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3906         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3907         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3908         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3909
3910         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3911         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3912         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3913         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3914
3915         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3916         l34timir |= (uint32_t)(filter->queue <<
3917                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3918         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3919         return 0;
3920 }
3921
3922 /*
3923  * remove a 5tuple filter
3924  *
3925  * @param
3926  * dev: Pointer to struct rte_eth_dev.
3927  * filter: the pointer of the filter will be removed.
3928  */
3929 static void
3930 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3931                         struct ixgbe_5tuple_filter *filter)
3932 {
3933         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934         struct ixgbe_filter_info *filter_info =
3935                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3936         uint16_t index = filter->index;
3937
3938         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3939                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3940         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3941         rte_free(filter);
3942
3943         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3944         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3945         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3946         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3947         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3948 }
3949
3950 static int
3951 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3952 {
3953         struct ixgbe_hw *hw;
3954         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3955
3956         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957
3958         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3959                 return -EINVAL;
3960
3961         /* refuse mtu that requires the support of scattered packets when this
3962          * feature has not been enabled before. */
3963         if (!dev->data->scattered_rx &&
3964             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3965              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3966                 return -EINVAL;
3967
3968         /*
3969          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3970          * request of the version 2.0 of the mailbox API.
3971          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3972          * of the mailbox API.
3973          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3974          * prior to 3.11.33 which contains the following change:
3975          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3976          */
3977         ixgbevf_rlpml_set_vf(hw, max_frame);
3978
3979         /* update max frame size */
3980         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3981         return 0;
3982 }
3983
3984 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
3985         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
3986                 return -ENOTSUP;\
3987 } while (0)
3988
3989 static inline struct ixgbe_5tuple_filter *
3990 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
3991                         struct ixgbe_5tuple_filter_info *key)
3992 {
3993         struct ixgbe_5tuple_filter *it;
3994
3995         TAILQ_FOREACH(it, filter_list, entries) {
3996                 if (memcmp(key, &it->filter_info,
3997                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
3998                         return it;
3999                 }
4000         }
4001         return NULL;
4002 }
4003
4004 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4005 static inline int
4006 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4007                         struct ixgbe_5tuple_filter_info *filter_info)
4008 {
4009         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4010                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4011                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4012                 return -EINVAL;
4013
4014         switch (filter->dst_ip_mask) {
4015         case UINT32_MAX:
4016                 filter_info->dst_ip_mask = 0;
4017                 filter_info->dst_ip = filter->dst_ip;
4018                 break;
4019         case 0:
4020                 filter_info->dst_ip_mask = 1;
4021                 break;
4022         default:
4023                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4024                 return -EINVAL;
4025         }
4026
4027         switch (filter->src_ip_mask) {
4028         case UINT32_MAX:
4029                 filter_info->src_ip_mask = 0;
4030                 filter_info->src_ip = filter->src_ip;
4031                 break;
4032         case 0:
4033                 filter_info->src_ip_mask = 1;
4034                 break;
4035         default:
4036                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4037                 return -EINVAL;
4038         }
4039
4040         switch (filter->dst_port_mask) {
4041         case UINT16_MAX:
4042                 filter_info->dst_port_mask = 0;
4043                 filter_info->dst_port = filter->dst_port;
4044                 break;
4045         case 0:
4046                 filter_info->dst_port_mask = 1;
4047                 break;
4048         default:
4049                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4050                 return -EINVAL;
4051         }
4052
4053         switch (filter->src_port_mask) {
4054         case UINT16_MAX:
4055                 filter_info->src_port_mask = 0;
4056                 filter_info->src_port = filter->src_port;
4057                 break;
4058         case 0:
4059                 filter_info->src_port_mask = 1;
4060                 break;
4061         default:
4062                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4063                 return -EINVAL;
4064         }
4065
4066         switch (filter->proto_mask) {
4067         case UINT8_MAX:
4068                 filter_info->proto_mask = 0;
4069                 filter_info->proto =
4070                         convert_protocol_type(filter->proto);
4071                 break;
4072         case 0:
4073                 filter_info->proto_mask = 1;
4074                 break;
4075         default:
4076                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4077                 return -EINVAL;
4078         }
4079
4080         filter_info->priority = (uint8_t)filter->priority;
4081         return 0;
4082 }
4083
4084 /*
4085  * add or delete a ntuple filter
4086  *
4087  * @param
4088  * dev: Pointer to struct rte_eth_dev.
4089  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4090  * add: if true, add filter, if false, remove filter
4091  *
4092  * @return
4093  *    - On success, zero.
4094  *    - On failure, a negative value.
4095  */
4096 static int
4097 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4098                         struct rte_eth_ntuple_filter *ntuple_filter,
4099                         bool add)
4100 {
4101         struct ixgbe_filter_info *filter_info =
4102                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4103         struct ixgbe_5tuple_filter_info filter_5tuple;
4104         struct ixgbe_5tuple_filter *filter;
4105         int ret;
4106
4107         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4108                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4109                 return -EINVAL;
4110         }
4111
4112         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4113         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4114         if (ret < 0)
4115                 return ret;
4116
4117         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4118                                          &filter_5tuple);
4119         if (filter != NULL && add) {
4120                 PMD_DRV_LOG(ERR, "filter exists.");
4121                 return -EEXIST;
4122         }
4123         if (filter == NULL && !add) {
4124                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4125                 return -ENOENT;
4126         }
4127
4128         if (add) {
4129                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4130                                 sizeof(struct ixgbe_5tuple_filter), 0);
4131                 if (filter == NULL)
4132                         return -ENOMEM;
4133                 (void)rte_memcpy(&filter->filter_info,
4134                                  &filter_5tuple,
4135                                  sizeof(struct ixgbe_5tuple_filter_info));
4136                 filter->queue = ntuple_filter->queue;
4137                 ret = ixgbe_add_5tuple_filter(dev, filter);
4138                 if (ret < 0) {
4139                         rte_free(filter);
4140                         return ret;
4141                 }
4142         } else
4143                 ixgbe_remove_5tuple_filter(dev, filter);
4144
4145         return 0;
4146 }
4147
4148 /*
4149  * get a ntuple filter
4150  *
4151  * @param
4152  * dev: Pointer to struct rte_eth_dev.
4153  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4154  *
4155  * @return
4156  *    - On success, zero.
4157  *    - On failure, a negative value.
4158  */
4159 static int
4160 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4161                         struct rte_eth_ntuple_filter *ntuple_filter)
4162 {
4163         struct ixgbe_filter_info *filter_info =
4164                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4165         struct ixgbe_5tuple_filter_info filter_5tuple;
4166         struct ixgbe_5tuple_filter *filter;
4167         int ret;
4168
4169         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4170                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4171                 return -EINVAL;
4172         }
4173
4174         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4175         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4176         if (ret < 0)
4177                 return ret;
4178
4179         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4180                                          &filter_5tuple);
4181         if (filter == NULL) {
4182                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4183                 return -ENOENT;
4184         }
4185         ntuple_filter->queue = filter->queue;
4186         return 0;
4187 }
4188
4189 /*
4190  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4191  * @dev: pointer to rte_eth_dev structure
4192  * @filter_op:operation will be taken.
4193  * @arg: a pointer to specific structure corresponding to the filter_op
4194  *
4195  * @return
4196  *    - On success, zero.
4197  *    - On failure, a negative value.
4198  */
4199 static int
4200 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4201                                 enum rte_filter_op filter_op,
4202                                 void *arg)
4203 {
4204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4205         int ret;
4206
4207         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4208
4209         if (filter_op == RTE_ETH_FILTER_NOP)
4210                 return 0;
4211
4212         if (arg == NULL) {
4213                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4214                             filter_op);
4215                 return -EINVAL;
4216         }
4217
4218         switch (filter_op) {
4219         case RTE_ETH_FILTER_ADD:
4220                 ret = ixgbe_add_del_ntuple_filter(dev,
4221                         (struct rte_eth_ntuple_filter *)arg,
4222                         TRUE);
4223                 break;
4224         case RTE_ETH_FILTER_DELETE:
4225                 ret = ixgbe_add_del_ntuple_filter(dev,
4226                         (struct rte_eth_ntuple_filter *)arg,
4227                         FALSE);
4228                 break;
4229         case RTE_ETH_FILTER_GET:
4230                 ret = ixgbe_get_ntuple_filter(dev,
4231                         (struct rte_eth_ntuple_filter *)arg);
4232                 break;
4233         default:
4234                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4235                 ret = -EINVAL;
4236                 break;
4237         }
4238         return ret;
4239 }
4240
4241 static inline int
4242 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4243                         uint16_t ethertype)
4244 {
4245         int i;
4246
4247         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4248                 if (filter_info->ethertype_filters[i] == ethertype &&
4249                     (filter_info->ethertype_mask & (1 << i)))
4250                         return i;
4251         }
4252         return -1;
4253 }
4254
4255 static inline int
4256 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4257                         uint16_t ethertype)
4258 {
4259         int i;
4260
4261         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4262                 if (!(filter_info->ethertype_mask & (1 << i))) {
4263                         filter_info->ethertype_mask |= 1 << i;
4264                         filter_info->ethertype_filters[i] = ethertype;
4265                         return i;
4266                 }
4267         }
4268         return -1;
4269 }
4270
4271 static inline int
4272 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4273                         uint8_t idx)
4274 {
4275         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4276                 return -1;
4277         filter_info->ethertype_mask &= ~(1 << idx);
4278         filter_info->ethertype_filters[idx] = 0;
4279         return idx;
4280 }
4281
4282 static int
4283 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4284                         struct rte_eth_ethertype_filter *filter,
4285                         bool add)
4286 {
4287         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288         struct ixgbe_filter_info *filter_info =
4289                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4290         uint32_t etqf = 0;
4291         uint32_t etqs = 0;
4292         int ret;
4293
4294         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4295                 return -EINVAL;
4296
4297         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4298                 filter->ether_type == ETHER_TYPE_IPv6) {
4299                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4300                         " ethertype filter.", filter->ether_type);
4301                 return -EINVAL;
4302         }
4303
4304         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4305                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4306                 return -EINVAL;
4307         }
4308         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4309                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4310                 return -EINVAL;
4311         }
4312
4313         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4314         if (ret >= 0 && add) {
4315                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4316                             filter->ether_type);
4317                 return -EEXIST;
4318         }
4319         if (ret < 0 && !add) {
4320                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4321                             filter->ether_type);
4322                 return -ENOENT;
4323         }
4324
4325         if (add) {
4326                 ret = ixgbe_ethertype_filter_insert(filter_info,
4327                         filter->ether_type);
4328                 if (ret < 0) {
4329                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4330                         return -ENOSYS;
4331                 }
4332                 etqf = IXGBE_ETQF_FILTER_EN;
4333                 etqf |= (uint32_t)filter->ether_type;
4334                 etqs |= (uint32_t)((filter->queue <<
4335                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4336                                     IXGBE_ETQS_RX_QUEUE);
4337                 etqs |= IXGBE_ETQS_QUEUE_EN;
4338         } else {
4339                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4340                 if (ret < 0)
4341                         return -ENOSYS;
4342         }
4343         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4344         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4345         IXGBE_WRITE_FLUSH(hw);
4346
4347         return 0;
4348 }
4349
4350 static int
4351 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4352                         struct rte_eth_ethertype_filter *filter)
4353 {
4354         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4355         struct ixgbe_filter_info *filter_info =
4356                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4357         uint32_t etqf, etqs;
4358         int ret;
4359
4360         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4361         if (ret < 0) {
4362                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4363                             filter->ether_type);
4364                 return -ENOENT;
4365         }
4366
4367         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4368         if (etqf & IXGBE_ETQF_FILTER_EN) {
4369                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4370                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4371                 filter->flags = 0;
4372                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4373                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4374                 return 0;
4375         }
4376         return -ENOENT;
4377 }
4378
4379 /*
4380  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4381  * @dev: pointer to rte_eth_dev structure
4382  * @filter_op:operation will be taken.
4383  * @arg: a pointer to specific structure corresponding to the filter_op
4384  */
4385 static int
4386 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4387                                 enum rte_filter_op filter_op,
4388                                 void *arg)
4389 {
4390         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4391         int ret;
4392
4393         MAC_TYPE_FILTER_SUP(hw->mac.type);
4394
4395         if (filter_op == RTE_ETH_FILTER_NOP)
4396                 return 0;
4397
4398         if (arg == NULL) {
4399                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4400                             filter_op);
4401                 return -EINVAL;
4402         }
4403
4404         switch (filter_op) {
4405         case RTE_ETH_FILTER_ADD:
4406                 ret = ixgbe_add_del_ethertype_filter(dev,
4407                         (struct rte_eth_ethertype_filter *)arg,
4408                         TRUE);
4409                 break;
4410         case RTE_ETH_FILTER_DELETE:
4411                 ret = ixgbe_add_del_ethertype_filter(dev,
4412                         (struct rte_eth_ethertype_filter *)arg,
4413                         FALSE);
4414                 break;
4415         case RTE_ETH_FILTER_GET:
4416                 ret = ixgbe_get_ethertype_filter(dev,
4417                         (struct rte_eth_ethertype_filter *)arg);
4418                 break;
4419         default:
4420                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4421                 ret = -EINVAL;
4422                 break;
4423         }
4424         return ret;
4425 }
4426
4427 static int
4428 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4429                      enum rte_filter_type filter_type,
4430                      enum rte_filter_op filter_op,
4431                      void *arg)
4432 {
4433         int ret = -EINVAL;
4434
4435         switch (filter_type) {
4436         case RTE_ETH_FILTER_NTUPLE:
4437                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4438                 break;
4439         case RTE_ETH_FILTER_ETHERTYPE:
4440                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4441                 break;
4442         case RTE_ETH_FILTER_SYN:
4443                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4444                 break;
4445         case RTE_ETH_FILTER_FDIR:
4446                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4447                 break;
4448         default:
4449                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4450                                                         filter_type);
4451                 break;
4452         }
4453
4454         return ret;
4455 }
4456
4457 static u8 *
4458 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4459                         u8 **mc_addr_ptr, u32 *vmdq)
4460 {
4461         u8 *mc_addr;
4462
4463         *vmdq = 0;
4464         mc_addr = *mc_addr_ptr;
4465         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4466         return mc_addr;
4467 }
4468
4469 static int
4470 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4471                            struct ether_addr *mc_addr_set,
4472                            uint32_t nb_mc_addr)
4473 {
4474         struct ixgbe_hw *hw;
4475         u8 *mc_addr_list;
4476
4477         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478         mc_addr_list = (u8 *)mc_addr_set;
4479         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4480                                          ixgbe_dev_addr_list_itr, TRUE);
4481 }
4482
4483 static struct rte_driver rte_ixgbe_driver = {
4484         .type = PMD_PDEV,
4485         .init = rte_ixgbe_pmd_init,
4486 };
4487
4488 static struct rte_driver rte_ixgbevf_driver = {
4489         .type = PMD_PDEV,
4490         .init = rte_ixgbevf_pmd_init,
4491 };
4492
4493 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4494 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);