drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void ixgbe_dev_setup_link_alarm_handler(void *param);
 233
 234 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 235                         struct rte_ether_addr *mac_addr,
 236                         uint32_t index, uint32_t pool);
 237 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 238 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 239                                            struct rte_ether_addr *mac_addr);
 240 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 241 static bool is_device_supported(struct rte_eth_dev *dev,
 242                                 struct rte_pci_driver *drv);
 243
 244 /* For Virtual Function support */
 245 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 246 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 247 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 248 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 249 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 250                                    int wait_to_complete);
 251 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 252 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 253 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 254 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 255 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 256 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 257                 struct rte_eth_stats *stats);
 258 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 259 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 260                 uint16_t vlan_id, int on);
 261 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 262                 uint16_t queue, int on);
 263 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 264 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 265 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 266 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id);
 268 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 269                                              uint16_t queue_id);
 270 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 271                                  uint8_t queue, uint8_t msix_vector);
 272 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 273 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 274 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 275 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 276 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 277
 278 /* For Eth VMDQ APIs support */
 279 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 280                 rte_ether_addr * mac_addr, uint8_t on);
 281 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 282 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 283                 struct rte_eth_mirror_conf *mirror_conf,
 284                 uint8_t rule_id, uint8_t on);
 285 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 286                 uint8_t rule_id);
 287 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 288                                           uint16_t queue_id);
 289 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 290                                            uint16_t queue_id);
 291 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 292                                uint8_t queue, uint8_t msix_vector);
 293 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 294
 295 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 296                                 struct rte_ether_addr *mac_addr,
 297                                 uint32_t index, uint32_t pool);
 298 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 299 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 300                                              struct rte_ether_addr *mac_addr);
 301 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 302                         struct rte_eth_syn_filter *filter);
 303 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 304                         enum rte_filter_op filter_op,
 305                         void *arg);
 306 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 307                         struct ixgbe_5tuple_filter *filter);
 308 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 311                                 enum rte_filter_op filter_op,
 312                                 void *arg);
 313 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 314                         struct rte_eth_ntuple_filter *filter);
 315 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 316                                 enum rte_filter_op filter_op,
 317                                 void *arg);
 318 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 319                         struct rte_eth_ethertype_filter *filter);
 320 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 321                      enum rte_filter_type filter_type,
 322                      enum rte_filter_op filter_op,
 323                      void *arg);
 324 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 325
 326 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 327                                       struct rte_ether_addr *mc_addr_set,
 328                                       uint32_t nb_mc_addr);
 329 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 330                                    struct rte_eth_dcb_info *dcb_info);
 331
 332 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 333 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 334                             struct rte_dev_reg_info *regs);
 335 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 336 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340
 341 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 342                                  struct rte_eth_dev_module_info *modinfo);
 343 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 344                                    struct rte_dev_eeprom_info *info);
 345
 346 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 347 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 348                                 struct rte_dev_reg_info *regs);
 349
 350 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 351 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 353                                             struct timespec *timestamp,
 354                                             uint32_t flags);
 355 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 356                                             struct timespec *timestamp);
 357 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 361                                    const struct timespec *timestamp);
 362 static void ixgbevf_dev_interrupt_handler(void *param);
 363
 364 static int ixgbe_dev_l2_tunnel_eth_type_conf
 365         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 366 static int ixgbe_dev_l2_tunnel_offload_set
 367         (struct rte_eth_dev *dev,
 368          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 369          uint32_t mask,
 370          uint8_t en);
 371 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 372                                              enum rte_filter_op filter_op,
 373                                              void *arg);
 374
 375 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 376                                          struct rte_eth_udp_tunnel *udp_tunnel);
 377 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 380 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 381
 382 /*
 383  * Define VF Stats MACRO for Non "cleared on read" register
 384  */
 385 #define UPDATE_VF_STAT(reg, last, cur)                          \
 386 {                                                               \
 387         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 388         cur += (latest - last) & UINT_MAX;                      \
 389         last = latest;                                          \
 390 }
 391
 392 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 393 {                                                                \
 394         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 395         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 396         u64 latest = ((new_msb << 32) | new_lsb);                \
 397         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 398         last = latest;                                           \
 399 }
 400
 401 #define IXGBE_SET_HWSTRIP(h, q) do {\
 402                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 403                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 404                 (h)->bitmap[idx] |= 1 << bit;\
 405         } while (0)
 406
 407 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 408                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 409                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 410                 (h)->bitmap[idx] &= ~(1 << bit);\
 411         } while (0)
 412
 413 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 414                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 415                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 416                 (r) = (h)->bitmap[idx] >> bit & 1;\
 417         } while (0)
 418
 419 int ixgbe_logtype_init;
 420 int ixgbe_logtype_driver;
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 549         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 550         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 551         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 552         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 553         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 554         .dev_led_on           = ixgbe_dev_led_on,
 555         .dev_led_off          = ixgbe_dev_led_off,
 556         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 557         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 558         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 559         .mac_addr_add         = ixgbe_add_rar,
 560         .mac_addr_remove      = ixgbe_remove_rar,
 561         .mac_addr_set         = ixgbe_set_default_mac_addr,
 562         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 563         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 564         .mirror_rule_set      = ixgbe_mirror_rule_set,
 565         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 566         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 567         .reta_update          = ixgbe_dev_rss_reta_update,
 568         .reta_query           = ixgbe_dev_rss_reta_query,
 569         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 570         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 571         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 572         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 573         .rxq_info_get         = ixgbe_rxq_info_get,
 574         .txq_info_get         = ixgbe_txq_info_get,
 575         .timesync_enable      = ixgbe_timesync_enable,
 576         .timesync_disable     = ixgbe_timesync_disable,
 577         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 578         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 579         .get_reg              = ixgbe_get_regs,
 580         .get_eeprom_length    = ixgbe_get_eeprom_length,
 581         .get_eeprom           = ixgbe_get_eeprom,
 582         .set_eeprom           = ixgbe_set_eeprom,
 583         .get_module_info      = ixgbe_get_module_info,
 584         .get_module_eeprom    = ixgbe_get_module_eeprom,
 585         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 586         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 587         .timesync_read_time   = ixgbe_timesync_read_time,
 588         .timesync_write_time  = ixgbe_timesync_write_time,
 589         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 590         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 591         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 592         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 593         .tm_ops_get           = ixgbe_tm_ops_get,
 594 };
 595
 596 /*
 597  * dev_ops for virtual function, bare necessities for basic vf
 598  * operation have been implemented
 599  */
 600 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 601         .dev_configure        = ixgbevf_dev_configure,
 602         .dev_start            = ixgbevf_dev_start,
 603         .dev_stop             = ixgbevf_dev_stop,
 604         .link_update          = ixgbevf_dev_link_update,
 605         .stats_get            = ixgbevf_dev_stats_get,
 606         .xstats_get           = ixgbevf_dev_xstats_get,
 607         .stats_reset          = ixgbevf_dev_stats_reset,
 608         .xstats_reset         = ixgbevf_dev_stats_reset,
 609         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 610         .dev_close            = ixgbevf_dev_close,
 611         .dev_reset            = ixgbevf_dev_reset,
 612         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 613         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 614         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 615         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 616         .dev_infos_get        = ixgbevf_dev_info_get,
 617         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 618         .mtu_set              = ixgbevf_dev_set_mtu,
 619         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 620         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 621         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 622         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 623         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 624         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 625         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 626         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 627         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 628         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 629         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 630         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 631         .mac_addr_add         = ixgbevf_add_mac_addr,
 632         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 633         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 634         .rxq_info_get         = ixgbe_rxq_info_get,
 635         .txq_info_get         = ixgbe_txq_info_get,
 636         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 637         .get_reg              = ixgbevf_get_regs,
 638         .reta_update          = ixgbe_dev_rss_reta_update,
 639         .reta_query           = ixgbe_dev_rss_reta_query,
 640         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 641         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 642 };
 643
 644 /* store statistics names and its offset in stats structure */
 645 struct rte_ixgbe_xstats_name_off {
 646         char name[RTE_ETH_XSTATS_NAME_SIZE];
 647         unsigned offset;
 648 };
 649
 650 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 651         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 652         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 653         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 654         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 655         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 656         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 657         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 658         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 659         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 660         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 661         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 662         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 663         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 664         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 665         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 666                 prc1023)},
 667         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 668                 prc1522)},
 669         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 670         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 671         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 672         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 673         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 674         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 675         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 676         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 677         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 678         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 679         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 680         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 681         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 682         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 683         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 684         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 685         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 686                 ptc1023)},
 687         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 688                 ptc1522)},
 689         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 690         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 691         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 692         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 693
 694         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 695                 fdirustat_add)},
 696         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirustat_remove)},
 698         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 699                 fdirfstat_fadd)},
 700         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 701                 fdirfstat_fremove)},
 702         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirmatch)},
 704         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirmiss)},
 706
 707         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 708         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 709         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 710                 fclast)},
 711         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 712         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 713         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 714         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 715         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 716                 fcoe_noddp)},
 717         {"rx_fcoe_no_direct_data_placement_ext_buff",
 718                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 719
 720         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 721                 lxontxc)},
 722         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 723                 lxonrxc)},
 724         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxofftxc)},
 726         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxoffrxc)},
 728         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 729 };
 730
 731 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 732                            sizeof(rte_ixgbe_stats_strings[0]))
 733
 734 /* MACsec statistics */
 735 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 736         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 737                 out_pkts_untagged)},
 738         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 739                 out_pkts_encrypted)},
 740         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_protected)},
 742         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 743                 out_octets_encrypted)},
 744         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 745                 out_octets_protected)},
 746         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_untagged)},
 748         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_badtag)},
 750         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_nosci)},
 752         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_unknownsci)},
 754         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 755                 in_octets_decrypted)},
 756         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 757                 in_octets_validated)},
 758         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_unchecked)},
 760         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_delayed)},
 762         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_late)},
 764         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_ok)},
 766         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_invalid)},
 768         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_notvalid)},
 770         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_unusedsa)},
 772         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_notusingsa)},
 774 };
 775
 776 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 777                            sizeof(rte_ixgbe_macsec_strings[0]))
 778
 779 /* Per-queue statistics */
 780 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 781         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 782         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 783         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 784         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 785 };
 786
 787 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 788                            sizeof(rte_ixgbe_rxq_strings[0]))
 789 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 790
 791 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 792         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 793         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 794         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 795                 pxon2offc)},
 796 };
 797
 798 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 799                            sizeof(rte_ixgbe_txq_strings[0]))
 800 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 801
 802 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 803         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 804 };
 805
 806 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 807                 sizeof(rte_ixgbevf_stats_strings[0]))
 808
 809 /*
 810  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 811  */
 812 static inline int
 813 ixgbe_is_sfp(struct ixgbe_hw *hw)
 814 {
 815         switch (hw->phy.type) {
 816         case ixgbe_phy_sfp_avago:
 817         case ixgbe_phy_sfp_ftl:
 818         case ixgbe_phy_sfp_intel:
 819         case ixgbe_phy_sfp_unknown:
 820         case ixgbe_phy_sfp_passive_tyco:
 821         case ixgbe_phy_sfp_passive_unknown:
 822                 return 1;
 823         default:
 824                 return 0;
 825         }
 826 }
 827
 828 static inline int32_t
 829 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 830 {
 831         uint32_t ctrl_ext;
 832         int32_t status;
 833
 834         status = ixgbe_reset_hw(hw);
 835
 836         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 837         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 838         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 839         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 840         IXGBE_WRITE_FLUSH(hw);
 841
 842         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 843                 status = IXGBE_SUCCESS;
 844         return status;
 845 }
 846
 847 static inline void
 848 ixgbe_enable_intr(struct rte_eth_dev *dev)
 849 {
 850         struct ixgbe_interrupt *intr =
 851                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 852         struct ixgbe_hw *hw =
 853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854
 855         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 856         IXGBE_WRITE_FLUSH(hw);
 857 }
 858
 859 /*
 860  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 861  */
 862 static void
 863 ixgbe_disable_intr(struct ixgbe_hw *hw)
 864 {
 865         PMD_INIT_FUNC_TRACE();
 866
 867         if (hw->mac.type == ixgbe_mac_82598EB) {
 868                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 869         } else {
 870                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 871                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 872                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 873         }
 874         IXGBE_WRITE_FLUSH(hw);
 875 }
 876
 877 /*
 878  * This function resets queue statistics mapping registers.
 879  * From Niantic datasheet, Initialization of Statistics section:
 880  * "...if software requires the queue counters, the RQSMR and TQSM registers
 881  * must be re-programmed following a device reset.
 882  */
 883 static void
 884 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 885 {
 886         uint32_t i;
 887
 888         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 889                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 890                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 891         }
 892 }
 893
 894
 895 static int
 896 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 897                                   uint16_t queue_id,
 898                                   uint8_t stat_idx,
 899                                   uint8_t is_rx)
 900 {
 901 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 902 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 903 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 904
 905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 906         struct ixgbe_stat_mapping_registers *stat_mappings =
 907                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 908         uint32_t qsmr_mask = 0;
 909         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 910         uint32_t q_map;
 911         uint8_t n, offset;
 912
 913         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 914                 (hw->mac.type != ixgbe_mac_X540) &&
 915                 (hw->mac.type != ixgbe_mac_X550) &&
 916                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 917                 (hw->mac.type != ixgbe_mac_X550EM_a))
 918                 return -ENOSYS;
 919
 920         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 921                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 922                      queue_id, stat_idx);
 923
 924         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 925         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 926                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 927                 return -EIO;
 928         }
 929         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 930
 931         /* Now clear any previous stat_idx set */
 932         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 933         if (!is_rx)
 934                 stat_mappings->tqsm[n] &= ~clearing_mask;
 935         else
 936                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 937
 938         q_map = (uint32_t)stat_idx;
 939         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 940         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 941         if (!is_rx)
 942                 stat_mappings->tqsm[n] |= qsmr_mask;
 943         else
 944                 stat_mappings->rqsmr[n] |= qsmr_mask;
 945
 946         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 947                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 948                      queue_id, stat_idx);
 949         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 950                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 951
 952         /* Now write the mapping in the appropriate register */
 953         if (is_rx) {
 954                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 955                              stat_mappings->rqsmr[n], n);
 956                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 957         } else {
 958                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 959                              stat_mappings->tqsm[n], n);
 960                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 961         }
 962         return 0;
 963 }
 964
 965 static void
 966 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 967 {
 968         struct ixgbe_stat_mapping_registers *stat_mappings =
 969                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 971         int i;
 972
 973         /* write whatever was in stat mapping table to the NIC */
 974         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 975                 /* rx */
 976                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 977
 978                 /* tx */
 979                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 980         }
 981 }
 982
 983 static void
 984 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 985 {
 986         uint8_t i;
 987         struct ixgbe_dcb_tc_config *tc;
 988         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 989
 990         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 991         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 992         for (i = 0; i < dcb_max_tc; i++) {
 993                 tc = &dcb_config->tc_config[i];
 994                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 995                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 996                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 997                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 998                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 999                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1000                 tc->pfc = ixgbe_dcb_pfc_disabled;
1001         }
1002
1003         /* Initialize default user to priority mapping, UPx->TC0 */
1004         tc = &dcb_config->tc_config[0];
1005         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1006         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1007         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1008                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1009                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1010         }
1011         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1012         dcb_config->pfc_mode_enable = false;
1013         dcb_config->vt_mode = true;
1014         dcb_config->round_robin_enable = false;
1015         /* support all DCB capabilities in 82599 */
1016         dcb_config->support.capabilities = 0xFF;
1017
1018         /*we only support 4 Tcs for X540, X550 */
1019         if (hw->mac.type == ixgbe_mac_X540 ||
1020                 hw->mac.type == ixgbe_mac_X550 ||
1021                 hw->mac.type == ixgbe_mac_X550EM_x ||
1022                 hw->mac.type == ixgbe_mac_X550EM_a) {
1023                 dcb_config->num_tcs.pg_tcs = 4;
1024                 dcb_config->num_tcs.pfc_tcs = 4;
1025         }
1026 }
1027
1028 /*
1029  * Ensure that all locks are released before first NVM or PHY access
1030  */
1031 static void
1032 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1033 {
1034         uint16_t mask;
1035
1036         /*
1037          * Phy lock should not fail in this early stage. If this is the case,
1038          * it is due to an improper exit of the application.
1039          * So force the release of the faulty lock. Release of common lock
1040          * is done automatically by swfw_sync function.
1041          */
1042         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1043         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1044                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1045         }
1046         ixgbe_release_swfw_semaphore(hw, mask);
1047
1048         /*
1049          * These ones are more tricky since they are common to all ports; but
1050          * swfw_sync retries last long enough (1s) to be almost sure that if
1051          * lock can not be taken it is due to an improper lock of the
1052          * semaphore.
1053          */
1054         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1055         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1056                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1057         }
1058         ixgbe_release_swfw_semaphore(hw, mask);
1059 }
1060
1061 /*
1062  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1063  * It returns 0 on success.
1064  */
1065 static int
1066 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1067 {
1068         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1069         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1070         struct ixgbe_hw *hw =
1071                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1072         struct ixgbe_vfta *shadow_vfta =
1073                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1074         struct ixgbe_hwstrip *hwstrip =
1075                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1076         struct ixgbe_dcb_config *dcb_config =
1077                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1078         struct ixgbe_filter_info *filter_info =
1079                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1080         struct ixgbe_bw_conf *bw_conf =
1081                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1082         uint32_t ctrl_ext;
1083         uint16_t csum;
1084         int diag, i;
1085
1086         PMD_INIT_FUNC_TRACE();
1087
1088         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1089         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1090         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1091         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1092
1093         /*
1094          * For secondary processes, we don't initialise any further as primary
1095          * has already done this work. Only check we don't need a different
1096          * RX and TX function.
1097          */
1098         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1099                 struct ixgbe_tx_queue *txq;
1100                 /* TX queue function in primary, set by last queue initialized
1101                  * Tx queue may not initialized by primary process
1102                  */
1103                 if (eth_dev->data->tx_queues) {
1104                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1105                         ixgbe_set_tx_function(eth_dev, txq);
1106                 } else {
1107                         /* Use default TX function if we get here */
1108                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1109                                      "Using default TX function.");
1110                 }
1111
1112                 ixgbe_set_rx_function(eth_dev);
1113
1114                 return 0;
1115         }
1116
1117         rte_eth_copy_pci_info(eth_dev, pci_dev);
1118
1119         /* Vendor and Device ID need to be set before init of shared code */
1120         hw->device_id = pci_dev->id.device_id;
1121         hw->vendor_id = pci_dev->id.vendor_id;
1122         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1123         hw->allow_unsupported_sfp = 1;
1124
1125         /* Initialize the shared code (base driver) */
1126 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1127         diag = ixgbe_bypass_init_shared_code(hw);
1128 #else
1129         diag = ixgbe_init_shared_code(hw);
1130 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1131
1132         if (diag != IXGBE_SUCCESS) {
1133                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1134                 return -EIO;
1135         }
1136
1137         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1138                 PMD_INIT_LOG(ERR, "\nERROR: "
1139                         "Firmware recovery mode detected. Limiting functionality.\n"
1140                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1141                         "User Guide for details on firmware recovery mode.");
1142                 return -EIO;
1143         }
1144
1145         /* pick up the PCI bus settings for reporting later */
1146         ixgbe_get_bus_info(hw);
1147
1148         /* Unlock any pending hardware semaphore */
1149         ixgbe_swfw_lock_reset(hw);
1150
1151 #ifdef RTE_LIBRTE_SECURITY
1152         /* Initialize security_ctx only for primary process*/
1153         if (ixgbe_ipsec_ctx_create(eth_dev))
1154                 return -ENOMEM;
1155 #endif
1156
1157         /* Initialize DCB configuration*/
1158         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1159         ixgbe_dcb_init(hw, dcb_config);
1160         /* Get Hardware Flow Control setting */
1161         hw->fc.requested_mode = ixgbe_fc_full;
1162         hw->fc.current_mode = ixgbe_fc_full;
1163         hw->fc.pause_time = IXGBE_FC_PAUSE;
1164         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1165                 hw->fc.low_water[i] = IXGBE_FC_LO;
1166                 hw->fc.high_water[i] = IXGBE_FC_HI;
1167         }
1168         hw->fc.send_xon = 1;
1169
1170         /* Make sure we have a good EEPROM before we read from it */
1171         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1172         if (diag != IXGBE_SUCCESS) {
1173                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1174                 return -EIO;
1175         }
1176
1177 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1178         diag = ixgbe_bypass_init_hw(hw);
1179 #else
1180         diag = ixgbe_init_hw(hw);
1181 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1182
1183         /*
1184          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1185          * is called too soon after the kernel driver unbinding/binding occurs.
1186          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1187          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1188          * also called. See ixgbe_identify_phy_82599(). The reason for the
1189          * failure is not known, and only occuts when virtualisation features
1190          * are disabled in the bios. A delay of 100ms  was found to be enough by
1191          * trial-and-error, and is doubled to be safe.
1192          */
1193         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1194                 rte_delay_ms(200);
1195                 diag = ixgbe_init_hw(hw);
1196         }
1197
1198         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1199                 diag = IXGBE_SUCCESS;
1200
1201         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1202                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1203                              "LOM.  Please be aware there may be issues associated "
1204                              "with your hardware.");
1205                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1206                              "please contact your Intel or hardware representative "
1207                              "who provided you with this hardware.");
1208         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1209                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1210         if (diag) {
1211                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1212                 return -EIO;
1213         }
1214
1215         /* Reset the hw statistics */
1216         ixgbe_dev_stats_reset(eth_dev);
1217
1218         /* disable interrupt */
1219         ixgbe_disable_intr(hw);
1220
1221         /* reset mappings for queue statistics hw counters*/
1222         ixgbe_reset_qstat_mappings(hw);
1223
1224         /* Allocate memory for storing MAC addresses */
1225         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1226                                                hw->mac.num_rar_entries, 0);
1227         if (eth_dev->data->mac_addrs == NULL) {
1228                 PMD_INIT_LOG(ERR,
1229                              "Failed to allocate %u bytes needed to store "
1230                              "MAC addresses",
1231                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1232                 return -ENOMEM;
1233         }
1234         /* Copy the permanent MAC address */
1235         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1236                         &eth_dev->data->mac_addrs[0]);
1237
1238         /* Allocate memory for storing hash filter MAC addresses */
1239         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1240                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1241         if (eth_dev->data->hash_mac_addrs == NULL) {
1242                 PMD_INIT_LOG(ERR,
1243                              "Failed to allocate %d bytes needed to store MAC addresses",
1244                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1245                 return -ENOMEM;
1246         }
1247
1248         /* initialize the vfta */
1249         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1250
1251         /* initialize the hw strip bitmap*/
1252         memset(hwstrip, 0, sizeof(*hwstrip));
1253
1254         /* initialize PF if max_vfs not zero */
1255         ixgbe_pf_host_init(eth_dev);
1256
1257         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1258         /* let hardware know driver is loaded */
1259         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1260         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1261         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1262         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1263         IXGBE_WRITE_FLUSH(hw);
1264
1265         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1266                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1267                              (int) hw->mac.type, (int) hw->phy.type,
1268                              (int) hw->phy.sfp_type);
1269         else
1270                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1271                              (int) hw->mac.type, (int) hw->phy.type);
1272
1273         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1274                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1275                      pci_dev->id.device_id);
1276
1277         rte_intr_callback_register(intr_handle,
1278                                    ixgbe_dev_interrupt_handler, eth_dev);
1279
1280         /* enable uio/vfio intr/eventfd mapping */
1281         rte_intr_enable(intr_handle);
1282
1283         /* enable support intr */
1284         ixgbe_enable_intr(eth_dev);
1285
1286         /* initialize filter info */
1287         memset(filter_info, 0,
1288                sizeof(struct ixgbe_filter_info));
1289
1290         /* initialize 5tuple filter list */
1291         TAILQ_INIT(&filter_info->fivetuple_list);
1292
1293         /* initialize flow director filter list & hash */
1294         ixgbe_fdir_filter_init(eth_dev);
1295
1296         /* initialize l2 tunnel filter list & hash */
1297         ixgbe_l2_tn_filter_init(eth_dev);
1298
1299         /* initialize flow filter lists */
1300         ixgbe_filterlist_init();
1301
1302         /* initialize bandwidth configuration info */
1303         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1304
1305         /* initialize Traffic Manager configuration */
1306         ixgbe_tm_conf_init(eth_dev);
1307
1308         return 0;
1309 }
1310
1311 static int
1312 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1313 {
1314         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1315         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1316         struct ixgbe_hw *hw;
1317         int retries = 0;
1318         int ret;
1319
1320         PMD_INIT_FUNC_TRACE();
1321
1322         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1323                 return 0;
1324
1325         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1326
1327         if (hw->adapter_stopped == 0)
1328                 ixgbe_dev_close(eth_dev);
1329
1330         eth_dev->dev_ops = NULL;
1331         eth_dev->rx_pkt_burst = NULL;
1332         eth_dev->tx_pkt_burst = NULL;
1333
1334         /* Unlock any pending hardware semaphore */
1335         ixgbe_swfw_lock_reset(hw);
1336
1337         /* disable uio intr before callback unregister */
1338         rte_intr_disable(intr_handle);
1339
1340         do {
1341                 ret = rte_intr_callback_unregister(intr_handle,
1342                                 ixgbe_dev_interrupt_handler, eth_dev);
1343                 if (ret >= 0) {
1344                         break;
1345                 } else if (ret != -EAGAIN) {
1346                         PMD_INIT_LOG(ERR,
1347                                 "intr callback unregister failed: %d",
1348                                 ret);
1349                         return ret;
1350                 }
1351                 rte_delay_ms(100);
1352         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1353
1354         /* cancel the delay handler before remove dev */
1355         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1356
1357         /* cancel the link handler before remove dev */
1358         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, eth_dev);
1359
1360         /* uninitialize PF if max_vfs not zero */
1361         ixgbe_pf_host_uninit(eth_dev);
1362
1363         /* remove all the fdir filters & hash */
1364         ixgbe_fdir_filter_uninit(eth_dev);
1365
1366         /* remove all the L2 tunnel filters & hash */
1367         ixgbe_l2_tn_filter_uninit(eth_dev);
1368
1369         /* Remove all ntuple filters of the device */
1370         ixgbe_ntuple_filter_uninit(eth_dev);
1371
1372         /* clear all the filters list */
1373         ixgbe_filterlist_flush();
1374
1375         /* Remove all Traffic Manager configuration */
1376         ixgbe_tm_conf_uninit(eth_dev);
1377
1378 #ifdef RTE_LIBRTE_SECURITY
1379         rte_free(eth_dev->security_ctx);
1380 #endif
1381
1382         return 0;
1383 }
1384
1385 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1386 {
1387         struct ixgbe_filter_info *filter_info =
1388                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1389         struct ixgbe_5tuple_filter *p_5tuple;
1390
1391         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1392                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1393                              p_5tuple,
1394                              entries);
1395                 rte_free(p_5tuple);
1396         }
1397         memset(filter_info->fivetuple_mask, 0,
1398                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_hw_fdir_info *fdir_info =
1406                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1407         struct ixgbe_fdir_filter *fdir_filter;
1408
1409                 if (fdir_info->hash_map)
1410                 rte_free(fdir_info->hash_map);
1411         if (fdir_info->hash_handle)
1412                 rte_hash_free(fdir_info->hash_handle);
1413
1414         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1415                 TAILQ_REMOVE(&fdir_info->fdir_list,
1416                              fdir_filter,
1417                              entries);
1418                 rte_free(fdir_filter);
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_l2_tn_info *l2_tn_info =
1427                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1428         struct ixgbe_l2_tn_filter *l2_tn_filter;
1429
1430         if (l2_tn_info->hash_map)
1431                 rte_free(l2_tn_info->hash_map);
1432         if (l2_tn_info->hash_handle)
1433                 rte_hash_free(l2_tn_info->hash_handle);
1434
1435         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1436                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1437                              l2_tn_filter,
1438                              entries);
1439                 rte_free(l2_tn_filter);
1440         }
1441
1442         return 0;
1443 }
1444
1445 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1446 {
1447         struct ixgbe_hw_fdir_info *fdir_info =
1448                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1449         char fdir_hash_name[RTE_HASH_NAMESIZE];
1450         struct rte_hash_parameters fdir_hash_params = {
1451                 .name = fdir_hash_name,
1452                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1453                 .key_len = sizeof(union ixgbe_atr_input),
1454                 .hash_func = rte_hash_crc,
1455                 .hash_func_init_val = 0,
1456                 .socket_id = rte_socket_id(),
1457         };
1458
1459         TAILQ_INIT(&fdir_info->fdir_list);
1460         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1461                  "fdir_%s", eth_dev->device->name);
1462         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1463         if (!fdir_info->hash_handle) {
1464                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1465                 return -EINVAL;
1466         }
1467         fdir_info->hash_map = rte_zmalloc("ixgbe",
1468                                           sizeof(struct ixgbe_fdir_filter *) *
1469                                           IXGBE_MAX_FDIR_FILTER_NUM,
1470                                           0);
1471         if (!fdir_info->hash_map) {
1472                 PMD_INIT_LOG(ERR,
1473                              "Failed to allocate memory for fdir hash map!");
1474                 return -ENOMEM;
1475         }
1476         fdir_info->mask_added = FALSE;
1477
1478         return 0;
1479 }
1480
1481 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1482 {
1483         struct ixgbe_l2_tn_info *l2_tn_info =
1484                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1485         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1486         struct rte_hash_parameters l2_tn_hash_params = {
1487                 .name = l2_tn_hash_name,
1488                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1489                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1490                 .hash_func = rte_hash_crc,
1491                 .hash_func_init_val = 0,
1492                 .socket_id = rte_socket_id(),
1493         };
1494
1495         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1496         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1497                  "l2_tn_%s", eth_dev->device->name);
1498         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1499         if (!l2_tn_info->hash_handle) {
1500                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1501                 return -EINVAL;
1502         }
1503         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1504                                    sizeof(struct ixgbe_l2_tn_filter *) *
1505                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1506                                    0);
1507         if (!l2_tn_info->hash_map) {
1508                 PMD_INIT_LOG(ERR,
1509                         "Failed to allocate memory for L2 TN hash map!");
1510                 return -ENOMEM;
1511         }
1512         l2_tn_info->e_tag_en = FALSE;
1513         l2_tn_info->e_tag_fwd_en = FALSE;
1514         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1515
1516         return 0;
1517 }
1518 /*
1519  * Negotiate mailbox API version with the PF.
1520  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1521  * Then we try to negotiate starting with the most recent one.
1522  * If all negotiation attempts fail, then we will proceed with
1523  * the default one (ixgbe_mbox_api_10).
1524  */
1525 static void
1526 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1527 {
1528         int32_t i;
1529
1530         /* start with highest supported, proceed down */
1531         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1532                 ixgbe_mbox_api_13,
1533                 ixgbe_mbox_api_12,
1534                 ixgbe_mbox_api_11,
1535                 ixgbe_mbox_api_10,
1536         };
1537
1538         for (i = 0;
1539                         i != RTE_DIM(sup_ver) &&
1540                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1541                         i++)
1542                 ;
1543 }
1544
1545 static void
1546 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1547 {
1548         uint64_t random;
1549
1550         /* Set Organizationally Unique Identifier (OUI) prefix. */
1551         mac_addr->addr_bytes[0] = 0x00;
1552         mac_addr->addr_bytes[1] = 0x09;
1553         mac_addr->addr_bytes[2] = 0xC0;
1554         /* Force indication of locally assigned MAC address. */
1555         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1556         /* Generate the last 3 bytes of the MAC address with a random number. */
1557         random = rte_rand();
1558         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1559 }
1560
1561 static int
1562 devarg_handle_int(__rte_unused const char *key, const char *value,
1563                   void *extra_args)
1564 {
1565         uint16_t *n = extra_args;
1566
1567         if (value == NULL || extra_args == NULL)
1568                 return -EINVAL;
1569
1570         *n = (uint16_t)strtoul(value, NULL, 0);
1571         if (*n == USHRT_MAX && errno == ERANGE)
1572                 return -1;
1573
1574         return 0;
1575 }
1576
1577 static void
1578 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1579                       struct rte_devargs *devargs)
1580 {
1581         struct rte_kvargs *kvlist;
1582         uint16_t pflink_fullchk;
1583
1584         if (devargs == NULL)
1585                 return;
1586
1587         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1588         if (kvlist == NULL)
1589                 return;
1590
1591         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1592             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1593                                devarg_handle_int, &pflink_fullchk) == 0 &&
1594             pflink_fullchk == 1)
1595                 adapter->pflink_fullchk = 1;
1596
1597         rte_kvargs_free(kvlist);
1598 }
1599
1600 /*
1601  * Virtual Function device init
1602  */
1603 static int
1604 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1605 {
1606         int diag;
1607         uint32_t tc, tcs;
1608         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1609         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1610         struct ixgbe_hw *hw =
1611                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1612         struct ixgbe_vfta *shadow_vfta =
1613                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1614         struct ixgbe_hwstrip *hwstrip =
1615                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1616         struct rte_ether_addr *perm_addr =
1617                 (struct rte_ether_addr *)hw->mac.perm_addr;
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1622         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1623         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1624
1625         /* for secondary processes, we don't initialise any further as primary
1626          * has already done this work. Only check we don't need a different
1627          * RX function
1628          */
1629         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1630                 struct ixgbe_tx_queue *txq;
1631                 /* TX queue function in primary, set by last queue initialized
1632                  * Tx queue may not initialized by primary process
1633                  */
1634                 if (eth_dev->data->tx_queues) {
1635                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1636                         ixgbe_set_tx_function(eth_dev, txq);
1637                 } else {
1638                         /* Use default TX function if we get here */
1639                         PMD_INIT_LOG(NOTICE,
1640                                      "No TX queues configured yet. Using default TX function.");
1641                 }
1642
1643                 ixgbe_set_rx_function(eth_dev);
1644
1645                 return 0;
1646         }
1647
1648         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1649                               pci_dev->device.devargs);
1650
1651         rte_eth_copy_pci_info(eth_dev, pci_dev);
1652
1653         hw->device_id = pci_dev->id.device_id;
1654         hw->vendor_id = pci_dev->id.vendor_id;
1655         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1656
1657         /* initialize the vfta */
1658         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1659
1660         /* initialize the hw strip bitmap*/
1661         memset(hwstrip, 0, sizeof(*hwstrip));
1662
1663         /* Initialize the shared code (base driver) */
1664         diag = ixgbe_init_shared_code(hw);
1665         if (diag != IXGBE_SUCCESS) {
1666                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1667                 return -EIO;
1668         }
1669
1670         /* init_mailbox_params */
1671         hw->mbx.ops.init_params(hw);
1672
1673         /* Reset the hw statistics */
1674         ixgbevf_dev_stats_reset(eth_dev);
1675
1676         /* Disable the interrupts for VF */
1677         ixgbevf_intr_disable(eth_dev);
1678
1679         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1680         diag = hw->mac.ops.reset_hw(hw);
1681
1682         /*
1683          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1684          * the underlying PF driver has not assigned a MAC address to the VF.
1685          * In this case, assign a random MAC address.
1686          */
1687         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1688                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1689                 /*
1690                  * This error code will be propagated to the app by
1691                  * rte_eth_dev_reset, so use a public error code rather than
1692                  * the internal-only IXGBE_ERR_RESET_FAILED
1693                  */
1694                 return -EAGAIN;
1695         }
1696
1697         /* negotiate mailbox API version to use with the PF. */
1698         ixgbevf_negotiate_api(hw);
1699
1700         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1701         ixgbevf_get_queues(hw, &tcs, &tc);
1702
1703         /* Allocate memory for storing MAC addresses */
1704         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1705                                                hw->mac.num_rar_entries, 0);
1706         if (eth_dev->data->mac_addrs == NULL) {
1707                 PMD_INIT_LOG(ERR,
1708                              "Failed to allocate %u bytes needed to store "
1709                              "MAC addresses",
1710                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1711                 return -ENOMEM;
1712         }
1713
1714         /* Generate a random MAC address, if none was assigned by PF. */
1715         if (rte_is_zero_ether_addr(perm_addr)) {
1716                 generate_random_mac_addr(perm_addr);
1717                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1718                 if (diag) {
1719                         rte_free(eth_dev->data->mac_addrs);
1720                         eth_dev->data->mac_addrs = NULL;
1721                         return diag;
1722                 }
1723                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1724                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1725                              "%02x:%02x:%02x:%02x:%02x:%02x",
1726                              perm_addr->addr_bytes[0],
1727                              perm_addr->addr_bytes[1],
1728                              perm_addr->addr_bytes[2],
1729                              perm_addr->addr_bytes[3],
1730                              perm_addr->addr_bytes[4],
1731                              perm_addr->addr_bytes[5]);
1732         }
1733
1734         /* Copy the permanent MAC address */
1735         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1736
1737         /* reset the hardware with the new settings */
1738         diag = hw->mac.ops.start_hw(hw);
1739         switch (diag) {
1740         case  0:
1741                 break;
1742
1743         default:
1744                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1745                 return -EIO;
1746         }
1747
1748         rte_intr_callback_register(intr_handle,
1749                                    ixgbevf_dev_interrupt_handler, eth_dev);
1750         rte_intr_enable(intr_handle);
1751         ixgbevf_intr_enable(eth_dev);
1752
1753         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1754                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1755                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1756
1757         return 0;
1758 }
1759
1760 /* Virtual Function device uninit */
1761
1762 static int
1763 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1764 {
1765         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1767         struct ixgbe_hw *hw;
1768
1769         PMD_INIT_FUNC_TRACE();
1770
1771         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1772                 return 0;
1773
1774         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1775
1776         if (hw->adapter_stopped == 0)
1777                 ixgbevf_dev_close(eth_dev);
1778
1779         eth_dev->dev_ops = NULL;
1780         eth_dev->rx_pkt_burst = NULL;
1781         eth_dev->tx_pkt_burst = NULL;
1782
1783         /* Disable the interrupts for VF */
1784         ixgbevf_intr_disable(eth_dev);
1785
1786         rte_intr_disable(intr_handle);
1787         rte_intr_callback_unregister(intr_handle,
1788                                      ixgbevf_dev_interrupt_handler, eth_dev);
1789
1790         return 0;
1791 }
1792
1793 static int
1794 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1795                 struct rte_pci_device *pci_dev)
1796 {
1797         char name[RTE_ETH_NAME_MAX_LEN];
1798         struct rte_eth_dev *pf_ethdev;
1799         struct rte_eth_devargs eth_da;
1800         int i, retval;
1801
1802         if (pci_dev->device.devargs) {
1803                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1804                                 &eth_da);
1805                 if (retval)
1806                         return retval;
1807         } else
1808                 memset(&eth_da, 0, sizeof(eth_da));
1809
1810         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1811                 sizeof(struct ixgbe_adapter),
1812                 eth_dev_pci_specific_init, pci_dev,
1813                 eth_ixgbe_dev_init, NULL);
1814
1815         if (retval || eth_da.nb_representor_ports < 1)
1816                 return retval;
1817
1818         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1819         if (pf_ethdev == NULL)
1820                 return -ENODEV;
1821
1822         /* probe VF representor ports */
1823         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1824                 struct ixgbe_vf_info *vfinfo;
1825                 struct ixgbe_vf_representor representor;
1826
1827                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1828                         pf_ethdev->data->dev_private);
1829                 if (vfinfo == NULL) {
1830                         PMD_DRV_LOG(ERR,
1831                                 "no virtual functions supported by PF");
1832                         break;
1833                 }
1834
1835                 representor.vf_id = eth_da.representor_ports[i];
1836                 representor.switch_domain_id = vfinfo->switch_domain_id;
1837                 representor.pf_ethdev = pf_ethdev;
1838
1839                 /* representor port net_bdf_port */
1840                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1841                         pci_dev->device.name,
1842                         eth_da.representor_ports[i]);
1843
1844                 retval = rte_eth_dev_create(&pci_dev->device, name,
1845                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1846                         ixgbe_vf_representor_init, &representor);
1847
1848                 if (retval)
1849                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1850                                 "representor %s.", name);
1851         }
1852
1853         return 0;
1854 }
1855
1856 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1857 {
1858         struct rte_eth_dev *ethdev;
1859
1860         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1861         if (!ethdev)
1862                 return -ENODEV;
1863
1864         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1865                 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1866         else
1867                 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1868 }
1869
1870 static struct rte_pci_driver rte_ixgbe_pmd = {
1871         .id_table = pci_id_ixgbe_map,
1872         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1873         .probe = eth_ixgbe_pci_probe,
1874         .remove = eth_ixgbe_pci_remove,
1875 };
1876
1877 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1878         struct rte_pci_device *pci_dev)
1879 {
1880         return rte_eth_dev_pci_generic_probe(pci_dev,
1881                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1882 }
1883
1884 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1885 {
1886         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1887 }
1888
1889 /*
1890  * virtual function driver struct
1891  */
1892 static struct rte_pci_driver rte_ixgbevf_pmd = {
1893         .id_table = pci_id_ixgbevf_map,
1894         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1895         .probe = eth_ixgbevf_pci_probe,
1896         .remove = eth_ixgbevf_pci_remove,
1897 };
1898
1899 static int
1900 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1901 {
1902         struct ixgbe_hw *hw =
1903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904         struct ixgbe_vfta *shadow_vfta =
1905                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1906         uint32_t vfta;
1907         uint32_t vid_idx;
1908         uint32_t vid_bit;
1909
1910         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1911         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1912         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1913         if (on)
1914                 vfta |= vid_bit;
1915         else
1916                 vfta &= ~vid_bit;
1917         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1918
1919         /* update local VFTA copy */
1920         shadow_vfta->vfta[vid_idx] = vfta;
1921
1922         return 0;
1923 }
1924
1925 static void
1926 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1927 {
1928         if (on)
1929                 ixgbe_vlan_hw_strip_enable(dev, queue);
1930         else
1931                 ixgbe_vlan_hw_strip_disable(dev, queue);
1932 }
1933
1934 static int
1935 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1936                     enum rte_vlan_type vlan_type,
1937                     uint16_t tpid)
1938 {
1939         struct ixgbe_hw *hw =
1940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         int ret = 0;
1942         uint32_t reg;
1943         uint32_t qinq;
1944
1945         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1946         qinq &= IXGBE_DMATXCTL_GDV;
1947
1948         switch (vlan_type) {
1949         case ETH_VLAN_TYPE_INNER:
1950                 if (qinq) {
1951                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1952                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1953                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1954                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1955                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1956                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1957                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1958                 } else {
1959                         ret = -ENOTSUP;
1960                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1961                                     " by single VLAN");
1962                 }
1963                 break;
1964         case ETH_VLAN_TYPE_OUTER:
1965                 if (qinq) {
1966                         /* Only the high 16-bits is valid */
1967                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1968                                         IXGBE_EXVET_VET_EXT_SHIFT);
1969                 } else {
1970                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1971                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1972                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1973                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1974                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1975                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1976                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1977                 }
1978
1979                 break;
1980         default:
1981                 ret = -EINVAL;
1982                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1983                 break;
1984         }
1985
1986         return ret;
1987 }
1988
1989 void
1990 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1991 {
1992         struct ixgbe_hw *hw =
1993                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994         uint32_t vlnctrl;
1995
1996         PMD_INIT_FUNC_TRACE();
1997
1998         /* Filter Table Disable */
1999         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2000         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2001
2002         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2003 }
2004
2005 void
2006 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2007 {
2008         struct ixgbe_hw *hw =
2009                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010         struct ixgbe_vfta *shadow_vfta =
2011                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2012         uint32_t vlnctrl;
2013         uint16_t i;
2014
2015         PMD_INIT_FUNC_TRACE();
2016
2017         /* Filter Table Enable */
2018         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2019         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2020         vlnctrl |= IXGBE_VLNCTRL_VFE;
2021
2022         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2023
2024         /* write whatever is in local vfta copy */
2025         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
2026                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
2027 }
2028
2029 static void
2030 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
2031 {
2032         struct ixgbe_hwstrip *hwstrip =
2033                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
2034         struct ixgbe_rx_queue *rxq;
2035
2036         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
2037                 return;
2038
2039         if (on)
2040                 IXGBE_SET_HWSTRIP(hwstrip, queue);
2041         else
2042                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
2043
2044         if (queue >= dev->data->nb_rx_queues)
2045                 return;
2046
2047         rxq = dev->data->rx_queues[queue];
2048
2049         if (on) {
2050                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2051                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2052         } else {
2053                 rxq->vlan_flags = PKT_RX_VLAN;
2054                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2055         }
2056 }
2057
2058 static void
2059 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2060 {
2061         struct ixgbe_hw *hw =
2062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2063         uint32_t ctrl;
2064
2065         PMD_INIT_FUNC_TRACE();
2066
2067         if (hw->mac.type == ixgbe_mac_82598EB) {
2068                 /* No queue level support */
2069                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2070                 return;
2071         }
2072
2073         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2074         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2075         ctrl &= ~IXGBE_RXDCTL_VME;
2076         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2077
2078         /* record those setting for HW strip per queue */
2079         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2080 }
2081
2082 static void
2083 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2084 {
2085         struct ixgbe_hw *hw =
2086                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2087         uint32_t ctrl;
2088
2089         PMD_INIT_FUNC_TRACE();
2090
2091         if (hw->mac.type == ixgbe_mac_82598EB) {
2092                 /* No queue level supported */
2093                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2094                 return;
2095         }
2096
2097         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2098         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2099         ctrl |= IXGBE_RXDCTL_VME;
2100         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2101
2102         /* record those setting for HW strip per queue */
2103         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2104 }
2105
2106 static void
2107 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2108 {
2109         struct ixgbe_hw *hw =
2110                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2111         uint32_t ctrl;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         /* DMATXCTRL: Geric Double VLAN Disable */
2116         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2117         ctrl &= ~IXGBE_DMATXCTL_GDV;
2118         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2119
2120         /* CTRL_EXT: Global Double VLAN Disable */
2121         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2122         ctrl &= ~IXGBE_EXTENDED_VLAN;
2123         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2124
2125 }
2126
2127 static void
2128 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2129 {
2130         struct ixgbe_hw *hw =
2131                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132         uint32_t ctrl;
2133
2134         PMD_INIT_FUNC_TRACE();
2135
2136         /* DMATXCTRL: Geric Double VLAN Enable */
2137         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2138         ctrl |= IXGBE_DMATXCTL_GDV;
2139         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2140
2141         /* CTRL_EXT: Global Double VLAN Enable */
2142         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2143         ctrl |= IXGBE_EXTENDED_VLAN;
2144         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2145
2146         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2147         if (hw->mac.type == ixgbe_mac_X550 ||
2148             hw->mac.type == ixgbe_mac_X550EM_x ||
2149             hw->mac.type == ixgbe_mac_X550EM_a) {
2150                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2151                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2152                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2153         }
2154
2155         /*
2156          * VET EXT field in the EXVET register = 0x8100 by default
2157          * So no need to change. Same to VT field of DMATXCTL register
2158          */
2159 }
2160
2161 void
2162 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2163 {
2164         struct ixgbe_hw *hw =
2165                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2166         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2167         uint32_t ctrl;
2168         uint16_t i;
2169         struct ixgbe_rx_queue *rxq;
2170         bool on;
2171
2172         PMD_INIT_FUNC_TRACE();
2173
2174         if (hw->mac.type == ixgbe_mac_82598EB) {
2175                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2176                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2177                         ctrl |= IXGBE_VLNCTRL_VME;
2178                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2179                 } else {
2180                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2181                         ctrl &= ~IXGBE_VLNCTRL_VME;
2182                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2183                 }
2184         } else {
2185                 /*
2186                  * Other 10G NIC, the VLAN strip can be setup
2187                  * per queue in RXDCTL
2188                  */
2189                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2190                         rxq = dev->data->rx_queues[i];
2191                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2192                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2193                                 ctrl |= IXGBE_RXDCTL_VME;
2194                                 on = TRUE;
2195                         } else {
2196                                 ctrl &= ~IXGBE_RXDCTL_VME;
2197                                 on = FALSE;
2198                         }
2199                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2200
2201                         /* record those setting for HW strip per queue */
2202                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2203                 }
2204         }
2205 }
2206
2207 static void
2208 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2209 {
2210         uint16_t i;
2211         struct rte_eth_rxmode *rxmode;
2212         struct ixgbe_rx_queue *rxq;
2213
2214         if (mask & ETH_VLAN_STRIP_MASK) {
2215                 rxmode = &dev->data->dev_conf.rxmode;
2216                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2217                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2218                                 rxq = dev->data->rx_queues[i];
2219                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2220                         }
2221                 else
2222                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2223                                 rxq = dev->data->rx_queues[i];
2224                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2225                         }
2226         }
2227 }
2228
2229 static int
2230 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2231 {
2232         struct rte_eth_rxmode *rxmode;
2233         rxmode = &dev->data->dev_conf.rxmode;
2234
2235         if (mask & ETH_VLAN_STRIP_MASK) {
2236                 ixgbe_vlan_hw_strip_config(dev);
2237         }
2238
2239         if (mask & ETH_VLAN_FILTER_MASK) {
2240                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2241                         ixgbe_vlan_hw_filter_enable(dev);
2242                 else
2243                         ixgbe_vlan_hw_filter_disable(dev);
2244         }
2245
2246         if (mask & ETH_VLAN_EXTEND_MASK) {
2247                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2248                         ixgbe_vlan_hw_extend_enable(dev);
2249                 else
2250                         ixgbe_vlan_hw_extend_disable(dev);
2251         }
2252
2253         return 0;
2254 }
2255
2256 static int
2257 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2258 {
2259         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2260
2261         ixgbe_vlan_offload_config(dev, mask);
2262
2263         return 0;
2264 }
2265
2266 static void
2267 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2268 {
2269         struct ixgbe_hw *hw =
2270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2272         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2273
2274         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2275         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2276 }
2277
2278 static int
2279 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2280 {
2281         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2282
2283         switch (nb_rx_q) {
2284         case 1:
2285         case 2:
2286                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2287                 break;
2288         case 4:
2289                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2290                 break;
2291         default:
2292                 return -EINVAL;
2293         }
2294
2295         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2296                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2297         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2298                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2299         return 0;
2300 }
2301
2302 static int
2303 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2304 {
2305         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2307         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2308         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2309
2310         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2311                 /* check multi-queue mode */
2312                 switch (dev_conf->rxmode.mq_mode) {
2313                 case ETH_MQ_RX_VMDQ_DCB:
2314                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2315                         break;
2316                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2317                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2318                         PMD_INIT_LOG(ERR, "SRIOV active,"
2319                                         " unsupported mq_mode rx %d.",
2320                                         dev_conf->rxmode.mq_mode);
2321                         return -EINVAL;
2322                 case ETH_MQ_RX_RSS:
2323                 case ETH_MQ_RX_VMDQ_RSS:
2324                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2325                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2326                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2327                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2328                                                 " invalid queue number"
2329                                                 " for VMDQ RSS, allowed"
2330                                                 " value are 1, 2 or 4.");
2331                                         return -EINVAL;
2332                                 }
2333                         break;
2334                 case ETH_MQ_RX_VMDQ_ONLY:
2335                 case ETH_MQ_RX_NONE:
2336                         /* if nothing mq mode configure, use default scheme */
2337                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2338                         break;
2339                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2340                         /* SRIOV only works in VMDq enable mode */
2341                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2342                                         " wrong mq_mode rx %d.",
2343                                         dev_conf->rxmode.mq_mode);
2344                         return -EINVAL;
2345                 }
2346
2347                 switch (dev_conf->txmode.mq_mode) {
2348                 case ETH_MQ_TX_VMDQ_DCB:
2349                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2350                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2351                         break;
2352                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2353                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2354                         break;
2355                 }
2356
2357                 /* check valid queue number */
2358                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2359                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2360                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2361                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2362                                         " must be less than or equal to %d.",
2363                                         nb_rx_q, nb_tx_q,
2364                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2365                         return -EINVAL;
2366                 }
2367         } else {
2368                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2369                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2370                                           " not supported.");
2371                         return -EINVAL;
2372                 }
2373                 /* check configuration for vmdb+dcb mode */
2374                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2375                         const struct rte_eth_vmdq_dcb_conf *conf;
2376
2377                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2378                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2379                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2380                                 return -EINVAL;
2381                         }
2382                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2383                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2384                                conf->nb_queue_pools == ETH_32_POOLS)) {
2385                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2386                                                 " nb_queue_pools must be %d or %d.",
2387                                                 ETH_16_POOLS, ETH_32_POOLS);
2388                                 return -EINVAL;
2389                         }
2390                 }
2391                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2392                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2393
2394                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2395                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2396                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2397                                 return -EINVAL;
2398                         }
2399                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2400                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2401                                conf->nb_queue_pools == ETH_32_POOLS)) {
2402                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2403                                                 " nb_queue_pools != %d and"
2404                                                 " nb_queue_pools != %d.",
2405                                                 ETH_16_POOLS, ETH_32_POOLS);
2406                                 return -EINVAL;
2407                         }
2408                 }
2409
2410                 /* For DCB mode check our configuration before we go further */
2411                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2412                         const struct rte_eth_dcb_rx_conf *conf;
2413
2414                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2415                         if (!(conf->nb_tcs == ETH_4_TCS ||
2416                                conf->nb_tcs == ETH_8_TCS)) {
2417                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2418                                                 " and nb_tcs != %d.",
2419                                                 ETH_4_TCS, ETH_8_TCS);
2420                                 return -EINVAL;
2421                         }
2422                 }
2423
2424                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2425                         const struct rte_eth_dcb_tx_conf *conf;
2426
2427                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2428                         if (!(conf->nb_tcs == ETH_4_TCS ||
2429                                conf->nb_tcs == ETH_8_TCS)) {
2430                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2431                                                 " and nb_tcs != %d.",
2432                                                 ETH_4_TCS, ETH_8_TCS);
2433                                 return -EINVAL;
2434                         }
2435                 }
2436
2437                 /*
2438                  * When DCB/VT is off, maximum number of queues changes,
2439                  * except for 82598EB, which remains constant.
2440                  */
2441                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2442                                 hw->mac.type != ixgbe_mac_82598EB) {
2443                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2444                                 PMD_INIT_LOG(ERR,
2445                                              "Neither VT nor DCB are enabled, "
2446                                              "nb_tx_q > %d.",
2447                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2448                                 return -EINVAL;
2449                         }
2450                 }
2451         }
2452         return 0;
2453 }
2454
2455 static int
2456 ixgbe_dev_configure(struct rte_eth_dev *dev)
2457 {
2458         struct ixgbe_interrupt *intr =
2459                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2460         struct ixgbe_adapter *adapter = dev->data->dev_private;
2461         int ret;
2462
2463         PMD_INIT_FUNC_TRACE();
2464         /* multipe queue mode checking */
2465         ret  = ixgbe_check_mq_mode(dev);
2466         if (ret != 0) {
2467                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2468                             ret);
2469                 return ret;
2470         }
2471
2472         /* set flag to update link status after init */
2473         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2474
2475         /*
2476          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2477          * allocation or vector Rx preconditions we will reset it.
2478          */
2479         adapter->rx_bulk_alloc_allowed = true;
2480         adapter->rx_vec_allowed = true;
2481
2482         return 0;
2483 }
2484
2485 static void
2486 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2487 {
2488         struct ixgbe_hw *hw =
2489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490         struct ixgbe_interrupt *intr =
2491                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2492         uint32_t gpie;
2493
2494         /* only set up it on X550EM_X */
2495         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2496                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2497                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2498                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2499                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2500                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2501         }
2502 }
2503
2504 int
2505 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2506                         uint16_t tx_rate, uint64_t q_msk)
2507 {
2508         struct ixgbe_hw *hw;
2509         struct ixgbe_vf_info *vfinfo;
2510         struct rte_eth_link link;
2511         uint8_t  nb_q_per_pool;
2512         uint32_t queue_stride;
2513         uint32_t queue_idx, idx = 0, vf_idx;
2514         uint32_t queue_end;
2515         uint16_t total_rate = 0;
2516         struct rte_pci_device *pci_dev;
2517
2518         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2519         rte_eth_link_get_nowait(dev->data->port_id, &link);
2520
2521         if (vf >= pci_dev->max_vfs)
2522                 return -EINVAL;
2523
2524         if (tx_rate > link.link_speed)
2525                 return -EINVAL;
2526
2527         if (q_msk == 0)
2528                 return 0;
2529
2530         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2531         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2532         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2533         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2534         queue_idx = vf * queue_stride;
2535         queue_end = queue_idx + nb_q_per_pool - 1;
2536         if (queue_end >= hw->mac.max_tx_queues)
2537                 return -EINVAL;
2538
2539         if (vfinfo) {
2540                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2541                         if (vf_idx == vf)
2542                                 continue;
2543                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2544                                 idx++)
2545                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2546                 }
2547         } else {
2548                 return -EINVAL;
2549         }
2550
2551         /* Store tx_rate for this vf. */
2552         for (idx = 0; idx < nb_q_per_pool; idx++) {
2553                 if (((uint64_t)0x1 << idx) & q_msk) {
2554                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2555                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2556                         total_rate += tx_rate;
2557                 }
2558         }
2559
2560         if (total_rate > dev->data->dev_link.link_speed) {
2561                 /* Reset stored TX rate of the VF if it causes exceed
2562                  * link speed.
2563                  */
2564                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2565                 return -EINVAL;
2566         }
2567
2568         /* Set RTTBCNRC of each queue/pool for vf X  */
2569         for (; queue_idx <= queue_end; queue_idx++) {
2570                 if (0x1 & q_msk)
2571                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2572                 q_msk = q_msk >> 1;
2573         }
2574
2575         return 0;
2576 }
2577
2578 /*
2579  * Configure device link speed and setup link.
2580  * It returns 0 on success.
2581  */
2582 static int
2583 ixgbe_dev_start(struct rte_eth_dev *dev)
2584 {
2585         struct ixgbe_hw *hw =
2586                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587         struct ixgbe_vf_info *vfinfo =
2588                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2589         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2590         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2591         uint32_t intr_vector = 0;
2592         int err, link_up = 0, negotiate = 0;
2593         uint32_t speed = 0;
2594         uint32_t allowed_speeds = 0;
2595         int mask = 0;
2596         int status;
2597         uint16_t vf, idx;
2598         uint32_t *link_speeds;
2599         struct ixgbe_tm_conf *tm_conf =
2600                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2601
2602         PMD_INIT_FUNC_TRACE();
2603
2604         /* IXGBE devices don't support:
2605         *    - half duplex (checked afterwards for valid speeds)
2606         *    - fixed speed: TODO implement
2607         */
2608         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2609                 PMD_INIT_LOG(ERR,
2610                 "Invalid link_speeds for port %u, fix speed not supported",
2611                                 dev->data->port_id);
2612                 return -EINVAL;
2613         }
2614
2615         /* Stop the link setup handler before resetting the HW. */
2616         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2617
2618         /* disable uio/vfio intr/eventfd mapping */
2619         rte_intr_disable(intr_handle);
2620
2621         /* stop adapter */
2622         hw->adapter_stopped = 0;
2623         ixgbe_stop_adapter(hw);
2624
2625         /* reinitialize adapter
2626          * this calls reset and start
2627          */
2628         status = ixgbe_pf_reset_hw(hw);
2629         if (status != 0)
2630                 return -1;
2631         hw->mac.ops.start_hw(hw);
2632         hw->mac.get_link_status = true;
2633
2634         /* configure PF module if SRIOV enabled */
2635         ixgbe_pf_host_configure(dev);
2636
2637         ixgbe_dev_phy_intr_setup(dev);
2638
2639         /* check and configure queue intr-vector mapping */
2640         if ((rte_intr_cap_multiple(intr_handle) ||
2641              !RTE_ETH_DEV_SRIOV(dev).active) &&
2642             dev->data->dev_conf.intr_conf.rxq != 0) {
2643                 intr_vector = dev->data->nb_rx_queues;
2644                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2645                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2646                                         IXGBE_MAX_INTR_QUEUE_NUM);
2647                         return -ENOTSUP;
2648                 }
2649                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2650                         return -1;
2651         }
2652
2653         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2654                 intr_handle->intr_vec =
2655                         rte_zmalloc("intr_vec",
2656                                     dev->data->nb_rx_queues * sizeof(int), 0);
2657                 if (intr_handle->intr_vec == NULL) {
2658                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2659                                      " intr_vec", dev->data->nb_rx_queues);
2660                         return -ENOMEM;
2661                 }
2662         }
2663
2664         /* confiugre msix for sleep until rx interrupt */
2665         ixgbe_configure_msix(dev);
2666
2667         /* initialize transmission unit */
2668         ixgbe_dev_tx_init(dev);
2669
2670         /* This can fail when allocating mbufs for descriptor rings */
2671         err = ixgbe_dev_rx_init(dev);
2672         if (err) {
2673                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2674                 goto error;
2675         }
2676
2677         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2678                 ETH_VLAN_EXTEND_MASK;
2679         err = ixgbe_vlan_offload_config(dev, mask);
2680         if (err) {
2681                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2682                 goto error;
2683         }
2684
2685         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2686                 /* Enable vlan filtering for VMDq */
2687                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2688         }
2689
2690         /* Configure DCB hw */
2691         ixgbe_configure_dcb(dev);
2692
2693         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2694                 err = ixgbe_fdir_configure(dev);
2695                 if (err)
2696                         goto error;
2697         }
2698
2699         /* Restore vf rate limit */
2700         if (vfinfo != NULL) {
2701                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2702                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2703                                 if (vfinfo[vf].tx_rate[idx] != 0)
2704                                         ixgbe_set_vf_rate_limit(
2705                                                 dev, vf,
2706                                                 vfinfo[vf].tx_rate[idx],
2707                                                 1 << idx);
2708         }
2709
2710         ixgbe_restore_statistics_mapping(dev);
2711
2712         err = ixgbe_dev_rxtx_start(dev);
2713         if (err < 0) {
2714                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2715                 goto error;
2716         }
2717
2718         /* Skip link setup if loopback mode is enabled. */
2719         if (dev->data->dev_conf.lpbk_mode != 0) {
2720                 err = ixgbe_check_supported_loopback_mode(dev);
2721                 if (err < 0) {
2722                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2723                         goto error;
2724                 } else {
2725                         goto skip_link_setup;
2726                 }
2727         }
2728
2729         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2730                 err = hw->mac.ops.setup_sfp(hw);
2731                 if (err)
2732                         goto error;
2733         }
2734
2735         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2736                 /* Turn on the copper */
2737                 ixgbe_set_phy_power(hw, true);
2738         } else {
2739                 /* Turn on the laser */
2740                 ixgbe_enable_tx_laser(hw);
2741         }
2742
2743         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2744         if (err)
2745                 goto error;
2746         dev->data->dev_link.link_status = link_up;
2747
2748         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2749         if (err)
2750                 goto error;
2751
2752         switch (hw->mac.type) {
2753         case ixgbe_mac_X550:
2754         case ixgbe_mac_X550EM_x:
2755         case ixgbe_mac_X550EM_a:
2756                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2757                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2758                         ETH_LINK_SPEED_10G;
2759                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2760                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2761                         allowed_speeds = ETH_LINK_SPEED_10M |
2762                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2763                 break;
2764         default:
2765                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2766                         ETH_LINK_SPEED_10G;
2767         }
2768
2769         link_speeds = &dev->data->dev_conf.link_speeds;
2770         if (*link_speeds & ~allowed_speeds) {
2771                 PMD_INIT_LOG(ERR, "Invalid link setting");
2772                 goto error;
2773         }
2774
2775         speed = 0x0;
2776         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2777                 switch (hw->mac.type) {
2778                 case ixgbe_mac_82598EB:
2779                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2780                         break;
2781                 case ixgbe_mac_82599EB:
2782                 case ixgbe_mac_X540:
2783                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2784                         break;
2785                 case ixgbe_mac_X550:
2786                 case ixgbe_mac_X550EM_x:
2787                 case ixgbe_mac_X550EM_a:
2788                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2789                         break;
2790                 default:
2791                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2792                 }
2793         } else {
2794                 if (*link_speeds & ETH_LINK_SPEED_10G)
2795                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2796                 if (*link_speeds & ETH_LINK_SPEED_5G)
2797                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2798                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2799                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2800                 if (*link_speeds & ETH_LINK_SPEED_1G)
2801                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2802                 if (*link_speeds & ETH_LINK_SPEED_100M)
2803                         speed |= IXGBE_LINK_SPEED_100_FULL;
2804                 if (*link_speeds & ETH_LINK_SPEED_10M)
2805                         speed |= IXGBE_LINK_SPEED_10_FULL;
2806         }
2807
2808         err = ixgbe_setup_link(hw, speed, link_up);
2809         if (err)
2810                 goto error;
2811
2812 skip_link_setup:
2813
2814         if (rte_intr_allow_others(intr_handle)) {
2815                 /* check if lsc interrupt is enabled */
2816                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2817                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2818                 else
2819                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2820                 ixgbe_dev_macsec_interrupt_setup(dev);
2821         } else {
2822                 rte_intr_callback_unregister(intr_handle,
2823                                              ixgbe_dev_interrupt_handler, dev);
2824                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2825                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2826                                      " no intr multiplex");
2827         }
2828
2829         /* check if rxq interrupt is enabled */
2830         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2831             rte_intr_dp_is_en(intr_handle))
2832                 ixgbe_dev_rxq_interrupt_setup(dev);
2833
2834         /* enable uio/vfio intr/eventfd mapping */
2835         rte_intr_enable(intr_handle);
2836
2837         /* resume enabled intr since hw reset */
2838         ixgbe_enable_intr(dev);
2839         ixgbe_l2_tunnel_conf(dev);
2840         ixgbe_filter_restore(dev);
2841
2842         if (tm_conf->root && !tm_conf->committed)
2843                 PMD_DRV_LOG(WARNING,
2844                             "please call hierarchy_commit() "
2845                             "before starting the port");
2846
2847         /*
2848          * Update link status right before return, because it may
2849          * start link configuration process in a separate thread.
2850          */
2851         ixgbe_dev_link_update(dev, 0);
2852
2853         return 0;
2854
2855 error:
2856         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2857         ixgbe_dev_clear_queues(dev);
2858         return -EIO;
2859 }
2860
2861 /*
2862  * Stop device: disable rx and tx functions to allow for reconfiguring.
2863  */
2864 static void
2865 ixgbe_dev_stop(struct rte_eth_dev *dev)
2866 {
2867         struct rte_eth_link link;
2868         struct ixgbe_adapter *adapter = dev->data->dev_private;
2869         struct ixgbe_hw *hw =
2870                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         struct ixgbe_vf_info *vfinfo =
2872                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2873         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2874         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2875         int vf;
2876         struct ixgbe_tm_conf *tm_conf =
2877                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2878
2879         PMD_INIT_FUNC_TRACE();
2880
2881         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2882
2883         /* disable interrupts */
2884         ixgbe_disable_intr(hw);
2885
2886         /* reset the NIC */
2887         ixgbe_pf_reset_hw(hw);
2888         hw->adapter_stopped = 0;
2889
2890         /* stop adapter */
2891         ixgbe_stop_adapter(hw);
2892
2893         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2894                 vfinfo[vf].clear_to_send = false;
2895
2896         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2897                 /* Turn off the copper */
2898                 ixgbe_set_phy_power(hw, false);
2899         } else {
2900                 /* Turn off the laser */
2901                 ixgbe_disable_tx_laser(hw);
2902         }
2903
2904         ixgbe_dev_clear_queues(dev);
2905
2906         /* Clear stored conf */
2907         dev->data->scattered_rx = 0;
2908         dev->data->lro = 0;
2909
2910         /* Clear recorded link status */
2911         memset(&link, 0, sizeof(link));
2912         rte_eth_linkstatus_set(dev, &link);
2913
2914         if (!rte_intr_allow_others(intr_handle))
2915                 /* resume to the default handler */
2916                 rte_intr_callback_register(intr_handle,
2917                                            ixgbe_dev_interrupt_handler,
2918                                            (void *)dev);
2919
2920         /* Clean datapath event and queue/vec mapping */
2921         rte_intr_efd_disable(intr_handle);
2922         if (intr_handle->intr_vec != NULL) {
2923                 rte_free(intr_handle->intr_vec);
2924                 intr_handle->intr_vec = NULL;
2925         }
2926
2927         /* reset hierarchy commit */
2928         tm_conf->committed = false;
2929
2930         adapter->rss_reta_updated = 0;
2931 }
2932
2933 /*
2934  * Set device link up: enable tx.
2935  */
2936 static int
2937 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2938 {
2939         struct ixgbe_hw *hw =
2940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941         if (hw->mac.type == ixgbe_mac_82599EB) {
2942 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2943                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2944                         /* Not suported in bypass mode */
2945                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2946                                      "by device id 0x%x", hw->device_id);
2947                         return -ENOTSUP;
2948                 }
2949 #endif
2950         }
2951
2952         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2953                 /* Turn on the copper */
2954                 ixgbe_set_phy_power(hw, true);
2955         } else {
2956                 /* Turn on the laser */
2957                 ixgbe_enable_tx_laser(hw);
2958         }
2959
2960         return 0;
2961 }
2962
2963 /*
2964  * Set device link down: disable tx.
2965  */
2966 static int
2967 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2968 {
2969         struct ixgbe_hw *hw =
2970                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         if (hw->mac.type == ixgbe_mac_82599EB) {
2972 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2973                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2974                         /* Not suported in bypass mode */
2975                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2976                                      "by device id 0x%x", hw->device_id);
2977                         return -ENOTSUP;
2978                 }
2979 #endif
2980         }
2981
2982         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2983                 /* Turn off the copper */
2984                 ixgbe_set_phy_power(hw, false);
2985         } else {
2986                 /* Turn off the laser */
2987                 ixgbe_disable_tx_laser(hw);
2988         }
2989
2990         return 0;
2991 }
2992
2993 /*
2994  * Reset and stop device.
2995  */
2996 static void
2997 ixgbe_dev_close(struct rte_eth_dev *dev)
2998 {
2999         struct ixgbe_hw *hw =
3000                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3001
3002         PMD_INIT_FUNC_TRACE();
3003
3004         ixgbe_pf_reset_hw(hw);
3005
3006         ixgbe_dev_stop(dev);
3007         hw->adapter_stopped = 1;
3008
3009         ixgbe_dev_free_queues(dev);
3010
3011         ixgbe_disable_pcie_master(hw);
3012
3013         /* reprogram the RAR[0] in case user changed it. */
3014         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3015 }
3016
3017 /*
3018  * Reset PF device.
3019  */
3020 static int
3021 ixgbe_dev_reset(struct rte_eth_dev *dev)
3022 {
3023         int ret;
3024
3025         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3026          * its VF to make them align with it. The detailed notification
3027          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3028          * To avoid unexpected behavior in VF, currently reset of PF with
3029          * SR-IOV activation is not supported. It might be supported later.
3030          */
3031         if (dev->data->sriov.active)
3032                 return -ENOTSUP;
3033
3034         ret = eth_ixgbe_dev_uninit(dev);
3035         if (ret)
3036                 return ret;
3037
3038         ret = eth_ixgbe_dev_init(dev, NULL);
3039
3040         return ret;
3041 }
3042
3043 static void
3044 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3045                            struct ixgbe_hw_stats *hw_stats,
3046                            struct ixgbe_macsec_stats *macsec_stats,
3047                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3048                            uint64_t *total_qprc, uint64_t *total_qprdc)
3049 {
3050         uint32_t bprc, lxon, lxoff, total;
3051         uint32_t delta_gprc = 0;
3052         unsigned i;
3053         /* Workaround for RX byte count not including CRC bytes when CRC
3054          * strip is enabled. CRC bytes are removed from counters when crc_strip
3055          * is disabled.
3056          */
3057         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3058                         IXGBE_HLREG0_RXCRCSTRP);
3059
3060         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3061         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3062         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3063         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3064
3065         for (i = 0; i < 8; i++) {
3066                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3067
3068                 /* global total per queue */
3069                 hw_stats->mpc[i] += mp;
3070                 /* Running comprehensive total for stats display */
3071                 *total_missed_rx += hw_stats->mpc[i];
3072                 if (hw->mac.type == ixgbe_mac_82598EB) {
3073                         hw_stats->rnbc[i] +=
3074                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3075                         hw_stats->pxonrxc[i] +=
3076                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3077                         hw_stats->pxoffrxc[i] +=
3078                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3079                 } else {
3080                         hw_stats->pxonrxc[i] +=
3081                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3082                         hw_stats->pxoffrxc[i] +=
3083                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3084                         hw_stats->pxon2offc[i] +=
3085                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3086                 }
3087                 hw_stats->pxontxc[i] +=
3088                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3089                 hw_stats->pxofftxc[i] +=
3090                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3091         }
3092         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3093                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3094                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3095                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3096
3097                 delta_gprc += delta_qprc;
3098
3099                 hw_stats->qprc[i] += delta_qprc;
3100                 hw_stats->qptc[i] += delta_qptc;
3101
3102                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3103                 hw_stats->qbrc[i] +=
3104                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3105                 if (crc_strip == 0)
3106                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3107
3108                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3109                 hw_stats->qbtc[i] +=
3110                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3111
3112                 hw_stats->qprdc[i] += delta_qprdc;
3113                 *total_qprdc += hw_stats->qprdc[i];
3114
3115                 *total_qprc += hw_stats->qprc[i];
3116                 *total_qbrc += hw_stats->qbrc[i];
3117         }
3118         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3119         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3120         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3121
3122         /*
3123          * An errata states that gprc actually counts good + missed packets:
3124          * Workaround to set gprc to summated queue packet receives
3125          */
3126         hw_stats->gprc = *total_qprc;
3127
3128         if (hw->mac.type != ixgbe_mac_82598EB) {
3129                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3130                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3131                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3132                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3133                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3134                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3135                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3136                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3137         } else {
3138                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3139                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3140                 /* 82598 only has a counter in the high register */
3141                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3142                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3143                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3144         }
3145         uint64_t old_tpr = hw_stats->tpr;
3146
3147         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3148         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3149
3150         if (crc_strip == 0)
3151                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3152
3153         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3154         hw_stats->gptc += delta_gptc;
3155         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3156         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3157
3158         /*
3159          * Workaround: mprc hardware is incorrectly counting
3160          * broadcasts, so for now we subtract those.
3161          */
3162         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3163         hw_stats->bprc += bprc;
3164         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3165         if (hw->mac.type == ixgbe_mac_82598EB)
3166                 hw_stats->mprc -= bprc;
3167
3168         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3169         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3170         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3171         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3172         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3173         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3174
3175         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3176         hw_stats->lxontxc += lxon;
3177         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3178         hw_stats->lxofftxc += lxoff;
3179         total = lxon + lxoff;
3180
3181         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3182         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3183         hw_stats->gptc -= total;
3184         hw_stats->mptc -= total;
3185         hw_stats->ptc64 -= total;
3186         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3187
3188         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3189         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3190         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3191         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3192         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3193         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3194         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3195         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3196         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3197         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3198         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3199         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3200         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3201         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3202         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3203         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3204         /* Only read FCOE on 82599 */
3205         if (hw->mac.type != ixgbe_mac_82598EB) {
3206                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3207                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3208                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3209                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3210                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3211         }
3212
3213         /* Flow Director Stats registers */
3214         if (hw->mac.type != ixgbe_mac_82598EB) {
3215                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3216                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3217                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3218                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3219                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3220                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3221                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3222                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3223                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3224                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3225         }
3226         /* MACsec Stats registers */
3227         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3228         macsec_stats->out_pkts_encrypted +=
3229                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3230         macsec_stats->out_pkts_protected +=
3231                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3232         macsec_stats->out_octets_encrypted +=
3233                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3234         macsec_stats->out_octets_protected +=
3235                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3236         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3237         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3238         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3239         macsec_stats->in_pkts_unknownsci +=
3240                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3241         macsec_stats->in_octets_decrypted +=
3242                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3243         macsec_stats->in_octets_validated +=
3244                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3245         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3246         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3247         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3248         for (i = 0; i < 2; i++) {
3249                 macsec_stats->in_pkts_ok +=
3250                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3251                 macsec_stats->in_pkts_invalid +=
3252                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3253                 macsec_stats->in_pkts_notvalid +=
3254                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3255         }
3256         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3257         macsec_stats->in_pkts_notusingsa +=
3258                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3259 }
3260
3261 /*
3262  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3263  */
3264 static int
3265 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3266 {
3267         struct ixgbe_hw *hw =
3268                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3269         struct ixgbe_hw_stats *hw_stats =
3270                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3271         struct ixgbe_macsec_stats *macsec_stats =
3272                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3273                                 dev->data->dev_private);
3274         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3275         unsigned i;
3276
3277         total_missed_rx = 0;
3278         total_qbrc = 0;
3279         total_qprc = 0;
3280         total_qprdc = 0;
3281
3282         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3283                         &total_qbrc, &total_qprc, &total_qprdc);
3284
3285         if (stats == NULL)
3286                 return -EINVAL;
3287
3288         /* Fill out the rte_eth_stats statistics structure */
3289         stats->ipackets = total_qprc;
3290         stats->ibytes = total_qbrc;
3291         stats->opackets = hw_stats->gptc;
3292         stats->obytes = hw_stats->gotc;
3293
3294         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3295                 stats->q_ipackets[i] = hw_stats->qprc[i];
3296                 stats->q_opackets[i] = hw_stats->qptc[i];
3297                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3298                 stats->q_obytes[i] = hw_stats->qbtc[i];
3299                 stats->q_errors[i] = hw_stats->qprdc[i];
3300         }
3301
3302         /* Rx Errors */
3303         stats->imissed  = total_missed_rx;
3304         stats->ierrors  = hw_stats->crcerrs +
3305                           hw_stats->mspdc +
3306                           hw_stats->rlec +
3307                           hw_stats->ruc +
3308                           hw_stats->roc +
3309                           hw_stats->illerrc +
3310                           hw_stats->errbc +
3311                           hw_stats->rfc +
3312                           hw_stats->fccrc +
3313                           hw_stats->fclast;
3314
3315         /* Tx Errors */
3316         stats->oerrors  = 0;
3317         return 0;
3318 }
3319
3320 static int
3321 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3322 {
3323         struct ixgbe_hw_stats *stats =
3324                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3325
3326         /* HW registers are cleared on read */
3327         ixgbe_dev_stats_get(dev, NULL);
3328
3329         /* Reset software totals */
3330         memset(stats, 0, sizeof(*stats));
3331
3332         return 0;
3333 }
3334
3335 /* This function calculates the number of xstats based on the current config */
3336 static unsigned
3337 ixgbe_xstats_calc_num(void) {
3338         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3339                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3340                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3341 }
3342
3343 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3344         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3345 {
3346         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3347         unsigned stat, i, count;
3348
3349         if (xstats_names != NULL) {
3350                 count = 0;
3351
3352                 /* Note: limit >= cnt_stats checked upstream
3353                  * in rte_eth_xstats_names()
3354                  */
3355
3356                 /* Extended stats from ixgbe_hw_stats */
3357                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3358                         strlcpy(xstats_names[count].name,
3359                                 rte_ixgbe_stats_strings[i].name,
3360                                 sizeof(xstats_names[count].name));
3361                         count++;
3362                 }
3363
3364                 /* MACsec Stats */
3365                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3366                         strlcpy(xstats_names[count].name,
3367                                 rte_ixgbe_macsec_strings[i].name,
3368                                 sizeof(xstats_names[count].name));
3369                         count++;
3370                 }
3371
3372                 /* RX Priority Stats */
3373                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3374                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3375                                 snprintf(xstats_names[count].name,
3376                                         sizeof(xstats_names[count].name),
3377                                         "rx_priority%u_%s", i,
3378                                         rte_ixgbe_rxq_strings[stat].name);
3379                                 count++;
3380                         }
3381                 }
3382
3383                 /* TX Priority Stats */
3384                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3385                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3386                                 snprintf(xstats_names[count].name,
3387                                         sizeof(xstats_names[count].name),
3388                                         "tx_priority%u_%s", i,
3389                                         rte_ixgbe_txq_strings[stat].name);
3390                                 count++;
3391                         }
3392                 }
3393         }
3394         return cnt_stats;
3395 }
3396
3397 static int ixgbe_dev_xstats_get_names_by_id(
3398         struct rte_eth_dev *dev,
3399         struct rte_eth_xstat_name *xstats_names,
3400         const uint64_t *ids,
3401         unsigned int limit)
3402 {
3403         if (!ids) {
3404                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3405                 unsigned int stat, i, count;
3406
3407                 if (xstats_names != NULL) {
3408                         count = 0;
3409
3410                         /* Note: limit >= cnt_stats checked upstream
3411                          * in rte_eth_xstats_names()
3412                          */
3413
3414                         /* Extended stats from ixgbe_hw_stats */
3415                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3416                                 strlcpy(xstats_names[count].name,
3417                                         rte_ixgbe_stats_strings[i].name,
3418                                         sizeof(xstats_names[count].name));
3419                                 count++;
3420                         }
3421
3422                         /* MACsec Stats */
3423                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3424                                 strlcpy(xstats_names[count].name,
3425                                         rte_ixgbe_macsec_strings[i].name,
3426                                         sizeof(xstats_names[count].name));
3427                                 count++;
3428                         }
3429
3430                         /* RX Priority Stats */
3431                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3432                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3433                                         snprintf(xstats_names[count].name,
3434                                             sizeof(xstats_names[count].name),
3435                                             "rx_priority%u_%s", i,
3436                                             rte_ixgbe_rxq_strings[stat].name);
3437                                         count++;
3438                                 }
3439                         }
3440
3441                         /* TX Priority Stats */
3442                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3443                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3444                                         snprintf(xstats_names[count].name,
3445                                             sizeof(xstats_names[count].name),
3446                                             "tx_priority%u_%s", i,
3447                                             rte_ixgbe_txq_strings[stat].name);
3448                                         count++;
3449                                 }
3450                         }
3451                 }
3452                 return cnt_stats;
3453         }
3454
3455         uint16_t i;
3456         uint16_t size = ixgbe_xstats_calc_num();
3457         struct rte_eth_xstat_name xstats_names_copy[size];
3458
3459         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3460                         size);
3461
3462         for (i = 0; i < limit; i++) {
3463                 if (ids[i] >= size) {
3464                         PMD_INIT_LOG(ERR, "id value isn't valid");
3465                         return -1;
3466                 }
3467                 strcpy(xstats_names[i].name,
3468                                 xstats_names_copy[ids[i]].name);
3469         }
3470         return limit;
3471 }
3472
3473 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3474         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3475 {
3476         unsigned i;
3477
3478         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3479                 return -ENOMEM;
3480
3481         if (xstats_names != NULL)
3482                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3483                         strlcpy(xstats_names[i].name,
3484                                 rte_ixgbevf_stats_strings[i].name,
3485                                 sizeof(xstats_names[i].name));
3486         return IXGBEVF_NB_XSTATS;
3487 }
3488
3489 static int
3490 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3491                                          unsigned n)
3492 {
3493         struct ixgbe_hw *hw =
3494                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3495         struct ixgbe_hw_stats *hw_stats =
3496                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3497         struct ixgbe_macsec_stats *macsec_stats =
3498                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3499                                 dev->data->dev_private);
3500         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3501         unsigned i, stat, count = 0;
3502
3503         count = ixgbe_xstats_calc_num();
3504
3505         if (n < count)
3506                 return count;
3507
3508         total_missed_rx = 0;
3509         total_qbrc = 0;
3510         total_qprc = 0;
3511         total_qprdc = 0;
3512
3513         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3514                         &total_qbrc, &total_qprc, &total_qprdc);
3515
3516         /* If this is a reset xstats is NULL, and we have cleared the
3517          * registers by reading them.
3518          */
3519         if (!xstats)
3520                 return 0;
3521
3522         /* Extended stats from ixgbe_hw_stats */
3523         count = 0;
3524         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3525                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3526                                 rte_ixgbe_stats_strings[i].offset);
3527                 xstats[count].id = count;
3528                 count++;
3529         }
3530
3531         /* MACsec Stats */
3532         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3533                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3534                                 rte_ixgbe_macsec_strings[i].offset);
3535                 xstats[count].id = count;
3536                 count++;
3537         }
3538
3539         /* RX Priority Stats */
3540         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3541                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3542                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3543                                         rte_ixgbe_rxq_strings[stat].offset +
3544                                         (sizeof(uint64_t) * i));
3545                         xstats[count].id = count;
3546                         count++;
3547                 }
3548         }
3549
3550         /* TX Priority Stats */
3551         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3552                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3553                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3554                                         rte_ixgbe_txq_strings[stat].offset +
3555                                         (sizeof(uint64_t) * i));
3556                         xstats[count].id = count;
3557                         count++;
3558                 }
3559         }
3560         return count;
3561 }
3562
3563 static int
3564 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3565                 uint64_t *values, unsigned int n)
3566 {
3567         if (!ids) {
3568                 struct ixgbe_hw *hw =
3569                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570                 struct ixgbe_hw_stats *hw_stats =
3571                                 IXGBE_DEV_PRIVATE_TO_STATS(
3572                                                 dev->data->dev_private);
3573                 struct ixgbe_macsec_stats *macsec_stats =
3574                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3575                                         dev->data->dev_private);
3576                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3577                 unsigned int i, stat, count = 0;
3578
3579                 count = ixgbe_xstats_calc_num();
3580
3581                 if (!ids && n < count)
3582                         return count;
3583
3584                 total_missed_rx = 0;
3585                 total_qbrc = 0;
3586                 total_qprc = 0;
3587                 total_qprdc = 0;
3588
3589                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3590                                 &total_missed_rx, &total_qbrc, &total_qprc,
3591                                 &total_qprdc);
3592
3593                 /* If this is a reset xstats is NULL, and we have cleared the
3594                  * registers by reading them.
3595                  */
3596                 if (!ids && !values)
3597                         return 0;
3598
3599                 /* Extended stats from ixgbe_hw_stats */
3600                 count = 0;
3601                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3602                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3603                                         rte_ixgbe_stats_strings[i].offset);
3604                         count++;
3605                 }
3606
3607                 /* MACsec Stats */
3608                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3609                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3610                                         rte_ixgbe_macsec_strings[i].offset);
3611                         count++;
3612                 }
3613
3614                 /* RX Priority Stats */
3615                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3616                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3617                                 values[count] =
3618                                         *(uint64_t *)(((char *)hw_stats) +
3619                                         rte_ixgbe_rxq_strings[stat].offset +
3620                                         (sizeof(uint64_t) * i));
3621                                 count++;
3622                         }
3623                 }
3624
3625                 /* TX Priority Stats */
3626                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3627                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3628                                 values[count] =
3629                                         *(uint64_t *)(((char *)hw_stats) +
3630                                         rte_ixgbe_txq_strings[stat].offset +
3631                                         (sizeof(uint64_t) * i));
3632                                 count++;
3633                         }
3634                 }
3635                 return count;
3636         }
3637
3638         uint16_t i;
3639         uint16_t size = ixgbe_xstats_calc_num();
3640         uint64_t values_copy[size];
3641
3642         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3643
3644         for (i = 0; i < n; i++) {
3645                 if (ids[i] >= size) {
3646                         PMD_INIT_LOG(ERR, "id value isn't valid");
3647                         return -1;
3648                 }
3649                 values[i] = values_copy[ids[i]];
3650         }
3651         return n;
3652 }
3653
3654 static int
3655 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3656 {
3657         struct ixgbe_hw_stats *stats =
3658                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3659         struct ixgbe_macsec_stats *macsec_stats =
3660                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3661                                 dev->data->dev_private);
3662
3663         unsigned count = ixgbe_xstats_calc_num();
3664
3665         /* HW registers are cleared on read */
3666         ixgbe_dev_xstats_get(dev, NULL, count);
3667
3668         /* Reset software totals */
3669         memset(stats, 0, sizeof(*stats));
3670         memset(macsec_stats, 0, sizeof(*macsec_stats));
3671
3672         return 0;
3673 }
3674
3675 static void
3676 ixgbevf_update_stats(struct rte_eth_dev *dev)
3677 {
3678         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3679         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3680                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3681
3682         /* Good Rx packet, include VF loopback */
3683         UPDATE_VF_STAT(IXGBE_VFGPRC,
3684             hw_stats->last_vfgprc, hw_stats->vfgprc);
3685
3686         /* Good Rx octets, include VF loopback */
3687         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3688             hw_stats->last_vfgorc, hw_stats->vfgorc);
3689
3690         /* Good Tx packet, include VF loopback */
3691         UPDATE_VF_STAT(IXGBE_VFGPTC,
3692             hw_stats->last_vfgptc, hw_stats->vfgptc);
3693
3694         /* Good Tx octets, include VF loopback */
3695         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3696             hw_stats->last_vfgotc, hw_stats->vfgotc);
3697
3698         /* Rx Multicst Packet */
3699         UPDATE_VF_STAT(IXGBE_VFMPRC,
3700             hw_stats->last_vfmprc, hw_stats->vfmprc);
3701 }
3702
3703 static int
3704 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3705                        unsigned n)
3706 {
3707         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3708                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3709         unsigned i;
3710
3711         if (n < IXGBEVF_NB_XSTATS)
3712                 return IXGBEVF_NB_XSTATS;
3713
3714         ixgbevf_update_stats(dev);
3715
3716         if (!xstats)
3717                 return 0;
3718
3719         /* Extended stats */
3720         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3721                 xstats[i].id = i;
3722                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3723                         rte_ixgbevf_stats_strings[i].offset);
3724         }
3725
3726         return IXGBEVF_NB_XSTATS;
3727 }
3728
3729 static int
3730 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3731 {
3732         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3733                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3734
3735         ixgbevf_update_stats(dev);
3736
3737         if (stats == NULL)
3738                 return -EINVAL;
3739
3740         stats->ipackets = hw_stats->vfgprc;
3741         stats->ibytes = hw_stats->vfgorc;
3742         stats->opackets = hw_stats->vfgptc;
3743         stats->obytes = hw_stats->vfgotc;
3744         return 0;
3745 }
3746
3747 static int
3748 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3749 {
3750         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3751                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3752
3753         /* Sync HW register to the last stats */
3754         ixgbevf_dev_stats_get(dev, NULL);
3755
3756         /* reset HW current stats*/
3757         hw_stats->vfgprc = 0;
3758         hw_stats->vfgorc = 0;
3759         hw_stats->vfgptc = 0;
3760         hw_stats->vfgotc = 0;
3761
3762         return 0;
3763 }
3764
3765 static int
3766 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3767 {
3768         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769         u16 eeprom_verh, eeprom_verl;
3770         u32 etrack_id;
3771         int ret;
3772
3773         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3774         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3775
3776         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3777         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3778
3779         ret += 1; /* add the size of '\0' */
3780         if (fw_size < (u32)ret)
3781                 return ret;
3782         else
3783                 return 0;
3784 }
3785
3786 static int
3787 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3788 {
3789         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3792
3793         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3794         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3795         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3796                 /*
3797                  * When DCB/VT is off, maximum number of queues changes,
3798                  * except for 82598EB, which remains constant.
3799                  */
3800                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3801                                 hw->mac.type != ixgbe_mac_82598EB)
3802                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3803         }
3804         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3805         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3806         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3807         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3808         dev_info->max_vfs = pci_dev->max_vfs;
3809         if (hw->mac.type == ixgbe_mac_82598EB)
3810                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3811         else
3812                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3813         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3814         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3815         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3816         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3817         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3818                                      dev_info->rx_queue_offload_capa);
3819         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3820         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3821
3822         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3823                 .rx_thresh = {
3824                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3825                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3826                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3827                 },
3828                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3829                 .rx_drop_en = 0,
3830                 .offloads = 0,
3831         };
3832
3833         dev_info->default_txconf = (struct rte_eth_txconf) {
3834                 .tx_thresh = {
3835                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3836                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3837                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3838                 },
3839                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3840                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3841                 .offloads = 0,
3842         };
3843
3844         dev_info->rx_desc_lim = rx_desc_lim;
3845         dev_info->tx_desc_lim = tx_desc_lim;
3846
3847         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3848         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3849         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3850
3851         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3852         if (hw->mac.type == ixgbe_mac_X540 ||
3853             hw->mac.type == ixgbe_mac_X540_vf ||
3854             hw->mac.type == ixgbe_mac_X550 ||
3855             hw->mac.type == ixgbe_mac_X550_vf) {
3856                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3857         }
3858         if (hw->mac.type == ixgbe_mac_X550) {
3859                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3860                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3861         }
3862
3863         /* Driver-preferred Rx/Tx parameters */
3864         dev_info->default_rxportconf.burst_size = 32;
3865         dev_info->default_txportconf.burst_size = 32;
3866         dev_info->default_rxportconf.nb_queues = 1;
3867         dev_info->default_txportconf.nb_queues = 1;
3868         dev_info->default_rxportconf.ring_size = 256;
3869         dev_info->default_txportconf.ring_size = 256;
3870
3871         return 0;
3872 }
3873
3874 static const uint32_t *
3875 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3876 {
3877         static const uint32_t ptypes[] = {
3878                 /* For non-vec functions,
3879                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3880                  * for vec functions,
3881                  * refers to _recv_raw_pkts_vec().
3882                  */
3883                 RTE_PTYPE_L2_ETHER,
3884                 RTE_PTYPE_L3_IPV4,
3885                 RTE_PTYPE_L3_IPV4_EXT,
3886                 RTE_PTYPE_L3_IPV6,
3887                 RTE_PTYPE_L3_IPV6_EXT,
3888                 RTE_PTYPE_L4_SCTP,
3889                 RTE_PTYPE_L4_TCP,
3890                 RTE_PTYPE_L4_UDP,
3891                 RTE_PTYPE_TUNNEL_IP,
3892                 RTE_PTYPE_INNER_L3_IPV6,
3893                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3894                 RTE_PTYPE_INNER_L4_TCP,
3895                 RTE_PTYPE_INNER_L4_UDP,
3896                 RTE_PTYPE_UNKNOWN
3897         };
3898
3899         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3900             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3901             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3902             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3903                 return ptypes;
3904
3905 #if defined(RTE_ARCH_X86)
3906         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3907             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3908                 return ptypes;
3909 #endif
3910         return NULL;
3911 }
3912
3913 static int
3914 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3915                      struct rte_eth_dev_info *dev_info)
3916 {
3917         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3918         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3919
3920         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3921         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3922         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3923         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3924         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3925         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3926         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3927         dev_info->max_vfs = pci_dev->max_vfs;
3928         if (hw->mac.type == ixgbe_mac_82598EB)
3929                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3930         else
3931                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3932         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3933         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3934                                      dev_info->rx_queue_offload_capa);
3935         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3936         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3937         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3938         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3939         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3940
3941         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3942                 .rx_thresh = {
3943                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3944                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3945                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3946                 },
3947                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3948                 .rx_drop_en = 0,
3949                 .offloads = 0,
3950         };
3951
3952         dev_info->default_txconf = (struct rte_eth_txconf) {
3953                 .tx_thresh = {
3954                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3955                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3956                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3957                 },
3958                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3959                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3960                 .offloads = 0,
3961         };
3962
3963         dev_info->rx_desc_lim = rx_desc_lim;
3964         dev_info->tx_desc_lim = tx_desc_lim;
3965
3966         return 0;
3967 }
3968
3969 static int
3970 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3971                    int *link_up, int wait_to_complete)
3972 {
3973         struct ixgbe_adapter *adapter = container_of(hw,
3974                                                      struct ixgbe_adapter, hw);
3975         struct ixgbe_mbx_info *mbx = &hw->mbx;
3976         struct ixgbe_mac_info *mac = &hw->mac;
3977         uint32_t links_reg, in_msg;
3978         int ret_val = 0;
3979
3980         /* If we were hit with a reset drop the link */
3981         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3982                 mac->get_link_status = true;
3983
3984         if (!mac->get_link_status)
3985                 goto out;
3986
3987         /* if link status is down no point in checking to see if pf is up */
3988         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3989         if (!(links_reg & IXGBE_LINKS_UP))
3990                 goto out;
3991
3992         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3993          * before the link status is correct
3994          */
3995         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3996                 int i;
3997
3998                 for (i = 0; i < 5; i++) {
3999                         rte_delay_us(100);
4000                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4001
4002                         if (!(links_reg & IXGBE_LINKS_UP))
4003                                 goto out;
4004                 }
4005         }
4006
4007         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4008         case IXGBE_LINKS_SPEED_10G_82599:
4009                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4010                 if (hw->mac.type >= ixgbe_mac_X550) {
4011                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4012                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4013                 }
4014                 break;
4015         case IXGBE_LINKS_SPEED_1G_82599:
4016                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4017                 break;
4018         case IXGBE_LINKS_SPEED_100_82599:
4019                 *speed = IXGBE_LINK_SPEED_100_FULL;
4020                 if (hw->mac.type == ixgbe_mac_X550) {
4021                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4022                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4023                 }
4024                 break;
4025         case IXGBE_LINKS_SPEED_10_X550EM_A:
4026                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4027                 /* Since Reserved in older MAC's */
4028                 if (hw->mac.type >= ixgbe_mac_X550)
4029                         *speed = IXGBE_LINK_SPEED_10_FULL;
4030                 break;
4031         default:
4032                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4033         }
4034
4035         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4036                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4037                         mac->get_link_status = true;
4038                 else
4039                         mac->get_link_status = false;
4040
4041                 goto out;
4042         }
4043
4044         /* if the read failed it could just be a mailbox collision, best wait
4045          * until we are called again and don't report an error
4046          */
4047         if (mbx->ops.read(hw, &in_msg, 1, 0))
4048                 goto out;
4049
4050         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4051                 /* msg is not CTS and is NACK we must have lost CTS status */
4052                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4053                         mac->get_link_status = false;
4054                 goto out;
4055         }
4056
4057         /* the pf is talking, if we timed out in the past we reinit */
4058         if (!mbx->timeout) {
4059                 ret_val = -1;
4060                 goto out;
4061         }
4062
4063         /* if we passed all the tests above then the link is up and we no
4064          * longer need to check for link
4065          */
4066         mac->get_link_status = false;
4067
4068 out:
4069         *link_up = !mac->get_link_status;
4070         return ret_val;
4071 }
4072
4073 static void
4074 ixgbe_dev_setup_link_alarm_handler(void *param)
4075 {
4076         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4077         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4078         struct ixgbe_interrupt *intr =
4079                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4080         u32 speed;
4081         bool autoneg = false;
4082
4083         speed = hw->phy.autoneg_advertised;
4084         if (!speed)
4085                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4086
4087         ixgbe_setup_link(hw, speed, true);
4088
4089         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4090 }
4091
4092 /* return 0 means link status changed, -1 means not changed */
4093 int
4094 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4095                             int wait_to_complete, int vf)
4096 {
4097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4098         struct rte_eth_link link;
4099         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4100         struct ixgbe_interrupt *intr =
4101                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4102         int link_up;
4103         int diag;
4104         int wait = 1;
4105
4106         memset(&link, 0, sizeof(link));
4107         link.link_status = ETH_LINK_DOWN;
4108         link.link_speed = ETH_SPEED_NUM_NONE;
4109         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4110         link.link_autoneg = ETH_LINK_AUTONEG;
4111
4112         hw->mac.get_link_status = true;
4113
4114         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4115                 return rte_eth_linkstatus_set(dev, &link);
4116
4117         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4118         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4119                 wait = 0;
4120
4121         if (vf)
4122                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4123         else
4124                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4125
4126         if (diag != 0) {
4127                 link.link_speed = ETH_SPEED_NUM_100M;
4128                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4129                 return rte_eth_linkstatus_set(dev, &link);
4130         }
4131
4132         if (link_up == 0) {
4133                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4134                         intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4135                         rte_eal_alarm_set(10,
4136                                 ixgbe_dev_setup_link_alarm_handler, dev);
4137                 }
4138                 return rte_eth_linkstatus_set(dev, &link);
4139         }
4140
4141         link.link_status = ETH_LINK_UP;
4142         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4143
4144         switch (link_speed) {
4145         default:
4146         case IXGBE_LINK_SPEED_UNKNOWN:
4147                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4148                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4149                         link.link_speed = ETH_SPEED_NUM_10M;
4150                 else
4151                         link.link_speed = ETH_SPEED_NUM_100M;
4152                 break;
4153
4154         case IXGBE_LINK_SPEED_100_FULL:
4155                 link.link_speed = ETH_SPEED_NUM_100M;
4156                 break;
4157
4158         case IXGBE_LINK_SPEED_1GB_FULL:
4159                 link.link_speed = ETH_SPEED_NUM_1G;
4160                 break;
4161
4162         case IXGBE_LINK_SPEED_2_5GB_FULL:
4163                 link.link_speed = ETH_SPEED_NUM_2_5G;
4164                 break;
4165
4166         case IXGBE_LINK_SPEED_5GB_FULL:
4167                 link.link_speed = ETH_SPEED_NUM_5G;
4168                 break;
4169
4170         case IXGBE_LINK_SPEED_10GB_FULL:
4171                 link.link_speed = ETH_SPEED_NUM_10G;
4172                 break;
4173         }
4174
4175         return rte_eth_linkstatus_set(dev, &link);
4176 }
4177
4178 static int
4179 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4180 {
4181         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4182 }
4183
4184 static int
4185 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4186 {
4187         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4188 }
4189
4190 static int
4191 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4192 {
4193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4194         uint32_t fctrl;
4195
4196         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4197         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4198         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4199
4200         return 0;
4201 }
4202
4203 static int
4204 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4205 {
4206         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4207         uint32_t fctrl;
4208
4209         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4210         fctrl &= (~IXGBE_FCTRL_UPE);
4211         if (dev->data->all_multicast == 1)
4212                 fctrl |= IXGBE_FCTRL_MPE;
4213         else
4214                 fctrl &= (~IXGBE_FCTRL_MPE);
4215         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4216
4217         return 0;
4218 }
4219
4220 static void
4221 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4222 {
4223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4224         uint32_t fctrl;
4225
4226         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4227         fctrl |= IXGBE_FCTRL_MPE;
4228         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4229 }
4230
4231 static void
4232 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4233 {
4234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4235         uint32_t fctrl;
4236
4237         if (dev->data->promiscuous == 1)
4238                 return; /* must remain in all_multicast mode */
4239
4240         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4241         fctrl &= (~IXGBE_FCTRL_MPE);
4242         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4243 }
4244
4245 /**
4246  * It clears the interrupt causes and enables the interrupt.
4247  * It will be called once only during nic initialized.
4248  *
4249  * @param dev
4250  *  Pointer to struct rte_eth_dev.
4251  * @param on
4252  *  Enable or Disable.
4253  *
4254  * @return
4255  *  - On success, zero.
4256  *  - On failure, a negative value.
4257  */
4258 static int
4259 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4260 {
4261         struct ixgbe_interrupt *intr =
4262                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4263
4264         ixgbe_dev_link_status_print(dev);
4265         if (on)
4266                 intr->mask |= IXGBE_EICR_LSC;
4267         else
4268                 intr->mask &= ~IXGBE_EICR_LSC;
4269
4270         return 0;
4271 }
4272
4273 /**
4274  * It clears the interrupt causes and enables the interrupt.
4275  * It will be called once only during nic initialized.
4276  *
4277  * @param dev
4278  *  Pointer to struct rte_eth_dev.
4279  *
4280  * @return
4281  *  - On success, zero.
4282  *  - On failure, a negative value.
4283  */
4284 static int
4285 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4286 {
4287         struct ixgbe_interrupt *intr =
4288                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4289
4290         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4291
4292         return 0;
4293 }
4294
4295 /**
4296  * It clears the interrupt causes and enables the interrupt.
4297  * It will be called once only during nic initialized.
4298  *
4299  * @param dev
4300  *  Pointer to struct rte_eth_dev.
4301  *
4302  * @return
4303  *  - On success, zero.
4304  *  - On failure, a negative value.
4305  */
4306 static int
4307 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4308 {
4309         struct ixgbe_interrupt *intr =
4310                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4311
4312         intr->mask |= IXGBE_EICR_LINKSEC;
4313
4314         return 0;
4315 }
4316
4317 /*
4318  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4319  *
4320  * @param dev
4321  *  Pointer to struct rte_eth_dev.
4322  *
4323  * @return
4324  *  - On success, zero.
4325  *  - On failure, a negative value.
4326  */
4327 static int
4328 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4329 {
4330         uint32_t eicr;
4331         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4332         struct ixgbe_interrupt *intr =
4333                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4334
4335         /* clear all cause mask */
4336         ixgbe_disable_intr(hw);
4337
4338         /* read-on-clear nic registers here */
4339         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4340         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4341
4342         intr->flags = 0;
4343
4344         /* set flag for async link update */
4345         if (eicr & IXGBE_EICR_LSC)
4346                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4347
4348         if (eicr & IXGBE_EICR_MAILBOX)
4349                 intr->flags |= IXGBE_FLAG_MAILBOX;
4350
4351         if (eicr & IXGBE_EICR_LINKSEC)
4352                 intr->flags |= IXGBE_FLAG_MACSEC;
4353
4354         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4355             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4356             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4357                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4358
4359         return 0;
4360 }
4361
4362 /**
4363  * It gets and then prints the link status.
4364  *
4365  * @param dev
4366  *  Pointer to struct rte_eth_dev.
4367  *
4368  * @return
4369  *  - On success, zero.
4370  *  - On failure, a negative value.
4371  */
4372 static void
4373 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4374 {
4375         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4376         struct rte_eth_link link;
4377
4378         rte_eth_linkstatus_get(dev, &link);
4379
4380         if (link.link_status) {
4381                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4382                                         (int)(dev->data->port_id),
4383                                         (unsigned)link.link_speed,
4384                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4385                                         "full-duplex" : "half-duplex");
4386         } else {
4387                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4388                                 (int)(dev->data->port_id));
4389         }
4390         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4391                                 pci_dev->addr.domain,
4392                                 pci_dev->addr.bus,
4393                                 pci_dev->addr.devid,
4394                                 pci_dev->addr.function);
4395 }
4396
4397 /*
4398  * It executes link_update after knowing an interrupt occurred.
4399  *
4400  * @param dev
4401  *  Pointer to struct rte_eth_dev.
4402  *
4403  * @return
4404  *  - On success, zero.
4405  *  - On failure, a negative value.
4406  */
4407 static int
4408 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4409 {
4410         struct ixgbe_interrupt *intr =
4411                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4412         int64_t timeout;
4413         struct ixgbe_hw *hw =
4414                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415
4416         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4417
4418         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4419                 ixgbe_pf_mbx_process(dev);
4420                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4421         }
4422
4423         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4424                 ixgbe_handle_lasi(hw);
4425                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4426         }
4427
4428         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4429                 struct rte_eth_link link;
4430
4431                 /* get the link status before link update, for predicting later */
4432                 rte_eth_linkstatus_get(dev, &link);
4433
4434                 ixgbe_dev_link_update(dev, 0);
4435
4436                 /* likely to up */
4437                 if (!link.link_status)
4438                         /* handle it 1 sec later, wait it being stable */
4439                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4440                 /* likely to down */
4441                 else
4442                         /* handle it 4 sec later, wait it being stable */
4443                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4444
4445                 ixgbe_dev_link_status_print(dev);
4446                 if (rte_eal_alarm_set(timeout * 1000,
4447                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4448                         PMD_DRV_LOG(ERR, "Error setting alarm");
4449                 else {
4450                         /* remember original mask */
4451                         intr->mask_original = intr->mask;
4452                         /* only disable lsc interrupt */
4453                         intr->mask &= ~IXGBE_EIMS_LSC;
4454                 }
4455         }
4456
4457         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4458         ixgbe_enable_intr(dev);
4459
4460         return 0;
4461 }
4462
4463 /**
4464  * Interrupt handler which shall be registered for alarm callback for delayed
4465  * handling specific interrupt to wait for the stable nic state. As the
4466  * NIC interrupt state is not stable for ixgbe after link is just down,
4467  * it needs to wait 4 seconds to get the stable status.
4468  *
4469  * @param handle
4470  *  Pointer to interrupt handle.
4471  * @param param
4472  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4473  *
4474  * @return
4475  *  void
4476  */
4477 static void
4478 ixgbe_dev_interrupt_delayed_handler(void *param)
4479 {
4480         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4481         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4483         struct ixgbe_interrupt *intr =
4484                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4485         struct ixgbe_hw *hw =
4486                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4487         uint32_t eicr;
4488
4489         ixgbe_disable_intr(hw);
4490
4491         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4492         if (eicr & IXGBE_EICR_MAILBOX)
4493                 ixgbe_pf_mbx_process(dev);
4494
4495         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4496                 ixgbe_handle_lasi(hw);
4497                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4498         }
4499
4500         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4501                 ixgbe_dev_link_update(dev, 0);
4502                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4503                 ixgbe_dev_link_status_print(dev);
4504                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4505                                               NULL);
4506         }
4507
4508         if (intr->flags & IXGBE_FLAG_MACSEC) {
4509                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4510                                               NULL);
4511                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4512         }
4513
4514         /* restore original mask */
4515         intr->mask = intr->mask_original;
4516         intr->mask_original = 0;
4517
4518         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4519         ixgbe_enable_intr(dev);
4520         rte_intr_ack(intr_handle);
4521 }
4522
4523 /**
4524  * Interrupt handler triggered by NIC  for handling
4525  * specific interrupt.
4526  *
4527  * @param handle
4528  *  Pointer to interrupt handle.
4529  * @param param
4530  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4531  *
4532  * @return
4533  *  void
4534  */
4535 static void
4536 ixgbe_dev_interrupt_handler(void *param)
4537 {
4538         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4539
4540         ixgbe_dev_interrupt_get_status(dev);
4541         ixgbe_dev_interrupt_action(dev);
4542 }
4543
4544 static int
4545 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4546 {
4547         struct ixgbe_hw *hw;
4548
4549         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4550         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4551 }
4552
4553 static int
4554 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4555 {
4556         struct ixgbe_hw *hw;
4557
4558         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4560 }
4561
4562 static int
4563 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4564 {
4565         struct ixgbe_hw *hw;
4566         uint32_t mflcn_reg;
4567         uint32_t fccfg_reg;
4568         int rx_pause;
4569         int tx_pause;
4570
4571         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4572
4573         fc_conf->pause_time = hw->fc.pause_time;
4574         fc_conf->high_water = hw->fc.high_water[0];
4575         fc_conf->low_water = hw->fc.low_water[0];
4576         fc_conf->send_xon = hw->fc.send_xon;
4577         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4578
4579         /*
4580          * Return rx_pause status according to actual setting of
4581          * MFLCN register.
4582          */
4583         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4584         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4585                 rx_pause = 1;
4586         else
4587                 rx_pause = 0;
4588
4589         /*
4590          * Return tx_pause status according to actual setting of
4591          * FCCFG register.
4592          */
4593         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4594         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4595                 tx_pause = 1;
4596         else
4597                 tx_pause = 0;
4598
4599         if (rx_pause && tx_pause)
4600                 fc_conf->mode = RTE_FC_FULL;
4601         else if (rx_pause)
4602                 fc_conf->mode = RTE_FC_RX_PAUSE;
4603         else if (tx_pause)
4604                 fc_conf->mode = RTE_FC_TX_PAUSE;
4605         else
4606                 fc_conf->mode = RTE_FC_NONE;
4607
4608         return 0;
4609 }
4610
4611 static int
4612 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4613 {
4614         struct ixgbe_hw *hw;
4615         int err;
4616         uint32_t rx_buf_size;
4617         uint32_t max_high_water;
4618         uint32_t mflcn;
4619         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4620                 ixgbe_fc_none,
4621                 ixgbe_fc_rx_pause,
4622                 ixgbe_fc_tx_pause,
4623                 ixgbe_fc_full
4624         };
4625
4626         PMD_INIT_FUNC_TRACE();
4627
4628         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4629         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4630         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4631
4632         /*
4633          * At least reserve one Ethernet frame for watermark
4634          * high_water/low_water in kilo bytes for ixgbe
4635          */
4636         max_high_water = (rx_buf_size -
4637                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4638         if ((fc_conf->high_water > max_high_water) ||
4639                 (fc_conf->high_water < fc_conf->low_water)) {
4640                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4641                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4642                 return -EINVAL;
4643         }
4644
4645         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4646         hw->fc.pause_time     = fc_conf->pause_time;
4647         hw->fc.high_water[0]  = fc_conf->high_water;
4648         hw->fc.low_water[0]   = fc_conf->low_water;
4649         hw->fc.send_xon       = fc_conf->send_xon;
4650         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4651
4652         err = ixgbe_fc_enable(hw);
4653
4654         /* Not negotiated is not an error case */
4655         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4656
4657                 /* check if we want to forward MAC frames - driver doesn't have native
4658                  * capability to do that, so we'll write the registers ourselves */
4659
4660                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4661
4662                 /* set or clear MFLCN.PMCF bit depending on configuration */
4663                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4664                         mflcn |= IXGBE_MFLCN_PMCF;
4665                 else
4666                         mflcn &= ~IXGBE_MFLCN_PMCF;
4667
4668                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4669                 IXGBE_WRITE_FLUSH(hw);
4670
4671                 return 0;
4672         }
4673
4674         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4675         return -EIO;
4676 }
4677
4678 /**
4679  *  ixgbe_pfc_enable_generic - Enable flow control
4680  *  @hw: pointer to hardware structure
4681  *  @tc_num: traffic class number
4682  *  Enable flow control according to the current settings.
4683  */
4684 static int
4685 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4686 {
4687         int ret_val = 0;
4688         uint32_t mflcn_reg, fccfg_reg;
4689         uint32_t reg;
4690         uint32_t fcrtl, fcrth;
4691         uint8_t i;
4692         uint8_t nb_rx_en;
4693
4694         /* Validate the water mark configuration */
4695         if (!hw->fc.pause_time) {
4696                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4697                 goto out;
4698         }
4699
4700         /* Low water mark of zero causes XOFF floods */
4701         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4702                  /* High/Low water can not be 0 */
4703                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4704                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4705                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4706                         goto out;
4707                 }
4708
4709                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4710                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4711                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4712                         goto out;
4713                 }
4714         }
4715         /* Negotiate the fc mode to use */
4716         ixgbe_fc_autoneg(hw);
4717
4718         /* Disable any previous flow control settings */
4719         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4720         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4721
4722         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4723         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4724
4725         switch (hw->fc.current_mode) {
4726         case ixgbe_fc_none:
4727                 /*
4728                  * If the count of enabled RX Priority Flow control >1,
4729                  * and the TX pause can not be disabled
4730                  */
4731                 nb_rx_en = 0;
4732                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4733                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4734                         if (reg & IXGBE_FCRTH_FCEN)
4735                                 nb_rx_en++;
4736                 }
4737                 if (nb_rx_en > 1)
4738                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4739                 break;
4740         case ixgbe_fc_rx_pause:
4741                 /*
4742                  * Rx Flow control is enabled and Tx Flow control is
4743                  * disabled by software override. Since there really
4744                  * isn't a way to advertise that we are capable of RX
4745                  * Pause ONLY, we will advertise that we support both
4746                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4747                  * disable the adapter's ability to send PAUSE frames.
4748                  */
4749                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4750                 /*
4751                  * If the count of enabled RX Priority Flow control >1,
4752                  * and the TX pause can not be disabled
4753                  */
4754                 nb_rx_en = 0;
4755                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4756                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4757                         if (reg & IXGBE_FCRTH_FCEN)
4758                                 nb_rx_en++;
4759                 }
4760                 if (nb_rx_en > 1)
4761                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4762                 break;
4763         case ixgbe_fc_tx_pause:
4764                 /*
4765                  * Tx Flow control is enabled, and Rx Flow control is
4766                  * disabled by software override.
4767                  */
4768                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4769                 break;
4770         case ixgbe_fc_full:
4771                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4772                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4773                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4774                 break;
4775         default:
4776                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4777                 ret_val = IXGBE_ERR_CONFIG;
4778                 goto out;
4779         }
4780
4781         /* Set 802.3x based flow control settings. */
4782         mflcn_reg |= IXGBE_MFLCN_DPF;
4783         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4784         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4785
4786         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4787         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4788                 hw->fc.high_water[tc_num]) {
4789                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4790                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4791                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4792         } else {
4793                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4794                 /*
4795                  * In order to prevent Tx hangs when the internal Tx
4796                  * switch is enabled we must set the high water mark
4797                  * to the maximum FCRTH value.  This allows the Tx
4798                  * switch to function even under heavy Rx workloads.
4799                  */
4800                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4801         }
4802         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4803
4804         /* Configure pause time (2 TCs per register) */
4805         reg = hw->fc.pause_time * 0x00010001;
4806         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4807                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4808
4809         /* Configure flow control refresh threshold value */
4810         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4811
4812 out:
4813         return ret_val;
4814 }
4815
4816 static int
4817 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4818 {
4819         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4820         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4821
4822         if (hw->mac.type != ixgbe_mac_82598EB) {
4823                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4824         }
4825         return ret_val;
4826 }
4827
4828 static int
4829 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4830 {
4831         int err;
4832         uint32_t rx_buf_size;
4833         uint32_t max_high_water;
4834         uint8_t tc_num;
4835         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4836         struct ixgbe_hw *hw =
4837                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4838         struct ixgbe_dcb_config *dcb_config =
4839                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4840
4841         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4842                 ixgbe_fc_none,
4843                 ixgbe_fc_rx_pause,
4844                 ixgbe_fc_tx_pause,
4845                 ixgbe_fc_full
4846         };
4847
4848         PMD_INIT_FUNC_TRACE();
4849
4850         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4851         tc_num = map[pfc_conf->priority];
4852         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4853         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4854         /*
4855          * At least reserve one Ethernet frame for watermark
4856          * high_water/low_water in kilo bytes for ixgbe
4857          */
4858         max_high_water = (rx_buf_size -
4859                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4860         if ((pfc_conf->fc.high_water > max_high_water) ||
4861             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4862                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4863                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4864                 return -EINVAL;
4865         }
4866
4867         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4868         hw->fc.pause_time = pfc_conf->fc.pause_time;
4869         hw->fc.send_xon = pfc_conf->fc.send_xon;
4870         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4871         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4872
4873         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4874
4875         /* Not negotiated is not an error case */
4876         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4877                 return 0;
4878
4879         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4880         return -EIO;
4881 }
4882
4883 static int
4884 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4885                           struct rte_eth_rss_reta_entry64 *reta_conf,
4886                           uint16_t reta_size)
4887 {
4888         uint16_t i, sp_reta_size;
4889         uint8_t j, mask;
4890         uint32_t reta, r;
4891         uint16_t idx, shift;
4892         struct ixgbe_adapter *adapter = dev->data->dev_private;
4893         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4894         uint32_t reta_reg;
4895
4896         PMD_INIT_FUNC_TRACE();
4897
4898         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4899                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4900                         "NIC.");
4901                 return -ENOTSUP;
4902         }
4903
4904         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4905         if (reta_size != sp_reta_size) {
4906                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4907                         "(%d) doesn't match the number hardware can supported "
4908                         "(%d)", reta_size, sp_reta_size);
4909                 return -EINVAL;
4910         }
4911
4912         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4913                 idx = i / RTE_RETA_GROUP_SIZE;
4914                 shift = i % RTE_RETA_GROUP_SIZE;
4915                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4916                                                 IXGBE_4_BIT_MASK);
4917                 if (!mask)
4918                         continue;
4919                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4920                 if (mask == IXGBE_4_BIT_MASK)
4921                         r = 0;
4922                 else
4923                         r = IXGBE_READ_REG(hw, reta_reg);
4924                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4925                         if (mask & (0x1 << j))
4926                                 reta |= reta_conf[idx].reta[shift + j] <<
4927                                                         (CHAR_BIT * j);
4928                         else
4929                                 reta |= r & (IXGBE_8_BIT_MASK <<
4930                                                 (CHAR_BIT * j));
4931                 }
4932                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4933         }
4934         adapter->rss_reta_updated = 1;
4935
4936         return 0;
4937 }
4938
4939 static int
4940 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4941                          struct rte_eth_rss_reta_entry64 *reta_conf,
4942                          uint16_t reta_size)
4943 {
4944         uint16_t i, sp_reta_size;
4945         uint8_t j, mask;
4946         uint32_t reta;
4947         uint16_t idx, shift;
4948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949         uint32_t reta_reg;
4950
4951         PMD_INIT_FUNC_TRACE();
4952         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4953         if (reta_size != sp_reta_size) {
4954                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4955                         "(%d) doesn't match the number hardware can supported "
4956                         "(%d)", reta_size, sp_reta_size);
4957                 return -EINVAL;
4958         }
4959
4960         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4961                 idx = i / RTE_RETA_GROUP_SIZE;
4962                 shift = i % RTE_RETA_GROUP_SIZE;
4963                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4964                                                 IXGBE_4_BIT_MASK);
4965                 if (!mask)
4966                         continue;
4967
4968                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4969                 reta = IXGBE_READ_REG(hw, reta_reg);
4970                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4971                         if (mask & (0x1 << j))
4972                                 reta_conf[idx].reta[shift + j] =
4973                                         ((reta >> (CHAR_BIT * j)) &
4974                                                 IXGBE_8_BIT_MASK);
4975                 }
4976         }
4977
4978         return 0;
4979 }
4980
4981 static int
4982 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
4983                                 uint32_t index, uint32_t pool)
4984 {
4985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986         uint32_t enable_addr = 1;
4987
4988         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4989                              pool, enable_addr);
4990 }
4991
4992 static void
4993 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4994 {
4995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996
4997         ixgbe_clear_rar(hw, index);
4998 }
4999
5000 static int
5001 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5002 {
5003         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5004
5005         ixgbe_remove_rar(dev, 0);
5006         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5007
5008         return 0;
5009 }
5010
5011 static bool
5012 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5013 {
5014         if (strcmp(dev->device->driver->name, drv->driver.name))
5015                 return false;
5016
5017         return true;
5018 }
5019
5020 bool
5021 is_ixgbe_supported(struct rte_eth_dev *dev)
5022 {
5023         return is_device_supported(dev, &rte_ixgbe_pmd);
5024 }
5025
5026 static int
5027 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5028 {
5029         uint32_t hlreg0;
5030         uint32_t maxfrs;
5031         struct ixgbe_hw *hw;
5032         struct rte_eth_dev_info dev_info;
5033         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5034         struct rte_eth_dev_data *dev_data = dev->data;
5035         int ret;
5036
5037         ret = ixgbe_dev_info_get(dev, &dev_info);
5038         if (ret != 0)
5039                 return ret;
5040
5041         /* check that mtu is within the allowed range */
5042         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5043                 return -EINVAL;
5044
5045         /* If device is started, refuse mtu that requires the support of
5046          * scattered packets when this feature has not been enabled before.
5047          */
5048         if (dev_data->dev_started && !dev_data->scattered_rx &&
5049             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5050              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5051                 PMD_INIT_LOG(ERR, "Stop port first.");
5052                 return -EINVAL;
5053         }
5054
5055         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5056         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5057
5058         /* switch to jumbo mode if needed */
5059         if (frame_size > RTE_ETHER_MAX_LEN) {
5060                 dev->data->dev_conf.rxmode.offloads |=
5061                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5062                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5063         } else {
5064                 dev->data->dev_conf.rxmode.offloads &=
5065                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5066                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5067         }
5068         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5069
5070         /* update max frame size */
5071         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5072
5073         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5074         maxfrs &= 0x0000FFFF;
5075         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5076         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5077
5078         return 0;
5079 }
5080
5081 /*
5082  * Virtual Function operations
5083  */
5084 static void
5085 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5086 {
5087         struct ixgbe_interrupt *intr =
5088                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5089         struct ixgbe_hw *hw =
5090                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5091
5092         PMD_INIT_FUNC_TRACE();
5093
5094         /* Clear interrupt mask to stop from interrupts being generated */
5095         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5096
5097         IXGBE_WRITE_FLUSH(hw);
5098
5099         /* Clear mask value. */
5100         intr->mask = 0;
5101 }
5102
5103 static void
5104 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5105 {
5106         struct ixgbe_interrupt *intr =
5107                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5108         struct ixgbe_hw *hw =
5109                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5110
5111         PMD_INIT_FUNC_TRACE();
5112
5113         /* VF enable interrupt autoclean */
5114         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5115         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5116         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5117
5118         IXGBE_WRITE_FLUSH(hw);
5119
5120         /* Save IXGBE_VTEIMS value to mask. */
5121         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5122 }
5123
5124 static int
5125 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5126 {
5127         struct rte_eth_conf *conf = &dev->data->dev_conf;
5128         struct ixgbe_adapter *adapter = dev->data->dev_private;
5129
5130         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5131                      dev->data->port_id);
5132
5133         /*
5134          * VF has no ability to enable/disable HW CRC
5135          * Keep the persistent behavior the same as Host PF
5136          */
5137 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5138         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5139                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5140                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5141         }
5142 #else
5143         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5144                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5145                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5146         }
5147 #endif
5148
5149         /*
5150          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5151          * allocation or vector Rx preconditions we will reset it.
5152          */
5153         adapter->rx_bulk_alloc_allowed = true;
5154         adapter->rx_vec_allowed = true;
5155
5156         return 0;
5157 }
5158
5159 static int
5160 ixgbevf_dev_start(struct rte_eth_dev *dev)
5161 {
5162         struct ixgbe_hw *hw =
5163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5164         uint32_t intr_vector = 0;
5165         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5166         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5167
5168         int err, mask = 0;
5169
5170         PMD_INIT_FUNC_TRACE();
5171
5172         /* Stop the link setup handler before resetting the HW. */
5173         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5174
5175         err = hw->mac.ops.reset_hw(hw);
5176         if (err) {
5177                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5178                 return err;
5179         }
5180         hw->mac.get_link_status = true;
5181
5182         /* negotiate mailbox API version to use with the PF. */
5183         ixgbevf_negotiate_api(hw);
5184
5185         ixgbevf_dev_tx_init(dev);
5186
5187         /* This can fail when allocating mbufs for descriptor rings */
5188         err = ixgbevf_dev_rx_init(dev);
5189         if (err) {
5190                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5191                 ixgbe_dev_clear_queues(dev);
5192                 return err;
5193         }
5194
5195         /* Set vfta */
5196         ixgbevf_set_vfta_all(dev, 1);
5197
5198         /* Set HW strip */
5199         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5200                 ETH_VLAN_EXTEND_MASK;
5201         err = ixgbevf_vlan_offload_config(dev, mask);
5202         if (err) {
5203                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5204                 ixgbe_dev_clear_queues(dev);
5205                 return err;
5206         }
5207
5208         ixgbevf_dev_rxtx_start(dev);
5209
5210         /* check and configure queue intr-vector mapping */
5211         if (rte_intr_cap_multiple(intr_handle) &&
5212             dev->data->dev_conf.intr_conf.rxq) {
5213                 /* According to datasheet, only vector 0/1/2 can be used,
5214                  * now only one vector is used for Rx queue
5215                  */
5216                 intr_vector = 1;
5217                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5218                         return -1;
5219         }
5220
5221         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5222                 intr_handle->intr_vec =
5223                         rte_zmalloc("intr_vec",
5224                                     dev->data->nb_rx_queues * sizeof(int), 0);
5225                 if (intr_handle->intr_vec == NULL) {
5226                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5227                                      " intr_vec", dev->data->nb_rx_queues);
5228                         return -ENOMEM;
5229                 }
5230         }
5231         ixgbevf_configure_msix(dev);
5232
5233         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5234          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5235          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5236          * is not cleared, it will fail when following rte_intr_enable( ) tries
5237          * to map Rx queue interrupt to other VFIO vectors.
5238          * So clear uio/vfio intr/evevnfd first to avoid failure.
5239          */
5240         rte_intr_disable(intr_handle);
5241
5242         rte_intr_enable(intr_handle);
5243
5244         /* Re-enable interrupt for VF */
5245         ixgbevf_intr_enable(dev);
5246
5247         /*
5248          * Update link status right before return, because it may
5249          * start link configuration process in a separate thread.
5250          */
5251         ixgbevf_dev_link_update(dev, 0);
5252
5253         return 0;
5254 }
5255
5256 static void
5257 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5258 {
5259         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5260         struct ixgbe_adapter *adapter = dev->data->dev_private;
5261         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5262         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5263
5264         PMD_INIT_FUNC_TRACE();
5265
5266         rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5267
5268         ixgbevf_intr_disable(dev);
5269
5270         hw->adapter_stopped = 1;
5271         ixgbe_stop_adapter(hw);
5272
5273         /*
5274           * Clear what we set, but we still keep shadow_vfta to
5275           * restore after device starts
5276           */
5277         ixgbevf_set_vfta_all(dev, 0);
5278
5279         /* Clear stored conf */
5280         dev->data->scattered_rx = 0;
5281
5282         ixgbe_dev_clear_queues(dev);
5283
5284         /* Clean datapath event and queue/vec mapping */
5285         rte_intr_efd_disable(intr_handle);
5286         if (intr_handle->intr_vec != NULL) {
5287                 rte_free(intr_handle->intr_vec);
5288                 intr_handle->intr_vec = NULL;
5289         }
5290
5291         adapter->rss_reta_updated = 0;
5292 }
5293
5294 static void
5295 ixgbevf_dev_close(struct rte_eth_dev *dev)
5296 {
5297         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5298
5299         PMD_INIT_FUNC_TRACE();
5300
5301         ixgbe_reset_hw(hw);
5302
5303         ixgbevf_dev_stop(dev);
5304
5305         ixgbe_dev_free_queues(dev);
5306
5307         /**
5308          * Remove the VF MAC address ro ensure
5309          * that the VF traffic goes to the PF
5310          * after stop, close and detach of the VF
5311          **/
5312         ixgbevf_remove_mac_addr(dev, 0);
5313 }
5314
5315 /*
5316  * Reset VF device
5317  */
5318 static int
5319 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5320 {
5321         int ret;
5322
5323         ret = eth_ixgbevf_dev_uninit(dev);
5324         if (ret)
5325                 return ret;
5326
5327         ret = eth_ixgbevf_dev_init(dev);
5328
5329         return ret;
5330 }
5331
5332 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5333 {
5334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335         struct ixgbe_vfta *shadow_vfta =
5336                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5337         int i = 0, j = 0, vfta = 0, mask = 1;
5338
5339         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5340                 vfta = shadow_vfta->vfta[i];
5341                 if (vfta) {
5342                         mask = 1;
5343                         for (j = 0; j < 32; j++) {
5344                                 if (vfta & mask)
5345                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5346                                                        on, false);
5347                                 mask <<= 1;
5348                         }
5349                 }
5350         }
5351
5352 }
5353
5354 static int
5355 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5356 {
5357         struct ixgbe_hw *hw =
5358                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5359         struct ixgbe_vfta *shadow_vfta =
5360                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5361         uint32_t vid_idx = 0;
5362         uint32_t vid_bit = 0;
5363         int ret = 0;
5364
5365         PMD_INIT_FUNC_TRACE();
5366
5367         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5368         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5369         if (ret) {
5370                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5371                 return ret;
5372         }
5373         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5374         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5375
5376         /* Save what we set and retore it after device reset */
5377         if (on)
5378                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5379         else
5380                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5381
5382         return 0;
5383 }
5384
5385 static void
5386 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5387 {
5388         struct ixgbe_hw *hw =
5389                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5390         uint32_t ctrl;
5391
5392         PMD_INIT_FUNC_TRACE();
5393
5394         if (queue >= hw->mac.max_rx_queues)
5395                 return;
5396
5397         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5398         if (on)
5399                 ctrl |= IXGBE_RXDCTL_VME;
5400         else
5401                 ctrl &= ~IXGBE_RXDCTL_VME;
5402         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5403
5404         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5405 }
5406
5407 static int
5408 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5409 {
5410         struct ixgbe_rx_queue *rxq;
5411         uint16_t i;
5412         int on = 0;
5413
5414         /* VF function only support hw strip feature, others are not support */
5415         if (mask & ETH_VLAN_STRIP_MASK) {
5416                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5417                         rxq = dev->data->rx_queues[i];
5418                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5419                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5420                 }
5421         }
5422
5423         return 0;
5424 }
5425
5426 static int
5427 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5428 {
5429         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5430
5431         ixgbevf_vlan_offload_config(dev, mask);
5432
5433         return 0;
5434 }
5435
5436 int
5437 ixgbe_vt_check(struct ixgbe_hw *hw)
5438 {
5439         uint32_t reg_val;
5440
5441         /* if Virtualization Technology is enabled */
5442         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5443         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5444                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5445                 return -1;
5446         }
5447
5448         return 0;
5449 }
5450
5451 static uint32_t
5452 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5453 {
5454         uint32_t vector = 0;
5455
5456         switch (hw->mac.mc_filter_type) {
5457         case 0:   /* use bits [47:36] of the address */
5458                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5459                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5460                 break;
5461         case 1:   /* use bits [46:35] of the address */
5462                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5463                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5464                 break;
5465         case 2:   /* use bits [45:34] of the address */
5466                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5467                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5468                 break;
5469         case 3:   /* use bits [43:32] of the address */
5470                 vector = ((uc_addr->addr_bytes[4]) |
5471                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5472                 break;
5473         default:  /* Invalid mc_filter_type */
5474                 break;
5475         }
5476
5477         /* vector can only be 12-bits or boundary will be exceeded */
5478         vector &= 0xFFF;
5479         return vector;
5480 }
5481
5482 static int
5483 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5484                         struct rte_ether_addr *mac_addr, uint8_t on)
5485 {
5486         uint32_t vector;
5487         uint32_t uta_idx;
5488         uint32_t reg_val;
5489         uint32_t uta_shift;
5490         uint32_t rc;
5491         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5492         const uint32_t ixgbe_uta_bit_shift = 5;
5493         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5494         const uint32_t bit1 = 0x1;
5495
5496         struct ixgbe_hw *hw =
5497                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5498         struct ixgbe_uta_info *uta_info =
5499                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5500
5501         /* The UTA table only exists on 82599 hardware and newer */
5502         if (hw->mac.type < ixgbe_mac_82599EB)
5503                 return -ENOTSUP;
5504
5505         vector = ixgbe_uta_vector(hw, mac_addr);
5506         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5507         uta_shift = vector & ixgbe_uta_bit_mask;
5508
5509         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5510         if (rc == on)
5511                 return 0;
5512
5513         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5514         if (on) {
5515                 uta_info->uta_in_use++;
5516                 reg_val |= (bit1 << uta_shift);
5517                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5518         } else {
5519                 uta_info->uta_in_use--;
5520                 reg_val &= ~(bit1 << uta_shift);
5521                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5522         }
5523
5524         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5525
5526         if (uta_info->uta_in_use > 0)
5527                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5528                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5529         else
5530                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5531
5532         return 0;
5533 }
5534
5535 static int
5536 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5537 {
5538         int i;
5539         struct ixgbe_hw *hw =
5540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5541         struct ixgbe_uta_info *uta_info =
5542                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5543
5544         /* The UTA table only exists on 82599 hardware and newer */
5545         if (hw->mac.type < ixgbe_mac_82599EB)
5546                 return -ENOTSUP;
5547
5548         if (on) {
5549                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5550                         uta_info->uta_shadow[i] = ~0;
5551                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5552                 }
5553         } else {
5554                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5555                         uta_info->uta_shadow[i] = 0;
5556                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5557                 }
5558         }
5559         return 0;
5560
5561 }
5562
5563 uint32_t
5564 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5565 {
5566         uint32_t new_val = orig_val;
5567
5568         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5569                 new_val |= IXGBE_VMOLR_AUPE;
5570         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5571                 new_val |= IXGBE_VMOLR_ROMPE;
5572         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5573                 new_val |= IXGBE_VMOLR_ROPE;
5574         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5575                 new_val |= IXGBE_VMOLR_BAM;
5576         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5577                 new_val |= IXGBE_VMOLR_MPE;
5578
5579         return new_val;
5580 }
5581
5582 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5583 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5584 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5585 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5586 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5587         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5588         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5589
5590 static int
5591 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5592                       struct rte_eth_mirror_conf *mirror_conf,
5593                       uint8_t rule_id, uint8_t on)
5594 {
5595         uint32_t mr_ctl, vlvf;
5596         uint32_t mp_lsb = 0;
5597         uint32_t mv_msb = 0;
5598         uint32_t mv_lsb = 0;
5599         uint32_t mp_msb = 0;
5600         uint8_t i = 0;
5601         int reg_index = 0;
5602         uint64_t vlan_mask = 0;
5603
5604         const uint8_t pool_mask_offset = 32;
5605         const uint8_t vlan_mask_offset = 32;
5606         const uint8_t dst_pool_offset = 8;
5607         const uint8_t rule_mr_offset  = 4;
5608         const uint8_t mirror_rule_mask = 0x0F;
5609
5610         struct ixgbe_mirror_info *mr_info =
5611                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5612         struct ixgbe_hw *hw =
5613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5614         uint8_t mirror_type = 0;
5615
5616         if (ixgbe_vt_check(hw) < 0)
5617                 return -ENOTSUP;
5618
5619         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5620                 return -EINVAL;
5621
5622         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5623                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5624                             mirror_conf->rule_type);
5625                 return -EINVAL;
5626         }
5627
5628         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5629                 mirror_type |= IXGBE_MRCTL_VLME;
5630                 /* Check if vlan id is valid and find conresponding VLAN ID
5631                  * index in VLVF
5632                  */
5633                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5634                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5635                                 /* search vlan id related pool vlan filter
5636                                  * index
5637                                  */
5638                                 reg_index = ixgbe_find_vlvf_slot(
5639                                                 hw,
5640                                                 mirror_conf->vlan.vlan_id[i],
5641                                                 false);
5642                                 if (reg_index < 0)
5643                                         return -EINVAL;
5644                                 vlvf = IXGBE_READ_REG(hw,
5645                                                       IXGBE_VLVF(reg_index));
5646                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5647                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5648                                       mirror_conf->vlan.vlan_id[i]))
5649                                         vlan_mask |= (1ULL << reg_index);
5650                                 else
5651                                         return -EINVAL;
5652                         }
5653                 }
5654
5655                 if (on) {
5656                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5657                         mv_msb = vlan_mask >> vlan_mask_offset;
5658
5659                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5660                                                 mirror_conf->vlan.vlan_mask;
5661                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5662                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5663                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5664                                                 mirror_conf->vlan.vlan_id[i];
5665                         }
5666                 } else {
5667                         mv_lsb = 0;
5668                         mv_msb = 0;
5669                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5670                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5671                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5672                 }
5673         }
5674
5675         /**
5676          * if enable pool mirror, write related pool mask register,if disable
5677          * pool mirror, clear PFMRVM register
5678          */
5679         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5680                 mirror_type |= IXGBE_MRCTL_VPME;
5681                 if (on) {
5682                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5683                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5684                         mr_info->mr_conf[rule_id].pool_mask =
5685                                         mirror_conf->pool_mask;
5686
5687                 } else {
5688                         mp_lsb = 0;
5689                         mp_msb = 0;
5690                         mr_info->mr_conf[rule_id].pool_mask = 0;
5691                 }
5692         }
5693         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5694                 mirror_type |= IXGBE_MRCTL_UPME;
5695         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5696                 mirror_type |= IXGBE_MRCTL_DPME;
5697
5698         /* read  mirror control register and recalculate it */
5699         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5700
5701         if (on) {
5702                 mr_ctl |= mirror_type;
5703                 mr_ctl &= mirror_rule_mask;
5704                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5705         } else {
5706                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5707         }
5708
5709         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5710         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5711
5712         /* write mirrror control  register */
5713         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5714
5715         /* write pool mirrror control  register */
5716         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5717                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5718                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5719                                 mp_msb);
5720         }
5721         /* write VLAN mirrror control  register */
5722         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5723                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5724                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5725                                 mv_msb);
5726         }
5727
5728         return 0;
5729 }
5730
5731 static int
5732 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5733 {
5734         int mr_ctl = 0;
5735         uint32_t lsb_val = 0;
5736         uint32_t msb_val = 0;
5737         const uint8_t rule_mr_offset = 4;
5738
5739         struct ixgbe_hw *hw =
5740                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5741         struct ixgbe_mirror_info *mr_info =
5742                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5743
5744         if (ixgbe_vt_check(hw) < 0)
5745                 return -ENOTSUP;
5746
5747         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5748                 return -EINVAL;
5749
5750         memset(&mr_info->mr_conf[rule_id], 0,
5751                sizeof(struct rte_eth_mirror_conf));
5752
5753         /* clear PFVMCTL register */
5754         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5755
5756         /* clear pool mask register */
5757         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5758         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5759
5760         /* clear vlan mask register */
5761         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5762         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5763
5764         return 0;
5765 }
5766
5767 static int
5768 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5769 {
5770         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5771         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5772         struct ixgbe_interrupt *intr =
5773                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5774         struct ixgbe_hw *hw =
5775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5776         uint32_t vec = IXGBE_MISC_VEC_ID;
5777
5778         if (rte_intr_allow_others(intr_handle))
5779                 vec = IXGBE_RX_VEC_START;
5780         intr->mask |= (1 << vec);
5781         RTE_SET_USED(queue_id);
5782         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5783
5784         rte_intr_ack(intr_handle);
5785
5786         return 0;
5787 }
5788
5789 static int
5790 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5791 {
5792         struct ixgbe_interrupt *intr =
5793                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5794         struct ixgbe_hw *hw =
5795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5796         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5797         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5798         uint32_t vec = IXGBE_MISC_VEC_ID;
5799
5800         if (rte_intr_allow_others(intr_handle))
5801                 vec = IXGBE_RX_VEC_START;
5802         intr->mask &= ~(1 << vec);
5803         RTE_SET_USED(queue_id);
5804         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5805
5806         return 0;
5807 }
5808
5809 static int
5810 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5811 {
5812         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5813         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5814         uint32_t mask;
5815         struct ixgbe_hw *hw =
5816                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817         struct ixgbe_interrupt *intr =
5818                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5819
5820         if (queue_id < 16) {
5821                 ixgbe_disable_intr(hw);
5822                 intr->mask |= (1 << queue_id);
5823                 ixgbe_enable_intr(dev);
5824         } else if (queue_id < 32) {
5825                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5826                 mask &= (1 << queue_id);
5827                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5828         } else if (queue_id < 64) {
5829                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5830                 mask &= (1 << (queue_id - 32));
5831                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5832         }
5833         rte_intr_ack(intr_handle);
5834
5835         return 0;
5836 }
5837
5838 static int
5839 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5840 {
5841         uint32_t mask;
5842         struct ixgbe_hw *hw =
5843                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5844         struct ixgbe_interrupt *intr =
5845                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5846
5847         if (queue_id < 16) {
5848                 ixgbe_disable_intr(hw);
5849                 intr->mask &= ~(1 << queue_id);
5850                 ixgbe_enable_intr(dev);
5851         } else if (queue_id < 32) {
5852                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5853                 mask &= ~(1 << queue_id);
5854                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5855         } else if (queue_id < 64) {
5856                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5857                 mask &= ~(1 << (queue_id - 32));
5858                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5859         }
5860
5861         return 0;
5862 }
5863
5864 static void
5865 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5866                      uint8_t queue, uint8_t msix_vector)
5867 {
5868         uint32_t tmp, idx;
5869
5870         if (direction == -1) {
5871                 /* other causes */
5872                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5873                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5874                 tmp &= ~0xFF;
5875                 tmp |= msix_vector;
5876                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5877         } else {
5878                 /* rx or tx cause */
5879                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5880                 idx = ((16 * (queue & 1)) + (8 * direction));
5881                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5882                 tmp &= ~(0xFF << idx);
5883                 tmp |= (msix_vector << idx);
5884                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5885         }
5886 }
5887
5888 /**
5889  * set the IVAR registers, mapping interrupt causes to vectors
5890  * @param hw
5891  *  pointer to ixgbe_hw struct
5892  * @direction
5893  *  0 for Rx, 1 for Tx, -1 for other causes
5894  * @queue
5895  *  queue to map the corresponding interrupt to
5896  * @msix_vector
5897  *  the vector to map to the corresponding queue
5898  */
5899 static void
5900 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5901                    uint8_t queue, uint8_t msix_vector)
5902 {
5903         uint32_t tmp, idx;
5904
5905         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5906         if (hw->mac.type == ixgbe_mac_82598EB) {
5907                 if (direction == -1)
5908                         direction = 0;
5909                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5910                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5911                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5912                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5913                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5914         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5915                         (hw->mac.type == ixgbe_mac_X540) ||
5916                         (hw->mac.type == ixgbe_mac_X550) ||
5917                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
5918                 if (direction == -1) {
5919                         /* other causes */
5920                         idx = ((queue & 1) * 8);
5921                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5922                         tmp &= ~(0xFF << idx);
5923                         tmp |= (msix_vector << idx);
5924                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5925                 } else {
5926                         /* rx or tx causes */
5927                         idx = ((16 * (queue & 1)) + (8 * direction));
5928                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5929                         tmp &= ~(0xFF << idx);
5930                         tmp |= (msix_vector << idx);
5931                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5932                 }
5933         }
5934 }
5935
5936 static void
5937 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5938 {
5939         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5940         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5941         struct ixgbe_hw *hw =
5942                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943         uint32_t q_idx;
5944         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5945         uint32_t base = IXGBE_MISC_VEC_ID;
5946
5947         /* Configure VF other cause ivar */
5948         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5949
5950         /* won't configure msix register if no mapping is done
5951          * between intr vector and event fd.
5952          */
5953         if (!rte_intr_dp_is_en(intr_handle))
5954                 return;
5955
5956         if (rte_intr_allow_others(intr_handle)) {
5957                 base = IXGBE_RX_VEC_START;
5958                 vector_idx = IXGBE_RX_VEC_START;
5959         }
5960
5961         /* Configure all RX queues of VF */
5962         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5963                 /* Force all queue use vector 0,
5964                  * as IXGBE_VF_MAXMSIVECOTR = 1
5965                  */
5966                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5967                 intr_handle->intr_vec[q_idx] = vector_idx;
5968                 if (vector_idx < base + intr_handle->nb_efd - 1)
5969                         vector_idx++;
5970         }
5971
5972         /* As RX queue setting above show, all queues use the vector 0.
5973          * Set only the ITR value of IXGBE_MISC_VEC_ID.
5974          */
5975         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5976                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5977                         | IXGBE_EITR_CNT_WDIS);
5978 }
5979
5980 /**
5981  * Sets up the hardware to properly generate MSI-X interrupts
5982  * @hw
5983  *  board private structure
5984  */
5985 static void
5986 ixgbe_configure_msix(struct rte_eth_dev *dev)
5987 {
5988         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5989         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5990         struct ixgbe_hw *hw =
5991                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5992         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5993         uint32_t vec = IXGBE_MISC_VEC_ID;
5994         uint32_t mask;
5995         uint32_t gpie;
5996
5997         /* won't configure msix register if no mapping is done
5998          * between intr vector and event fd
5999          * but if misx has been enabled already, need to configure
6000          * auto clean, auto mask and throttling.
6001          */
6002         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6003         if (!rte_intr_dp_is_en(intr_handle) &&
6004             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6005                 return;
6006
6007         if (rte_intr_allow_others(intr_handle))
6008                 vec = base = IXGBE_RX_VEC_START;
6009
6010         /* setup GPIE for MSI-x mode */
6011         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6012         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6013                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6014         /* auto clearing and auto setting corresponding bits in EIMS
6015          * when MSI-X interrupt is triggered
6016          */
6017         if (hw->mac.type == ixgbe_mac_82598EB) {
6018                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6019         } else {
6020                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6021                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6022         }
6023         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6024
6025         /* Populate the IVAR table and set the ITR values to the
6026          * corresponding register.
6027          */
6028         if (rte_intr_dp_is_en(intr_handle)) {
6029                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6030                         queue_id++) {
6031                         /* by default, 1:1 mapping */
6032                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6033                         intr_handle->intr_vec[queue_id] = vec;
6034                         if (vec < base + intr_handle->nb_efd - 1)
6035                                 vec++;
6036                 }
6037
6038                 switch (hw->mac.type) {
6039                 case ixgbe_mac_82598EB:
6040                         ixgbe_set_ivar_map(hw, -1,
6041                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6042                                            IXGBE_MISC_VEC_ID);
6043                         break;
6044                 case ixgbe_mac_82599EB:
6045                 case ixgbe_mac_X540:
6046                 case ixgbe_mac_X550:
6047                 case ixgbe_mac_X550EM_x:
6048                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6049                         break;
6050                 default:
6051                         break;
6052                 }
6053         }
6054         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6055                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6056                         | IXGBE_EITR_CNT_WDIS);
6057
6058         /* set up to autoclear timer, and the vectors */
6059         mask = IXGBE_EIMS_ENABLE_MASK;
6060         mask &= ~(IXGBE_EIMS_OTHER |
6061                   IXGBE_EIMS_MAILBOX |
6062                   IXGBE_EIMS_LSC);
6063
6064         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6065 }
6066
6067 int
6068 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6069                            uint16_t queue_idx, uint16_t tx_rate)
6070 {
6071         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6072         struct rte_eth_rxmode *rxmode;
6073         uint32_t rf_dec, rf_int;
6074         uint32_t bcnrc_val;
6075         uint16_t link_speed = dev->data->dev_link.link_speed;
6076
6077         if (queue_idx >= hw->mac.max_tx_queues)
6078                 return -EINVAL;
6079
6080         if (tx_rate != 0) {
6081                 /* Calculate the rate factor values to set */
6082                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6083                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6084                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6085
6086                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6087                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6088                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6089                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6090         } else {
6091                 bcnrc_val = 0;
6092         }
6093
6094         rxmode = &dev->data->dev_conf.rxmode;
6095         /*
6096          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6097          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6098          * set as 0x4.
6099          */
6100         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6101             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6102                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6103                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6104         else
6105                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6106                         IXGBE_MMW_SIZE_DEFAULT);
6107
6108         /* Set RTTBCNRC of queue X */
6109         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6110         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6111         IXGBE_WRITE_FLUSH(hw);
6112
6113         return 0;
6114 }
6115
6116 static int
6117 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6118                      __attribute__((unused)) uint32_t index,
6119                      __attribute__((unused)) uint32_t pool)
6120 {
6121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6122         int diag;
6123
6124         /*
6125          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6126          * operation. Trap this case to avoid exhausting the [very limited]
6127          * set of PF resources used to store VF MAC addresses.
6128          */
6129         if (memcmp(hw->mac.perm_addr, mac_addr,
6130                         sizeof(struct rte_ether_addr)) == 0)
6131                 return -1;
6132         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6133         if (diag != 0)
6134                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6135                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6136                             mac_addr->addr_bytes[0],
6137                             mac_addr->addr_bytes[1],
6138                             mac_addr->addr_bytes[2],
6139                             mac_addr->addr_bytes[3],
6140                             mac_addr->addr_bytes[4],
6141                             mac_addr->addr_bytes[5],
6142                             diag);
6143         return diag;
6144 }
6145
6146 static void
6147 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6148 {
6149         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6150         struct rte_ether_addr *perm_addr =
6151                 (struct rte_ether_addr *)hw->mac.perm_addr;
6152         struct rte_ether_addr *mac_addr;
6153         uint32_t i;
6154         int diag;
6155
6156         /*
6157          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6158          * not support the deletion of a given MAC address.
6159          * Instead, it imposes to delete all MAC addresses, then to add again
6160          * all MAC addresses with the exception of the one to be deleted.
6161          */
6162         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6163
6164         /*
6165          * Add again all MAC addresses, with the exception of the deleted one
6166          * and of the permanent MAC address.
6167          */
6168         for (i = 0, mac_addr = dev->data->mac_addrs;
6169              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6170                 /* Skip the deleted MAC address */
6171                 if (i == index)
6172                         continue;
6173                 /* Skip NULL MAC addresses */
6174                 if (rte_is_zero_ether_addr(mac_addr))
6175                         continue;
6176                 /* Skip the permanent MAC address */
6177                 if (memcmp(perm_addr, mac_addr,
6178                                 sizeof(struct rte_ether_addr)) == 0)
6179                         continue;
6180                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6181                 if (diag != 0)
6182                         PMD_DRV_LOG(ERR,
6183                                     "Adding again MAC address "
6184                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6185                                     "diag=%d",
6186                                     mac_addr->addr_bytes[0],
6187                                     mac_addr->addr_bytes[1],
6188                                     mac_addr->addr_bytes[2],
6189                                     mac_addr->addr_bytes[3],
6190                                     mac_addr->addr_bytes[4],
6191                                     mac_addr->addr_bytes[5],
6192                                     diag);
6193         }
6194 }
6195
6196 static int
6197 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6198                         struct rte_ether_addr *addr)
6199 {
6200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6201
6202         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6203
6204         return 0;
6205 }
6206
6207 int
6208 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6209                         struct rte_eth_syn_filter *filter,
6210                         bool add)
6211 {
6212         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6213         struct ixgbe_filter_info *filter_info =
6214                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6215         uint32_t syn_info;
6216         uint32_t synqf;
6217
6218         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6219                 return -EINVAL;
6220
6221         syn_info = filter_info->syn_info;
6222
6223         if (add) {
6224                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6225                         return -EINVAL;
6226                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6227                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6228
6229                 if (filter->hig_pri)
6230                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6231                 else
6232                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6233         } else {
6234                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6235                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6236                         return -ENOENT;
6237                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6238         }
6239
6240         filter_info->syn_info = synqf;
6241         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6242         IXGBE_WRITE_FLUSH(hw);
6243         return 0;
6244 }
6245
6246 static int
6247 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6248                         struct rte_eth_syn_filter *filter)
6249 {
6250         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6251         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6252
6253         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6254                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6255                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6256                 return 0;
6257         }
6258         return -ENOENT;
6259 }
6260
6261 static int
6262 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6263                         enum rte_filter_op filter_op,
6264                         void *arg)
6265 {
6266         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6267         int ret;
6268
6269         MAC_TYPE_FILTER_SUP(hw->mac.type);
6270
6271         if (filter_op == RTE_ETH_FILTER_NOP)
6272                 return 0;
6273
6274         if (arg == NULL) {
6275                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6276                             filter_op);
6277                 return -EINVAL;
6278         }
6279
6280         switch (filter_op) {
6281         case RTE_ETH_FILTER_ADD:
6282                 ret = ixgbe_syn_filter_set(dev,
6283                                 (struct rte_eth_syn_filter *)arg,
6284                                 TRUE);
6285                 break;
6286         case RTE_ETH_FILTER_DELETE:
6287                 ret = ixgbe_syn_filter_set(dev,
6288                                 (struct rte_eth_syn_filter *)arg,
6289                                 FALSE);
6290                 break;
6291         case RTE_ETH_FILTER_GET:
6292                 ret = ixgbe_syn_filter_get(dev,
6293                                 (struct rte_eth_syn_filter *)arg);
6294                 break;
6295         default:
6296                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6297                 ret = -EINVAL;
6298                 break;
6299         }
6300
6301         return ret;
6302 }
6303
6304
6305 static inline enum ixgbe_5tuple_protocol
6306 convert_protocol_type(uint8_t protocol_value)
6307 {
6308         if (protocol_value == IPPROTO_TCP)
6309                 return IXGBE_FILTER_PROTOCOL_TCP;
6310         else if (protocol_value == IPPROTO_UDP)
6311                 return IXGBE_FILTER_PROTOCOL_UDP;
6312         else if (protocol_value == IPPROTO_SCTP)
6313                 return IXGBE_FILTER_PROTOCOL_SCTP;
6314         else
6315                 return IXGBE_FILTER_PROTOCOL_NONE;
6316 }
6317
6318 /* inject a 5-tuple filter to HW */
6319 static inline void
6320 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6321                            struct ixgbe_5tuple_filter *filter)
6322 {
6323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6324         int i;
6325         uint32_t ftqf, sdpqf;
6326         uint32_t l34timir = 0;
6327         uint8_t mask = 0xff;
6328
6329         i = filter->index;
6330
6331         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6332                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6333         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6334
6335         ftqf = (uint32_t)(filter->filter_info.proto &
6336                 IXGBE_FTQF_PROTOCOL_MASK);
6337         ftqf |= (uint32_t)((filter->filter_info.priority &
6338                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6339         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6340                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6341         if (filter->filter_info.dst_ip_mask == 0)
6342                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6343         if (filter->filter_info.src_port_mask == 0)
6344                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6345         if (filter->filter_info.dst_port_mask == 0)
6346                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6347         if (filter->filter_info.proto_mask == 0)
6348                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6349         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6350         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6351         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6352
6353         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6354         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6355         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6356         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6357
6358         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6359         l34timir |= (uint32_t)(filter->queue <<
6360                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6361         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6362 }
6363
6364 /*
6365  * add a 5tuple filter
6366  *
6367  * @param
6368  * dev: Pointer to struct rte_eth_dev.
6369  * index: the index the filter allocates.
6370  * filter: ponter to the filter that will be added.
6371  * rx_queue: the queue id the filter assigned to.
6372  *
6373  * @return
6374  *    - On success, zero.
6375  *    - On failure, a negative value.
6376  */
6377 static int
6378 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6379                         struct ixgbe_5tuple_filter *filter)
6380 {
6381         struct ixgbe_filter_info *filter_info =
6382                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6383         int i, idx, shift;
6384
6385         /*
6386          * look for an unused 5tuple filter index,
6387          * and insert the filter to list.
6388          */
6389         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6390                 idx = i / (sizeof(uint32_t) * NBBY);
6391                 shift = i % (sizeof(uint32_t) * NBBY);
6392                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6393                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6394                         filter->index = i;
6395                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6396                                           filter,
6397                                           entries);
6398                         break;
6399                 }
6400         }
6401         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6402                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6403                 return -ENOSYS;
6404         }
6405
6406         ixgbe_inject_5tuple_filter(dev, filter);
6407
6408         return 0;
6409 }
6410
6411 /*
6412  * remove a 5tuple filter
6413  *
6414  * @param
6415  * dev: Pointer to struct rte_eth_dev.
6416  * filter: the pointer of the filter will be removed.
6417  */
6418 static void
6419 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6420                         struct ixgbe_5tuple_filter *filter)
6421 {
6422         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6423         struct ixgbe_filter_info *filter_info =
6424                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6425         uint16_t index = filter->index;
6426
6427         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6428                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6429         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6430         rte_free(filter);
6431
6432         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6433         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6434         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6435         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6436         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6437 }
6438
6439 static int
6440 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6441 {
6442         struct ixgbe_hw *hw;
6443         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6444         struct rte_eth_dev_data *dev_data = dev->data;
6445
6446         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6447
6448         if (mtu < RTE_ETHER_MIN_MTU ||
6449                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6450                 return -EINVAL;
6451
6452         /* If device is started, refuse mtu that requires the support of
6453          * scattered packets when this feature has not been enabled before.
6454          */
6455         if (dev_data->dev_started && !dev_data->scattered_rx &&
6456             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6457              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6458                 PMD_INIT_LOG(ERR, "Stop port first.");
6459                 return -EINVAL;
6460         }
6461
6462         /*
6463          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6464          * request of the version 2.0 of the mailbox API.
6465          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6466          * of the mailbox API.
6467          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6468          * prior to 3.11.33 which contains the following change:
6469          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6470          */
6471         ixgbevf_rlpml_set_vf(hw, max_frame);
6472
6473         /* update max frame size */
6474         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6475         return 0;
6476 }
6477
6478 static inline struct ixgbe_5tuple_filter *
6479 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6480                         struct ixgbe_5tuple_filter_info *key)
6481 {
6482         struct ixgbe_5tuple_filter *it;
6483
6484         TAILQ_FOREACH(it, filter_list, entries) {
6485                 if (memcmp(key, &it->filter_info,
6486                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6487                         return it;
6488                 }
6489         }
6490         return NULL;
6491 }
6492
6493 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6494 static inline int
6495 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6496                         struct ixgbe_5tuple_filter_info *filter_info)
6497 {
6498         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6499                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6500                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6501                 return -EINVAL;
6502
6503         switch (filter->dst_ip_mask) {
6504         case UINT32_MAX:
6505                 filter_info->dst_ip_mask = 0;
6506                 filter_info->dst_ip = filter->dst_ip;
6507                 break;
6508         case 0:
6509                 filter_info->dst_ip_mask = 1;
6510                 break;
6511         default:
6512                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6513                 return -EINVAL;
6514         }
6515
6516         switch (filter->src_ip_mask) {
6517         case UINT32_MAX:
6518                 filter_info->src_ip_mask = 0;
6519                 filter_info->src_ip = filter->src_ip;
6520                 break;
6521         case 0:
6522                 filter_info->src_ip_mask = 1;
6523                 break;
6524         default:
6525                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6526                 return -EINVAL;
6527         }
6528
6529         switch (filter->dst_port_mask) {
6530         case UINT16_MAX:
6531                 filter_info->dst_port_mask = 0;
6532                 filter_info->dst_port = filter->dst_port;
6533                 break;
6534         case 0:
6535                 filter_info->dst_port_mask = 1;
6536                 break;
6537         default:
6538                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6539                 return -EINVAL;
6540         }
6541
6542         switch (filter->src_port_mask) {
6543         case UINT16_MAX:
6544                 filter_info->src_port_mask = 0;
6545                 filter_info->src_port = filter->src_port;
6546                 break;
6547         case 0:
6548                 filter_info->src_port_mask = 1;
6549                 break;
6550         default:
6551                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6552                 return -EINVAL;
6553         }
6554
6555         switch (filter->proto_mask) {
6556         case UINT8_MAX:
6557                 filter_info->proto_mask = 0;
6558                 filter_info->proto =
6559                         convert_protocol_type(filter->proto);
6560                 break;
6561         case 0:
6562                 filter_info->proto_mask = 1;
6563                 break;
6564         default:
6565                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6566                 return -EINVAL;
6567         }
6568
6569         filter_info->priority = (uint8_t)filter->priority;
6570         return 0;
6571 }
6572
6573 /*
6574  * add or delete a ntuple filter
6575  *
6576  * @param
6577  * dev: Pointer to struct rte_eth_dev.
6578  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6579  * add: if true, add filter, if false, remove filter
6580  *
6581  * @return
6582  *    - On success, zero.
6583  *    - On failure, a negative value.
6584  */
6585 int
6586 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6587                         struct rte_eth_ntuple_filter *ntuple_filter,
6588                         bool add)
6589 {
6590         struct ixgbe_filter_info *filter_info =
6591                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6592         struct ixgbe_5tuple_filter_info filter_5tuple;
6593         struct ixgbe_5tuple_filter *filter;
6594         int ret;
6595
6596         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6597                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6598                 return -EINVAL;
6599         }
6600
6601         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6602         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6603         if (ret < 0)
6604                 return ret;
6605
6606         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6607                                          &filter_5tuple);
6608         if (filter != NULL && add) {
6609                 PMD_DRV_LOG(ERR, "filter exists.");
6610                 return -EEXIST;
6611         }
6612         if (filter == NULL && !add) {
6613                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6614                 return -ENOENT;
6615         }
6616
6617         if (add) {
6618                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6619                                 sizeof(struct ixgbe_5tuple_filter), 0);
6620                 if (filter == NULL)
6621                         return -ENOMEM;
6622                 rte_memcpy(&filter->filter_info,
6623                                  &filter_5tuple,
6624                                  sizeof(struct ixgbe_5tuple_filter_info));
6625                 filter->queue = ntuple_filter->queue;
6626                 ret = ixgbe_add_5tuple_filter(dev, filter);
6627                 if (ret < 0) {
6628                         rte_free(filter);
6629                         return ret;
6630                 }
6631         } else
6632                 ixgbe_remove_5tuple_filter(dev, filter);
6633
6634         return 0;
6635 }
6636
6637 /*
6638  * get a ntuple filter
6639  *
6640  * @param
6641  * dev: Pointer to struct rte_eth_dev.
6642  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6643  *
6644  * @return
6645  *    - On success, zero.
6646  *    - On failure, a negative value.
6647  */
6648 static int
6649 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6650                         struct rte_eth_ntuple_filter *ntuple_filter)
6651 {
6652         struct ixgbe_filter_info *filter_info =
6653                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6654         struct ixgbe_5tuple_filter_info filter_5tuple;
6655         struct ixgbe_5tuple_filter *filter;
6656         int ret;
6657
6658         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6659                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6660                 return -EINVAL;
6661         }
6662
6663         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6664         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6665         if (ret < 0)
6666                 return ret;
6667
6668         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6669                                          &filter_5tuple);
6670         if (filter == NULL) {
6671                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6672                 return -ENOENT;
6673         }
6674         ntuple_filter->queue = filter->queue;
6675         return 0;
6676 }
6677
6678 /*
6679  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6680  * @dev: pointer to rte_eth_dev structure
6681  * @filter_op:operation will be taken.
6682  * @arg: a pointer to specific structure corresponding to the filter_op
6683  *
6684  * @return
6685  *    - On success, zero.
6686  *    - On failure, a negative value.
6687  */
6688 static int
6689 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6690                                 enum rte_filter_op filter_op,
6691                                 void *arg)
6692 {
6693         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6694         int ret;
6695
6696         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6697
6698         if (filter_op == RTE_ETH_FILTER_NOP)
6699                 return 0;
6700
6701         if (arg == NULL) {
6702                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6703                             filter_op);
6704                 return -EINVAL;
6705         }
6706
6707         switch (filter_op) {
6708         case RTE_ETH_FILTER_ADD:
6709                 ret = ixgbe_add_del_ntuple_filter(dev,
6710                         (struct rte_eth_ntuple_filter *)arg,
6711                         TRUE);
6712                 break;
6713         case RTE_ETH_FILTER_DELETE:
6714                 ret = ixgbe_add_del_ntuple_filter(dev,
6715                         (struct rte_eth_ntuple_filter *)arg,
6716                         FALSE);
6717                 break;
6718         case RTE_ETH_FILTER_GET:
6719                 ret = ixgbe_get_ntuple_filter(dev,
6720                         (struct rte_eth_ntuple_filter *)arg);
6721                 break;
6722         default:
6723                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6724                 ret = -EINVAL;
6725                 break;
6726         }
6727         return ret;
6728 }
6729
6730 int
6731 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6732                         struct rte_eth_ethertype_filter *filter,
6733                         bool add)
6734 {
6735         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736         struct ixgbe_filter_info *filter_info =
6737                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6738         uint32_t etqf = 0;
6739         uint32_t etqs = 0;
6740         int ret;
6741         struct ixgbe_ethertype_filter ethertype_filter;
6742
6743         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6744                 return -EINVAL;
6745
6746         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6747                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6748                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6749                         " ethertype filter.", filter->ether_type);
6750                 return -EINVAL;
6751         }
6752
6753         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6754                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6755                 return -EINVAL;
6756         }
6757         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6758                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6759                 return -EINVAL;
6760         }
6761
6762         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6763         if (ret >= 0 && add) {
6764                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6765                             filter->ether_type);
6766                 return -EEXIST;
6767         }
6768         if (ret < 0 && !add) {
6769                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6770                             filter->ether_type);
6771                 return -ENOENT;
6772         }
6773
6774         if (add) {
6775                 etqf = IXGBE_ETQF_FILTER_EN;
6776                 etqf |= (uint32_t)filter->ether_type;
6777                 etqs |= (uint32_t)((filter->queue <<
6778                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6779                                     IXGBE_ETQS_RX_QUEUE);
6780                 etqs |= IXGBE_ETQS_QUEUE_EN;
6781
6782                 ethertype_filter.ethertype = filter->ether_type;
6783                 ethertype_filter.etqf = etqf;
6784                 ethertype_filter.etqs = etqs;
6785                 ethertype_filter.conf = FALSE;
6786                 ret = ixgbe_ethertype_filter_insert(filter_info,
6787                                                     &ethertype_filter);
6788                 if (ret < 0) {
6789                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6790                         return -ENOSPC;
6791                 }
6792         } else {
6793                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6794                 if (ret < 0)
6795                         return -ENOSYS;
6796         }
6797         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6798         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6799         IXGBE_WRITE_FLUSH(hw);
6800
6801         return 0;
6802 }
6803
6804 static int
6805 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6806                         struct rte_eth_ethertype_filter *filter)
6807 {
6808         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6809         struct ixgbe_filter_info *filter_info =
6810                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6811         uint32_t etqf, etqs;
6812         int ret;
6813
6814         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6815         if (ret < 0) {
6816                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6817                             filter->ether_type);
6818                 return -ENOENT;
6819         }
6820
6821         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6822         if (etqf & IXGBE_ETQF_FILTER_EN) {
6823                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6824                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6825                 filter->flags = 0;
6826                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6827                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6828                 return 0;
6829         }
6830         return -ENOENT;
6831 }
6832
6833 /*
6834  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6835  * @dev: pointer to rte_eth_dev structure
6836  * @filter_op:operation will be taken.
6837  * @arg: a pointer to specific structure corresponding to the filter_op
6838  */
6839 static int
6840 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6841                                 enum rte_filter_op filter_op,
6842                                 void *arg)
6843 {
6844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6845         int ret;
6846
6847         MAC_TYPE_FILTER_SUP(hw->mac.type);
6848
6849         if (filter_op == RTE_ETH_FILTER_NOP)
6850                 return 0;
6851
6852         if (arg == NULL) {
6853                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6854                             filter_op);
6855                 return -EINVAL;
6856         }
6857
6858         switch (filter_op) {
6859         case RTE_ETH_FILTER_ADD:
6860                 ret = ixgbe_add_del_ethertype_filter(dev,
6861                         (struct rte_eth_ethertype_filter *)arg,
6862                         TRUE);
6863                 break;
6864         case RTE_ETH_FILTER_DELETE:
6865                 ret = ixgbe_add_del_ethertype_filter(dev,
6866                         (struct rte_eth_ethertype_filter *)arg,
6867                         FALSE);
6868                 break;
6869         case RTE_ETH_FILTER_GET:
6870                 ret = ixgbe_get_ethertype_filter(dev,
6871                         (struct rte_eth_ethertype_filter *)arg);
6872                 break;
6873         default:
6874                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6875                 ret = -EINVAL;
6876                 break;
6877         }
6878         return ret;
6879 }
6880
6881 static int
6882 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6883                      enum rte_filter_type filter_type,
6884                      enum rte_filter_op filter_op,
6885                      void *arg)
6886 {
6887         int ret = 0;
6888
6889         switch (filter_type) {
6890         case RTE_ETH_FILTER_NTUPLE:
6891                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6892                 break;
6893         case RTE_ETH_FILTER_ETHERTYPE:
6894                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6895                 break;
6896         case RTE_ETH_FILTER_SYN:
6897                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6898                 break;
6899         case RTE_ETH_FILTER_FDIR:
6900                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6901                 break;
6902         case RTE_ETH_FILTER_L2_TUNNEL:
6903                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6904                 break;
6905         case RTE_ETH_FILTER_GENERIC:
6906                 if (filter_op != RTE_ETH_FILTER_GET)
6907                         return -EINVAL;
6908                 *(const void **)arg = &ixgbe_flow_ops;
6909                 break;
6910         default:
6911                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6912                                                         filter_type);
6913                 ret = -EINVAL;
6914                 break;
6915         }
6916
6917         return ret;
6918 }
6919
6920 static u8 *
6921 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6922                         u8 **mc_addr_ptr, u32 *vmdq)
6923 {
6924         u8 *mc_addr;
6925
6926         *vmdq = 0;
6927         mc_addr = *mc_addr_ptr;
6928         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6929         return mc_addr;
6930 }
6931
6932 static int
6933 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6934                           struct rte_ether_addr *mc_addr_set,
6935                           uint32_t nb_mc_addr)
6936 {
6937         struct ixgbe_hw *hw;
6938         u8 *mc_addr_list;
6939
6940         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6941         mc_addr_list = (u8 *)mc_addr_set;
6942         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6943                                          ixgbe_dev_addr_list_itr, TRUE);
6944 }
6945
6946 static uint64_t
6947 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6948 {
6949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6950         uint64_t systime_cycles;
6951
6952         switch (hw->mac.type) {
6953         case ixgbe_mac_X550:
6954         case ixgbe_mac_X550EM_x:
6955         case ixgbe_mac_X550EM_a:
6956                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6957                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6958                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6959                                 * NSEC_PER_SEC;
6960                 break;
6961         default:
6962                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6963                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6964                                 << 32;
6965         }
6966
6967         return systime_cycles;
6968 }
6969
6970 static uint64_t
6971 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6972 {
6973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6974         uint64_t rx_tstamp_cycles;
6975
6976         switch (hw->mac.type) {
6977         case ixgbe_mac_X550:
6978         case ixgbe_mac_X550EM_x:
6979         case ixgbe_mac_X550EM_a:
6980                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6981                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6982                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6983                                 * NSEC_PER_SEC;
6984                 break;
6985         default:
6986                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6987                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6988                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6989                                 << 32;
6990         }
6991
6992         return rx_tstamp_cycles;
6993 }
6994
6995 static uint64_t
6996 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6997 {
6998         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6999         uint64_t tx_tstamp_cycles;
7000
7001         switch (hw->mac.type) {
7002         case ixgbe_mac_X550:
7003         case ixgbe_mac_X550EM_x:
7004         case ixgbe_mac_X550EM_a:
7005                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7006                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7007                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7008                                 * NSEC_PER_SEC;
7009                 break;
7010         default:
7011                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7012                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7013                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7014                                 << 32;
7015         }
7016
7017         return tx_tstamp_cycles;
7018 }
7019
7020 static void
7021 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7022 {
7023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7024         struct ixgbe_adapter *adapter = dev->data->dev_private;
7025         struct rte_eth_link link;
7026         uint32_t incval = 0;
7027         uint32_t shift = 0;
7028
7029         /* Get current link speed. */
7030         ixgbe_dev_link_update(dev, 1);
7031         rte_eth_linkstatus_get(dev, &link);
7032
7033         switch (link.link_speed) {
7034         case ETH_SPEED_NUM_100M:
7035                 incval = IXGBE_INCVAL_100;
7036                 shift = IXGBE_INCVAL_SHIFT_100;
7037                 break;
7038         case ETH_SPEED_NUM_1G:
7039                 incval = IXGBE_INCVAL_1GB;
7040                 shift = IXGBE_INCVAL_SHIFT_1GB;
7041                 break;
7042         case ETH_SPEED_NUM_10G:
7043         default:
7044                 incval = IXGBE_INCVAL_10GB;
7045                 shift = IXGBE_INCVAL_SHIFT_10GB;
7046                 break;
7047         }
7048
7049         switch (hw->mac.type) {
7050         case ixgbe_mac_X550:
7051         case ixgbe_mac_X550EM_x:
7052         case ixgbe_mac_X550EM_a:
7053                 /* Independent of link speed. */
7054                 incval = 1;
7055                 /* Cycles read will be interpreted as ns. */
7056                 shift = 0;
7057                 /* Fall-through */
7058         case ixgbe_mac_X540:
7059                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7060                 break;
7061         case ixgbe_mac_82599EB:
7062                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7063                 shift -= IXGBE_INCVAL_SHIFT_82599;
7064                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7065                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7066                 break;
7067         default:
7068                 /* Not supported. */
7069                 return;
7070         }
7071
7072         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7073         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7074         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7075
7076         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7077         adapter->systime_tc.cc_shift = shift;
7078         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7079
7080         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7081         adapter->rx_tstamp_tc.cc_shift = shift;
7082         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7083
7084         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7085         adapter->tx_tstamp_tc.cc_shift = shift;
7086         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7087 }
7088
7089 static int
7090 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7091 {
7092         struct ixgbe_adapter *adapter = dev->data->dev_private;
7093
7094         adapter->systime_tc.nsec += delta;
7095         adapter->rx_tstamp_tc.nsec += delta;
7096         adapter->tx_tstamp_tc.nsec += delta;
7097
7098         return 0;
7099 }
7100
7101 static int
7102 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7103 {
7104         uint64_t ns;
7105         struct ixgbe_adapter *adapter = dev->data->dev_private;
7106
7107         ns = rte_timespec_to_ns(ts);
7108         /* Set the timecounters to a new value. */
7109         adapter->systime_tc.nsec = ns;
7110         adapter->rx_tstamp_tc.nsec = ns;
7111         adapter->tx_tstamp_tc.nsec = ns;
7112
7113         return 0;
7114 }
7115
7116 static int
7117 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7118 {
7119         uint64_t ns, systime_cycles;
7120         struct ixgbe_adapter *adapter = dev->data->dev_private;
7121
7122         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7123         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7124         *ts = rte_ns_to_timespec(ns);
7125
7126         return 0;
7127 }
7128
7129 static int
7130 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7131 {
7132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7133         uint32_t tsync_ctl;
7134         uint32_t tsauxc;
7135
7136         /* Stop the timesync system time. */
7137         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7138         /* Reset the timesync system time value. */
7139         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7140         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7141
7142         /* Enable system time for platforms where it isn't on by default. */
7143         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7144         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7145         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7146
7147         ixgbe_start_timecounters(dev);
7148
7149         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7150         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7151                         (RTE_ETHER_TYPE_1588 |
7152                          IXGBE_ETQF_FILTER_EN |
7153                          IXGBE_ETQF_1588));
7154
7155         /* Enable timestamping of received PTP packets. */
7156         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7157         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7158         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7159
7160         /* Enable timestamping of transmitted PTP packets. */
7161         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7162         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7163         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7164
7165         IXGBE_WRITE_FLUSH(hw);
7166
7167         return 0;
7168 }
7169
7170 static int
7171 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7172 {
7173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7174         uint32_t tsync_ctl;
7175
7176         /* Disable timestamping of transmitted PTP packets. */
7177         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7178         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7179         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7180
7181         /* Disable timestamping of received PTP packets. */
7182         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7183         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7184         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7185
7186         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7187         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7188
7189         /* Stop incrementating the System Time registers. */
7190         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7191
7192         return 0;
7193 }
7194
7195 static int
7196 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7197                                  struct timespec *timestamp,
7198                                  uint32_t flags __rte_unused)
7199 {
7200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7201         struct ixgbe_adapter *adapter = dev->data->dev_private;
7202         uint32_t tsync_rxctl;
7203         uint64_t rx_tstamp_cycles;
7204         uint64_t ns;
7205
7206         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7207         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7208                 return -EINVAL;
7209
7210         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7211         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7212         *timestamp = rte_ns_to_timespec(ns);
7213
7214         return  0;
7215 }
7216
7217 static int
7218 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7219                                  struct timespec *timestamp)
7220 {
7221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7222         struct ixgbe_adapter *adapter = dev->data->dev_private;
7223         uint32_t tsync_txctl;
7224         uint64_t tx_tstamp_cycles;
7225         uint64_t ns;
7226
7227         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7228         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7229                 return -EINVAL;
7230
7231         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7232         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7233         *timestamp = rte_ns_to_timespec(ns);
7234
7235         return 0;
7236 }
7237
7238 static int
7239 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7240 {
7241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7242         int count = 0;
7243         int g_ind = 0;
7244         const struct reg_info *reg_group;
7245         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7246                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7247
7248         while ((reg_group = reg_set[g_ind++]))
7249                 count += ixgbe_regs_group_count(reg_group);
7250
7251         return count;
7252 }
7253
7254 static int
7255 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7256 {
7257         int count = 0;
7258         int g_ind = 0;
7259         const struct reg_info *reg_group;
7260
7261         while ((reg_group = ixgbevf_regs[g_ind++]))
7262                 count += ixgbe_regs_group_count(reg_group);
7263
7264         return count;
7265 }
7266
7267 static int
7268 ixgbe_get_regs(struct rte_eth_dev *dev,
7269               struct rte_dev_reg_info *regs)
7270 {
7271         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7272         uint32_t *data = regs->data;
7273         int g_ind = 0;
7274         int count = 0;
7275         const struct reg_info *reg_group;
7276         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7277                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7278
7279         if (data == NULL) {
7280                 regs->length = ixgbe_get_reg_length(dev);
7281                 regs->width = sizeof(uint32_t);
7282                 return 0;
7283         }
7284
7285         /* Support only full register dump */
7286         if ((regs->length == 0) ||
7287             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7288                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7289                         hw->device_id;
7290                 while ((reg_group = reg_set[g_ind++]))
7291                         count += ixgbe_read_regs_group(dev, &data[count],
7292                                 reg_group);
7293                 return 0;
7294         }
7295
7296         return -ENOTSUP;
7297 }
7298
7299 static int
7300 ixgbevf_get_regs(struct rte_eth_dev *dev,
7301                 struct rte_dev_reg_info *regs)
7302 {
7303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7304         uint32_t *data = regs->data;
7305         int g_ind = 0;
7306         int count = 0;
7307         const struct reg_info *reg_group;
7308
7309         if (data == NULL) {
7310                 regs->length = ixgbevf_get_reg_length(dev);
7311                 regs->width = sizeof(uint32_t);
7312                 return 0;
7313         }
7314
7315         /* Support only full register dump */
7316         if ((regs->length == 0) ||
7317             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7318                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7319                         hw->device_id;
7320                 while ((reg_group = ixgbevf_regs[g_ind++]))
7321                         count += ixgbe_read_regs_group(dev, &data[count],
7322                                                       reg_group);
7323                 return 0;
7324         }
7325
7326         return -ENOTSUP;
7327 }
7328
7329 static int
7330 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7331 {
7332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7333
7334         /* Return unit is byte count */
7335         return hw->eeprom.word_size * 2;
7336 }
7337
7338 static int
7339 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7340                 struct rte_dev_eeprom_info *in_eeprom)
7341 {
7342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7343         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7344         uint16_t *data = in_eeprom->data;
7345         int first, length;
7346
7347         first = in_eeprom->offset >> 1;
7348         length = in_eeprom->length >> 1;
7349         if ((first > hw->eeprom.word_size) ||
7350             ((first + length) > hw->eeprom.word_size))
7351                 return -EINVAL;
7352
7353         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7354
7355         return eeprom->ops.read_buffer(hw, first, length, data);
7356 }
7357
7358 static int
7359 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7360                 struct rte_dev_eeprom_info *in_eeprom)
7361 {
7362         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7363         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7364         uint16_t *data = in_eeprom->data;
7365         int first, length;
7366
7367         first = in_eeprom->offset >> 1;
7368         length = in_eeprom->length >> 1;
7369         if ((first > hw->eeprom.word_size) ||
7370             ((first + length) > hw->eeprom.word_size))
7371                 return -EINVAL;
7372
7373         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7374
7375         return eeprom->ops.write_buffer(hw,  first, length, data);
7376 }
7377
7378 static int
7379 ixgbe_get_module_info(struct rte_eth_dev *dev,
7380                       struct rte_eth_dev_module_info *modinfo)
7381 {
7382         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7383         uint32_t status;
7384         uint8_t sff8472_rev, addr_mode;
7385         bool page_swap = false;
7386
7387         /* Check whether we support SFF-8472 or not */
7388         status = hw->phy.ops.read_i2c_eeprom(hw,
7389                                              IXGBE_SFF_SFF_8472_COMP,
7390                                              &sff8472_rev);
7391         if (status != 0)
7392                 return -EIO;
7393
7394         /* addressing mode is not supported */
7395         status = hw->phy.ops.read_i2c_eeprom(hw,
7396                                              IXGBE_SFF_SFF_8472_SWAP,
7397                                              &addr_mode);
7398         if (status != 0)
7399                 return -EIO;
7400
7401         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7402                 PMD_DRV_LOG(ERR,
7403                             "Address change required to access page 0xA2, "
7404                             "but not supported. Please report the module "
7405                             "type to the driver maintainers.");
7406                 page_swap = true;
7407         }
7408
7409         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7410                 /* We have a SFP, but it does not support SFF-8472 */
7411                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7412                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7413         } else {
7414                 /* We have a SFP which supports a revision of SFF-8472. */
7415                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7416                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7417         }
7418
7419         return 0;
7420 }
7421
7422 static int
7423 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7424                         struct rte_dev_eeprom_info *info)
7425 {
7426         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7427         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7428         uint8_t databyte = 0xFF;
7429         uint8_t *data = info->data;
7430         uint32_t i = 0;
7431
7432         if (info->length == 0)
7433                 return -EINVAL;
7434
7435         for (i = info->offset; i < info->offset + info->length; i++) {
7436                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7437                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7438                 else
7439                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7440
7441                 if (status != 0)
7442                         return -EIO;
7443
7444                 data[i - info->offset] = databyte;
7445         }
7446
7447         return 0;
7448 }
7449
7450 uint16_t
7451 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7452         switch (mac_type) {
7453         case ixgbe_mac_X550:
7454         case ixgbe_mac_X550EM_x:
7455         case ixgbe_mac_X550EM_a:
7456                 return ETH_RSS_RETA_SIZE_512;
7457         case ixgbe_mac_X550_vf:
7458         case ixgbe_mac_X550EM_x_vf:
7459         case ixgbe_mac_X550EM_a_vf:
7460                 return ETH_RSS_RETA_SIZE_64;
7461         case ixgbe_mac_X540_vf:
7462         case ixgbe_mac_82599_vf:
7463                 return 0;
7464         default:
7465                 return ETH_RSS_RETA_SIZE_128;
7466         }
7467 }
7468
7469 uint32_t
7470 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7471         switch (mac_type) {
7472         case ixgbe_mac_X550:
7473         case ixgbe_mac_X550EM_x:
7474         case ixgbe_mac_X550EM_a:
7475                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7476                         return IXGBE_RETA(reta_idx >> 2);
7477                 else
7478                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7479         case ixgbe_mac_X550_vf:
7480         case ixgbe_mac_X550EM_x_vf:
7481         case ixgbe_mac_X550EM_a_vf:
7482                 return IXGBE_VFRETA(reta_idx >> 2);
7483         default:
7484                 return IXGBE_RETA(reta_idx >> 2);
7485         }
7486 }
7487
7488 uint32_t
7489 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7490         switch (mac_type) {
7491         case ixgbe_mac_X550_vf:
7492         case ixgbe_mac_X550EM_x_vf:
7493         case ixgbe_mac_X550EM_a_vf:
7494                 return IXGBE_VFMRQC;
7495         default:
7496                 return IXGBE_MRQC;
7497         }
7498 }
7499
7500 uint32_t
7501 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7502         switch (mac_type) {
7503         case ixgbe_mac_X550_vf:
7504         case ixgbe_mac_X550EM_x_vf:
7505         case ixgbe_mac_X550EM_a_vf:
7506                 return IXGBE_VFRSSRK(i);
7507         default:
7508                 return IXGBE_RSSRK(i);
7509         }
7510 }
7511
7512 bool
7513 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7514         switch (mac_type) {
7515         case ixgbe_mac_82599_vf:
7516         case ixgbe_mac_X540_vf:
7517                 return 0;
7518         default:
7519                 return 1;
7520         }
7521 }
7522
7523 static int
7524 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7525                         struct rte_eth_dcb_info *dcb_info)
7526 {
7527         struct ixgbe_dcb_config *dcb_config =
7528                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7529         struct ixgbe_dcb_tc_config *tc;
7530         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7531         uint8_t nb_tcs;
7532         uint8_t i, j;
7533
7534         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7535                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7536         else
7537                 dcb_info->nb_tcs = 1;
7538
7539         tc_queue = &dcb_info->tc_queue;
7540         nb_tcs = dcb_info->nb_tcs;
7541
7542         if (dcb_config->vt_mode) { /* vt is enabled*/
7543                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7544                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7545                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7546                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7547                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7548                         for (j = 0; j < nb_tcs; j++) {
7549                                 tc_queue->tc_rxq[0][j].base = j;
7550                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7551                                 tc_queue->tc_txq[0][j].base = j;
7552                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7553                         }
7554                 } else {
7555                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7556                                 for (j = 0; j < nb_tcs; j++) {
7557                                         tc_queue->tc_rxq[i][j].base =
7558                                                 i * nb_tcs + j;
7559                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7560                                         tc_queue->tc_txq[i][j].base =
7561                                                 i * nb_tcs + j;
7562                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7563                                 }
7564                         }
7565                 }
7566         } else { /* vt is disabled*/
7567                 struct rte_eth_dcb_rx_conf *rx_conf =
7568                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7569                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7570                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7571                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7572                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7573                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7574                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7575                         }
7576                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7577                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7578                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7579                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7580                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7581                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7582                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7583                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7584                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7585                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7586                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7587                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7588                         }
7589                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7590                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7591                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7592                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7593                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7594                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7595                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7596                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7597                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7598                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7599                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7600                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7601                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7602                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7603                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7604                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7605                 }
7606         }
7607         for (i = 0; i < dcb_info->nb_tcs; i++) {
7608                 tc = &dcb_config->tc_config[i];
7609                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7610         }
7611         return 0;
7612 }
7613
7614 /* Update e-tag ether type */
7615 static int
7616 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7617                             uint16_t ether_type)
7618 {
7619         uint32_t etag_etype;
7620
7621         if (hw->mac.type != ixgbe_mac_X550 &&
7622             hw->mac.type != ixgbe_mac_X550EM_x &&
7623             hw->mac.type != ixgbe_mac_X550EM_a) {
7624                 return -ENOTSUP;
7625         }
7626
7627         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7628         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7629         etag_etype |= ether_type;
7630         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7631         IXGBE_WRITE_FLUSH(hw);
7632
7633         return 0;
7634 }
7635
7636 /* Config l2 tunnel ether type */
7637 static int
7638 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7639                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7640 {
7641         int ret = 0;
7642         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7643         struct ixgbe_l2_tn_info *l2_tn_info =
7644                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7645
7646         if (l2_tunnel == NULL)
7647                 return -EINVAL;
7648
7649         switch (l2_tunnel->l2_tunnel_type) {
7650         case RTE_L2_TUNNEL_TYPE_E_TAG:
7651                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7652                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7653                 break;
7654         default:
7655                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7656                 ret = -EINVAL;
7657                 break;
7658         }
7659
7660         return ret;
7661 }
7662
7663 /* Enable e-tag tunnel */
7664 static int
7665 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7666 {
7667         uint32_t etag_etype;
7668
7669         if (hw->mac.type != ixgbe_mac_X550 &&
7670             hw->mac.type != ixgbe_mac_X550EM_x &&
7671             hw->mac.type != ixgbe_mac_X550EM_a) {
7672                 return -ENOTSUP;
7673         }
7674
7675         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7676         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7677         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7678         IXGBE_WRITE_FLUSH(hw);
7679
7680         return 0;
7681 }
7682
7683 /* Enable l2 tunnel */
7684 static int
7685 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7686                            enum rte_eth_tunnel_type l2_tunnel_type)
7687 {
7688         int ret = 0;
7689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7690         struct ixgbe_l2_tn_info *l2_tn_info =
7691                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7692
7693         switch (l2_tunnel_type) {
7694         case RTE_L2_TUNNEL_TYPE_E_TAG:
7695                 l2_tn_info->e_tag_en = TRUE;
7696                 ret = ixgbe_e_tag_enable(hw);
7697                 break;
7698         default:
7699                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7700                 ret = -EINVAL;
7701                 break;
7702         }
7703
7704         return ret;
7705 }
7706
7707 /* Disable e-tag tunnel */
7708 static int
7709 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7710 {
7711         uint32_t etag_etype;
7712
7713         if (hw->mac.type != ixgbe_mac_X550 &&
7714             hw->mac.type != ixgbe_mac_X550EM_x &&
7715             hw->mac.type != ixgbe_mac_X550EM_a) {
7716                 return -ENOTSUP;
7717         }
7718
7719         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7720         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7721         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7722         IXGBE_WRITE_FLUSH(hw);
7723
7724         return 0;
7725 }
7726
7727 /* Disable l2 tunnel */
7728 static int
7729 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7730                             enum rte_eth_tunnel_type l2_tunnel_type)
7731 {
7732         int ret = 0;
7733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7734         struct ixgbe_l2_tn_info *l2_tn_info =
7735                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7736
7737         switch (l2_tunnel_type) {
7738         case RTE_L2_TUNNEL_TYPE_E_TAG:
7739                 l2_tn_info->e_tag_en = FALSE;
7740                 ret = ixgbe_e_tag_disable(hw);
7741                 break;
7742         default:
7743                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7744                 ret = -EINVAL;
7745                 break;
7746         }
7747
7748         return ret;
7749 }
7750
7751 static int
7752 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7753                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7754 {
7755         int ret = 0;
7756         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7757         uint32_t i, rar_entries;
7758         uint32_t rar_low, rar_high;
7759
7760         if (hw->mac.type != ixgbe_mac_X550 &&
7761             hw->mac.type != ixgbe_mac_X550EM_x &&
7762             hw->mac.type != ixgbe_mac_X550EM_a) {
7763                 return -ENOTSUP;
7764         }
7765
7766         rar_entries = ixgbe_get_num_rx_addrs(hw);
7767
7768         for (i = 1; i < rar_entries; i++) {
7769                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7770                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7771                 if ((rar_high & IXGBE_RAH_AV) &&
7772                     (rar_high & IXGBE_RAH_ADTYPE) &&
7773                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7774                      l2_tunnel->tunnel_id)) {
7775                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7776                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7777
7778                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7779
7780                         return ret;
7781                 }
7782         }
7783
7784         return ret;
7785 }
7786
7787 static int
7788 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7789                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7790 {
7791         int ret = 0;
7792         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7793         uint32_t i, rar_entries;
7794         uint32_t rar_low, rar_high;
7795
7796         if (hw->mac.type != ixgbe_mac_X550 &&
7797             hw->mac.type != ixgbe_mac_X550EM_x &&
7798             hw->mac.type != ixgbe_mac_X550EM_a) {
7799                 return -ENOTSUP;
7800         }
7801
7802         /* One entry for one tunnel. Try to remove potential existing entry. */
7803         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7804
7805         rar_entries = ixgbe_get_num_rx_addrs(hw);
7806
7807         for (i = 1; i < rar_entries; i++) {
7808                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7809                 if (rar_high & IXGBE_RAH_AV) {
7810                         continue;
7811                 } else {
7812                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7813                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7814                         rar_low = l2_tunnel->tunnel_id;
7815
7816                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7817                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7818
7819                         return ret;
7820                 }
7821         }
7822
7823         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7824                      " Please remove a rule before adding a new one.");
7825         return -EINVAL;
7826 }
7827
7828 static inline struct ixgbe_l2_tn_filter *
7829 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7830                           struct ixgbe_l2_tn_key *key)
7831 {
7832         int ret;
7833
7834         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7835         if (ret < 0)
7836                 return NULL;
7837
7838         return l2_tn_info->hash_map[ret];
7839 }
7840
7841 static inline int
7842 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7843                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7844 {
7845         int ret;
7846
7847         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7848                                &l2_tn_filter->key);
7849
7850         if (ret < 0) {
7851                 PMD_DRV_LOG(ERR,
7852                             "Failed to insert L2 tunnel filter"
7853                             " to hash table %d!",
7854                             ret);
7855                 return ret;
7856         }
7857
7858         l2_tn_info->hash_map[ret] = l2_tn_filter;
7859
7860         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7861
7862         return 0;
7863 }
7864
7865 static inline int
7866 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7867                           struct ixgbe_l2_tn_key *key)
7868 {
7869         int ret;
7870         struct ixgbe_l2_tn_filter *l2_tn_filter;
7871
7872         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7873
7874         if (ret < 0) {
7875                 PMD_DRV_LOG(ERR,
7876                             "No such L2 tunnel filter to delete %d!",
7877                             ret);
7878                 return ret;
7879         }
7880
7881         l2_tn_filter = l2_tn_info->hash_map[ret];
7882         l2_tn_info->hash_map[ret] = NULL;
7883
7884         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7885         rte_free(l2_tn_filter);
7886
7887         return 0;
7888 }
7889
7890 /* Add l2 tunnel filter */
7891 int
7892 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7893                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7894                                bool restore)
7895 {
7896         int ret;
7897         struct ixgbe_l2_tn_info *l2_tn_info =
7898                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7899         struct ixgbe_l2_tn_key key;
7900         struct ixgbe_l2_tn_filter *node;
7901
7902         if (!restore) {
7903                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7904                 key.tn_id = l2_tunnel->tunnel_id;
7905
7906                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7907
7908                 if (node) {
7909                         PMD_DRV_LOG(ERR,
7910                                     "The L2 tunnel filter already exists!");
7911                         return -EINVAL;
7912                 }
7913
7914                 node = rte_zmalloc("ixgbe_l2_tn",
7915                                    sizeof(struct ixgbe_l2_tn_filter),
7916                                    0);
7917                 if (!node)
7918                         return -ENOMEM;
7919
7920                 rte_memcpy(&node->key,
7921                                  &key,
7922                                  sizeof(struct ixgbe_l2_tn_key));
7923                 node->pool = l2_tunnel->pool;
7924                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7925                 if (ret < 0) {
7926                         rte_free(node);
7927                         return ret;
7928                 }
7929         }
7930
7931         switch (l2_tunnel->l2_tunnel_type) {
7932         case RTE_L2_TUNNEL_TYPE_E_TAG:
7933                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7934                 break;
7935         default:
7936                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7937                 ret = -EINVAL;
7938                 break;
7939         }
7940
7941         if ((!restore) && (ret < 0))
7942                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7943
7944         return ret;
7945 }
7946
7947 /* Delete l2 tunnel filter */
7948 int
7949 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7950                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7951 {
7952         int ret;
7953         struct ixgbe_l2_tn_info *l2_tn_info =
7954                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7955         struct ixgbe_l2_tn_key key;
7956
7957         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7958         key.tn_id = l2_tunnel->tunnel_id;
7959         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7960         if (ret < 0)
7961                 return ret;
7962
7963         switch (l2_tunnel->l2_tunnel_type) {
7964         case RTE_L2_TUNNEL_TYPE_E_TAG:
7965                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7966                 break;
7967         default:
7968                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7969                 ret = -EINVAL;
7970                 break;
7971         }
7972
7973         return ret;
7974 }
7975
7976 /**
7977  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7978  * @dev: pointer to rte_eth_dev structure
7979  * @filter_op:operation will be taken.
7980  * @arg: a pointer to specific structure corresponding to the filter_op
7981  */
7982 static int
7983 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7984                                   enum rte_filter_op filter_op,
7985                                   void *arg)
7986 {
7987         int ret;
7988
7989         if (filter_op == RTE_ETH_FILTER_NOP)
7990                 return 0;
7991
7992         if (arg == NULL) {
7993                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7994                             filter_op);
7995                 return -EINVAL;
7996         }
7997
7998         switch (filter_op) {
7999         case RTE_ETH_FILTER_ADD:
8000                 ret = ixgbe_dev_l2_tunnel_filter_add
8001                         (dev,
8002                          (struct rte_eth_l2_tunnel_conf *)arg,
8003                          FALSE);
8004                 break;
8005         case RTE_ETH_FILTER_DELETE:
8006                 ret = ixgbe_dev_l2_tunnel_filter_del
8007                         (dev,
8008                          (struct rte_eth_l2_tunnel_conf *)arg);
8009                 break;
8010         default:
8011                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8012                 ret = -EINVAL;
8013                 break;
8014         }
8015         return ret;
8016 }
8017
8018 static int
8019 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8020 {
8021         int ret = 0;
8022         uint32_t ctrl;
8023         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8024
8025         if (hw->mac.type != ixgbe_mac_X550 &&
8026             hw->mac.type != ixgbe_mac_X550EM_x &&
8027             hw->mac.type != ixgbe_mac_X550EM_a) {
8028                 return -ENOTSUP;
8029         }
8030
8031         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8032         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8033         if (en)
8034                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8035         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8036
8037         return ret;
8038 }
8039
8040 /* Enable l2 tunnel forwarding */
8041 static int
8042 ixgbe_dev_l2_tunnel_forwarding_enable
8043         (struct rte_eth_dev *dev,
8044          enum rte_eth_tunnel_type l2_tunnel_type)
8045 {
8046         struct ixgbe_l2_tn_info *l2_tn_info =
8047                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8048         int ret = 0;
8049
8050         switch (l2_tunnel_type) {
8051         case RTE_L2_TUNNEL_TYPE_E_TAG:
8052                 l2_tn_info->e_tag_fwd_en = TRUE;
8053                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8054                 break;
8055         default:
8056                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8057                 ret = -EINVAL;
8058                 break;
8059         }
8060
8061         return ret;
8062 }
8063
8064 /* Disable l2 tunnel forwarding */
8065 static int
8066 ixgbe_dev_l2_tunnel_forwarding_disable
8067         (struct rte_eth_dev *dev,
8068          enum rte_eth_tunnel_type l2_tunnel_type)
8069 {
8070         struct ixgbe_l2_tn_info *l2_tn_info =
8071                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8072         int ret = 0;
8073
8074         switch (l2_tunnel_type) {
8075         case RTE_L2_TUNNEL_TYPE_E_TAG:
8076                 l2_tn_info->e_tag_fwd_en = FALSE;
8077                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8078                 break;
8079         default:
8080                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8081                 ret = -EINVAL;
8082                 break;
8083         }
8084
8085         return ret;
8086 }
8087
8088 static int
8089 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8090                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8091                              bool en)
8092 {
8093         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8094         int ret = 0;
8095         uint32_t vmtir, vmvir;
8096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8097
8098         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8099                 PMD_DRV_LOG(ERR,
8100                             "VF id %u should be less than %u",
8101                             l2_tunnel->vf_id,
8102                             pci_dev->max_vfs);
8103                 return -EINVAL;
8104         }
8105
8106         if (hw->mac.type != ixgbe_mac_X550 &&
8107             hw->mac.type != ixgbe_mac_X550EM_x &&
8108             hw->mac.type != ixgbe_mac_X550EM_a) {
8109                 return -ENOTSUP;
8110         }
8111
8112         if (en)
8113                 vmtir = l2_tunnel->tunnel_id;
8114         else
8115                 vmtir = 0;
8116
8117         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8118
8119         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8120         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8121         if (en)
8122                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8123         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8124
8125         return ret;
8126 }
8127
8128 /* Enable l2 tunnel tag insertion */
8129 static int
8130 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8131                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8132 {
8133         int ret = 0;
8134
8135         switch (l2_tunnel->l2_tunnel_type) {
8136         case RTE_L2_TUNNEL_TYPE_E_TAG:
8137                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8138                 break;
8139         default:
8140                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8141                 ret = -EINVAL;
8142                 break;
8143         }
8144
8145         return ret;
8146 }
8147
8148 /* Disable l2 tunnel tag insertion */
8149 static int
8150 ixgbe_dev_l2_tunnel_insertion_disable
8151         (struct rte_eth_dev *dev,
8152          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8153 {
8154         int ret = 0;
8155
8156         switch (l2_tunnel->l2_tunnel_type) {
8157         case RTE_L2_TUNNEL_TYPE_E_TAG:
8158                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8159                 break;
8160         default:
8161                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8162                 ret = -EINVAL;
8163                 break;
8164         }
8165
8166         return ret;
8167 }
8168
8169 static int
8170 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8171                              bool en)
8172 {
8173         int ret = 0;
8174         uint32_t qde;
8175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8176
8177         if (hw->mac.type != ixgbe_mac_X550 &&
8178             hw->mac.type != ixgbe_mac_X550EM_x &&
8179             hw->mac.type != ixgbe_mac_X550EM_a) {
8180                 return -ENOTSUP;
8181         }
8182
8183         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8184         if (en)
8185                 qde |= IXGBE_QDE_STRIP_TAG;
8186         else
8187                 qde &= ~IXGBE_QDE_STRIP_TAG;
8188         qde &= ~IXGBE_QDE_READ;
8189         qde |= IXGBE_QDE_WRITE;
8190         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8191
8192         return ret;
8193 }
8194
8195 /* Enable l2 tunnel tag stripping */
8196 static int
8197 ixgbe_dev_l2_tunnel_stripping_enable
8198         (struct rte_eth_dev *dev,
8199          enum rte_eth_tunnel_type l2_tunnel_type)
8200 {
8201         int ret = 0;
8202
8203         switch (l2_tunnel_type) {
8204         case RTE_L2_TUNNEL_TYPE_E_TAG:
8205                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8206                 break;
8207         default:
8208                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8209                 ret = -EINVAL;
8210                 break;
8211         }
8212
8213         return ret;
8214 }
8215
8216 /* Disable l2 tunnel tag stripping */
8217 static int
8218 ixgbe_dev_l2_tunnel_stripping_disable
8219         (struct rte_eth_dev *dev,
8220          enum rte_eth_tunnel_type l2_tunnel_type)
8221 {
8222         int ret = 0;
8223
8224         switch (l2_tunnel_type) {
8225         case RTE_L2_TUNNEL_TYPE_E_TAG:
8226                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8227                 break;
8228         default:
8229                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8230                 ret = -EINVAL;
8231                 break;
8232         }
8233
8234         return ret;
8235 }
8236
8237 /* Enable/disable l2 tunnel offload functions */
8238 static int
8239 ixgbe_dev_l2_tunnel_offload_set
8240         (struct rte_eth_dev *dev,
8241          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8242          uint32_t mask,
8243          uint8_t en)
8244 {
8245         int ret = 0;
8246
8247         if (l2_tunnel == NULL)
8248                 return -EINVAL;
8249
8250         ret = -EINVAL;
8251         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8252                 if (en)
8253                         ret = ixgbe_dev_l2_tunnel_enable(
8254                                 dev,
8255                                 l2_tunnel->l2_tunnel_type);
8256                 else
8257                         ret = ixgbe_dev_l2_tunnel_disable(
8258                                 dev,
8259                                 l2_tunnel->l2_tunnel_type);
8260         }
8261
8262         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8263                 if (en)
8264                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8265                                 dev,
8266                                 l2_tunnel);
8267                 else
8268                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8269                                 dev,
8270                                 l2_tunnel);
8271         }
8272
8273         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8274                 if (en)
8275                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8276                                 dev,
8277                                 l2_tunnel->l2_tunnel_type);
8278                 else
8279                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8280                                 dev,
8281                                 l2_tunnel->l2_tunnel_type);
8282         }
8283
8284         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8285                 if (en)
8286                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8287                                 dev,
8288                                 l2_tunnel->l2_tunnel_type);
8289                 else
8290                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8291                                 dev,
8292                                 l2_tunnel->l2_tunnel_type);
8293         }
8294
8295         return ret;
8296 }
8297
8298 static int
8299 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8300                         uint16_t port)
8301 {
8302         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8303         IXGBE_WRITE_FLUSH(hw);
8304
8305         return 0;
8306 }
8307
8308 /* There's only one register for VxLAN UDP port.
8309  * So, we cannot add several ports. Will update it.
8310  */
8311 static int
8312 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8313                      uint16_t port)
8314 {
8315         if (port == 0) {
8316                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8317                 return -EINVAL;
8318         }
8319
8320         return ixgbe_update_vxlan_port(hw, port);
8321 }
8322
8323 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8324  * UDP port, it must have a value.
8325  * So, will reset it to the original value 0.
8326  */
8327 static int
8328 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8329                      uint16_t port)
8330 {
8331         uint16_t cur_port;
8332
8333         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8334
8335         if (cur_port != port) {
8336                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8337                 return -EINVAL;
8338         }
8339
8340         return ixgbe_update_vxlan_port(hw, 0);
8341 }
8342
8343 /* Add UDP tunneling port */
8344 static int
8345 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8346                               struct rte_eth_udp_tunnel *udp_tunnel)
8347 {
8348         int ret = 0;
8349         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8350
8351         if (hw->mac.type != ixgbe_mac_X550 &&
8352             hw->mac.type != ixgbe_mac_X550EM_x &&
8353             hw->mac.type != ixgbe_mac_X550EM_a) {
8354                 return -ENOTSUP;
8355         }
8356
8357         if (udp_tunnel == NULL)
8358                 return -EINVAL;
8359
8360         switch (udp_tunnel->prot_type) {
8361         case RTE_TUNNEL_TYPE_VXLAN:
8362                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8363                 break;
8364
8365         case RTE_TUNNEL_TYPE_GENEVE:
8366         case RTE_TUNNEL_TYPE_TEREDO:
8367                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8368                 ret = -EINVAL;
8369                 break;
8370
8371         default:
8372                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8373                 ret = -EINVAL;
8374                 break;
8375         }
8376
8377         return ret;
8378 }
8379
8380 /* Remove UDP tunneling port */
8381 static int
8382 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8383                               struct rte_eth_udp_tunnel *udp_tunnel)
8384 {
8385         int ret = 0;
8386         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8387
8388         if (hw->mac.type != ixgbe_mac_X550 &&
8389             hw->mac.type != ixgbe_mac_X550EM_x &&
8390             hw->mac.type != ixgbe_mac_X550EM_a) {
8391                 return -ENOTSUP;
8392         }
8393
8394         if (udp_tunnel == NULL)
8395                 return -EINVAL;
8396
8397         switch (udp_tunnel->prot_type) {
8398         case RTE_TUNNEL_TYPE_VXLAN:
8399                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8400                 break;
8401         case RTE_TUNNEL_TYPE_GENEVE:
8402         case RTE_TUNNEL_TYPE_TEREDO:
8403                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8404                 ret = -EINVAL;
8405                 break;
8406         default:
8407                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8408                 ret = -EINVAL;
8409                 break;
8410         }
8411
8412         return ret;
8413 }
8414
8415 static int
8416 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8417 {
8418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8419         int ret;
8420
8421         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8422         case IXGBE_SUCCESS:
8423                 ret = 0;
8424                 break;
8425         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8426                 ret = -ENOTSUP;
8427                 break;
8428         default:
8429                 ret = -EAGAIN;
8430                 break;
8431         }
8432
8433         return ret;
8434 }
8435
8436 static int
8437 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8438 {
8439         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8440         int ret;
8441
8442         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8443         case IXGBE_SUCCESS:
8444                 ret = 0;
8445                 break;
8446         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8447                 ret = -ENOTSUP;
8448                 break;
8449         default:
8450                 ret = -EAGAIN;
8451                 break;
8452         }
8453
8454         return ret;
8455 }
8456
8457 static void
8458 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8459 {
8460         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8461
8462         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8463 }
8464
8465 static void
8466 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8467 {
8468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8469
8470         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8471 }
8472
8473 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8474 {
8475         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8476         u32 in_msg = 0;
8477
8478         /* peek the message first */
8479         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8480
8481         /* PF reset VF event */
8482         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8483                 /* dummy mbx read to ack pf */
8484                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8485                         return;
8486                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8487                                               NULL);
8488         }
8489 }
8490
8491 static int
8492 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8493 {
8494         uint32_t eicr;
8495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8496         struct ixgbe_interrupt *intr =
8497                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8498         ixgbevf_intr_disable(dev);
8499
8500         /* read-on-clear nic registers here */
8501         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8502         intr->flags = 0;
8503
8504         /* only one misc vector supported - mailbox */
8505         eicr &= IXGBE_VTEICR_MASK;
8506         if (eicr == IXGBE_MISC_VEC_ID)
8507                 intr->flags |= IXGBE_FLAG_MAILBOX;
8508
8509         return 0;
8510 }
8511
8512 static int
8513 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8514 {
8515         struct ixgbe_interrupt *intr =
8516                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8517
8518         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8519                 ixgbevf_mbx_process(dev);
8520                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8521         }
8522
8523         ixgbevf_intr_enable(dev);
8524
8525         return 0;
8526 }
8527
8528 static void
8529 ixgbevf_dev_interrupt_handler(void *param)
8530 {
8531         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8532
8533         ixgbevf_dev_interrupt_get_status(dev);
8534         ixgbevf_dev_interrupt_action(dev);
8535 }
8536
8537 /**
8538  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8539  *  @hw: pointer to hardware structure
8540  *
8541  *  Stops the transmit data path and waits for the HW to internally empty
8542  *  the Tx security block
8543  **/
8544 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8545 {
8546 #define IXGBE_MAX_SECTX_POLL 40
8547
8548         int i;
8549         int sectxreg;
8550
8551         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8552         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8553         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8554         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8555                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8556                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8557                         break;
8558                 /* Use interrupt-safe sleep just in case */
8559                 usec_delay(1000);
8560         }
8561
8562         /* For informational purposes only */
8563         if (i >= IXGBE_MAX_SECTX_POLL)
8564                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8565                          "path fully disabled.  Continuing with init.");
8566
8567         return IXGBE_SUCCESS;
8568 }
8569
8570 /**
8571  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8572  *  @hw: pointer to hardware structure
8573  *
8574  *  Enables the transmit data path.
8575  **/
8576 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8577 {
8578         uint32_t sectxreg;
8579
8580         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8581         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8582         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8583         IXGBE_WRITE_FLUSH(hw);
8584
8585         return IXGBE_SUCCESS;
8586 }
8587
8588 /* restore n-tuple filter */
8589 static inline void
8590 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8591 {
8592         struct ixgbe_filter_info *filter_info =
8593                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8594         struct ixgbe_5tuple_filter *node;
8595
8596         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8597                 ixgbe_inject_5tuple_filter(dev, node);
8598         }
8599 }
8600
8601 /* restore ethernet type filter */
8602 static inline void
8603 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8604 {
8605         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8606         struct ixgbe_filter_info *filter_info =
8607                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8608         int i;
8609
8610         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8611                 if (filter_info->ethertype_mask & (1 << i)) {
8612                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8613                                         filter_info->ethertype_filters[i].etqf);
8614                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8615                                         filter_info->ethertype_filters[i].etqs);
8616                         IXGBE_WRITE_FLUSH(hw);
8617                 }
8618         }
8619 }
8620
8621 /* restore SYN filter */
8622 static inline void
8623 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8624 {
8625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8626         struct ixgbe_filter_info *filter_info =
8627                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8628         uint32_t synqf;
8629
8630         synqf = filter_info->syn_info;
8631
8632         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8633                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8634                 IXGBE_WRITE_FLUSH(hw);
8635         }
8636 }
8637
8638 /* restore L2 tunnel filter */
8639 static inline void
8640 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8641 {
8642         struct ixgbe_l2_tn_info *l2_tn_info =
8643                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8644         struct ixgbe_l2_tn_filter *node;
8645         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8646
8647         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8648                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8649                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8650                 l2_tn_conf.pool           = node->pool;
8651                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8652         }
8653 }
8654
8655 /* restore rss filter */
8656 static inline void
8657 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8658 {
8659         struct ixgbe_filter_info *filter_info =
8660                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8661
8662         if (filter_info->rss_info.conf.queue_num)
8663                 ixgbe_config_rss_filter(dev,
8664                         &filter_info->rss_info, TRUE);
8665 }
8666
8667 static int
8668 ixgbe_filter_restore(struct rte_eth_dev *dev)
8669 {
8670         ixgbe_ntuple_filter_restore(dev);
8671         ixgbe_ethertype_filter_restore(dev);
8672         ixgbe_syn_filter_restore(dev);
8673         ixgbe_fdir_filter_restore(dev);
8674         ixgbe_l2_tn_filter_restore(dev);
8675         ixgbe_rss_filter_restore(dev);
8676
8677         return 0;
8678 }
8679
8680 static void
8681 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8682 {
8683         struct ixgbe_l2_tn_info *l2_tn_info =
8684                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8685         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8686
8687         if (l2_tn_info->e_tag_en)
8688                 (void)ixgbe_e_tag_enable(hw);
8689
8690         if (l2_tn_info->e_tag_fwd_en)
8691                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8692
8693         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8694 }
8695
8696 /* remove all the n-tuple filters */
8697 void
8698 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8699 {
8700         struct ixgbe_filter_info *filter_info =
8701                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8702         struct ixgbe_5tuple_filter *p_5tuple;
8703
8704         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8705                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8706 }
8707
8708 /* remove all the ether type filters */
8709 void
8710 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8711 {
8712         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8713         struct ixgbe_filter_info *filter_info =
8714                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8715         int i;
8716
8717         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8718                 if (filter_info->ethertype_mask & (1 << i) &&
8719                     !filter_info->ethertype_filters[i].conf) {
8720                         (void)ixgbe_ethertype_filter_remove(filter_info,
8721                                                             (uint8_t)i);
8722                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8723                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8724                         IXGBE_WRITE_FLUSH(hw);
8725                 }
8726         }
8727 }
8728
8729 /* remove the SYN filter */
8730 void
8731 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8732 {
8733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8734         struct ixgbe_filter_info *filter_info =
8735                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8736
8737         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8738                 filter_info->syn_info = 0;
8739
8740                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8741                 IXGBE_WRITE_FLUSH(hw);
8742         }
8743 }
8744
8745 /* remove all the L2 tunnel filters */
8746 int
8747 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8748 {
8749         struct ixgbe_l2_tn_info *l2_tn_info =
8750                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8751         struct ixgbe_l2_tn_filter *l2_tn_filter;
8752         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8753         int ret = 0;
8754
8755         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8756                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8757                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8758                 l2_tn_conf.pool           = l2_tn_filter->pool;
8759                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8760                 if (ret < 0)
8761                         return ret;
8762         }
8763
8764         return 0;
8765 }
8766
8767 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8768 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8769 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8770 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8771 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8772 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8773 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8774                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8775
8776 RTE_INIT(ixgbe_init_log)
8777 {
8778         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8779         if (ixgbe_logtype_init >= 0)
8780                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8781         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8782         if (ixgbe_logtype_driver >= 0)
8783                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8784 }