drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153
 154 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 155 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 156 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 157 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 158 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 159 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 160 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 161 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 163 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 164 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 167                                 int wait_to_complete);
 168 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 169                                 struct rte_eth_stats *stats);
 170 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 171                                 struct rte_eth_xstats *xstats, unsigned n);
 172 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 173                                   struct rte_eth_xstats *xstats, unsigned n);
 174 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 181                                struct rte_eth_dev_info *dev_info);
 182 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 183                                  struct rte_eth_dev_info *dev_info);
 184 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 185
 186 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 187                 uint16_t vlan_id, int on);
 188 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 189                                enum rte_vlan_type vlan_type,
 190                                uint16_t tpid_id);
 191 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 192                 uint16_t queue, bool on);
 193 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 194                 int on);
 195 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 200
 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 204                                struct rte_eth_fc_conf *fc_conf);
 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 206                                struct rte_eth_fc_conf *fc_conf);
 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 208                 struct rte_eth_pfc_conf *pfc_conf);
 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 210                         struct rte_eth_rss_reta_entry64 *reta_conf,
 211                         uint16_t reta_size);
 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 218 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 220 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 221                 void *param);
 222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 223 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 224                 uint32_t index, uint32_t pool);
 225 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 226 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 227                                            struct ether_addr *mac_addr);
 228 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 229
 230 /* For Virtual Function support */
 231 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 232 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 233 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 234 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 235 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 236 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 237 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 238 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 239 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 240                 struct rte_eth_stats *stats);
 241 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 242 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 243                 uint16_t vlan_id, int on);
 244 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 245                 uint16_t queue, int on);
 246 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 247 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 248 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 249                                             uint16_t queue_id);
 250 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 251                                              uint16_t queue_id);
 252 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 253                                  uint8_t queue, uint8_t msix_vector);
 254 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 255
 256 /* For Eth VMDQ APIs support */
 257 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 258                 ether_addr* mac_addr,uint8_t on);
 259 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 260 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 261                 uint16_t rx_mask, uint8_t on);
 262 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 263 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 264 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 265                 uint64_t pool_mask,uint8_t vlan_on);
 266 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 267                 struct rte_eth_mirror_conf *mirror_conf,
 268                 uint8_t rule_id, uint8_t on);
 269 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 270                 uint8_t rule_id);
 271 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                           uint16_t queue_id);
 273 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                            uint16_t queue_id);
 275 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 276                                uint8_t queue, uint8_t msix_vector);
 277 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 278
 279 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 280                 uint16_t queue_idx, uint16_t tx_rate);
 281 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 282                 uint16_t tx_rate, uint64_t q_msk);
 283
 284 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                  struct ether_addr *mac_addr,
 286                                  uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter,
 292                         bool add);
 293 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 294                         struct rte_eth_syn_filter *filter);
 295 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 296                         enum rte_filter_op filter_op,
 297                         void *arg);
 298 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 299                         struct ixgbe_5tuple_filter *filter);
 300 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 301                         struct ixgbe_5tuple_filter *filter);
 302 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter,
 304                         bool add);
 305 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 306                                 enum rte_filter_op filter_op,
 307                                 void *arg);
 308 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 309                         struct rte_eth_ntuple_filter *filter);
 310 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 311                         struct rte_eth_ethertype_filter *filter,
 312                         bool add);
 313 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 314                                 enum rte_filter_op filter_op,
 315                                 void *arg);
 316 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 317                         struct rte_eth_ethertype_filter *filter);
 318 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 319                      enum rte_filter_type filter_type,
 320                      enum rte_filter_op filter_op,
 321                      void *arg);
 322 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 323
 324 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 325                                       struct ether_addr *mc_addr_set,
 326                                       uint32_t nb_mc_addr);
 327 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                    struct rte_eth_dcb_info *dcb_info);
 329
 330 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 331 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 332                             struct rte_dev_reg_info *regs);
 333 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 334 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 335                                 struct rte_dev_eeprom_info *eeprom);
 336 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 337                                 struct rte_dev_eeprom_info *eeprom);
 338
 339 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 340 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 341                                 struct rte_dev_reg_info *regs);
 342
 343 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 344 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 345 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                             struct timespec *timestamp,
 347                                             uint32_t flags);
 348 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                             struct timespec *timestamp);
 350 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 351 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 352                                    struct timespec *timestamp);
 353 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 354                                    const struct timespec *timestamp);
 355
 356 static int ixgbe_dev_l2_tunnel_eth_type_conf
 357         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 358 static int ixgbe_dev_l2_tunnel_offload_set
 359         (struct rte_eth_dev *dev,
 360          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 361          uint32_t mask,
 362          uint8_t en);
 363 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 364                                              enum rte_filter_op filter_op,
 365                                              void *arg);
 366
 367 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 368                                          struct rte_eth_udp_tunnel *udp_tunnel);
 369 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 370                                          struct rte_eth_udp_tunnel *udp_tunnel);
 371
 372 /*
 373  * Define VF Stats MACRO for Non "cleared on read" register
 374  */
 375 #define UPDATE_VF_STAT(reg, last, cur)                          \
 376 {                                                               \
 377         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 378         cur += (latest - last) & UINT_MAX;                      \
 379         last = latest;                                          \
 380 }
 381
 382 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 383 {                                                                \
 384         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 385         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 386         u64 latest = ((new_msb << 32) | new_lsb);                \
 387         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 388         last = latest;                                           \
 389 }
 390
 391 #define IXGBE_SET_HWSTRIP(h, q) do{\
 392                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 393                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 394                 (h)->bitmap[idx] |= 1 << bit;\
 395         } while (0)
 396
 397 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 398                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 399                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 400                 (h)->bitmap[idx] &= ~(1 << bit);\
 401         } while (0)
 402
 403 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 404                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 406                 (r) = (h)->bitmap[idx] >> bit & 1;\
 407         } while (0)
 408
 409 /*
 410  * The set of PCI devices this driver supports
 411  */
 412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 413
 414 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 415 #include "rte_pci_dev_ids.h"
 416
 417 { .vendor_id = 0, /* sentinel */ },
 418 };
 419
 420
 421 /*
 422  * The set of PCI devices this driver supports (for 82599 VF)
 423  */
 424 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 425
 426 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 427 #include "rte_pci_dev_ids.h"
 428 { .vendor_id = 0, /* sentinel */ },
 429
 430 };
 431
 432 static const struct rte_eth_desc_lim rx_desc_lim = {
 433         .nb_max = IXGBE_MAX_RING_DESC,
 434         .nb_min = IXGBE_MIN_RING_DESC,
 435         .nb_align = IXGBE_RXD_ALIGN,
 436 };
 437
 438 static const struct rte_eth_desc_lim tx_desc_lim = {
 439         .nb_max = IXGBE_MAX_RING_DESC,
 440         .nb_min = IXGBE_MIN_RING_DESC,
 441         .nb_align = IXGBE_TXD_ALIGN,
 442 };
 443
 444 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 445         .dev_configure        = ixgbe_dev_configure,
 446         .dev_start            = ixgbe_dev_start,
 447         .dev_stop             = ixgbe_dev_stop,
 448         .dev_set_link_up    = ixgbe_dev_set_link_up,
 449         .dev_set_link_down  = ixgbe_dev_set_link_down,
 450         .dev_close            = ixgbe_dev_close,
 451         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 452         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 453         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 454         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 455         .link_update          = ixgbe_dev_link_update,
 456         .stats_get            = ixgbe_dev_stats_get,
 457         .xstats_get           = ixgbe_dev_xstats_get,
 458         .stats_reset          = ixgbe_dev_stats_reset,
 459         .xstats_reset         = ixgbe_dev_xstats_reset,
 460         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 461         .dev_infos_get        = ixgbe_dev_info_get,
 462         .mtu_set              = ixgbe_dev_mtu_set,
 463         .vlan_filter_set      = ixgbe_vlan_filter_set,
 464         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 465         .vlan_offload_set     = ixgbe_vlan_offload_set,
 466         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 467         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 468         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 469         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 470         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 471         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 472         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 474         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 475         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 476         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 477         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 478         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 479         .dev_led_on           = ixgbe_dev_led_on,
 480         .dev_led_off          = ixgbe_dev_led_off,
 481         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 482         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 483         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 484         .mac_addr_add         = ixgbe_add_rar,
 485         .mac_addr_remove      = ixgbe_remove_rar,
 486         .mac_addr_set         = ixgbe_set_default_mac_addr,
 487         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 488         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 489         .mirror_rule_set      = ixgbe_mirror_rule_set,
 490         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 491         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 492         .set_vf_rx            = ixgbe_set_pool_rx,
 493         .set_vf_tx            = ixgbe_set_pool_tx,
 494         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 495         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 496         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 497         .reta_update          = ixgbe_dev_rss_reta_update,
 498         .reta_query           = ixgbe_dev_rss_reta_query,
 499 #ifdef RTE_NIC_BYPASS
 500         .bypass_init          = ixgbe_bypass_init,
 501         .bypass_state_set     = ixgbe_bypass_state_store,
 502         .bypass_state_show    = ixgbe_bypass_state_show,
 503         .bypass_event_set     = ixgbe_bypass_event_store,
 504         .bypass_event_show    = ixgbe_bypass_event_show,
 505         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 506         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 507         .bypass_ver_show      = ixgbe_bypass_ver_show,
 508         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 509 #endif /* RTE_NIC_BYPASS */
 510         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 511         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 512         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 513         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 514         .rxq_info_get         = ixgbe_rxq_info_get,
 515         .txq_info_get         = ixgbe_txq_info_get,
 516         .timesync_enable      = ixgbe_timesync_enable,
 517         .timesync_disable     = ixgbe_timesync_disable,
 518         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 519         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 520         .get_reg_length       = ixgbe_get_reg_length,
 521         .get_reg              = ixgbe_get_regs,
 522         .get_eeprom_length    = ixgbe_get_eeprom_length,
 523         .get_eeprom           = ixgbe_get_eeprom,
 524         .set_eeprom           = ixgbe_set_eeprom,
 525         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 526         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 527         .timesync_read_time   = ixgbe_timesync_read_time,
 528         .timesync_write_time  = ixgbe_timesync_write_time,
 529         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 530         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 531         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 532         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 533 };
 534
 535 /*
 536  * dev_ops for virtual function, bare necessities for basic vf
 537  * operation have been implemented
 538  */
 539 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 540         .dev_configure        = ixgbevf_dev_configure,
 541         .dev_start            = ixgbevf_dev_start,
 542         .dev_stop             = ixgbevf_dev_stop,
 543         .link_update          = ixgbe_dev_link_update,
 544         .stats_get            = ixgbevf_dev_stats_get,
 545         .xstats_get           = ixgbevf_dev_xstats_get,
 546         .stats_reset          = ixgbevf_dev_stats_reset,
 547         .xstats_reset         = ixgbevf_dev_stats_reset,
 548         .dev_close            = ixgbevf_dev_close,
 549         .dev_infos_get        = ixgbevf_dev_info_get,
 550         .mtu_set              = ixgbevf_dev_set_mtu,
 551         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 552         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 553         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 554         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 555         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 556         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 557         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 558         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 559         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 560         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 561         .mac_addr_add         = ixgbevf_add_mac_addr,
 562         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 563         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 564         .rxq_info_get         = ixgbe_rxq_info_get,
 565         .txq_info_get         = ixgbe_txq_info_get,
 566         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 567         .get_reg_length       = ixgbevf_get_reg_length,
 568         .get_reg              = ixgbevf_get_regs,
 569         .reta_update          = ixgbe_dev_rss_reta_update,
 570         .reta_query           = ixgbe_dev_rss_reta_query,
 571         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 572         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 573 };
 574
 575 /* store statistics names and its offset in stats structure */
 576 struct rte_ixgbe_xstats_name_off {
 577         char name[RTE_ETH_XSTATS_NAME_SIZE];
 578         unsigned offset;
 579 };
 580
 581 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 582         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 583         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 584         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 585         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 586         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 587         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 588         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 589         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 590         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 591         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 592         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 593         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 594         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 595         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 596         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 597                 prc1023)},
 598         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 599                 prc1522)},
 600         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 601         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 602         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 603         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 604         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 605         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 606         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 607         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 608         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 609         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 610         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 611         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 612         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 613         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 614         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 615         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 616         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 617                 ptc1023)},
 618         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 619                 ptc1522)},
 620         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 621         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 622         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 623         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 624
 625         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 626                 fdirustat_add)},
 627         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 628                 fdirustat_remove)},
 629         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 630                 fdirfstat_fadd)},
 631         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 632                 fdirfstat_fremove)},
 633         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 634                 fdirmatch)},
 635         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 636                 fdirmiss)},
 637
 638         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 639         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 640         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 641                 fclast)},
 642         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 643         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 644         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 645         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 646         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 647                 fcoe_noddp)},
 648         {"rx_fcoe_no_direct_data_placement_ext_buff",
 649                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 650
 651         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 652                 lxontxc)},
 653         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 654                 lxonrxc)},
 655         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 656                 lxofftxc)},
 657         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 658                 lxoffrxc)},
 659         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 660 };
 661
 662 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 663                            sizeof(rte_ixgbe_stats_strings[0]))
 664
 665 /* Per-queue statistics */
 666 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 667         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 668         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 669         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 670         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 671 };
 672
 673 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 674                            sizeof(rte_ixgbe_rxq_strings[0]))
 675
 676 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 677         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 678         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 679         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 680                 pxon2offc)},
 681 };
 682
 683 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 684                            sizeof(rte_ixgbe_txq_strings[0]))
 685
 686 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 687         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 688 };
 689
 690 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 691                 sizeof(rte_ixgbevf_stats_strings[0]))
 692
 693 /**
 694  * Atomically reads the link status information from global
 695  * structure rte_eth_dev.
 696  *
 697  * @param dev
 698  *   - Pointer to the structure rte_eth_dev to read from.
 699  *   - Pointer to the buffer to be saved with the link status.
 700  *
 701  * @return
 702  *   - On success, zero.
 703  *   - On failure, negative value.
 704  */
 705 static inline int
 706 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 707                                 struct rte_eth_link *link)
 708 {
 709         struct rte_eth_link *dst = link;
 710         struct rte_eth_link *src = &(dev->data->dev_link);
 711
 712         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 713                                         *(uint64_t *)src) == 0)
 714                 return -1;
 715
 716         return 0;
 717 }
 718
 719 /**
 720  * Atomically writes the link status information into global
 721  * structure rte_eth_dev.
 722  *
 723  * @param dev
 724  *   - Pointer to the structure rte_eth_dev to read from.
 725  *   - Pointer to the buffer to be saved with the link status.
 726  *
 727  * @return
 728  *   - On success, zero.
 729  *   - On failure, negative value.
 730  */
 731 static inline int
 732 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 733                                 struct rte_eth_link *link)
 734 {
 735         struct rte_eth_link *dst = &(dev->data->dev_link);
 736         struct rte_eth_link *src = link;
 737
 738         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 739                                         *(uint64_t *)src) == 0)
 740                 return -1;
 741
 742         return 0;
 743 }
 744
 745 /*
 746  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 747  */
 748 static inline int
 749 ixgbe_is_sfp(struct ixgbe_hw *hw)
 750 {
 751         switch (hw->phy.type) {
 752         case ixgbe_phy_sfp_avago:
 753         case ixgbe_phy_sfp_ftl:
 754         case ixgbe_phy_sfp_intel:
 755         case ixgbe_phy_sfp_unknown:
 756         case ixgbe_phy_sfp_passive_tyco:
 757         case ixgbe_phy_sfp_passive_unknown:
 758                 return 1;
 759         default:
 760                 return 0;
 761         }
 762 }
 763
 764 static inline int32_t
 765 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 766 {
 767         uint32_t ctrl_ext;
 768         int32_t status;
 769
 770         status = ixgbe_reset_hw(hw);
 771
 772         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 773         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 774         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 775         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 776         IXGBE_WRITE_FLUSH(hw);
 777
 778         return status;
 779 }
 780
 781 static inline void
 782 ixgbe_enable_intr(struct rte_eth_dev *dev)
 783 {
 784         struct ixgbe_interrupt *intr =
 785                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 786         struct ixgbe_hw *hw =
 787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 788
 789         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 790         IXGBE_WRITE_FLUSH(hw);
 791 }
 792
 793 /*
 794  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 795  */
 796 static void
 797 ixgbe_disable_intr(struct ixgbe_hw *hw)
 798 {
 799         PMD_INIT_FUNC_TRACE();
 800
 801         if (hw->mac.type == ixgbe_mac_82598EB) {
 802                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 803         } else {
 804                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 805                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 806                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 807         }
 808         IXGBE_WRITE_FLUSH(hw);
 809 }
 810
 811 /*
 812  * This function resets queue statistics mapping registers.
 813  * From Niantic datasheet, Initialization of Statistics section:
 814  * "...if software requires the queue counters, the RQSMR and TQSM registers
 815  * must be re-programmed following a device reset.
 816  */
 817 static void
 818 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 819 {
 820         uint32_t i;
 821
 822         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 823                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 824                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 825         }
 826 }
 827
 828
 829 static int
 830 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 831                                   uint16_t queue_id,
 832                                   uint8_t stat_idx,
 833                                   uint8_t is_rx)
 834 {
 835 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 836 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 837 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 838
 839         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 840         struct ixgbe_stat_mapping_registers *stat_mappings =
 841                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 842         uint32_t qsmr_mask = 0;
 843         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 844         uint32_t q_map;
 845         uint8_t n, offset;
 846
 847         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 848                 (hw->mac.type != ixgbe_mac_X540) &&
 849                 (hw->mac.type != ixgbe_mac_X550) &&
 850                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 851                 (hw->mac.type != ixgbe_mac_X550EM_a))
 852                 return -ENOSYS;
 853
 854         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 855                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 856                      queue_id, stat_idx);
 857
 858         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 859         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 860                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 861                 return -EIO;
 862         }
 863         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 864
 865         /* Now clear any previous stat_idx set */
 866         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 867         if (!is_rx)
 868                 stat_mappings->tqsm[n] &= ~clearing_mask;
 869         else
 870                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 871
 872         q_map = (uint32_t)stat_idx;
 873         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 874         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 875         if (!is_rx)
 876                 stat_mappings->tqsm[n] |= qsmr_mask;
 877         else
 878                 stat_mappings->rqsmr[n] |= qsmr_mask;
 879
 880         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 881                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 882                      queue_id, stat_idx);
 883         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 884                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 885
 886         /* Now write the mapping in the appropriate register */
 887         if (is_rx) {
 888                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 889                              stat_mappings->rqsmr[n], n);
 890                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 891         }
 892         else {
 893                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 894                              stat_mappings->tqsm[n], n);
 895                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 896         }
 897         return 0;
 898 }
 899
 900 static void
 901 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 902 {
 903         struct ixgbe_stat_mapping_registers *stat_mappings =
 904                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 906         int i;
 907
 908         /* write whatever was in stat mapping table to the NIC */
 909         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 910                 /* rx */
 911                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 912
 913                 /* tx */
 914                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 915         }
 916 }
 917
 918 static void
 919 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 920 {
 921         uint8_t i;
 922         struct ixgbe_dcb_tc_config *tc;
 923         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 924
 925         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 926         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 927         for (i = 0; i < dcb_max_tc; i++) {
 928                 tc = &dcb_config->tc_config[i];
 929                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 930                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 931                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 932                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 933                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 934                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 935                 tc->pfc = ixgbe_dcb_pfc_disabled;
 936         }
 937
 938         /* Initialize default user to priority mapping, UPx->TC0 */
 939         tc = &dcb_config->tc_config[0];
 940         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 941         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 942         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 943                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 944                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 945         }
 946         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 947         dcb_config->pfc_mode_enable = false;
 948         dcb_config->vt_mode = true;
 949         dcb_config->round_robin_enable = false;
 950         /* support all DCB capabilities in 82599 */
 951         dcb_config->support.capabilities = 0xFF;
 952
 953         /*we only support 4 Tcs for X540, X550 */
 954         if (hw->mac.type == ixgbe_mac_X540 ||
 955                 hw->mac.type == ixgbe_mac_X550 ||
 956                 hw->mac.type == ixgbe_mac_X550EM_x ||
 957                 hw->mac.type == ixgbe_mac_X550EM_a) {
 958                 dcb_config->num_tcs.pg_tcs = 4;
 959                 dcb_config->num_tcs.pfc_tcs = 4;
 960         }
 961 }
 962
 963 /*
 964  * Ensure that all locks are released before first NVM or PHY access
 965  */
 966 static void
 967 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 968 {
 969         uint16_t mask;
 970
 971         /*
 972          * Phy lock should not fail in this early stage. If this is the case,
 973          * it is due to an improper exit of the application.
 974          * So force the release of the faulty lock. Release of common lock
 975          * is done automatically by swfw_sync function.
 976          */
 977         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 978         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 979                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 980         }
 981         ixgbe_release_swfw_semaphore(hw, mask);
 982
 983         /*
 984          * These ones are more tricky since they are common to all ports; but
 985          * swfw_sync retries last long enough (1s) to be almost sure that if
 986          * lock can not be taken it is due to an improper lock of the
 987          * semaphore.
 988          */
 989         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 990         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 991                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 992         }
 993         ixgbe_release_swfw_semaphore(hw, mask);
 994 }
 995
 996 /*
 997  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 998  * It returns 0 on success.
 999  */
1000 static int
1001 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1002 {
1003         struct rte_pci_device *pci_dev;
1004         struct ixgbe_hw *hw =
1005                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1006         struct ixgbe_vfta * shadow_vfta =
1007                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1008         struct ixgbe_hwstrip *hwstrip =
1009                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1010         struct ixgbe_dcb_config *dcb_config =
1011                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1012         struct ixgbe_filter_info *filter_info =
1013                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1014         uint32_t ctrl_ext;
1015         uint16_t csum;
1016         int diag, i;
1017
1018         PMD_INIT_FUNC_TRACE();
1019
1020         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1021         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1022         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1023
1024         /*
1025          * For secondary processes, we don't initialise any further as primary
1026          * has already done this work. Only check we don't need a different
1027          * RX and TX function.
1028          */
1029         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1030                 struct ixgbe_tx_queue *txq;
1031                 /* TX queue function in primary, set by last queue initialized
1032                  * Tx queue may not initialized by primary process */
1033                 if (eth_dev->data->tx_queues) {
1034                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1035                         ixgbe_set_tx_function(eth_dev, txq);
1036                 } else {
1037                         /* Use default TX function if we get here */
1038                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1039                                              "Using default TX function.");
1040                 }
1041
1042                 ixgbe_set_rx_function(eth_dev);
1043
1044                 return 0;
1045         }
1046         pci_dev = eth_dev->pci_dev;
1047
1048         rte_eth_copy_pci_info(eth_dev, pci_dev);
1049
1050         /* Vendor and Device ID need to be set before init of shared code */
1051         hw->device_id = pci_dev->id.device_id;
1052         hw->vendor_id = pci_dev->id.vendor_id;
1053         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1054         hw->allow_unsupported_sfp = 1;
1055
1056         /* Initialize the shared code (base driver) */
1057 #ifdef RTE_NIC_BYPASS
1058         diag = ixgbe_bypass_init_shared_code(hw);
1059 #else
1060         diag = ixgbe_init_shared_code(hw);
1061 #endif /* RTE_NIC_BYPASS */
1062
1063         if (diag != IXGBE_SUCCESS) {
1064                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1065                 return -EIO;
1066         }
1067
1068         /* pick up the PCI bus settings for reporting later */
1069         ixgbe_get_bus_info(hw);
1070
1071         /* Unlock any pending hardware semaphore */
1072         ixgbe_swfw_lock_reset(hw);
1073
1074         /* Initialize DCB configuration*/
1075         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1076         ixgbe_dcb_init(hw,dcb_config);
1077         /* Get Hardware Flow Control setting */
1078         hw->fc.requested_mode = ixgbe_fc_full;
1079         hw->fc.current_mode = ixgbe_fc_full;
1080         hw->fc.pause_time = IXGBE_FC_PAUSE;
1081         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1082                 hw->fc.low_water[i] = IXGBE_FC_LO;
1083                 hw->fc.high_water[i] = IXGBE_FC_HI;
1084         }
1085         hw->fc.send_xon = 1;
1086
1087         /* Make sure we have a good EEPROM before we read from it */
1088         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1089         if (diag != IXGBE_SUCCESS) {
1090                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1091                 return -EIO;
1092         }
1093
1094 #ifdef RTE_NIC_BYPASS
1095         diag = ixgbe_bypass_init_hw(hw);
1096 #else
1097         diag = ixgbe_init_hw(hw);
1098 #endif /* RTE_NIC_BYPASS */
1099
1100         /*
1101          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1102          * is called too soon after the kernel driver unbinding/binding occurs.
1103          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1104          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1105          * also called. See ixgbe_identify_phy_82599(). The reason for the
1106          * failure is not known, and only occuts when virtualisation features
1107          * are disabled in the bios. A delay of 100ms  was found to be enough by
1108          * trial-and-error, and is doubled to be safe.
1109          */
1110         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1111                 rte_delay_ms(200);
1112                 diag = ixgbe_init_hw(hw);
1113         }
1114
1115         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1116                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1117                     "LOM.  Please be aware there may be issues associated "
1118                     "with your hardware.");
1119                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1120                     "please contact your Intel or hardware representative "
1121                     "who provided you with this hardware.");
1122         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1123                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1124         if (diag) {
1125                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1126                 return -EIO;
1127         }
1128
1129         /* Reset the hw statistics */
1130         ixgbe_dev_stats_reset(eth_dev);
1131
1132         /* disable interrupt */
1133         ixgbe_disable_intr(hw);
1134
1135         /* reset mappings for queue statistics hw counters*/
1136         ixgbe_reset_qstat_mappings(hw);
1137
1138         /* Allocate memory for storing MAC addresses */
1139         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1140                         hw->mac.num_rar_entries, 0);
1141         if (eth_dev->data->mac_addrs == NULL) {
1142                 PMD_INIT_LOG(ERR,
1143                         "Failed to allocate %u bytes needed to store "
1144                         "MAC addresses",
1145                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1146                 return -ENOMEM;
1147         }
1148         /* Copy the permanent MAC address */
1149         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1150                         &eth_dev->data->mac_addrs[0]);
1151
1152         /* Allocate memory for storing hash filter MAC addresses */
1153         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1154                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1155         if (eth_dev->data->hash_mac_addrs == NULL) {
1156                 PMD_INIT_LOG(ERR,
1157                         "Failed to allocate %d bytes needed to store MAC addresses",
1158                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1159                 return -ENOMEM;
1160         }
1161
1162         /* initialize the vfta */
1163         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1164
1165         /* initialize the hw strip bitmap*/
1166         memset(hwstrip, 0, sizeof(*hwstrip));
1167
1168         /* initialize PF if max_vfs not zero */
1169         ixgbe_pf_host_init(eth_dev);
1170
1171         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1172         /* let hardware know driver is loaded */
1173         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1174         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1175         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1176         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1177         IXGBE_WRITE_FLUSH(hw);
1178
1179         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1180                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1181                              (int) hw->mac.type, (int) hw->phy.type,
1182                              (int) hw->phy.sfp_type);
1183         else
1184                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1185                              (int) hw->mac.type, (int) hw->phy.type);
1186
1187         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1188                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1189                         pci_dev->id.device_id);
1190
1191         rte_intr_callback_register(&pci_dev->intr_handle,
1192                                    ixgbe_dev_interrupt_handler,
1193                                    (void *)eth_dev);
1194
1195         /* enable uio/vfio intr/eventfd mapping */
1196         rte_intr_enable(&pci_dev->intr_handle);
1197
1198         /* enable support intr */
1199         ixgbe_enable_intr(eth_dev);
1200
1201         /* initialize 5tuple filter list */
1202         TAILQ_INIT(&filter_info->fivetuple_list);
1203         memset(filter_info->fivetuple_mask, 0,
1204                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1205
1206         return 0;
1207 }
1208
1209 static int
1210 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1211 {
1212         struct rte_pci_device *pci_dev;
1213         struct ixgbe_hw *hw;
1214
1215         PMD_INIT_FUNC_TRACE();
1216
1217         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1218                 return -EPERM;
1219
1220         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1221         pci_dev = eth_dev->pci_dev;
1222
1223         if (hw->adapter_stopped == 0)
1224                 ixgbe_dev_close(eth_dev);
1225
1226         eth_dev->dev_ops = NULL;
1227         eth_dev->rx_pkt_burst = NULL;
1228         eth_dev->tx_pkt_burst = NULL;
1229
1230         /* Unlock any pending hardware semaphore */
1231         ixgbe_swfw_lock_reset(hw);
1232
1233         /* disable uio intr before callback unregister */
1234         rte_intr_disable(&(pci_dev->intr_handle));
1235         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1236                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1237
1238         /* uninitialize PF if max_vfs not zero */
1239         ixgbe_pf_host_uninit(eth_dev);
1240
1241         rte_free(eth_dev->data->mac_addrs);
1242         eth_dev->data->mac_addrs = NULL;
1243
1244         rte_free(eth_dev->data->hash_mac_addrs);
1245         eth_dev->data->hash_mac_addrs = NULL;
1246
1247         return 0;
1248 }
1249
1250 /*
1251  * Negotiate mailbox API version with the PF.
1252  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1253  * Then we try to negotiate starting with the most recent one.
1254  * If all negotiation attempts fail, then we will proceed with
1255  * the default one (ixgbe_mbox_api_10).
1256  */
1257 static void
1258 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1259 {
1260         int32_t i;
1261
1262         /* start with highest supported, proceed down */
1263         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1264                 ixgbe_mbox_api_11,
1265                 ixgbe_mbox_api_10,
1266         };
1267
1268         for (i = 0;
1269                         i != RTE_DIM(sup_ver) &&
1270                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1271                         i++)
1272                 ;
1273 }
1274
1275 static void
1276 generate_random_mac_addr(struct ether_addr *mac_addr)
1277 {
1278         uint64_t random;
1279
1280         /* Set Organizationally Unique Identifier (OUI) prefix. */
1281         mac_addr->addr_bytes[0] = 0x00;
1282         mac_addr->addr_bytes[1] = 0x09;
1283         mac_addr->addr_bytes[2] = 0xC0;
1284         /* Force indication of locally assigned MAC address. */
1285         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1286         /* Generate the last 3 bytes of the MAC address with a random number. */
1287         random = rte_rand();
1288         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1289 }
1290
1291 /*
1292  * Virtual Function device init
1293  */
1294 static int
1295 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1296 {
1297         int diag;
1298         uint32_t tc, tcs;
1299         struct rte_pci_device *pci_dev;
1300         struct ixgbe_hw *hw =
1301                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1302         struct ixgbe_vfta * shadow_vfta =
1303                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1304         struct ixgbe_hwstrip *hwstrip =
1305                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1306         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1307
1308         PMD_INIT_FUNC_TRACE();
1309
1310         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1311         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1312         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1313
1314         /* for secondary processes, we don't initialise any further as primary
1315          * has already done this work. Only check we don't need a different
1316          * RX function */
1317         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1318                 if (eth_dev->data->scattered_rx)
1319                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1320                 return 0;
1321         }
1322
1323         pci_dev = eth_dev->pci_dev;
1324
1325         rte_eth_copy_pci_info(eth_dev, pci_dev);
1326
1327         hw->device_id = pci_dev->id.device_id;
1328         hw->vendor_id = pci_dev->id.vendor_id;
1329         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1330
1331         /* initialize the vfta */
1332         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1333
1334         /* initialize the hw strip bitmap*/
1335         memset(hwstrip, 0, sizeof(*hwstrip));
1336
1337         /* Initialize the shared code (base driver) */
1338         diag = ixgbe_init_shared_code(hw);
1339         if (diag != IXGBE_SUCCESS) {
1340                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1341                 return -EIO;
1342         }
1343
1344         /* init_mailbox_params */
1345         hw->mbx.ops.init_params(hw);
1346
1347         /* Reset the hw statistics */
1348         ixgbevf_dev_stats_reset(eth_dev);
1349
1350         /* Disable the interrupts for VF */
1351         ixgbevf_intr_disable(hw);
1352
1353         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1354         diag = hw->mac.ops.reset_hw(hw);
1355
1356         /*
1357          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1358          * the underlying PF driver has not assigned a MAC address to the VF.
1359          * In this case, assign a random MAC address.
1360          */
1361         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1362                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1363                 return diag;
1364         }
1365
1366         /* negotiate mailbox API version to use with the PF. */
1367         ixgbevf_negotiate_api(hw);
1368
1369         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1370         ixgbevf_get_queues(hw, &tcs, &tc);
1371
1372         /* Allocate memory for storing MAC addresses */
1373         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1374                         hw->mac.num_rar_entries, 0);
1375         if (eth_dev->data->mac_addrs == NULL) {
1376                 PMD_INIT_LOG(ERR,
1377                         "Failed to allocate %u bytes needed to store "
1378                         "MAC addresses",
1379                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1380                 return -ENOMEM;
1381         }
1382
1383         /* Generate a random MAC address, if none was assigned by PF. */
1384         if (is_zero_ether_addr(perm_addr)) {
1385                 generate_random_mac_addr(perm_addr);
1386                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1387                 if (diag) {
1388                         rte_free(eth_dev->data->mac_addrs);
1389                         eth_dev->data->mac_addrs = NULL;
1390                         return diag;
1391                 }
1392                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1393                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1394                              "%02x:%02x:%02x:%02x:%02x:%02x",
1395                              perm_addr->addr_bytes[0],
1396                              perm_addr->addr_bytes[1],
1397                              perm_addr->addr_bytes[2],
1398                              perm_addr->addr_bytes[3],
1399                              perm_addr->addr_bytes[4],
1400                              perm_addr->addr_bytes[5]);
1401         }
1402
1403         /* Copy the permanent MAC address */
1404         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1405
1406         /* reset the hardware with the new settings */
1407         diag = hw->mac.ops.start_hw(hw);
1408         switch (diag) {
1409                 case  0:
1410                         break;
1411
1412                 default:
1413                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1414                         return -EIO;
1415         }
1416
1417         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1418                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1419                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1420
1421         return 0;
1422 }
1423
1424 /* Virtual Function device uninit */
1425
1426 static int
1427 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1428 {
1429         struct ixgbe_hw *hw;
1430         unsigned i;
1431
1432         PMD_INIT_FUNC_TRACE();
1433
1434         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1435                 return -EPERM;
1436
1437         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1438
1439         if (hw->adapter_stopped == 0)
1440                 ixgbevf_dev_close(eth_dev);
1441
1442         eth_dev->dev_ops = NULL;
1443         eth_dev->rx_pkt_burst = NULL;
1444         eth_dev->tx_pkt_burst = NULL;
1445
1446         /* Disable the interrupts for VF */
1447         ixgbevf_intr_disable(hw);
1448
1449         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1450                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1451                 eth_dev->data->rx_queues[i] = NULL;
1452         }
1453         eth_dev->data->nb_rx_queues = 0;
1454
1455         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1456                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1457                 eth_dev->data->tx_queues[i] = NULL;
1458         }
1459         eth_dev->data->nb_tx_queues = 0;
1460
1461         rte_free(eth_dev->data->mac_addrs);
1462         eth_dev->data->mac_addrs = NULL;
1463
1464         return 0;
1465 }
1466
1467 static struct eth_driver rte_ixgbe_pmd = {
1468         .pci_drv = {
1469                 .name = "rte_ixgbe_pmd",
1470                 .id_table = pci_id_ixgbe_map,
1471                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1472                         RTE_PCI_DRV_DETACHABLE,
1473         },
1474         .eth_dev_init = eth_ixgbe_dev_init,
1475         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1476         .dev_private_size = sizeof(struct ixgbe_adapter),
1477 };
1478
1479 /*
1480  * virtual function driver struct
1481  */
1482 static struct eth_driver rte_ixgbevf_pmd = {
1483         .pci_drv = {
1484                 .name = "rte_ixgbevf_pmd",
1485                 .id_table = pci_id_ixgbevf_map,
1486                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1487         },
1488         .eth_dev_init = eth_ixgbevf_dev_init,
1489         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1490         .dev_private_size = sizeof(struct ixgbe_adapter),
1491 };
1492
1493 /*
1494  * Driver initialization routine.
1495  * Invoked once at EAL init time.
1496  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1497  */
1498 static int
1499 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1500 {
1501         PMD_INIT_FUNC_TRACE();
1502
1503         rte_eth_driver_register(&rte_ixgbe_pmd);
1504         return 0;
1505 }
1506
1507 /*
1508  * VF Driver initialization routine.
1509  * Invoked one at EAL init time.
1510  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1511  */
1512 static int
1513 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1514 {
1515         PMD_INIT_FUNC_TRACE();
1516
1517         rte_eth_driver_register(&rte_ixgbevf_pmd);
1518         return 0;
1519 }
1520
1521 static int
1522 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1523 {
1524         struct ixgbe_hw *hw =
1525                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1526         struct ixgbe_vfta * shadow_vfta =
1527                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1528         uint32_t vfta;
1529         uint32_t vid_idx;
1530         uint32_t vid_bit;
1531
1532         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1533         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1534         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1535         if (on)
1536                 vfta |= vid_bit;
1537         else
1538                 vfta &= ~vid_bit;
1539         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1540
1541         /* update local VFTA copy */
1542         shadow_vfta->vfta[vid_idx] = vfta;
1543
1544         return 0;
1545 }
1546
1547 static void
1548 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1549 {
1550         if (on)
1551                 ixgbe_vlan_hw_strip_enable(dev, queue);
1552         else
1553                 ixgbe_vlan_hw_strip_disable(dev, queue);
1554 }
1555
1556 static int
1557 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1558                     enum rte_vlan_type vlan_type,
1559                     uint16_t tpid)
1560 {
1561         struct ixgbe_hw *hw =
1562                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1563         int ret = 0;
1564
1565         switch (vlan_type) {
1566         case ETH_VLAN_TYPE_INNER:
1567                 /* Only the high 16-bits is valid */
1568                 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1569                 break;
1570         default:
1571                 ret = -EINVAL;
1572                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d\n", vlan_type);
1573                 break;
1574         }
1575
1576         return ret;
1577 }
1578
1579 void
1580 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1581 {
1582         struct ixgbe_hw *hw =
1583                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584         uint32_t vlnctrl;
1585
1586         PMD_INIT_FUNC_TRACE();
1587
1588         /* Filter Table Disable */
1589         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1590         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1591
1592         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1593 }
1594
1595 void
1596 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1597 {
1598         struct ixgbe_hw *hw =
1599                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600         struct ixgbe_vfta * shadow_vfta =
1601                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1602         uint32_t vlnctrl;
1603         uint16_t i;
1604
1605         PMD_INIT_FUNC_TRACE();
1606
1607         /* Filter Table Enable */
1608         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1609         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1610         vlnctrl |= IXGBE_VLNCTRL_VFE;
1611
1612         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1613
1614         /* write whatever is in local vfta copy */
1615         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1616                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1617 }
1618
1619 static void
1620 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1621 {
1622         struct ixgbe_hwstrip *hwstrip =
1623                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1624
1625         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1626                 return;
1627
1628         if (on)
1629                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1630         else
1631                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1632 }
1633
1634 static void
1635 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1636 {
1637         struct ixgbe_hw *hw =
1638                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1639         uint32_t ctrl;
1640
1641         PMD_INIT_FUNC_TRACE();
1642
1643         if (hw->mac.type == ixgbe_mac_82598EB) {
1644                 /* No queue level support */
1645                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1646                 return;
1647         }
1648         else {
1649                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1650                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1651                 ctrl &= ~IXGBE_RXDCTL_VME;
1652                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1653         }
1654         /* record those setting for HW strip per queue */
1655         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1656 }
1657
1658 static void
1659 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1660 {
1661         struct ixgbe_hw *hw =
1662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1663         uint32_t ctrl;
1664
1665         PMD_INIT_FUNC_TRACE();
1666
1667         if (hw->mac.type == ixgbe_mac_82598EB) {
1668                 /* No queue level supported */
1669                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1670                 return;
1671         }
1672         else {
1673                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1674                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1675                 ctrl |= IXGBE_RXDCTL_VME;
1676                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1677         }
1678         /* record those setting for HW strip per queue */
1679         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1680 }
1681
1682 void
1683 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1684 {
1685         struct ixgbe_hw *hw =
1686                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         uint32_t ctrl;
1688         uint16_t i;
1689
1690         PMD_INIT_FUNC_TRACE();
1691
1692         if (hw->mac.type == ixgbe_mac_82598EB) {
1693                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1694                 ctrl &= ~IXGBE_VLNCTRL_VME;
1695                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1696         }
1697         else {
1698                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1699                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1700                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1701                         ctrl &= ~IXGBE_RXDCTL_VME;
1702                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1703
1704                         /* record those setting for HW strip per queue */
1705                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1706                 }
1707         }
1708 }
1709
1710 void
1711 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1712 {
1713         struct ixgbe_hw *hw =
1714                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715         uint32_t ctrl;
1716         uint16_t i;
1717
1718         PMD_INIT_FUNC_TRACE();
1719
1720         if (hw->mac.type == ixgbe_mac_82598EB) {
1721                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1722                 ctrl |= IXGBE_VLNCTRL_VME;
1723                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1724         }
1725         else {
1726                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1727                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1728                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1729                         ctrl |= IXGBE_RXDCTL_VME;
1730                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1731
1732                         /* record those setting for HW strip per queue */
1733                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1734                 }
1735         }
1736 }
1737
1738 static void
1739 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1740 {
1741         struct ixgbe_hw *hw =
1742                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1743         uint32_t ctrl;
1744
1745         PMD_INIT_FUNC_TRACE();
1746
1747         /* DMATXCTRL: Geric Double VLAN Disable */
1748         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1749         ctrl &= ~IXGBE_DMATXCTL_GDV;
1750         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1751
1752         /* CTRL_EXT: Global Double VLAN Disable */
1753         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1754         ctrl &= ~IXGBE_EXTENDED_VLAN;
1755         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1756
1757 }
1758
1759 static void
1760 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1761 {
1762         struct ixgbe_hw *hw =
1763                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764         uint32_t ctrl;
1765
1766         PMD_INIT_FUNC_TRACE();
1767
1768         /* DMATXCTRL: Geric Double VLAN Enable */
1769         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1770         ctrl |= IXGBE_DMATXCTL_GDV;
1771         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1772
1773         /* CTRL_EXT: Global Double VLAN Enable */
1774         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1775         ctrl |= IXGBE_EXTENDED_VLAN;
1776         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1777
1778         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1779         if (hw->mac.type == ixgbe_mac_X550 ||
1780             hw->mac.type == ixgbe_mac_X550EM_x) {
1781                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1782                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1783                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1784         }
1785
1786         /*
1787          * VET EXT field in the EXVET register = 0x8100 by default
1788          * So no need to change. Same to VT field of DMATXCTL register
1789          */
1790 }
1791
1792 static void
1793 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1794 {
1795         if (mask & ETH_VLAN_STRIP_MASK) {
1796                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1797                         ixgbe_vlan_hw_strip_enable_all(dev);
1798                 else
1799                         ixgbe_vlan_hw_strip_disable_all(dev);
1800         }
1801
1802         if (mask & ETH_VLAN_FILTER_MASK) {
1803                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1804                         ixgbe_vlan_hw_filter_enable(dev);
1805                 else
1806                         ixgbe_vlan_hw_filter_disable(dev);
1807         }
1808
1809         if (mask & ETH_VLAN_EXTEND_MASK) {
1810                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1811                         ixgbe_vlan_hw_extend_enable(dev);
1812                 else
1813                         ixgbe_vlan_hw_extend_disable(dev);
1814         }
1815 }
1816
1817 static void
1818 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1819 {
1820         struct ixgbe_hw *hw =
1821                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1822         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1823         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1824         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1825         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1826 }
1827
1828 static int
1829 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1830 {
1831         switch (nb_rx_q) {
1832         case 1:
1833         case 2:
1834                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1835                 break;
1836         case 4:
1837                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1838                 break;
1839         default:
1840                 return -EINVAL;
1841         }
1842
1843         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1844         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1845
1846         return 0;
1847 }
1848
1849 static int
1850 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1851 {
1852         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1853         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1854         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1855
1856         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1857                 /* check multi-queue mode */
1858                 switch (dev_conf->rxmode.mq_mode) {
1859                 case ETH_MQ_RX_VMDQ_DCB:
1860                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1861                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1862                         PMD_INIT_LOG(ERR, "SRIOV active,"
1863                                         " unsupported mq_mode rx %d.",
1864                                         dev_conf->rxmode.mq_mode);
1865                         return -EINVAL;
1866                 case ETH_MQ_RX_RSS:
1867                 case ETH_MQ_RX_VMDQ_RSS:
1868                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1869                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1870                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1871                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1872                                                 " invalid queue number"
1873                                                 " for VMDQ RSS, allowed"
1874                                                 " value are 1, 2 or 4.");
1875                                         return -EINVAL;
1876                                 }
1877                         break;
1878                 case ETH_MQ_RX_VMDQ_ONLY:
1879                 case ETH_MQ_RX_NONE:
1880                         /* if nothing mq mode configure, use default scheme */
1881                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1882                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1883                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1884                         break;
1885                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1886                         /* SRIOV only works in VMDq enable mode */
1887                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1888                                         " wrong mq_mode rx %d.",
1889                                         dev_conf->rxmode.mq_mode);
1890                         return -EINVAL;
1891                 }
1892
1893                 switch (dev_conf->txmode.mq_mode) {
1894                 case ETH_MQ_TX_VMDQ_DCB:
1895                         /* DCB VMDQ in SRIOV mode, not implement yet */
1896                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1897                                         " unsupported VMDQ mq_mode tx %d.",
1898                                         dev_conf->txmode.mq_mode);
1899                         return -EINVAL;
1900                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1901                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1902                         break;
1903                 }
1904
1905                 /* check valid queue number */
1906                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1907                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1908                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1909                                         " queue number must less equal to %d.",
1910                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1911                         return -EINVAL;
1912                 }
1913         } else {
1914                 /* check configuration for vmdb+dcb mode */
1915                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1916                         const struct rte_eth_vmdq_dcb_conf *conf;
1917
1918                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1919                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1920                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1921                                 return -EINVAL;
1922                         }
1923                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1924                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1925                                conf->nb_queue_pools == ETH_32_POOLS)) {
1926                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1927                                                 " nb_queue_pools must be %d or %d.",
1928                                                 ETH_16_POOLS, ETH_32_POOLS);
1929                                 return -EINVAL;
1930                         }
1931                 }
1932                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1933                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1934
1935                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1936                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1937                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1938                                 return -EINVAL;
1939                         }
1940                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1941                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1942                                conf->nb_queue_pools == ETH_32_POOLS)) {
1943                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1944                                                 " nb_queue_pools != %d and"
1945                                                 " nb_queue_pools != %d.",
1946                                                 ETH_16_POOLS, ETH_32_POOLS);
1947                                 return -EINVAL;
1948                         }
1949                 }
1950
1951                 /* For DCB mode check our configuration before we go further */
1952                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1953                         const struct rte_eth_dcb_rx_conf *conf;
1954
1955                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1956                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1957                                                  IXGBE_DCB_NB_QUEUES);
1958                                 return -EINVAL;
1959                         }
1960                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1961                         if (!(conf->nb_tcs == ETH_4_TCS ||
1962                                conf->nb_tcs == ETH_8_TCS)) {
1963                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1964                                                 " and nb_tcs != %d.",
1965                                                 ETH_4_TCS, ETH_8_TCS);
1966                                 return -EINVAL;
1967                         }
1968                 }
1969
1970                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1971                         const struct rte_eth_dcb_tx_conf *conf;
1972
1973                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1974                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1975                                                  IXGBE_DCB_NB_QUEUES);
1976                                 return -EINVAL;
1977                         }
1978                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1979                         if (!(conf->nb_tcs == ETH_4_TCS ||
1980                                conf->nb_tcs == ETH_8_TCS)) {
1981                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1982                                                 " and nb_tcs != %d.",
1983                                                 ETH_4_TCS, ETH_8_TCS);
1984                                 return -EINVAL;
1985                         }
1986                 }
1987         }
1988         return 0;
1989 }
1990
1991 static int
1992 ixgbe_dev_configure(struct rte_eth_dev *dev)
1993 {
1994         struct ixgbe_interrupt *intr =
1995                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1996         struct ixgbe_adapter *adapter =
1997                 (struct ixgbe_adapter *)dev->data->dev_private;
1998         int ret;
1999
2000         PMD_INIT_FUNC_TRACE();
2001         /* multipe queue mode checking */
2002         ret  = ixgbe_check_mq_mode(dev);
2003         if (ret != 0) {
2004                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2005                             ret);
2006                 return ret;
2007         }
2008
2009         /* set flag to update link status after init */
2010         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2011
2012         /*
2013          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2014          * allocation or vector Rx preconditions we will reset it.
2015          */
2016         adapter->rx_bulk_alloc_allowed = true;
2017         adapter->rx_vec_allowed = true;
2018
2019         return 0;
2020 }
2021
2022 /*
2023  * Configure device link speed and setup link.
2024  * It returns 0 on success.
2025  */
2026 static int
2027 ixgbe_dev_start(struct rte_eth_dev *dev)
2028 {
2029         struct ixgbe_hw *hw =
2030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2031         struct ixgbe_vf_info *vfinfo =
2032                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2033         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2034         uint32_t intr_vector = 0;
2035         int err, link_up = 0, negotiate = 0;
2036         uint32_t speed = 0;
2037         int mask = 0;
2038         int status;
2039         uint16_t vf, idx;
2040
2041         PMD_INIT_FUNC_TRACE();
2042
2043         /* IXGBE devices don't support half duplex */
2044         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
2045                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
2046                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
2047                              dev->data->dev_conf.link_duplex,
2048                              dev->data->port_id);
2049                 return -EINVAL;
2050         }
2051
2052         /* disable uio/vfio intr/eventfd mapping */
2053         rte_intr_disable(intr_handle);
2054
2055         /* stop adapter */
2056         hw->adapter_stopped = 0;
2057         ixgbe_stop_adapter(hw);
2058
2059         /* reinitialize adapter
2060          * this calls reset and start */
2061         status = ixgbe_pf_reset_hw(hw);
2062         if (status != 0)
2063                 return -1;
2064         hw->mac.ops.start_hw(hw);
2065         hw->mac.get_link_status = true;
2066
2067         /* configure PF module if SRIOV enabled */
2068         ixgbe_pf_host_configure(dev);
2069
2070         /* check and configure queue intr-vector mapping */
2071         if ((rte_intr_cap_multiple(intr_handle) ||
2072              !RTE_ETH_DEV_SRIOV(dev).active) &&
2073             dev->data->dev_conf.intr_conf.rxq != 0) {
2074                 intr_vector = dev->data->nb_rx_queues;
2075                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2076                         return -1;
2077         }
2078
2079         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2080                 intr_handle->intr_vec =
2081                         rte_zmalloc("intr_vec",
2082                                     dev->data->nb_rx_queues * sizeof(int), 0);
2083                 if (intr_handle->intr_vec == NULL) {
2084                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2085                                      " intr_vec\n", dev->data->nb_rx_queues);
2086                         return -ENOMEM;
2087                 }
2088         }
2089
2090         /* confiugre msix for sleep until rx interrupt */
2091         ixgbe_configure_msix(dev);
2092
2093         /* initialize transmission unit */
2094         ixgbe_dev_tx_init(dev);
2095
2096         /* This can fail when allocating mbufs for descriptor rings */
2097         err = ixgbe_dev_rx_init(dev);
2098         if (err) {
2099                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2100                 goto error;
2101         }
2102
2103         err = ixgbe_dev_rxtx_start(dev);
2104         if (err < 0) {
2105                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2106                 goto error;
2107         }
2108
2109         /* Skip link setup if loopback mode is enabled for 82599. */
2110         if (hw->mac.type == ixgbe_mac_82599EB &&
2111                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2112                 goto skip_link_setup;
2113
2114         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2115                 err = hw->mac.ops.setup_sfp(hw);
2116                 if (err)
2117                         goto error;
2118         }
2119
2120         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2121                 /* Turn on the copper */
2122                 ixgbe_set_phy_power(hw, true);
2123         } else {
2124                 /* Turn on the laser */
2125                 ixgbe_enable_tx_laser(hw);
2126         }
2127
2128         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2129         if (err)
2130                 goto error;
2131         dev->data->dev_link.link_status = link_up;
2132
2133         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2134         if (err)
2135                 goto error;
2136
2137         switch(dev->data->dev_conf.link_speed) {
2138         case ETH_LINK_SPEED_AUTONEG:
2139                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2140                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2141                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2142                 break;
2143         case ETH_LINK_SPEED_100:
2144                 /*
2145                  * Invalid for 82598 but error will be detected by
2146                  * ixgbe_setup_link()
2147                  */
2148                 speed = IXGBE_LINK_SPEED_100_FULL;
2149                 break;
2150         case ETH_LINK_SPEED_1000:
2151                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2152                 break;
2153         case ETH_LINK_SPEED_10000:
2154                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2155                 break;
2156         default:
2157                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2158                              dev->data->dev_conf.link_speed,
2159                              dev->data->port_id);
2160                 goto error;
2161         }
2162
2163         err = ixgbe_setup_link(hw, speed, link_up);
2164         if (err)
2165                 goto error;
2166
2167 skip_link_setup:
2168
2169         if (rte_intr_allow_others(intr_handle)) {
2170                 /* check if lsc interrupt is enabled */
2171                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2172                         ixgbe_dev_lsc_interrupt_setup(dev);
2173         } else {
2174                 rte_intr_callback_unregister(intr_handle,
2175                                              ixgbe_dev_interrupt_handler,
2176                                              (void *)dev);
2177                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2178                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2179                                      " no intr multiplex\n");
2180         }
2181
2182         /* check if rxq interrupt is enabled */
2183         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2184             rte_intr_dp_is_en(intr_handle))
2185                 ixgbe_dev_rxq_interrupt_setup(dev);
2186
2187         /* enable uio/vfio intr/eventfd mapping */
2188         rte_intr_enable(intr_handle);
2189
2190         /* resume enabled intr since hw reset */
2191         ixgbe_enable_intr(dev);
2192
2193         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2194                 ETH_VLAN_EXTEND_MASK;
2195         ixgbe_vlan_offload_set(dev, mask);
2196
2197         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2198                 /* Enable vlan filtering for VMDq */
2199                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2200         }
2201
2202         /* Configure DCB hw */
2203         ixgbe_configure_dcb(dev);
2204
2205         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2206                 err = ixgbe_fdir_configure(dev);
2207                 if (err)
2208                         goto error;
2209         }
2210
2211         /* Restore vf rate limit */
2212         if (vfinfo != NULL) {
2213                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2214                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2215                                 if (vfinfo[vf].tx_rate[idx] != 0)
2216                                         ixgbe_set_vf_rate_limit(dev, vf,
2217                                                 vfinfo[vf].tx_rate[idx],
2218                                                 1 << idx);
2219         }
2220
2221         ixgbe_restore_statistics_mapping(dev);
2222
2223         return 0;
2224
2225 error:
2226         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2227         ixgbe_dev_clear_queues(dev);
2228         return -EIO;
2229 }
2230
2231 /*
2232  * Stop device: disable rx and tx functions to allow for reconfiguring.
2233  */
2234 static void
2235 ixgbe_dev_stop(struct rte_eth_dev *dev)
2236 {
2237         struct rte_eth_link link;
2238         struct ixgbe_hw *hw =
2239                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct ixgbe_vf_info *vfinfo =
2241                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2242         struct ixgbe_filter_info *filter_info =
2243                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2244         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2245         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2246         int vf;
2247
2248         PMD_INIT_FUNC_TRACE();
2249
2250         /* disable interrupts */
2251         ixgbe_disable_intr(hw);
2252
2253         /* reset the NIC */
2254         ixgbe_pf_reset_hw(hw);
2255         hw->adapter_stopped = 0;
2256
2257         /* stop adapter */
2258         ixgbe_stop_adapter(hw);
2259
2260         for (vf = 0; vfinfo != NULL &&
2261                      vf < dev->pci_dev->max_vfs; vf++)
2262                 vfinfo[vf].clear_to_send = false;
2263
2264         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2265                 /* Turn off the copper */
2266                 ixgbe_set_phy_power(hw, false);
2267         } else {
2268                 /* Turn off the laser */
2269                 ixgbe_disable_tx_laser(hw);
2270         }
2271
2272         ixgbe_dev_clear_queues(dev);
2273
2274         /* Clear stored conf */
2275         dev->data->scattered_rx = 0;
2276         dev->data->lro = 0;
2277
2278         /* Clear recorded link status */
2279         memset(&link, 0, sizeof(link));
2280         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2281
2282         /* Remove all ntuple filters of the device */
2283         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2284              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2285                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2286                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2287                              p_5tuple, entries);
2288                 rte_free(p_5tuple);
2289         }
2290         memset(filter_info->fivetuple_mask, 0,
2291                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2292
2293         if (!rte_intr_allow_others(intr_handle))
2294                 /* resume to the default handler */
2295                 rte_intr_callback_register(intr_handle,
2296                                            ixgbe_dev_interrupt_handler,
2297                                            (void *)dev);
2298
2299         /* Clean datapath event and queue/vec mapping */
2300         rte_intr_efd_disable(intr_handle);
2301         if (intr_handle->intr_vec != NULL) {
2302                 rte_free(intr_handle->intr_vec);
2303                 intr_handle->intr_vec = NULL;
2304         }
2305 }
2306
2307 /*
2308  * Set device link up: enable tx.
2309  */
2310 static int
2311 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2312 {
2313         struct ixgbe_hw *hw =
2314                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315         if (hw->mac.type == ixgbe_mac_82599EB) {
2316 #ifdef RTE_NIC_BYPASS
2317                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2318                         /* Not suported in bypass mode */
2319                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2320                                      "by device id 0x%x", hw->device_id);
2321                         return -ENOTSUP;
2322                 }
2323 #endif
2324         }
2325
2326         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2327                 /* Turn on the copper */
2328                 ixgbe_set_phy_power(hw, true);
2329         } else {
2330                 /* Turn on the laser */
2331                 ixgbe_enable_tx_laser(hw);
2332         }
2333
2334         return 0;
2335 }
2336
2337 /*
2338  * Set device link down: disable tx.
2339  */
2340 static int
2341 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2342 {
2343         struct ixgbe_hw *hw =
2344                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345         if (hw->mac.type == ixgbe_mac_82599EB) {
2346 #ifdef RTE_NIC_BYPASS
2347                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2348                         /* Not suported in bypass mode */
2349                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2350                                      "by device id 0x%x", hw->device_id);
2351                         return -ENOTSUP;
2352                 }
2353 #endif
2354         }
2355
2356         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2357                 /* Turn off the copper */
2358                 ixgbe_set_phy_power(hw, false);
2359         } else {
2360                 /* Turn off the laser */
2361                 ixgbe_disable_tx_laser(hw);
2362         }
2363
2364         return 0;
2365 }
2366
2367 /*
2368  * Reest and stop device.
2369  */
2370 static void
2371 ixgbe_dev_close(struct rte_eth_dev *dev)
2372 {
2373         struct ixgbe_hw *hw =
2374                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375
2376         PMD_INIT_FUNC_TRACE();
2377
2378         ixgbe_pf_reset_hw(hw);
2379
2380         ixgbe_dev_stop(dev);
2381         hw->adapter_stopped = 1;
2382
2383         ixgbe_dev_free_queues(dev);
2384
2385         ixgbe_disable_pcie_master(hw);
2386
2387         /* reprogram the RAR[0] in case user changed it. */
2388         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2389 }
2390
2391 static void
2392 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2393                            struct ixgbe_hw_stats *hw_stats,
2394                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2395                            uint64_t *total_qprc, uint64_t *total_qprdc)
2396 {
2397         uint32_t bprc, lxon, lxoff, total;
2398         uint32_t delta_gprc = 0;
2399         unsigned i;
2400         /* Workaround for RX byte count not including CRC bytes when CRC
2401 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2402          * is disabled.
2403 +        */
2404         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2405                         IXGBE_HLREG0_RXCRCSTRP);
2406
2407         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2408         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2409         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2410         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2411
2412         for (i = 0; i < 8; i++) {
2413                 uint32_t mp;
2414                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2415                 /* global total per queue */
2416                 hw_stats->mpc[i] += mp;
2417                 /* Running comprehensive total for stats display */
2418                 *total_missed_rx += hw_stats->mpc[i];
2419                 if (hw->mac.type == ixgbe_mac_82598EB) {
2420                         hw_stats->rnbc[i] +=
2421                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2422                         hw_stats->pxonrxc[i] +=
2423                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2424                         hw_stats->pxoffrxc[i] +=
2425                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2426                 } else {
2427                         hw_stats->pxonrxc[i] +=
2428                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2429                         hw_stats->pxoffrxc[i] +=
2430                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2431                         hw_stats->pxon2offc[i] +=
2432                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2433                 }
2434                 hw_stats->pxontxc[i] +=
2435                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2436                 hw_stats->pxofftxc[i] +=
2437                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2438         }
2439         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2440                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2441                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2442                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2443
2444                 delta_gprc += delta_qprc;
2445
2446                 hw_stats->qprc[i] += delta_qprc;
2447                 hw_stats->qptc[i] += delta_qptc;
2448
2449                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2450                 hw_stats->qbrc[i] +=
2451                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2452                 if (crc_strip == 0)
2453                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2454
2455                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2456                 hw_stats->qbtc[i] +=
2457                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2458
2459                 hw_stats->qprdc[i] += delta_qprdc;
2460                 *total_qprdc += hw_stats->qprdc[i];
2461
2462                 *total_qprc += hw_stats->qprc[i];
2463                 *total_qbrc += hw_stats->qbrc[i];
2464         }
2465         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2466         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2467         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2468
2469         /*
2470          * An errata states that gprc actually counts good + missed packets:
2471          * Workaround to set gprc to summated queue packet receives
2472          */
2473         hw_stats->gprc = *total_qprc;
2474
2475         if (hw->mac.type != ixgbe_mac_82598EB) {
2476                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2477                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2478                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2479                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2480                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2481                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2482                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2483                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2484         } else {
2485                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2486                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2487                 /* 82598 only has a counter in the high register */
2488                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2489                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2490                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2491         }
2492         uint64_t old_tpr = hw_stats->tpr;
2493
2494         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2495         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2496
2497         if (crc_strip == 0)
2498                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2499
2500         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2501         hw_stats->gptc += delta_gptc;
2502         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2503         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2504
2505         /*
2506          * Workaround: mprc hardware is incorrectly counting
2507          * broadcasts, so for now we subtract those.
2508          */
2509         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2510         hw_stats->bprc += bprc;
2511         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2512         if (hw->mac.type == ixgbe_mac_82598EB)
2513                 hw_stats->mprc -= bprc;
2514
2515         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2516         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2517         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2518         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2519         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2520         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2521
2522         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2523         hw_stats->lxontxc += lxon;
2524         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2525         hw_stats->lxofftxc += lxoff;
2526         total = lxon + lxoff;
2527
2528         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2529         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2530         hw_stats->gptc -= total;
2531         hw_stats->mptc -= total;
2532         hw_stats->ptc64 -= total;
2533         hw_stats->gotc -= total * ETHER_MIN_LEN;
2534
2535         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2536         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2537         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2538         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2539         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2540         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2541         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2542         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2543         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2544         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2545         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2546         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2547         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2548         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2549         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2550         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2551         /* Only read FCOE on 82599 */
2552         if (hw->mac.type != ixgbe_mac_82598EB) {
2553                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2554                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2555                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2556                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2557                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2558         }
2559
2560         /* Flow Director Stats registers */
2561         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2562         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2563 }
2564
2565 /*
2566  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2567  */
2568 static void
2569 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2570 {
2571         struct ixgbe_hw *hw =
2572                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         struct ixgbe_hw_stats *hw_stats =
2574                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2575         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2576         unsigned i;
2577
2578         total_missed_rx = 0;
2579         total_qbrc = 0;
2580         total_qprc = 0;
2581         total_qprdc = 0;
2582
2583         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2584                         &total_qprc, &total_qprdc);
2585
2586         if (stats == NULL)
2587                 return;
2588
2589         /* Fill out the rte_eth_stats statistics structure */
2590         stats->ipackets = total_qprc;
2591         stats->ibytes = total_qbrc;
2592         stats->opackets = hw_stats->gptc;
2593         stats->obytes = hw_stats->gotc;
2594
2595         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2596                 stats->q_ipackets[i] = hw_stats->qprc[i];
2597                 stats->q_opackets[i] = hw_stats->qptc[i];
2598                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2599                 stats->q_obytes[i] = hw_stats->qbtc[i];
2600                 stats->q_errors[i] = hw_stats->qprdc[i];
2601         }
2602
2603         /* Rx Errors */
2604         stats->imissed  = total_missed_rx;
2605         stats->ierrors  = hw_stats->crcerrs +
2606                           hw_stats->mspdc +
2607                           hw_stats->rlec +
2608                           hw_stats->ruc +
2609                           hw_stats->roc +
2610                           total_missed_rx +
2611                           hw_stats->illerrc +
2612                           hw_stats->errbc +
2613                           hw_stats->rfc +
2614                           hw_stats->fccrc +
2615                           hw_stats->fclast;
2616
2617         /* Tx Errors */
2618         stats->oerrors  = 0;
2619 }
2620
2621 static void
2622 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2623 {
2624         struct ixgbe_hw_stats *stats =
2625                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2626
2627         /* HW registers are cleared on read */
2628         ixgbe_dev_stats_get(dev, NULL);
2629
2630         /* Reset software totals */
2631         memset(stats, 0, sizeof(*stats));
2632 }
2633
2634 /* This function calculates the number of xstats based on the current config */
2635 static unsigned
2636 ixgbe_xstats_calc_num(void) {
2637         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2638                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2639 }
2640
2641 static int
2642 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2643                                          unsigned n)
2644 {
2645         struct ixgbe_hw *hw =
2646                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct ixgbe_hw_stats *hw_stats =
2648                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2649         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2650         unsigned i, stat, count = 0;
2651
2652         count = ixgbe_xstats_calc_num();
2653
2654         if (n < count)
2655                 return count;
2656
2657         total_missed_rx = 0;
2658         total_qbrc = 0;
2659         total_qprc = 0;
2660         total_qprdc = 0;
2661
2662         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2663                                    &total_qprc, &total_qprdc);
2664
2665         /* If this is a reset xstats is NULL, and we have cleared the
2666          * registers by reading them.
2667          */
2668         if (!xstats)
2669                 return 0;
2670
2671         /* Extended stats from ixgbe_hw_stats */
2672         count = 0;
2673         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2674                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2675                          rte_ixgbe_stats_strings[i].name);
2676                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2677                                 rte_ixgbe_stats_strings[i].offset);
2678                 count++;
2679         }
2680
2681         /* RX Priority Stats */
2682         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2683                 for (i = 0; i < 8; i++) {
2684                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2685                                  "rx_priority%u_%s", i,
2686                                  rte_ixgbe_rxq_strings[stat].name);
2687                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2688                                         rte_ixgbe_rxq_strings[stat].offset +
2689                                         (sizeof(uint64_t) * i));
2690                         count++;
2691                 }
2692         }
2693
2694         /* TX Priority Stats */
2695         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2696                 for (i = 0; i < 8; i++) {
2697                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2698                                  "tx_priority%u_%s", i,
2699                                  rte_ixgbe_txq_strings[stat].name);
2700                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2701                                         rte_ixgbe_txq_strings[stat].offset +
2702                                         (sizeof(uint64_t) * i));
2703                         count++;
2704                 }
2705         }
2706
2707         return count;
2708 }
2709
2710 static void
2711 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2712 {
2713         struct ixgbe_hw_stats *stats =
2714                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2715
2716         unsigned count = ixgbe_xstats_calc_num();
2717
2718         /* HW registers are cleared on read */
2719         ixgbe_dev_xstats_get(dev, NULL, count);
2720
2721         /* Reset software totals */
2722         memset(stats, 0, sizeof(*stats));
2723 }
2724
2725 static void
2726 ixgbevf_update_stats(struct rte_eth_dev *dev)
2727 {
2728         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2729         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2730                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2731
2732         /* Good Rx packet, include VF loopback */
2733         UPDATE_VF_STAT(IXGBE_VFGPRC,
2734             hw_stats->last_vfgprc, hw_stats->vfgprc);
2735
2736         /* Good Rx octets, include VF loopback */
2737         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2738             hw_stats->last_vfgorc, hw_stats->vfgorc);
2739
2740         /* Good Tx packet, include VF loopback */
2741         UPDATE_VF_STAT(IXGBE_VFGPTC,
2742             hw_stats->last_vfgptc, hw_stats->vfgptc);
2743
2744         /* Good Tx octets, include VF loopback */
2745         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2746             hw_stats->last_vfgotc, hw_stats->vfgotc);
2747
2748         /* Rx Multicst Packet */
2749         UPDATE_VF_STAT(IXGBE_VFMPRC,
2750             hw_stats->last_vfmprc, hw_stats->vfmprc);
2751 }
2752
2753 static int
2754 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2755                        unsigned n)
2756 {
2757         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2758                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2759         unsigned i;
2760
2761         if (n < IXGBEVF_NB_XSTATS)
2762                 return IXGBEVF_NB_XSTATS;
2763
2764         ixgbevf_update_stats(dev);
2765
2766         if (!xstats)
2767                 return 0;
2768
2769         /* Extended stats */
2770         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2771                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2772                          "%s", rte_ixgbevf_stats_strings[i].name);
2773                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2774                         rte_ixgbevf_stats_strings[i].offset);
2775         }
2776
2777         return IXGBEVF_NB_XSTATS;
2778 }
2779
2780 static void
2781 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2782 {
2783         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2784                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2785
2786         ixgbevf_update_stats(dev);
2787
2788         if (stats == NULL)
2789                 return;
2790
2791         stats->ipackets = hw_stats->vfgprc;
2792         stats->ibytes = hw_stats->vfgorc;
2793         stats->opackets = hw_stats->vfgptc;
2794         stats->obytes = hw_stats->vfgotc;
2795         stats->imcasts = hw_stats->vfmprc;
2796         /* stats->imcasts should be removed as imcasts is deprecated */
2797 }
2798
2799 static void
2800 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2801 {
2802         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2803                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2804
2805         /* Sync HW register to the last stats */
2806         ixgbevf_dev_stats_get(dev, NULL);
2807
2808         /* reset HW current stats*/
2809         hw_stats->vfgprc = 0;
2810         hw_stats->vfgorc = 0;
2811         hw_stats->vfgptc = 0;
2812         hw_stats->vfgotc = 0;
2813         hw_stats->vfmprc = 0;
2814
2815 }
2816
2817 static void
2818 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2819 {
2820         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2821
2822         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2823         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2824         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2825         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2826         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2827         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2828         dev_info->max_vfs = dev->pci_dev->max_vfs;
2829         if (hw->mac.type == ixgbe_mac_82598EB)
2830                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2831         else
2832                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2833         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2834         dev_info->rx_offload_capa =
2835                 DEV_RX_OFFLOAD_VLAN_STRIP |
2836                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2837                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2838                 DEV_RX_OFFLOAD_TCP_CKSUM;
2839
2840         /*
2841          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2842          * mode.
2843          */
2844         if ((hw->mac.type == ixgbe_mac_82599EB ||
2845              hw->mac.type == ixgbe_mac_X540) &&
2846             !RTE_ETH_DEV_SRIOV(dev).active)
2847                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2848
2849         if (hw->mac.type == ixgbe_mac_X550 ||
2850             hw->mac.type == ixgbe_mac_X550EM_x)
2851                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
2852
2853         dev_info->tx_offload_capa =
2854                 DEV_TX_OFFLOAD_VLAN_INSERT |
2855                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2856                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2857                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2858                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2859                 DEV_TX_OFFLOAD_TCP_TSO;
2860
2861         if (hw->mac.type == ixgbe_mac_X550 ||
2862             hw->mac.type == ixgbe_mac_X550EM_x)
2863                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2864
2865         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2866                 .rx_thresh = {
2867                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2868                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2869                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2870                 },
2871                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2872                 .rx_drop_en = 0,
2873         };
2874
2875         dev_info->default_txconf = (struct rte_eth_txconf) {
2876                 .tx_thresh = {
2877                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2878                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2879                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2880                 },
2881                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2882                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2883                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2884                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2885         };
2886
2887         dev_info->rx_desc_lim = rx_desc_lim;
2888         dev_info->tx_desc_lim = tx_desc_lim;
2889
2890         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2891         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2892         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2893 }
2894
2895 static void
2896 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2897                      struct rte_eth_dev_info *dev_info)
2898 {
2899         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2900
2901         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2902         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2903         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2904         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2905         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2906         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2907         dev_info->max_vfs = dev->pci_dev->max_vfs;
2908         if (hw->mac.type == ixgbe_mac_82598EB)
2909                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2910         else
2911                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2912         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2913                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2914                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2915                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2916         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2917                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2918                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2919                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2920                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2921                                 DEV_TX_OFFLOAD_TCP_TSO;
2922
2923         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2924                 .rx_thresh = {
2925                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2926                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2927                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2928                 },
2929                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2930                 .rx_drop_en = 0,
2931         };
2932
2933         dev_info->default_txconf = (struct rte_eth_txconf) {
2934                 .tx_thresh = {
2935                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2936                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2937                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2938                 },
2939                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2940                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2941                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2942                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2943         };
2944
2945         dev_info->rx_desc_lim = rx_desc_lim;
2946         dev_info->tx_desc_lim = tx_desc_lim;
2947 }
2948
2949 /* return 0 means link status changed, -1 means not changed */
2950 static int
2951 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2952 {
2953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2954         struct rte_eth_link link, old;
2955         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2956         int link_up;
2957         int diag;
2958
2959         link.link_status = 0;
2960         link.link_speed = 0;
2961         link.link_duplex = 0;
2962         memset(&old, 0, sizeof(old));
2963         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2964
2965         hw->mac.get_link_status = true;
2966
2967         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2968         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2969                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2970         else
2971                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2972
2973         if (diag != 0) {
2974                 link.link_speed = ETH_LINK_SPEED_100;
2975                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2976                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2977                 if (link.link_status == old.link_status)
2978                         return -1;
2979                 return 0;
2980         }
2981
2982         if (link_up == 0) {
2983                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2984                 if (link.link_status == old.link_status)
2985                         return -1;
2986                 return 0;
2987         }
2988         link.link_status = 1;
2989         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2990
2991         switch (link_speed) {
2992         default:
2993         case IXGBE_LINK_SPEED_UNKNOWN:
2994                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2995                 link.link_speed = ETH_LINK_SPEED_100;
2996                 break;
2997
2998         case IXGBE_LINK_SPEED_100_FULL:
2999                 link.link_speed = ETH_LINK_SPEED_100;
3000                 break;
3001
3002         case IXGBE_LINK_SPEED_1GB_FULL:
3003                 link.link_speed = ETH_LINK_SPEED_1000;
3004                 break;
3005
3006         case IXGBE_LINK_SPEED_10GB_FULL:
3007                 link.link_speed = ETH_LINK_SPEED_10000;
3008                 break;
3009         }
3010         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3011
3012         if (link.link_status == old.link_status)
3013                 return -1;
3014
3015         return 0;
3016 }
3017
3018 static void
3019 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3020 {
3021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022         uint32_t fctrl;
3023
3024         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3025         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3026         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3027 }
3028
3029 static void
3030 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3031 {
3032         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3033         uint32_t fctrl;
3034
3035         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3036         fctrl &= (~IXGBE_FCTRL_UPE);
3037         if (dev->data->all_multicast == 1)
3038                 fctrl |= IXGBE_FCTRL_MPE;
3039         else
3040                 fctrl &= (~IXGBE_FCTRL_MPE);
3041         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3042 }
3043
3044 static void
3045 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3046 {
3047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048         uint32_t fctrl;
3049
3050         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3051         fctrl |= IXGBE_FCTRL_MPE;
3052         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3053 }
3054
3055 static void
3056 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3057 {
3058         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3059         uint32_t fctrl;
3060
3061         if (dev->data->promiscuous == 1)
3062                 return; /* must remain in all_multicast mode */
3063
3064         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3065         fctrl &= (~IXGBE_FCTRL_MPE);
3066         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3067 }
3068
3069 /**
3070  * It clears the interrupt causes and enables the interrupt.
3071  * It will be called once only during nic initialized.
3072  *
3073  * @param dev
3074  *  Pointer to struct rte_eth_dev.
3075  *
3076  * @return
3077  *  - On success, zero.
3078  *  - On failure, a negative value.
3079  */
3080 static int
3081 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3082 {
3083         struct ixgbe_interrupt *intr =
3084                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3085
3086         ixgbe_dev_link_status_print(dev);
3087         intr->mask |= IXGBE_EICR_LSC;
3088
3089         return 0;
3090 }
3091
3092 /**
3093  * It clears the interrupt causes and enables the interrupt.
3094  * It will be called once only during nic initialized.
3095  *
3096  * @param dev
3097  *  Pointer to struct rte_eth_dev.
3098  *
3099  * @return
3100  *  - On success, zero.
3101  *  - On failure, a negative value.
3102  */
3103 static int
3104 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3105 {
3106         struct ixgbe_interrupt *intr =
3107                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3108
3109         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3110
3111         return 0;
3112 }
3113
3114 /*
3115  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3116  *
3117  * @param dev
3118  *  Pointer to struct rte_eth_dev.
3119  *
3120  * @return
3121  *  - On success, zero.
3122  *  - On failure, a negative value.
3123  */
3124 static int
3125 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3126 {
3127         uint32_t eicr;
3128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3129         struct ixgbe_interrupt *intr =
3130                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3131
3132         /* clear all cause mask */
3133         ixgbe_disable_intr(hw);
3134
3135         /* read-on-clear nic registers here */
3136         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3137         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3138
3139         intr->flags = 0;
3140
3141         /* set flag for async link update */
3142         if (eicr & IXGBE_EICR_LSC)
3143                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3144
3145         if (eicr & IXGBE_EICR_MAILBOX)
3146                 intr->flags |= IXGBE_FLAG_MAILBOX;
3147
3148         return 0;
3149 }
3150
3151 /**
3152  * It gets and then prints the link status.
3153  *
3154  * @param dev
3155  *  Pointer to struct rte_eth_dev.
3156  *
3157  * @return
3158  *  - On success, zero.
3159  *  - On failure, a negative value.
3160  */
3161 static void
3162 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3163 {
3164         struct rte_eth_link link;
3165
3166         memset(&link, 0, sizeof(link));
3167         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3168         if (link.link_status) {
3169                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3170                                         (int)(dev->data->port_id),
3171                                         (unsigned)link.link_speed,
3172                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3173                                         "full-duplex" : "half-duplex");
3174         } else {
3175                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3176                                 (int)(dev->data->port_id));
3177         }
3178         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3179                                 dev->pci_dev->addr.domain,
3180                                 dev->pci_dev->addr.bus,
3181                                 dev->pci_dev->addr.devid,
3182                                 dev->pci_dev->addr.function);
3183 }
3184
3185 /*
3186  * It executes link_update after knowing an interrupt occurred.
3187  *
3188  * @param dev
3189  *  Pointer to struct rte_eth_dev.
3190  *
3191  * @return
3192  *  - On success, zero.
3193  *  - On failure, a negative value.
3194  */
3195 static int
3196 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3197 {
3198         struct ixgbe_interrupt *intr =
3199                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3200         int64_t timeout;
3201         struct rte_eth_link link;
3202         int intr_enable_delay = false;
3203
3204         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3205
3206         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3207                 ixgbe_pf_mbx_process(dev);
3208                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3209         }
3210
3211         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3212                 /* get the link status before link update, for predicting later */
3213                 memset(&link, 0, sizeof(link));
3214                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3215
3216                 ixgbe_dev_link_update(dev, 0);
3217
3218                 /* likely to up */
3219                 if (!link.link_status)
3220                         /* handle it 1 sec later, wait it being stable */
3221                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3222                 /* likely to down */
3223                 else
3224                         /* handle it 4 sec later, wait it being stable */
3225                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3226
3227                 ixgbe_dev_link_status_print(dev);
3228
3229                 intr_enable_delay = true;
3230         }
3231
3232         if (intr_enable_delay) {
3233                 if (rte_eal_alarm_set(timeout * 1000,
3234                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3235                         PMD_DRV_LOG(ERR, "Error setting alarm");
3236         } else {
3237                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3238                 ixgbe_enable_intr(dev);
3239                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3240         }
3241
3242
3243         return 0;
3244 }
3245
3246 /**
3247  * Interrupt handler which shall be registered for alarm callback for delayed
3248  * handling specific interrupt to wait for the stable nic state. As the
3249  * NIC interrupt state is not stable for ixgbe after link is just down,
3250  * it needs to wait 4 seconds to get the stable status.
3251  *
3252  * @param handle
3253  *  Pointer to interrupt handle.
3254  * @param param
3255  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3256  *
3257  * @return
3258  *  void
3259  */
3260 static void
3261 ixgbe_dev_interrupt_delayed_handler(void *param)
3262 {
3263         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3264         struct ixgbe_interrupt *intr =
3265                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3266         struct ixgbe_hw *hw =
3267                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268         uint32_t eicr;
3269
3270         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3271         if (eicr & IXGBE_EICR_MAILBOX)
3272                 ixgbe_pf_mbx_process(dev);
3273
3274         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3275                 ixgbe_dev_link_update(dev, 0);
3276                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3277                 ixgbe_dev_link_status_print(dev);
3278                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3279         }
3280
3281         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3282         ixgbe_enable_intr(dev);
3283         rte_intr_enable(&(dev->pci_dev->intr_handle));
3284 }
3285
3286 /**
3287  * Interrupt handler triggered by NIC  for handling
3288  * specific interrupt.
3289  *
3290  * @param handle
3291  *  Pointer to interrupt handle.
3292  * @param param
3293  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3294  *
3295  * @return
3296  *  void
3297  */
3298 static void
3299 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3300                             void *param)
3301 {
3302         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3303
3304         ixgbe_dev_interrupt_get_status(dev);
3305         ixgbe_dev_interrupt_action(dev);
3306 }
3307
3308 static int
3309 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3310 {
3311         struct ixgbe_hw *hw;
3312
3313         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3314         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3315 }
3316
3317 static int
3318 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3319 {
3320         struct ixgbe_hw *hw;
3321
3322         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3323         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3324 }
3325
3326 static int
3327 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3328 {
3329         struct ixgbe_hw *hw;
3330         uint32_t mflcn_reg;
3331         uint32_t fccfg_reg;
3332         int rx_pause;
3333         int tx_pause;
3334
3335         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336
3337         fc_conf->pause_time = hw->fc.pause_time;
3338         fc_conf->high_water = hw->fc.high_water[0];
3339         fc_conf->low_water = hw->fc.low_water[0];
3340         fc_conf->send_xon = hw->fc.send_xon;
3341         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3342
3343         /*
3344          * Return rx_pause status according to actual setting of
3345          * MFLCN register.
3346          */
3347         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3348         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3349                 rx_pause = 1;
3350         else
3351                 rx_pause = 0;
3352
3353         /*
3354          * Return tx_pause status according to actual setting of
3355          * FCCFG register.
3356          */
3357         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3358         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3359                 tx_pause = 1;
3360         else
3361                 tx_pause = 0;
3362
3363         if (rx_pause && tx_pause)
3364                 fc_conf->mode = RTE_FC_FULL;
3365         else if (rx_pause)
3366                 fc_conf->mode = RTE_FC_RX_PAUSE;
3367         else if (tx_pause)
3368                 fc_conf->mode = RTE_FC_TX_PAUSE;
3369         else
3370                 fc_conf->mode = RTE_FC_NONE;
3371
3372         return 0;
3373 }
3374
3375 static int
3376 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3377 {
3378         struct ixgbe_hw *hw;
3379         int err;
3380         uint32_t rx_buf_size;
3381         uint32_t max_high_water;
3382         uint32_t mflcn;
3383         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3384                 ixgbe_fc_none,
3385                 ixgbe_fc_rx_pause,
3386                 ixgbe_fc_tx_pause,
3387                 ixgbe_fc_full
3388         };
3389
3390         PMD_INIT_FUNC_TRACE();
3391
3392         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3393         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3394         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3395
3396         /*
3397          * At least reserve one Ethernet frame for watermark
3398          * high_water/low_water in kilo bytes for ixgbe
3399          */
3400         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3401         if ((fc_conf->high_water > max_high_water) ||
3402                 (fc_conf->high_water < fc_conf->low_water)) {
3403                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3404                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3405                 return -EINVAL;
3406         }
3407
3408         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3409         hw->fc.pause_time     = fc_conf->pause_time;
3410         hw->fc.high_water[0]  = fc_conf->high_water;
3411         hw->fc.low_water[0]   = fc_conf->low_water;
3412         hw->fc.send_xon       = fc_conf->send_xon;
3413         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3414
3415         err = ixgbe_fc_enable(hw);
3416
3417         /* Not negotiated is not an error case */
3418         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3419
3420                 /* check if we want to forward MAC frames - driver doesn't have native
3421                  * capability to do that, so we'll write the registers ourselves */
3422
3423                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3424
3425                 /* set or clear MFLCN.PMCF bit depending on configuration */
3426                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3427                         mflcn |= IXGBE_MFLCN_PMCF;
3428                 else
3429                         mflcn &= ~IXGBE_MFLCN_PMCF;
3430
3431                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3432                 IXGBE_WRITE_FLUSH(hw);
3433
3434                 return 0;
3435         }
3436
3437         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3438         return -EIO;
3439 }
3440
3441 /**
3442  *  ixgbe_pfc_enable_generic - Enable flow control
3443  *  @hw: pointer to hardware structure
3444  *  @tc_num: traffic class number
3445  *  Enable flow control according to the current settings.
3446  */
3447 static int
3448 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3449 {
3450         int ret_val = 0;
3451         uint32_t mflcn_reg, fccfg_reg;
3452         uint32_t reg;
3453         uint32_t fcrtl, fcrth;
3454         uint8_t i;
3455         uint8_t nb_rx_en;
3456
3457         /* Validate the water mark configuration */
3458         if (!hw->fc.pause_time) {
3459                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3460                 goto out;
3461         }
3462
3463         /* Low water mark of zero causes XOFF floods */
3464         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3465                  /* High/Low water can not be 0 */
3466                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3467                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3468                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3469                         goto out;
3470                 }
3471
3472                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3473                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3474                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3475                         goto out;
3476                 }
3477         }
3478         /* Negotiate the fc mode to use */
3479         ixgbe_fc_autoneg(hw);
3480
3481         /* Disable any previous flow control settings */
3482         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3483         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3484
3485         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3486         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3487
3488         switch (hw->fc.current_mode) {
3489         case ixgbe_fc_none:
3490                 /*
3491                  * If the count of enabled RX Priority Flow control >1,
3492                  * and the TX pause can not be disabled
3493                  */
3494                 nb_rx_en = 0;
3495                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3496                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3497                         if (reg & IXGBE_FCRTH_FCEN)
3498                                 nb_rx_en++;
3499                 }
3500                 if (nb_rx_en > 1)
3501                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3502                 break;
3503         case ixgbe_fc_rx_pause:
3504                 /*
3505                  * Rx Flow control is enabled and Tx Flow control is
3506                  * disabled by software override. Since there really
3507                  * isn't a way to advertise that we are capable of RX
3508                  * Pause ONLY, we will advertise that we support both
3509                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3510                  * disable the adapter's ability to send PAUSE frames.
3511                  */
3512                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3513                 /*
3514                  * If the count of enabled RX Priority Flow control >1,
3515                  * and the TX pause can not be disabled
3516                  */
3517                 nb_rx_en = 0;
3518                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3519                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3520                         if (reg & IXGBE_FCRTH_FCEN)
3521                                 nb_rx_en++;
3522                 }
3523                 if (nb_rx_en > 1)
3524                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3525                 break;
3526         case ixgbe_fc_tx_pause:
3527                 /*
3528                  * Tx Flow control is enabled, and Rx Flow control is
3529                  * disabled by software override.
3530                  */
3531                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3532                 break;
3533         case ixgbe_fc_full:
3534                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3535                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3536                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3537                 break;
3538         default:
3539                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3540                 ret_val = IXGBE_ERR_CONFIG;
3541                 goto out;
3542                 break;
3543         }
3544
3545         /* Set 802.3x based flow control settings. */
3546         mflcn_reg |= IXGBE_MFLCN_DPF;
3547         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3548         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3549
3550         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3551         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3552                 hw->fc.high_water[tc_num]) {
3553                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3554                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3555                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3556         } else {
3557                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3558                 /*
3559                  * In order to prevent Tx hangs when the internal Tx
3560                  * switch is enabled we must set the high water mark
3561                  * to the maximum FCRTH value.  This allows the Tx
3562                  * switch to function even under heavy Rx workloads.
3563                  */
3564                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3565         }
3566         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3567
3568         /* Configure pause time (2 TCs per register) */
3569         reg = hw->fc.pause_time * 0x00010001;
3570         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3571                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3572
3573         /* Configure flow control refresh threshold value */
3574         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3575
3576 out:
3577         return ret_val;
3578 }
3579
3580 static int
3581 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3582 {
3583         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3584         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3585
3586         if (hw->mac.type != ixgbe_mac_82598EB) {
3587                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3588         }
3589         return ret_val;
3590 }
3591
3592 static int
3593 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3594 {
3595         int err;
3596         uint32_t rx_buf_size;
3597         uint32_t max_high_water;
3598         uint8_t tc_num;
3599         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3600         struct ixgbe_hw *hw =
3601                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602         struct ixgbe_dcb_config *dcb_config =
3603                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3604
3605         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3606                 ixgbe_fc_none,
3607                 ixgbe_fc_rx_pause,
3608                 ixgbe_fc_tx_pause,
3609                 ixgbe_fc_full
3610         };
3611
3612         PMD_INIT_FUNC_TRACE();
3613
3614         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3615         tc_num = map[pfc_conf->priority];
3616         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3617         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3618         /*
3619          * At least reserve one Ethernet frame for watermark
3620          * high_water/low_water in kilo bytes for ixgbe
3621          */
3622         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3623         if ((pfc_conf->fc.high_water > max_high_water) ||
3624             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3625                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3626                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3627                 return -EINVAL;
3628         }
3629
3630         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3631         hw->fc.pause_time = pfc_conf->fc.pause_time;
3632         hw->fc.send_xon = pfc_conf->fc.send_xon;
3633         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3634         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3635
3636         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3637
3638         /* Not negotiated is not an error case */
3639         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3640                 return 0;
3641
3642         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3643         return -EIO;
3644 }
3645
3646 static int
3647 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3648                           struct rte_eth_rss_reta_entry64 *reta_conf,
3649                           uint16_t reta_size)
3650 {
3651         uint8_t i, j, mask;
3652         uint32_t reta, r;
3653         uint16_t idx, shift;
3654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3655         uint16_t sp_reta_size;
3656         uint32_t reta_reg;
3657
3658         PMD_INIT_FUNC_TRACE();
3659
3660         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3661                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3662                         "NIC.");
3663                 return -ENOTSUP;
3664         }
3665
3666         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3667         if (reta_size != sp_reta_size) {
3668                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3669                         "(%d) doesn't match the number hardware can supported "
3670                         "(%d)\n", reta_size, sp_reta_size);
3671                 return -EINVAL;
3672         }
3673
3674         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3675                 idx = i / RTE_RETA_GROUP_SIZE;
3676                 shift = i % RTE_RETA_GROUP_SIZE;
3677                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3678                                                 IXGBE_4_BIT_MASK);
3679                 if (!mask)
3680                         continue;
3681                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3682                 if (mask == IXGBE_4_BIT_MASK)
3683                         r = 0;
3684                 else
3685                         r = IXGBE_READ_REG(hw, reta_reg);
3686                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3687                         if (mask & (0x1 << j))
3688                                 reta |= reta_conf[idx].reta[shift + j] <<
3689                                                         (CHAR_BIT * j);
3690                         else
3691                                 reta |= r & (IXGBE_8_BIT_MASK <<
3692                                                 (CHAR_BIT * j));
3693                 }
3694                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3695         }
3696
3697         return 0;
3698 }
3699
3700 static int
3701 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3702                          struct rte_eth_rss_reta_entry64 *reta_conf,
3703                          uint16_t reta_size)
3704 {
3705         uint8_t i, j, mask;
3706         uint32_t reta;
3707         uint16_t idx, shift;
3708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3709         uint16_t sp_reta_size;
3710         uint32_t reta_reg;
3711
3712         PMD_INIT_FUNC_TRACE();
3713         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3714         if (reta_size != sp_reta_size) {
3715                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3716                         "(%d) doesn't match the number hardware can supported "
3717                         "(%d)\n", reta_size, sp_reta_size);
3718                 return -EINVAL;
3719         }
3720
3721         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3722                 idx = i / RTE_RETA_GROUP_SIZE;
3723                 shift = i % RTE_RETA_GROUP_SIZE;
3724                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3725                                                 IXGBE_4_BIT_MASK);
3726                 if (!mask)
3727                         continue;
3728
3729                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3730                 reta = IXGBE_READ_REG(hw, reta_reg);
3731                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3732                         if (mask & (0x1 << j))
3733                                 reta_conf[idx].reta[shift + j] =
3734                                         ((reta >> (CHAR_BIT * j)) &
3735                                                 IXGBE_8_BIT_MASK);
3736                 }
3737         }
3738
3739         return 0;
3740 }
3741
3742 static void
3743 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3744                                 uint32_t index, uint32_t pool)
3745 {
3746         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3747         uint32_t enable_addr = 1;
3748
3749         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3750 }
3751
3752 static void
3753 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3754 {
3755         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756
3757         ixgbe_clear_rar(hw, index);
3758 }
3759
3760 static void
3761 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3762 {
3763         ixgbe_remove_rar(dev, 0);
3764
3765         ixgbe_add_rar(dev, addr, 0, 0);
3766 }
3767
3768 static int
3769 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3770 {
3771         uint32_t hlreg0;
3772         uint32_t maxfrs;
3773         struct ixgbe_hw *hw;
3774         struct rte_eth_dev_info dev_info;
3775         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3776
3777         ixgbe_dev_info_get(dev, &dev_info);
3778
3779         /* check that mtu is within the allowed range */
3780         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3781                 return -EINVAL;
3782
3783         /* refuse mtu that requires the support of scattered packets when this
3784          * feature has not been enabled before. */
3785         if (!dev->data->scattered_rx &&
3786             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3787              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3788                 return -EINVAL;
3789
3790         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3792
3793         /* switch to jumbo mode if needed */
3794         if (frame_size > ETHER_MAX_LEN) {
3795                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3796                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3797         } else {
3798                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3799                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3800         }
3801         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3802
3803         /* update max frame size */
3804         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3805
3806         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3807         maxfrs &= 0x0000FFFF;
3808         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3809         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3810
3811         return 0;
3812 }
3813
3814 /*
3815  * Virtual Function operations
3816  */
3817 static void
3818 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3819 {
3820         PMD_INIT_FUNC_TRACE();
3821
3822         /* Clear interrupt mask to stop from interrupts being generated */
3823         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3824
3825         IXGBE_WRITE_FLUSH(hw);
3826 }
3827
3828 static void
3829 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3830 {
3831         PMD_INIT_FUNC_TRACE();
3832
3833         /* VF enable interrupt autoclean */
3834         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3835         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3836         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3837
3838         IXGBE_WRITE_FLUSH(hw);
3839 }
3840
3841 static int
3842 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3843 {
3844         struct rte_eth_conf* conf = &dev->data->dev_conf;
3845         struct ixgbe_adapter *adapter =
3846                         (struct ixgbe_adapter *)dev->data->dev_private;
3847
3848         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3849                      dev->data->port_id);
3850
3851         /*
3852          * VF has no ability to enable/disable HW CRC
3853          * Keep the persistent behavior the same as Host PF
3854          */
3855 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3856         if (!conf->rxmode.hw_strip_crc) {
3857                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3858                 conf->rxmode.hw_strip_crc = 1;
3859         }
3860 #else
3861         if (conf->rxmode.hw_strip_crc) {
3862                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3863                 conf->rxmode.hw_strip_crc = 0;
3864         }
3865 #endif
3866
3867         /*
3868          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3869          * allocation or vector Rx preconditions we will reset it.
3870          */
3871         adapter->rx_bulk_alloc_allowed = true;
3872         adapter->rx_vec_allowed = true;
3873
3874         return 0;
3875 }
3876
3877 static int
3878 ixgbevf_dev_start(struct rte_eth_dev *dev)
3879 {
3880         struct ixgbe_hw *hw =
3881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3882         uint32_t intr_vector = 0;
3883         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3884
3885         int err, mask = 0;
3886
3887         PMD_INIT_FUNC_TRACE();
3888
3889         hw->mac.ops.reset_hw(hw);
3890         hw->mac.get_link_status = true;
3891
3892         /* negotiate mailbox API version to use with the PF. */
3893         ixgbevf_negotiate_api(hw);
3894
3895         ixgbevf_dev_tx_init(dev);
3896
3897         /* This can fail when allocating mbufs for descriptor rings */
3898         err = ixgbevf_dev_rx_init(dev);
3899         if (err) {
3900                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3901                 ixgbe_dev_clear_queues(dev);
3902                 return err;
3903         }
3904
3905         /* Set vfta */
3906         ixgbevf_set_vfta_all(dev,1);
3907
3908         /* Set HW strip */
3909         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3910                 ETH_VLAN_EXTEND_MASK;
3911         ixgbevf_vlan_offload_set(dev, mask);
3912
3913         ixgbevf_dev_rxtx_start(dev);
3914
3915         /* check and configure queue intr-vector mapping */
3916         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3917                 intr_vector = dev->data->nb_rx_queues;
3918                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3919                         return -1;
3920         }
3921
3922         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3923                 intr_handle->intr_vec =
3924                         rte_zmalloc("intr_vec",
3925                                     dev->data->nb_rx_queues * sizeof(int), 0);
3926                 if (intr_handle->intr_vec == NULL) {
3927                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3928                                      " intr_vec\n", dev->data->nb_rx_queues);
3929                         return -ENOMEM;
3930                 }
3931         }
3932         ixgbevf_configure_msix(dev);
3933
3934         rte_intr_enable(intr_handle);
3935
3936         /* Re-enable interrupt for VF */
3937         ixgbevf_intr_enable(hw);
3938
3939         return 0;
3940 }
3941
3942 static void
3943 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3944 {
3945         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3947
3948         PMD_INIT_FUNC_TRACE();
3949
3950         hw->adapter_stopped = 1;
3951         ixgbe_stop_adapter(hw);
3952
3953         /*
3954           * Clear what we set, but we still keep shadow_vfta to
3955           * restore after device starts
3956           */
3957         ixgbevf_set_vfta_all(dev,0);
3958
3959         /* Clear stored conf */
3960         dev->data->scattered_rx = 0;
3961
3962         ixgbe_dev_clear_queues(dev);
3963
3964         /* Clean datapath event and queue/vec mapping */
3965         rte_intr_efd_disable(intr_handle);
3966         if (intr_handle->intr_vec != NULL) {
3967                 rte_free(intr_handle->intr_vec);
3968                 intr_handle->intr_vec = NULL;
3969         }
3970 }
3971
3972 static void
3973 ixgbevf_dev_close(struct rte_eth_dev *dev)
3974 {
3975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3976
3977         PMD_INIT_FUNC_TRACE();
3978
3979         ixgbe_reset_hw(hw);
3980
3981         ixgbevf_dev_stop(dev);
3982
3983         ixgbe_dev_free_queues(dev);
3984
3985         /* reprogram the RAR[0] in case user changed it. */
3986         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3987 }
3988
3989 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3990 {
3991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3992         struct ixgbe_vfta * shadow_vfta =
3993                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3994         int i = 0, j = 0, vfta = 0, mask = 1;
3995
3996         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3997                 vfta = shadow_vfta->vfta[i];
3998                 if (vfta) {
3999                         mask = 1;
4000                         for (j = 0; j < 32; j++){
4001                                 if (vfta & mask)
4002                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4003                                 mask<<=1;
4004                         }
4005                 }
4006         }
4007
4008 }
4009
4010 static int
4011 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4012 {
4013         struct ixgbe_hw *hw =
4014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015         struct ixgbe_vfta * shadow_vfta =
4016                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4017         uint32_t vid_idx = 0;
4018         uint32_t vid_bit = 0;
4019         int ret = 0;
4020
4021         PMD_INIT_FUNC_TRACE();
4022
4023         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4024         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4025         if (ret) {
4026                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4027                 return ret;
4028         }
4029         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4030         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4031
4032         /* Save what we set and retore it after device reset */
4033         if (on)
4034                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4035         else
4036                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4037
4038         return 0;
4039 }
4040
4041 static void
4042 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4043 {
4044         struct ixgbe_hw *hw =
4045                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4046         uint32_t ctrl;
4047
4048         PMD_INIT_FUNC_TRACE();
4049
4050         if (queue >= hw->mac.max_rx_queues)
4051                 return;
4052
4053         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4054         if (on)
4055                 ctrl |= IXGBE_RXDCTL_VME;
4056         else
4057                 ctrl &= ~IXGBE_RXDCTL_VME;
4058         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4059
4060         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4061 }
4062
4063 static void
4064 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4065 {
4066         struct ixgbe_hw *hw =
4067                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4068         uint16_t i;
4069         int on = 0;
4070
4071         /* VF function only support hw strip feature, others are not support */
4072         if (mask & ETH_VLAN_STRIP_MASK) {
4073                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4074
4075                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4076                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4077         }
4078 }
4079
4080 static int
4081 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4082 {
4083         uint32_t reg_val;
4084
4085         /* we only need to do this if VMDq is enabled */
4086         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4087         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4088                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4089                 return -1;
4090         }
4091
4092         return 0;
4093 }
4094
4095 static uint32_t
4096 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4097 {
4098         uint32_t vector = 0;
4099         switch (hw->mac.mc_filter_type) {
4100         case 0:   /* use bits [47:36] of the address */
4101                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4102                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4103                 break;
4104         case 1:   /* use bits [46:35] of the address */
4105                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4106                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4107                 break;
4108         case 2:   /* use bits [45:34] of the address */
4109                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4110                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4111                 break;
4112         case 3:   /* use bits [43:32] of the address */
4113                 vector = ((uc_addr->addr_bytes[4]) |
4114                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4115                 break;
4116         default:  /* Invalid mc_filter_type */
4117                 break;
4118         }
4119
4120         /* vector can only be 12-bits or boundary will be exceeded */
4121         vector &= 0xFFF;
4122         return vector;
4123 }
4124
4125 static int
4126 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4127                                uint8_t on)
4128 {
4129         uint32_t vector;
4130         uint32_t uta_idx;
4131         uint32_t reg_val;
4132         uint32_t uta_shift;
4133         uint32_t rc;
4134         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4135         const uint32_t ixgbe_uta_bit_shift = 5;
4136         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4137         const uint32_t bit1 = 0x1;
4138
4139         struct ixgbe_hw *hw =
4140                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141         struct ixgbe_uta_info *uta_info =
4142                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4143
4144         /* The UTA table only exists on 82599 hardware and newer */
4145         if (hw->mac.type < ixgbe_mac_82599EB)
4146                 return -ENOTSUP;
4147
4148         vector = ixgbe_uta_vector(hw,mac_addr);
4149         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4150         uta_shift = vector & ixgbe_uta_bit_mask;
4151
4152         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4153         if (rc == on)
4154                 return 0;
4155
4156         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4157         if (on) {
4158                 uta_info->uta_in_use++;
4159                 reg_val |= (bit1 << uta_shift);
4160                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4161         } else {
4162                 uta_info->uta_in_use--;
4163                 reg_val &= ~(bit1 << uta_shift);
4164                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4165         }
4166
4167         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4168
4169         if (uta_info->uta_in_use > 0)
4170                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4171                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4172         else
4173                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4174
4175         return 0;
4176 }
4177
4178 static int
4179 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4180 {
4181         int i;
4182         struct ixgbe_hw *hw =
4183                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4184         struct ixgbe_uta_info *uta_info =
4185                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4186
4187         /* The UTA table only exists on 82599 hardware and newer */
4188         if (hw->mac.type < ixgbe_mac_82599EB)
4189                 return -ENOTSUP;
4190
4191         if (on) {
4192                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4193                         uta_info->uta_shadow[i] = ~0;
4194                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4195                 }
4196         } else {
4197                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4198                         uta_info->uta_shadow[i] = 0;
4199                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4200                 }
4201         }
4202         return 0;
4203
4204 }
4205
4206 uint32_t
4207 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4208 {
4209         uint32_t new_val = orig_val;
4210
4211         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4212                 new_val |= IXGBE_VMOLR_AUPE;
4213         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4214                 new_val |= IXGBE_VMOLR_ROMPE;
4215         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4216                 new_val |= IXGBE_VMOLR_ROPE;
4217         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4218                 new_val |= IXGBE_VMOLR_BAM;
4219         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4220                 new_val |= IXGBE_VMOLR_MPE;
4221
4222         return new_val;
4223 }
4224
4225 static int
4226 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4227                                uint16_t rx_mask, uint8_t on)
4228 {
4229         int val = 0;
4230
4231         struct ixgbe_hw *hw =
4232                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4233         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4234
4235         if (hw->mac.type == ixgbe_mac_82598EB) {
4236                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4237                              " on 82599 hardware and newer");
4238                 return -ENOTSUP;
4239         }
4240         if (ixgbe_vmdq_mode_check(hw) < 0)
4241                 return -ENOTSUP;
4242
4243         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4244
4245         if (on)
4246                 vmolr |= val;
4247         else
4248                 vmolr &= ~val;
4249
4250         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4251
4252         return 0;
4253 }
4254
4255 static int
4256 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4257 {
4258         uint32_t reg,addr;
4259         uint32_t val;
4260         const uint8_t bit1 = 0x1;
4261
4262         struct ixgbe_hw *hw =
4263                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4264
4265         if (ixgbe_vmdq_mode_check(hw) < 0)
4266                 return -ENOTSUP;
4267
4268         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4269         reg = IXGBE_READ_REG(hw, addr);
4270         val = bit1 << pool;
4271
4272         if (on)
4273                 reg |= val;
4274         else
4275                 reg &= ~val;
4276
4277         IXGBE_WRITE_REG(hw, addr,reg);
4278
4279         return 0;
4280 }
4281
4282 static int
4283 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4284 {
4285         uint32_t reg,addr;
4286         uint32_t val;
4287         const uint8_t bit1 = 0x1;
4288
4289         struct ixgbe_hw *hw =
4290                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4291
4292         if (ixgbe_vmdq_mode_check(hw) < 0)
4293                 return -ENOTSUP;
4294
4295         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4296         reg = IXGBE_READ_REG(hw, addr);
4297         val = bit1 << pool;
4298
4299         if (on)
4300                 reg |= val;
4301         else
4302                 reg &= ~val;
4303
4304         IXGBE_WRITE_REG(hw, addr,reg);
4305
4306         return 0;
4307 }
4308
4309 static int
4310 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4311                         uint64_t pool_mask, uint8_t vlan_on)
4312 {
4313         int ret = 0;
4314         uint16_t pool_idx;
4315         struct ixgbe_hw *hw =
4316                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4317
4318         if (ixgbe_vmdq_mode_check(hw) < 0)
4319                 return -ENOTSUP;
4320         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4321                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4322                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4323                         if (ret < 0)
4324                                 return ret;
4325         }
4326
4327         return ret;
4328 }
4329
4330 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4331 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4332 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4333 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4334 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4335         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4336         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4337
4338 static int
4339 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4340                         struct rte_eth_mirror_conf *mirror_conf,
4341                         uint8_t rule_id, uint8_t on)
4342 {
4343         uint32_t mr_ctl,vlvf;
4344         uint32_t mp_lsb = 0;
4345         uint32_t mv_msb = 0;
4346         uint32_t mv_lsb = 0;
4347         uint32_t mp_msb = 0;
4348         uint8_t i = 0;
4349         int reg_index = 0;
4350         uint64_t vlan_mask = 0;
4351
4352         const uint8_t pool_mask_offset = 32;
4353         const uint8_t vlan_mask_offset = 32;
4354         const uint8_t dst_pool_offset = 8;
4355         const uint8_t rule_mr_offset  = 4;
4356         const uint8_t mirror_rule_mask= 0x0F;
4357
4358         struct ixgbe_mirror_info *mr_info =
4359                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4360         struct ixgbe_hw *hw =
4361                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4362         uint8_t mirror_type = 0;
4363
4364         if (ixgbe_vmdq_mode_check(hw) < 0)
4365                 return -ENOTSUP;
4366
4367         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4368                 return -EINVAL;
4369
4370         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4371                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4372                         mirror_conf->rule_type);
4373                 return -EINVAL;
4374         }
4375
4376         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4377                 mirror_type |= IXGBE_MRCTL_VLME;
4378                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4379                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4380                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4381                                 /* search vlan id related pool vlan filter index */
4382                                 reg_index = ixgbe_find_vlvf_slot(hw,
4383                                                 mirror_conf->vlan.vlan_id[i]);
4384                                 if (reg_index < 0)
4385                                         return -EINVAL;
4386                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4387                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4388                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4389                                       mirror_conf->vlan.vlan_id[i]))
4390                                         vlan_mask |= (1ULL << reg_index);
4391                                 else
4392                                         return -EINVAL;
4393                         }
4394                 }
4395
4396                 if (on) {
4397                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4398                         mv_msb = vlan_mask >> vlan_mask_offset;
4399
4400                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4401                                                 mirror_conf->vlan.vlan_mask;
4402                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4403                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4404                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4405                                                 mirror_conf->vlan.vlan_id[i];
4406                         }
4407                 } else {
4408                         mv_lsb = 0;
4409                         mv_msb = 0;
4410                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4411                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4412                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4413                 }
4414         }
4415
4416         /*
4417          * if enable pool mirror, write related pool mask register,if disable
4418          * pool mirror, clear PFMRVM register
4419          */
4420         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4421                 mirror_type |= IXGBE_MRCTL_VPME;
4422                 if (on) {
4423                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4424                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4425                         mr_info->mr_conf[rule_id].pool_mask =
4426                                         mirror_conf->pool_mask;
4427
4428                 } else {
4429                         mp_lsb = 0;
4430                         mp_msb = 0;
4431                         mr_info->mr_conf[rule_id].pool_mask = 0;
4432                 }
4433         }
4434         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4435                 mirror_type |= IXGBE_MRCTL_UPME;
4436         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4437                 mirror_type |= IXGBE_MRCTL_DPME;
4438
4439         /* read  mirror control register and recalculate it */
4440         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4441
4442         if (on) {
4443                 mr_ctl |= mirror_type;
4444                 mr_ctl &= mirror_rule_mask;
4445                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4446         } else
4447                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4448
4449         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4450         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4451
4452         /* write mirrror control  register */
4453         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4454
4455         /* write pool mirrror control  register */
4456         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4457                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4458                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4459                                 mp_msb);
4460         }
4461         /* write VLAN mirrror control  register */
4462         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4463                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4464                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4465                                 mv_msb);
4466         }
4467
4468         return 0;
4469 }
4470
4471 static int
4472 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4473 {
4474         int mr_ctl = 0;
4475         uint32_t lsb_val = 0;
4476         uint32_t msb_val = 0;
4477         const uint8_t rule_mr_offset = 4;
4478
4479         struct ixgbe_hw *hw =
4480                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4481         struct ixgbe_mirror_info *mr_info =
4482                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4483
4484         if (ixgbe_vmdq_mode_check(hw) < 0)
4485                 return -ENOTSUP;
4486
4487         memset(&mr_info->mr_conf[rule_id], 0,
4488                 sizeof(struct rte_eth_mirror_conf));
4489
4490         /* clear PFVMCTL register */
4491         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4492
4493         /* clear pool mask register */
4494         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4495         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4496
4497         /* clear vlan mask register */
4498         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4499         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4500
4501         return 0;
4502 }
4503
4504 static int
4505 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4506 {
4507         uint32_t mask;
4508         struct ixgbe_hw *hw =
4509                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4510
4511         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4512         mask |= (1 << IXGBE_MISC_VEC_ID);
4513         RTE_SET_USED(queue_id);
4514         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4515
4516         rte_intr_enable(&dev->pci_dev->intr_handle);
4517
4518         return 0;
4519 }
4520
4521 static int
4522 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4523 {
4524         uint32_t mask;
4525         struct ixgbe_hw *hw =
4526                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527
4528         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4529         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4530         RTE_SET_USED(queue_id);
4531         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4532
4533         return 0;
4534 }
4535
4536 static int
4537 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4538 {
4539         uint32_t mask;
4540         struct ixgbe_hw *hw =
4541                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4542         struct ixgbe_interrupt *intr =
4543                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4544
4545         if (queue_id < 16) {
4546                 ixgbe_disable_intr(hw);
4547                 intr->mask |= (1 << queue_id);
4548                 ixgbe_enable_intr(dev);
4549         } else if (queue_id < 32) {
4550                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4551                 mask &= (1 << queue_id);
4552                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4553         } else if (queue_id < 64) {
4554                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4555                 mask &= (1 << (queue_id - 32));
4556                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4557         }
4558         rte_intr_enable(&dev->pci_dev->intr_handle);
4559
4560         return 0;
4561 }
4562
4563 static int
4564 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4565 {
4566         uint32_t mask;
4567         struct ixgbe_hw *hw =
4568                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4569         struct ixgbe_interrupt *intr =
4570                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4571
4572         if (queue_id < 16) {
4573                 ixgbe_disable_intr(hw);
4574                 intr->mask &= ~(1 << queue_id);
4575                 ixgbe_enable_intr(dev);
4576         } else if (queue_id < 32) {
4577                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4578                 mask &= ~(1 << queue_id);
4579                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4580         } else if (queue_id < 64) {
4581                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4582                 mask &= ~(1 << (queue_id - 32));
4583                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4584         }
4585
4586         return 0;
4587 }
4588
4589 static void
4590 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4591                      uint8_t queue, uint8_t msix_vector)
4592 {
4593         uint32_t tmp, idx;
4594
4595         if (direction == -1) {
4596                 /* other causes */
4597                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4598                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4599                 tmp &= ~0xFF;
4600                 tmp |= msix_vector;
4601                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4602         } else {
4603                 /* rx or tx cause */
4604                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4605                 idx = ((16 * (queue & 1)) + (8 * direction));
4606                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4607                 tmp &= ~(0xFF << idx);
4608                 tmp |= (msix_vector << idx);
4609                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4610         }
4611 }
4612
4613 /**
4614  * set the IVAR registers, mapping interrupt causes to vectors
4615  * @param hw
4616  *  pointer to ixgbe_hw struct
4617  * @direction
4618  *  0 for Rx, 1 for Tx, -1 for other causes
4619  * @queue
4620  *  queue to map the corresponding interrupt to
4621  * @msix_vector
4622  *  the vector to map to the corresponding queue
4623  */
4624 static void
4625 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4626                    uint8_t queue, uint8_t msix_vector)
4627 {
4628         uint32_t tmp, idx;
4629
4630         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4631         if (hw->mac.type == ixgbe_mac_82598EB) {
4632                 if (direction == -1)
4633                         direction = 0;
4634                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4635                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4636                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4637                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4638                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4639         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4640                         (hw->mac.type == ixgbe_mac_X540)) {
4641                 if (direction == -1) {
4642                         /* other causes */
4643                         idx = ((queue & 1) * 8);
4644                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4645                         tmp &= ~(0xFF << idx);
4646                         tmp |= (msix_vector << idx);
4647                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4648                 } else {
4649                         /* rx or tx causes */
4650                         idx = ((16 * (queue & 1)) + (8 * direction));
4651                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4652                         tmp &= ~(0xFF << idx);
4653                         tmp |= (msix_vector << idx);
4654                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4655                 }
4656         }
4657 }
4658
4659 static void
4660 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4661 {
4662         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4663         struct ixgbe_hw *hw =
4664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4665         uint32_t q_idx;
4666         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4667
4668         /* won't configure msix register if no mapping is done
4669          * between intr vector and event fd.
4670          */
4671         if (!rte_intr_dp_is_en(intr_handle))
4672                 return;
4673
4674         /* Configure all RX queues of VF */
4675         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4676                 /* Force all queue use vector 0,
4677                  * as IXGBE_VF_MAXMSIVECOTR = 1
4678                  */
4679                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4680                 intr_handle->intr_vec[q_idx] = vector_idx;
4681         }
4682
4683         /* Configure VF other cause ivar */
4684         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4685 }
4686
4687 /**
4688  * Sets up the hardware to properly generate MSI-X interrupts
4689  * @hw
4690  *  board private structure
4691  */
4692 static void
4693 ixgbe_configure_msix(struct rte_eth_dev *dev)
4694 {
4695         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4696         struct ixgbe_hw *hw =
4697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4699         uint32_t vec = IXGBE_MISC_VEC_ID;
4700         uint32_t mask;
4701         uint32_t gpie;
4702
4703         /* won't configure msix register if no mapping is done
4704          * between intr vector and event fd
4705          */
4706         if (!rte_intr_dp_is_en(intr_handle))
4707                 return;
4708
4709         if (rte_intr_allow_others(intr_handle))
4710                 vec = base = IXGBE_RX_VEC_START;
4711
4712         /* setup GPIE for MSI-x mode */
4713         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4714         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4715                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4716         /* auto clearing and auto setting corresponding bits in EIMS
4717          * when MSI-X interrupt is triggered
4718          */
4719         if (hw->mac.type == ixgbe_mac_82598EB) {
4720                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4721         } else {
4722                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4723                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4724         }
4725         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4726
4727         /* Populate the IVAR table and set the ITR values to the
4728          * corresponding register.
4729          */
4730         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4731              queue_id++) {
4732                 /* by default, 1:1 mapping */
4733                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4734                 intr_handle->intr_vec[queue_id] = vec;
4735                 if (vec < base + intr_handle->nb_efd - 1)
4736                         vec++;
4737         }
4738
4739         switch (hw->mac.type) {
4740         case ixgbe_mac_82598EB:
4741                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4742                                    IXGBE_MISC_VEC_ID);
4743                 break;
4744         case ixgbe_mac_82599EB:
4745         case ixgbe_mac_X540:
4746                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4747                 break;
4748         default:
4749                 break;
4750         }
4751         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4752                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4753
4754         /* set up to autoclear timer, and the vectors */
4755         mask = IXGBE_EIMS_ENABLE_MASK;
4756         mask &= ~(IXGBE_EIMS_OTHER |
4757                   IXGBE_EIMS_MAILBOX |
4758                   IXGBE_EIMS_LSC);
4759
4760         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4761 }
4762
4763 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4764         uint16_t queue_idx, uint16_t tx_rate)
4765 {
4766         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4767         uint32_t rf_dec, rf_int;
4768         uint32_t bcnrc_val;
4769         uint16_t link_speed = dev->data->dev_link.link_speed;
4770
4771         if (queue_idx >= hw->mac.max_tx_queues)
4772                 return -EINVAL;
4773
4774         if (tx_rate != 0) {
4775                 /* Calculate the rate factor values to set */
4776                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4777                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4778                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4779
4780                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4781                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4782                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4783                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4784         } else {
4785                 bcnrc_val = 0;
4786         }
4787
4788         /*
4789          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4790          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4791          * set as 0x4.
4792          */
4793         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4794                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4795                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4796                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4797                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4798         else
4799                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4800                         IXGBE_MMW_SIZE_DEFAULT);
4801
4802         /* Set RTTBCNRC of queue X */
4803         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4804         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4805         IXGBE_WRITE_FLUSH(hw);
4806
4807         return 0;
4808 }
4809
4810 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4811         uint16_t tx_rate, uint64_t q_msk)
4812 {
4813         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4814         struct ixgbe_vf_info *vfinfo =
4815                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4816         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4817         uint32_t queue_stride =
4818                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4819         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4820         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4821         uint16_t total_rate = 0;
4822
4823         if (queue_end >= hw->mac.max_tx_queues)
4824                 return -EINVAL;
4825
4826         if (vfinfo != NULL) {
4827                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4828                         if (vf_idx == vf)
4829                                 continue;
4830                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4831                                 idx++)
4832                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4833                 }
4834         } else
4835                 return -EINVAL;
4836
4837         /* Store tx_rate for this vf. */
4838         for (idx = 0; idx < nb_q_per_pool; idx++) {
4839                 if (((uint64_t)0x1 << idx) & q_msk) {
4840                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4841                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4842                         total_rate += tx_rate;
4843                 }
4844         }
4845
4846         if (total_rate > dev->data->dev_link.link_speed) {
4847                 /*
4848                  * Reset stored TX rate of the VF if it causes exceed
4849                  * link speed.
4850                  */
4851                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4852                 return -EINVAL;
4853         }
4854
4855         /* Set RTTBCNRC of each queue/pool for vf X  */
4856         for (; queue_idx <= queue_end; queue_idx++) {
4857                 if (0x1 & q_msk)
4858                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4859                 q_msk = q_msk >> 1;
4860         }
4861
4862         return 0;
4863 }
4864
4865 static void
4866 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4867                      __attribute__((unused)) uint32_t index,
4868                      __attribute__((unused)) uint32_t pool)
4869 {
4870         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4871         int diag;
4872
4873         /*
4874          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4875          * operation. Trap this case to avoid exhausting the [very limited]
4876          * set of PF resources used to store VF MAC addresses.
4877          */
4878         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4879                 return;
4880         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4881         if (diag == 0)
4882                 return;
4883         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4884 }
4885
4886 static void
4887 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4888 {
4889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4891         struct ether_addr *mac_addr;
4892         uint32_t i;
4893         int diag;
4894
4895         /*
4896          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4897          * not support the deletion of a given MAC address.
4898          * Instead, it imposes to delete all MAC addresses, then to add again
4899          * all MAC addresses with the exception of the one to be deleted.
4900          */
4901         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4902
4903         /*
4904          * Add again all MAC addresses, with the exception of the deleted one
4905          * and of the permanent MAC address.
4906          */
4907         for (i = 0, mac_addr = dev->data->mac_addrs;
4908              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4909                 /* Skip the deleted MAC address */
4910                 if (i == index)
4911                         continue;
4912                 /* Skip NULL MAC addresses */
4913                 if (is_zero_ether_addr(mac_addr))
4914                         continue;
4915                 /* Skip the permanent MAC address */
4916                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4917                         continue;
4918                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4919                 if (diag != 0)
4920                         PMD_DRV_LOG(ERR,
4921                                     "Adding again MAC address "
4922                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4923                                     "diag=%d",
4924                                     mac_addr->addr_bytes[0],
4925                                     mac_addr->addr_bytes[1],
4926                                     mac_addr->addr_bytes[2],
4927                                     mac_addr->addr_bytes[3],
4928                                     mac_addr->addr_bytes[4],
4929                                     mac_addr->addr_bytes[5],
4930                                     diag);
4931         }
4932 }
4933
4934 static void
4935 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4936 {
4937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4938
4939         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4940 }
4941
4942 #define MAC_TYPE_FILTER_SUP(type)    do {\
4943         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4944                 (type) != ixgbe_mac_X550)\
4945                 return -ENOTSUP;\
4946 } while (0)
4947
4948 static int
4949 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4950                         struct rte_eth_syn_filter *filter,
4951                         bool add)
4952 {
4953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4954         uint32_t synqf;
4955
4956         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4957                 return -EINVAL;
4958
4959         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4960
4961         if (add) {
4962                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4963                         return -EINVAL;
4964                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4965                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4966
4967                 if (filter->hig_pri)
4968                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4969                 else
4970                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4971         } else {
4972                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4973                         return -ENOENT;
4974                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4975         }
4976         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4977         IXGBE_WRITE_FLUSH(hw);
4978         return 0;
4979 }
4980
4981 static int
4982 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4983                         struct rte_eth_syn_filter *filter)
4984 {
4985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4986         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4987
4988         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4989                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4990                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4991                 return 0;
4992         }
4993         return -ENOENT;
4994 }
4995
4996 static int
4997 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4998                         enum rte_filter_op filter_op,
4999                         void *arg)
5000 {
5001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5002         int ret;
5003
5004         MAC_TYPE_FILTER_SUP(hw->mac.type);
5005
5006         if (filter_op == RTE_ETH_FILTER_NOP)
5007                 return 0;
5008
5009         if (arg == NULL) {
5010                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5011                             filter_op);
5012                 return -EINVAL;
5013         }
5014
5015         switch (filter_op) {
5016         case RTE_ETH_FILTER_ADD:
5017                 ret = ixgbe_syn_filter_set(dev,
5018                                 (struct rte_eth_syn_filter *)arg,
5019                                 TRUE);
5020                 break;
5021         case RTE_ETH_FILTER_DELETE:
5022                 ret = ixgbe_syn_filter_set(dev,
5023                                 (struct rte_eth_syn_filter *)arg,
5024                                 FALSE);
5025                 break;
5026         case RTE_ETH_FILTER_GET:
5027                 ret = ixgbe_syn_filter_get(dev,
5028                                 (struct rte_eth_syn_filter *)arg);
5029                 break;
5030         default:
5031                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5032                 ret = -EINVAL;
5033                 break;
5034         }
5035
5036         return ret;
5037 }
5038
5039
5040 static inline enum ixgbe_5tuple_protocol
5041 convert_protocol_type(uint8_t protocol_value)
5042 {
5043         if (protocol_value == IPPROTO_TCP)
5044                 return IXGBE_FILTER_PROTOCOL_TCP;
5045         else if (protocol_value == IPPROTO_UDP)
5046                 return IXGBE_FILTER_PROTOCOL_UDP;
5047         else if (protocol_value == IPPROTO_SCTP)
5048                 return IXGBE_FILTER_PROTOCOL_SCTP;
5049         else
5050                 return IXGBE_FILTER_PROTOCOL_NONE;
5051 }
5052
5053 /*
5054  * add a 5tuple filter
5055  *
5056  * @param
5057  * dev: Pointer to struct rte_eth_dev.
5058  * index: the index the filter allocates.
5059  * filter: ponter to the filter that will be added.
5060  * rx_queue: the queue id the filter assigned to.
5061  *
5062  * @return
5063  *    - On success, zero.
5064  *    - On failure, a negative value.
5065  */
5066 static int
5067 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5068                         struct ixgbe_5tuple_filter *filter)
5069 {
5070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5071         struct ixgbe_filter_info *filter_info =
5072                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5073         int i, idx, shift;
5074         uint32_t ftqf, sdpqf;
5075         uint32_t l34timir = 0;
5076         uint8_t mask = 0xff;
5077
5078         /*
5079          * look for an unused 5tuple filter index,
5080          * and insert the filter to list.
5081          */
5082         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5083                 idx = i / (sizeof(uint32_t) * NBBY);
5084                 shift = i % (sizeof(uint32_t) * NBBY);
5085                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5086                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5087                         filter->index = i;
5088                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5089                                           filter,
5090                                           entries);
5091                         break;
5092                 }
5093         }
5094         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5095                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5096                 return -ENOSYS;
5097         }
5098
5099         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5100                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5101         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5102
5103         ftqf = (uint32_t)(filter->filter_info.proto &
5104                 IXGBE_FTQF_PROTOCOL_MASK);
5105         ftqf |= (uint32_t)((filter->filter_info.priority &
5106                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5107         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5108                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5109         if (filter->filter_info.dst_ip_mask == 0)
5110                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5111         if (filter->filter_info.src_port_mask == 0)
5112                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5113         if (filter->filter_info.dst_port_mask == 0)
5114                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5115         if (filter->filter_info.proto_mask == 0)
5116                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5117         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5118         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5119         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5120
5121         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5122         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5123         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5124         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5125
5126         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5127         l34timir |= (uint32_t)(filter->queue <<
5128                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5129         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5130         return 0;
5131 }
5132
5133 /*
5134  * remove a 5tuple filter
5135  *
5136  * @param
5137  * dev: Pointer to struct rte_eth_dev.
5138  * filter: the pointer of the filter will be removed.
5139  */
5140 static void
5141 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5142                         struct ixgbe_5tuple_filter *filter)
5143 {
5144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5145         struct ixgbe_filter_info *filter_info =
5146                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5147         uint16_t index = filter->index;
5148
5149         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5150                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5151         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5152         rte_free(filter);
5153
5154         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5155         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5156         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5157         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5158         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5159 }
5160
5161 static int
5162 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5163 {
5164         struct ixgbe_hw *hw;
5165         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5166
5167         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5168
5169         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5170                 return -EINVAL;
5171
5172         /* refuse mtu that requires the support of scattered packets when this
5173          * feature has not been enabled before. */
5174         if (!dev->data->scattered_rx &&
5175             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5176              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5177                 return -EINVAL;
5178
5179         /*
5180          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5181          * request of the version 2.0 of the mailbox API.
5182          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5183          * of the mailbox API.
5184          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5185          * prior to 3.11.33 which contains the following change:
5186          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5187          */
5188         ixgbevf_rlpml_set_vf(hw, max_frame);
5189
5190         /* update max frame size */
5191         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5192         return 0;
5193 }
5194
5195 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5196         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5197                 return -ENOTSUP;\
5198 } while (0)
5199
5200 static inline struct ixgbe_5tuple_filter *
5201 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5202                         struct ixgbe_5tuple_filter_info *key)
5203 {
5204         struct ixgbe_5tuple_filter *it;
5205
5206         TAILQ_FOREACH(it, filter_list, entries) {
5207                 if (memcmp(key, &it->filter_info,
5208                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5209                         return it;
5210                 }
5211         }
5212         return NULL;
5213 }
5214
5215 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5216 static inline int
5217 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5218                         struct ixgbe_5tuple_filter_info *filter_info)
5219 {
5220         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5221                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5222                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5223                 return -EINVAL;
5224
5225         switch (filter->dst_ip_mask) {
5226         case UINT32_MAX:
5227                 filter_info->dst_ip_mask = 0;
5228                 filter_info->dst_ip = filter->dst_ip;
5229                 break;
5230         case 0:
5231                 filter_info->dst_ip_mask = 1;
5232                 break;
5233         default:
5234                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5235                 return -EINVAL;
5236         }
5237
5238         switch (filter->src_ip_mask) {
5239         case UINT32_MAX:
5240                 filter_info->src_ip_mask = 0;
5241                 filter_info->src_ip = filter->src_ip;
5242                 break;
5243         case 0:
5244                 filter_info->src_ip_mask = 1;
5245                 break;
5246         default:
5247                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5248                 return -EINVAL;
5249         }
5250
5251         switch (filter->dst_port_mask) {
5252         case UINT16_MAX:
5253                 filter_info->dst_port_mask = 0;
5254                 filter_info->dst_port = filter->dst_port;
5255                 break;
5256         case 0:
5257                 filter_info->dst_port_mask = 1;
5258                 break;
5259         default:
5260                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5261                 return -EINVAL;
5262         }
5263
5264         switch (filter->src_port_mask) {
5265         case UINT16_MAX:
5266                 filter_info->src_port_mask = 0;
5267                 filter_info->src_port = filter->src_port;
5268                 break;
5269         case 0:
5270                 filter_info->src_port_mask = 1;
5271                 break;
5272         default:
5273                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5274                 return -EINVAL;
5275         }
5276
5277         switch (filter->proto_mask) {
5278         case UINT8_MAX:
5279                 filter_info->proto_mask = 0;
5280                 filter_info->proto =
5281                         convert_protocol_type(filter->proto);
5282                 break;
5283         case 0:
5284                 filter_info->proto_mask = 1;
5285                 break;
5286         default:
5287                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5288                 return -EINVAL;
5289         }
5290
5291         filter_info->priority = (uint8_t)filter->priority;
5292         return 0;
5293 }
5294
5295 /*
5296  * add or delete a ntuple filter
5297  *
5298  * @param
5299  * dev: Pointer to struct rte_eth_dev.
5300  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5301  * add: if true, add filter, if false, remove filter
5302  *
5303  * @return
5304  *    - On success, zero.
5305  *    - On failure, a negative value.
5306  */
5307 static int
5308 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5309                         struct rte_eth_ntuple_filter *ntuple_filter,
5310                         bool add)
5311 {
5312         struct ixgbe_filter_info *filter_info =
5313                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5314         struct ixgbe_5tuple_filter_info filter_5tuple;
5315         struct ixgbe_5tuple_filter *filter;
5316         int ret;
5317
5318         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5319                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5320                 return -EINVAL;
5321         }
5322
5323         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5324         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5325         if (ret < 0)
5326                 return ret;
5327
5328         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5329                                          &filter_5tuple);
5330         if (filter != NULL && add) {
5331                 PMD_DRV_LOG(ERR, "filter exists.");
5332                 return -EEXIST;
5333         }
5334         if (filter == NULL && !add) {
5335                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5336                 return -ENOENT;
5337         }
5338
5339         if (add) {
5340                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5341                                 sizeof(struct ixgbe_5tuple_filter), 0);
5342                 if (filter == NULL)
5343                         return -ENOMEM;
5344                 (void)rte_memcpy(&filter->filter_info,
5345                                  &filter_5tuple,
5346                                  sizeof(struct ixgbe_5tuple_filter_info));
5347                 filter->queue = ntuple_filter->queue;
5348                 ret = ixgbe_add_5tuple_filter(dev, filter);
5349                 if (ret < 0) {
5350                         rte_free(filter);
5351                         return ret;
5352                 }
5353         } else
5354                 ixgbe_remove_5tuple_filter(dev, filter);
5355
5356         return 0;
5357 }
5358
5359 /*
5360  * get a ntuple filter
5361  *
5362  * @param
5363  * dev: Pointer to struct rte_eth_dev.
5364  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5365  *
5366  * @return
5367  *    - On success, zero.
5368  *    - On failure, a negative value.
5369  */
5370 static int
5371 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5372                         struct rte_eth_ntuple_filter *ntuple_filter)
5373 {
5374         struct ixgbe_filter_info *filter_info =
5375                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5376         struct ixgbe_5tuple_filter_info filter_5tuple;
5377         struct ixgbe_5tuple_filter *filter;
5378         int ret;
5379
5380         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5381                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5382                 return -EINVAL;
5383         }
5384
5385         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5386         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5387         if (ret < 0)
5388                 return ret;
5389
5390         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5391                                          &filter_5tuple);
5392         if (filter == NULL) {
5393                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5394                 return -ENOENT;
5395         }
5396         ntuple_filter->queue = filter->queue;
5397         return 0;
5398 }
5399
5400 /*
5401  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5402  * @dev: pointer to rte_eth_dev structure
5403  * @filter_op:operation will be taken.
5404  * @arg: a pointer to specific structure corresponding to the filter_op
5405  *
5406  * @return
5407  *    - On success, zero.
5408  *    - On failure, a negative value.
5409  */
5410 static int
5411 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5412                                 enum rte_filter_op filter_op,
5413                                 void *arg)
5414 {
5415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5416         int ret;
5417
5418         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5419
5420         if (filter_op == RTE_ETH_FILTER_NOP)
5421                 return 0;
5422
5423         if (arg == NULL) {
5424                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5425                             filter_op);
5426                 return -EINVAL;
5427         }
5428
5429         switch (filter_op) {
5430         case RTE_ETH_FILTER_ADD:
5431                 ret = ixgbe_add_del_ntuple_filter(dev,
5432                         (struct rte_eth_ntuple_filter *)arg,
5433                         TRUE);
5434                 break;
5435         case RTE_ETH_FILTER_DELETE:
5436                 ret = ixgbe_add_del_ntuple_filter(dev,
5437                         (struct rte_eth_ntuple_filter *)arg,
5438                         FALSE);
5439                 break;
5440         case RTE_ETH_FILTER_GET:
5441                 ret = ixgbe_get_ntuple_filter(dev,
5442                         (struct rte_eth_ntuple_filter *)arg);
5443                 break;
5444         default:
5445                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5446                 ret = -EINVAL;
5447                 break;
5448         }
5449         return ret;
5450 }
5451
5452 static inline int
5453 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5454                         uint16_t ethertype)
5455 {
5456         int i;
5457
5458         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5459                 if (filter_info->ethertype_filters[i] == ethertype &&
5460                     (filter_info->ethertype_mask & (1 << i)))
5461                         return i;
5462         }
5463         return -1;
5464 }
5465
5466 static inline int
5467 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5468                         uint16_t ethertype)
5469 {
5470         int i;
5471
5472         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5473                 if (!(filter_info->ethertype_mask & (1 << i))) {
5474                         filter_info->ethertype_mask |= 1 << i;
5475                         filter_info->ethertype_filters[i] = ethertype;
5476                         return i;
5477                 }
5478         }
5479         return -1;
5480 }
5481
5482 static inline int
5483 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5484                         uint8_t idx)
5485 {
5486         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5487                 return -1;
5488         filter_info->ethertype_mask &= ~(1 << idx);
5489         filter_info->ethertype_filters[idx] = 0;
5490         return idx;
5491 }
5492
5493 static int
5494 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5495                         struct rte_eth_ethertype_filter *filter,
5496                         bool add)
5497 {
5498         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5499         struct ixgbe_filter_info *filter_info =
5500                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5501         uint32_t etqf = 0;
5502         uint32_t etqs = 0;
5503         int ret;
5504
5505         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5506                 return -EINVAL;
5507
5508         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5509                 filter->ether_type == ETHER_TYPE_IPv6) {
5510                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5511                         " ethertype filter.", filter->ether_type);
5512                 return -EINVAL;
5513         }
5514
5515         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5516                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5517                 return -EINVAL;
5518         }
5519         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5520                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5521                 return -EINVAL;
5522         }
5523
5524         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5525         if (ret >= 0 && add) {
5526                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5527                             filter->ether_type);
5528                 return -EEXIST;
5529         }
5530         if (ret < 0 && !add) {
5531                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5532                             filter->ether_type);
5533                 return -ENOENT;
5534         }
5535
5536         if (add) {
5537                 ret = ixgbe_ethertype_filter_insert(filter_info,
5538                         filter->ether_type);
5539                 if (ret < 0) {
5540                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5541                         return -ENOSYS;
5542                 }
5543                 etqf = IXGBE_ETQF_FILTER_EN;
5544                 etqf |= (uint32_t)filter->ether_type;
5545                 etqs |= (uint32_t)((filter->queue <<
5546                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5547                                     IXGBE_ETQS_RX_QUEUE);
5548                 etqs |= IXGBE_ETQS_QUEUE_EN;
5549         } else {
5550                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5551                 if (ret < 0)
5552                         return -ENOSYS;
5553         }
5554         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5555         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5556         IXGBE_WRITE_FLUSH(hw);
5557
5558         return 0;
5559 }
5560
5561 static int
5562 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5563                         struct rte_eth_ethertype_filter *filter)
5564 {
5565         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5566         struct ixgbe_filter_info *filter_info =
5567                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5568         uint32_t etqf, etqs;
5569         int ret;
5570
5571         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5572         if (ret < 0) {
5573                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5574                             filter->ether_type);
5575                 return -ENOENT;
5576         }
5577
5578         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5579         if (etqf & IXGBE_ETQF_FILTER_EN) {
5580                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5581                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5582                 filter->flags = 0;
5583                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5584                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5585                 return 0;
5586         }
5587         return -ENOENT;
5588 }
5589
5590 /*
5591  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5592  * @dev: pointer to rte_eth_dev structure
5593  * @filter_op:operation will be taken.
5594  * @arg: a pointer to specific structure corresponding to the filter_op
5595  */
5596 static int
5597 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5598                                 enum rte_filter_op filter_op,
5599                                 void *arg)
5600 {
5601         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5602         int ret;
5603
5604         MAC_TYPE_FILTER_SUP(hw->mac.type);
5605
5606         if (filter_op == RTE_ETH_FILTER_NOP)
5607                 return 0;
5608
5609         if (arg == NULL) {
5610                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5611                             filter_op);
5612                 return -EINVAL;
5613         }
5614
5615         switch (filter_op) {
5616         case RTE_ETH_FILTER_ADD:
5617                 ret = ixgbe_add_del_ethertype_filter(dev,
5618                         (struct rte_eth_ethertype_filter *)arg,
5619                         TRUE);
5620                 break;
5621         case RTE_ETH_FILTER_DELETE:
5622                 ret = ixgbe_add_del_ethertype_filter(dev,
5623                         (struct rte_eth_ethertype_filter *)arg,
5624                         FALSE);
5625                 break;
5626         case RTE_ETH_FILTER_GET:
5627                 ret = ixgbe_get_ethertype_filter(dev,
5628                         (struct rte_eth_ethertype_filter *)arg);
5629                 break;
5630         default:
5631                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5632                 ret = -EINVAL;
5633                 break;
5634         }
5635         return ret;
5636 }
5637
5638 static int
5639 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5640                      enum rte_filter_type filter_type,
5641                      enum rte_filter_op filter_op,
5642                      void *arg)
5643 {
5644         int ret = -EINVAL;
5645
5646         switch (filter_type) {
5647         case RTE_ETH_FILTER_NTUPLE:
5648                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5649                 break;
5650         case RTE_ETH_FILTER_ETHERTYPE:
5651                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5652                 break;
5653         case RTE_ETH_FILTER_SYN:
5654                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5655                 break;
5656         case RTE_ETH_FILTER_FDIR:
5657                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5658                 break;
5659         case RTE_ETH_FILTER_L2_TUNNEL:
5660                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5661                 break;
5662         default:
5663                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5664                                                         filter_type);
5665                 break;
5666         }
5667
5668         return ret;
5669 }
5670
5671 static u8 *
5672 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5673                         u8 **mc_addr_ptr, u32 *vmdq)
5674 {
5675         u8 *mc_addr;
5676
5677         *vmdq = 0;
5678         mc_addr = *mc_addr_ptr;
5679         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5680         return mc_addr;
5681 }
5682
5683 static int
5684 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5685                           struct ether_addr *mc_addr_set,
5686                           uint32_t nb_mc_addr)
5687 {
5688         struct ixgbe_hw *hw;
5689         u8 *mc_addr_list;
5690
5691         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5692         mc_addr_list = (u8 *)mc_addr_set;
5693         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5694                                          ixgbe_dev_addr_list_itr, TRUE);
5695 }
5696
5697 static uint64_t
5698 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5699 {
5700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5701         uint64_t systime_cycles;
5702
5703         switch (hw->mac.type) {
5704         case ixgbe_mac_X550:
5705                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5706                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5707                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5708                                 * NSEC_PER_SEC;
5709                 break;
5710         default:
5711                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5712                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5713                                 << 32;
5714         }
5715
5716         return systime_cycles;
5717 }
5718
5719 static uint64_t
5720 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5721 {
5722         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5723         uint64_t rx_tstamp_cycles;
5724
5725         switch (hw->mac.type) {
5726         case ixgbe_mac_X550:
5727                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5728                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5729                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5730                                 * NSEC_PER_SEC;
5731                 break;
5732         default:
5733                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5734                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5735                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5736                                 << 32;
5737         }
5738
5739         return rx_tstamp_cycles;
5740 }
5741
5742 static uint64_t
5743 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5744 {
5745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746         uint64_t tx_tstamp_cycles;
5747
5748         switch (hw->mac.type) {
5749         case ixgbe_mac_X550:
5750                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5751                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5752                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5753                                 * NSEC_PER_SEC;
5754                 break;
5755         default:
5756                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5757                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5758                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5759                                 << 32;
5760         }
5761
5762         return tx_tstamp_cycles;
5763 }
5764
5765 static void
5766 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5767 {
5768         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5769         struct ixgbe_adapter *adapter =
5770                 (struct ixgbe_adapter *)dev->data->dev_private;
5771         struct rte_eth_link link;
5772         uint32_t incval = 0;
5773         uint32_t shift = 0;
5774
5775         /* Get current link speed. */
5776         memset(&link, 0, sizeof(link));
5777         ixgbe_dev_link_update(dev, 1);
5778         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5779
5780         switch (link.link_speed) {
5781         case ETH_LINK_SPEED_100:
5782                 incval = IXGBE_INCVAL_100;
5783                 shift = IXGBE_INCVAL_SHIFT_100;
5784                 break;
5785         case ETH_LINK_SPEED_1000:
5786                 incval = IXGBE_INCVAL_1GB;
5787                 shift = IXGBE_INCVAL_SHIFT_1GB;
5788                 break;
5789         case ETH_LINK_SPEED_10000:
5790         default:
5791                 incval = IXGBE_INCVAL_10GB;
5792                 shift = IXGBE_INCVAL_SHIFT_10GB;
5793                 break;
5794         }
5795
5796         switch (hw->mac.type) {
5797         case ixgbe_mac_X550:
5798                 /* Independent of link speed. */
5799                 incval = 1;
5800                 /* Cycles read will be interpreted as ns. */
5801                 shift = 0;
5802                 /* Fall-through */
5803         case ixgbe_mac_X540:
5804                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5805                 break;
5806         case ixgbe_mac_82599EB:
5807                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5808                 shift -= IXGBE_INCVAL_SHIFT_82599;
5809                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5810                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5811                 break;
5812         default:
5813                 /* Not supported. */
5814                 return;
5815         }
5816
5817         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5818         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5819         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5820
5821         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5822         adapter->systime_tc.cc_shift = shift;
5823         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5824
5825         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5826         adapter->rx_tstamp_tc.cc_shift = shift;
5827         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5828
5829         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5830         adapter->tx_tstamp_tc.cc_shift = shift;
5831         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5832 }
5833
5834 static int
5835 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5836 {
5837         struct ixgbe_adapter *adapter =
5838                         (struct ixgbe_adapter *)dev->data->dev_private;
5839
5840         adapter->systime_tc.nsec += delta;
5841         adapter->rx_tstamp_tc.nsec += delta;
5842         adapter->tx_tstamp_tc.nsec += delta;
5843
5844         return 0;
5845 }
5846
5847 static int
5848 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5849 {
5850         uint64_t ns;
5851         struct ixgbe_adapter *adapter =
5852                         (struct ixgbe_adapter *)dev->data->dev_private;
5853
5854         ns = rte_timespec_to_ns(ts);
5855         /* Set the timecounters to a new value. */
5856         adapter->systime_tc.nsec = ns;
5857         adapter->rx_tstamp_tc.nsec = ns;
5858         adapter->tx_tstamp_tc.nsec = ns;
5859
5860         return 0;
5861 }
5862
5863 static int
5864 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5865 {
5866         uint64_t ns, systime_cycles;
5867         struct ixgbe_adapter *adapter =
5868                         (struct ixgbe_adapter *)dev->data->dev_private;
5869
5870         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5871         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5872         *ts = rte_ns_to_timespec(ns);
5873
5874         return 0;
5875 }
5876
5877 static int
5878 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5879 {
5880         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5881         uint32_t tsync_ctl;
5882         uint32_t tsauxc;
5883
5884         /* Stop the timesync system time. */
5885         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5886         /* Reset the timesync system time value. */
5887         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5888         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5889
5890         /* Enable system time for platforms where it isn't on by default. */
5891         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5892         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5893         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5894
5895         ixgbe_start_timecounters(dev);
5896
5897         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5898         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5899                         (ETHER_TYPE_1588 |
5900                          IXGBE_ETQF_FILTER_EN |
5901                          IXGBE_ETQF_1588));
5902
5903         /* Enable timestamping of received PTP packets. */
5904         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5905         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5906         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5907
5908         /* Enable timestamping of transmitted PTP packets. */
5909         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5910         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5911         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5912
5913         IXGBE_WRITE_FLUSH(hw);
5914
5915         return 0;
5916 }
5917
5918 static int
5919 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5920 {
5921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5922         uint32_t tsync_ctl;
5923
5924         /* Disable timestamping of transmitted PTP packets. */
5925         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5926         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5927         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5928
5929         /* Disable timestamping of received PTP packets. */
5930         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5931         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5932         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5933
5934         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5935         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5936
5937         /* Stop incrementating the System Time registers. */
5938         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5939
5940         return 0;
5941 }
5942
5943 static int
5944 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5945                                  struct timespec *timestamp,
5946                                  uint32_t flags __rte_unused)
5947 {
5948         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5949         struct ixgbe_adapter *adapter =
5950                 (struct ixgbe_adapter *)dev->data->dev_private;
5951         uint32_t tsync_rxctl;
5952         uint64_t rx_tstamp_cycles;
5953         uint64_t ns;
5954
5955         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5956         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5957                 return -EINVAL;
5958
5959         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
5960         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5961         *timestamp = rte_ns_to_timespec(ns);
5962
5963         return  0;
5964 }
5965
5966 static int
5967 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5968                                  struct timespec *timestamp)
5969 {
5970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5971         struct ixgbe_adapter *adapter =
5972                 (struct ixgbe_adapter *)dev->data->dev_private;
5973         uint32_t tsync_txctl;
5974         uint64_t tx_tstamp_cycles;
5975         uint64_t ns;
5976
5977         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5978         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5979                 return -EINVAL;
5980
5981         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
5982         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5983         *timestamp = rte_ns_to_timespec(ns);
5984
5985         return 0;
5986 }
5987
5988 static int
5989 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5990 {
5991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5992         int count = 0;
5993         int g_ind = 0;
5994         const struct reg_info *reg_group;
5995         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5996                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5997
5998         while ((reg_group = reg_set[g_ind++]))
5999                 count += ixgbe_regs_group_count(reg_group);
6000
6001         return count;
6002 }
6003
6004 static int
6005 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6006 {
6007         int count = 0;
6008         int g_ind = 0;
6009         const struct reg_info *reg_group;
6010
6011         while ((reg_group = ixgbevf_regs[g_ind++]))
6012                 count += ixgbe_regs_group_count(reg_group);
6013
6014         return count;
6015 }
6016
6017 static int
6018 ixgbe_get_regs(struct rte_eth_dev *dev,
6019               struct rte_dev_reg_info *regs)
6020 {
6021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6022         uint32_t *data = regs->data;
6023         int g_ind = 0;
6024         int count = 0;
6025         const struct reg_info *reg_group;
6026         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6027                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6028
6029         /* Support only full register dump */
6030         if ((regs->length == 0) ||
6031             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6032                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6033                         hw->device_id;
6034                 while ((reg_group = reg_set[g_ind++]))
6035                         count += ixgbe_read_regs_group(dev, &data[count],
6036                                 reg_group);
6037                 return 0;
6038         }
6039
6040         return -ENOTSUP;
6041 }
6042
6043 static int
6044 ixgbevf_get_regs(struct rte_eth_dev *dev,
6045                 struct rte_dev_reg_info *regs)
6046 {
6047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6048         uint32_t *data = regs->data;
6049         int g_ind = 0;
6050         int count = 0;
6051         const struct reg_info *reg_group;
6052
6053         /* Support only full register dump */
6054         if ((regs->length == 0) ||
6055             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6056                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6057                         hw->device_id;
6058                 while ((reg_group = ixgbevf_regs[g_ind++]))
6059                         count += ixgbe_read_regs_group(dev, &data[count],
6060                                                       reg_group);
6061                 return 0;
6062         }
6063
6064         return -ENOTSUP;
6065 }
6066
6067 static int
6068 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6069 {
6070         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6071
6072         /* Return unit is byte count */
6073         return hw->eeprom.word_size * 2;
6074 }
6075
6076 static int
6077 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6078                 struct rte_dev_eeprom_info *in_eeprom)
6079 {
6080         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6081         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6082         uint16_t *data = in_eeprom->data;
6083         int first, length;
6084
6085         first = in_eeprom->offset >> 1;
6086         length = in_eeprom->length >> 1;
6087         if ((first > hw->eeprom.word_size) ||
6088             ((first + length) > hw->eeprom.word_size))
6089                 return -EINVAL;
6090
6091         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6092
6093         return eeprom->ops.read_buffer(hw, first, length, data);
6094 }
6095
6096 static int
6097 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6098                 struct rte_dev_eeprom_info *in_eeprom)
6099 {
6100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6101         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6102         uint16_t *data = in_eeprom->data;
6103         int first, length;
6104
6105         first = in_eeprom->offset >> 1;
6106         length = in_eeprom->length >> 1;
6107         if ((first > hw->eeprom.word_size) ||
6108             ((first + length) > hw->eeprom.word_size))
6109                 return -EINVAL;
6110
6111         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6112
6113         return eeprom->ops.write_buffer(hw,  first, length, data);
6114 }
6115
6116 uint16_t
6117 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6118         switch (mac_type) {
6119         case ixgbe_mac_X550:
6120         case ixgbe_mac_X550EM_x:
6121         case ixgbe_mac_X550EM_a:
6122                 return ETH_RSS_RETA_SIZE_512;
6123         case ixgbe_mac_X550_vf:
6124         case ixgbe_mac_X550EM_x_vf:
6125         case ixgbe_mac_X550EM_a_vf:
6126                 return ETH_RSS_RETA_SIZE_64;
6127         default:
6128                 return ETH_RSS_RETA_SIZE_128;
6129         }
6130 }
6131
6132 uint32_t
6133 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6134         switch (mac_type) {
6135         case ixgbe_mac_X550:
6136         case ixgbe_mac_X550EM_x:
6137         case ixgbe_mac_X550EM_a:
6138                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6139                         return IXGBE_RETA(reta_idx >> 2);
6140                 else
6141                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6142         case ixgbe_mac_X550_vf:
6143         case ixgbe_mac_X550EM_x_vf:
6144         case ixgbe_mac_X550EM_a_vf:
6145                 return IXGBE_VFRETA(reta_idx >> 2);
6146         default:
6147                 return IXGBE_RETA(reta_idx >> 2);
6148         }
6149 }
6150
6151 uint32_t
6152 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6153         switch (mac_type) {
6154         case ixgbe_mac_X550_vf:
6155         case ixgbe_mac_X550EM_x_vf:
6156         case ixgbe_mac_X550EM_a_vf:
6157                 return IXGBE_VFMRQC;
6158         default:
6159                 return IXGBE_MRQC;
6160         }
6161 }
6162
6163 uint32_t
6164 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6165         switch (mac_type) {
6166         case ixgbe_mac_X550_vf:
6167         case ixgbe_mac_X550EM_x_vf:
6168         case ixgbe_mac_X550EM_a_vf:
6169                 return IXGBE_VFRSSRK(i);
6170         default:
6171                 return IXGBE_RSSRK(i);
6172         }
6173 }
6174
6175 bool
6176 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6177         switch (mac_type) {
6178         case ixgbe_mac_82599_vf:
6179         case ixgbe_mac_X540_vf:
6180                 return 0;
6181         default:
6182                 return 1;
6183         }
6184 }
6185
6186 static int
6187 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6188                         struct rte_eth_dcb_info *dcb_info)
6189 {
6190         struct ixgbe_dcb_config *dcb_config =
6191                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6192         struct ixgbe_dcb_tc_config *tc;
6193         uint8_t i, j;
6194
6195         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6196                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6197         else
6198                 dcb_info->nb_tcs = 1;
6199
6200         if (dcb_config->vt_mode) { /* vt is enabled*/
6201                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6202                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6203                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6204                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6205                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6206                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6207                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6208                                                 i * dcb_info->nb_tcs + j;
6209                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6210                                 dcb_info->tc_queue.tc_txq[i][j].base =
6211                                                 i * dcb_info->nb_tcs + j;
6212                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6213                         }
6214                 }
6215         } else { /* vt is disabled*/
6216                 struct rte_eth_dcb_rx_conf *rx_conf =
6217                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6218                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6219                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6220                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6221                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6222                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6223                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6224                         }
6225                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6226                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6227                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6228                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6229                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6230                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6231                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6232                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6233                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6234                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6235                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6236                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6237                         }
6238                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6239                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6240                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6241                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6242                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6243                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6244                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6245                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6246                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6247                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6248                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6249                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6250                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6251                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6252                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6253                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6254                 }
6255         }
6256         for (i = 0; i < dcb_info->nb_tcs; i++) {
6257                 tc = &dcb_config->tc_config[i];
6258                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6259         }
6260         return 0;
6261 }
6262
6263 /* Update e-tag ether type */
6264 static int
6265 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6266                             uint16_t ether_type)
6267 {
6268         uint32_t etag_etype;
6269
6270         if (hw->mac.type != ixgbe_mac_X550 &&
6271             hw->mac.type != ixgbe_mac_X550EM_x) {
6272                 return -ENOTSUP;
6273         }
6274
6275         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6276         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6277         etag_etype |= ether_type;
6278         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6279         IXGBE_WRITE_FLUSH(hw);
6280
6281         return 0;
6282 }
6283
6284 /* Config l2 tunnel ether type */
6285 static int
6286 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6287                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6288 {
6289         int ret = 0;
6290         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6291
6292         if (l2_tunnel == NULL)
6293                 return -EINVAL;
6294
6295         switch (l2_tunnel->l2_tunnel_type) {
6296         case RTE_L2_TUNNEL_TYPE_E_TAG:
6297                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6298                 break;
6299         default:
6300                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6301                 ret = -EINVAL;
6302                 break;
6303         }
6304
6305         return ret;
6306 }
6307
6308 /* Enable e-tag tunnel */
6309 static int
6310 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6311 {
6312         uint32_t etag_etype;
6313
6314         if (hw->mac.type != ixgbe_mac_X550 &&
6315             hw->mac.type != ixgbe_mac_X550EM_x) {
6316                 return -ENOTSUP;
6317         }
6318
6319         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6320         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6321         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6322         IXGBE_WRITE_FLUSH(hw);
6323
6324         return 0;
6325 }
6326
6327 /* Enable l2 tunnel */
6328 static int
6329 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6330                            enum rte_eth_tunnel_type l2_tunnel_type)
6331 {
6332         int ret = 0;
6333         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6334
6335         switch (l2_tunnel_type) {
6336         case RTE_L2_TUNNEL_TYPE_E_TAG:
6337                 ret = ixgbe_e_tag_enable(hw);
6338                 break;
6339         default:
6340                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6341                 ret = -EINVAL;
6342                 break;
6343         }
6344
6345         return ret;
6346 }
6347
6348 /* Disable e-tag tunnel */
6349 static int
6350 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6351 {
6352         uint32_t etag_etype;
6353
6354         if (hw->mac.type != ixgbe_mac_X550 &&
6355             hw->mac.type != ixgbe_mac_X550EM_x) {
6356                 return -ENOTSUP;
6357         }
6358
6359         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6360         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6361         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6362         IXGBE_WRITE_FLUSH(hw);
6363
6364         return 0;
6365 }
6366
6367 /* Disable l2 tunnel */
6368 static int
6369 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6370                             enum rte_eth_tunnel_type l2_tunnel_type)
6371 {
6372         int ret = 0;
6373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6374
6375         switch (l2_tunnel_type) {
6376         case RTE_L2_TUNNEL_TYPE_E_TAG:
6377                 ret = ixgbe_e_tag_disable(hw);
6378                 break;
6379         default:
6380                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6381                 ret = -EINVAL;
6382                 break;
6383         }
6384
6385         return ret;
6386 }
6387
6388 static int
6389 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6390                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6391 {
6392         int ret = 0;
6393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6394         uint32_t i, rar_entries;
6395         uint32_t rar_low, rar_high;
6396
6397         if (hw->mac.type != ixgbe_mac_X550 &&
6398             hw->mac.type != ixgbe_mac_X550EM_x) {
6399                 return -ENOTSUP;
6400         }
6401
6402         rar_entries = ixgbe_get_num_rx_addrs(hw);
6403
6404         for (i = 1; i < rar_entries; i++) {
6405                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6406                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6407                 if ((rar_high & IXGBE_RAH_AV) &&
6408                     (rar_high & IXGBE_RAH_ADTYPE) &&
6409                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6410                      l2_tunnel->tunnel_id)) {
6411                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6412                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6413
6414                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6415
6416                         return ret;
6417                 }
6418         }
6419
6420         return ret;
6421 }
6422
6423 static int
6424 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6425                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6426 {
6427         int ret = 0;
6428         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6429         uint32_t i, rar_entries;
6430         uint32_t rar_low, rar_high;
6431
6432         if (hw->mac.type != ixgbe_mac_X550 &&
6433             hw->mac.type != ixgbe_mac_X550EM_x) {
6434                 return -ENOTSUP;
6435         }
6436
6437         /* One entry for one tunnel. Try to remove potential existing entry. */
6438         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6439
6440         rar_entries = ixgbe_get_num_rx_addrs(hw);
6441
6442         for (i = 1; i < rar_entries; i++) {
6443                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6444                 if (rar_high & IXGBE_RAH_AV) {
6445                         continue;
6446                 } else {
6447                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6448                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6449                         rar_low = l2_tunnel->tunnel_id;
6450
6451                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6452                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6453
6454                         return ret;
6455                 }
6456         }
6457
6458         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6459                      " Please remove a rule before adding a new one.");
6460         return -EINVAL;
6461 }
6462
6463 /* Add l2 tunnel filter */
6464 static int
6465 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6466                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6467 {
6468         int ret = 0;
6469
6470         switch (l2_tunnel->l2_tunnel_type) {
6471         case RTE_L2_TUNNEL_TYPE_E_TAG:
6472                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6473                 break;
6474         default:
6475                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6476                 ret = -EINVAL;
6477                 break;
6478         }
6479
6480         return ret;
6481 }
6482
6483 /* Delete l2 tunnel filter */
6484 static int
6485 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6486                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6487 {
6488         int ret = 0;
6489
6490         switch (l2_tunnel->l2_tunnel_type) {
6491         case RTE_L2_TUNNEL_TYPE_E_TAG:
6492                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6493                 break;
6494         default:
6495                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6496                 ret = -EINVAL;
6497                 break;
6498         }
6499
6500         return ret;
6501 }
6502
6503 /**
6504  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6505  * @dev: pointer to rte_eth_dev structure
6506  * @filter_op:operation will be taken.
6507  * @arg: a pointer to specific structure corresponding to the filter_op
6508  */
6509 static int
6510 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6511                                   enum rte_filter_op filter_op,
6512                                   void *arg)
6513 {
6514         int ret = 0;
6515
6516         if (filter_op == RTE_ETH_FILTER_NOP)
6517                 return 0;
6518
6519         if (arg == NULL) {
6520                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6521                             filter_op);
6522                 return -EINVAL;
6523         }
6524
6525         switch (filter_op) {
6526         case RTE_ETH_FILTER_ADD:
6527                 ret = ixgbe_dev_l2_tunnel_filter_add
6528                         (dev,
6529                          (struct rte_eth_l2_tunnel_conf *)arg);
6530                 break;
6531         case RTE_ETH_FILTER_DELETE:
6532                 ret = ixgbe_dev_l2_tunnel_filter_del
6533                         (dev,
6534                          (struct rte_eth_l2_tunnel_conf *)arg);
6535                 break;
6536         default:
6537                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6538                 ret = -EINVAL;
6539                 break;
6540         }
6541         return ret;
6542 }
6543
6544 static int
6545 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6546 {
6547         int ret = 0;
6548         uint32_t ctrl;
6549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6550
6551         if (hw->mac.type != ixgbe_mac_X550 &&
6552             hw->mac.type != ixgbe_mac_X550EM_x) {
6553                 return -ENOTSUP;
6554         }
6555
6556         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6557         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6558         if (en)
6559                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6560         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6561
6562         return ret;
6563 }
6564
6565 /* Enable l2 tunnel forwarding */
6566 static int
6567 ixgbe_dev_l2_tunnel_forwarding_enable
6568         (struct rte_eth_dev *dev,
6569          enum rte_eth_tunnel_type l2_tunnel_type)
6570 {
6571         int ret = 0;
6572
6573         switch (l2_tunnel_type) {
6574         case RTE_L2_TUNNEL_TYPE_E_TAG:
6575                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6576                 break;
6577         default:
6578                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6579                 ret = -EINVAL;
6580                 break;
6581         }
6582
6583         return ret;
6584 }
6585
6586 /* Disable l2 tunnel forwarding */
6587 static int
6588 ixgbe_dev_l2_tunnel_forwarding_disable
6589         (struct rte_eth_dev *dev,
6590          enum rte_eth_tunnel_type l2_tunnel_type)
6591 {
6592         int ret = 0;
6593
6594         switch (l2_tunnel_type) {
6595         case RTE_L2_TUNNEL_TYPE_E_TAG:
6596                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6597                 break;
6598         default:
6599                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6600                 ret = -EINVAL;
6601                 break;
6602         }
6603
6604         return ret;
6605 }
6606
6607 static int
6608 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6609                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6610                              bool en)
6611 {
6612         int ret = 0;
6613         uint32_t vmtir, vmvir;
6614         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6615
6616         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6617                 PMD_DRV_LOG(ERR,
6618                             "VF id %u should be less than %u",
6619                             l2_tunnel->vf_id,
6620                             dev->pci_dev->max_vfs);
6621                 return -EINVAL;
6622         }
6623
6624         if (hw->mac.type != ixgbe_mac_X550 &&
6625             hw->mac.type != ixgbe_mac_X550EM_x) {
6626                 return -ENOTSUP;
6627         }
6628
6629         if (en)
6630                 vmtir = l2_tunnel->tunnel_id;
6631         else
6632                 vmtir = 0;
6633
6634         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6635
6636         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6637         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6638         if (en)
6639                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6640         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6641
6642         return ret;
6643 }
6644
6645 /* Enable l2 tunnel tag insertion */
6646 static int
6647 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6648                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6649 {
6650         int ret = 0;
6651
6652         switch (l2_tunnel->l2_tunnel_type) {
6653         case RTE_L2_TUNNEL_TYPE_E_TAG:
6654                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6655                 break;
6656         default:
6657                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6658                 ret = -EINVAL;
6659                 break;
6660         }
6661
6662         return ret;
6663 }
6664
6665 /* Disable l2 tunnel tag insertion */
6666 static int
6667 ixgbe_dev_l2_tunnel_insertion_disable
6668         (struct rte_eth_dev *dev,
6669          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6670 {
6671         int ret = 0;
6672
6673         switch (l2_tunnel->l2_tunnel_type) {
6674         case RTE_L2_TUNNEL_TYPE_E_TAG:
6675                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6676                 break;
6677         default:
6678                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6679                 ret = -EINVAL;
6680                 break;
6681         }
6682
6683         return ret;
6684 }
6685
6686 static int
6687 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6688                              bool en)
6689 {
6690         int ret = 0;
6691         uint32_t qde;
6692         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6693
6694         if (hw->mac.type != ixgbe_mac_X550 &&
6695             hw->mac.type != ixgbe_mac_X550EM_x) {
6696                 return -ENOTSUP;
6697         }
6698
6699         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
6700         if (en)
6701                 qde |= IXGBE_QDE_STRIP_TAG;
6702         else
6703                 qde &= ~IXGBE_QDE_STRIP_TAG;
6704         qde &= ~IXGBE_QDE_READ;
6705         qde |= IXGBE_QDE_WRITE;
6706         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
6707
6708         return ret;
6709 }
6710
6711 /* Enable l2 tunnel tag stripping */
6712 static int
6713 ixgbe_dev_l2_tunnel_stripping_enable
6714         (struct rte_eth_dev *dev,
6715          enum rte_eth_tunnel_type l2_tunnel_type)
6716 {
6717         int ret = 0;
6718
6719         switch (l2_tunnel_type) {
6720         case RTE_L2_TUNNEL_TYPE_E_TAG:
6721                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
6722                 break;
6723         default:
6724                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6725                 ret = -EINVAL;
6726                 break;
6727         }
6728
6729         return ret;
6730 }
6731
6732 /* Disable l2 tunnel tag stripping */
6733 static int
6734 ixgbe_dev_l2_tunnel_stripping_disable
6735         (struct rte_eth_dev *dev,
6736          enum rte_eth_tunnel_type l2_tunnel_type)
6737 {
6738         int ret = 0;
6739
6740         switch (l2_tunnel_type) {
6741         case RTE_L2_TUNNEL_TYPE_E_TAG:
6742                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
6743                 break;
6744         default:
6745                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6746                 ret = -EINVAL;
6747                 break;
6748         }
6749
6750         return ret;
6751 }
6752
6753 /* Enable/disable l2 tunnel offload functions */
6754 static int
6755 ixgbe_dev_l2_tunnel_offload_set
6756         (struct rte_eth_dev *dev,
6757          struct rte_eth_l2_tunnel_conf *l2_tunnel,
6758          uint32_t mask,
6759          uint8_t en)
6760 {
6761         int ret = 0;
6762
6763         if (l2_tunnel == NULL)
6764                 return -EINVAL;
6765
6766         ret = -EINVAL;
6767         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
6768                 if (en)
6769                         ret = ixgbe_dev_l2_tunnel_enable(
6770                                 dev,
6771                                 l2_tunnel->l2_tunnel_type);
6772                 else
6773                         ret = ixgbe_dev_l2_tunnel_disable(
6774                                 dev,
6775                                 l2_tunnel->l2_tunnel_type);
6776         }
6777
6778         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
6779                 if (en)
6780                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
6781                                 dev,
6782                                 l2_tunnel);
6783                 else
6784                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
6785                                 dev,
6786                                 l2_tunnel);
6787         }
6788
6789         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
6790                 if (en)
6791                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
6792                                 dev,
6793                                 l2_tunnel->l2_tunnel_type);
6794                 else
6795                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
6796                                 dev,
6797                                 l2_tunnel->l2_tunnel_type);
6798         }
6799
6800         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
6801                 if (en)
6802                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
6803                                 dev,
6804                                 l2_tunnel->l2_tunnel_type);
6805                 else
6806                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
6807                                 dev,
6808                                 l2_tunnel->l2_tunnel_type);
6809         }
6810
6811         return ret;
6812 }
6813
6814 static int
6815 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
6816                         uint16_t port)
6817 {
6818         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
6819         IXGBE_WRITE_FLUSH(hw);
6820
6821         return 0;
6822 }
6823
6824 /* There's only one register for VxLAN UDP port.
6825  * So, we cannot add several ports. Will update it.
6826  */
6827 static int
6828 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
6829                      uint16_t port)
6830 {
6831         if (port == 0) {
6832                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
6833                 return -EINVAL;
6834         }
6835
6836         return ixgbe_update_vxlan_port(hw, port);
6837 }
6838
6839 /* We cannot delete the VxLAN port. For there's a register for VxLAN
6840  * UDP port, it must have a value.
6841  * So, will reset it to the original value 0.
6842  */
6843 static int
6844 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
6845                      uint16_t port)
6846 {
6847         uint16_t cur_port;
6848
6849         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
6850
6851         if (cur_port != port) {
6852                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
6853                 return -EINVAL;
6854         }
6855
6856         return ixgbe_update_vxlan_port(hw, 0);
6857 }
6858
6859 /* Add UDP tunneling port */
6860 static int
6861 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6862                               struct rte_eth_udp_tunnel *udp_tunnel)
6863 {
6864         int ret = 0;
6865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6866
6867         if (hw->mac.type != ixgbe_mac_X550 &&
6868             hw->mac.type != ixgbe_mac_X550EM_x) {
6869                 return -ENOTSUP;
6870         }
6871
6872         if (udp_tunnel == NULL)
6873                 return -EINVAL;
6874
6875         switch (udp_tunnel->prot_type) {
6876         case RTE_TUNNEL_TYPE_VXLAN:
6877                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
6878                 break;
6879
6880         case RTE_TUNNEL_TYPE_GENEVE:
6881         case RTE_TUNNEL_TYPE_TEREDO:
6882                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6883                 ret = -EINVAL;
6884                 break;
6885
6886         default:
6887                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6888                 ret = -EINVAL;
6889                 break;
6890         }
6891
6892         return ret;
6893 }
6894
6895 /* Remove UDP tunneling port */
6896 static int
6897 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6898                               struct rte_eth_udp_tunnel *udp_tunnel)
6899 {
6900         int ret = 0;
6901         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6902
6903         if (hw->mac.type != ixgbe_mac_X550 &&
6904             hw->mac.type != ixgbe_mac_X550EM_x) {
6905                 return -ENOTSUP;
6906         }
6907
6908         if (udp_tunnel == NULL)
6909                 return -EINVAL;
6910
6911         switch (udp_tunnel->prot_type) {
6912         case RTE_TUNNEL_TYPE_VXLAN:
6913                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
6914                 break;
6915         case RTE_TUNNEL_TYPE_GENEVE:
6916         case RTE_TUNNEL_TYPE_TEREDO:
6917                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6918                 ret = -EINVAL;
6919                 break;
6920         default:
6921                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6922                 ret = -EINVAL;
6923                 break;
6924         }
6925
6926         return ret;
6927 }
6928
6929 static struct rte_driver rte_ixgbe_driver = {
6930         .type = PMD_PDEV,
6931         .init = rte_ixgbe_pmd_init,
6932 };
6933
6934 static struct rte_driver rte_ixgbevf_driver = {
6935         .type = PMD_PDEV,
6936         .init = rte_ixgbevf_pmd_init,
6937 };
6938
6939 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6940 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);