drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 /* Additional timesync values. */
 104 #define NSEC_PER_SEC             1000000000L
 105 #define IXGBE_INCVAL_10GB        0x66666666
 106 #define IXGBE_INCVAL_1GB         0x40000000
 107 #define IXGBE_INCVAL_100         0x50000000
 108 #define IXGBE_INCVAL_SHIFT_10GB  28
 109 #define IXGBE_INCVAL_SHIFT_1GB   24
 110 #define IXGBE_INCVAL_SHIFT_100   21
 111 #define IXGBE_INCVAL_SHIFT_82599 7
 112 #define IXGBE_INCPER_SHIFT_82599 24
 113
 114 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 117 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 118 #define DEFAULT_ETAG_ETYPE                     0x893f
 119 #define IXGBE_ETAG_ETYPE                       0x00005084
 120 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 121 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 122 #define IXGBE_RAH_ADTYPE                       0x40000000
 123 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 124 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 125 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 126 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 127 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 128 #define IXGBE_VTEICR_MASK                      0x07
 129
 130 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 131 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 132
 133 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 134 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 135 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 136 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 140 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 141 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 152                                 int wait_to_complete);
 153 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 154                                 struct rte_eth_stats *stats);
 155 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_xstat *xstats, unsigned n);
 157 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 158                                   struct rte_eth_xstat *xstats, unsigned n);
 159 static int
 160 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 161                 uint64_t *values, unsigned int n);
 162 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 163 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 164 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 165         struct rte_eth_xstat_name *xstats_names,
 166         unsigned int size);
 167 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 168         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 169 static int ixgbe_dev_xstats_get_names_by_id(
 170         struct rte_eth_dev *dev,
 171         struct rte_eth_xstat_name *xstats_names,
 172         const uint64_t *ids,
 173         unsigned int limit);
 174 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 175                                              uint16_t queue_id,
 176                                              uint8_t stat_idx,
 177                                              uint8_t is_rx);
 178 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 179                                  size_t fw_size);
 180 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 181                                struct rte_eth_dev_info *dev_info);
 182 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 183 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 184                                  struct rte_eth_dev_info *dev_info);
 185 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 186
 187 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 188                 uint16_t vlan_id, int on);
 189 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 190                                enum rte_vlan_type vlan_type,
 191                                uint16_t tpid_id);
 192 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 193                 uint16_t queue, bool on);
 194 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 195                 int on);
 196 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 197 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 198 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 199 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 200 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 201
 202 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 204 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_fc_conf *fc_conf);
 206 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 209                 struct rte_eth_pfc_conf *pfc_conf);
 210 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 211                         struct rte_eth_rss_reta_entry64 *reta_conf,
 212                         uint16_t reta_size);
 213 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 214                         struct rte_eth_rss_reta_entry64 *reta_conf,
 215                         uint16_t reta_size);
 216 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 218 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 220 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 222                                       struct rte_intr_handle *handle);
 223 static void ixgbe_dev_interrupt_handler(void *param);
 224 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 226                          uint32_t index, uint32_t pool);
 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 229                                            struct ether_addr *mac_addr);
 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 231 static bool is_device_supported(struct rte_eth_dev *dev,
 232                                 struct rte_pci_driver *drv);
 233
 234 /* For Virtual Function support */
 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 237 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 238 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 240                                    int wait_to_complete);
 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 243 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 244 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 245 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 247                 struct rte_eth_stats *stats);
 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 250                 uint16_t vlan_id, int on);
 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                 uint16_t queue, int on);
 253 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 254 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 255 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 256                                             uint16_t queue_id);
 257 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 258                                              uint16_t queue_id);
 259 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 260                                  uint8_t queue, uint8_t msix_vector);
 261 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 262 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 264
 265 /* For Eth VMDQ APIs support */
 266 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 267                 ether_addr * mac_addr, uint8_t on);
 268 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 269 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 270                 struct rte_eth_mirror_conf *mirror_conf,
 271                 uint8_t rule_id, uint8_t on);
 272 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 273                 uint8_t rule_id);
 274 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 275                                           uint16_t queue_id);
 276 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 277                                            uint16_t queue_id);
 278 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 279                                uint8_t queue, uint8_t msix_vector);
 280 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 281
 282 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 283                                 struct ether_addr *mac_addr,
 284                                 uint32_t index, uint32_t pool);
 285 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 286 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 287                                              struct ether_addr *mac_addr);
 288 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 289                         struct rte_eth_syn_filter *filter);
 290 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 291                         enum rte_filter_op filter_op,
 292                         void *arg);
 293 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 294                         struct ixgbe_5tuple_filter *filter);
 295 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 298                                 enum rte_filter_op filter_op,
 299                                 void *arg);
 300 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 301                         struct rte_eth_ntuple_filter *filter);
 302 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 303                                 enum rte_filter_op filter_op,
 304                                 void *arg);
 305 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 306                         struct rte_eth_ethertype_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 329                                  struct rte_eth_dev_module_info *modinfo);
 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 331                                    struct rte_dev_eeprom_info *info);
 332
 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 335                                 struct rte_dev_reg_info *regs);
 336
 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp,
 341                                             uint32_t flags);
 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp);
 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 346                                    struct timespec *timestamp);
 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 348                                    const struct timespec *timestamp);
 349 static void ixgbevf_dev_interrupt_handler(void *param);
 350
 351 static int ixgbe_dev_l2_tunnel_eth_type_conf
 352         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 353 static int ixgbe_dev_l2_tunnel_offload_set
 354         (struct rte_eth_dev *dev,
 355          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 356          uint32_t mask,
 357          uint8_t en);
 358 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 359                                              enum rte_filter_op filter_op,
 360                                              void *arg);
 361
 362 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 363                                          struct rte_eth_udp_tunnel *udp_tunnel);
 364 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 365                                          struct rte_eth_udp_tunnel *udp_tunnel);
 366 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 367 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 368
 369 /*
 370  * Define VF Stats MACRO for Non "cleared on read" register
 371  */
 372 #define UPDATE_VF_STAT(reg, last, cur)                          \
 373 {                                                               \
 374         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 375         cur += (latest - last) & UINT_MAX;                      \
 376         last = latest;                                          \
 377 }
 378
 379 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 380 {                                                                \
 381         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 382         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 383         u64 latest = ((new_msb << 32) | new_lsb);                \
 384         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 385         last = latest;                                           \
 386 }
 387
 388 #define IXGBE_SET_HWSTRIP(h, q) do {\
 389                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 390                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 391                 (h)->bitmap[idx] |= 1 << bit;\
 392         } while (0)
 393
 394 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 395                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 396                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 397                 (h)->bitmap[idx] &= ~(1 << bit);\
 398         } while (0)
 399
 400 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 401                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 402                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 403                 (r) = (h)->bitmap[idx] >> bit & 1;\
 404         } while (0)
 405
 406 int ixgbe_logtype_init;
 407 int ixgbe_logtype_driver;
 408
 409 /*
 410  * The set of PCI devices this driver supports
 411  */
 412 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 463 #endif
 464         { .vendor_id = 0, /* sentinel */ },
 465 };
 466
 467 /*
 468  * The set of PCI devices this driver supports (for 82599 VF)
 469  */
 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 static const struct rte_eth_desc_lim rx_desc_lim = {
 485         .nb_max = IXGBE_MAX_RING_DESC,
 486         .nb_min = IXGBE_MIN_RING_DESC,
 487         .nb_align = IXGBE_RXD_ALIGN,
 488 };
 489
 490 static const struct rte_eth_desc_lim tx_desc_lim = {
 491         .nb_max = IXGBE_MAX_RING_DESC,
 492         .nb_min = IXGBE_MIN_RING_DESC,
 493         .nb_align = IXGBE_TXD_ALIGN,
 494         .nb_seg_max = IXGBE_TX_MAX_SEG,
 495         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 496 };
 497
 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 499         .dev_configure        = ixgbe_dev_configure,
 500         .dev_start            = ixgbe_dev_start,
 501         .dev_stop             = ixgbe_dev_stop,
 502         .dev_set_link_up    = ixgbe_dev_set_link_up,
 503         .dev_set_link_down  = ixgbe_dev_set_link_down,
 504         .dev_close            = ixgbe_dev_close,
 505         .dev_reset            = ixgbe_dev_reset,
 506         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 507         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 508         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 509         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 510         .link_update          = ixgbe_dev_link_update,
 511         .stats_get            = ixgbe_dev_stats_get,
 512         .xstats_get           = ixgbe_dev_xstats_get,
 513         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 514         .stats_reset          = ixgbe_dev_stats_reset,
 515         .xstats_reset         = ixgbe_dev_xstats_reset,
 516         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 517         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 518         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 519         .fw_version_get       = ixgbe_fw_version_get,
 520         .dev_infos_get        = ixgbe_dev_info_get,
 521         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 522         .mtu_set              = ixgbe_dev_mtu_set,
 523         .vlan_filter_set      = ixgbe_vlan_filter_set,
 524         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 525         .vlan_offload_set     = ixgbe_vlan_offload_set,
 526         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 527         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 528         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 529         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 530         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 531         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 532         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 533         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 534         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 535         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 536         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 537         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 538         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 539         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 540         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 541         .dev_led_on           = ixgbe_dev_led_on,
 542         .dev_led_off          = ixgbe_dev_led_off,
 543         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 544         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 545         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 546         .mac_addr_add         = ixgbe_add_rar,
 547         .mac_addr_remove      = ixgbe_remove_rar,
 548         .mac_addr_set         = ixgbe_set_default_mac_addr,
 549         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 550         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 551         .mirror_rule_set      = ixgbe_mirror_rule_set,
 552         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 553         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 554         .reta_update          = ixgbe_dev_rss_reta_update,
 555         .reta_query           = ixgbe_dev_rss_reta_query,
 556         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 557         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 558         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 559         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 560         .rxq_info_get         = ixgbe_rxq_info_get,
 561         .txq_info_get         = ixgbe_txq_info_get,
 562         .timesync_enable      = ixgbe_timesync_enable,
 563         .timesync_disable     = ixgbe_timesync_disable,
 564         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 566         .get_reg              = ixgbe_get_regs,
 567         .get_eeprom_length    = ixgbe_get_eeprom_length,
 568         .get_eeprom           = ixgbe_get_eeprom,
 569         .set_eeprom           = ixgbe_set_eeprom,
 570         .get_module_info      = ixgbe_get_module_info,
 571         .get_module_eeprom    = ixgbe_get_module_eeprom,
 572         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 573         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 574         .timesync_read_time   = ixgbe_timesync_read_time,
 575         .timesync_write_time  = ixgbe_timesync_write_time,
 576         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 577         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 578         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 579         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 580         .tm_ops_get           = ixgbe_tm_ops_get,
 581 };
 582
 583 /*
 584  * dev_ops for virtual function, bare necessities for basic vf
 585  * operation have been implemented
 586  */
 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 588         .dev_configure        = ixgbevf_dev_configure,
 589         .dev_start            = ixgbevf_dev_start,
 590         .dev_stop             = ixgbevf_dev_stop,
 591         .link_update          = ixgbevf_dev_link_update,
 592         .stats_get            = ixgbevf_dev_stats_get,
 593         .xstats_get           = ixgbevf_dev_xstats_get,
 594         .stats_reset          = ixgbevf_dev_stats_reset,
 595         .xstats_reset         = ixgbevf_dev_stats_reset,
 596         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 597         .dev_close            = ixgbevf_dev_close,
 598         .dev_reset            = ixgbevf_dev_reset,
 599         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 600         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 601         .dev_infos_get        = ixgbevf_dev_info_get,
 602         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 603         .mtu_set              = ixgbevf_dev_set_mtu,
 604         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 605         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 606         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 607         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 608         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 609         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 610         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 611         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 612         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 613         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 614         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 615         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 616         .mac_addr_add         = ixgbevf_add_mac_addr,
 617         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 618         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 619         .rxq_info_get         = ixgbe_rxq_info_get,
 620         .txq_info_get         = ixgbe_txq_info_get,
 621         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 622         .get_reg              = ixgbevf_get_regs,
 623         .reta_update          = ixgbe_dev_rss_reta_update,
 624         .reta_query           = ixgbe_dev_rss_reta_query,
 625         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 626         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 627 };
 628
 629 /* store statistics names and its offset in stats structure */
 630 struct rte_ixgbe_xstats_name_off {
 631         char name[RTE_ETH_XSTATS_NAME_SIZE];
 632         unsigned offset;
 633 };
 634
 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 636         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 637         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 638         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 639         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 640         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 641         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 642         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 643         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 644         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 645         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 646         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 647         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 648         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 649         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 650         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 651                 prc1023)},
 652         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1522)},
 654         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 655         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 656         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 657         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 658         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 659         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 660         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 661         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 662         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 663         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 664         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 665         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 666         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 667         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 668         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 669         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 670         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 671                 ptc1023)},
 672         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1522)},
 674         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 675         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 676         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 677         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 678
 679         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 680                 fdirustat_add)},
 681         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_remove)},
 683         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 684                 fdirfstat_fadd)},
 685         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fremove)},
 687         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 688                 fdirmatch)},
 689         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmiss)},
 691
 692         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 693         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 694         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 695                 fclast)},
 696         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 697         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 698         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 699         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 700         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 701                 fcoe_noddp)},
 702         {"rx_fcoe_no_direct_data_placement_ext_buff",
 703                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 704
 705         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 706                 lxontxc)},
 707         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxonrxc)},
 709         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxofftxc)},
 711         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxoffrxc)},
 713         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 714 };
 715
 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 717                            sizeof(rte_ixgbe_stats_strings[0]))
 718
 719 /* MACsec statistics */
 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 721         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 722                 out_pkts_untagged)},
 723         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_encrypted)},
 725         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_protected)},
 727         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 728                 out_octets_encrypted)},
 729         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_protected)},
 731         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 732                 in_pkts_untagged)},
 733         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_badtag)},
 735         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_nosci)},
 737         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_unknownsci)},
 739         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 740                 in_octets_decrypted)},
 741         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_validated)},
 743         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 744                 in_pkts_unchecked)},
 745         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_delayed)},
 747         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_late)},
 749         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_ok)},
 751         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_invalid)},
 753         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_notvalid)},
 755         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_unusedsa)},
 757         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_notusingsa)},
 759 };
 760
 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 762                            sizeof(rte_ixgbe_macsec_strings[0]))
 763
 764 /* Per-queue statistics */
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 766         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 767         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 768         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 769         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 770 };
 771
 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 773                            sizeof(rte_ixgbe_rxq_strings[0]))
 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 777         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 778         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 779         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 780                 pxon2offc)},
 781 };
 782
 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 784                            sizeof(rte_ixgbe_txq_strings[0]))
 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 786
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 788         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 789 };
 790
 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 792                 sizeof(rte_ixgbevf_stats_strings[0]))
 793
 794 /*
 795  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 796  */
 797 static inline int
 798 ixgbe_is_sfp(struct ixgbe_hw *hw)
 799 {
 800         switch (hw->phy.type) {
 801         case ixgbe_phy_sfp_avago:
 802         case ixgbe_phy_sfp_ftl:
 803         case ixgbe_phy_sfp_intel:
 804         case ixgbe_phy_sfp_unknown:
 805         case ixgbe_phy_sfp_passive_tyco:
 806         case ixgbe_phy_sfp_passive_unknown:
 807                 return 1;
 808         default:
 809                 return 0;
 810         }
 811 }
 812
 813 static inline int32_t
 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 815 {
 816         uint32_t ctrl_ext;
 817         int32_t status;
 818
 819         status = ixgbe_reset_hw(hw);
 820
 821         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 822         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 823         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 824         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 825         IXGBE_WRITE_FLUSH(hw);
 826
 827         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 828                 status = IXGBE_SUCCESS;
 829         return status;
 830 }
 831
 832 static inline void
 833 ixgbe_enable_intr(struct rte_eth_dev *dev)
 834 {
 835         struct ixgbe_interrupt *intr =
 836                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 837         struct ixgbe_hw *hw =
 838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839
 840         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 841         IXGBE_WRITE_FLUSH(hw);
 842 }
 843
 844 /*
 845  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 846  */
 847 static void
 848 ixgbe_disable_intr(struct ixgbe_hw *hw)
 849 {
 850         PMD_INIT_FUNC_TRACE();
 851
 852         if (hw->mac.type == ixgbe_mac_82598EB) {
 853                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 854         } else {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 856                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 858         }
 859         IXGBE_WRITE_FLUSH(hw);
 860 }
 861
 862 /*
 863  * This function resets queue statistics mapping registers.
 864  * From Niantic datasheet, Initialization of Statistics section:
 865  * "...if software requires the queue counters, the RQSMR and TQSM registers
 866  * must be re-programmed following a device reset.
 867  */
 868 static void
 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 870 {
 871         uint32_t i;
 872
 873         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 875                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 876         }
 877 }
 878
 879
 880 static int
 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 882                                   uint16_t queue_id,
 883                                   uint8_t stat_idx,
 884                                   uint8_t is_rx)
 885 {
 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 889
 890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 891         struct ixgbe_stat_mapping_registers *stat_mappings =
 892                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 893         uint32_t qsmr_mask = 0;
 894         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 895         uint32_t q_map;
 896         uint8_t n, offset;
 897
 898         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 899                 (hw->mac.type != ixgbe_mac_X540) &&
 900                 (hw->mac.type != ixgbe_mac_X550) &&
 901                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 902                 (hw->mac.type != ixgbe_mac_X550EM_a))
 903                 return -ENOSYS;
 904
 905         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 906                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 907                      queue_id, stat_idx);
 908
 909         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 910         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 911                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 912                 return -EIO;
 913         }
 914         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 915
 916         /* Now clear any previous stat_idx set */
 917         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 918         if (!is_rx)
 919                 stat_mappings->tqsm[n] &= ~clearing_mask;
 920         else
 921                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 922
 923         q_map = (uint32_t)stat_idx;
 924         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 925         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 926         if (!is_rx)
 927                 stat_mappings->tqsm[n] |= qsmr_mask;
 928         else
 929                 stat_mappings->rqsmr[n] |= qsmr_mask;
 930
 931         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 932                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 933                      queue_id, stat_idx);
 934         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 935                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 936
 937         /* Now write the mapping in the appropriate register */
 938         if (is_rx) {
 939                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 940                              stat_mappings->rqsmr[n], n);
 941                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 942         } else {
 943                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 944                              stat_mappings->tqsm[n], n);
 945                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 946         }
 947         return 0;
 948 }
 949
 950 static void
 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 952 {
 953         struct ixgbe_stat_mapping_registers *stat_mappings =
 954                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 956         int i;
 957
 958         /* write whatever was in stat mapping table to the NIC */
 959         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 960                 /* rx */
 961                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 962
 963                 /* tx */
 964                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 965         }
 966 }
 967
 968 static void
 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 970 {
 971         uint8_t i;
 972         struct ixgbe_dcb_tc_config *tc;
 973         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 974
 975         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 976         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 977         for (i = 0; i < dcb_max_tc; i++) {
 978                 tc = &dcb_config->tc_config[i];
 979                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 980                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 981                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 982                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 983                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 984                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 985                 tc->pfc = ixgbe_dcb_pfc_disabled;
 986         }
 987
 988         /* Initialize default user to priority mapping, UPx->TC0 */
 989         tc = &dcb_config->tc_config[0];
 990         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 991         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 992         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 993                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 994                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 995         }
 996         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 997         dcb_config->pfc_mode_enable = false;
 998         dcb_config->vt_mode = true;
 999         dcb_config->round_robin_enable = false;
1000         /* support all DCB capabilities in 82599 */
1001         dcb_config->support.capabilities = 0xFF;
1002
1003         /*we only support 4 Tcs for X540, X550 */
1004         if (hw->mac.type == ixgbe_mac_X540 ||
1005                 hw->mac.type == ixgbe_mac_X550 ||
1006                 hw->mac.type == ixgbe_mac_X550EM_x ||
1007                 hw->mac.type == ixgbe_mac_X550EM_a) {
1008                 dcb_config->num_tcs.pg_tcs = 4;
1009                 dcb_config->num_tcs.pfc_tcs = 4;
1010         }
1011 }
1012
1013 /*
1014  * Ensure that all locks are released before first NVM or PHY access
1015  */
1016 static void
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1018 {
1019         uint16_t mask;
1020
1021         /*
1022          * Phy lock should not fail in this early stage. If this is the case,
1023          * it is due to an improper exit of the application.
1024          * So force the release of the faulty lock. Release of common lock
1025          * is done automatically by swfw_sync function.
1026          */
1027         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1030         }
1031         ixgbe_release_swfw_semaphore(hw, mask);
1032
1033         /*
1034          * These ones are more tricky since they are common to all ports; but
1035          * swfw_sync retries last long enough (1s) to be almost sure that if
1036          * lock can not be taken it is due to an improper lock of the
1037          * semaphore.
1038          */
1039         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1042         }
1043         ixgbe_release_swfw_semaphore(hw, mask);
1044 }
1045
1046 /*
1047  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048  * It returns 0 on success.
1049  */
1050 static int
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1052 {
1053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055         struct ixgbe_hw *hw =
1056                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057         struct ixgbe_vfta *shadow_vfta =
1058                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059         struct ixgbe_hwstrip *hwstrip =
1060                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061         struct ixgbe_dcb_config *dcb_config =
1062                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063         struct ixgbe_filter_info *filter_info =
1064                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065         struct ixgbe_bw_conf *bw_conf =
1066                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1067         uint32_t ctrl_ext;
1068         uint16_t csum;
1069         int diag, i;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1077
1078         /*
1079          * For secondary processes, we don't initialise any further as primary
1080          * has already done this work. Only check we don't need a different
1081          * RX and TX function.
1082          */
1083         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084                 struct ixgbe_tx_queue *txq;
1085                 /* TX queue function in primary, set by last queue initialized
1086                  * Tx queue may not initialized by primary process
1087                  */
1088                 if (eth_dev->data->tx_queues) {
1089                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090                         ixgbe_set_tx_function(eth_dev, txq);
1091                 } else {
1092                         /* Use default TX function if we get here */
1093                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094                                      "Using default TX function.");
1095                 }
1096
1097                 ixgbe_set_rx_function(eth_dev);
1098
1099                 return 0;
1100         }
1101
1102         rte_eth_copy_pci_info(eth_dev, pci_dev);
1103
1104         /* Vendor and Device ID need to be set before init of shared code */
1105         hw->device_id = pci_dev->id.device_id;
1106         hw->vendor_id = pci_dev->id.vendor_id;
1107         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108         hw->allow_unsupported_sfp = 1;
1109
1110         /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112         diag = ixgbe_bypass_init_shared_code(hw);
1113 #else
1114         diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1116
1117         if (diag != IXGBE_SUCCESS) {
1118                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1119                 return -EIO;
1120         }
1121
1122         /* pick up the PCI bus settings for reporting later */
1123         ixgbe_get_bus_info(hw);
1124
1125         /* Unlock any pending hardware semaphore */
1126         ixgbe_swfw_lock_reset(hw);
1127
1128 #ifdef RTE_LIBRTE_SECURITY
1129         /* Initialize security_ctx only for primary process*/
1130         if (ixgbe_ipsec_ctx_create(eth_dev))
1131                 return -ENOMEM;
1132 #endif
1133
1134         /* Initialize DCB configuration*/
1135         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1136         ixgbe_dcb_init(hw, dcb_config);
1137         /* Get Hardware Flow Control setting */
1138         hw->fc.requested_mode = ixgbe_fc_full;
1139         hw->fc.current_mode = ixgbe_fc_full;
1140         hw->fc.pause_time = IXGBE_FC_PAUSE;
1141         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1142                 hw->fc.low_water[i] = IXGBE_FC_LO;
1143                 hw->fc.high_water[i] = IXGBE_FC_HI;
1144         }
1145         hw->fc.send_xon = 1;
1146
1147         /* Make sure we have a good EEPROM before we read from it */
1148         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1149         if (diag != IXGBE_SUCCESS) {
1150                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1151                 return -EIO;
1152         }
1153
1154 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1155         diag = ixgbe_bypass_init_hw(hw);
1156 #else
1157         diag = ixgbe_init_hw(hw);
1158 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1159
1160         /*
1161          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1162          * is called too soon after the kernel driver unbinding/binding occurs.
1163          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1164          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1165          * also called. See ixgbe_identify_phy_82599(). The reason for the
1166          * failure is not known, and only occuts when virtualisation features
1167          * are disabled in the bios. A delay of 100ms  was found to be enough by
1168          * trial-and-error, and is doubled to be safe.
1169          */
1170         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1171                 rte_delay_ms(200);
1172                 diag = ixgbe_init_hw(hw);
1173         }
1174
1175         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1176                 diag = IXGBE_SUCCESS;
1177
1178         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1179                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1180                              "LOM.  Please be aware there may be issues associated "
1181                              "with your hardware.");
1182                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1183                              "please contact your Intel or hardware representative "
1184                              "who provided you with this hardware.");
1185         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1186                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1187         if (diag) {
1188                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1189                 return -EIO;
1190         }
1191
1192         /* Reset the hw statistics */
1193         ixgbe_dev_stats_reset(eth_dev);
1194
1195         /* disable interrupt */
1196         ixgbe_disable_intr(hw);
1197
1198         /* reset mappings for queue statistics hw counters*/
1199         ixgbe_reset_qstat_mappings(hw);
1200
1201         /* Allocate memory for storing MAC addresses */
1202         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1203                                                hw->mac.num_rar_entries, 0);
1204         if (eth_dev->data->mac_addrs == NULL) {
1205                 PMD_INIT_LOG(ERR,
1206                              "Failed to allocate %u bytes needed to store "
1207                              "MAC addresses",
1208                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1209                 return -ENOMEM;
1210         }
1211         /* Copy the permanent MAC address */
1212         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1213                         &eth_dev->data->mac_addrs[0]);
1214
1215         /* Allocate memory for storing hash filter MAC addresses */
1216         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1217                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1218         if (eth_dev->data->hash_mac_addrs == NULL) {
1219                 PMD_INIT_LOG(ERR,
1220                              "Failed to allocate %d bytes needed to store MAC addresses",
1221                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1222                 return -ENOMEM;
1223         }
1224
1225         /* initialize the vfta */
1226         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1227
1228         /* initialize the hw strip bitmap*/
1229         memset(hwstrip, 0, sizeof(*hwstrip));
1230
1231         /* initialize PF if max_vfs not zero */
1232         ixgbe_pf_host_init(eth_dev);
1233
1234         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1235         /* let hardware know driver is loaded */
1236         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1237         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1238         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1239         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1240         IXGBE_WRITE_FLUSH(hw);
1241
1242         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1243                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1244                              (int) hw->mac.type, (int) hw->phy.type,
1245                              (int) hw->phy.sfp_type);
1246         else
1247                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1248                              (int) hw->mac.type, (int) hw->phy.type);
1249
1250         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1251                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1252                      pci_dev->id.device_id);
1253
1254         rte_intr_callback_register(intr_handle,
1255                                    ixgbe_dev_interrupt_handler, eth_dev);
1256
1257         /* enable uio/vfio intr/eventfd mapping */
1258         rte_intr_enable(intr_handle);
1259
1260         /* enable support intr */
1261         ixgbe_enable_intr(eth_dev);
1262
1263         /* initialize filter info */
1264         memset(filter_info, 0,
1265                sizeof(struct ixgbe_filter_info));
1266
1267         /* initialize 5tuple filter list */
1268         TAILQ_INIT(&filter_info->fivetuple_list);
1269
1270         /* initialize flow director filter list & hash */
1271         ixgbe_fdir_filter_init(eth_dev);
1272
1273         /* initialize l2 tunnel filter list & hash */
1274         ixgbe_l2_tn_filter_init(eth_dev);
1275
1276         /* initialize flow filter lists */
1277         ixgbe_filterlist_init();
1278
1279         /* initialize bandwidth configuration info */
1280         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1281
1282         /* initialize Traffic Manager configuration */
1283         ixgbe_tm_conf_init(eth_dev);
1284
1285         return 0;
1286 }
1287
1288 static int
1289 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1290 {
1291         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1293         struct ixgbe_hw *hw;
1294         int retries = 0;
1295         int ret;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1300                 return -EPERM;
1301
1302         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1303
1304         if (hw->adapter_stopped == 0)
1305                 ixgbe_dev_close(eth_dev);
1306
1307         eth_dev->dev_ops = NULL;
1308         eth_dev->rx_pkt_burst = NULL;
1309         eth_dev->tx_pkt_burst = NULL;
1310
1311         /* Unlock any pending hardware semaphore */
1312         ixgbe_swfw_lock_reset(hw);
1313
1314         /* disable uio intr before callback unregister */
1315         rte_intr_disable(intr_handle);
1316
1317         do {
1318                 ret = rte_intr_callback_unregister(intr_handle,
1319                                 ixgbe_dev_interrupt_handler, eth_dev);
1320                 if (ret >= 0) {
1321                         break;
1322                 } else if (ret != -EAGAIN) {
1323                         PMD_INIT_LOG(ERR,
1324                                 "intr callback unregister failed: %d",
1325                                 ret);
1326                         return ret;
1327                 }
1328                 rte_delay_ms(100);
1329         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1330
1331         /* uninitialize PF if max_vfs not zero */
1332         ixgbe_pf_host_uninit(eth_dev);
1333
1334         rte_free(eth_dev->data->mac_addrs);
1335         eth_dev->data->mac_addrs = NULL;
1336
1337         rte_free(eth_dev->data->hash_mac_addrs);
1338         eth_dev->data->hash_mac_addrs = NULL;
1339
1340         /* remove all the fdir filters & hash */
1341         ixgbe_fdir_filter_uninit(eth_dev);
1342
1343         /* remove all the L2 tunnel filters & hash */
1344         ixgbe_l2_tn_filter_uninit(eth_dev);
1345
1346         /* Remove all ntuple filters of the device */
1347         ixgbe_ntuple_filter_uninit(eth_dev);
1348
1349         /* clear all the filters list */
1350         ixgbe_filterlist_flush();
1351
1352         /* Remove all Traffic Manager configuration */
1353         ixgbe_tm_conf_uninit(eth_dev);
1354
1355 #ifdef RTE_LIBRTE_SECURITY
1356         rte_free(eth_dev->security_ctx);
1357 #endif
1358
1359         return 0;
1360 }
1361
1362 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1363 {
1364         struct ixgbe_filter_info *filter_info =
1365                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1366         struct ixgbe_5tuple_filter *p_5tuple;
1367
1368         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1369                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1370                              p_5tuple,
1371                              entries);
1372                 rte_free(p_5tuple);
1373         }
1374         memset(filter_info->fivetuple_mask, 0,
1375                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1376
1377         return 0;
1378 }
1379
1380 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1381 {
1382         struct ixgbe_hw_fdir_info *fdir_info =
1383                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1384         struct ixgbe_fdir_filter *fdir_filter;
1385
1386                 if (fdir_info->hash_map)
1387                 rte_free(fdir_info->hash_map);
1388         if (fdir_info->hash_handle)
1389                 rte_hash_free(fdir_info->hash_handle);
1390
1391         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1392                 TAILQ_REMOVE(&fdir_info->fdir_list,
1393                              fdir_filter,
1394                              entries);
1395                 rte_free(fdir_filter);
1396         }
1397
1398         return 0;
1399 }
1400
1401 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1402 {
1403         struct ixgbe_l2_tn_info *l2_tn_info =
1404                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1405         struct ixgbe_l2_tn_filter *l2_tn_filter;
1406
1407         if (l2_tn_info->hash_map)
1408                 rte_free(l2_tn_info->hash_map);
1409         if (l2_tn_info->hash_handle)
1410                 rte_hash_free(l2_tn_info->hash_handle);
1411
1412         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1413                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1414                              l2_tn_filter,
1415                              entries);
1416                 rte_free(l2_tn_filter);
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1423 {
1424         struct ixgbe_hw_fdir_info *fdir_info =
1425                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1426         char fdir_hash_name[RTE_HASH_NAMESIZE];
1427         struct rte_hash_parameters fdir_hash_params = {
1428                 .name = fdir_hash_name,
1429                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1430                 .key_len = sizeof(union ixgbe_atr_input),
1431                 .hash_func = rte_hash_crc,
1432                 .hash_func_init_val = 0,
1433                 .socket_id = rte_socket_id(),
1434         };
1435
1436         TAILQ_INIT(&fdir_info->fdir_list);
1437         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1438                  "fdir_%s", eth_dev->device->name);
1439         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1440         if (!fdir_info->hash_handle) {
1441                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1442                 return -EINVAL;
1443         }
1444         fdir_info->hash_map = rte_zmalloc("ixgbe",
1445                                           sizeof(struct ixgbe_fdir_filter *) *
1446                                           IXGBE_MAX_FDIR_FILTER_NUM,
1447                                           0);
1448         if (!fdir_info->hash_map) {
1449                 PMD_INIT_LOG(ERR,
1450                              "Failed to allocate memory for fdir hash map!");
1451                 return -ENOMEM;
1452         }
1453         fdir_info->mask_added = FALSE;
1454
1455         return 0;
1456 }
1457
1458 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1459 {
1460         struct ixgbe_l2_tn_info *l2_tn_info =
1461                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1462         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1463         struct rte_hash_parameters l2_tn_hash_params = {
1464                 .name = l2_tn_hash_name,
1465                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1466                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1467                 .hash_func = rte_hash_crc,
1468                 .hash_func_init_val = 0,
1469                 .socket_id = rte_socket_id(),
1470         };
1471
1472         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1473         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1474                  "l2_tn_%s", eth_dev->device->name);
1475         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1476         if (!l2_tn_info->hash_handle) {
1477                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1478                 return -EINVAL;
1479         }
1480         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1481                                    sizeof(struct ixgbe_l2_tn_filter *) *
1482                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1483                                    0);
1484         if (!l2_tn_info->hash_map) {
1485                 PMD_INIT_LOG(ERR,
1486                         "Failed to allocate memory for L2 TN hash map!");
1487                 return -ENOMEM;
1488         }
1489         l2_tn_info->e_tag_en = FALSE;
1490         l2_tn_info->e_tag_fwd_en = FALSE;
1491         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1492
1493         return 0;
1494 }
1495 /*
1496  * Negotiate mailbox API version with the PF.
1497  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1498  * Then we try to negotiate starting with the most recent one.
1499  * If all negotiation attempts fail, then we will proceed with
1500  * the default one (ixgbe_mbox_api_10).
1501  */
1502 static void
1503 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1504 {
1505         int32_t i;
1506
1507         /* start with highest supported, proceed down */
1508         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1509                 ixgbe_mbox_api_12,
1510                 ixgbe_mbox_api_11,
1511                 ixgbe_mbox_api_10,
1512         };
1513
1514         for (i = 0;
1515                         i != RTE_DIM(sup_ver) &&
1516                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1517                         i++)
1518                 ;
1519 }
1520
1521 static void
1522 generate_random_mac_addr(struct ether_addr *mac_addr)
1523 {
1524         uint64_t random;
1525
1526         /* Set Organizationally Unique Identifier (OUI) prefix. */
1527         mac_addr->addr_bytes[0] = 0x00;
1528         mac_addr->addr_bytes[1] = 0x09;
1529         mac_addr->addr_bytes[2] = 0xC0;
1530         /* Force indication of locally assigned MAC address. */
1531         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1532         /* Generate the last 3 bytes of the MAC address with a random number. */
1533         random = rte_rand();
1534         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1535 }
1536
1537 /*
1538  * Virtual Function device init
1539  */
1540 static int
1541 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1542 {
1543         int diag;
1544         uint32_t tc, tcs;
1545         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1546         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1547         struct ixgbe_hw *hw =
1548                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1549         struct ixgbe_vfta *shadow_vfta =
1550                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1551         struct ixgbe_hwstrip *hwstrip =
1552                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1553         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1558         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1559         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1560
1561         /* for secondary processes, we don't initialise any further as primary
1562          * has already done this work. Only check we don't need a different
1563          * RX function
1564          */
1565         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1566                 struct ixgbe_tx_queue *txq;
1567                 /* TX queue function in primary, set by last queue initialized
1568                  * Tx queue may not initialized by primary process
1569                  */
1570                 if (eth_dev->data->tx_queues) {
1571                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1572                         ixgbe_set_tx_function(eth_dev, txq);
1573                 } else {
1574                         /* Use default TX function if we get here */
1575                         PMD_INIT_LOG(NOTICE,
1576                                      "No TX queues configured yet. Using default TX function.");
1577                 }
1578
1579                 ixgbe_set_rx_function(eth_dev);
1580
1581                 return 0;
1582         }
1583
1584         rte_eth_copy_pci_info(eth_dev, pci_dev);
1585
1586         hw->device_id = pci_dev->id.device_id;
1587         hw->vendor_id = pci_dev->id.vendor_id;
1588         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1589
1590         /* initialize the vfta */
1591         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1592
1593         /* initialize the hw strip bitmap*/
1594         memset(hwstrip, 0, sizeof(*hwstrip));
1595
1596         /* Initialize the shared code (base driver) */
1597         diag = ixgbe_init_shared_code(hw);
1598         if (diag != IXGBE_SUCCESS) {
1599                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1600                 return -EIO;
1601         }
1602
1603         /* init_mailbox_params */
1604         hw->mbx.ops.init_params(hw);
1605
1606         /* Reset the hw statistics */
1607         ixgbevf_dev_stats_reset(eth_dev);
1608
1609         /* Disable the interrupts for VF */
1610         ixgbevf_intr_disable(hw);
1611
1612         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1613         diag = hw->mac.ops.reset_hw(hw);
1614
1615         /*
1616          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1617          * the underlying PF driver has not assigned a MAC address to the VF.
1618          * In this case, assign a random MAC address.
1619          */
1620         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1621                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1622                 return diag;
1623         }
1624
1625         /* negotiate mailbox API version to use with the PF. */
1626         ixgbevf_negotiate_api(hw);
1627
1628         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1629         ixgbevf_get_queues(hw, &tcs, &tc);
1630
1631         /* Allocate memory for storing MAC addresses */
1632         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1633                                                hw->mac.num_rar_entries, 0);
1634         if (eth_dev->data->mac_addrs == NULL) {
1635                 PMD_INIT_LOG(ERR,
1636                              "Failed to allocate %u bytes needed to store "
1637                              "MAC addresses",
1638                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1639                 return -ENOMEM;
1640         }
1641
1642         /* Generate a random MAC address, if none was assigned by PF. */
1643         if (is_zero_ether_addr(perm_addr)) {
1644                 generate_random_mac_addr(perm_addr);
1645                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1646                 if (diag) {
1647                         rte_free(eth_dev->data->mac_addrs);
1648                         eth_dev->data->mac_addrs = NULL;
1649                         return diag;
1650                 }
1651                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1652                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1653                              "%02x:%02x:%02x:%02x:%02x:%02x",
1654                              perm_addr->addr_bytes[0],
1655                              perm_addr->addr_bytes[1],
1656                              perm_addr->addr_bytes[2],
1657                              perm_addr->addr_bytes[3],
1658                              perm_addr->addr_bytes[4],
1659                              perm_addr->addr_bytes[5]);
1660         }
1661
1662         /* Copy the permanent MAC address */
1663         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1664
1665         /* reset the hardware with the new settings */
1666         diag = hw->mac.ops.start_hw(hw);
1667         switch (diag) {
1668         case  0:
1669                 break;
1670
1671         default:
1672                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1673                 return -EIO;
1674         }
1675
1676         rte_intr_callback_register(intr_handle,
1677                                    ixgbevf_dev_interrupt_handler, eth_dev);
1678         rte_intr_enable(intr_handle);
1679         ixgbevf_intr_enable(hw);
1680
1681         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1682                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1683                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1684
1685         return 0;
1686 }
1687
1688 /* Virtual Function device uninit */
1689
1690 static int
1691 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1692 {
1693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1695         struct ixgbe_hw *hw;
1696
1697         PMD_INIT_FUNC_TRACE();
1698
1699         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1700                 return -EPERM;
1701
1702         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1703
1704         if (hw->adapter_stopped == 0)
1705                 ixgbevf_dev_close(eth_dev);
1706
1707         eth_dev->dev_ops = NULL;
1708         eth_dev->rx_pkt_burst = NULL;
1709         eth_dev->tx_pkt_burst = NULL;
1710
1711         /* Disable the interrupts for VF */
1712         ixgbevf_intr_disable(hw);
1713
1714         rte_free(eth_dev->data->mac_addrs);
1715         eth_dev->data->mac_addrs = NULL;
1716
1717         rte_intr_disable(intr_handle);
1718         rte_intr_callback_unregister(intr_handle,
1719                                      ixgbevf_dev_interrupt_handler, eth_dev);
1720
1721         return 0;
1722 }
1723
1724 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1725         struct rte_pci_device *pci_dev)
1726 {
1727         return rte_eth_dev_pci_generic_probe(pci_dev,
1728                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1729 }
1730
1731 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1732 {
1733         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1734 }
1735
1736 static struct rte_pci_driver rte_ixgbe_pmd = {
1737         .id_table = pci_id_ixgbe_map,
1738         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1739                      RTE_PCI_DRV_IOVA_AS_VA,
1740         .probe = eth_ixgbe_pci_probe,
1741         .remove = eth_ixgbe_pci_remove,
1742 };
1743
1744 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1745         struct rte_pci_device *pci_dev)
1746 {
1747         return rte_eth_dev_pci_generic_probe(pci_dev,
1748                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1749 }
1750
1751 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1752 {
1753         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1754 }
1755
1756 /*
1757  * virtual function driver struct
1758  */
1759 static struct rte_pci_driver rte_ixgbevf_pmd = {
1760         .id_table = pci_id_ixgbevf_map,
1761         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1762         .probe = eth_ixgbevf_pci_probe,
1763         .remove = eth_ixgbevf_pci_remove,
1764 };
1765
1766 static int
1767 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1768 {
1769         struct ixgbe_hw *hw =
1770                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771         struct ixgbe_vfta *shadow_vfta =
1772                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1773         uint32_t vfta;
1774         uint32_t vid_idx;
1775         uint32_t vid_bit;
1776
1777         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1778         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1779         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1780         if (on)
1781                 vfta |= vid_bit;
1782         else
1783                 vfta &= ~vid_bit;
1784         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1785
1786         /* update local VFTA copy */
1787         shadow_vfta->vfta[vid_idx] = vfta;
1788
1789         return 0;
1790 }
1791
1792 static void
1793 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1794 {
1795         if (on)
1796                 ixgbe_vlan_hw_strip_enable(dev, queue);
1797         else
1798                 ixgbe_vlan_hw_strip_disable(dev, queue);
1799 }
1800
1801 static int
1802 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1803                     enum rte_vlan_type vlan_type,
1804                     uint16_t tpid)
1805 {
1806         struct ixgbe_hw *hw =
1807                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1808         int ret = 0;
1809         uint32_t reg;
1810         uint32_t qinq;
1811
1812         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1813         qinq &= IXGBE_DMATXCTL_GDV;
1814
1815         switch (vlan_type) {
1816         case ETH_VLAN_TYPE_INNER:
1817                 if (qinq) {
1818                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1819                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1820                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1821                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1822                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1823                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1824                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1825                 } else {
1826                         ret = -ENOTSUP;
1827                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1828                                     " by single VLAN");
1829                 }
1830                 break;
1831         case ETH_VLAN_TYPE_OUTER:
1832                 if (qinq) {
1833                         /* Only the high 16-bits is valid */
1834                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1835                                         IXGBE_EXVET_VET_EXT_SHIFT);
1836                 } else {
1837                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1838                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1839                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1840                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1841                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1842                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1843                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1844                 }
1845
1846                 break;
1847         default:
1848                 ret = -EINVAL;
1849                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1850                 break;
1851         }
1852
1853         return ret;
1854 }
1855
1856 void
1857 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1858 {
1859         struct ixgbe_hw *hw =
1860                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1861         uint32_t vlnctrl;
1862
1863         PMD_INIT_FUNC_TRACE();
1864
1865         /* Filter Table Disable */
1866         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1867         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1868
1869         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1870 }
1871
1872 void
1873 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1874 {
1875         struct ixgbe_hw *hw =
1876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877         struct ixgbe_vfta *shadow_vfta =
1878                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1879         uint32_t vlnctrl;
1880         uint16_t i;
1881
1882         PMD_INIT_FUNC_TRACE();
1883
1884         /* Filter Table Enable */
1885         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1886         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1887         vlnctrl |= IXGBE_VLNCTRL_VFE;
1888
1889         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1890
1891         /* write whatever is in local vfta copy */
1892         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1893                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1894 }
1895
1896 static void
1897 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1898 {
1899         struct ixgbe_hwstrip *hwstrip =
1900                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1901         struct ixgbe_rx_queue *rxq;
1902
1903         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1904                 return;
1905
1906         if (on)
1907                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1908         else
1909                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1910
1911         if (queue >= dev->data->nb_rx_queues)
1912                 return;
1913
1914         rxq = dev->data->rx_queues[queue];
1915
1916         if (on)
1917                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1918         else
1919                 rxq->vlan_flags = PKT_RX_VLAN;
1920 }
1921
1922 static void
1923 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1924 {
1925         struct ixgbe_hw *hw =
1926                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927         uint32_t ctrl;
1928
1929         PMD_INIT_FUNC_TRACE();
1930
1931         if (hw->mac.type == ixgbe_mac_82598EB) {
1932                 /* No queue level support */
1933                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1934                 return;
1935         }
1936
1937         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1938         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1939         ctrl &= ~IXGBE_RXDCTL_VME;
1940         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1941
1942         /* record those setting for HW strip per queue */
1943         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1944 }
1945
1946 static void
1947 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1948 {
1949         struct ixgbe_hw *hw =
1950                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         uint32_t ctrl;
1952
1953         PMD_INIT_FUNC_TRACE();
1954
1955         if (hw->mac.type == ixgbe_mac_82598EB) {
1956                 /* No queue level supported */
1957                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1958                 return;
1959         }
1960
1961         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1962         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1963         ctrl |= IXGBE_RXDCTL_VME;
1964         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1965
1966         /* record those setting for HW strip per queue */
1967         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1968 }
1969
1970 static void
1971 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1972 {
1973         struct ixgbe_hw *hw =
1974                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975         uint32_t ctrl;
1976
1977         PMD_INIT_FUNC_TRACE();
1978
1979         /* DMATXCTRL: Geric Double VLAN Disable */
1980         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1981         ctrl &= ~IXGBE_DMATXCTL_GDV;
1982         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1983
1984         /* CTRL_EXT: Global Double VLAN Disable */
1985         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1986         ctrl &= ~IXGBE_EXTENDED_VLAN;
1987         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1988
1989 }
1990
1991 static void
1992 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1993 {
1994         struct ixgbe_hw *hw =
1995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         uint32_t ctrl;
1997
1998         PMD_INIT_FUNC_TRACE();
1999
2000         /* DMATXCTRL: Geric Double VLAN Enable */
2001         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2002         ctrl |= IXGBE_DMATXCTL_GDV;
2003         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2004
2005         /* CTRL_EXT: Global Double VLAN Enable */
2006         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2007         ctrl |= IXGBE_EXTENDED_VLAN;
2008         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2009
2010         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2011         if (hw->mac.type == ixgbe_mac_X550 ||
2012             hw->mac.type == ixgbe_mac_X550EM_x ||
2013             hw->mac.type == ixgbe_mac_X550EM_a) {
2014                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2015                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2016                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2017         }
2018
2019         /*
2020          * VET EXT field in the EXVET register = 0x8100 by default
2021          * So no need to change. Same to VT field of DMATXCTL register
2022          */
2023 }
2024
2025 void
2026 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2027 {
2028         struct ixgbe_hw *hw =
2029                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2031         uint32_t ctrl;
2032         uint16_t i;
2033         struct ixgbe_rx_queue *rxq;
2034         bool on;
2035
2036         PMD_INIT_FUNC_TRACE();
2037
2038         if (hw->mac.type == ixgbe_mac_82598EB) {
2039                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2040                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2041                         ctrl |= IXGBE_VLNCTRL_VME;
2042                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2043                 } else {
2044                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2045                         ctrl &= ~IXGBE_VLNCTRL_VME;
2046                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2047                 }
2048         } else {
2049                 /*
2050                  * Other 10G NIC, the VLAN strip can be setup
2051                  * per queue in RXDCTL
2052                  */
2053                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2054                         rxq = dev->data->rx_queues[i];
2055                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2056                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2057                                 ctrl |= IXGBE_RXDCTL_VME;
2058                                 on = TRUE;
2059                         } else {
2060                                 ctrl &= ~IXGBE_RXDCTL_VME;
2061                                 on = FALSE;
2062                         }
2063                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2064
2065                         /* record those setting for HW strip per queue */
2066                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2067                 }
2068         }
2069 }
2070
2071 static int
2072 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2073 {
2074         struct rte_eth_rxmode *rxmode;
2075         rxmode = &dev->data->dev_conf.rxmode;
2076
2077         if (mask & ETH_VLAN_STRIP_MASK) {
2078                 ixgbe_vlan_hw_strip_config(dev);
2079         }
2080
2081         if (mask & ETH_VLAN_FILTER_MASK) {
2082                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2083                         ixgbe_vlan_hw_filter_enable(dev);
2084                 else
2085                         ixgbe_vlan_hw_filter_disable(dev);
2086         }
2087
2088         if (mask & ETH_VLAN_EXTEND_MASK) {
2089                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2090                         ixgbe_vlan_hw_extend_enable(dev);
2091                 else
2092                         ixgbe_vlan_hw_extend_disable(dev);
2093         }
2094
2095         return 0;
2096 }
2097
2098 static void
2099 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2100 {
2101         struct ixgbe_hw *hw =
2102                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2104         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2105
2106         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2107         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2108 }
2109
2110 static int
2111 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2112 {
2113         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2114
2115         switch (nb_rx_q) {
2116         case 1:
2117         case 2:
2118                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2119                 break;
2120         case 4:
2121                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2122                 break;
2123         default:
2124                 return -EINVAL;
2125         }
2126
2127         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2128                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2129         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2130                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2131         return 0;
2132 }
2133
2134 static int
2135 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2136 {
2137         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2139         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2140         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2141
2142         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2143                 /* check multi-queue mode */
2144                 switch (dev_conf->rxmode.mq_mode) {
2145                 case ETH_MQ_RX_VMDQ_DCB:
2146                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2147                         break;
2148                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2149                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2150                         PMD_INIT_LOG(ERR, "SRIOV active,"
2151                                         " unsupported mq_mode rx %d.",
2152                                         dev_conf->rxmode.mq_mode);
2153                         return -EINVAL;
2154                 case ETH_MQ_RX_RSS:
2155                 case ETH_MQ_RX_VMDQ_RSS:
2156                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2157                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2158                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2159                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2160                                                 " invalid queue number"
2161                                                 " for VMDQ RSS, allowed"
2162                                                 " value are 1, 2 or 4.");
2163                                         return -EINVAL;
2164                                 }
2165                         break;
2166                 case ETH_MQ_RX_VMDQ_ONLY:
2167                 case ETH_MQ_RX_NONE:
2168                         /* if nothing mq mode configure, use default scheme */
2169                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2170                         break;
2171                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2172                         /* SRIOV only works in VMDq enable mode */
2173                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2174                                         " wrong mq_mode rx %d.",
2175                                         dev_conf->rxmode.mq_mode);
2176                         return -EINVAL;
2177                 }
2178
2179                 switch (dev_conf->txmode.mq_mode) {
2180                 case ETH_MQ_TX_VMDQ_DCB:
2181                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2182                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2183                         break;
2184                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2185                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2186                         break;
2187                 }
2188
2189                 /* check valid queue number */
2190                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2191                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2192                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2193                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2194                                         " must be less than or equal to %d.",
2195                                         nb_rx_q, nb_tx_q,
2196                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2197                         return -EINVAL;
2198                 }
2199         } else {
2200                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2201                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2202                                           " not supported.");
2203                         return -EINVAL;
2204                 }
2205                 /* check configuration for vmdb+dcb mode */
2206                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2207                         const struct rte_eth_vmdq_dcb_conf *conf;
2208
2209                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2210                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2211                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2212                                 return -EINVAL;
2213                         }
2214                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2215                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2216                                conf->nb_queue_pools == ETH_32_POOLS)) {
2217                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2218                                                 " nb_queue_pools must be %d or %d.",
2219                                                 ETH_16_POOLS, ETH_32_POOLS);
2220                                 return -EINVAL;
2221                         }
2222                 }
2223                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2224                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2225
2226                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2227                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2228                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2229                                 return -EINVAL;
2230                         }
2231                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2232                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2233                                conf->nb_queue_pools == ETH_32_POOLS)) {
2234                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2235                                                 " nb_queue_pools != %d and"
2236                                                 " nb_queue_pools != %d.",
2237                                                 ETH_16_POOLS, ETH_32_POOLS);
2238                                 return -EINVAL;
2239                         }
2240                 }
2241
2242                 /* For DCB mode check our configuration before we go further */
2243                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2244                         const struct rte_eth_dcb_rx_conf *conf;
2245
2246                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2247                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2248                                                  IXGBE_DCB_NB_QUEUES);
2249                                 return -EINVAL;
2250                         }
2251                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2252                         if (!(conf->nb_tcs == ETH_4_TCS ||
2253                                conf->nb_tcs == ETH_8_TCS)) {
2254                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2255                                                 " and nb_tcs != %d.",
2256                                                 ETH_4_TCS, ETH_8_TCS);
2257                                 return -EINVAL;
2258                         }
2259                 }
2260
2261                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2262                         const struct rte_eth_dcb_tx_conf *conf;
2263
2264                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2265                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2266                                                  IXGBE_DCB_NB_QUEUES);
2267                                 return -EINVAL;
2268                         }
2269                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2270                         if (!(conf->nb_tcs == ETH_4_TCS ||
2271                                conf->nb_tcs == ETH_8_TCS)) {
2272                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2273                                                 " and nb_tcs != %d.",
2274                                                 ETH_4_TCS, ETH_8_TCS);
2275                                 return -EINVAL;
2276                         }
2277                 }
2278
2279                 /*
2280                  * When DCB/VT is off, maximum number of queues changes,
2281                  * except for 82598EB, which remains constant.
2282                  */
2283                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2284                                 hw->mac.type != ixgbe_mac_82598EB) {
2285                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2286                                 PMD_INIT_LOG(ERR,
2287                                              "Neither VT nor DCB are enabled, "
2288                                              "nb_tx_q > %d.",
2289                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2290                                 return -EINVAL;
2291                         }
2292                 }
2293         }
2294         return 0;
2295 }
2296
2297 static int
2298 ixgbe_dev_configure(struct rte_eth_dev *dev)
2299 {
2300         struct ixgbe_interrupt *intr =
2301                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2302         struct ixgbe_adapter *adapter =
2303                 (struct ixgbe_adapter *)dev->data->dev_private;
2304         struct rte_eth_dev_info dev_info;
2305         uint64_t rx_offloads;
2306         uint64_t tx_offloads;
2307         int ret;
2308
2309         PMD_INIT_FUNC_TRACE();
2310         /* multipe queue mode checking */
2311         ret  = ixgbe_check_mq_mode(dev);
2312         if (ret != 0) {
2313                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2314                             ret);
2315                 return ret;
2316         }
2317
2318         ixgbe_dev_info_get(dev, &dev_info);
2319         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2320         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2321                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2322                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2323                             rx_offloads, dev_info.rx_offload_capa);
2324                 return -ENOTSUP;
2325         }
2326         tx_offloads = dev->data->dev_conf.txmode.offloads;
2327         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2328                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2329                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2330                             tx_offloads, dev_info.tx_offload_capa);
2331                 return -ENOTSUP;
2332         }
2333
2334         /* set flag to update link status after init */
2335         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2336
2337         /*
2338          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2339          * allocation or vector Rx preconditions we will reset it.
2340          */
2341         adapter->rx_bulk_alloc_allowed = true;
2342         adapter->rx_vec_allowed = true;
2343
2344         return 0;
2345 }
2346
2347 static void
2348 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2349 {
2350         struct ixgbe_hw *hw =
2351                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352         struct ixgbe_interrupt *intr =
2353                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2354         uint32_t gpie;
2355
2356         /* only set up it on X550EM_X */
2357         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2358                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2359                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2360                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2361                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2362                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2363         }
2364 }
2365
2366 int
2367 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2368                         uint16_t tx_rate, uint64_t q_msk)
2369 {
2370         struct ixgbe_hw *hw;
2371         struct ixgbe_vf_info *vfinfo;
2372         struct rte_eth_link link;
2373         uint8_t  nb_q_per_pool;
2374         uint32_t queue_stride;
2375         uint32_t queue_idx, idx = 0, vf_idx;
2376         uint32_t queue_end;
2377         uint16_t total_rate = 0;
2378         struct rte_pci_device *pci_dev;
2379
2380         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2381         rte_eth_link_get_nowait(dev->data->port_id, &link);
2382
2383         if (vf >= pci_dev->max_vfs)
2384                 return -EINVAL;
2385
2386         if (tx_rate > link.link_speed)
2387                 return -EINVAL;
2388
2389         if (q_msk == 0)
2390                 return 0;
2391
2392         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2394         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2395         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2396         queue_idx = vf * queue_stride;
2397         queue_end = queue_idx + nb_q_per_pool - 1;
2398         if (queue_end >= hw->mac.max_tx_queues)
2399                 return -EINVAL;
2400
2401         if (vfinfo) {
2402                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2403                         if (vf_idx == vf)
2404                                 continue;
2405                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2406                                 idx++)
2407                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2408                 }
2409         } else {
2410                 return -EINVAL;
2411         }
2412
2413         /* Store tx_rate for this vf. */
2414         for (idx = 0; idx < nb_q_per_pool; idx++) {
2415                 if (((uint64_t)0x1 << idx) & q_msk) {
2416                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2417                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2418                         total_rate += tx_rate;
2419                 }
2420         }
2421
2422         if (total_rate > dev->data->dev_link.link_speed) {
2423                 /* Reset stored TX rate of the VF if it causes exceed
2424                  * link speed.
2425                  */
2426                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2427                 return -EINVAL;
2428         }
2429
2430         /* Set RTTBCNRC of each queue/pool for vf X  */
2431         for (; queue_idx <= queue_end; queue_idx++) {
2432                 if (0x1 & q_msk)
2433                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2434                 q_msk = q_msk >> 1;
2435         }
2436
2437         return 0;
2438 }
2439
2440 /*
2441  * Configure device link speed and setup link.
2442  * It returns 0 on success.
2443  */
2444 static int
2445 ixgbe_dev_start(struct rte_eth_dev *dev)
2446 {
2447         struct ixgbe_hw *hw =
2448                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2449         struct ixgbe_vf_info *vfinfo =
2450                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2451         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2452         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2453         uint32_t intr_vector = 0;
2454         int err, link_up = 0, negotiate = 0;
2455         uint32_t speed = 0;
2456         uint32_t allowed_speeds = 0;
2457         int mask = 0;
2458         int status;
2459         uint16_t vf, idx;
2460         uint32_t *link_speeds;
2461         struct ixgbe_tm_conf *tm_conf =
2462                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2463
2464         PMD_INIT_FUNC_TRACE();
2465
2466         /* IXGBE devices don't support:
2467         *    - half duplex (checked afterwards for valid speeds)
2468         *    - fixed speed: TODO implement
2469         */
2470         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2471                 PMD_INIT_LOG(ERR,
2472                 "Invalid link_speeds for port %u, fix speed not supported",
2473                                 dev->data->port_id);
2474                 return -EINVAL;
2475         }
2476
2477         /* disable uio/vfio intr/eventfd mapping */
2478         rte_intr_disable(intr_handle);
2479
2480         /* stop adapter */
2481         hw->adapter_stopped = 0;
2482         ixgbe_stop_adapter(hw);
2483
2484         /* reinitialize adapter
2485          * this calls reset and start
2486          */
2487         status = ixgbe_pf_reset_hw(hw);
2488         if (status != 0)
2489                 return -1;
2490         hw->mac.ops.start_hw(hw);
2491         hw->mac.get_link_status = true;
2492
2493         /* configure PF module if SRIOV enabled */
2494         ixgbe_pf_host_configure(dev);
2495
2496         ixgbe_dev_phy_intr_setup(dev);
2497
2498         /* check and configure queue intr-vector mapping */
2499         if ((rte_intr_cap_multiple(intr_handle) ||
2500              !RTE_ETH_DEV_SRIOV(dev).active) &&
2501             dev->data->dev_conf.intr_conf.rxq != 0) {
2502                 intr_vector = dev->data->nb_rx_queues;
2503                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2504                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2505                                         IXGBE_MAX_INTR_QUEUE_NUM);
2506                         return -ENOTSUP;
2507                 }
2508                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2509                         return -1;
2510         }
2511
2512         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2513                 intr_handle->intr_vec =
2514                         rte_zmalloc("intr_vec",
2515                                     dev->data->nb_rx_queues * sizeof(int), 0);
2516                 if (intr_handle->intr_vec == NULL) {
2517                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2518                                      " intr_vec", dev->data->nb_rx_queues);
2519                         return -ENOMEM;
2520                 }
2521         }
2522
2523         /* confiugre msix for sleep until rx interrupt */
2524         ixgbe_configure_msix(dev);
2525
2526         /* initialize transmission unit */
2527         ixgbe_dev_tx_init(dev);
2528
2529         /* This can fail when allocating mbufs for descriptor rings */
2530         err = ixgbe_dev_rx_init(dev);
2531         if (err) {
2532                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2533                 goto error;
2534         }
2535
2536         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2537                 ETH_VLAN_EXTEND_MASK;
2538         err = ixgbe_vlan_offload_set(dev, mask);
2539         if (err) {
2540                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2541                 goto error;
2542         }
2543
2544         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2545                 /* Enable vlan filtering for VMDq */
2546                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2547         }
2548
2549         /* Configure DCB hw */
2550         ixgbe_configure_dcb(dev);
2551
2552         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2553                 err = ixgbe_fdir_configure(dev);
2554                 if (err)
2555                         goto error;
2556         }
2557
2558         /* Restore vf rate limit */
2559         if (vfinfo != NULL) {
2560                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2561                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2562                                 if (vfinfo[vf].tx_rate[idx] != 0)
2563                                         ixgbe_set_vf_rate_limit(
2564                                                 dev, vf,
2565                                                 vfinfo[vf].tx_rate[idx],
2566                                                 1 << idx);
2567         }
2568
2569         ixgbe_restore_statistics_mapping(dev);
2570
2571         err = ixgbe_dev_rxtx_start(dev);
2572         if (err < 0) {
2573                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2574                 goto error;
2575         }
2576
2577         /* Skip link setup if loopback mode is enabled for 82599. */
2578         if (hw->mac.type == ixgbe_mac_82599EB &&
2579                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2580                 goto skip_link_setup;
2581
2582         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2583                 err = hw->mac.ops.setup_sfp(hw);
2584                 if (err)
2585                         goto error;
2586         }
2587
2588         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2589                 /* Turn on the copper */
2590                 ixgbe_set_phy_power(hw, true);
2591         } else {
2592                 /* Turn on the laser */
2593                 ixgbe_enable_tx_laser(hw);
2594         }
2595
2596         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2597         if (err)
2598                 goto error;
2599         dev->data->dev_link.link_status = link_up;
2600
2601         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2602         if (err)
2603                 goto error;
2604
2605         switch (hw->mac.type) {
2606         case ixgbe_mac_X550:
2607         case ixgbe_mac_X550EM_x:
2608         case ixgbe_mac_X550EM_a:
2609                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2610                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2611                         ETH_LINK_SPEED_10G;
2612                 break;
2613         default:
2614                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2615                         ETH_LINK_SPEED_10G;
2616         }
2617
2618         link_speeds = &dev->data->dev_conf.link_speeds;
2619         if (*link_speeds & ~allowed_speeds) {
2620                 PMD_INIT_LOG(ERR, "Invalid link setting");
2621                 goto error;
2622         }
2623
2624         speed = 0x0;
2625         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2626                 switch (hw->mac.type) {
2627                 case ixgbe_mac_82598EB:
2628                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2629                         break;
2630                 case ixgbe_mac_82599EB:
2631                 case ixgbe_mac_X540:
2632                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2633                         break;
2634                 case ixgbe_mac_X550:
2635                 case ixgbe_mac_X550EM_x:
2636                 case ixgbe_mac_X550EM_a:
2637                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2638                         break;
2639                 default:
2640                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2641                 }
2642         } else {
2643                 if (*link_speeds & ETH_LINK_SPEED_10G)
2644                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2645                 if (*link_speeds & ETH_LINK_SPEED_5G)
2646                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2647                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2648                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2649                 if (*link_speeds & ETH_LINK_SPEED_1G)
2650                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2651                 if (*link_speeds & ETH_LINK_SPEED_100M)
2652                         speed |= IXGBE_LINK_SPEED_100_FULL;
2653         }
2654
2655         err = ixgbe_setup_link(hw, speed, link_up);
2656         if (err)
2657                 goto error;
2658
2659         ixgbe_dev_link_update(dev, 0);
2660
2661 skip_link_setup:
2662
2663         if (rte_intr_allow_others(intr_handle)) {
2664                 /* check if lsc interrupt is enabled */
2665                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2666                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2667                 else
2668                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2669                 ixgbe_dev_macsec_interrupt_setup(dev);
2670         } else {
2671                 rte_intr_callback_unregister(intr_handle,
2672                                              ixgbe_dev_interrupt_handler, dev);
2673                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2674                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2675                                      " no intr multiplex");
2676         }
2677
2678         /* check if rxq interrupt is enabled */
2679         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2680             rte_intr_dp_is_en(intr_handle))
2681                 ixgbe_dev_rxq_interrupt_setup(dev);
2682
2683         /* enable uio/vfio intr/eventfd mapping */
2684         rte_intr_enable(intr_handle);
2685
2686         /* resume enabled intr since hw reset */
2687         ixgbe_enable_intr(dev);
2688         ixgbe_l2_tunnel_conf(dev);
2689         ixgbe_filter_restore(dev);
2690
2691         if (tm_conf->root && !tm_conf->committed)
2692                 PMD_DRV_LOG(WARNING,
2693                             "please call hierarchy_commit() "
2694                             "before starting the port");
2695
2696         return 0;
2697
2698 error:
2699         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2700         ixgbe_dev_clear_queues(dev);
2701         return -EIO;
2702 }
2703
2704 /*
2705  * Stop device: disable rx and tx functions to allow for reconfiguring.
2706  */
2707 static void
2708 ixgbe_dev_stop(struct rte_eth_dev *dev)
2709 {
2710         struct rte_eth_link link;
2711         struct ixgbe_hw *hw =
2712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713         struct ixgbe_vf_info *vfinfo =
2714                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2715         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2716         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2717         int vf;
2718         struct ixgbe_tm_conf *tm_conf =
2719                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2720
2721         PMD_INIT_FUNC_TRACE();
2722
2723         /* disable interrupts */
2724         ixgbe_disable_intr(hw);
2725
2726         /* reset the NIC */
2727         ixgbe_pf_reset_hw(hw);
2728         hw->adapter_stopped = 0;
2729
2730         /* stop adapter */
2731         ixgbe_stop_adapter(hw);
2732
2733         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2734                 vfinfo[vf].clear_to_send = false;
2735
2736         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2737                 /* Turn off the copper */
2738                 ixgbe_set_phy_power(hw, false);
2739         } else {
2740                 /* Turn off the laser */
2741                 ixgbe_disable_tx_laser(hw);
2742         }
2743
2744         ixgbe_dev_clear_queues(dev);
2745
2746         /* Clear stored conf */
2747         dev->data->scattered_rx = 0;
2748         dev->data->lro = 0;
2749
2750         /* Clear recorded link status */
2751         memset(&link, 0, sizeof(link));
2752         rte_eth_linkstatus_set(dev, &link);
2753
2754         if (!rte_intr_allow_others(intr_handle))
2755                 /* resume to the default handler */
2756                 rte_intr_callback_register(intr_handle,
2757                                            ixgbe_dev_interrupt_handler,
2758                                            (void *)dev);
2759
2760         /* Clean datapath event and queue/vec mapping */
2761         rte_intr_efd_disable(intr_handle);
2762         if (intr_handle->intr_vec != NULL) {
2763                 rte_free(intr_handle->intr_vec);
2764                 intr_handle->intr_vec = NULL;
2765         }
2766
2767         /* reset hierarchy commit */
2768         tm_conf->committed = false;
2769 }
2770
2771 /*
2772  * Set device link up: enable tx.
2773  */
2774 static int
2775 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2776 {
2777         struct ixgbe_hw *hw =
2778                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779         if (hw->mac.type == ixgbe_mac_82599EB) {
2780 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2781                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2782                         /* Not suported in bypass mode */
2783                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2784                                      "by device id 0x%x", hw->device_id);
2785                         return -ENOTSUP;
2786                 }
2787 #endif
2788         }
2789
2790         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2791                 /* Turn on the copper */
2792                 ixgbe_set_phy_power(hw, true);
2793         } else {
2794                 /* Turn on the laser */
2795                 ixgbe_enable_tx_laser(hw);
2796         }
2797
2798         return 0;
2799 }
2800
2801 /*
2802  * Set device link down: disable tx.
2803  */
2804 static int
2805 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2806 {
2807         struct ixgbe_hw *hw =
2808                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2809         if (hw->mac.type == ixgbe_mac_82599EB) {
2810 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2811                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2812                         /* Not suported in bypass mode */
2813                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2814                                      "by device id 0x%x", hw->device_id);
2815                         return -ENOTSUP;
2816                 }
2817 #endif
2818         }
2819
2820         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2821                 /* Turn off the copper */
2822                 ixgbe_set_phy_power(hw, false);
2823         } else {
2824                 /* Turn off the laser */
2825                 ixgbe_disable_tx_laser(hw);
2826         }
2827
2828         return 0;
2829 }
2830
2831 /*
2832  * Reset and stop device.
2833  */
2834 static void
2835 ixgbe_dev_close(struct rte_eth_dev *dev)
2836 {
2837         struct ixgbe_hw *hw =
2838                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839
2840         PMD_INIT_FUNC_TRACE();
2841
2842         ixgbe_pf_reset_hw(hw);
2843
2844         ixgbe_dev_stop(dev);
2845         hw->adapter_stopped = 1;
2846
2847         ixgbe_dev_free_queues(dev);
2848
2849         ixgbe_disable_pcie_master(hw);
2850
2851         /* reprogram the RAR[0] in case user changed it. */
2852         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2853 }
2854
2855 /*
2856  * Reset PF device.
2857  */
2858 static int
2859 ixgbe_dev_reset(struct rte_eth_dev *dev)
2860 {
2861         int ret;
2862
2863         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2864          * its VF to make them align with it. The detailed notification
2865          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2866          * To avoid unexpected behavior in VF, currently reset of PF with
2867          * SR-IOV activation is not supported. It might be supported later.
2868          */
2869         if (dev->data->sriov.active)
2870                 return -ENOTSUP;
2871
2872         ret = eth_ixgbe_dev_uninit(dev);
2873         if (ret)
2874                 return ret;
2875
2876         ret = eth_ixgbe_dev_init(dev);
2877
2878         return ret;
2879 }
2880
2881 static void
2882 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2883                            struct ixgbe_hw_stats *hw_stats,
2884                            struct ixgbe_macsec_stats *macsec_stats,
2885                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2886                            uint64_t *total_qprc, uint64_t *total_qprdc)
2887 {
2888         uint32_t bprc, lxon, lxoff, total;
2889         uint32_t delta_gprc = 0;
2890         unsigned i;
2891         /* Workaround for RX byte count not including CRC bytes when CRC
2892          * strip is enabled. CRC bytes are removed from counters when crc_strip
2893          * is disabled.
2894          */
2895         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2896                         IXGBE_HLREG0_RXCRCSTRP);
2897
2898         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2899         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2900         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2901         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2902
2903         for (i = 0; i < 8; i++) {
2904                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2905
2906                 /* global total per queue */
2907                 hw_stats->mpc[i] += mp;
2908                 /* Running comprehensive total for stats display */
2909                 *total_missed_rx += hw_stats->mpc[i];
2910                 if (hw->mac.type == ixgbe_mac_82598EB) {
2911                         hw_stats->rnbc[i] +=
2912                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2913                         hw_stats->pxonrxc[i] +=
2914                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2915                         hw_stats->pxoffrxc[i] +=
2916                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2917                 } else {
2918                         hw_stats->pxonrxc[i] +=
2919                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2920                         hw_stats->pxoffrxc[i] +=
2921                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2922                         hw_stats->pxon2offc[i] +=
2923                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2924                 }
2925                 hw_stats->pxontxc[i] +=
2926                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2927                 hw_stats->pxofftxc[i] +=
2928                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2929         }
2930         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2931                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2932                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2933                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2934
2935                 delta_gprc += delta_qprc;
2936
2937                 hw_stats->qprc[i] += delta_qprc;
2938                 hw_stats->qptc[i] += delta_qptc;
2939
2940                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2941                 hw_stats->qbrc[i] +=
2942                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2943                 if (crc_strip == 0)
2944                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2945
2946                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2947                 hw_stats->qbtc[i] +=
2948                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2949
2950                 hw_stats->qprdc[i] += delta_qprdc;
2951                 *total_qprdc += hw_stats->qprdc[i];
2952
2953                 *total_qprc += hw_stats->qprc[i];
2954                 *total_qbrc += hw_stats->qbrc[i];
2955         }
2956         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2957         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2958         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2959
2960         /*
2961          * An errata states that gprc actually counts good + missed packets:
2962          * Workaround to set gprc to summated queue packet receives
2963          */
2964         hw_stats->gprc = *total_qprc;
2965
2966         if (hw->mac.type != ixgbe_mac_82598EB) {
2967                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2968                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2969                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2970                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2971                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2972                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2973                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2974                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2975         } else {
2976                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2977                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2978                 /* 82598 only has a counter in the high register */
2979                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2980                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2981                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2982         }
2983         uint64_t old_tpr = hw_stats->tpr;
2984
2985         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2986         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2987
2988         if (crc_strip == 0)
2989                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2990
2991         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2992         hw_stats->gptc += delta_gptc;
2993         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2994         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2995
2996         /*
2997          * Workaround: mprc hardware is incorrectly counting
2998          * broadcasts, so for now we subtract those.
2999          */
3000         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3001         hw_stats->bprc += bprc;
3002         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3003         if (hw->mac.type == ixgbe_mac_82598EB)
3004                 hw_stats->mprc -= bprc;
3005
3006         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3007         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3008         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3009         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3010         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3011         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3012
3013         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3014         hw_stats->lxontxc += lxon;
3015         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3016         hw_stats->lxofftxc += lxoff;
3017         total = lxon + lxoff;
3018
3019         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3020         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3021         hw_stats->gptc -= total;
3022         hw_stats->mptc -= total;
3023         hw_stats->ptc64 -= total;
3024         hw_stats->gotc -= total * ETHER_MIN_LEN;
3025
3026         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3027         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3028         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3029         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3030         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3031         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3032         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3033         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3034         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3035         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3036         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3037         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3038         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3039         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3040         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3041         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3042         /* Only read FCOE on 82599 */
3043         if (hw->mac.type != ixgbe_mac_82598EB) {
3044                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3045                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3046                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3047                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3048                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3049         }
3050
3051         /* Flow Director Stats registers */
3052         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3053         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3054
3055         /* MACsec Stats registers */
3056         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3057         macsec_stats->out_pkts_encrypted +=
3058                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3059         macsec_stats->out_pkts_protected +=
3060                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3061         macsec_stats->out_octets_encrypted +=
3062                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3063         macsec_stats->out_octets_protected +=
3064                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3065         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3066         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3067         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3068         macsec_stats->in_pkts_unknownsci +=
3069                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3070         macsec_stats->in_octets_decrypted +=
3071                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3072         macsec_stats->in_octets_validated +=
3073                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3074         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3075         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3076         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3077         for (i = 0; i < 2; i++) {
3078                 macsec_stats->in_pkts_ok +=
3079                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3080                 macsec_stats->in_pkts_invalid +=
3081                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3082                 macsec_stats->in_pkts_notvalid +=
3083                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3084         }
3085         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3086         macsec_stats->in_pkts_notusingsa +=
3087                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3088 }
3089
3090 /*
3091  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3092  */
3093 static int
3094 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3095 {
3096         struct ixgbe_hw *hw =
3097                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3098         struct ixgbe_hw_stats *hw_stats =
3099                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3100         struct ixgbe_macsec_stats *macsec_stats =
3101                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3102                                 dev->data->dev_private);
3103         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3104         unsigned i;
3105
3106         total_missed_rx = 0;
3107         total_qbrc = 0;
3108         total_qprc = 0;
3109         total_qprdc = 0;
3110
3111         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3112                         &total_qbrc, &total_qprc, &total_qprdc);
3113
3114         if (stats == NULL)
3115                 return -EINVAL;
3116
3117         /* Fill out the rte_eth_stats statistics structure */
3118         stats->ipackets = total_qprc;
3119         stats->ibytes = total_qbrc;
3120         stats->opackets = hw_stats->gptc;
3121         stats->obytes = hw_stats->gotc;
3122
3123         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3124                 stats->q_ipackets[i] = hw_stats->qprc[i];
3125                 stats->q_opackets[i] = hw_stats->qptc[i];
3126                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3127                 stats->q_obytes[i] = hw_stats->qbtc[i];
3128                 stats->q_errors[i] = hw_stats->qprdc[i];
3129         }
3130
3131         /* Rx Errors */
3132         stats->imissed  = total_missed_rx;
3133         stats->ierrors  = hw_stats->crcerrs +
3134                           hw_stats->mspdc +
3135                           hw_stats->rlec +
3136                           hw_stats->ruc +
3137                           hw_stats->roc +
3138                           hw_stats->illerrc +
3139                           hw_stats->errbc +
3140                           hw_stats->rfc +
3141                           hw_stats->fccrc +
3142                           hw_stats->fclast;
3143
3144         /* Tx Errors */
3145         stats->oerrors  = 0;
3146         return 0;
3147 }
3148
3149 static void
3150 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3151 {
3152         struct ixgbe_hw_stats *stats =
3153                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3154
3155         /* HW registers are cleared on read */
3156         ixgbe_dev_stats_get(dev, NULL);
3157
3158         /* Reset software totals */
3159         memset(stats, 0, sizeof(*stats));
3160 }
3161
3162 /* This function calculates the number of xstats based on the current config */
3163 static unsigned
3164 ixgbe_xstats_calc_num(void) {
3165         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3166                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3167                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3168 }
3169
3170 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3171         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3172 {
3173         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3174         unsigned stat, i, count;
3175
3176         if (xstats_names != NULL) {
3177                 count = 0;
3178
3179                 /* Note: limit >= cnt_stats checked upstream
3180                  * in rte_eth_xstats_names()
3181                  */
3182
3183                 /* Extended stats from ixgbe_hw_stats */
3184                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3185                         snprintf(xstats_names[count].name,
3186                                 sizeof(xstats_names[count].name),
3187                                 "%s",
3188                                 rte_ixgbe_stats_strings[i].name);
3189                         count++;
3190                 }
3191
3192                 /* MACsec Stats */
3193                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3194                         snprintf(xstats_names[count].name,
3195                                 sizeof(xstats_names[count].name),
3196                                 "%s",
3197                                 rte_ixgbe_macsec_strings[i].name);
3198                         count++;
3199                 }
3200
3201                 /* RX Priority Stats */
3202                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3203                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3204                                 snprintf(xstats_names[count].name,
3205                                         sizeof(xstats_names[count].name),
3206                                         "rx_priority%u_%s", i,
3207                                         rte_ixgbe_rxq_strings[stat].name);
3208                                 count++;
3209                         }
3210                 }
3211
3212                 /* TX Priority Stats */
3213                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3214                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3215                                 snprintf(xstats_names[count].name,
3216                                         sizeof(xstats_names[count].name),
3217                                         "tx_priority%u_%s", i,
3218                                         rte_ixgbe_txq_strings[stat].name);
3219                                 count++;
3220                         }
3221                 }
3222         }
3223         return cnt_stats;
3224 }
3225
3226 static int ixgbe_dev_xstats_get_names_by_id(
3227         struct rte_eth_dev *dev,
3228         struct rte_eth_xstat_name *xstats_names,
3229         const uint64_t *ids,
3230         unsigned int limit)
3231 {
3232         if (!ids) {
3233                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3234                 unsigned int stat, i, count;
3235
3236                 if (xstats_names != NULL) {
3237                         count = 0;
3238
3239                         /* Note: limit >= cnt_stats checked upstream
3240                          * in rte_eth_xstats_names()
3241                          */
3242
3243                         /* Extended stats from ixgbe_hw_stats */
3244                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3245                                 snprintf(xstats_names[count].name,
3246                                         sizeof(xstats_names[count].name),
3247                                         "%s",
3248                                         rte_ixgbe_stats_strings[i].name);
3249                                 count++;
3250                         }
3251
3252                         /* MACsec Stats */
3253                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3254                                 snprintf(xstats_names[count].name,
3255                                         sizeof(xstats_names[count].name),
3256                                         "%s",
3257                                         rte_ixgbe_macsec_strings[i].name);
3258                                 count++;
3259                         }
3260
3261                         /* RX Priority Stats */
3262                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3263                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3264                                         snprintf(xstats_names[count].name,
3265                                             sizeof(xstats_names[count].name),
3266                                             "rx_priority%u_%s", i,
3267                                             rte_ixgbe_rxq_strings[stat].name);
3268                                         count++;
3269                                 }
3270                         }
3271
3272                         /* TX Priority Stats */
3273                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3274                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3275                                         snprintf(xstats_names[count].name,
3276                                             sizeof(xstats_names[count].name),
3277                                             "tx_priority%u_%s", i,
3278                                             rte_ixgbe_txq_strings[stat].name);
3279                                         count++;
3280                                 }
3281                         }
3282                 }
3283                 return cnt_stats;
3284         }
3285
3286         uint16_t i;
3287         uint16_t size = ixgbe_xstats_calc_num();
3288         struct rte_eth_xstat_name xstats_names_copy[size];
3289
3290         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3291                         size);
3292
3293         for (i = 0; i < limit; i++) {
3294                 if (ids[i] >= size) {
3295                         PMD_INIT_LOG(ERR, "id value isn't valid");
3296                         return -1;
3297                 }
3298                 strcpy(xstats_names[i].name,
3299                                 xstats_names_copy[ids[i]].name);
3300         }
3301         return limit;
3302 }
3303
3304 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3305         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3306 {
3307         unsigned i;
3308
3309         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3310                 return -ENOMEM;
3311
3312         if (xstats_names != NULL)
3313                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3314                         snprintf(xstats_names[i].name,
3315                                 sizeof(xstats_names[i].name),
3316                                 "%s", rte_ixgbevf_stats_strings[i].name);
3317         return IXGBEVF_NB_XSTATS;
3318 }
3319
3320 static int
3321 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3322                                          unsigned n)
3323 {
3324         struct ixgbe_hw *hw =
3325                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3326         struct ixgbe_hw_stats *hw_stats =
3327                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3328         struct ixgbe_macsec_stats *macsec_stats =
3329                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3330                                 dev->data->dev_private);
3331         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3332         unsigned i, stat, count = 0;
3333
3334         count = ixgbe_xstats_calc_num();
3335
3336         if (n < count)
3337                 return count;
3338
3339         total_missed_rx = 0;
3340         total_qbrc = 0;
3341         total_qprc = 0;
3342         total_qprdc = 0;
3343
3344         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3345                         &total_qbrc, &total_qprc, &total_qprdc);
3346
3347         /* If this is a reset xstats is NULL, and we have cleared the
3348          * registers by reading them.
3349          */
3350         if (!xstats)
3351                 return 0;
3352
3353         /* Extended stats from ixgbe_hw_stats */
3354         count = 0;
3355         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3356                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3357                                 rte_ixgbe_stats_strings[i].offset);
3358                 xstats[count].id = count;
3359                 count++;
3360         }
3361
3362         /* MACsec Stats */
3363         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3364                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3365                                 rte_ixgbe_macsec_strings[i].offset);
3366                 xstats[count].id = count;
3367                 count++;
3368         }
3369
3370         /* RX Priority Stats */
3371         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3372                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3373                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3374                                         rte_ixgbe_rxq_strings[stat].offset +
3375                                         (sizeof(uint64_t) * i));
3376                         xstats[count].id = count;
3377                         count++;
3378                 }
3379         }
3380
3381         /* TX Priority Stats */
3382         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3383                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3384                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3385                                         rte_ixgbe_txq_strings[stat].offset +
3386                                         (sizeof(uint64_t) * i));
3387                         xstats[count].id = count;
3388                         count++;
3389                 }
3390         }
3391         return count;
3392 }
3393
3394 static int
3395 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3396                 uint64_t *values, unsigned int n)
3397 {
3398         if (!ids) {
3399                 struct ixgbe_hw *hw =
3400                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3401                 struct ixgbe_hw_stats *hw_stats =
3402                                 IXGBE_DEV_PRIVATE_TO_STATS(
3403                                                 dev->data->dev_private);
3404                 struct ixgbe_macsec_stats *macsec_stats =
3405                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3406                                         dev->data->dev_private);
3407                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3408                 unsigned int i, stat, count = 0;
3409
3410                 count = ixgbe_xstats_calc_num();
3411
3412                 if (!ids && n < count)
3413                         return count;
3414
3415                 total_missed_rx = 0;
3416                 total_qbrc = 0;
3417                 total_qprc = 0;
3418                 total_qprdc = 0;
3419
3420                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3421                                 &total_missed_rx, &total_qbrc, &total_qprc,
3422                                 &total_qprdc);
3423
3424                 /* If this is a reset xstats is NULL, and we have cleared the
3425                  * registers by reading them.
3426                  */
3427                 if (!ids && !values)
3428                         return 0;
3429
3430                 /* Extended stats from ixgbe_hw_stats */
3431                 count = 0;
3432                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3433                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3434                                         rte_ixgbe_stats_strings[i].offset);
3435                         count++;
3436                 }
3437
3438                 /* MACsec Stats */
3439                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3440                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3441                                         rte_ixgbe_macsec_strings[i].offset);
3442                         count++;
3443                 }
3444
3445                 /* RX Priority Stats */
3446                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3447                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3448                                 values[count] =
3449                                         *(uint64_t *)(((char *)hw_stats) +
3450                                         rte_ixgbe_rxq_strings[stat].offset +
3451                                         (sizeof(uint64_t) * i));
3452                                 count++;
3453                         }
3454                 }
3455
3456                 /* TX Priority Stats */
3457                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3458                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3459                                 values[count] =
3460                                         *(uint64_t *)(((char *)hw_stats) +
3461                                         rte_ixgbe_txq_strings[stat].offset +
3462                                         (sizeof(uint64_t) * i));
3463                                 count++;
3464                         }
3465                 }
3466                 return count;
3467         }
3468
3469         uint16_t i;
3470         uint16_t size = ixgbe_xstats_calc_num();
3471         uint64_t values_copy[size];
3472
3473         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3474
3475         for (i = 0; i < n; i++) {
3476                 if (ids[i] >= size) {
3477                         PMD_INIT_LOG(ERR, "id value isn't valid");
3478                         return -1;
3479                 }
3480                 values[i] = values_copy[ids[i]];
3481         }
3482         return n;
3483 }
3484
3485 static void
3486 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3487 {
3488         struct ixgbe_hw_stats *stats =
3489                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3490         struct ixgbe_macsec_stats *macsec_stats =
3491                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3492                                 dev->data->dev_private);
3493
3494         unsigned count = ixgbe_xstats_calc_num();
3495
3496         /* HW registers are cleared on read */
3497         ixgbe_dev_xstats_get(dev, NULL, count);
3498
3499         /* Reset software totals */
3500         memset(stats, 0, sizeof(*stats));
3501         memset(macsec_stats, 0, sizeof(*macsec_stats));
3502 }
3503
3504 static void
3505 ixgbevf_update_stats(struct rte_eth_dev *dev)
3506 {
3507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3508         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3509                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3510
3511         /* Good Rx packet, include VF loopback */
3512         UPDATE_VF_STAT(IXGBE_VFGPRC,
3513             hw_stats->last_vfgprc, hw_stats->vfgprc);
3514
3515         /* Good Rx octets, include VF loopback */
3516         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3517             hw_stats->last_vfgorc, hw_stats->vfgorc);
3518
3519         /* Good Tx packet, include VF loopback */
3520         UPDATE_VF_STAT(IXGBE_VFGPTC,
3521             hw_stats->last_vfgptc, hw_stats->vfgptc);
3522
3523         /* Good Tx octets, include VF loopback */
3524         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3525             hw_stats->last_vfgotc, hw_stats->vfgotc);
3526
3527         /* Rx Multicst Packet */
3528         UPDATE_VF_STAT(IXGBE_VFMPRC,
3529             hw_stats->last_vfmprc, hw_stats->vfmprc);
3530 }
3531
3532 static int
3533 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3534                        unsigned n)
3535 {
3536         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3537                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3538         unsigned i;
3539
3540         if (n < IXGBEVF_NB_XSTATS)
3541                 return IXGBEVF_NB_XSTATS;
3542
3543         ixgbevf_update_stats(dev);
3544
3545         if (!xstats)
3546                 return 0;
3547
3548         /* Extended stats */
3549         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3550                 xstats[i].id = i;
3551                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3552                         rte_ixgbevf_stats_strings[i].offset);
3553         }
3554
3555         return IXGBEVF_NB_XSTATS;
3556 }
3557
3558 static int
3559 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3560 {
3561         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3562                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3563
3564         ixgbevf_update_stats(dev);
3565
3566         if (stats == NULL)
3567                 return -EINVAL;
3568
3569         stats->ipackets = hw_stats->vfgprc;
3570         stats->ibytes = hw_stats->vfgorc;
3571         stats->opackets = hw_stats->vfgptc;
3572         stats->obytes = hw_stats->vfgotc;
3573         return 0;
3574 }
3575
3576 static void
3577 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3578 {
3579         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3580                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3581
3582         /* Sync HW register to the last stats */
3583         ixgbevf_dev_stats_get(dev, NULL);
3584
3585         /* reset HW current stats*/
3586         hw_stats->vfgprc = 0;
3587         hw_stats->vfgorc = 0;
3588         hw_stats->vfgptc = 0;
3589         hw_stats->vfgotc = 0;
3590 }
3591
3592 static int
3593 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3594 {
3595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596         u16 eeprom_verh, eeprom_verl;
3597         u32 etrack_id;
3598         int ret;
3599
3600         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3601         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3602
3603         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3604         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3605
3606         ret += 1; /* add the size of '\0' */
3607         if (fw_size < (u32)ret)
3608                 return ret;
3609         else
3610                 return 0;
3611 }
3612
3613 static void
3614 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3615 {
3616         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3619
3620         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3621         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3622         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3623                 /*
3624                  * When DCB/VT is off, maximum number of queues changes,
3625                  * except for 82598EB, which remains constant.
3626                  */
3627                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3628                                 hw->mac.type != ixgbe_mac_82598EB)
3629                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3630         }
3631         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3632         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3633         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3634         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3635         dev_info->max_vfs = pci_dev->max_vfs;
3636         if (hw->mac.type == ixgbe_mac_82598EB)
3637                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3638         else
3639                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3640         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3641         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3642         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3643                                      dev_info->rx_queue_offload_capa);
3644         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3645         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3646
3647         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3648                 .rx_thresh = {
3649                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3650                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3651                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3652                 },
3653                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3654                 .rx_drop_en = 0,
3655                 .offloads = 0,
3656         };
3657
3658         dev_info->default_txconf = (struct rte_eth_txconf) {
3659                 .tx_thresh = {
3660                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3661                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3662                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3663                 },
3664                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3665                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3666                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3667                              ETH_TXQ_FLAGS_NOOFFLOADS |
3668                              ETH_TXQ_FLAGS_IGNORE,
3669                 .offloads = 0,
3670         };
3671
3672         dev_info->rx_desc_lim = rx_desc_lim;
3673         dev_info->tx_desc_lim = tx_desc_lim;
3674
3675         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3676         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3677         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3678
3679         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3680         if (hw->mac.type == ixgbe_mac_X540 ||
3681             hw->mac.type == ixgbe_mac_X540_vf ||
3682             hw->mac.type == ixgbe_mac_X550 ||
3683             hw->mac.type == ixgbe_mac_X550_vf) {
3684                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3685         }
3686         if (hw->mac.type == ixgbe_mac_X550) {
3687                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3688                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3689         }
3690 }
3691
3692 static const uint32_t *
3693 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3694 {
3695         static const uint32_t ptypes[] = {
3696                 /* For non-vec functions,
3697                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3698                  * for vec functions,
3699                  * refers to _recv_raw_pkts_vec().
3700                  */
3701                 RTE_PTYPE_L2_ETHER,
3702                 RTE_PTYPE_L3_IPV4,
3703                 RTE_PTYPE_L3_IPV4_EXT,
3704                 RTE_PTYPE_L3_IPV6,
3705                 RTE_PTYPE_L3_IPV6_EXT,
3706                 RTE_PTYPE_L4_SCTP,
3707                 RTE_PTYPE_L4_TCP,
3708                 RTE_PTYPE_L4_UDP,
3709                 RTE_PTYPE_TUNNEL_IP,
3710                 RTE_PTYPE_INNER_L3_IPV6,
3711                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3712                 RTE_PTYPE_INNER_L4_TCP,
3713                 RTE_PTYPE_INNER_L4_UDP,
3714                 RTE_PTYPE_UNKNOWN
3715         };
3716
3717         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3718             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3719             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3720             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3721                 return ptypes;
3722
3723 #if defined(RTE_ARCH_X86)
3724         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3725             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3726                 return ptypes;
3727 #endif
3728         return NULL;
3729 }
3730
3731 static void
3732 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3733                      struct rte_eth_dev_info *dev_info)
3734 {
3735         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737
3738         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3739         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3740         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3741         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3742         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3743         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3744         dev_info->max_vfs = pci_dev->max_vfs;
3745         if (hw->mac.type == ixgbe_mac_82598EB)
3746                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3747         else
3748                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3749         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3750         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3751                                      dev_info->rx_queue_offload_capa);
3752         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3753         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3754
3755         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3756                 .rx_thresh = {
3757                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3758                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3759                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3760                 },
3761                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3762                 .rx_drop_en = 0,
3763                 .offloads = 0,
3764         };
3765
3766         dev_info->default_txconf = (struct rte_eth_txconf) {
3767                 .tx_thresh = {
3768                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3769                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3770                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3771                 },
3772                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3773                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3774                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3775                              ETH_TXQ_FLAGS_NOOFFLOADS |
3776                              ETH_TXQ_FLAGS_IGNORE,
3777                 .offloads = 0,
3778         };
3779
3780         dev_info->rx_desc_lim = rx_desc_lim;
3781         dev_info->tx_desc_lim = tx_desc_lim;
3782 }
3783
3784 static int
3785 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3786                    int *link_up, int wait_to_complete)
3787 {
3788         /**
3789          * for a quick link status checking, wait_to_compelet == 0,
3790          * skip PF link status checking
3791          */
3792         bool no_pflink_check = wait_to_complete == 0;
3793         struct ixgbe_mbx_info *mbx = &hw->mbx;
3794         struct ixgbe_mac_info *mac = &hw->mac;
3795         uint32_t links_reg, in_msg;
3796         int ret_val = 0;
3797
3798         /* If we were hit with a reset drop the link */
3799         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3800                 mac->get_link_status = true;
3801
3802         if (!mac->get_link_status)
3803                 goto out;
3804
3805         /* if link status is down no point in checking to see if pf is up */
3806         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3807         if (!(links_reg & IXGBE_LINKS_UP))
3808                 goto out;
3809
3810         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3811          * before the link status is correct
3812          */
3813         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3814                 int i;
3815
3816                 for (i = 0; i < 5; i++) {
3817                         rte_delay_us(100);
3818                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3819
3820                         if (!(links_reg & IXGBE_LINKS_UP))
3821                                 goto out;
3822                 }
3823         }
3824
3825         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3826         case IXGBE_LINKS_SPEED_10G_82599:
3827                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3828                 if (hw->mac.type >= ixgbe_mac_X550) {
3829                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3830                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3831                 }
3832                 break;
3833         case IXGBE_LINKS_SPEED_1G_82599:
3834                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3835                 break;
3836         case IXGBE_LINKS_SPEED_100_82599:
3837                 *speed = IXGBE_LINK_SPEED_100_FULL;
3838                 if (hw->mac.type == ixgbe_mac_X550) {
3839                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3840                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3841                 }
3842                 break;
3843         case IXGBE_LINKS_SPEED_10_X550EM_A:
3844                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3845                 /* Since Reserved in older MAC's */
3846                 if (hw->mac.type >= ixgbe_mac_X550)
3847                         *speed = IXGBE_LINK_SPEED_10_FULL;
3848                 break;
3849         default:
3850                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3851         }
3852
3853         if (no_pflink_check) {
3854                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3855                         mac->get_link_status = true;
3856                 else
3857                         mac->get_link_status = false;
3858
3859                 goto out;
3860         }
3861         /* if the read failed it could just be a mailbox collision, best wait
3862          * until we are called again and don't report an error
3863          */
3864         if (mbx->ops.read(hw, &in_msg, 1, 0))
3865                 goto out;
3866
3867         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3868                 /* msg is not CTS and is NACK we must have lost CTS status */
3869                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3870                         ret_val = -1;
3871                 goto out;
3872         }
3873
3874         /* the pf is talking, if we timed out in the past we reinit */
3875         if (!mbx->timeout) {
3876                 ret_val = -1;
3877                 goto out;
3878         }
3879
3880         /* if we passed all the tests above then the link is up and we no
3881          * longer need to check for link
3882          */
3883         mac->get_link_status = false;
3884
3885 out:
3886         *link_up = !mac->get_link_status;
3887         return ret_val;
3888 }
3889
3890 /* return 0 means link status changed, -1 means not changed */
3891 static int
3892 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3893                             int wait_to_complete, int vf)
3894 {
3895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3896         struct rte_eth_link link;
3897         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3898         struct ixgbe_interrupt *intr =
3899                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3900         int link_up;
3901         int diag;
3902         u32 speed = 0;
3903         int wait = 1;
3904         bool autoneg = false;
3905
3906         memset(&link, 0, sizeof(link));
3907         link.link_status = ETH_LINK_DOWN;
3908         link.link_speed = ETH_SPEED_NUM_NONE;
3909         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3910         link.link_autoneg = ETH_LINK_AUTONEG;
3911
3912         hw->mac.get_link_status = true;
3913
3914         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3915                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3916                 speed = hw->phy.autoneg_advertised;
3917                 if (!speed)
3918                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3919                 ixgbe_setup_link(hw, speed, true);
3920         }
3921
3922         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3923         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3924                 wait = 0;
3925
3926         if (vf)
3927                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3928         else
3929                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3930
3931         if (diag != 0) {
3932                 link.link_speed = ETH_SPEED_NUM_100M;
3933                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3934                 return rte_eth_linkstatus_set(dev, &link);
3935         }
3936
3937         if (link_up == 0) {
3938                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3939                 return rte_eth_linkstatus_set(dev, &link);
3940         }
3941
3942         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3943         link.link_status = ETH_LINK_UP;
3944         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3945
3946         switch (link_speed) {
3947         default:
3948         case IXGBE_LINK_SPEED_UNKNOWN:
3949                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3950                 link.link_speed = ETH_SPEED_NUM_100M;
3951                 break;
3952
3953         case IXGBE_LINK_SPEED_100_FULL:
3954                 link.link_speed = ETH_SPEED_NUM_100M;
3955                 break;
3956
3957         case IXGBE_LINK_SPEED_1GB_FULL:
3958                 link.link_speed = ETH_SPEED_NUM_1G;
3959                 break;
3960
3961         case IXGBE_LINK_SPEED_2_5GB_FULL:
3962                 link.link_speed = ETH_SPEED_NUM_2_5G;
3963                 break;
3964
3965         case IXGBE_LINK_SPEED_5GB_FULL:
3966                 link.link_speed = ETH_SPEED_NUM_5G;
3967                 break;
3968
3969         case IXGBE_LINK_SPEED_10GB_FULL:
3970                 link.link_speed = ETH_SPEED_NUM_10G;
3971                 break;
3972         }
3973
3974         return rte_eth_linkstatus_set(dev, &link);
3975 }
3976
3977 static int
3978 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3979 {
3980         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3981 }
3982
3983 static int
3984 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3985 {
3986         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3987 }
3988
3989 static void
3990 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3991 {
3992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3993         uint32_t fctrl;
3994
3995         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3996         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3997         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3998 }
3999
4000 static void
4001 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4002 {
4003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4004         uint32_t fctrl;
4005
4006         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4007         fctrl &= (~IXGBE_FCTRL_UPE);
4008         if (dev->data->all_multicast == 1)
4009                 fctrl |= IXGBE_FCTRL_MPE;
4010         else
4011                 fctrl &= (~IXGBE_FCTRL_MPE);
4012         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4013 }
4014
4015 static void
4016 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4017 {
4018         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4019         uint32_t fctrl;
4020
4021         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4022         fctrl |= IXGBE_FCTRL_MPE;
4023         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4024 }
4025
4026 static void
4027 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4028 {
4029         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4030         uint32_t fctrl;
4031
4032         if (dev->data->promiscuous == 1)
4033                 return; /* must remain in all_multicast mode */
4034
4035         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4036         fctrl &= (~IXGBE_FCTRL_MPE);
4037         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4038 }
4039
4040 /**
4041  * It clears the interrupt causes and enables the interrupt.
4042  * It will be called once only during nic initialized.
4043  *
4044  * @param dev
4045  *  Pointer to struct rte_eth_dev.
4046  * @param on
4047  *  Enable or Disable.
4048  *
4049  * @return
4050  *  - On success, zero.
4051  *  - On failure, a negative value.
4052  */
4053 static int
4054 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4055 {
4056         struct ixgbe_interrupt *intr =
4057                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4058
4059         ixgbe_dev_link_status_print(dev);
4060         if (on)
4061                 intr->mask |= IXGBE_EICR_LSC;
4062         else
4063                 intr->mask &= ~IXGBE_EICR_LSC;
4064
4065         return 0;
4066 }
4067
4068 /**
4069  * It clears the interrupt causes and enables the interrupt.
4070  * It will be called once only during nic initialized.
4071  *
4072  * @param dev
4073  *  Pointer to struct rte_eth_dev.
4074  *
4075  * @return
4076  *  - On success, zero.
4077  *  - On failure, a negative value.
4078  */
4079 static int
4080 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4081 {
4082         struct ixgbe_interrupt *intr =
4083                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4084
4085         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4086
4087         return 0;
4088 }
4089
4090 /**
4091  * It clears the interrupt causes and enables the interrupt.
4092  * It will be called once only during nic initialized.
4093  *
4094  * @param dev
4095  *  Pointer to struct rte_eth_dev.
4096  *
4097  * @return
4098  *  - On success, zero.
4099  *  - On failure, a negative value.
4100  */
4101 static int
4102 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4103 {
4104         struct ixgbe_interrupt *intr =
4105                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4106
4107         intr->mask |= IXGBE_EICR_LINKSEC;
4108
4109         return 0;
4110 }
4111
4112 /*
4113  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4114  *
4115  * @param dev
4116  *  Pointer to struct rte_eth_dev.
4117  *
4118  * @return
4119  *  - On success, zero.
4120  *  - On failure, a negative value.
4121  */
4122 static int
4123 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4124 {
4125         uint32_t eicr;
4126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         struct ixgbe_interrupt *intr =
4128                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4129
4130         /* clear all cause mask */
4131         ixgbe_disable_intr(hw);
4132
4133         /* read-on-clear nic registers here */
4134         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4135         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4136
4137         intr->flags = 0;
4138
4139         /* set flag for async link update */
4140         if (eicr & IXGBE_EICR_LSC)
4141                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4142
4143         if (eicr & IXGBE_EICR_MAILBOX)
4144                 intr->flags |= IXGBE_FLAG_MAILBOX;
4145
4146         if (eicr & IXGBE_EICR_LINKSEC)
4147                 intr->flags |= IXGBE_FLAG_MACSEC;
4148
4149         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4150             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4151             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4152                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4153
4154         return 0;
4155 }
4156
4157 /**
4158  * It gets and then prints the link status.
4159  *
4160  * @param dev
4161  *  Pointer to struct rte_eth_dev.
4162  *
4163  * @return
4164  *  - On success, zero.
4165  *  - On failure, a negative value.
4166  */
4167 static void
4168 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4169 {
4170         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4171         struct rte_eth_link link;
4172
4173         rte_eth_linkstatus_get(dev, &link);
4174
4175         if (link.link_status) {
4176                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4177                                         (int)(dev->data->port_id),
4178                                         (unsigned)link.link_speed,
4179                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4180                                         "full-duplex" : "half-duplex");
4181         } else {
4182                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4183                                 (int)(dev->data->port_id));
4184         }
4185         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4186                                 pci_dev->addr.domain,
4187                                 pci_dev->addr.bus,
4188                                 pci_dev->addr.devid,
4189                                 pci_dev->addr.function);
4190 }
4191
4192 /*
4193  * It executes link_update after knowing an interrupt occurred.
4194  *
4195  * @param dev
4196  *  Pointer to struct rte_eth_dev.
4197  *
4198  * @return
4199  *  - On success, zero.
4200  *  - On failure, a negative value.
4201  */
4202 static int
4203 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4204                            struct rte_intr_handle *intr_handle)
4205 {
4206         struct ixgbe_interrupt *intr =
4207                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4208         int64_t timeout;
4209         struct ixgbe_hw *hw =
4210                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211
4212         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4213
4214         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4215                 ixgbe_pf_mbx_process(dev);
4216                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4217         }
4218
4219         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4220                 ixgbe_handle_lasi(hw);
4221                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4222         }
4223
4224         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4225                 struct rte_eth_link link;
4226
4227                 /* get the link status before link update, for predicting later */
4228                 rte_eth_linkstatus_get(dev, &link);
4229
4230                 ixgbe_dev_link_update(dev, 0);
4231
4232                 /* likely to up */
4233                 if (!link.link_status)
4234                         /* handle it 1 sec later, wait it being stable */
4235                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4236                 /* likely to down */
4237                 else
4238                         /* handle it 4 sec later, wait it being stable */
4239                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4240
4241                 ixgbe_dev_link_status_print(dev);
4242                 if (rte_eal_alarm_set(timeout * 1000,
4243                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4244                         PMD_DRV_LOG(ERR, "Error setting alarm");
4245                 else {
4246                         /* remember original mask */
4247                         intr->mask_original = intr->mask;
4248                         /* only disable lsc interrupt */
4249                         intr->mask &= ~IXGBE_EIMS_LSC;
4250                 }
4251         }
4252
4253         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4254         ixgbe_enable_intr(dev);
4255         rte_intr_enable(intr_handle);
4256
4257         return 0;
4258 }
4259
4260 /**
4261  * Interrupt handler which shall be registered for alarm callback for delayed
4262  * handling specific interrupt to wait for the stable nic state. As the
4263  * NIC interrupt state is not stable for ixgbe after link is just down,
4264  * it needs to wait 4 seconds to get the stable status.
4265  *
4266  * @param handle
4267  *  Pointer to interrupt handle.
4268  * @param param
4269  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4270  *
4271  * @return
4272  *  void
4273  */
4274 static void
4275 ixgbe_dev_interrupt_delayed_handler(void *param)
4276 {
4277         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4278         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4279         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4280         struct ixgbe_interrupt *intr =
4281                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4282         struct ixgbe_hw *hw =
4283                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4284         uint32_t eicr;
4285
4286         ixgbe_disable_intr(hw);
4287
4288         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4289         if (eicr & IXGBE_EICR_MAILBOX)
4290                 ixgbe_pf_mbx_process(dev);
4291
4292         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4293                 ixgbe_handle_lasi(hw);
4294                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4295         }
4296
4297         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4298                 ixgbe_dev_link_update(dev, 0);
4299                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4300                 ixgbe_dev_link_status_print(dev);
4301                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4302                                               NULL);
4303         }
4304
4305         if (intr->flags & IXGBE_FLAG_MACSEC) {
4306                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4307                                               NULL);
4308                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4309         }
4310
4311         /* restore original mask */
4312         intr->mask = intr->mask_original;
4313         intr->mask_original = 0;
4314
4315         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4316         ixgbe_enable_intr(dev);
4317         rte_intr_enable(intr_handle);
4318 }
4319
4320 /**
4321  * Interrupt handler triggered by NIC  for handling
4322  * specific interrupt.
4323  *
4324  * @param handle
4325  *  Pointer to interrupt handle.
4326  * @param param
4327  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4328  *
4329  * @return
4330  *  void
4331  */
4332 static void
4333 ixgbe_dev_interrupt_handler(void *param)
4334 {
4335         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4336
4337         ixgbe_dev_interrupt_get_status(dev);
4338         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4339 }
4340
4341 static int
4342 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4343 {
4344         struct ixgbe_hw *hw;
4345
4346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4348 }
4349
4350 static int
4351 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4352 {
4353         struct ixgbe_hw *hw;
4354
4355         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4356         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4357 }
4358
4359 static int
4360 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4361 {
4362         struct ixgbe_hw *hw;
4363         uint32_t mflcn_reg;
4364         uint32_t fccfg_reg;
4365         int rx_pause;
4366         int tx_pause;
4367
4368         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4369
4370         fc_conf->pause_time = hw->fc.pause_time;
4371         fc_conf->high_water = hw->fc.high_water[0];
4372         fc_conf->low_water = hw->fc.low_water[0];
4373         fc_conf->send_xon = hw->fc.send_xon;
4374         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4375
4376         /*
4377          * Return rx_pause status according to actual setting of
4378          * MFLCN register.
4379          */
4380         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4381         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4382                 rx_pause = 1;
4383         else
4384                 rx_pause = 0;
4385
4386         /*
4387          * Return tx_pause status according to actual setting of
4388          * FCCFG register.
4389          */
4390         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4391         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4392                 tx_pause = 1;
4393         else
4394                 tx_pause = 0;
4395
4396         if (rx_pause && tx_pause)
4397                 fc_conf->mode = RTE_FC_FULL;
4398         else if (rx_pause)
4399                 fc_conf->mode = RTE_FC_RX_PAUSE;
4400         else if (tx_pause)
4401                 fc_conf->mode = RTE_FC_TX_PAUSE;
4402         else
4403                 fc_conf->mode = RTE_FC_NONE;
4404
4405         return 0;
4406 }
4407
4408 static int
4409 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4410 {
4411         struct ixgbe_hw *hw;
4412         int err;
4413         uint32_t rx_buf_size;
4414         uint32_t max_high_water;
4415         uint32_t mflcn;
4416         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4417                 ixgbe_fc_none,
4418                 ixgbe_fc_rx_pause,
4419                 ixgbe_fc_tx_pause,
4420                 ixgbe_fc_full
4421         };
4422
4423         PMD_INIT_FUNC_TRACE();
4424
4425         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4426         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4427         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4428
4429         /*
4430          * At least reserve one Ethernet frame for watermark
4431          * high_water/low_water in kilo bytes for ixgbe
4432          */
4433         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4434         if ((fc_conf->high_water > max_high_water) ||
4435                 (fc_conf->high_water < fc_conf->low_water)) {
4436                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4437                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4438                 return -EINVAL;
4439         }
4440
4441         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4442         hw->fc.pause_time     = fc_conf->pause_time;
4443         hw->fc.high_water[0]  = fc_conf->high_water;
4444         hw->fc.low_water[0]   = fc_conf->low_water;
4445         hw->fc.send_xon       = fc_conf->send_xon;
4446         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4447
4448         err = ixgbe_fc_enable(hw);
4449
4450         /* Not negotiated is not an error case */
4451         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4452
4453                 /* check if we want to forward MAC frames - driver doesn't have native
4454                  * capability to do that, so we'll write the registers ourselves */
4455
4456                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4457
4458                 /* set or clear MFLCN.PMCF bit depending on configuration */
4459                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4460                         mflcn |= IXGBE_MFLCN_PMCF;
4461                 else
4462                         mflcn &= ~IXGBE_MFLCN_PMCF;
4463
4464                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4465                 IXGBE_WRITE_FLUSH(hw);
4466
4467                 return 0;
4468         }
4469
4470         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4471         return -EIO;
4472 }
4473
4474 /**
4475  *  ixgbe_pfc_enable_generic - Enable flow control
4476  *  @hw: pointer to hardware structure
4477  *  @tc_num: traffic class number
4478  *  Enable flow control according to the current settings.
4479  */
4480 static int
4481 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4482 {
4483         int ret_val = 0;
4484         uint32_t mflcn_reg, fccfg_reg;
4485         uint32_t reg;
4486         uint32_t fcrtl, fcrth;
4487         uint8_t i;
4488         uint8_t nb_rx_en;
4489
4490         /* Validate the water mark configuration */
4491         if (!hw->fc.pause_time) {
4492                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4493                 goto out;
4494         }
4495
4496         /* Low water mark of zero causes XOFF floods */
4497         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4498                  /* High/Low water can not be 0 */
4499                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4500                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4501                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4502                         goto out;
4503                 }
4504
4505                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4506                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4507                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4508                         goto out;
4509                 }
4510         }
4511         /* Negotiate the fc mode to use */
4512         ixgbe_fc_autoneg(hw);
4513
4514         /* Disable any previous flow control settings */
4515         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4516         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4517
4518         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4519         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4520
4521         switch (hw->fc.current_mode) {
4522         case ixgbe_fc_none:
4523                 /*
4524                  * If the count of enabled RX Priority Flow control >1,
4525                  * and the TX pause can not be disabled
4526                  */
4527                 nb_rx_en = 0;
4528                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4529                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4530                         if (reg & IXGBE_FCRTH_FCEN)
4531                                 nb_rx_en++;
4532                 }
4533                 if (nb_rx_en > 1)
4534                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4535                 break;
4536         case ixgbe_fc_rx_pause:
4537                 /*
4538                  * Rx Flow control is enabled and Tx Flow control is
4539                  * disabled by software override. Since there really
4540                  * isn't a way to advertise that we are capable of RX
4541                  * Pause ONLY, we will advertise that we support both
4542                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4543                  * disable the adapter's ability to send PAUSE frames.
4544                  */
4545                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4546                 /*
4547                  * If the count of enabled RX Priority Flow control >1,
4548                  * and the TX pause can not be disabled
4549                  */
4550                 nb_rx_en = 0;
4551                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4552                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4553                         if (reg & IXGBE_FCRTH_FCEN)
4554                                 nb_rx_en++;
4555                 }
4556                 if (nb_rx_en > 1)
4557                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4558                 break;
4559         case ixgbe_fc_tx_pause:
4560                 /*
4561                  * Tx Flow control is enabled, and Rx Flow control is
4562                  * disabled by software override.
4563                  */
4564                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4565                 break;
4566         case ixgbe_fc_full:
4567                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4568                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4569                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4570                 break;
4571         default:
4572                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4573                 ret_val = IXGBE_ERR_CONFIG;
4574                 goto out;
4575         }
4576
4577         /* Set 802.3x based flow control settings. */
4578         mflcn_reg |= IXGBE_MFLCN_DPF;
4579         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4580         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4581
4582         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4583         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4584                 hw->fc.high_water[tc_num]) {
4585                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4586                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4587                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4588         } else {
4589                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4590                 /*
4591                  * In order to prevent Tx hangs when the internal Tx
4592                  * switch is enabled we must set the high water mark
4593                  * to the maximum FCRTH value.  This allows the Tx
4594                  * switch to function even under heavy Rx workloads.
4595                  */
4596                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4597         }
4598         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4599
4600         /* Configure pause time (2 TCs per register) */
4601         reg = hw->fc.pause_time * 0x00010001;
4602         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4603                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4604
4605         /* Configure flow control refresh threshold value */
4606         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4607
4608 out:
4609         return ret_val;
4610 }
4611
4612 static int
4613 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4614 {
4615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4616         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4617
4618         if (hw->mac.type != ixgbe_mac_82598EB) {
4619                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4620         }
4621         return ret_val;
4622 }
4623
4624 static int
4625 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4626 {
4627         int err;
4628         uint32_t rx_buf_size;
4629         uint32_t max_high_water;
4630         uint8_t tc_num;
4631         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4632         struct ixgbe_hw *hw =
4633                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634         struct ixgbe_dcb_config *dcb_config =
4635                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4636
4637         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4638                 ixgbe_fc_none,
4639                 ixgbe_fc_rx_pause,
4640                 ixgbe_fc_tx_pause,
4641                 ixgbe_fc_full
4642         };
4643
4644         PMD_INIT_FUNC_TRACE();
4645
4646         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4647         tc_num = map[pfc_conf->priority];
4648         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4649         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4650         /*
4651          * At least reserve one Ethernet frame for watermark
4652          * high_water/low_water in kilo bytes for ixgbe
4653          */
4654         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4655         if ((pfc_conf->fc.high_water > max_high_water) ||
4656             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4657                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4658                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4659                 return -EINVAL;
4660         }
4661
4662         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4663         hw->fc.pause_time = pfc_conf->fc.pause_time;
4664         hw->fc.send_xon = pfc_conf->fc.send_xon;
4665         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4666         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4667
4668         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4669
4670         /* Not negotiated is not an error case */
4671         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4672                 return 0;
4673
4674         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4675         return -EIO;
4676 }
4677
4678 static int
4679 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4680                           struct rte_eth_rss_reta_entry64 *reta_conf,
4681                           uint16_t reta_size)
4682 {
4683         uint16_t i, sp_reta_size;
4684         uint8_t j, mask;
4685         uint32_t reta, r;
4686         uint16_t idx, shift;
4687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4688         uint32_t reta_reg;
4689
4690         PMD_INIT_FUNC_TRACE();
4691
4692         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4693                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4694                         "NIC.");
4695                 return -ENOTSUP;
4696         }
4697
4698         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4699         if (reta_size != sp_reta_size) {
4700                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4701                         "(%d) doesn't match the number hardware can supported "
4702                         "(%d)", reta_size, sp_reta_size);
4703                 return -EINVAL;
4704         }
4705
4706         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4707                 idx = i / RTE_RETA_GROUP_SIZE;
4708                 shift = i % RTE_RETA_GROUP_SIZE;
4709                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4710                                                 IXGBE_4_BIT_MASK);
4711                 if (!mask)
4712                         continue;
4713                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4714                 if (mask == IXGBE_4_BIT_MASK)
4715                         r = 0;
4716                 else
4717                         r = IXGBE_READ_REG(hw, reta_reg);
4718                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4719                         if (mask & (0x1 << j))
4720                                 reta |= reta_conf[idx].reta[shift + j] <<
4721                                                         (CHAR_BIT * j);
4722                         else
4723                                 reta |= r & (IXGBE_8_BIT_MASK <<
4724                                                 (CHAR_BIT * j));
4725                 }
4726                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4727         }
4728
4729         return 0;
4730 }
4731
4732 static int
4733 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4734                          struct rte_eth_rss_reta_entry64 *reta_conf,
4735                          uint16_t reta_size)
4736 {
4737         uint16_t i, sp_reta_size;
4738         uint8_t j, mask;
4739         uint32_t reta;
4740         uint16_t idx, shift;
4741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742         uint32_t reta_reg;
4743
4744         PMD_INIT_FUNC_TRACE();
4745         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4746         if (reta_size != sp_reta_size) {
4747                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4748                         "(%d) doesn't match the number hardware can supported "
4749                         "(%d)", reta_size, sp_reta_size);
4750                 return -EINVAL;
4751         }
4752
4753         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4754                 idx = i / RTE_RETA_GROUP_SIZE;
4755                 shift = i % RTE_RETA_GROUP_SIZE;
4756                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4757                                                 IXGBE_4_BIT_MASK);
4758                 if (!mask)
4759                         continue;
4760
4761                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4762                 reta = IXGBE_READ_REG(hw, reta_reg);
4763                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4764                         if (mask & (0x1 << j))
4765                                 reta_conf[idx].reta[shift + j] =
4766                                         ((reta >> (CHAR_BIT * j)) &
4767                                                 IXGBE_8_BIT_MASK);
4768                 }
4769         }
4770
4771         return 0;
4772 }
4773
4774 static int
4775 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4776                                 uint32_t index, uint32_t pool)
4777 {
4778         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4779         uint32_t enable_addr = 1;
4780
4781         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4782                              pool, enable_addr);
4783 }
4784
4785 static void
4786 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4787 {
4788         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789
4790         ixgbe_clear_rar(hw, index);
4791 }
4792
4793 static int
4794 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4795 {
4796         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4797
4798         ixgbe_remove_rar(dev, 0);
4799         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4800
4801         return 0;
4802 }
4803
4804 static bool
4805 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4806 {
4807         if (strcmp(dev->device->driver->name, drv->driver.name))
4808                 return false;
4809
4810         return true;
4811 }
4812
4813 bool
4814 is_ixgbe_supported(struct rte_eth_dev *dev)
4815 {
4816         return is_device_supported(dev, &rte_ixgbe_pmd);
4817 }
4818
4819 static int
4820 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4821 {
4822         uint32_t hlreg0;
4823         uint32_t maxfrs;
4824         struct ixgbe_hw *hw;
4825         struct rte_eth_dev_info dev_info;
4826         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4827         struct rte_eth_dev_data *dev_data = dev->data;
4828
4829         ixgbe_dev_info_get(dev, &dev_info);
4830
4831         /* check that mtu is within the allowed range */
4832         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4833                 return -EINVAL;
4834
4835         /* If device is started, refuse mtu that requires the support of
4836          * scattered packets when this feature has not been enabled before.
4837          */
4838         if (dev_data->dev_started && !dev_data->scattered_rx &&
4839             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4840              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4841                 PMD_INIT_LOG(ERR, "Stop port first.");
4842                 return -EINVAL;
4843         }
4844
4845         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4846         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4847
4848         /* switch to jumbo mode if needed */
4849         if (frame_size > ETHER_MAX_LEN) {
4850                 dev->data->dev_conf.rxmode.offloads |=
4851                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4852                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4853         } else {
4854                 dev->data->dev_conf.rxmode.offloads &=
4855                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4856                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4857         }
4858         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4859
4860         /* update max frame size */
4861         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4862
4863         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4864         maxfrs &= 0x0000FFFF;
4865         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4866         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4867
4868         return 0;
4869 }
4870
4871 /*
4872  * Virtual Function operations
4873  */
4874 static void
4875 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4876 {
4877         PMD_INIT_FUNC_TRACE();
4878
4879         /* Clear interrupt mask to stop from interrupts being generated */
4880         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4881
4882         IXGBE_WRITE_FLUSH(hw);
4883 }
4884
4885 static void
4886 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4887 {
4888         PMD_INIT_FUNC_TRACE();
4889
4890         /* VF enable interrupt autoclean */
4891         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4892         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4893         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4894
4895         IXGBE_WRITE_FLUSH(hw);
4896 }
4897
4898 static int
4899 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4900 {
4901         struct rte_eth_conf *conf = &dev->data->dev_conf;
4902         struct ixgbe_adapter *adapter =
4903                         (struct ixgbe_adapter *)dev->data->dev_private;
4904         struct rte_eth_dev_info dev_info;
4905         uint64_t rx_offloads;
4906         uint64_t tx_offloads;
4907
4908         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4909                      dev->data->port_id);
4910
4911         ixgbevf_dev_info_get(dev, &dev_info);
4912         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4913         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4914                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4915                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4916                             rx_offloads, dev_info.rx_offload_capa);
4917                 return -ENOTSUP;
4918         }
4919         tx_offloads = dev->data->dev_conf.txmode.offloads;
4920         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4921                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4922                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4923                             tx_offloads, dev_info.tx_offload_capa);
4924                 return -ENOTSUP;
4925         }
4926
4927         /*
4928          * VF has no ability to enable/disable HW CRC
4929          * Keep the persistent behavior the same as Host PF
4930          */
4931 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4932         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4933                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4934                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4935         }
4936 #else
4937         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4938                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4939                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4940         }
4941 #endif
4942
4943         /*
4944          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4945          * allocation or vector Rx preconditions we will reset it.
4946          */
4947         adapter->rx_bulk_alloc_allowed = true;
4948         adapter->rx_vec_allowed = true;
4949
4950         return 0;
4951 }
4952
4953 static int
4954 ixgbevf_dev_start(struct rte_eth_dev *dev)
4955 {
4956         struct ixgbe_hw *hw =
4957                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4958         uint32_t intr_vector = 0;
4959         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4960         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4961
4962         int err, mask = 0;
4963
4964         PMD_INIT_FUNC_TRACE();
4965
4966         err = hw->mac.ops.reset_hw(hw);
4967         if (err) {
4968                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4969                 return err;
4970         }
4971         hw->mac.get_link_status = true;
4972
4973         /* negotiate mailbox API version to use with the PF. */
4974         ixgbevf_negotiate_api(hw);
4975
4976         ixgbevf_dev_tx_init(dev);
4977
4978         /* This can fail when allocating mbufs for descriptor rings */
4979         err = ixgbevf_dev_rx_init(dev);
4980         if (err) {
4981                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4982                 ixgbe_dev_clear_queues(dev);
4983                 return err;
4984         }
4985
4986         /* Set vfta */
4987         ixgbevf_set_vfta_all(dev, 1);
4988
4989         /* Set HW strip */
4990         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4991                 ETH_VLAN_EXTEND_MASK;
4992         err = ixgbevf_vlan_offload_set(dev, mask);
4993         if (err) {
4994                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4995                 ixgbe_dev_clear_queues(dev);
4996                 return err;
4997         }
4998
4999         ixgbevf_dev_rxtx_start(dev);
5000
5001         ixgbevf_dev_link_update(dev, 0);
5002
5003         /* check and configure queue intr-vector mapping */
5004         if (rte_intr_cap_multiple(intr_handle) &&
5005             dev->data->dev_conf.intr_conf.rxq) {
5006                 /* According to datasheet, only vector 0/1/2 can be used,
5007                  * now only one vector is used for Rx queue
5008                  */
5009                 intr_vector = 1;
5010                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5011                         return -1;
5012         }
5013
5014         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5015                 intr_handle->intr_vec =
5016                         rte_zmalloc("intr_vec",
5017                                     dev->data->nb_rx_queues * sizeof(int), 0);
5018                 if (intr_handle->intr_vec == NULL) {
5019                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5020                                      " intr_vec", dev->data->nb_rx_queues);
5021                         return -ENOMEM;
5022                 }
5023         }
5024         ixgbevf_configure_msix(dev);
5025
5026         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5027          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5028          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5029          * is not cleared, it will fail when following rte_intr_enable( ) tries
5030          * to map Rx queue interrupt to other VFIO vectors.
5031          * So clear uio/vfio intr/evevnfd first to avoid failure.
5032          */
5033         rte_intr_disable(intr_handle);
5034
5035         rte_intr_enable(intr_handle);
5036
5037         /* Re-enable interrupt for VF */
5038         ixgbevf_intr_enable(hw);
5039
5040         return 0;
5041 }
5042
5043 static void
5044 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5045 {
5046         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5047         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5048         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5049
5050         PMD_INIT_FUNC_TRACE();
5051
5052         ixgbevf_intr_disable(hw);
5053
5054         hw->adapter_stopped = 1;
5055         ixgbe_stop_adapter(hw);
5056
5057         /*
5058           * Clear what we set, but we still keep shadow_vfta to
5059           * restore after device starts
5060           */
5061         ixgbevf_set_vfta_all(dev, 0);
5062
5063         /* Clear stored conf */
5064         dev->data->scattered_rx = 0;
5065
5066         ixgbe_dev_clear_queues(dev);
5067
5068         /* Clean datapath event and queue/vec mapping */
5069         rte_intr_efd_disable(intr_handle);
5070         if (intr_handle->intr_vec != NULL) {
5071                 rte_free(intr_handle->intr_vec);
5072                 intr_handle->intr_vec = NULL;
5073         }
5074 }
5075
5076 static void
5077 ixgbevf_dev_close(struct rte_eth_dev *dev)
5078 {
5079         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5080
5081         PMD_INIT_FUNC_TRACE();
5082
5083         ixgbe_reset_hw(hw);
5084
5085         ixgbevf_dev_stop(dev);
5086
5087         ixgbe_dev_free_queues(dev);
5088
5089         /**
5090          * Remove the VF MAC address ro ensure
5091          * that the VF traffic goes to the PF
5092          * after stop, close and detach of the VF
5093          **/
5094         ixgbevf_remove_mac_addr(dev, 0);
5095 }
5096
5097 /*
5098  * Reset VF device
5099  */
5100 static int
5101 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5102 {
5103         int ret;
5104
5105         ret = eth_ixgbevf_dev_uninit(dev);
5106         if (ret)
5107                 return ret;
5108
5109         ret = eth_ixgbevf_dev_init(dev);
5110
5111         return ret;
5112 }
5113
5114 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5115 {
5116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5117         struct ixgbe_vfta *shadow_vfta =
5118                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5119         int i = 0, j = 0, vfta = 0, mask = 1;
5120
5121         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5122                 vfta = shadow_vfta->vfta[i];
5123                 if (vfta) {
5124                         mask = 1;
5125                         for (j = 0; j < 32; j++) {
5126                                 if (vfta & mask)
5127                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5128                                                        on, false);
5129                                 mask <<= 1;
5130                         }
5131                 }
5132         }
5133
5134 }
5135
5136 static int
5137 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5138 {
5139         struct ixgbe_hw *hw =
5140                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5141         struct ixgbe_vfta *shadow_vfta =
5142                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5143         uint32_t vid_idx = 0;
5144         uint32_t vid_bit = 0;
5145         int ret = 0;
5146
5147         PMD_INIT_FUNC_TRACE();
5148
5149         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5150         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5151         if (ret) {
5152                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5153                 return ret;
5154         }
5155         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5156         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5157
5158         /* Save what we set and retore it after device reset */
5159         if (on)
5160                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5161         else
5162                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5163
5164         return 0;
5165 }
5166
5167 static void
5168 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5169 {
5170         struct ixgbe_hw *hw =
5171                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172         uint32_t ctrl;
5173
5174         PMD_INIT_FUNC_TRACE();
5175
5176         if (queue >= hw->mac.max_rx_queues)
5177                 return;
5178
5179         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5180         if (on)
5181                 ctrl |= IXGBE_RXDCTL_VME;
5182         else
5183                 ctrl &= ~IXGBE_RXDCTL_VME;
5184         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5185
5186         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5187 }
5188
5189 static int
5190 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5191 {
5192         struct ixgbe_rx_queue *rxq;
5193         uint16_t i;
5194         int on = 0;
5195
5196         /* VF function only support hw strip feature, others are not support */
5197         if (mask & ETH_VLAN_STRIP_MASK) {
5198                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5199                         rxq = dev->data->rx_queues[i];
5200                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5201                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5202                 }
5203         }
5204
5205         return 0;
5206 }
5207
5208 int
5209 ixgbe_vt_check(struct ixgbe_hw *hw)
5210 {
5211         uint32_t reg_val;
5212
5213         /* if Virtualization Technology is enabled */
5214         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5215         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5216                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5217                 return -1;
5218         }
5219
5220         return 0;
5221 }
5222
5223 static uint32_t
5224 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5225 {
5226         uint32_t vector = 0;
5227
5228         switch (hw->mac.mc_filter_type) {
5229         case 0:   /* use bits [47:36] of the address */
5230                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5231                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5232                 break;
5233         case 1:   /* use bits [46:35] of the address */
5234                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5235                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5236                 break;
5237         case 2:   /* use bits [45:34] of the address */
5238                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5239                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5240                 break;
5241         case 3:   /* use bits [43:32] of the address */
5242                 vector = ((uc_addr->addr_bytes[4]) |
5243                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5244                 break;
5245         default:  /* Invalid mc_filter_type */
5246                 break;
5247         }
5248
5249         /* vector can only be 12-bits or boundary will be exceeded */
5250         vector &= 0xFFF;
5251         return vector;
5252 }
5253
5254 static int
5255 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5256                         uint8_t on)
5257 {
5258         uint32_t vector;
5259         uint32_t uta_idx;
5260         uint32_t reg_val;
5261         uint32_t uta_shift;
5262         uint32_t rc;
5263         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5264         const uint32_t ixgbe_uta_bit_shift = 5;
5265         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5266         const uint32_t bit1 = 0x1;
5267
5268         struct ixgbe_hw *hw =
5269                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5270         struct ixgbe_uta_info *uta_info =
5271                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5272
5273         /* The UTA table only exists on 82599 hardware and newer */
5274         if (hw->mac.type < ixgbe_mac_82599EB)
5275                 return -ENOTSUP;
5276
5277         vector = ixgbe_uta_vector(hw, mac_addr);
5278         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5279         uta_shift = vector & ixgbe_uta_bit_mask;
5280
5281         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5282         if (rc == on)
5283                 return 0;
5284
5285         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5286         if (on) {
5287                 uta_info->uta_in_use++;
5288                 reg_val |= (bit1 << uta_shift);
5289                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5290         } else {
5291                 uta_info->uta_in_use--;
5292                 reg_val &= ~(bit1 << uta_shift);
5293                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5294         }
5295
5296         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5297
5298         if (uta_info->uta_in_use > 0)
5299                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5300                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5301         else
5302                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5303
5304         return 0;
5305 }
5306
5307 static int
5308 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5309 {
5310         int i;
5311         struct ixgbe_hw *hw =
5312                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5313         struct ixgbe_uta_info *uta_info =
5314                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5315
5316         /* The UTA table only exists on 82599 hardware and newer */
5317         if (hw->mac.type < ixgbe_mac_82599EB)
5318                 return -ENOTSUP;
5319
5320         if (on) {
5321                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5322                         uta_info->uta_shadow[i] = ~0;
5323                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5324                 }
5325         } else {
5326                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5327                         uta_info->uta_shadow[i] = 0;
5328                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5329                 }
5330         }
5331         return 0;
5332
5333 }
5334
5335 uint32_t
5336 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5337 {
5338         uint32_t new_val = orig_val;
5339
5340         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5341                 new_val |= IXGBE_VMOLR_AUPE;
5342         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5343                 new_val |= IXGBE_VMOLR_ROMPE;
5344         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5345                 new_val |= IXGBE_VMOLR_ROPE;
5346         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5347                 new_val |= IXGBE_VMOLR_BAM;
5348         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5349                 new_val |= IXGBE_VMOLR_MPE;
5350
5351         return new_val;
5352 }
5353
5354 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5355 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5356 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5357 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5358 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5359         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5360         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5361
5362 static int
5363 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5364                       struct rte_eth_mirror_conf *mirror_conf,
5365                       uint8_t rule_id, uint8_t on)
5366 {
5367         uint32_t mr_ctl, vlvf;
5368         uint32_t mp_lsb = 0;
5369         uint32_t mv_msb = 0;
5370         uint32_t mv_lsb = 0;
5371         uint32_t mp_msb = 0;
5372         uint8_t i = 0;
5373         int reg_index = 0;
5374         uint64_t vlan_mask = 0;
5375
5376         const uint8_t pool_mask_offset = 32;
5377         const uint8_t vlan_mask_offset = 32;
5378         const uint8_t dst_pool_offset = 8;
5379         const uint8_t rule_mr_offset  = 4;
5380         const uint8_t mirror_rule_mask = 0x0F;
5381
5382         struct ixgbe_mirror_info *mr_info =
5383                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5384         struct ixgbe_hw *hw =
5385                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5386         uint8_t mirror_type = 0;
5387
5388         if (ixgbe_vt_check(hw) < 0)
5389                 return -ENOTSUP;
5390
5391         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5392                 return -EINVAL;
5393
5394         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5395                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5396                             mirror_conf->rule_type);
5397                 return -EINVAL;
5398         }
5399
5400         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5401                 mirror_type |= IXGBE_MRCTL_VLME;
5402                 /* Check if vlan id is valid and find conresponding VLAN ID
5403                  * index in VLVF
5404                  */
5405                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5406                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5407                                 /* search vlan id related pool vlan filter
5408                                  * index
5409                                  */
5410                                 reg_index = ixgbe_find_vlvf_slot(
5411                                                 hw,
5412                                                 mirror_conf->vlan.vlan_id[i],
5413                                                 false);
5414                                 if (reg_index < 0)
5415                                         return -EINVAL;
5416                                 vlvf = IXGBE_READ_REG(hw,
5417                                                       IXGBE_VLVF(reg_index));
5418                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5419                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5420                                       mirror_conf->vlan.vlan_id[i]))
5421                                         vlan_mask |= (1ULL << reg_index);
5422                                 else
5423                                         return -EINVAL;
5424                         }
5425                 }
5426
5427                 if (on) {
5428                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5429                         mv_msb = vlan_mask >> vlan_mask_offset;
5430
5431                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5432                                                 mirror_conf->vlan.vlan_mask;
5433                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5434                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5435                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5436                                                 mirror_conf->vlan.vlan_id[i];
5437                         }
5438                 } else {
5439                         mv_lsb = 0;
5440                         mv_msb = 0;
5441                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5442                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5443                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5444                 }
5445         }
5446
5447         /**
5448          * if enable pool mirror, write related pool mask register,if disable
5449          * pool mirror, clear PFMRVM register
5450          */
5451         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5452                 mirror_type |= IXGBE_MRCTL_VPME;
5453                 if (on) {
5454                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5455                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5456                         mr_info->mr_conf[rule_id].pool_mask =
5457                                         mirror_conf->pool_mask;
5458
5459                 } else {
5460                         mp_lsb = 0;
5461                         mp_msb = 0;
5462                         mr_info->mr_conf[rule_id].pool_mask = 0;
5463                 }
5464         }
5465         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5466                 mirror_type |= IXGBE_MRCTL_UPME;
5467         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5468                 mirror_type |= IXGBE_MRCTL_DPME;
5469
5470         /* read  mirror control register and recalculate it */
5471         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5472
5473         if (on) {
5474                 mr_ctl |= mirror_type;
5475                 mr_ctl &= mirror_rule_mask;
5476                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5477         } else {
5478                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5479         }
5480
5481         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5482         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5483
5484         /* write mirrror control  register */
5485         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5486
5487         /* write pool mirrror control  register */
5488         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5489                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5490                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5491                                 mp_msb);
5492         }
5493         /* write VLAN mirrror control  register */
5494         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5495                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5496                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5497                                 mv_msb);
5498         }
5499
5500         return 0;
5501 }
5502
5503 static int
5504 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5505 {
5506         int mr_ctl = 0;
5507         uint32_t lsb_val = 0;
5508         uint32_t msb_val = 0;
5509         const uint8_t rule_mr_offset = 4;
5510
5511         struct ixgbe_hw *hw =
5512                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5513         struct ixgbe_mirror_info *mr_info =
5514                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5515
5516         if (ixgbe_vt_check(hw) < 0)
5517                 return -ENOTSUP;
5518
5519         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5520                 return -EINVAL;
5521
5522         memset(&mr_info->mr_conf[rule_id], 0,
5523                sizeof(struct rte_eth_mirror_conf));
5524
5525         /* clear PFVMCTL register */
5526         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5527
5528         /* clear pool mask register */
5529         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5530         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5531
5532         /* clear vlan mask register */
5533         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5534         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5535
5536         return 0;
5537 }
5538
5539 static int
5540 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5541 {
5542         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5543         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5544         uint32_t mask;
5545         struct ixgbe_hw *hw =
5546                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5547         uint32_t vec = IXGBE_MISC_VEC_ID;
5548
5549         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5550         if (rte_intr_allow_others(intr_handle))
5551                 vec = IXGBE_RX_VEC_START;
5552         mask |= (1 << vec);
5553         RTE_SET_USED(queue_id);
5554         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5555
5556         rte_intr_enable(intr_handle);
5557
5558         return 0;
5559 }
5560
5561 static int
5562 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5563 {
5564         uint32_t mask;
5565         struct ixgbe_hw *hw =
5566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5567         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5568         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5569         uint32_t vec = IXGBE_MISC_VEC_ID;
5570
5571         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5572         if (rte_intr_allow_others(intr_handle))
5573                 vec = IXGBE_RX_VEC_START;
5574         mask &= ~(1 << vec);
5575         RTE_SET_USED(queue_id);
5576         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5577
5578         return 0;
5579 }
5580
5581 static int
5582 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5583 {
5584         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5585         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5586         uint32_t mask;
5587         struct ixgbe_hw *hw =
5588                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5589         struct ixgbe_interrupt *intr =
5590                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5591
5592         if (queue_id < 16) {
5593                 ixgbe_disable_intr(hw);
5594                 intr->mask |= (1 << queue_id);
5595                 ixgbe_enable_intr(dev);
5596         } else if (queue_id < 32) {
5597                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5598                 mask &= (1 << queue_id);
5599                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5600         } else if (queue_id < 64) {
5601                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5602                 mask &= (1 << (queue_id - 32));
5603                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5604         }
5605         rte_intr_enable(intr_handle);
5606
5607         return 0;
5608 }
5609
5610 static int
5611 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5612 {
5613         uint32_t mask;
5614         struct ixgbe_hw *hw =
5615                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5616         struct ixgbe_interrupt *intr =
5617                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5618
5619         if (queue_id < 16) {
5620                 ixgbe_disable_intr(hw);
5621                 intr->mask &= ~(1 << queue_id);
5622                 ixgbe_enable_intr(dev);
5623         } else if (queue_id < 32) {
5624                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5625                 mask &= ~(1 << queue_id);
5626                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5627         } else if (queue_id < 64) {
5628                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5629                 mask &= ~(1 << (queue_id - 32));
5630                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5631         }
5632
5633         return 0;
5634 }
5635
5636 static void
5637 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5638                      uint8_t queue, uint8_t msix_vector)
5639 {
5640         uint32_t tmp, idx;
5641
5642         if (direction == -1) {
5643                 /* other causes */
5644                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5645                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5646                 tmp &= ~0xFF;
5647                 tmp |= msix_vector;
5648                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5649         } else {
5650                 /* rx or tx cause */
5651                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5652                 idx = ((16 * (queue & 1)) + (8 * direction));
5653                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5654                 tmp &= ~(0xFF << idx);
5655                 tmp |= (msix_vector << idx);
5656                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5657         }
5658 }
5659
5660 /**
5661  * set the IVAR registers, mapping interrupt causes to vectors
5662  * @param hw
5663  *  pointer to ixgbe_hw struct
5664  * @direction
5665  *  0 for Rx, 1 for Tx, -1 for other causes
5666  * @queue
5667  *  queue to map the corresponding interrupt to
5668  * @msix_vector
5669  *  the vector to map to the corresponding queue
5670  */
5671 static void
5672 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5673                    uint8_t queue, uint8_t msix_vector)
5674 {
5675         uint32_t tmp, idx;
5676
5677         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5678         if (hw->mac.type == ixgbe_mac_82598EB) {
5679                 if (direction == -1)
5680                         direction = 0;
5681                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5682                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5683                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5684                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5685                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5686         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5687                         (hw->mac.type == ixgbe_mac_X540) ||
5688                         (hw->mac.type == ixgbe_mac_X550)) {
5689                 if (direction == -1) {
5690                         /* other causes */
5691                         idx = ((queue & 1) * 8);
5692                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5693                         tmp &= ~(0xFF << idx);
5694                         tmp |= (msix_vector << idx);
5695                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5696                 } else {
5697                         /* rx or tx causes */
5698                         idx = ((16 * (queue & 1)) + (8 * direction));
5699                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5700                         tmp &= ~(0xFF << idx);
5701                         tmp |= (msix_vector << idx);
5702                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5703                 }
5704         }
5705 }
5706
5707 static void
5708 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5709 {
5710         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5711         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5712         struct ixgbe_hw *hw =
5713                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5714         uint32_t q_idx;
5715         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5716         uint32_t base = IXGBE_MISC_VEC_ID;
5717
5718         /* Configure VF other cause ivar */
5719         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5720
5721         /* won't configure msix register if no mapping is done
5722          * between intr vector and event fd.
5723          */
5724         if (!rte_intr_dp_is_en(intr_handle))
5725                 return;
5726
5727         if (rte_intr_allow_others(intr_handle)) {
5728                 base = IXGBE_RX_VEC_START;
5729                 vector_idx = IXGBE_RX_VEC_START;
5730         }
5731
5732         /* Configure all RX queues of VF */
5733         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5734                 /* Force all queue use vector 0,
5735                  * as IXGBE_VF_MAXMSIVECOTR = 1
5736                  */
5737                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5738                 intr_handle->intr_vec[q_idx] = vector_idx;
5739                 if (vector_idx < base + intr_handle->nb_efd - 1)
5740                         vector_idx++;
5741         }
5742 }
5743
5744 /**
5745  * Sets up the hardware to properly generate MSI-X interrupts
5746  * @hw
5747  *  board private structure
5748  */
5749 static void
5750 ixgbe_configure_msix(struct rte_eth_dev *dev)
5751 {
5752         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5753         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5754         struct ixgbe_hw *hw =
5755                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5756         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5757         uint32_t vec = IXGBE_MISC_VEC_ID;
5758         uint32_t mask;
5759         uint32_t gpie;
5760
5761         /* won't configure msix register if no mapping is done
5762          * between intr vector and event fd
5763          */
5764         if (!rte_intr_dp_is_en(intr_handle))
5765                 return;
5766
5767         if (rte_intr_allow_others(intr_handle))
5768                 vec = base = IXGBE_RX_VEC_START;
5769
5770         /* setup GPIE for MSI-x mode */
5771         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5772         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5773                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5774         /* auto clearing and auto setting corresponding bits in EIMS
5775          * when MSI-X interrupt is triggered
5776          */
5777         if (hw->mac.type == ixgbe_mac_82598EB) {
5778                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5779         } else {
5780                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5781                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5782         }
5783         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5784
5785         /* Populate the IVAR table and set the ITR values to the
5786          * corresponding register.
5787          */
5788         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5789              queue_id++) {
5790                 /* by default, 1:1 mapping */
5791                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5792                 intr_handle->intr_vec[queue_id] = vec;
5793                 if (vec < base + intr_handle->nb_efd - 1)
5794                         vec++;
5795         }
5796
5797         switch (hw->mac.type) {
5798         case ixgbe_mac_82598EB:
5799                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5800                                    IXGBE_MISC_VEC_ID);
5801                 break;
5802         case ixgbe_mac_82599EB:
5803         case ixgbe_mac_X540:
5804         case ixgbe_mac_X550:
5805                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5806                 break;
5807         default:
5808                 break;
5809         }
5810         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5811                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5812
5813         /* set up to autoclear timer, and the vectors */
5814         mask = IXGBE_EIMS_ENABLE_MASK;
5815         mask &= ~(IXGBE_EIMS_OTHER |
5816                   IXGBE_EIMS_MAILBOX |
5817                   IXGBE_EIMS_LSC);
5818
5819         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5820 }
5821
5822 int
5823 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5824                            uint16_t queue_idx, uint16_t tx_rate)
5825 {
5826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5827         struct rte_eth_rxmode *rxmode;
5828         uint32_t rf_dec, rf_int;
5829         uint32_t bcnrc_val;
5830         uint16_t link_speed = dev->data->dev_link.link_speed;
5831
5832         if (queue_idx >= hw->mac.max_tx_queues)
5833                 return -EINVAL;
5834
5835         if (tx_rate != 0) {
5836                 /* Calculate the rate factor values to set */
5837                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5838                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5839                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5840
5841                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5842                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5843                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5844                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5845         } else {
5846                 bcnrc_val = 0;
5847         }
5848
5849         rxmode = &dev->data->dev_conf.rxmode;
5850         /*
5851          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5852          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5853          * set as 0x4.
5854          */
5855         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5856             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5857                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5858                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5859         else
5860                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5861                         IXGBE_MMW_SIZE_DEFAULT);
5862
5863         /* Set RTTBCNRC of queue X */
5864         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5865         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5866         IXGBE_WRITE_FLUSH(hw);
5867
5868         return 0;
5869 }
5870
5871 static int
5872 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5873                      __attribute__((unused)) uint32_t index,
5874                      __attribute__((unused)) uint32_t pool)
5875 {
5876         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5877         int diag;
5878
5879         /*
5880          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5881          * operation. Trap this case to avoid exhausting the [very limited]
5882          * set of PF resources used to store VF MAC addresses.
5883          */
5884         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5885                 return -1;
5886         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5887         if (diag != 0)
5888                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5889                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5890                             mac_addr->addr_bytes[0],
5891                             mac_addr->addr_bytes[1],
5892                             mac_addr->addr_bytes[2],
5893                             mac_addr->addr_bytes[3],
5894                             mac_addr->addr_bytes[4],
5895                             mac_addr->addr_bytes[5],
5896                             diag);
5897         return diag;
5898 }
5899
5900 static void
5901 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5902 {
5903         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5904         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5905         struct ether_addr *mac_addr;
5906         uint32_t i;
5907         int diag;
5908
5909         /*
5910          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5911          * not support the deletion of a given MAC address.
5912          * Instead, it imposes to delete all MAC addresses, then to add again
5913          * all MAC addresses with the exception of the one to be deleted.
5914          */
5915         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5916
5917         /*
5918          * Add again all MAC addresses, with the exception of the deleted one
5919          * and of the permanent MAC address.
5920          */
5921         for (i = 0, mac_addr = dev->data->mac_addrs;
5922              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5923                 /* Skip the deleted MAC address */
5924                 if (i == index)
5925                         continue;
5926                 /* Skip NULL MAC addresses */
5927                 if (is_zero_ether_addr(mac_addr))
5928                         continue;
5929                 /* Skip the permanent MAC address */
5930                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5931                         continue;
5932                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5933                 if (diag != 0)
5934                         PMD_DRV_LOG(ERR,
5935                                     "Adding again MAC address "
5936                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5937                                     "diag=%d",
5938                                     mac_addr->addr_bytes[0],
5939                                     mac_addr->addr_bytes[1],
5940                                     mac_addr->addr_bytes[2],
5941                                     mac_addr->addr_bytes[3],
5942                                     mac_addr->addr_bytes[4],
5943                                     mac_addr->addr_bytes[5],
5944                                     diag);
5945         }
5946 }
5947
5948 static int
5949 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5950 {
5951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5952
5953         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5954
5955         return 0;
5956 }
5957
5958 int
5959 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5960                         struct rte_eth_syn_filter *filter,
5961                         bool add)
5962 {
5963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5964         struct ixgbe_filter_info *filter_info =
5965                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5966         uint32_t syn_info;
5967         uint32_t synqf;
5968
5969         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5970                 return -EINVAL;
5971
5972         syn_info = filter_info->syn_info;
5973
5974         if (add) {
5975                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5976                         return -EINVAL;
5977                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5978                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5979
5980                 if (filter->hig_pri)
5981                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5982                 else
5983                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5984         } else {
5985                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5986                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5987                         return -ENOENT;
5988                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5989         }
5990
5991         filter_info->syn_info = synqf;
5992         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5993         IXGBE_WRITE_FLUSH(hw);
5994         return 0;
5995 }
5996
5997 static int
5998 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5999                         struct rte_eth_syn_filter *filter)
6000 {
6001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6002         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6003
6004         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6005                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6006                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6007                 return 0;
6008         }
6009         return -ENOENT;
6010 }
6011
6012 static int
6013 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6014                         enum rte_filter_op filter_op,
6015                         void *arg)
6016 {
6017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6018         int ret;
6019
6020         MAC_TYPE_FILTER_SUP(hw->mac.type);
6021
6022         if (filter_op == RTE_ETH_FILTER_NOP)
6023                 return 0;
6024
6025         if (arg == NULL) {
6026                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6027                             filter_op);
6028                 return -EINVAL;
6029         }
6030
6031         switch (filter_op) {
6032         case RTE_ETH_FILTER_ADD:
6033                 ret = ixgbe_syn_filter_set(dev,
6034                                 (struct rte_eth_syn_filter *)arg,
6035                                 TRUE);
6036                 break;
6037         case RTE_ETH_FILTER_DELETE:
6038                 ret = ixgbe_syn_filter_set(dev,
6039                                 (struct rte_eth_syn_filter *)arg,
6040                                 FALSE);
6041                 break;
6042         case RTE_ETH_FILTER_GET:
6043                 ret = ixgbe_syn_filter_get(dev,
6044                                 (struct rte_eth_syn_filter *)arg);
6045                 break;
6046         default:
6047                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6048                 ret = -EINVAL;
6049                 break;
6050         }
6051
6052         return ret;
6053 }
6054
6055
6056 static inline enum ixgbe_5tuple_protocol
6057 convert_protocol_type(uint8_t protocol_value)
6058 {
6059         if (protocol_value == IPPROTO_TCP)
6060                 return IXGBE_FILTER_PROTOCOL_TCP;
6061         else if (protocol_value == IPPROTO_UDP)
6062                 return IXGBE_FILTER_PROTOCOL_UDP;
6063         else if (protocol_value == IPPROTO_SCTP)
6064                 return IXGBE_FILTER_PROTOCOL_SCTP;
6065         else
6066                 return IXGBE_FILTER_PROTOCOL_NONE;
6067 }
6068
6069 /* inject a 5-tuple filter to HW */
6070 static inline void
6071 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6072                            struct ixgbe_5tuple_filter *filter)
6073 {
6074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6075         int i;
6076         uint32_t ftqf, sdpqf;
6077         uint32_t l34timir = 0;
6078         uint8_t mask = 0xff;
6079
6080         i = filter->index;
6081
6082         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6083                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6084         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6085
6086         ftqf = (uint32_t)(filter->filter_info.proto &
6087                 IXGBE_FTQF_PROTOCOL_MASK);
6088         ftqf |= (uint32_t)((filter->filter_info.priority &
6089                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6090         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6091                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6092         if (filter->filter_info.dst_ip_mask == 0)
6093                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6094         if (filter->filter_info.src_port_mask == 0)
6095                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6096         if (filter->filter_info.dst_port_mask == 0)
6097                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6098         if (filter->filter_info.proto_mask == 0)
6099                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6100         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6101         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6102         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6103
6104         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6105         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6106         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6107         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6108
6109         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6110         l34timir |= (uint32_t)(filter->queue <<
6111                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6112         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6113 }
6114
6115 /*
6116  * add a 5tuple filter
6117  *
6118  * @param
6119  * dev: Pointer to struct rte_eth_dev.
6120  * index: the index the filter allocates.
6121  * filter: ponter to the filter that will be added.
6122  * rx_queue: the queue id the filter assigned to.
6123  *
6124  * @return
6125  *    - On success, zero.
6126  *    - On failure, a negative value.
6127  */
6128 static int
6129 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6130                         struct ixgbe_5tuple_filter *filter)
6131 {
6132         struct ixgbe_filter_info *filter_info =
6133                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6134         int i, idx, shift;
6135
6136         /*
6137          * look for an unused 5tuple filter index,
6138          * and insert the filter to list.
6139          */
6140         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6141                 idx = i / (sizeof(uint32_t) * NBBY);
6142                 shift = i % (sizeof(uint32_t) * NBBY);
6143                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6144                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6145                         filter->index = i;
6146                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6147                                           filter,
6148                                           entries);
6149                         break;
6150                 }
6151         }
6152         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6153                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6154                 return -ENOSYS;
6155         }
6156
6157         ixgbe_inject_5tuple_filter(dev, filter);
6158
6159         return 0;
6160 }
6161
6162 /*
6163  * remove a 5tuple filter
6164  *
6165  * @param
6166  * dev: Pointer to struct rte_eth_dev.
6167  * filter: the pointer of the filter will be removed.
6168  */
6169 static void
6170 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6171                         struct ixgbe_5tuple_filter *filter)
6172 {
6173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6174         struct ixgbe_filter_info *filter_info =
6175                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6176         uint16_t index = filter->index;
6177
6178         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6179                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6180         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6181         rte_free(filter);
6182
6183         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6184         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6185         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6186         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6187         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6188 }
6189
6190 static int
6191 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6192 {
6193         struct ixgbe_hw *hw;
6194         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6195         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6196
6197         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6198
6199         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6200                 return -EINVAL;
6201
6202         /* refuse mtu that requires the support of scattered packets when this
6203          * feature has not been enabled before.
6204          */
6205         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6206             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6207              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6208                 return -EINVAL;
6209
6210         /*
6211          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6212          * request of the version 2.0 of the mailbox API.
6213          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6214          * of the mailbox API.
6215          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6216          * prior to 3.11.33 which contains the following change:
6217          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6218          */
6219         ixgbevf_rlpml_set_vf(hw, max_frame);
6220
6221         /* update max frame size */
6222         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6223         return 0;
6224 }
6225
6226 static inline struct ixgbe_5tuple_filter *
6227 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6228                         struct ixgbe_5tuple_filter_info *key)
6229 {
6230         struct ixgbe_5tuple_filter *it;
6231
6232         TAILQ_FOREACH(it, filter_list, entries) {
6233                 if (memcmp(key, &it->filter_info,
6234                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6235                         return it;
6236                 }
6237         }
6238         return NULL;
6239 }
6240
6241 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6242 static inline int
6243 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6244                         struct ixgbe_5tuple_filter_info *filter_info)
6245 {
6246         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6247                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6248                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6249                 return -EINVAL;
6250
6251         switch (filter->dst_ip_mask) {
6252         case UINT32_MAX:
6253                 filter_info->dst_ip_mask = 0;
6254                 filter_info->dst_ip = filter->dst_ip;
6255                 break;
6256         case 0:
6257                 filter_info->dst_ip_mask = 1;
6258                 break;
6259         default:
6260                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6261                 return -EINVAL;
6262         }
6263
6264         switch (filter->src_ip_mask) {
6265         case UINT32_MAX:
6266                 filter_info->src_ip_mask = 0;
6267                 filter_info->src_ip = filter->src_ip;
6268                 break;
6269         case 0:
6270                 filter_info->src_ip_mask = 1;
6271                 break;
6272         default:
6273                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6274                 return -EINVAL;
6275         }
6276
6277         switch (filter->dst_port_mask) {
6278         case UINT16_MAX:
6279                 filter_info->dst_port_mask = 0;
6280                 filter_info->dst_port = filter->dst_port;
6281                 break;
6282         case 0:
6283                 filter_info->dst_port_mask = 1;
6284                 break;
6285         default:
6286                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6287                 return -EINVAL;
6288         }
6289
6290         switch (filter->src_port_mask) {
6291         case UINT16_MAX:
6292                 filter_info->src_port_mask = 0;
6293                 filter_info->src_port = filter->src_port;
6294                 break;
6295         case 0:
6296                 filter_info->src_port_mask = 1;
6297                 break;
6298         default:
6299                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6300                 return -EINVAL;
6301         }
6302
6303         switch (filter->proto_mask) {
6304         case UINT8_MAX:
6305                 filter_info->proto_mask = 0;
6306                 filter_info->proto =
6307                         convert_protocol_type(filter->proto);
6308                 break;
6309         case 0:
6310                 filter_info->proto_mask = 1;
6311                 break;
6312         default:
6313                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6314                 return -EINVAL;
6315         }
6316
6317         filter_info->priority = (uint8_t)filter->priority;
6318         return 0;
6319 }
6320
6321 /*
6322  * add or delete a ntuple filter
6323  *
6324  * @param
6325  * dev: Pointer to struct rte_eth_dev.
6326  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6327  * add: if true, add filter, if false, remove filter
6328  *
6329  * @return
6330  *    - On success, zero.
6331  *    - On failure, a negative value.
6332  */
6333 int
6334 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6335                         struct rte_eth_ntuple_filter *ntuple_filter,
6336                         bool add)
6337 {
6338         struct ixgbe_filter_info *filter_info =
6339                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6340         struct ixgbe_5tuple_filter_info filter_5tuple;
6341         struct ixgbe_5tuple_filter *filter;
6342         int ret;
6343
6344         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6345                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6346                 return -EINVAL;
6347         }
6348
6349         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6350         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6351         if (ret < 0)
6352                 return ret;
6353
6354         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6355                                          &filter_5tuple);
6356         if (filter != NULL && add) {
6357                 PMD_DRV_LOG(ERR, "filter exists.");
6358                 return -EEXIST;
6359         }
6360         if (filter == NULL && !add) {
6361                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6362                 return -ENOENT;
6363         }
6364
6365         if (add) {
6366                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6367                                 sizeof(struct ixgbe_5tuple_filter), 0);
6368                 if (filter == NULL)
6369                         return -ENOMEM;
6370                 rte_memcpy(&filter->filter_info,
6371                                  &filter_5tuple,
6372                                  sizeof(struct ixgbe_5tuple_filter_info));
6373                 filter->queue = ntuple_filter->queue;
6374                 ret = ixgbe_add_5tuple_filter(dev, filter);
6375                 if (ret < 0) {
6376                         rte_free(filter);
6377                         return ret;
6378                 }
6379         } else
6380                 ixgbe_remove_5tuple_filter(dev, filter);
6381
6382         return 0;
6383 }
6384
6385 /*
6386  * get a ntuple filter
6387  *
6388  * @param
6389  * dev: Pointer to struct rte_eth_dev.
6390  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6391  *
6392  * @return
6393  *    - On success, zero.
6394  *    - On failure, a negative value.
6395  */
6396 static int
6397 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6398                         struct rte_eth_ntuple_filter *ntuple_filter)
6399 {
6400         struct ixgbe_filter_info *filter_info =
6401                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6402         struct ixgbe_5tuple_filter_info filter_5tuple;
6403         struct ixgbe_5tuple_filter *filter;
6404         int ret;
6405
6406         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6407                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6408                 return -EINVAL;
6409         }
6410
6411         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6412         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6413         if (ret < 0)
6414                 return ret;
6415
6416         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6417                                          &filter_5tuple);
6418         if (filter == NULL) {
6419                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6420                 return -ENOENT;
6421         }
6422         ntuple_filter->queue = filter->queue;
6423         return 0;
6424 }
6425
6426 /*
6427  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6428  * @dev: pointer to rte_eth_dev structure
6429  * @filter_op:operation will be taken.
6430  * @arg: a pointer to specific structure corresponding to the filter_op
6431  *
6432  * @return
6433  *    - On success, zero.
6434  *    - On failure, a negative value.
6435  */
6436 static int
6437 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6438                                 enum rte_filter_op filter_op,
6439                                 void *arg)
6440 {
6441         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6442         int ret;
6443
6444         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6445
6446         if (filter_op == RTE_ETH_FILTER_NOP)
6447                 return 0;
6448
6449         if (arg == NULL) {
6450                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6451                             filter_op);
6452                 return -EINVAL;
6453         }
6454
6455         switch (filter_op) {
6456         case RTE_ETH_FILTER_ADD:
6457                 ret = ixgbe_add_del_ntuple_filter(dev,
6458                         (struct rte_eth_ntuple_filter *)arg,
6459                         TRUE);
6460                 break;
6461         case RTE_ETH_FILTER_DELETE:
6462                 ret = ixgbe_add_del_ntuple_filter(dev,
6463                         (struct rte_eth_ntuple_filter *)arg,
6464                         FALSE);
6465                 break;
6466         case RTE_ETH_FILTER_GET:
6467                 ret = ixgbe_get_ntuple_filter(dev,
6468                         (struct rte_eth_ntuple_filter *)arg);
6469                 break;
6470         default:
6471                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6472                 ret = -EINVAL;
6473                 break;
6474         }
6475         return ret;
6476 }
6477
6478 int
6479 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6480                         struct rte_eth_ethertype_filter *filter,
6481                         bool add)
6482 {
6483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6484         struct ixgbe_filter_info *filter_info =
6485                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6486         uint32_t etqf = 0;
6487         uint32_t etqs = 0;
6488         int ret;
6489         struct ixgbe_ethertype_filter ethertype_filter;
6490
6491         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6492                 return -EINVAL;
6493
6494         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6495                 filter->ether_type == ETHER_TYPE_IPv6) {
6496                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6497                         " ethertype filter.", filter->ether_type);
6498                 return -EINVAL;
6499         }
6500
6501         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6502                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6503                 return -EINVAL;
6504         }
6505         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6506                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6507                 return -EINVAL;
6508         }
6509
6510         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6511         if (ret >= 0 && add) {
6512                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6513                             filter->ether_type);
6514                 return -EEXIST;
6515         }
6516         if (ret < 0 && !add) {
6517                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6518                             filter->ether_type);
6519                 return -ENOENT;
6520         }
6521
6522         if (add) {
6523                 etqf = IXGBE_ETQF_FILTER_EN;
6524                 etqf |= (uint32_t)filter->ether_type;
6525                 etqs |= (uint32_t)((filter->queue <<
6526                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6527                                     IXGBE_ETQS_RX_QUEUE);
6528                 etqs |= IXGBE_ETQS_QUEUE_EN;
6529
6530                 ethertype_filter.ethertype = filter->ether_type;
6531                 ethertype_filter.etqf = etqf;
6532                 ethertype_filter.etqs = etqs;
6533                 ethertype_filter.conf = FALSE;
6534                 ret = ixgbe_ethertype_filter_insert(filter_info,
6535                                                     &ethertype_filter);
6536                 if (ret < 0) {
6537                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6538                         return -ENOSPC;
6539                 }
6540         } else {
6541                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6542                 if (ret < 0)
6543                         return -ENOSYS;
6544         }
6545         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6546         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6547         IXGBE_WRITE_FLUSH(hw);
6548
6549         return 0;
6550 }
6551
6552 static int
6553 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6554                         struct rte_eth_ethertype_filter *filter)
6555 {
6556         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6557         struct ixgbe_filter_info *filter_info =
6558                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6559         uint32_t etqf, etqs;
6560         int ret;
6561
6562         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6563         if (ret < 0) {
6564                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6565                             filter->ether_type);
6566                 return -ENOENT;
6567         }
6568
6569         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6570         if (etqf & IXGBE_ETQF_FILTER_EN) {
6571                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6572                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6573                 filter->flags = 0;
6574                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6575                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6576                 return 0;
6577         }
6578         return -ENOENT;
6579 }
6580
6581 /*
6582  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6583  * @dev: pointer to rte_eth_dev structure
6584  * @filter_op:operation will be taken.
6585  * @arg: a pointer to specific structure corresponding to the filter_op
6586  */
6587 static int
6588 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6589                                 enum rte_filter_op filter_op,
6590                                 void *arg)
6591 {
6592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6593         int ret;
6594
6595         MAC_TYPE_FILTER_SUP(hw->mac.type);
6596
6597         if (filter_op == RTE_ETH_FILTER_NOP)
6598                 return 0;
6599
6600         if (arg == NULL) {
6601                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6602                             filter_op);
6603                 return -EINVAL;
6604         }
6605
6606         switch (filter_op) {
6607         case RTE_ETH_FILTER_ADD:
6608                 ret = ixgbe_add_del_ethertype_filter(dev,
6609                         (struct rte_eth_ethertype_filter *)arg,
6610                         TRUE);
6611                 break;
6612         case RTE_ETH_FILTER_DELETE:
6613                 ret = ixgbe_add_del_ethertype_filter(dev,
6614                         (struct rte_eth_ethertype_filter *)arg,
6615                         FALSE);
6616                 break;
6617         case RTE_ETH_FILTER_GET:
6618                 ret = ixgbe_get_ethertype_filter(dev,
6619                         (struct rte_eth_ethertype_filter *)arg);
6620                 break;
6621         default:
6622                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6623                 ret = -EINVAL;
6624                 break;
6625         }
6626         return ret;
6627 }
6628
6629 static int
6630 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6631                      enum rte_filter_type filter_type,
6632                      enum rte_filter_op filter_op,
6633                      void *arg)
6634 {
6635         int ret = 0;
6636
6637         switch (filter_type) {
6638         case RTE_ETH_FILTER_NTUPLE:
6639                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6640                 break;
6641         case RTE_ETH_FILTER_ETHERTYPE:
6642                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6643                 break;
6644         case RTE_ETH_FILTER_SYN:
6645                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6646                 break;
6647         case RTE_ETH_FILTER_FDIR:
6648                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6649                 break;
6650         case RTE_ETH_FILTER_L2_TUNNEL:
6651                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6652                 break;
6653         case RTE_ETH_FILTER_GENERIC:
6654                 if (filter_op != RTE_ETH_FILTER_GET)
6655                         return -EINVAL;
6656                 *(const void **)arg = &ixgbe_flow_ops;
6657                 break;
6658         default:
6659                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6660                                                         filter_type);
6661                 ret = -EINVAL;
6662                 break;
6663         }
6664
6665         return ret;
6666 }
6667
6668 static u8 *
6669 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6670                         u8 **mc_addr_ptr, u32 *vmdq)
6671 {
6672         u8 *mc_addr;
6673
6674         *vmdq = 0;
6675         mc_addr = *mc_addr_ptr;
6676         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6677         return mc_addr;
6678 }
6679
6680 static int
6681 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6682                           struct ether_addr *mc_addr_set,
6683                           uint32_t nb_mc_addr)
6684 {
6685         struct ixgbe_hw *hw;
6686         u8 *mc_addr_list;
6687
6688         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6689         mc_addr_list = (u8 *)mc_addr_set;
6690         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6691                                          ixgbe_dev_addr_list_itr, TRUE);
6692 }
6693
6694 static uint64_t
6695 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6696 {
6697         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6698         uint64_t systime_cycles;
6699
6700         switch (hw->mac.type) {
6701         case ixgbe_mac_X550:
6702         case ixgbe_mac_X550EM_x:
6703         case ixgbe_mac_X550EM_a:
6704                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6705                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6706                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6707                                 * NSEC_PER_SEC;
6708                 break;
6709         default:
6710                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6711                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6712                                 << 32;
6713         }
6714
6715         return systime_cycles;
6716 }
6717
6718 static uint64_t
6719 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6720 {
6721         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6722         uint64_t rx_tstamp_cycles;
6723
6724         switch (hw->mac.type) {
6725         case ixgbe_mac_X550:
6726         case ixgbe_mac_X550EM_x:
6727         case ixgbe_mac_X550EM_a:
6728                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6729                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6730                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6731                                 * NSEC_PER_SEC;
6732                 break;
6733         default:
6734                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6735                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6736                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6737                                 << 32;
6738         }
6739
6740         return rx_tstamp_cycles;
6741 }
6742
6743 static uint64_t
6744 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6745 {
6746         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6747         uint64_t tx_tstamp_cycles;
6748
6749         switch (hw->mac.type) {
6750         case ixgbe_mac_X550:
6751         case ixgbe_mac_X550EM_x:
6752         case ixgbe_mac_X550EM_a:
6753                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6754                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6755                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6756                                 * NSEC_PER_SEC;
6757                 break;
6758         default:
6759                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6760                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6761                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6762                                 << 32;
6763         }
6764
6765         return tx_tstamp_cycles;
6766 }
6767
6768 static void
6769 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6770 {
6771         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6772         struct ixgbe_adapter *adapter =
6773                 (struct ixgbe_adapter *)dev->data->dev_private;
6774         struct rte_eth_link link;
6775         uint32_t incval = 0;
6776         uint32_t shift = 0;
6777
6778         /* Get current link speed. */
6779         ixgbe_dev_link_update(dev, 1);
6780         rte_eth_linkstatus_get(dev, &link);
6781
6782         switch (link.link_speed) {
6783         case ETH_SPEED_NUM_100M:
6784                 incval = IXGBE_INCVAL_100;
6785                 shift = IXGBE_INCVAL_SHIFT_100;
6786                 break;
6787         case ETH_SPEED_NUM_1G:
6788                 incval = IXGBE_INCVAL_1GB;
6789                 shift = IXGBE_INCVAL_SHIFT_1GB;
6790                 break;
6791         case ETH_SPEED_NUM_10G:
6792         default:
6793                 incval = IXGBE_INCVAL_10GB;
6794                 shift = IXGBE_INCVAL_SHIFT_10GB;
6795                 break;
6796         }
6797
6798         switch (hw->mac.type) {
6799         case ixgbe_mac_X550:
6800         case ixgbe_mac_X550EM_x:
6801         case ixgbe_mac_X550EM_a:
6802                 /* Independent of link speed. */
6803                 incval = 1;
6804                 /* Cycles read will be interpreted as ns. */
6805                 shift = 0;
6806                 /* Fall-through */
6807         case ixgbe_mac_X540:
6808                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6809                 break;
6810         case ixgbe_mac_82599EB:
6811                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6812                 shift -= IXGBE_INCVAL_SHIFT_82599;
6813                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6814                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6815                 break;
6816         default:
6817                 /* Not supported. */
6818                 return;
6819         }
6820
6821         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6822         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6823         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6824
6825         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6826         adapter->systime_tc.cc_shift = shift;
6827         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6828
6829         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6830         adapter->rx_tstamp_tc.cc_shift = shift;
6831         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6832
6833         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6834         adapter->tx_tstamp_tc.cc_shift = shift;
6835         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6836 }
6837
6838 static int
6839 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6840 {
6841         struct ixgbe_adapter *adapter =
6842                         (struct ixgbe_adapter *)dev->data->dev_private;
6843
6844         adapter->systime_tc.nsec += delta;
6845         adapter->rx_tstamp_tc.nsec += delta;
6846         adapter->tx_tstamp_tc.nsec += delta;
6847
6848         return 0;
6849 }
6850
6851 static int
6852 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6853 {
6854         uint64_t ns;
6855         struct ixgbe_adapter *adapter =
6856                         (struct ixgbe_adapter *)dev->data->dev_private;
6857
6858         ns = rte_timespec_to_ns(ts);
6859         /* Set the timecounters to a new value. */
6860         adapter->systime_tc.nsec = ns;
6861         adapter->rx_tstamp_tc.nsec = ns;
6862         adapter->tx_tstamp_tc.nsec = ns;
6863
6864         return 0;
6865 }
6866
6867 static int
6868 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6869 {
6870         uint64_t ns, systime_cycles;
6871         struct ixgbe_adapter *adapter =
6872                         (struct ixgbe_adapter *)dev->data->dev_private;
6873
6874         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6875         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6876         *ts = rte_ns_to_timespec(ns);
6877
6878         return 0;
6879 }
6880
6881 static int
6882 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6883 {
6884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6885         uint32_t tsync_ctl;
6886         uint32_t tsauxc;
6887
6888         /* Stop the timesync system time. */
6889         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6890         /* Reset the timesync system time value. */
6891         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6892         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6893
6894         /* Enable system time for platforms where it isn't on by default. */
6895         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6896         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6897         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6898
6899         ixgbe_start_timecounters(dev);
6900
6901         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6902         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6903                         (ETHER_TYPE_1588 |
6904                          IXGBE_ETQF_FILTER_EN |
6905                          IXGBE_ETQF_1588));
6906
6907         /* Enable timestamping of received PTP packets. */
6908         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6909         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6910         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6911
6912         /* Enable timestamping of transmitted PTP packets. */
6913         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6914         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6915         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6916
6917         IXGBE_WRITE_FLUSH(hw);
6918
6919         return 0;
6920 }
6921
6922 static int
6923 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6924 {
6925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6926         uint32_t tsync_ctl;
6927
6928         /* Disable timestamping of transmitted PTP packets. */
6929         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6930         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6931         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6932
6933         /* Disable timestamping of received PTP packets. */
6934         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6935         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6936         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6937
6938         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6939         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6940
6941         /* Stop incrementating the System Time registers. */
6942         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6943
6944         return 0;
6945 }
6946
6947 static int
6948 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6949                                  struct timespec *timestamp,
6950                                  uint32_t flags __rte_unused)
6951 {
6952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6953         struct ixgbe_adapter *adapter =
6954                 (struct ixgbe_adapter *)dev->data->dev_private;
6955         uint32_t tsync_rxctl;
6956         uint64_t rx_tstamp_cycles;
6957         uint64_t ns;
6958
6959         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6960         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6961                 return -EINVAL;
6962
6963         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6964         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6965         *timestamp = rte_ns_to_timespec(ns);
6966
6967         return  0;
6968 }
6969
6970 static int
6971 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6972                                  struct timespec *timestamp)
6973 {
6974         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6975         struct ixgbe_adapter *adapter =
6976                 (struct ixgbe_adapter *)dev->data->dev_private;
6977         uint32_t tsync_txctl;
6978         uint64_t tx_tstamp_cycles;
6979         uint64_t ns;
6980
6981         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6982         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6983                 return -EINVAL;
6984
6985         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6986         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6987         *timestamp = rte_ns_to_timespec(ns);
6988
6989         return 0;
6990 }
6991
6992 static int
6993 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6994 {
6995         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6996         int count = 0;
6997         int g_ind = 0;
6998         const struct reg_info *reg_group;
6999         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7000                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7001
7002         while ((reg_group = reg_set[g_ind++]))
7003                 count += ixgbe_regs_group_count(reg_group);
7004
7005         return count;
7006 }
7007
7008 static int
7009 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7010 {
7011         int count = 0;
7012         int g_ind = 0;
7013         const struct reg_info *reg_group;
7014
7015         while ((reg_group = ixgbevf_regs[g_ind++]))
7016                 count += ixgbe_regs_group_count(reg_group);
7017
7018         return count;
7019 }
7020
7021 static int
7022 ixgbe_get_regs(struct rte_eth_dev *dev,
7023               struct rte_dev_reg_info *regs)
7024 {
7025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7026         uint32_t *data = regs->data;
7027         int g_ind = 0;
7028         int count = 0;
7029         const struct reg_info *reg_group;
7030         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7031                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7032
7033         if (data == NULL) {
7034                 regs->length = ixgbe_get_reg_length(dev);
7035                 regs->width = sizeof(uint32_t);
7036                 return 0;
7037         }
7038
7039         /* Support only full register dump */
7040         if ((regs->length == 0) ||
7041             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7042                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7043                         hw->device_id;
7044                 while ((reg_group = reg_set[g_ind++]))
7045                         count += ixgbe_read_regs_group(dev, &data[count],
7046                                 reg_group);
7047                 return 0;
7048         }
7049
7050         return -ENOTSUP;
7051 }
7052
7053 static int
7054 ixgbevf_get_regs(struct rte_eth_dev *dev,
7055                 struct rte_dev_reg_info *regs)
7056 {
7057         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7058         uint32_t *data = regs->data;
7059         int g_ind = 0;
7060         int count = 0;
7061         const struct reg_info *reg_group;
7062
7063         if (data == NULL) {
7064                 regs->length = ixgbevf_get_reg_length(dev);
7065                 regs->width = sizeof(uint32_t);
7066                 return 0;
7067         }
7068
7069         /* Support only full register dump */
7070         if ((regs->length == 0) ||
7071             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7072                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7073                         hw->device_id;
7074                 while ((reg_group = ixgbevf_regs[g_ind++]))
7075                         count += ixgbe_read_regs_group(dev, &data[count],
7076                                                       reg_group);
7077                 return 0;
7078         }
7079
7080         return -ENOTSUP;
7081 }
7082
7083 static int
7084 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7085 {
7086         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7087
7088         /* Return unit is byte count */
7089         return hw->eeprom.word_size * 2;
7090 }
7091
7092 static int
7093 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7094                 struct rte_dev_eeprom_info *in_eeprom)
7095 {
7096         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7097         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7098         uint16_t *data = in_eeprom->data;
7099         int first, length;
7100
7101         first = in_eeprom->offset >> 1;
7102         length = in_eeprom->length >> 1;
7103         if ((first > hw->eeprom.word_size) ||
7104             ((first + length) > hw->eeprom.word_size))
7105                 return -EINVAL;
7106
7107         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7108
7109         return eeprom->ops.read_buffer(hw, first, length, data);
7110 }
7111
7112 static int
7113 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7114                 struct rte_dev_eeprom_info *in_eeprom)
7115 {
7116         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7117         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7118         uint16_t *data = in_eeprom->data;
7119         int first, length;
7120
7121         first = in_eeprom->offset >> 1;
7122         length = in_eeprom->length >> 1;
7123         if ((first > hw->eeprom.word_size) ||
7124             ((first + length) > hw->eeprom.word_size))
7125                 return -EINVAL;
7126
7127         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7128
7129         return eeprom->ops.write_buffer(hw,  first, length, data);
7130 }
7131
7132 static int
7133 ixgbe_get_module_info(struct rte_eth_dev *dev,
7134                       struct rte_eth_dev_module_info *modinfo)
7135 {
7136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7137         uint32_t status;
7138         uint8_t sff8472_rev, addr_mode;
7139         bool page_swap = false;
7140
7141         /* Check whether we support SFF-8472 or not */
7142         status = hw->phy.ops.read_i2c_eeprom(hw,
7143                                              IXGBE_SFF_SFF_8472_COMP,
7144                                              &sff8472_rev);
7145         if (status != 0)
7146                 return -EIO;
7147
7148         /* addressing mode is not supported */
7149         status = hw->phy.ops.read_i2c_eeprom(hw,
7150                                              IXGBE_SFF_SFF_8472_SWAP,
7151                                              &addr_mode);
7152         if (status != 0)
7153                 return -EIO;
7154
7155         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7156                 PMD_DRV_LOG(ERR,
7157                             "Address change required to access page 0xA2, "
7158                             "but not supported. Please report the module "
7159                             "type to the driver maintainers.");
7160                 page_swap = true;
7161         }
7162
7163         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7164                 /* We have a SFP, but it does not support SFF-8472 */
7165                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7166                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7167         } else {
7168                 /* We have a SFP which supports a revision of SFF-8472. */
7169                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7170                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7171         }
7172
7173         return 0;
7174 }
7175
7176 static int
7177 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7178                         struct rte_dev_eeprom_info *info)
7179 {
7180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7181         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7182         uint8_t databyte = 0xFF;
7183         uint8_t *data = info->data;
7184         uint32_t i = 0;
7185
7186         if (info->length == 0)
7187                 return -EINVAL;
7188
7189         for (i = info->offset; i < info->offset + info->length; i++) {
7190                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7191                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7192                 else
7193                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7194
7195                 if (status != 0)
7196                         return -EIO;
7197
7198                 data[i - info->offset] = databyte;
7199         }
7200
7201         return 0;
7202 }
7203
7204 uint16_t
7205 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7206         switch (mac_type) {
7207         case ixgbe_mac_X550:
7208         case ixgbe_mac_X550EM_x:
7209         case ixgbe_mac_X550EM_a:
7210                 return ETH_RSS_RETA_SIZE_512;
7211         case ixgbe_mac_X550_vf:
7212         case ixgbe_mac_X550EM_x_vf:
7213         case ixgbe_mac_X550EM_a_vf:
7214                 return ETH_RSS_RETA_SIZE_64;
7215         default:
7216                 return ETH_RSS_RETA_SIZE_128;
7217         }
7218 }
7219
7220 uint32_t
7221 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7222         switch (mac_type) {
7223         case ixgbe_mac_X550:
7224         case ixgbe_mac_X550EM_x:
7225         case ixgbe_mac_X550EM_a:
7226                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7227                         return IXGBE_RETA(reta_idx >> 2);
7228                 else
7229                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7230         case ixgbe_mac_X550_vf:
7231         case ixgbe_mac_X550EM_x_vf:
7232         case ixgbe_mac_X550EM_a_vf:
7233                 return IXGBE_VFRETA(reta_idx >> 2);
7234         default:
7235                 return IXGBE_RETA(reta_idx >> 2);
7236         }
7237 }
7238
7239 uint32_t
7240 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7241         switch (mac_type) {
7242         case ixgbe_mac_X550_vf:
7243         case ixgbe_mac_X550EM_x_vf:
7244         case ixgbe_mac_X550EM_a_vf:
7245                 return IXGBE_VFMRQC;
7246         default:
7247                 return IXGBE_MRQC;
7248         }
7249 }
7250
7251 uint32_t
7252 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7253         switch (mac_type) {
7254         case ixgbe_mac_X550_vf:
7255         case ixgbe_mac_X550EM_x_vf:
7256         case ixgbe_mac_X550EM_a_vf:
7257                 return IXGBE_VFRSSRK(i);
7258         default:
7259                 return IXGBE_RSSRK(i);
7260         }
7261 }
7262
7263 bool
7264 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7265         switch (mac_type) {
7266         case ixgbe_mac_82599_vf:
7267         case ixgbe_mac_X540_vf:
7268                 return 0;
7269         default:
7270                 return 1;
7271         }
7272 }
7273
7274 static int
7275 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7276                         struct rte_eth_dcb_info *dcb_info)
7277 {
7278         struct ixgbe_dcb_config *dcb_config =
7279                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7280         struct ixgbe_dcb_tc_config *tc;
7281         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7282         uint8_t nb_tcs;
7283         uint8_t i, j;
7284
7285         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7286                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7287         else
7288                 dcb_info->nb_tcs = 1;
7289
7290         tc_queue = &dcb_info->tc_queue;
7291         nb_tcs = dcb_info->nb_tcs;
7292
7293         if (dcb_config->vt_mode) { /* vt is enabled*/
7294                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7295                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7296                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7297                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7298                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7299                         for (j = 0; j < nb_tcs; j++) {
7300                                 tc_queue->tc_rxq[0][j].base = j;
7301                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7302                                 tc_queue->tc_txq[0][j].base = j;
7303                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7304                         }
7305                 } else {
7306                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7307                                 for (j = 0; j < nb_tcs; j++) {
7308                                         tc_queue->tc_rxq[i][j].base =
7309                                                 i * nb_tcs + j;
7310                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7311                                         tc_queue->tc_txq[i][j].base =
7312                                                 i * nb_tcs + j;
7313                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7314                                 }
7315                         }
7316                 }
7317         } else { /* vt is disabled*/
7318                 struct rte_eth_dcb_rx_conf *rx_conf =
7319                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7320                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7321                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7322                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7323                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7324                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7325                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7326                         }
7327                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7328                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7329                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7330                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7331                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7332                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7333                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7334                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7335                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7336                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7337                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7338                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7339                         }
7340                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7341                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7342                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7343                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7344                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7345                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7346                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7347                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7348                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7349                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7350                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7351                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7352                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7353                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7354                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7355                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7356                 }
7357         }
7358         for (i = 0; i < dcb_info->nb_tcs; i++) {
7359                 tc = &dcb_config->tc_config[i];
7360                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7361         }
7362         return 0;
7363 }
7364
7365 /* Update e-tag ether type */
7366 static int
7367 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7368                             uint16_t ether_type)
7369 {
7370         uint32_t etag_etype;
7371
7372         if (hw->mac.type != ixgbe_mac_X550 &&
7373             hw->mac.type != ixgbe_mac_X550EM_x &&
7374             hw->mac.type != ixgbe_mac_X550EM_a) {
7375                 return -ENOTSUP;
7376         }
7377
7378         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7379         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7380         etag_etype |= ether_type;
7381         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7382         IXGBE_WRITE_FLUSH(hw);
7383
7384         return 0;
7385 }
7386
7387 /* Config l2 tunnel ether type */
7388 static int
7389 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7390                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7391 {
7392         int ret = 0;
7393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7394         struct ixgbe_l2_tn_info *l2_tn_info =
7395                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7396
7397         if (l2_tunnel == NULL)
7398                 return -EINVAL;
7399
7400         switch (l2_tunnel->l2_tunnel_type) {
7401         case RTE_L2_TUNNEL_TYPE_E_TAG:
7402                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7403                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7404                 break;
7405         default:
7406                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7407                 ret = -EINVAL;
7408                 break;
7409         }
7410
7411         return ret;
7412 }
7413
7414 /* Enable e-tag tunnel */
7415 static int
7416 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7417 {
7418         uint32_t etag_etype;
7419
7420         if (hw->mac.type != ixgbe_mac_X550 &&
7421             hw->mac.type != ixgbe_mac_X550EM_x &&
7422             hw->mac.type != ixgbe_mac_X550EM_a) {
7423                 return -ENOTSUP;
7424         }
7425
7426         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7427         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7428         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7429         IXGBE_WRITE_FLUSH(hw);
7430
7431         return 0;
7432 }
7433
7434 /* Enable l2 tunnel */
7435 static int
7436 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7437                            enum rte_eth_tunnel_type l2_tunnel_type)
7438 {
7439         int ret = 0;
7440         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7441         struct ixgbe_l2_tn_info *l2_tn_info =
7442                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7443
7444         switch (l2_tunnel_type) {
7445         case RTE_L2_TUNNEL_TYPE_E_TAG:
7446                 l2_tn_info->e_tag_en = TRUE;
7447                 ret = ixgbe_e_tag_enable(hw);
7448                 break;
7449         default:
7450                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7451                 ret = -EINVAL;
7452                 break;
7453         }
7454
7455         return ret;
7456 }
7457
7458 /* Disable e-tag tunnel */
7459 static int
7460 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7461 {
7462         uint32_t etag_etype;
7463
7464         if (hw->mac.type != ixgbe_mac_X550 &&
7465             hw->mac.type != ixgbe_mac_X550EM_x &&
7466             hw->mac.type != ixgbe_mac_X550EM_a) {
7467                 return -ENOTSUP;
7468         }
7469
7470         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7471         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7472         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7473         IXGBE_WRITE_FLUSH(hw);
7474
7475         return 0;
7476 }
7477
7478 /* Disable l2 tunnel */
7479 static int
7480 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7481                             enum rte_eth_tunnel_type l2_tunnel_type)
7482 {
7483         int ret = 0;
7484         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7485         struct ixgbe_l2_tn_info *l2_tn_info =
7486                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7487
7488         switch (l2_tunnel_type) {
7489         case RTE_L2_TUNNEL_TYPE_E_TAG:
7490                 l2_tn_info->e_tag_en = FALSE;
7491                 ret = ixgbe_e_tag_disable(hw);
7492                 break;
7493         default:
7494                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7495                 ret = -EINVAL;
7496                 break;
7497         }
7498
7499         return ret;
7500 }
7501
7502 static int
7503 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7504                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7505 {
7506         int ret = 0;
7507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7508         uint32_t i, rar_entries;
7509         uint32_t rar_low, rar_high;
7510
7511         if (hw->mac.type != ixgbe_mac_X550 &&
7512             hw->mac.type != ixgbe_mac_X550EM_x &&
7513             hw->mac.type != ixgbe_mac_X550EM_a) {
7514                 return -ENOTSUP;
7515         }
7516
7517         rar_entries = ixgbe_get_num_rx_addrs(hw);
7518
7519         for (i = 1; i < rar_entries; i++) {
7520                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7521                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7522                 if ((rar_high & IXGBE_RAH_AV) &&
7523                     (rar_high & IXGBE_RAH_ADTYPE) &&
7524                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7525                      l2_tunnel->tunnel_id)) {
7526                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7527                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7528
7529                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7530
7531                         return ret;
7532                 }
7533         }
7534
7535         return ret;
7536 }
7537
7538 static int
7539 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7540                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7541 {
7542         int ret = 0;
7543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7544         uint32_t i, rar_entries;
7545         uint32_t rar_low, rar_high;
7546
7547         if (hw->mac.type != ixgbe_mac_X550 &&
7548             hw->mac.type != ixgbe_mac_X550EM_x &&
7549             hw->mac.type != ixgbe_mac_X550EM_a) {
7550                 return -ENOTSUP;
7551         }
7552
7553         /* One entry for one tunnel. Try to remove potential existing entry. */
7554         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7555
7556         rar_entries = ixgbe_get_num_rx_addrs(hw);
7557
7558         for (i = 1; i < rar_entries; i++) {
7559                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7560                 if (rar_high & IXGBE_RAH_AV) {
7561                         continue;
7562                 } else {
7563                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7564                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7565                         rar_low = l2_tunnel->tunnel_id;
7566
7567                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7568                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7569
7570                         return ret;
7571                 }
7572         }
7573
7574         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7575                      " Please remove a rule before adding a new one.");
7576         return -EINVAL;
7577 }
7578
7579 static inline struct ixgbe_l2_tn_filter *
7580 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7581                           struct ixgbe_l2_tn_key *key)
7582 {
7583         int ret;
7584
7585         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7586         if (ret < 0)
7587                 return NULL;
7588
7589         return l2_tn_info->hash_map[ret];
7590 }
7591
7592 static inline int
7593 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7594                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7595 {
7596         int ret;
7597
7598         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7599                                &l2_tn_filter->key);
7600
7601         if (ret < 0) {
7602                 PMD_DRV_LOG(ERR,
7603                             "Failed to insert L2 tunnel filter"
7604                             " to hash table %d!",
7605                             ret);
7606                 return ret;
7607         }
7608
7609         l2_tn_info->hash_map[ret] = l2_tn_filter;
7610
7611         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7612
7613         return 0;
7614 }
7615
7616 static inline int
7617 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7618                           struct ixgbe_l2_tn_key *key)
7619 {
7620         int ret;
7621         struct ixgbe_l2_tn_filter *l2_tn_filter;
7622
7623         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7624
7625         if (ret < 0) {
7626                 PMD_DRV_LOG(ERR,
7627                             "No such L2 tunnel filter to delete %d!",
7628                             ret);
7629                 return ret;
7630         }
7631
7632         l2_tn_filter = l2_tn_info->hash_map[ret];
7633         l2_tn_info->hash_map[ret] = NULL;
7634
7635         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7636         rte_free(l2_tn_filter);
7637
7638         return 0;
7639 }
7640
7641 /* Add l2 tunnel filter */
7642 int
7643 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7644                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7645                                bool restore)
7646 {
7647         int ret;
7648         struct ixgbe_l2_tn_info *l2_tn_info =
7649                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7650         struct ixgbe_l2_tn_key key;
7651         struct ixgbe_l2_tn_filter *node;
7652
7653         if (!restore) {
7654                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7655                 key.tn_id = l2_tunnel->tunnel_id;
7656
7657                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7658
7659                 if (node) {
7660                         PMD_DRV_LOG(ERR,
7661                                     "The L2 tunnel filter already exists!");
7662                         return -EINVAL;
7663                 }
7664
7665                 node = rte_zmalloc("ixgbe_l2_tn",
7666                                    sizeof(struct ixgbe_l2_tn_filter),
7667                                    0);
7668                 if (!node)
7669                         return -ENOMEM;
7670
7671                 rte_memcpy(&node->key,
7672                                  &key,
7673                                  sizeof(struct ixgbe_l2_tn_key));
7674                 node->pool = l2_tunnel->pool;
7675                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7676                 if (ret < 0) {
7677                         rte_free(node);
7678                         return ret;
7679                 }
7680         }
7681
7682         switch (l2_tunnel->l2_tunnel_type) {
7683         case RTE_L2_TUNNEL_TYPE_E_TAG:
7684                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7685                 break;
7686         default:
7687                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7688                 ret = -EINVAL;
7689                 break;
7690         }
7691
7692         if ((!restore) && (ret < 0))
7693                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7694
7695         return ret;
7696 }
7697
7698 /* Delete l2 tunnel filter */
7699 int
7700 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7701                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7702 {
7703         int ret;
7704         struct ixgbe_l2_tn_info *l2_tn_info =
7705                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7706         struct ixgbe_l2_tn_key key;
7707
7708         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7709         key.tn_id = l2_tunnel->tunnel_id;
7710         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7711         if (ret < 0)
7712                 return ret;
7713
7714         switch (l2_tunnel->l2_tunnel_type) {
7715         case RTE_L2_TUNNEL_TYPE_E_TAG:
7716                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7717                 break;
7718         default:
7719                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7720                 ret = -EINVAL;
7721                 break;
7722         }
7723
7724         return ret;
7725 }
7726
7727 /**
7728  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7729  * @dev: pointer to rte_eth_dev structure
7730  * @filter_op:operation will be taken.
7731  * @arg: a pointer to specific structure corresponding to the filter_op
7732  */
7733 static int
7734 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7735                                   enum rte_filter_op filter_op,
7736                                   void *arg)
7737 {
7738         int ret;
7739
7740         if (filter_op == RTE_ETH_FILTER_NOP)
7741                 return 0;
7742
7743         if (arg == NULL) {
7744                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7745                             filter_op);
7746                 return -EINVAL;
7747         }
7748
7749         switch (filter_op) {
7750         case RTE_ETH_FILTER_ADD:
7751                 ret = ixgbe_dev_l2_tunnel_filter_add
7752                         (dev,
7753                          (struct rte_eth_l2_tunnel_conf *)arg,
7754                          FALSE);
7755                 break;
7756         case RTE_ETH_FILTER_DELETE:
7757                 ret = ixgbe_dev_l2_tunnel_filter_del
7758                         (dev,
7759                          (struct rte_eth_l2_tunnel_conf *)arg);
7760                 break;
7761         default:
7762                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7763                 ret = -EINVAL;
7764                 break;
7765         }
7766         return ret;
7767 }
7768
7769 static int
7770 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7771 {
7772         int ret = 0;
7773         uint32_t ctrl;
7774         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7775
7776         if (hw->mac.type != ixgbe_mac_X550 &&
7777             hw->mac.type != ixgbe_mac_X550EM_x &&
7778             hw->mac.type != ixgbe_mac_X550EM_a) {
7779                 return -ENOTSUP;
7780         }
7781
7782         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7783         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7784         if (en)
7785                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7786         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7787
7788         return ret;
7789 }
7790
7791 /* Enable l2 tunnel forwarding */
7792 static int
7793 ixgbe_dev_l2_tunnel_forwarding_enable
7794         (struct rte_eth_dev *dev,
7795          enum rte_eth_tunnel_type l2_tunnel_type)
7796 {
7797         struct ixgbe_l2_tn_info *l2_tn_info =
7798                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7799         int ret = 0;
7800
7801         switch (l2_tunnel_type) {
7802         case RTE_L2_TUNNEL_TYPE_E_TAG:
7803                 l2_tn_info->e_tag_fwd_en = TRUE;
7804                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7805                 break;
7806         default:
7807                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7808                 ret = -EINVAL;
7809                 break;
7810         }
7811
7812         return ret;
7813 }
7814
7815 /* Disable l2 tunnel forwarding */
7816 static int
7817 ixgbe_dev_l2_tunnel_forwarding_disable
7818         (struct rte_eth_dev *dev,
7819          enum rte_eth_tunnel_type l2_tunnel_type)
7820 {
7821         struct ixgbe_l2_tn_info *l2_tn_info =
7822                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7823         int ret = 0;
7824
7825         switch (l2_tunnel_type) {
7826         case RTE_L2_TUNNEL_TYPE_E_TAG:
7827                 l2_tn_info->e_tag_fwd_en = FALSE;
7828                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7829                 break;
7830         default:
7831                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7832                 ret = -EINVAL;
7833                 break;
7834         }
7835
7836         return ret;
7837 }
7838
7839 static int
7840 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7841                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7842                              bool en)
7843 {
7844         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7845         int ret = 0;
7846         uint32_t vmtir, vmvir;
7847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7848
7849         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7850                 PMD_DRV_LOG(ERR,
7851                             "VF id %u should be less than %u",
7852                             l2_tunnel->vf_id,
7853                             pci_dev->max_vfs);
7854                 return -EINVAL;
7855         }
7856
7857         if (hw->mac.type != ixgbe_mac_X550 &&
7858             hw->mac.type != ixgbe_mac_X550EM_x &&
7859             hw->mac.type != ixgbe_mac_X550EM_a) {
7860                 return -ENOTSUP;
7861         }
7862
7863         if (en)
7864                 vmtir = l2_tunnel->tunnel_id;
7865         else
7866                 vmtir = 0;
7867
7868         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7869
7870         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7871         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7872         if (en)
7873                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7874         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7875
7876         return ret;
7877 }
7878
7879 /* Enable l2 tunnel tag insertion */
7880 static int
7881 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7882                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7883 {
7884         int ret = 0;
7885
7886         switch (l2_tunnel->l2_tunnel_type) {
7887         case RTE_L2_TUNNEL_TYPE_E_TAG:
7888                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7889                 break;
7890         default:
7891                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7892                 ret = -EINVAL;
7893                 break;
7894         }
7895
7896         return ret;
7897 }
7898
7899 /* Disable l2 tunnel tag insertion */
7900 static int
7901 ixgbe_dev_l2_tunnel_insertion_disable
7902         (struct rte_eth_dev *dev,
7903          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7904 {
7905         int ret = 0;
7906
7907         switch (l2_tunnel->l2_tunnel_type) {
7908         case RTE_L2_TUNNEL_TYPE_E_TAG:
7909                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7910                 break;
7911         default:
7912                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7913                 ret = -EINVAL;
7914                 break;
7915         }
7916
7917         return ret;
7918 }
7919
7920 static int
7921 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7922                              bool en)
7923 {
7924         int ret = 0;
7925         uint32_t qde;
7926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7927
7928         if (hw->mac.type != ixgbe_mac_X550 &&
7929             hw->mac.type != ixgbe_mac_X550EM_x &&
7930             hw->mac.type != ixgbe_mac_X550EM_a) {
7931                 return -ENOTSUP;
7932         }
7933
7934         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7935         if (en)
7936                 qde |= IXGBE_QDE_STRIP_TAG;
7937         else
7938                 qde &= ~IXGBE_QDE_STRIP_TAG;
7939         qde &= ~IXGBE_QDE_READ;
7940         qde |= IXGBE_QDE_WRITE;
7941         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7942
7943         return ret;
7944 }
7945
7946 /* Enable l2 tunnel tag stripping */
7947 static int
7948 ixgbe_dev_l2_tunnel_stripping_enable
7949         (struct rte_eth_dev *dev,
7950          enum rte_eth_tunnel_type l2_tunnel_type)
7951 {
7952         int ret = 0;
7953
7954         switch (l2_tunnel_type) {
7955         case RTE_L2_TUNNEL_TYPE_E_TAG:
7956                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7957                 break;
7958         default:
7959                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7960                 ret = -EINVAL;
7961                 break;
7962         }
7963
7964         return ret;
7965 }
7966
7967 /* Disable l2 tunnel tag stripping */
7968 static int
7969 ixgbe_dev_l2_tunnel_stripping_disable
7970         (struct rte_eth_dev *dev,
7971          enum rte_eth_tunnel_type l2_tunnel_type)
7972 {
7973         int ret = 0;
7974
7975         switch (l2_tunnel_type) {
7976         case RTE_L2_TUNNEL_TYPE_E_TAG:
7977                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7978                 break;
7979         default:
7980                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7981                 ret = -EINVAL;
7982                 break;
7983         }
7984
7985         return ret;
7986 }
7987
7988 /* Enable/disable l2 tunnel offload functions */
7989 static int
7990 ixgbe_dev_l2_tunnel_offload_set
7991         (struct rte_eth_dev *dev,
7992          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7993          uint32_t mask,
7994          uint8_t en)
7995 {
7996         int ret = 0;
7997
7998         if (l2_tunnel == NULL)
7999                 return -EINVAL;
8000
8001         ret = -EINVAL;
8002         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8003                 if (en)
8004                         ret = ixgbe_dev_l2_tunnel_enable(
8005                                 dev,
8006                                 l2_tunnel->l2_tunnel_type);
8007                 else
8008                         ret = ixgbe_dev_l2_tunnel_disable(
8009                                 dev,
8010                                 l2_tunnel->l2_tunnel_type);
8011         }
8012
8013         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8014                 if (en)
8015                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8016                                 dev,
8017                                 l2_tunnel);
8018                 else
8019                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8020                                 dev,
8021                                 l2_tunnel);
8022         }
8023
8024         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8025                 if (en)
8026                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8027                                 dev,
8028                                 l2_tunnel->l2_tunnel_type);
8029                 else
8030                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8031                                 dev,
8032                                 l2_tunnel->l2_tunnel_type);
8033         }
8034
8035         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8036                 if (en)
8037                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8038                                 dev,
8039                                 l2_tunnel->l2_tunnel_type);
8040                 else
8041                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8042                                 dev,
8043                                 l2_tunnel->l2_tunnel_type);
8044         }
8045
8046         return ret;
8047 }
8048
8049 static int
8050 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8051                         uint16_t port)
8052 {
8053         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8054         IXGBE_WRITE_FLUSH(hw);
8055
8056         return 0;
8057 }
8058
8059 /* There's only one register for VxLAN UDP port.
8060  * So, we cannot add several ports. Will update it.
8061  */
8062 static int
8063 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8064                      uint16_t port)
8065 {
8066         if (port == 0) {
8067                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8068                 return -EINVAL;
8069         }
8070
8071         return ixgbe_update_vxlan_port(hw, port);
8072 }
8073
8074 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8075  * UDP port, it must have a value.
8076  * So, will reset it to the original value 0.
8077  */
8078 static int
8079 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8080                      uint16_t port)
8081 {
8082         uint16_t cur_port;
8083
8084         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8085
8086         if (cur_port != port) {
8087                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8088                 return -EINVAL;
8089         }
8090
8091         return ixgbe_update_vxlan_port(hw, 0);
8092 }
8093
8094 /* Add UDP tunneling port */
8095 static int
8096 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8097                               struct rte_eth_udp_tunnel *udp_tunnel)
8098 {
8099         int ret = 0;
8100         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8101
8102         if (hw->mac.type != ixgbe_mac_X550 &&
8103             hw->mac.type != ixgbe_mac_X550EM_x &&
8104             hw->mac.type != ixgbe_mac_X550EM_a) {
8105                 return -ENOTSUP;
8106         }
8107
8108         if (udp_tunnel == NULL)
8109                 return -EINVAL;
8110
8111         switch (udp_tunnel->prot_type) {
8112         case RTE_TUNNEL_TYPE_VXLAN:
8113                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8114                 break;
8115
8116         case RTE_TUNNEL_TYPE_GENEVE:
8117         case RTE_TUNNEL_TYPE_TEREDO:
8118                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8119                 ret = -EINVAL;
8120                 break;
8121
8122         default:
8123                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8124                 ret = -EINVAL;
8125                 break;
8126         }
8127
8128         return ret;
8129 }
8130
8131 /* Remove UDP tunneling port */
8132 static int
8133 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8134                               struct rte_eth_udp_tunnel *udp_tunnel)
8135 {
8136         int ret = 0;
8137         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8138
8139         if (hw->mac.type != ixgbe_mac_X550 &&
8140             hw->mac.type != ixgbe_mac_X550EM_x &&
8141             hw->mac.type != ixgbe_mac_X550EM_a) {
8142                 return -ENOTSUP;
8143         }
8144
8145         if (udp_tunnel == NULL)
8146                 return -EINVAL;
8147
8148         switch (udp_tunnel->prot_type) {
8149         case RTE_TUNNEL_TYPE_VXLAN:
8150                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8151                 break;
8152         case RTE_TUNNEL_TYPE_GENEVE:
8153         case RTE_TUNNEL_TYPE_TEREDO:
8154                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8155                 ret = -EINVAL;
8156                 break;
8157         default:
8158                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8159                 ret = -EINVAL;
8160                 break;
8161         }
8162
8163         return ret;
8164 }
8165
8166 static void
8167 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8168 {
8169         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8170
8171         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8172 }
8173
8174 static void
8175 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8176 {
8177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8178
8179         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8180 }
8181
8182 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8183 {
8184         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8185         u32 in_msg = 0;
8186
8187         /* peek the message first */
8188         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8189
8190         /* PF reset VF event */
8191         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8192                 /* dummy mbx read to ack pf */
8193                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8194                         return;
8195                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8196                                               NULL);
8197         }
8198 }
8199
8200 static int
8201 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8202 {
8203         uint32_t eicr;
8204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8205         struct ixgbe_interrupt *intr =
8206                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8207         ixgbevf_intr_disable(hw);
8208
8209         /* read-on-clear nic registers here */
8210         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8211         intr->flags = 0;
8212
8213         /* only one misc vector supported - mailbox */
8214         eicr &= IXGBE_VTEICR_MASK;
8215         if (eicr == IXGBE_MISC_VEC_ID)
8216                 intr->flags |= IXGBE_FLAG_MAILBOX;
8217
8218         return 0;
8219 }
8220
8221 static int
8222 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8223 {
8224         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8225         struct ixgbe_interrupt *intr =
8226                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8227
8228         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8229                 ixgbevf_mbx_process(dev);
8230                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8231         }
8232
8233         ixgbevf_intr_enable(hw);
8234
8235         return 0;
8236 }
8237
8238 static void
8239 ixgbevf_dev_interrupt_handler(void *param)
8240 {
8241         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8242
8243         ixgbevf_dev_interrupt_get_status(dev);
8244         ixgbevf_dev_interrupt_action(dev);
8245 }
8246
8247 /**
8248  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8249  *  @hw: pointer to hardware structure
8250  *
8251  *  Stops the transmit data path and waits for the HW to internally empty
8252  *  the Tx security block
8253  **/
8254 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8255 {
8256 #define IXGBE_MAX_SECTX_POLL 40
8257
8258         int i;
8259         int sectxreg;
8260
8261         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8262         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8263         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8264         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8265                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8266                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8267                         break;
8268                 /* Use interrupt-safe sleep just in case */
8269                 usec_delay(1000);
8270         }
8271
8272         /* For informational purposes only */
8273         if (i >= IXGBE_MAX_SECTX_POLL)
8274                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8275                          "path fully disabled.  Continuing with init.");
8276
8277         return IXGBE_SUCCESS;
8278 }
8279
8280 /**
8281  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8282  *  @hw: pointer to hardware structure
8283  *
8284  *  Enables the transmit data path.
8285  **/
8286 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8287 {
8288         uint32_t sectxreg;
8289
8290         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8291         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8292         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8293         IXGBE_WRITE_FLUSH(hw);
8294
8295         return IXGBE_SUCCESS;
8296 }
8297
8298 /* restore n-tuple filter */
8299 static inline void
8300 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8301 {
8302         struct ixgbe_filter_info *filter_info =
8303                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8304         struct ixgbe_5tuple_filter *node;
8305
8306         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8307                 ixgbe_inject_5tuple_filter(dev, node);
8308         }
8309 }
8310
8311 /* restore ethernet type filter */
8312 static inline void
8313 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8314 {
8315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8316         struct ixgbe_filter_info *filter_info =
8317                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8318         int i;
8319
8320         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8321                 if (filter_info->ethertype_mask & (1 << i)) {
8322                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8323                                         filter_info->ethertype_filters[i].etqf);
8324                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8325                                         filter_info->ethertype_filters[i].etqs);
8326                         IXGBE_WRITE_FLUSH(hw);
8327                 }
8328         }
8329 }
8330
8331 /* restore SYN filter */
8332 static inline void
8333 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8334 {
8335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8336         struct ixgbe_filter_info *filter_info =
8337                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8338         uint32_t synqf;
8339
8340         synqf = filter_info->syn_info;
8341
8342         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8343                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8344                 IXGBE_WRITE_FLUSH(hw);
8345         }
8346 }
8347
8348 /* restore L2 tunnel filter */
8349 static inline void
8350 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8351 {
8352         struct ixgbe_l2_tn_info *l2_tn_info =
8353                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8354         struct ixgbe_l2_tn_filter *node;
8355         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8356
8357         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8358                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8359                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8360                 l2_tn_conf.pool           = node->pool;
8361                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8362         }
8363 }
8364
8365 /* restore rss filter */
8366 static inline void
8367 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8368 {
8369         struct ixgbe_filter_info *filter_info =
8370                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8371
8372         if (filter_info->rss_info.conf.queue_num)
8373                 ixgbe_config_rss_filter(dev,
8374                         &filter_info->rss_info, TRUE);
8375 }
8376
8377 static int
8378 ixgbe_filter_restore(struct rte_eth_dev *dev)
8379 {
8380         ixgbe_ntuple_filter_restore(dev);
8381         ixgbe_ethertype_filter_restore(dev);
8382         ixgbe_syn_filter_restore(dev);
8383         ixgbe_fdir_filter_restore(dev);
8384         ixgbe_l2_tn_filter_restore(dev);
8385         ixgbe_rss_filter_restore(dev);
8386
8387         return 0;
8388 }
8389
8390 static void
8391 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8392 {
8393         struct ixgbe_l2_tn_info *l2_tn_info =
8394                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8396
8397         if (l2_tn_info->e_tag_en)
8398                 (void)ixgbe_e_tag_enable(hw);
8399
8400         if (l2_tn_info->e_tag_fwd_en)
8401                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8402
8403         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8404 }
8405
8406 /* remove all the n-tuple filters */
8407 void
8408 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8409 {
8410         struct ixgbe_filter_info *filter_info =
8411                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8412         struct ixgbe_5tuple_filter *p_5tuple;
8413
8414         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8415                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8416 }
8417
8418 /* remove all the ether type filters */
8419 void
8420 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8421 {
8422         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8423         struct ixgbe_filter_info *filter_info =
8424                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8425         int i;
8426
8427         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8428                 if (filter_info->ethertype_mask & (1 << i) &&
8429                     !filter_info->ethertype_filters[i].conf) {
8430                         (void)ixgbe_ethertype_filter_remove(filter_info,
8431                                                             (uint8_t)i);
8432                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8433                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8434                         IXGBE_WRITE_FLUSH(hw);
8435                 }
8436         }
8437 }
8438
8439 /* remove the SYN filter */
8440 void
8441 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8442 {
8443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8444         struct ixgbe_filter_info *filter_info =
8445                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8446
8447         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8448                 filter_info->syn_info = 0;
8449
8450                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8451                 IXGBE_WRITE_FLUSH(hw);
8452         }
8453 }
8454
8455 /* remove all the L2 tunnel filters */
8456 int
8457 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8458 {
8459         struct ixgbe_l2_tn_info *l2_tn_info =
8460                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8461         struct ixgbe_l2_tn_filter *l2_tn_filter;
8462         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8463         int ret = 0;
8464
8465         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8466                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8467                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8468                 l2_tn_conf.pool           = l2_tn_filter->pool;
8469                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8470                 if (ret < 0)
8471                         return ret;
8472         }
8473
8474         return 0;
8475 }
8476
8477 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8478 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8479 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8480 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8481 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8482 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8483
8484 RTE_INIT(ixgbe_init_log);
8485 static void
8486 ixgbe_init_log(void)
8487 {
8488         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8489         if (ixgbe_logtype_init >= 0)
8490                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8491         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8492         if (ixgbe_logtype_driver >= 0)
8493                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8494 }