drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 549         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 550         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 551         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 552         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 553         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 554         .dev_led_on           = ixgbe_dev_led_on,
 555         .dev_led_off          = ixgbe_dev_led_off,
 556         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 557         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 558         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 559         .mac_addr_add         = ixgbe_add_rar,
 560         .mac_addr_remove      = ixgbe_remove_rar,
 561         .mac_addr_set         = ixgbe_set_default_mac_addr,
 562         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 563         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 564         .mirror_rule_set      = ixgbe_mirror_rule_set,
 565         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 566         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 567         .reta_update          = ixgbe_dev_rss_reta_update,
 568         .reta_query           = ixgbe_dev_rss_reta_query,
 569         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 570         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 571         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 572         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 573         .rxq_info_get         = ixgbe_rxq_info_get,
 574         .txq_info_get         = ixgbe_txq_info_get,
 575         .timesync_enable      = ixgbe_timesync_enable,
 576         .timesync_disable     = ixgbe_timesync_disable,
 577         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 578         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 579         .get_reg              = ixgbe_get_regs,
 580         .get_eeprom_length    = ixgbe_get_eeprom_length,
 581         .get_eeprom           = ixgbe_get_eeprom,
 582         .set_eeprom           = ixgbe_set_eeprom,
 583         .get_module_info      = ixgbe_get_module_info,
 584         .get_module_eeprom    = ixgbe_get_module_eeprom,
 585         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 586         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 587         .timesync_read_time   = ixgbe_timesync_read_time,
 588         .timesync_write_time  = ixgbe_timesync_write_time,
 589         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 590         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 591         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 592         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 593         .tm_ops_get           = ixgbe_tm_ops_get,
 594         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 595 };
 596
 597 /*
 598  * dev_ops for virtual function, bare necessities for basic vf
 599  * operation have been implemented
 600  */
 601 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 602         .dev_configure        = ixgbevf_dev_configure,
 603         .dev_start            = ixgbevf_dev_start,
 604         .dev_stop             = ixgbevf_dev_stop,
 605         .link_update          = ixgbevf_dev_link_update,
 606         .stats_get            = ixgbevf_dev_stats_get,
 607         .xstats_get           = ixgbevf_dev_xstats_get,
 608         .stats_reset          = ixgbevf_dev_stats_reset,
 609         .xstats_reset         = ixgbevf_dev_stats_reset,
 610         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 611         .dev_close            = ixgbevf_dev_close,
 612         .dev_reset            = ixgbevf_dev_reset,
 613         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 614         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 615         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 616         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 617         .dev_infos_get        = ixgbevf_dev_info_get,
 618         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 619         .mtu_set              = ixgbevf_dev_set_mtu,
 620         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 621         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 622         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 623         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 624         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 625         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 626         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 627         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 628         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 629         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 630         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 631         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 632         .mac_addr_add         = ixgbevf_add_mac_addr,
 633         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 634         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 635         .rxq_info_get         = ixgbe_rxq_info_get,
 636         .txq_info_get         = ixgbe_txq_info_get,
 637         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 638         .get_reg              = ixgbevf_get_regs,
 639         .reta_update          = ixgbe_dev_rss_reta_update,
 640         .reta_query           = ixgbe_dev_rss_reta_query,
 641         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 642         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 643         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 644 };
 645
 646 /* store statistics names and its offset in stats structure */
 647 struct rte_ixgbe_xstats_name_off {
 648         char name[RTE_ETH_XSTATS_NAME_SIZE];
 649         unsigned offset;
 650 };
 651
 652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 653         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 654         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 655         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 656         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 657         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 658         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 659         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 660         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 661         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 662         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 663         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 664         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 665         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 666         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 667         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 668                 prc1023)},
 669         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 670                 prc1522)},
 671         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 672         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 673         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 674         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 675         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 676         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 677         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 678         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 679         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 680         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 681         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 682         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 683         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 684         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 685         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 686         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 687         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 688                 ptc1023)},
 689         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 690                 ptc1522)},
 691         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 692         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 693         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 694         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 695
 696         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirustat_add)},
 698         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 699                 fdirustat_remove)},
 700         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 701                 fdirfstat_fadd)},
 702         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 703                 fdirfstat_fremove)},
 704         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirmatch)},
 706         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirmiss)},
 708
 709         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 710         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 711         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 712                 fclast)},
 713         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 714         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 715         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 716         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 717         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 718                 fcoe_noddp)},
 719         {"rx_fcoe_no_direct_data_placement_ext_buff",
 720                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 721
 722         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 723                 lxontxc)},
 724         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxonrxc)},
 726         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxofftxc)},
 728         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxoffrxc)},
 730         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 731 };
 732
 733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 734                            sizeof(rte_ixgbe_stats_strings[0]))
 735
 736 /* MACsec statistics */
 737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 738         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 739                 out_pkts_untagged)},
 740         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_encrypted)},
 742         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_protected)},
 744         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_octets_encrypted)},
 746         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_octets_protected)},
 748         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_untagged)},
 750         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_badtag)},
 752         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_nosci)},
 754         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unknownsci)},
 756         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 757                 in_octets_decrypted)},
 758         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 759                 in_octets_validated)},
 760         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unchecked)},
 762         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_delayed)},
 764         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_late)},
 766         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_ok)},
 768         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_invalid)},
 770         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_notvalid)},
 772         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unusedsa)},
 774         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notusingsa)},
 776 };
 777
 778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 779                            sizeof(rte_ixgbe_macsec_strings[0]))
 780
 781 /* Per-queue statistics */
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 783         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 784         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 785         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 786         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 787 };
 788
 789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 790                            sizeof(rte_ixgbe_rxq_strings[0]))
 791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 792
 793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 794         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 795         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 796         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 797                 pxon2offc)},
 798 };
 799
 800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 801                            sizeof(rte_ixgbe_txq_strings[0]))
 802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 803
 804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 805         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 806 };
 807
 808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 809                 sizeof(rte_ixgbevf_stats_strings[0]))
 810
 811 /*
 812  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 813  */
 814 static inline int
 815 ixgbe_is_sfp(struct ixgbe_hw *hw)
 816 {
 817         switch (hw->phy.type) {
 818         case ixgbe_phy_sfp_avago:
 819         case ixgbe_phy_sfp_ftl:
 820         case ixgbe_phy_sfp_intel:
 821         case ixgbe_phy_sfp_unknown:
 822         case ixgbe_phy_sfp_passive_tyco:
 823         case ixgbe_phy_sfp_passive_unknown:
 824                 return 1;
 825         default:
 826                 return 0;
 827         }
 828 }
 829
 830 static inline int32_t
 831 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 832 {
 833         uint32_t ctrl_ext;
 834         int32_t status;
 835
 836         status = ixgbe_reset_hw(hw);
 837
 838         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 839         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 840         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 841         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 842         IXGBE_WRITE_FLUSH(hw);
 843
 844         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 845                 status = IXGBE_SUCCESS;
 846         return status;
 847 }
 848
 849 static inline void
 850 ixgbe_enable_intr(struct rte_eth_dev *dev)
 851 {
 852         struct ixgbe_interrupt *intr =
 853                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 854         struct ixgbe_hw *hw =
 855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 856
 857         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 858         IXGBE_WRITE_FLUSH(hw);
 859 }
 860
 861 /*
 862  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 863  */
 864 static void
 865 ixgbe_disable_intr(struct ixgbe_hw *hw)
 866 {
 867         PMD_INIT_FUNC_TRACE();
 868
 869         if (hw->mac.type == ixgbe_mac_82598EB) {
 870                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 871         } else {
 872                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 873                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 874                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 875         }
 876         IXGBE_WRITE_FLUSH(hw);
 877 }
 878
 879 /*
 880  * This function resets queue statistics mapping registers.
 881  * From Niantic datasheet, Initialization of Statistics section:
 882  * "...if software requires the queue counters, the RQSMR and TQSM registers
 883  * must be re-programmed following a device reset.
 884  */
 885 static void
 886 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 887 {
 888         uint32_t i;
 889
 890         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 891                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 892                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 893         }
 894 }
 895
 896
 897 static int
 898 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 899                                   uint16_t queue_id,
 900                                   uint8_t stat_idx,
 901                                   uint8_t is_rx)
 902 {
 903 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 904 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 905 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 906
 907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 908         struct ixgbe_stat_mapping_registers *stat_mappings =
 909                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 910         uint32_t qsmr_mask = 0;
 911         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 912         uint32_t q_map;
 913         uint8_t n, offset;
 914
 915         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 916                 (hw->mac.type != ixgbe_mac_X540) &&
 917                 (hw->mac.type != ixgbe_mac_X550) &&
 918                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 919                 (hw->mac.type != ixgbe_mac_X550EM_a))
 920                 return -ENOSYS;
 921
 922         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 923                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 924                      queue_id, stat_idx);
 925
 926         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 927         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 928                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 929                 return -EIO;
 930         }
 931         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 932
 933         /* Now clear any previous stat_idx set */
 934         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 935         if (!is_rx)
 936                 stat_mappings->tqsm[n] &= ~clearing_mask;
 937         else
 938                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 939
 940         q_map = (uint32_t)stat_idx;
 941         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 942         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 943         if (!is_rx)
 944                 stat_mappings->tqsm[n] |= qsmr_mask;
 945         else
 946                 stat_mappings->rqsmr[n] |= qsmr_mask;
 947
 948         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 949                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 950                      queue_id, stat_idx);
 951         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 952                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 953
 954         /* Now write the mapping in the appropriate register */
 955         if (is_rx) {
 956                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 957                              stat_mappings->rqsmr[n], n);
 958                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 959         } else {
 960                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 961                              stat_mappings->tqsm[n], n);
 962                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 963         }
 964         return 0;
 965 }
 966
 967 static void
 968 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 969 {
 970         struct ixgbe_stat_mapping_registers *stat_mappings =
 971                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 973         int i;
 974
 975         /* write whatever was in stat mapping table to the NIC */
 976         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 977                 /* rx */
 978                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 979
 980                 /* tx */
 981                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 982         }
 983 }
 984
 985 static void
 986 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 987 {
 988         uint8_t i;
 989         struct ixgbe_dcb_tc_config *tc;
 990         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 991
 992         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 993         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 994         for (i = 0; i < dcb_max_tc; i++) {
 995                 tc = &dcb_config->tc_config[i];
 996                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 997                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 998                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 999                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1000                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1001                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1002                 tc->pfc = ixgbe_dcb_pfc_disabled;
1003         }
1004
1005         /* Initialize default user to priority mapping, UPx->TC0 */
1006         tc = &dcb_config->tc_config[0];
1007         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1008         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1009         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1010                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1011                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1012         }
1013         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1014         dcb_config->pfc_mode_enable = false;
1015         dcb_config->vt_mode = true;
1016         dcb_config->round_robin_enable = false;
1017         /* support all DCB capabilities in 82599 */
1018         dcb_config->support.capabilities = 0xFF;
1019
1020         /*we only support 4 Tcs for X540, X550 */
1021         if (hw->mac.type == ixgbe_mac_X540 ||
1022                 hw->mac.type == ixgbe_mac_X550 ||
1023                 hw->mac.type == ixgbe_mac_X550EM_x ||
1024                 hw->mac.type == ixgbe_mac_X550EM_a) {
1025                 dcb_config->num_tcs.pg_tcs = 4;
1026                 dcb_config->num_tcs.pfc_tcs = 4;
1027         }
1028 }
1029
1030 /*
1031  * Ensure that all locks are released before first NVM or PHY access
1032  */
1033 static void
1034 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1035 {
1036         uint16_t mask;
1037
1038         /*
1039          * Phy lock should not fail in this early stage. If this is the case,
1040          * it is due to an improper exit of the application.
1041          * So force the release of the faulty lock. Release of common lock
1042          * is done automatically by swfw_sync function.
1043          */
1044         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1045         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1046                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1047         }
1048         ixgbe_release_swfw_semaphore(hw, mask);
1049
1050         /*
1051          * These ones are more tricky since they are common to all ports; but
1052          * swfw_sync retries last long enough (1s) to be almost sure that if
1053          * lock can not be taken it is due to an improper lock of the
1054          * semaphore.
1055          */
1056         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1057         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1058                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1059         }
1060         ixgbe_release_swfw_semaphore(hw, mask);
1061 }
1062
1063 /*
1064  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1065  * It returns 0 on success.
1066  */
1067 static int
1068 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1069 {
1070         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1071         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1072         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1073         struct ixgbe_hw *hw =
1074                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1075         struct ixgbe_vfta *shadow_vfta =
1076                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1077         struct ixgbe_hwstrip *hwstrip =
1078                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1079         struct ixgbe_dcb_config *dcb_config =
1080                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1081         struct ixgbe_filter_info *filter_info =
1082                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1083         struct ixgbe_bw_conf *bw_conf =
1084                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1085         uint32_t ctrl_ext;
1086         uint16_t csum;
1087         int diag, i;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         ixgbe_dev_macsec_setting_reset(eth_dev);
1092
1093         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1094         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1095         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1096         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1097
1098         /*
1099          * For secondary processes, we don't initialise any further as primary
1100          * has already done this work. Only check we don't need a different
1101          * RX and TX function.
1102          */
1103         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1104                 struct ixgbe_tx_queue *txq;
1105                 /* TX queue function in primary, set by last queue initialized
1106                  * Tx queue may not initialized by primary process
1107                  */
1108                 if (eth_dev->data->tx_queues) {
1109                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1110                         ixgbe_set_tx_function(eth_dev, txq);
1111                 } else {
1112                         /* Use default TX function if we get here */
1113                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1114                                      "Using default TX function.");
1115                 }
1116
1117                 ixgbe_set_rx_function(eth_dev);
1118
1119                 return 0;
1120         }
1121
1122         rte_atomic32_clear(&ad->link_thread_running);
1123         rte_eth_copy_pci_info(eth_dev, pci_dev);
1124
1125         /* Vendor and Device ID need to be set before init of shared code */
1126         hw->device_id = pci_dev->id.device_id;
1127         hw->vendor_id = pci_dev->id.vendor_id;
1128         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1129         hw->allow_unsupported_sfp = 1;
1130
1131         /* Initialize the shared code (base driver) */
1132 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1133         diag = ixgbe_bypass_init_shared_code(hw);
1134 #else
1135         diag = ixgbe_init_shared_code(hw);
1136 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1137
1138         if (diag != IXGBE_SUCCESS) {
1139                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1140                 return -EIO;
1141         }
1142
1143         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1144                 PMD_INIT_LOG(ERR, "\nERROR: "
1145                         "Firmware recovery mode detected. Limiting functionality.\n"
1146                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1147                         "User Guide for details on firmware recovery mode.");
1148                 return -EIO;
1149         }
1150
1151         /* pick up the PCI bus settings for reporting later */
1152         ixgbe_get_bus_info(hw);
1153
1154         /* Unlock any pending hardware semaphore */
1155         ixgbe_swfw_lock_reset(hw);
1156
1157 #ifdef RTE_LIBRTE_SECURITY
1158         /* Initialize security_ctx only for primary process*/
1159         if (ixgbe_ipsec_ctx_create(eth_dev))
1160                 return -ENOMEM;
1161 #endif
1162
1163         /* Initialize DCB configuration*/
1164         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1165         ixgbe_dcb_init(hw, dcb_config);
1166         /* Get Hardware Flow Control setting */
1167         hw->fc.requested_mode = ixgbe_fc_none;
1168         hw->fc.current_mode = ixgbe_fc_none;
1169         hw->fc.pause_time = IXGBE_FC_PAUSE;
1170         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1171                 hw->fc.low_water[i] = IXGBE_FC_LO;
1172                 hw->fc.high_water[i] = IXGBE_FC_HI;
1173         }
1174         hw->fc.send_xon = 1;
1175
1176         /* Make sure we have a good EEPROM before we read from it */
1177         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1178         if (diag != IXGBE_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1180                 return -EIO;
1181         }
1182
1183 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1184         diag = ixgbe_bypass_init_hw(hw);
1185 #else
1186         diag = ixgbe_init_hw(hw);
1187 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1188
1189         /*
1190          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1191          * is called too soon after the kernel driver unbinding/binding occurs.
1192          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1193          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1194          * also called. See ixgbe_identify_phy_82599(). The reason for the
1195          * failure is not known, and only occuts when virtualisation features
1196          * are disabled in the bios. A delay of 100ms  was found to be enough by
1197          * trial-and-error, and is doubled to be safe.
1198          */
1199         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1200                 rte_delay_ms(200);
1201                 diag = ixgbe_init_hw(hw);
1202         }
1203
1204         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1205                 diag = IXGBE_SUCCESS;
1206
1207         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1208                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1209                              "LOM.  Please be aware there may be issues associated "
1210                              "with your hardware.");
1211                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1212                              "please contact your Intel or hardware representative "
1213                              "who provided you with this hardware.");
1214         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1215                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1216         if (diag) {
1217                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1218                 return -EIO;
1219         }
1220
1221         /* Reset the hw statistics */
1222         ixgbe_dev_stats_reset(eth_dev);
1223
1224         /* disable interrupt */
1225         ixgbe_disable_intr(hw);
1226
1227         /* reset mappings for queue statistics hw counters*/
1228         ixgbe_reset_qstat_mappings(hw);
1229
1230         /* Allocate memory for storing MAC addresses */
1231         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1232                                                hw->mac.num_rar_entries, 0);
1233         if (eth_dev->data->mac_addrs == NULL) {
1234                 PMD_INIT_LOG(ERR,
1235                              "Failed to allocate %u bytes needed to store "
1236                              "MAC addresses",
1237                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1238                 return -ENOMEM;
1239         }
1240         /* Copy the permanent MAC address */
1241         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1242                         &eth_dev->data->mac_addrs[0]);
1243
1244         /* Allocate memory for storing hash filter MAC addresses */
1245         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1246                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1247         if (eth_dev->data->hash_mac_addrs == NULL) {
1248                 PMD_INIT_LOG(ERR,
1249                              "Failed to allocate %d bytes needed to store MAC addresses",
1250                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1251                 return -ENOMEM;
1252         }
1253
1254         /* Pass the information to the rte_eth_dev_close() that it should also
1255          * release the private port resources.
1256          */
1257         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1258
1259         /* initialize the vfta */
1260         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1261
1262         /* initialize the hw strip bitmap*/
1263         memset(hwstrip, 0, sizeof(*hwstrip));
1264
1265         /* initialize PF if max_vfs not zero */
1266         ixgbe_pf_host_init(eth_dev);
1267
1268         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1269         /* let hardware know driver is loaded */
1270         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1271         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1272         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1273         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1274         IXGBE_WRITE_FLUSH(hw);
1275
1276         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1277                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1278                              (int) hw->mac.type, (int) hw->phy.type,
1279                              (int) hw->phy.sfp_type);
1280         else
1281                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1282                              (int) hw->mac.type, (int) hw->phy.type);
1283
1284         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1285                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1286                      pci_dev->id.device_id);
1287
1288         rte_intr_callback_register(intr_handle,
1289                                    ixgbe_dev_interrupt_handler, eth_dev);
1290
1291         /* enable uio/vfio intr/eventfd mapping */
1292         rte_intr_enable(intr_handle);
1293
1294         /* enable support intr */
1295         ixgbe_enable_intr(eth_dev);
1296
1297         /* initialize filter info */
1298         memset(filter_info, 0,
1299                sizeof(struct ixgbe_filter_info));
1300
1301         /* initialize 5tuple filter list */
1302         TAILQ_INIT(&filter_info->fivetuple_list);
1303
1304         /* initialize flow director filter list & hash */
1305         ixgbe_fdir_filter_init(eth_dev);
1306
1307         /* initialize l2 tunnel filter list & hash */
1308         ixgbe_l2_tn_filter_init(eth_dev);
1309
1310         /* initialize flow filter lists */
1311         ixgbe_filterlist_init();
1312
1313         /* initialize bandwidth configuration info */
1314         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1315
1316         /* initialize Traffic Manager configuration */
1317         ixgbe_tm_conf_init(eth_dev);
1318
1319         return 0;
1320 }
1321
1322 static int
1323 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1324 {
1325         PMD_INIT_FUNC_TRACE();
1326
1327         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1328                 return 0;
1329
1330         ixgbe_dev_close(eth_dev);
1331
1332         return 0;
1333 }
1334
1335 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1336 {
1337         struct ixgbe_filter_info *filter_info =
1338                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1339         struct ixgbe_5tuple_filter *p_5tuple;
1340
1341         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1342                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1343                              p_5tuple,
1344                              entries);
1345                 rte_free(p_5tuple);
1346         }
1347         memset(filter_info->fivetuple_mask, 0,
1348                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1349
1350         return 0;
1351 }
1352
1353 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1354 {
1355         struct ixgbe_hw_fdir_info *fdir_info =
1356                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1357         struct ixgbe_fdir_filter *fdir_filter;
1358
1359                 if (fdir_info->hash_map)
1360                 rte_free(fdir_info->hash_map);
1361         if (fdir_info->hash_handle)
1362                 rte_hash_free(fdir_info->hash_handle);
1363
1364         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365                 TAILQ_REMOVE(&fdir_info->fdir_list,
1366                              fdir_filter,
1367                              entries);
1368                 rte_free(fdir_filter);
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1375 {
1376         struct ixgbe_l2_tn_info *l2_tn_info =
1377                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1378         struct ixgbe_l2_tn_filter *l2_tn_filter;
1379
1380         if (l2_tn_info->hash_map)
1381                 rte_free(l2_tn_info->hash_map);
1382         if (l2_tn_info->hash_handle)
1383                 rte_hash_free(l2_tn_info->hash_handle);
1384
1385         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1386                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1387                              l2_tn_filter,
1388                              entries);
1389                 rte_free(l2_tn_filter);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1396 {
1397         struct ixgbe_hw_fdir_info *fdir_info =
1398                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1399         char fdir_hash_name[RTE_HASH_NAMESIZE];
1400         struct rte_hash_parameters fdir_hash_params = {
1401                 .name = fdir_hash_name,
1402                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1403                 .key_len = sizeof(union ixgbe_atr_input),
1404                 .hash_func = rte_hash_crc,
1405                 .hash_func_init_val = 0,
1406                 .socket_id = rte_socket_id(),
1407         };
1408
1409         TAILQ_INIT(&fdir_info->fdir_list);
1410         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1411                  "fdir_%s", eth_dev->device->name);
1412         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1413         if (!fdir_info->hash_handle) {
1414                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1415                 return -EINVAL;
1416         }
1417         fdir_info->hash_map = rte_zmalloc("ixgbe",
1418                                           sizeof(struct ixgbe_fdir_filter *) *
1419                                           IXGBE_MAX_FDIR_FILTER_NUM,
1420                                           0);
1421         if (!fdir_info->hash_map) {
1422                 PMD_INIT_LOG(ERR,
1423                              "Failed to allocate memory for fdir hash map!");
1424                 return -ENOMEM;
1425         }
1426         fdir_info->mask_added = FALSE;
1427
1428         return 0;
1429 }
1430
1431 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1432 {
1433         struct ixgbe_l2_tn_info *l2_tn_info =
1434                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1435         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1436         struct rte_hash_parameters l2_tn_hash_params = {
1437                 .name = l2_tn_hash_name,
1438                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1439                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1440                 .hash_func = rte_hash_crc,
1441                 .hash_func_init_val = 0,
1442                 .socket_id = rte_socket_id(),
1443         };
1444
1445         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1446         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1447                  "l2_tn_%s", eth_dev->device->name);
1448         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1449         if (!l2_tn_info->hash_handle) {
1450                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1451                 return -EINVAL;
1452         }
1453         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1454                                    sizeof(struct ixgbe_l2_tn_filter *) *
1455                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1456                                    0);
1457         if (!l2_tn_info->hash_map) {
1458                 PMD_INIT_LOG(ERR,
1459                         "Failed to allocate memory for L2 TN hash map!");
1460                 return -ENOMEM;
1461         }
1462         l2_tn_info->e_tag_en = FALSE;
1463         l2_tn_info->e_tag_fwd_en = FALSE;
1464         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1465
1466         return 0;
1467 }
1468 /*
1469  * Negotiate mailbox API version with the PF.
1470  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1471  * Then we try to negotiate starting with the most recent one.
1472  * If all negotiation attempts fail, then we will proceed with
1473  * the default one (ixgbe_mbox_api_10).
1474  */
1475 static void
1476 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1477 {
1478         int32_t i;
1479
1480         /* start with highest supported, proceed down */
1481         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1482                 ixgbe_mbox_api_13,
1483                 ixgbe_mbox_api_12,
1484                 ixgbe_mbox_api_11,
1485                 ixgbe_mbox_api_10,
1486         };
1487
1488         for (i = 0;
1489                         i != RTE_DIM(sup_ver) &&
1490                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1491                         i++)
1492                 ;
1493 }
1494
1495 static void
1496 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1497 {
1498         uint64_t random;
1499
1500         /* Set Organizationally Unique Identifier (OUI) prefix. */
1501         mac_addr->addr_bytes[0] = 0x00;
1502         mac_addr->addr_bytes[1] = 0x09;
1503         mac_addr->addr_bytes[2] = 0xC0;
1504         /* Force indication of locally assigned MAC address. */
1505         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1506         /* Generate the last 3 bytes of the MAC address with a random number. */
1507         random = rte_rand();
1508         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1509 }
1510
1511 static int
1512 devarg_handle_int(__rte_unused const char *key, const char *value,
1513                   void *extra_args)
1514 {
1515         uint16_t *n = extra_args;
1516
1517         if (value == NULL || extra_args == NULL)
1518                 return -EINVAL;
1519
1520         *n = (uint16_t)strtoul(value, NULL, 0);
1521         if (*n == USHRT_MAX && errno == ERANGE)
1522                 return -1;
1523
1524         return 0;
1525 }
1526
1527 static void
1528 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1529                       struct rte_devargs *devargs)
1530 {
1531         struct rte_kvargs *kvlist;
1532         uint16_t pflink_fullchk;
1533
1534         if (devargs == NULL)
1535                 return;
1536
1537         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1538         if (kvlist == NULL)
1539                 return;
1540
1541         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1542             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1543                                devarg_handle_int, &pflink_fullchk) == 0 &&
1544             pflink_fullchk == 1)
1545                 adapter->pflink_fullchk = 1;
1546
1547         rte_kvargs_free(kvlist);
1548 }
1549
1550 /*
1551  * Virtual Function device init
1552  */
1553 static int
1554 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1555 {
1556         int diag;
1557         uint32_t tc, tcs;
1558         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561         struct ixgbe_hw *hw =
1562                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1563         struct ixgbe_vfta *shadow_vfta =
1564                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1565         struct ixgbe_hwstrip *hwstrip =
1566                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1567         struct rte_ether_addr *perm_addr =
1568                 (struct rte_ether_addr *)hw->mac.perm_addr;
1569
1570         PMD_INIT_FUNC_TRACE();
1571
1572         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1573         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1574         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1575
1576         /* for secondary processes, we don't initialise any further as primary
1577          * has already done this work. Only check we don't need a different
1578          * RX function
1579          */
1580         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1581                 struct ixgbe_tx_queue *txq;
1582                 /* TX queue function in primary, set by last queue initialized
1583                  * Tx queue may not initialized by primary process
1584                  */
1585                 if (eth_dev->data->tx_queues) {
1586                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1587                         ixgbe_set_tx_function(eth_dev, txq);
1588                 } else {
1589                         /* Use default TX function if we get here */
1590                         PMD_INIT_LOG(NOTICE,
1591                                      "No TX queues configured yet. Using default TX function.");
1592                 }
1593
1594                 ixgbe_set_rx_function(eth_dev);
1595
1596                 return 0;
1597         }
1598
1599         rte_atomic32_clear(&ad->link_thread_running);
1600         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1601                               pci_dev->device.devargs);
1602
1603         rte_eth_copy_pci_info(eth_dev, pci_dev);
1604
1605         hw->device_id = pci_dev->id.device_id;
1606         hw->vendor_id = pci_dev->id.vendor_id;
1607         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1608
1609         /* initialize the vfta */
1610         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1611
1612         /* initialize the hw strip bitmap*/
1613         memset(hwstrip, 0, sizeof(*hwstrip));
1614
1615         /* Initialize the shared code (base driver) */
1616         diag = ixgbe_init_shared_code(hw);
1617         if (diag != IXGBE_SUCCESS) {
1618                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1619                 return -EIO;
1620         }
1621
1622         /* init_mailbox_params */
1623         hw->mbx.ops.init_params(hw);
1624
1625         /* Reset the hw statistics */
1626         ixgbevf_dev_stats_reset(eth_dev);
1627
1628         /* Disable the interrupts for VF */
1629         ixgbevf_intr_disable(eth_dev);
1630
1631         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1632         diag = hw->mac.ops.reset_hw(hw);
1633
1634         /*
1635          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1636          * the underlying PF driver has not assigned a MAC address to the VF.
1637          * In this case, assign a random MAC address.
1638          */
1639         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1640                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1641                 /*
1642                  * This error code will be propagated to the app by
1643                  * rte_eth_dev_reset, so use a public error code rather than
1644                  * the internal-only IXGBE_ERR_RESET_FAILED
1645                  */
1646                 return -EAGAIN;
1647         }
1648
1649         /* negotiate mailbox API version to use with the PF. */
1650         ixgbevf_negotiate_api(hw);
1651
1652         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1653         ixgbevf_get_queues(hw, &tcs, &tc);
1654
1655         /* Allocate memory for storing MAC addresses */
1656         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1657                                                hw->mac.num_rar_entries, 0);
1658         if (eth_dev->data->mac_addrs == NULL) {
1659                 PMD_INIT_LOG(ERR,
1660                              "Failed to allocate %u bytes needed to store "
1661                              "MAC addresses",
1662                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1663                 return -ENOMEM;
1664         }
1665
1666         /* Pass the information to the rte_eth_dev_close() that it should also
1667          * release the private port resources.
1668          */
1669         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1670
1671         /* Generate a random MAC address, if none was assigned by PF. */
1672         if (rte_is_zero_ether_addr(perm_addr)) {
1673                 generate_random_mac_addr(perm_addr);
1674                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1675                 if (diag) {
1676                         rte_free(eth_dev->data->mac_addrs);
1677                         eth_dev->data->mac_addrs = NULL;
1678                         return diag;
1679                 }
1680                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1681                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1682                              "%02x:%02x:%02x:%02x:%02x:%02x",
1683                              perm_addr->addr_bytes[0],
1684                              perm_addr->addr_bytes[1],
1685                              perm_addr->addr_bytes[2],
1686                              perm_addr->addr_bytes[3],
1687                              perm_addr->addr_bytes[4],
1688                              perm_addr->addr_bytes[5]);
1689         }
1690
1691         /* Copy the permanent MAC address */
1692         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1693
1694         /* reset the hardware with the new settings */
1695         diag = hw->mac.ops.start_hw(hw);
1696         switch (diag) {
1697         case  0:
1698                 break;
1699
1700         default:
1701                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1702                 return -EIO;
1703         }
1704
1705         rte_intr_callback_register(intr_handle,
1706                                    ixgbevf_dev_interrupt_handler, eth_dev);
1707         rte_intr_enable(intr_handle);
1708         ixgbevf_intr_enable(eth_dev);
1709
1710         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1711                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1712                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1713
1714         return 0;
1715 }
1716
1717 /* Virtual Function device uninit */
1718
1719 static int
1720 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1721 {
1722         PMD_INIT_FUNC_TRACE();
1723
1724         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1725                 return 0;
1726
1727         ixgbevf_dev_close(eth_dev);
1728
1729         return 0;
1730 }
1731
1732 static int
1733 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1734                 struct rte_pci_device *pci_dev)
1735 {
1736         char name[RTE_ETH_NAME_MAX_LEN];
1737         struct rte_eth_dev *pf_ethdev;
1738         struct rte_eth_devargs eth_da;
1739         int i, retval;
1740
1741         if (pci_dev->device.devargs) {
1742                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1743                                 &eth_da);
1744                 if (retval)
1745                         return retval;
1746         } else
1747                 memset(&eth_da, 0, sizeof(eth_da));
1748
1749         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1750                 sizeof(struct ixgbe_adapter),
1751                 eth_dev_pci_specific_init, pci_dev,
1752                 eth_ixgbe_dev_init, NULL);
1753
1754         if (retval || eth_da.nb_representor_ports < 1)
1755                 return retval;
1756
1757         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1758         if (pf_ethdev == NULL)
1759                 return -ENODEV;
1760
1761         /* probe VF representor ports */
1762         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1763                 struct ixgbe_vf_info *vfinfo;
1764                 struct ixgbe_vf_representor representor;
1765
1766                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1767                         pf_ethdev->data->dev_private);
1768                 if (vfinfo == NULL) {
1769                         PMD_DRV_LOG(ERR,
1770                                 "no virtual functions supported by PF");
1771                         break;
1772                 }
1773
1774                 representor.vf_id = eth_da.representor_ports[i];
1775                 representor.switch_domain_id = vfinfo->switch_domain_id;
1776                 representor.pf_ethdev = pf_ethdev;
1777
1778                 /* representor port net_bdf_port */
1779                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1780                         pci_dev->device.name,
1781                         eth_da.representor_ports[i]);
1782
1783                 retval = rte_eth_dev_create(&pci_dev->device, name,
1784                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1785                         ixgbe_vf_representor_init, &representor);
1786
1787                 if (retval)
1788                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1789                                 "representor %s.", name);
1790         }
1791
1792         return 0;
1793 }
1794
1795 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1796 {
1797         struct rte_eth_dev *ethdev;
1798
1799         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1800         if (!ethdev)
1801                 return 0;
1802
1803         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1804                 return rte_eth_dev_pci_generic_remove(pci_dev,
1805                                         ixgbe_vf_representor_uninit);
1806         else
1807                 return rte_eth_dev_pci_generic_remove(pci_dev,
1808                                                 eth_ixgbe_dev_uninit);
1809 }
1810
1811 static struct rte_pci_driver rte_ixgbe_pmd = {
1812         .id_table = pci_id_ixgbe_map,
1813         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1814         .probe = eth_ixgbe_pci_probe,
1815         .remove = eth_ixgbe_pci_remove,
1816 };
1817
1818 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1819         struct rte_pci_device *pci_dev)
1820 {
1821         return rte_eth_dev_pci_generic_probe(pci_dev,
1822                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1823 }
1824
1825 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1826 {
1827         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1828 }
1829
1830 /*
1831  * virtual function driver struct
1832  */
1833 static struct rte_pci_driver rte_ixgbevf_pmd = {
1834         .id_table = pci_id_ixgbevf_map,
1835         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1836         .probe = eth_ixgbevf_pci_probe,
1837         .remove = eth_ixgbevf_pci_remove,
1838 };
1839
1840 static int
1841 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1842 {
1843         struct ixgbe_hw *hw =
1844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct ixgbe_vfta *shadow_vfta =
1846                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1847         uint32_t vfta;
1848         uint32_t vid_idx;
1849         uint32_t vid_bit;
1850
1851         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1852         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1853         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1854         if (on)
1855                 vfta |= vid_bit;
1856         else
1857                 vfta &= ~vid_bit;
1858         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1859
1860         /* update local VFTA copy */
1861         shadow_vfta->vfta[vid_idx] = vfta;
1862
1863         return 0;
1864 }
1865
1866 static void
1867 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1868 {
1869         if (on)
1870                 ixgbe_vlan_hw_strip_enable(dev, queue);
1871         else
1872                 ixgbe_vlan_hw_strip_disable(dev, queue);
1873 }
1874
1875 static int
1876 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1877                     enum rte_vlan_type vlan_type,
1878                     uint16_t tpid)
1879 {
1880         struct ixgbe_hw *hw =
1881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         int ret = 0;
1883         uint32_t reg;
1884         uint32_t qinq;
1885
1886         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887         qinq &= IXGBE_DMATXCTL_GDV;
1888
1889         switch (vlan_type) {
1890         case ETH_VLAN_TYPE_INNER:
1891                 if (qinq) {
1892                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1893                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1894                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1895                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1896                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1897                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1898                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1899                 } else {
1900                         ret = -ENOTSUP;
1901                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1902                                     " by single VLAN");
1903                 }
1904                 break;
1905         case ETH_VLAN_TYPE_OUTER:
1906                 if (qinq) {
1907                         /* Only the high 16-bits is valid */
1908                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1909                                         IXGBE_EXVET_VET_EXT_SHIFT);
1910                 } else {
1911                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1913                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1914                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1915                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1916                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1917                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1918                 }
1919
1920                 break;
1921         default:
1922                 ret = -EINVAL;
1923                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1924                 break;
1925         }
1926
1927         return ret;
1928 }
1929
1930 void
1931 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1932 {
1933         struct ixgbe_hw *hw =
1934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         uint32_t vlnctrl;
1936
1937         PMD_INIT_FUNC_TRACE();
1938
1939         /* Filter Table Disable */
1940         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1941         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1942
1943         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1944 }
1945
1946 void
1947 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1948 {
1949         struct ixgbe_hw *hw =
1950                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct ixgbe_vfta *shadow_vfta =
1952                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1953         uint32_t vlnctrl;
1954         uint16_t i;
1955
1956         PMD_INIT_FUNC_TRACE();
1957
1958         /* Filter Table Enable */
1959         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1960         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1961         vlnctrl |= IXGBE_VLNCTRL_VFE;
1962
1963         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1964
1965         /* write whatever is in local vfta copy */
1966         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1967                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1968 }
1969
1970 static void
1971 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1972 {
1973         struct ixgbe_hwstrip *hwstrip =
1974                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1975         struct ixgbe_rx_queue *rxq;
1976
1977         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1978                 return;
1979
1980         if (on)
1981                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1982         else
1983                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1984
1985         if (queue >= dev->data->nb_rx_queues)
1986                 return;
1987
1988         rxq = dev->data->rx_queues[queue];
1989
1990         if (on) {
1991                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1992                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1993         } else {
1994                 rxq->vlan_flags = PKT_RX_VLAN;
1995                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1996         }
1997 }
1998
1999 static void
2000 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005
2006         PMD_INIT_FUNC_TRACE();
2007
2008         if (hw->mac.type == ixgbe_mac_82598EB) {
2009                 /* No queue level support */
2010                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2011                 return;
2012         }
2013
2014         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2015         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2016         ctrl &= ~IXGBE_RXDCTL_VME;
2017         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018
2019         /* record those setting for HW strip per queue */
2020         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2021 }
2022
2023 static void
2024 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2025 {
2026         struct ixgbe_hw *hw =
2027                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t ctrl;
2029
2030         PMD_INIT_FUNC_TRACE();
2031
2032         if (hw->mac.type == ixgbe_mac_82598EB) {
2033                 /* No queue level supported */
2034                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2035                 return;
2036         }
2037
2038         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2040         ctrl |= IXGBE_RXDCTL_VME;
2041         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2042
2043         /* record those setting for HW strip per queue */
2044         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2045 }
2046
2047 static void
2048 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2049 {
2050         struct ixgbe_hw *hw =
2051                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         uint32_t ctrl;
2053
2054         PMD_INIT_FUNC_TRACE();
2055
2056         /* DMATXCTRL: Geric Double VLAN Disable */
2057         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2058         ctrl &= ~IXGBE_DMATXCTL_GDV;
2059         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2060
2061         /* CTRL_EXT: Global Double VLAN Disable */
2062         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2063         ctrl &= ~IXGBE_EXTENDED_VLAN;
2064         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2065
2066 }
2067
2068 static void
2069 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2070 {
2071         struct ixgbe_hw *hw =
2072                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         uint32_t ctrl;
2074
2075         PMD_INIT_FUNC_TRACE();
2076
2077         /* DMATXCTRL: Geric Double VLAN Enable */
2078         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2079         ctrl |= IXGBE_DMATXCTL_GDV;
2080         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2081
2082         /* CTRL_EXT: Global Double VLAN Enable */
2083         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2084         ctrl |= IXGBE_EXTENDED_VLAN;
2085         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2086
2087         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2088         if (hw->mac.type == ixgbe_mac_X550 ||
2089             hw->mac.type == ixgbe_mac_X550EM_x ||
2090             hw->mac.type == ixgbe_mac_X550EM_a) {
2091                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2092                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2093                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2094         }
2095
2096         /*
2097          * VET EXT field in the EXVET register = 0x8100 by default
2098          * So no need to change. Same to VT field of DMATXCTL register
2099          */
2100 }
2101
2102 void
2103 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2104 {
2105         struct ixgbe_hw *hw =
2106                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2108         uint32_t ctrl;
2109         uint16_t i;
2110         struct ixgbe_rx_queue *rxq;
2111         bool on;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         if (hw->mac.type == ixgbe_mac_82598EB) {
2116                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2117                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2118                         ctrl |= IXGBE_VLNCTRL_VME;
2119                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2120                 } else {
2121                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2122                         ctrl &= ~IXGBE_VLNCTRL_VME;
2123                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2124                 }
2125         } else {
2126                 /*
2127                  * Other 10G NIC, the VLAN strip can be setup
2128                  * per queue in RXDCTL
2129                  */
2130                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2131                         rxq = dev->data->rx_queues[i];
2132                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2133                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2134                                 ctrl |= IXGBE_RXDCTL_VME;
2135                                 on = TRUE;
2136                         } else {
2137                                 ctrl &= ~IXGBE_RXDCTL_VME;
2138                                 on = FALSE;
2139                         }
2140                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2141
2142                         /* record those setting for HW strip per queue */
2143                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2144                 }
2145         }
2146 }
2147
2148 static void
2149 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2150 {
2151         uint16_t i;
2152         struct rte_eth_rxmode *rxmode;
2153         struct ixgbe_rx_queue *rxq;
2154
2155         if (mask & ETH_VLAN_STRIP_MASK) {
2156                 rxmode = &dev->data->dev_conf.rxmode;
2157                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2158                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                                 rxq = dev->data->rx_queues[i];
2160                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2161                         }
2162                 else
2163                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2164                                 rxq = dev->data->rx_queues[i];
2165                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2166                         }
2167         }
2168 }
2169
2170 static int
2171 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2172 {
2173         struct rte_eth_rxmode *rxmode;
2174         rxmode = &dev->data->dev_conf.rxmode;
2175
2176         if (mask & ETH_VLAN_STRIP_MASK) {
2177                 ixgbe_vlan_hw_strip_config(dev);
2178         }
2179
2180         if (mask & ETH_VLAN_FILTER_MASK) {
2181                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2182                         ixgbe_vlan_hw_filter_enable(dev);
2183                 else
2184                         ixgbe_vlan_hw_filter_disable(dev);
2185         }
2186
2187         if (mask & ETH_VLAN_EXTEND_MASK) {
2188                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2189                         ixgbe_vlan_hw_extend_enable(dev);
2190                 else
2191                         ixgbe_vlan_hw_extend_disable(dev);
2192         }
2193
2194         return 0;
2195 }
2196
2197 static int
2198 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2199 {
2200         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2201
2202         ixgbe_vlan_offload_config(dev, mask);
2203
2204         return 0;
2205 }
2206
2207 static void
2208 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw =
2211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2213         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2214
2215         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2216         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2217 }
2218
2219 static int
2220 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2221 {
2222         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2223
2224         switch (nb_rx_q) {
2225         case 1:
2226         case 2:
2227                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2228                 break;
2229         case 4:
2230                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2231                 break;
2232         default:
2233                 return -EINVAL;
2234         }
2235
2236         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2237                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2238         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2239                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2240         return 0;
2241 }
2242
2243 static int
2244 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2245 {
2246         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2249         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2250
2251         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2252                 /* check multi-queue mode */
2253                 switch (dev_conf->rxmode.mq_mode) {
2254                 case ETH_MQ_RX_VMDQ_DCB:
2255                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2256                         break;
2257                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2258                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2259                         PMD_INIT_LOG(ERR, "SRIOV active,"
2260                                         " unsupported mq_mode rx %d.",
2261                                         dev_conf->rxmode.mq_mode);
2262                         return -EINVAL;
2263                 case ETH_MQ_RX_RSS:
2264                 case ETH_MQ_RX_VMDQ_RSS:
2265                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2266                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2267                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2268                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2269                                                 " invalid queue number"
2270                                                 " for VMDQ RSS, allowed"
2271                                                 " value are 1, 2 or 4.");
2272                                         return -EINVAL;
2273                                 }
2274                         break;
2275                 case ETH_MQ_RX_VMDQ_ONLY:
2276                 case ETH_MQ_RX_NONE:
2277                         /* if nothing mq mode configure, use default scheme */
2278                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2279                         break;
2280                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2281                         /* SRIOV only works in VMDq enable mode */
2282                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2283                                         " wrong mq_mode rx %d.",
2284                                         dev_conf->rxmode.mq_mode);
2285                         return -EINVAL;
2286                 }
2287
2288                 switch (dev_conf->txmode.mq_mode) {
2289                 case ETH_MQ_TX_VMDQ_DCB:
2290                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2291                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2292                         break;
2293                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2294                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2295                         break;
2296                 }
2297
2298                 /* check valid queue number */
2299                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2300                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2301                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2302                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2303                                         " must be less than or equal to %d.",
2304                                         nb_rx_q, nb_tx_q,
2305                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2306                         return -EINVAL;
2307                 }
2308         } else {
2309                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2310                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2311                                           " not supported.");
2312                         return -EINVAL;
2313                 }
2314                 /* check configuration for vmdb+dcb mode */
2315                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2316                         const struct rte_eth_vmdq_dcb_conf *conf;
2317
2318                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2319                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2320                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2321                                 return -EINVAL;
2322                         }
2323                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2324                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2325                                conf->nb_queue_pools == ETH_32_POOLS)) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2327                                                 " nb_queue_pools must be %d or %d.",
2328                                                 ETH_16_POOLS, ETH_32_POOLS);
2329                                 return -EINVAL;
2330                         }
2331                 }
2332                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2333                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2334
2335                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2336                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2337                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2338                                 return -EINVAL;
2339                         }
2340                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2341                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2342                                conf->nb_queue_pools == ETH_32_POOLS)) {
2343                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2344                                                 " nb_queue_pools != %d and"
2345                                                 " nb_queue_pools != %d.",
2346                                                 ETH_16_POOLS, ETH_32_POOLS);
2347                                 return -EINVAL;
2348                         }
2349                 }
2350
2351                 /* For DCB mode check our configuration before we go further */
2352                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2353                         const struct rte_eth_dcb_rx_conf *conf;
2354
2355                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2356                         if (!(conf->nb_tcs == ETH_4_TCS ||
2357                                conf->nb_tcs == ETH_8_TCS)) {
2358                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2359                                                 " and nb_tcs != %d.",
2360                                                 ETH_4_TCS, ETH_8_TCS);
2361                                 return -EINVAL;
2362                         }
2363                 }
2364
2365                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2366                         const struct rte_eth_dcb_tx_conf *conf;
2367
2368                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2369                         if (!(conf->nb_tcs == ETH_4_TCS ||
2370                                conf->nb_tcs == ETH_8_TCS)) {
2371                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372                                                 " and nb_tcs != %d.",
2373                                                 ETH_4_TCS, ETH_8_TCS);
2374                                 return -EINVAL;
2375                         }
2376                 }
2377
2378                 /*
2379                  * When DCB/VT is off, maximum number of queues changes,
2380                  * except for 82598EB, which remains constant.
2381                  */
2382                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2383                                 hw->mac.type != ixgbe_mac_82598EB) {
2384                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2385                                 PMD_INIT_LOG(ERR,
2386                                              "Neither VT nor DCB are enabled, "
2387                                              "nb_tx_q > %d.",
2388                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2389                                 return -EINVAL;
2390                         }
2391                 }
2392         }
2393         return 0;
2394 }
2395
2396 static int
2397 ixgbe_dev_configure(struct rte_eth_dev *dev)
2398 {
2399         struct ixgbe_interrupt *intr =
2400                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2401         struct ixgbe_adapter *adapter = dev->data->dev_private;
2402         int ret;
2403
2404         PMD_INIT_FUNC_TRACE();
2405
2406         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2407                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2408
2409         /* multipe queue mode checking */
2410         ret  = ixgbe_check_mq_mode(dev);
2411         if (ret != 0) {
2412                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2413                             ret);
2414                 return ret;
2415         }
2416
2417         /* set flag to update link status after init */
2418         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2419
2420         /*
2421          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2422          * allocation or vector Rx preconditions we will reset it.
2423          */
2424         adapter->rx_bulk_alloc_allowed = true;
2425         adapter->rx_vec_allowed = true;
2426
2427         return 0;
2428 }
2429
2430 static void
2431 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2432 {
2433         struct ixgbe_hw *hw =
2434                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         struct ixgbe_interrupt *intr =
2436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2437         uint32_t gpie;
2438
2439         /* only set up it on X550EM_X */
2440         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2441                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2442                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2443                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2444                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2445                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2446         }
2447 }
2448
2449 int
2450 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2451                         uint16_t tx_rate, uint64_t q_msk)
2452 {
2453         struct ixgbe_hw *hw;
2454         struct ixgbe_vf_info *vfinfo;
2455         struct rte_eth_link link;
2456         uint8_t  nb_q_per_pool;
2457         uint32_t queue_stride;
2458         uint32_t queue_idx, idx = 0, vf_idx;
2459         uint32_t queue_end;
2460         uint16_t total_rate = 0;
2461         struct rte_pci_device *pci_dev;
2462         int ret;
2463
2464         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2465         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2466         if (ret < 0)
2467                 return ret;
2468
2469         if (vf >= pci_dev->max_vfs)
2470                 return -EINVAL;
2471
2472         if (tx_rate > link.link_speed)
2473                 return -EINVAL;
2474
2475         if (q_msk == 0)
2476                 return 0;
2477
2478         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2480         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2481         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2482         queue_idx = vf * queue_stride;
2483         queue_end = queue_idx + nb_q_per_pool - 1;
2484         if (queue_end >= hw->mac.max_tx_queues)
2485                 return -EINVAL;
2486
2487         if (vfinfo) {
2488                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2489                         if (vf_idx == vf)
2490                                 continue;
2491                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2492                                 idx++)
2493                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2494                 }
2495         } else {
2496                 return -EINVAL;
2497         }
2498
2499         /* Store tx_rate for this vf. */
2500         for (idx = 0; idx < nb_q_per_pool; idx++) {
2501                 if (((uint64_t)0x1 << idx) & q_msk) {
2502                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2503                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2504                         total_rate += tx_rate;
2505                 }
2506         }
2507
2508         if (total_rate > dev->data->dev_link.link_speed) {
2509                 /* Reset stored TX rate of the VF if it causes exceed
2510                  * link speed.
2511                  */
2512                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2513                 return -EINVAL;
2514         }
2515
2516         /* Set RTTBCNRC of each queue/pool for vf X  */
2517         for (; queue_idx <= queue_end; queue_idx++) {
2518                 if (0x1 & q_msk)
2519                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2520                 q_msk = q_msk >> 1;
2521         }
2522
2523         return 0;
2524 }
2525
2526 static int
2527 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2528 {
2529         struct ixgbe_adapter *adapter = dev->data->dev_private;
2530         int err;
2531         uint32_t mflcn;
2532
2533         ixgbe_setup_fc(hw);
2534
2535         err = ixgbe_fc_enable(hw);
2536
2537         /* Not negotiated is not an error case */
2538         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2539                 /*
2540                  *check if we want to forward MAC frames - driver doesn't
2541                  *have native capability to do that,
2542                  *so we'll write the registers ourselves
2543                  */
2544
2545                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2546
2547                 /* set or clear MFLCN.PMCF bit depending on configuration */
2548                 if (adapter->mac_ctrl_frame_fwd != 0)
2549                         mflcn |= IXGBE_MFLCN_PMCF;
2550                 else
2551                         mflcn &= ~IXGBE_MFLCN_PMCF;
2552
2553                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2554                 IXGBE_WRITE_FLUSH(hw);
2555
2556                 return 0;
2557         }
2558         return err;
2559 }
2560
2561 /*
2562  * Configure device link speed and setup link.
2563  * It returns 0 on success.
2564  */
2565 static int
2566 ixgbe_dev_start(struct rte_eth_dev *dev)
2567 {
2568         struct ixgbe_hw *hw =
2569                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570         struct ixgbe_vf_info *vfinfo =
2571                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2572         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2574         uint32_t intr_vector = 0;
2575         int err;
2576         bool link_up = false, negotiate = 0;
2577         uint32_t speed = 0;
2578         uint32_t allowed_speeds = 0;
2579         int mask = 0;
2580         int status;
2581         uint16_t vf, idx;
2582         uint32_t *link_speeds;
2583         struct ixgbe_tm_conf *tm_conf =
2584                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2585         struct ixgbe_macsec_setting *macsec_setting =
2586                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2587
2588         PMD_INIT_FUNC_TRACE();
2589
2590         /* Stop the link setup handler before resetting the HW. */
2591         ixgbe_dev_wait_setup_link_complete(dev, 0);
2592
2593         /* disable uio/vfio intr/eventfd mapping */
2594         rte_intr_disable(intr_handle);
2595
2596         /* stop adapter */
2597         hw->adapter_stopped = 0;
2598         ixgbe_stop_adapter(hw);
2599
2600         /* reinitialize adapter
2601          * this calls reset and start
2602          */
2603         status = ixgbe_pf_reset_hw(hw);
2604         if (status != 0)
2605                 return -1;
2606         hw->mac.ops.start_hw(hw);
2607         hw->mac.get_link_status = true;
2608
2609         /* configure PF module if SRIOV enabled */
2610         ixgbe_pf_host_configure(dev);
2611
2612         ixgbe_dev_phy_intr_setup(dev);
2613
2614         /* check and configure queue intr-vector mapping */
2615         if ((rte_intr_cap_multiple(intr_handle) ||
2616              !RTE_ETH_DEV_SRIOV(dev).active) &&
2617             dev->data->dev_conf.intr_conf.rxq != 0) {
2618                 intr_vector = dev->data->nb_rx_queues;
2619                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2620                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2621                                         IXGBE_MAX_INTR_QUEUE_NUM);
2622                         return -ENOTSUP;
2623                 }
2624                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2625                         return -1;
2626         }
2627
2628         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2629                 intr_handle->intr_vec =
2630                         rte_zmalloc("intr_vec",
2631                                     dev->data->nb_rx_queues * sizeof(int), 0);
2632                 if (intr_handle->intr_vec == NULL) {
2633                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2634                                      " intr_vec", dev->data->nb_rx_queues);
2635                         return -ENOMEM;
2636                 }
2637         }
2638
2639         /* confiugre msix for sleep until rx interrupt */
2640         ixgbe_configure_msix(dev);
2641
2642         /* initialize transmission unit */
2643         ixgbe_dev_tx_init(dev);
2644
2645         /* This can fail when allocating mbufs for descriptor rings */
2646         err = ixgbe_dev_rx_init(dev);
2647         if (err) {
2648                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2649                 goto error;
2650         }
2651
2652         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2653                 ETH_VLAN_EXTEND_MASK;
2654         err = ixgbe_vlan_offload_config(dev, mask);
2655         if (err) {
2656                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2657                 goto error;
2658         }
2659
2660         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2661                 /* Enable vlan filtering for VMDq */
2662                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2663         }
2664
2665         /* Configure DCB hw */
2666         ixgbe_configure_dcb(dev);
2667
2668         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2669                 err = ixgbe_fdir_configure(dev);
2670                 if (err)
2671                         goto error;
2672         }
2673
2674         /* Restore vf rate limit */
2675         if (vfinfo != NULL) {
2676                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2677                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2678                                 if (vfinfo[vf].tx_rate[idx] != 0)
2679                                         ixgbe_set_vf_rate_limit(
2680                                                 dev, vf,
2681                                                 vfinfo[vf].tx_rate[idx],
2682                                                 1 << idx);
2683         }
2684
2685         ixgbe_restore_statistics_mapping(dev);
2686
2687         err = ixgbe_flow_ctrl_enable(dev, hw);
2688         if (err < 0) {
2689                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2690                 goto error;
2691         }
2692
2693         err = ixgbe_dev_rxtx_start(dev);
2694         if (err < 0) {
2695                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2696                 goto error;
2697         }
2698
2699         /* Skip link setup if loopback mode is enabled. */
2700         if (dev->data->dev_conf.lpbk_mode != 0) {
2701                 err = ixgbe_check_supported_loopback_mode(dev);
2702                 if (err < 0) {
2703                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2704                         goto error;
2705                 } else {
2706                         goto skip_link_setup;
2707                 }
2708         }
2709
2710         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2711                 err = hw->mac.ops.setup_sfp(hw);
2712                 if (err)
2713                         goto error;
2714         }
2715
2716         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2717                 /* Turn on the copper */
2718                 ixgbe_set_phy_power(hw, true);
2719         } else {
2720                 /* Turn on the laser */
2721                 ixgbe_enable_tx_laser(hw);
2722         }
2723
2724         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2725         if (err)
2726                 goto error;
2727         dev->data->dev_link.link_status = link_up;
2728
2729         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2730         if (err)
2731                 goto error;
2732
2733         switch (hw->mac.type) {
2734         case ixgbe_mac_X550:
2735         case ixgbe_mac_X550EM_x:
2736         case ixgbe_mac_X550EM_a:
2737                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2738                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2739                         ETH_LINK_SPEED_10G;
2740                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2741                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2742                         allowed_speeds = ETH_LINK_SPEED_10M |
2743                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2744                 break;
2745         default:
2746                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2747                         ETH_LINK_SPEED_10G;
2748         }
2749
2750         link_speeds = &dev->data->dev_conf.link_speeds;
2751
2752         /* Ignore autoneg flag bit and check the validity of
2753          * link_speed
2754          */
2755         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2756                 PMD_INIT_LOG(ERR, "Invalid link setting");
2757                 goto error;
2758         }
2759
2760         speed = 0x0;
2761         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2762                 switch (hw->mac.type) {
2763                 case ixgbe_mac_82598EB:
2764                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2765                         break;
2766                 case ixgbe_mac_82599EB:
2767                 case ixgbe_mac_X540:
2768                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2769                         break;
2770                 case ixgbe_mac_X550:
2771                 case ixgbe_mac_X550EM_x:
2772                 case ixgbe_mac_X550EM_a:
2773                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2774                         break;
2775                 default:
2776                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2777                 }
2778         } else {
2779                 if (*link_speeds & ETH_LINK_SPEED_10G)
2780                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2781                 if (*link_speeds & ETH_LINK_SPEED_5G)
2782                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2783                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2784                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2785                 if (*link_speeds & ETH_LINK_SPEED_1G)
2786                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2787                 if (*link_speeds & ETH_LINK_SPEED_100M)
2788                         speed |= IXGBE_LINK_SPEED_100_FULL;
2789                 if (*link_speeds & ETH_LINK_SPEED_10M)
2790                         speed |= IXGBE_LINK_SPEED_10_FULL;
2791         }
2792
2793         err = ixgbe_setup_link(hw, speed, link_up);
2794         if (err)
2795                 goto error;
2796
2797 skip_link_setup:
2798
2799         if (rte_intr_allow_others(intr_handle)) {
2800                 /* check if lsc interrupt is enabled */
2801                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2802                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2803                 else
2804                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2805                 ixgbe_dev_macsec_interrupt_setup(dev);
2806         } else {
2807                 rte_intr_callback_unregister(intr_handle,
2808                                              ixgbe_dev_interrupt_handler, dev);
2809                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2810                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2811                                      " no intr multiplex");
2812         }
2813
2814         /* check if rxq interrupt is enabled */
2815         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2816             rte_intr_dp_is_en(intr_handle))
2817                 ixgbe_dev_rxq_interrupt_setup(dev);
2818
2819         /* enable uio/vfio intr/eventfd mapping */
2820         rte_intr_enable(intr_handle);
2821
2822         /* resume enabled intr since hw reset */
2823         ixgbe_enable_intr(dev);
2824         ixgbe_l2_tunnel_conf(dev);
2825         ixgbe_filter_restore(dev);
2826
2827         if (tm_conf->root && !tm_conf->committed)
2828                 PMD_DRV_LOG(WARNING,
2829                             "please call hierarchy_commit() "
2830                             "before starting the port");
2831
2832         /* wait for the controller to acquire link */
2833         err = ixgbe_wait_for_link_up(hw);
2834         if (err)
2835                 goto error;
2836
2837         /*
2838          * Update link status right before return, because it may
2839          * start link configuration process in a separate thread.
2840          */
2841         ixgbe_dev_link_update(dev, 0);
2842
2843         /* setup the macsec setting register */
2844         if (macsec_setting->offload_en)
2845                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2846
2847         return 0;
2848
2849 error:
2850         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2851         ixgbe_dev_clear_queues(dev);
2852         return -EIO;
2853 }
2854
2855 /*
2856  * Stop device: disable rx and tx functions to allow for reconfiguring.
2857  */
2858 static void
2859 ixgbe_dev_stop(struct rte_eth_dev *dev)
2860 {
2861         struct rte_eth_link link;
2862         struct ixgbe_adapter *adapter = dev->data->dev_private;
2863         struct ixgbe_hw *hw =
2864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         struct ixgbe_vf_info *vfinfo =
2866                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2867         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2868         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2869         int vf;
2870         struct ixgbe_tm_conf *tm_conf =
2871                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2872
2873         if (hw->adapter_stopped)
2874                 return;
2875
2876         PMD_INIT_FUNC_TRACE();
2877
2878         ixgbe_dev_wait_setup_link_complete(dev, 0);
2879
2880         /* disable interrupts */
2881         ixgbe_disable_intr(hw);
2882
2883         /* reset the NIC */
2884         ixgbe_pf_reset_hw(hw);
2885         hw->adapter_stopped = 0;
2886
2887         /* stop adapter */
2888         ixgbe_stop_adapter(hw);
2889
2890         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2891                 vfinfo[vf].clear_to_send = false;
2892
2893         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2894                 /* Turn off the copper */
2895                 ixgbe_set_phy_power(hw, false);
2896         } else {
2897                 /* Turn off the laser */
2898                 ixgbe_disable_tx_laser(hw);
2899         }
2900
2901         ixgbe_dev_clear_queues(dev);
2902
2903         /* Clear stored conf */
2904         dev->data->scattered_rx = 0;
2905         dev->data->lro = 0;
2906
2907         /* Clear recorded link status */
2908         memset(&link, 0, sizeof(link));
2909         rte_eth_linkstatus_set(dev, &link);
2910
2911         if (!rte_intr_allow_others(intr_handle))
2912                 /* resume to the default handler */
2913                 rte_intr_callback_register(intr_handle,
2914                                            ixgbe_dev_interrupt_handler,
2915                                            (void *)dev);
2916
2917         /* Clean datapath event and queue/vec mapping */
2918         rte_intr_efd_disable(intr_handle);
2919         if (intr_handle->intr_vec != NULL) {
2920                 rte_free(intr_handle->intr_vec);
2921                 intr_handle->intr_vec = NULL;
2922         }
2923
2924         /* reset hierarchy commit */
2925         tm_conf->committed = false;
2926
2927         adapter->rss_reta_updated = 0;
2928
2929         adapter->mac_ctrl_frame_fwd = 0;
2930
2931         hw->adapter_stopped = true;
2932 }
2933
2934 /*
2935  * Set device link up: enable tx.
2936  */
2937 static int
2938 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2939 {
2940         struct ixgbe_hw *hw =
2941                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942         if (hw->mac.type == ixgbe_mac_82599EB) {
2943 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2944                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2945                         /* Not suported in bypass mode */
2946                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2947                                      "by device id 0x%x", hw->device_id);
2948                         return -ENOTSUP;
2949                 }
2950 #endif
2951         }
2952
2953         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2954                 /* Turn on the copper */
2955                 ixgbe_set_phy_power(hw, true);
2956         } else {
2957                 /* Turn on the laser */
2958                 ixgbe_enable_tx_laser(hw);
2959                 ixgbe_dev_link_update(dev, 0);
2960         }
2961
2962         return 0;
2963 }
2964
2965 /*
2966  * Set device link down: disable tx.
2967  */
2968 static int
2969 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2970 {
2971         struct ixgbe_hw *hw =
2972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2973         if (hw->mac.type == ixgbe_mac_82599EB) {
2974 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2975                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2976                         /* Not suported in bypass mode */
2977                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2978                                      "by device id 0x%x", hw->device_id);
2979                         return -ENOTSUP;
2980                 }
2981 #endif
2982         }
2983
2984         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2985                 /* Turn off the copper */
2986                 ixgbe_set_phy_power(hw, false);
2987         } else {
2988                 /* Turn off the laser */
2989                 ixgbe_disable_tx_laser(hw);
2990                 ixgbe_dev_link_update(dev, 0);
2991         }
2992
2993         return 0;
2994 }
2995
2996 /*
2997  * Reset and stop device.
2998  */
2999 static void
3000 ixgbe_dev_close(struct rte_eth_dev *dev)
3001 {
3002         struct ixgbe_hw *hw =
3003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3005         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3006         int retries = 0;
3007         int ret;
3008
3009         PMD_INIT_FUNC_TRACE();
3010
3011         ixgbe_pf_reset_hw(hw);
3012
3013         ixgbe_dev_stop(dev);
3014
3015         ixgbe_dev_free_queues(dev);
3016
3017         ixgbe_disable_pcie_master(hw);
3018
3019         /* reprogram the RAR[0] in case user changed it. */
3020         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3021
3022         dev->dev_ops = NULL;
3023         dev->rx_pkt_burst = NULL;
3024         dev->tx_pkt_burst = NULL;
3025
3026         /* Unlock any pending hardware semaphore */
3027         ixgbe_swfw_lock_reset(hw);
3028
3029         /* disable uio intr before callback unregister */
3030         rte_intr_disable(intr_handle);
3031
3032         do {
3033                 ret = rte_intr_callback_unregister(intr_handle,
3034                                 ixgbe_dev_interrupt_handler, dev);
3035                 if (ret >= 0 || ret == -ENOENT) {
3036                         break;
3037                 } else if (ret != -EAGAIN) {
3038                         PMD_INIT_LOG(ERR,
3039                                 "intr callback unregister failed: %d",
3040                                 ret);
3041                 }
3042                 rte_delay_ms(100);
3043         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3044
3045         /* cancel the delay handler before remove dev */
3046         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3047
3048         /* uninitialize PF if max_vfs not zero */
3049         ixgbe_pf_host_uninit(dev);
3050
3051         /* remove all the fdir filters & hash */
3052         ixgbe_fdir_filter_uninit(dev);
3053
3054         /* remove all the L2 tunnel filters & hash */
3055         ixgbe_l2_tn_filter_uninit(dev);
3056
3057         /* Remove all ntuple filters of the device */
3058         ixgbe_ntuple_filter_uninit(dev);
3059
3060         /* clear all the filters list */
3061         ixgbe_filterlist_flush();
3062
3063         /* Remove all Traffic Manager configuration */
3064         ixgbe_tm_conf_uninit(dev);
3065
3066 #ifdef RTE_LIBRTE_SECURITY
3067         rte_free(dev->security_ctx);
3068 #endif
3069
3070 }
3071
3072 /*
3073  * Reset PF device.
3074  */
3075 static int
3076 ixgbe_dev_reset(struct rte_eth_dev *dev)
3077 {
3078         int ret;
3079
3080         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3081          * its VF to make them align with it. The detailed notification
3082          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3083          * To avoid unexpected behavior in VF, currently reset of PF with
3084          * SR-IOV activation is not supported. It might be supported later.
3085          */
3086         if (dev->data->sriov.active)
3087                 return -ENOTSUP;
3088
3089         ret = eth_ixgbe_dev_uninit(dev);
3090         if (ret)
3091                 return ret;
3092
3093         ret = eth_ixgbe_dev_init(dev, NULL);
3094
3095         return ret;
3096 }
3097
3098 static void
3099 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3100                            struct ixgbe_hw_stats *hw_stats,
3101                            struct ixgbe_macsec_stats *macsec_stats,
3102                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3103                            uint64_t *total_qprc, uint64_t *total_qprdc)
3104 {
3105         uint32_t bprc, lxon, lxoff, total;
3106         uint32_t delta_gprc = 0;
3107         unsigned i;
3108         /* Workaround for RX byte count not including CRC bytes when CRC
3109          * strip is enabled. CRC bytes are removed from counters when crc_strip
3110          * is disabled.
3111          */
3112         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3113                         IXGBE_HLREG0_RXCRCSTRP);
3114
3115         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3116         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3117         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3118         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3119
3120         for (i = 0; i < 8; i++) {
3121                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3122
3123                 /* global total per queue */
3124                 hw_stats->mpc[i] += mp;
3125                 /* Running comprehensive total for stats display */
3126                 *total_missed_rx += hw_stats->mpc[i];
3127                 if (hw->mac.type == ixgbe_mac_82598EB) {
3128                         hw_stats->rnbc[i] +=
3129                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3130                         hw_stats->pxonrxc[i] +=
3131                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3132                         hw_stats->pxoffrxc[i] +=
3133                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3134                 } else {
3135                         hw_stats->pxonrxc[i] +=
3136                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3137                         hw_stats->pxoffrxc[i] +=
3138                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3139                         hw_stats->pxon2offc[i] +=
3140                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3141                 }
3142                 hw_stats->pxontxc[i] +=
3143                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3144                 hw_stats->pxofftxc[i] +=
3145                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3146         }
3147         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3148                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3149                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3150                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3151
3152                 delta_gprc += delta_qprc;
3153
3154                 hw_stats->qprc[i] += delta_qprc;
3155                 hw_stats->qptc[i] += delta_qptc;
3156
3157                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3158                 hw_stats->qbrc[i] +=
3159                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3160                 if (crc_strip == 0)
3161                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3162
3163                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3164                 hw_stats->qbtc[i] +=
3165                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3166
3167                 hw_stats->qprdc[i] += delta_qprdc;
3168                 *total_qprdc += hw_stats->qprdc[i];
3169
3170                 *total_qprc += hw_stats->qprc[i];
3171                 *total_qbrc += hw_stats->qbrc[i];
3172         }
3173         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3174         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3175         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3176
3177         /*
3178          * An errata states that gprc actually counts good + missed packets:
3179          * Workaround to set gprc to summated queue packet receives
3180          */
3181         hw_stats->gprc = *total_qprc;
3182
3183         if (hw->mac.type != ixgbe_mac_82598EB) {
3184                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3185                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3186                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3187                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3188                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3189                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3190                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3191                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3192         } else {
3193                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3194                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3195                 /* 82598 only has a counter in the high register */
3196                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3197                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3198                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3199         }
3200         uint64_t old_tpr = hw_stats->tpr;
3201
3202         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3203         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3204
3205         if (crc_strip == 0)
3206                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3207
3208         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3209         hw_stats->gptc += delta_gptc;
3210         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3211         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3212
3213         /*
3214          * Workaround: mprc hardware is incorrectly counting
3215          * broadcasts, so for now we subtract those.
3216          */
3217         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3218         hw_stats->bprc += bprc;
3219         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3220         if (hw->mac.type == ixgbe_mac_82598EB)
3221                 hw_stats->mprc -= bprc;
3222
3223         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3224         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3225         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3226         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3227         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3228         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3229
3230         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3231         hw_stats->lxontxc += lxon;
3232         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3233         hw_stats->lxofftxc += lxoff;
3234         total = lxon + lxoff;
3235
3236         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3237         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3238         hw_stats->gptc -= total;
3239         hw_stats->mptc -= total;
3240         hw_stats->ptc64 -= total;
3241         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3242
3243         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3244         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3245         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3246         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3247         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3248         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3249         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3250         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3251         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3252         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3253         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3254         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3255         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3256         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3257         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3258         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3259         /* Only read FCOE on 82599 */
3260         if (hw->mac.type != ixgbe_mac_82598EB) {
3261                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3262                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3263                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3264                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3265                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3266         }
3267
3268         /* Flow Director Stats registers */
3269         if (hw->mac.type != ixgbe_mac_82598EB) {
3270                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3271                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3272                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3273                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3274                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3275                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3276                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3277                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3278                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3279                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3280         }
3281         /* MACsec Stats registers */
3282         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3283         macsec_stats->out_pkts_encrypted +=
3284                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3285         macsec_stats->out_pkts_protected +=
3286                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3287         macsec_stats->out_octets_encrypted +=
3288                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3289         macsec_stats->out_octets_protected +=
3290                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3291         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3292         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3293         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3294         macsec_stats->in_pkts_unknownsci +=
3295                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3296         macsec_stats->in_octets_decrypted +=
3297                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3298         macsec_stats->in_octets_validated +=
3299                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3300         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3301         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3302         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3303         for (i = 0; i < 2; i++) {
3304                 macsec_stats->in_pkts_ok +=
3305                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3306                 macsec_stats->in_pkts_invalid +=
3307                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3308                 macsec_stats->in_pkts_notvalid +=
3309                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3310         }
3311         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3312         macsec_stats->in_pkts_notusingsa +=
3313                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3314 }
3315
3316 /*
3317  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3318  */
3319 static int
3320 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3321 {
3322         struct ixgbe_hw *hw =
3323                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3324         struct ixgbe_hw_stats *hw_stats =
3325                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3326         struct ixgbe_macsec_stats *macsec_stats =
3327                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3328                                 dev->data->dev_private);
3329         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3330         unsigned i;
3331
3332         total_missed_rx = 0;
3333         total_qbrc = 0;
3334         total_qprc = 0;
3335         total_qprdc = 0;
3336
3337         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3338                         &total_qbrc, &total_qprc, &total_qprdc);
3339
3340         if (stats == NULL)
3341                 return -EINVAL;
3342
3343         /* Fill out the rte_eth_stats statistics structure */
3344         stats->ipackets = total_qprc;
3345         stats->ibytes = total_qbrc;
3346         stats->opackets = hw_stats->gptc;
3347         stats->obytes = hw_stats->gotc;
3348
3349         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3350                 stats->q_ipackets[i] = hw_stats->qprc[i];
3351                 stats->q_opackets[i] = hw_stats->qptc[i];
3352                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3353                 stats->q_obytes[i] = hw_stats->qbtc[i];
3354                 stats->q_errors[i] = hw_stats->qprdc[i];
3355         }
3356
3357         /* Rx Errors */
3358         stats->imissed  = total_missed_rx;
3359         stats->ierrors  = hw_stats->crcerrs +
3360                           hw_stats->mspdc +
3361                           hw_stats->rlec +
3362                           hw_stats->ruc +
3363                           hw_stats->roc +
3364                           hw_stats->illerrc +
3365                           hw_stats->errbc +
3366                           hw_stats->rfc +
3367                           hw_stats->fccrc +
3368                           hw_stats->fclast;
3369
3370         /* Tx Errors */
3371         stats->oerrors  = 0;
3372         return 0;
3373 }
3374
3375 static int
3376 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3377 {
3378         struct ixgbe_hw_stats *stats =
3379                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3380
3381         /* HW registers are cleared on read */
3382         ixgbe_dev_stats_get(dev, NULL);
3383
3384         /* Reset software totals */
3385         memset(stats, 0, sizeof(*stats));
3386
3387         return 0;
3388 }
3389
3390 /* This function calculates the number of xstats based on the current config */
3391 static unsigned
3392 ixgbe_xstats_calc_num(void) {
3393         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3394                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3395                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3396 }
3397
3398 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3399         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3400 {
3401         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3402         unsigned stat, i, count;
3403
3404         if (xstats_names != NULL) {
3405                 count = 0;
3406
3407                 /* Note: limit >= cnt_stats checked upstream
3408                  * in rte_eth_xstats_names()
3409                  */
3410
3411                 /* Extended stats from ixgbe_hw_stats */
3412                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3413                         strlcpy(xstats_names[count].name,
3414                                 rte_ixgbe_stats_strings[i].name,
3415                                 sizeof(xstats_names[count].name));
3416                         count++;
3417                 }
3418
3419                 /* MACsec Stats */
3420                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3421                         strlcpy(xstats_names[count].name,
3422                                 rte_ixgbe_macsec_strings[i].name,
3423                                 sizeof(xstats_names[count].name));
3424                         count++;
3425                 }
3426
3427                 /* RX Priority Stats */
3428                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3429                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3430                                 snprintf(xstats_names[count].name,
3431                                         sizeof(xstats_names[count].name),
3432                                         "rx_priority%u_%s", i,
3433                                         rte_ixgbe_rxq_strings[stat].name);
3434                                 count++;
3435                         }
3436                 }
3437
3438                 /* TX Priority Stats */
3439                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3440                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3441                                 snprintf(xstats_names[count].name,
3442                                         sizeof(xstats_names[count].name),
3443                                         "tx_priority%u_%s", i,
3444                                         rte_ixgbe_txq_strings[stat].name);
3445                                 count++;
3446                         }
3447                 }
3448         }
3449         return cnt_stats;
3450 }
3451
3452 static int ixgbe_dev_xstats_get_names_by_id(
3453         struct rte_eth_dev *dev,
3454         struct rte_eth_xstat_name *xstats_names,
3455         const uint64_t *ids,
3456         unsigned int limit)
3457 {
3458         if (!ids) {
3459                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3460                 unsigned int stat, i, count;
3461
3462                 if (xstats_names != NULL) {
3463                         count = 0;
3464
3465                         /* Note: limit >= cnt_stats checked upstream
3466                          * in rte_eth_xstats_names()
3467                          */
3468
3469                         /* Extended stats from ixgbe_hw_stats */
3470                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3471                                 strlcpy(xstats_names[count].name,
3472                                         rte_ixgbe_stats_strings[i].name,
3473                                         sizeof(xstats_names[count].name));
3474                                 count++;
3475                         }
3476
3477                         /* MACsec Stats */
3478                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3479                                 strlcpy(xstats_names[count].name,
3480                                         rte_ixgbe_macsec_strings[i].name,
3481                                         sizeof(xstats_names[count].name));
3482                                 count++;
3483                         }
3484
3485                         /* RX Priority Stats */
3486                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3487                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3488                                         snprintf(xstats_names[count].name,
3489                                             sizeof(xstats_names[count].name),
3490                                             "rx_priority%u_%s", i,
3491                                             rte_ixgbe_rxq_strings[stat].name);
3492                                         count++;
3493                                 }
3494                         }
3495
3496                         /* TX Priority Stats */
3497                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3498                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3499                                         snprintf(xstats_names[count].name,
3500                                             sizeof(xstats_names[count].name),
3501                                             "tx_priority%u_%s", i,
3502                                             rte_ixgbe_txq_strings[stat].name);
3503                                         count++;
3504                                 }
3505                         }
3506                 }
3507                 return cnt_stats;
3508         }
3509
3510         uint16_t i;
3511         uint16_t size = ixgbe_xstats_calc_num();
3512         struct rte_eth_xstat_name xstats_names_copy[size];
3513
3514         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3515                         size);
3516
3517         for (i = 0; i < limit; i++) {
3518                 if (ids[i] >= size) {
3519                         PMD_INIT_LOG(ERR, "id value isn't valid");
3520                         return -1;
3521                 }
3522                 strcpy(xstats_names[i].name,
3523                                 xstats_names_copy[ids[i]].name);
3524         }
3525         return limit;
3526 }
3527
3528 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3529         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3530 {
3531         unsigned i;
3532
3533         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3534                 return -ENOMEM;
3535
3536         if (xstats_names != NULL)
3537                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3538                         strlcpy(xstats_names[i].name,
3539                                 rte_ixgbevf_stats_strings[i].name,
3540                                 sizeof(xstats_names[i].name));
3541         return IXGBEVF_NB_XSTATS;
3542 }
3543
3544 static int
3545 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3546                                          unsigned n)
3547 {
3548         struct ixgbe_hw *hw =
3549                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3550         struct ixgbe_hw_stats *hw_stats =
3551                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3552         struct ixgbe_macsec_stats *macsec_stats =
3553                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3554                                 dev->data->dev_private);
3555         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3556         unsigned i, stat, count = 0;
3557
3558         count = ixgbe_xstats_calc_num();
3559
3560         if (n < count)
3561                 return count;
3562
3563         total_missed_rx = 0;
3564         total_qbrc = 0;
3565         total_qprc = 0;
3566         total_qprdc = 0;
3567
3568         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3569                         &total_qbrc, &total_qprc, &total_qprdc);
3570
3571         /* If this is a reset xstats is NULL, and we have cleared the
3572          * registers by reading them.
3573          */
3574         if (!xstats)
3575                 return 0;
3576
3577         /* Extended stats from ixgbe_hw_stats */
3578         count = 0;
3579         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3580                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3581                                 rte_ixgbe_stats_strings[i].offset);
3582                 xstats[count].id = count;
3583                 count++;
3584         }
3585
3586         /* MACsec Stats */
3587         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3588                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3589                                 rte_ixgbe_macsec_strings[i].offset);
3590                 xstats[count].id = count;
3591                 count++;
3592         }
3593
3594         /* RX Priority Stats */
3595         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3596                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3597                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3598                                         rte_ixgbe_rxq_strings[stat].offset +
3599                                         (sizeof(uint64_t) * i));
3600                         xstats[count].id = count;
3601                         count++;
3602                 }
3603         }
3604
3605         /* TX Priority Stats */
3606         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3607                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3608                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3609                                         rte_ixgbe_txq_strings[stat].offset +
3610                                         (sizeof(uint64_t) * i));
3611                         xstats[count].id = count;
3612                         count++;
3613                 }
3614         }
3615         return count;
3616 }
3617
3618 static int
3619 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3620                 uint64_t *values, unsigned int n)
3621 {
3622         if (!ids) {
3623                 struct ixgbe_hw *hw =
3624                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3625                 struct ixgbe_hw_stats *hw_stats =
3626                                 IXGBE_DEV_PRIVATE_TO_STATS(
3627                                                 dev->data->dev_private);
3628                 struct ixgbe_macsec_stats *macsec_stats =
3629                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3630                                         dev->data->dev_private);
3631                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3632                 unsigned int i, stat, count = 0;
3633
3634                 count = ixgbe_xstats_calc_num();
3635
3636                 if (!ids && n < count)
3637                         return count;
3638
3639                 total_missed_rx = 0;
3640                 total_qbrc = 0;
3641                 total_qprc = 0;
3642                 total_qprdc = 0;
3643
3644                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3645                                 &total_missed_rx, &total_qbrc, &total_qprc,
3646                                 &total_qprdc);
3647
3648                 /* If this is a reset xstats is NULL, and we have cleared the
3649                  * registers by reading them.
3650                  */
3651                 if (!ids && !values)
3652                         return 0;
3653
3654                 /* Extended stats from ixgbe_hw_stats */
3655                 count = 0;
3656                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3657                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3658                                         rte_ixgbe_stats_strings[i].offset);
3659                         count++;
3660                 }
3661
3662                 /* MACsec Stats */
3663                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3664                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3665                                         rte_ixgbe_macsec_strings[i].offset);
3666                         count++;
3667                 }
3668
3669                 /* RX Priority Stats */
3670                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3671                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3672                                 values[count] =
3673                                         *(uint64_t *)(((char *)hw_stats) +
3674                                         rte_ixgbe_rxq_strings[stat].offset +
3675                                         (sizeof(uint64_t) * i));
3676                                 count++;
3677                         }
3678                 }
3679
3680                 /* TX Priority Stats */
3681                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3682                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3683                                 values[count] =
3684                                         *(uint64_t *)(((char *)hw_stats) +
3685                                         rte_ixgbe_txq_strings[stat].offset +
3686                                         (sizeof(uint64_t) * i));
3687                                 count++;
3688                         }
3689                 }
3690                 return count;
3691         }
3692
3693         uint16_t i;
3694         uint16_t size = ixgbe_xstats_calc_num();
3695         uint64_t values_copy[size];
3696
3697         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3698
3699         for (i = 0; i < n; i++) {
3700                 if (ids[i] >= size) {
3701                         PMD_INIT_LOG(ERR, "id value isn't valid");
3702                         return -1;
3703                 }
3704                 values[i] = values_copy[ids[i]];
3705         }
3706         return n;
3707 }
3708
3709 static int
3710 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3711 {
3712         struct ixgbe_hw_stats *stats =
3713                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3714         struct ixgbe_macsec_stats *macsec_stats =
3715                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3716                                 dev->data->dev_private);
3717
3718         unsigned count = ixgbe_xstats_calc_num();
3719
3720         /* HW registers are cleared on read */
3721         ixgbe_dev_xstats_get(dev, NULL, count);
3722
3723         /* Reset software totals */
3724         memset(stats, 0, sizeof(*stats));
3725         memset(macsec_stats, 0, sizeof(*macsec_stats));
3726
3727         return 0;
3728 }
3729
3730 static void
3731 ixgbevf_update_stats(struct rte_eth_dev *dev)
3732 {
3733         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3734         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3735                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3736
3737         /* Good Rx packet, include VF loopback */
3738         UPDATE_VF_STAT(IXGBE_VFGPRC,
3739             hw_stats->last_vfgprc, hw_stats->vfgprc);
3740
3741         /* Good Rx octets, include VF loopback */
3742         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3743             hw_stats->last_vfgorc, hw_stats->vfgorc);
3744
3745         /* Good Tx packet, include VF loopback */
3746         UPDATE_VF_STAT(IXGBE_VFGPTC,
3747             hw_stats->last_vfgptc, hw_stats->vfgptc);
3748
3749         /* Good Tx octets, include VF loopback */
3750         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3751             hw_stats->last_vfgotc, hw_stats->vfgotc);
3752
3753         /* Rx Multicst Packet */
3754         UPDATE_VF_STAT(IXGBE_VFMPRC,
3755             hw_stats->last_vfmprc, hw_stats->vfmprc);
3756 }
3757
3758 static int
3759 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3760                        unsigned n)
3761 {
3762         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3763                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3764         unsigned i;
3765
3766         if (n < IXGBEVF_NB_XSTATS)
3767                 return IXGBEVF_NB_XSTATS;
3768
3769         ixgbevf_update_stats(dev);
3770
3771         if (!xstats)
3772                 return 0;
3773
3774         /* Extended stats */
3775         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3776                 xstats[i].id = i;
3777                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3778                         rte_ixgbevf_stats_strings[i].offset);
3779         }
3780
3781         return IXGBEVF_NB_XSTATS;
3782 }
3783
3784 static int
3785 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3786 {
3787         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3788                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3789
3790         ixgbevf_update_stats(dev);
3791
3792         if (stats == NULL)
3793                 return -EINVAL;
3794
3795         stats->ipackets = hw_stats->vfgprc;
3796         stats->ibytes = hw_stats->vfgorc;
3797         stats->opackets = hw_stats->vfgptc;
3798         stats->obytes = hw_stats->vfgotc;
3799         return 0;
3800 }
3801
3802 static int
3803 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3804 {
3805         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3806                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3807
3808         /* Sync HW register to the last stats */
3809         ixgbevf_dev_stats_get(dev, NULL);
3810
3811         /* reset HW current stats*/
3812         hw_stats->vfgprc = 0;
3813         hw_stats->vfgorc = 0;
3814         hw_stats->vfgptc = 0;
3815         hw_stats->vfgotc = 0;
3816
3817         return 0;
3818 }
3819
3820 static int
3821 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3822 {
3823         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3824         u16 eeprom_verh, eeprom_verl;
3825         u32 etrack_id;
3826         int ret;
3827
3828         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3829         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3830
3831         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3832         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3833
3834         ret += 1; /* add the size of '\0' */
3835         if (fw_size < (u32)ret)
3836                 return ret;
3837         else
3838                 return 0;
3839 }
3840
3841 static int
3842 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3843 {
3844         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3845         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3846         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3847
3848         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3849         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3850         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3851                 /*
3852                  * When DCB/VT is off, maximum number of queues changes,
3853                  * except for 82598EB, which remains constant.
3854                  */
3855                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3856                                 hw->mac.type != ixgbe_mac_82598EB)
3857                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3858         }
3859         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3860         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3861         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3862         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3863         dev_info->max_vfs = pci_dev->max_vfs;
3864         if (hw->mac.type == ixgbe_mac_82598EB)
3865                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3866         else
3867                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3868         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3869         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3870         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3871         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3872         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3873                                      dev_info->rx_queue_offload_capa);
3874         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3875         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3876
3877         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3878                 .rx_thresh = {
3879                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3880                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3881                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3882                 },
3883                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3884                 .rx_drop_en = 0,
3885                 .offloads = 0,
3886         };
3887
3888         dev_info->default_txconf = (struct rte_eth_txconf) {
3889                 .tx_thresh = {
3890                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3891                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3892                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3893                 },
3894                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3895                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3896                 .offloads = 0,
3897         };
3898
3899         dev_info->rx_desc_lim = rx_desc_lim;
3900         dev_info->tx_desc_lim = tx_desc_lim;
3901
3902         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3903         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3904         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3905
3906         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3907         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3908                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3909                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3910                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3911
3912         if (hw->mac.type == ixgbe_mac_X540 ||
3913             hw->mac.type == ixgbe_mac_X540_vf ||
3914             hw->mac.type == ixgbe_mac_X550 ||
3915             hw->mac.type == ixgbe_mac_X550_vf) {
3916                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3917         }
3918         if (hw->mac.type == ixgbe_mac_X550) {
3919                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3920                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3921         }
3922
3923         /* Driver-preferred Rx/Tx parameters */
3924         dev_info->default_rxportconf.burst_size = 32;
3925         dev_info->default_txportconf.burst_size = 32;
3926         dev_info->default_rxportconf.nb_queues = 1;
3927         dev_info->default_txportconf.nb_queues = 1;
3928         dev_info->default_rxportconf.ring_size = 256;
3929         dev_info->default_txportconf.ring_size = 256;
3930
3931         return 0;
3932 }
3933
3934 static const uint32_t *
3935 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3936 {
3937         static const uint32_t ptypes[] = {
3938                 /* For non-vec functions,
3939                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3940                  * for vec functions,
3941                  * refers to _recv_raw_pkts_vec().
3942                  */
3943                 RTE_PTYPE_L2_ETHER,
3944                 RTE_PTYPE_L3_IPV4,
3945                 RTE_PTYPE_L3_IPV4_EXT,
3946                 RTE_PTYPE_L3_IPV6,
3947                 RTE_PTYPE_L3_IPV6_EXT,
3948                 RTE_PTYPE_L4_SCTP,
3949                 RTE_PTYPE_L4_TCP,
3950                 RTE_PTYPE_L4_UDP,
3951                 RTE_PTYPE_TUNNEL_IP,
3952                 RTE_PTYPE_INNER_L3_IPV6,
3953                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3954                 RTE_PTYPE_INNER_L4_TCP,
3955                 RTE_PTYPE_INNER_L4_UDP,
3956                 RTE_PTYPE_UNKNOWN
3957         };
3958
3959         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3960             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3961             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3962             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3963                 return ptypes;
3964
3965 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3966         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3967             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3968                 return ptypes;
3969 #endif
3970         return NULL;
3971 }
3972
3973 static int
3974 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3975                      struct rte_eth_dev_info *dev_info)
3976 {
3977         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3978         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3979
3980         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3981         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3982         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3983         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3984         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3985         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3986         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3987         dev_info->max_vfs = pci_dev->max_vfs;
3988         if (hw->mac.type == ixgbe_mac_82598EB)
3989                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3990         else
3991                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3992         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3993         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3994                                      dev_info->rx_queue_offload_capa);
3995         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3996         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3997         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3998         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3999         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
4000
4001         dev_info->default_rxconf = (struct rte_eth_rxconf) {
4002                 .rx_thresh = {
4003                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4004                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4005                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4006                 },
4007                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4008                 .rx_drop_en = 0,
4009                 .offloads = 0,
4010         };
4011
4012         dev_info->default_txconf = (struct rte_eth_txconf) {
4013                 .tx_thresh = {
4014                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4015                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4016                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4017                 },
4018                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4019                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4020                 .offloads = 0,
4021         };
4022
4023         dev_info->rx_desc_lim = rx_desc_lim;
4024         dev_info->tx_desc_lim = tx_desc_lim;
4025
4026         return 0;
4027 }
4028
4029 static int
4030 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4031                    bool *link_up, int wait_to_complete)
4032 {
4033         struct ixgbe_adapter *adapter = container_of(hw,
4034                                                      struct ixgbe_adapter, hw);
4035         struct ixgbe_mbx_info *mbx = &hw->mbx;
4036         struct ixgbe_mac_info *mac = &hw->mac;
4037         uint32_t links_reg, in_msg;
4038         int ret_val = 0;
4039
4040         /* If we were hit with a reset drop the link */
4041         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4042                 mac->get_link_status = true;
4043
4044         if (!mac->get_link_status)
4045                 goto out;
4046
4047         /* if link status is down no point in checking to see if pf is up */
4048         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4049         if (!(links_reg & IXGBE_LINKS_UP))
4050                 goto out;
4051
4052         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4053          * before the link status is correct
4054          */
4055         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4056                 int i;
4057
4058                 for (i = 0; i < 5; i++) {
4059                         rte_delay_us(100);
4060                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4061
4062                         if (!(links_reg & IXGBE_LINKS_UP))
4063                                 goto out;
4064                 }
4065         }
4066
4067         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4068         case IXGBE_LINKS_SPEED_10G_82599:
4069                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4070                 if (hw->mac.type >= ixgbe_mac_X550) {
4071                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4072                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4073                 }
4074                 break;
4075         case IXGBE_LINKS_SPEED_1G_82599:
4076                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4077                 break;
4078         case IXGBE_LINKS_SPEED_100_82599:
4079                 *speed = IXGBE_LINK_SPEED_100_FULL;
4080                 if (hw->mac.type == ixgbe_mac_X550) {
4081                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4082                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4083                 }
4084                 break;
4085         case IXGBE_LINKS_SPEED_10_X550EM_A:
4086                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4087                 /* Since Reserved in older MAC's */
4088                 if (hw->mac.type >= ixgbe_mac_X550)
4089                         *speed = IXGBE_LINK_SPEED_10_FULL;
4090                 break;
4091         default:
4092                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4093         }
4094
4095         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4096                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4097                         mac->get_link_status = true;
4098                 else
4099                         mac->get_link_status = false;
4100
4101                 goto out;
4102         }
4103
4104         /* if the read failed it could just be a mailbox collision, best wait
4105          * until we are called again and don't report an error
4106          */
4107         if (mbx->ops.read(hw, &in_msg, 1, 0))
4108                 goto out;
4109
4110         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4111                 /* msg is not CTS and is NACK we must have lost CTS status */
4112                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4113                         mac->get_link_status = false;
4114                 goto out;
4115         }
4116
4117         /* the pf is talking, if we timed out in the past we reinit */
4118         if (!mbx->timeout) {
4119                 ret_val = -1;
4120                 goto out;
4121         }
4122
4123         /* if we passed all the tests above then the link is up and we no
4124          * longer need to check for link
4125          */
4126         mac->get_link_status = false;
4127
4128 out:
4129         *link_up = !mac->get_link_status;
4130         return ret_val;
4131 }
4132
4133 /*
4134  * If @timeout_ms was 0, it means that it will not return until link complete.
4135  * It returns 1 on complete, return 0 on timeout.
4136  */
4137 static int
4138 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4139 {
4140 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4141         struct ixgbe_adapter *ad = dev->data->dev_private;
4142         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4143
4144         while (rte_atomic32_read(&ad->link_thread_running)) {
4145                 msec_delay(1);
4146                 timeout--;
4147
4148                 if (timeout_ms) {
4149                         if (!timeout)
4150                                 return 0;
4151                 } else if (!timeout) {
4152                         /* It will not return until link complete */
4153                         timeout = WARNING_TIMEOUT;
4154                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4155                 }
4156         }
4157
4158         return 1;
4159 }
4160
4161 static void *
4162 ixgbe_dev_setup_link_thread_handler(void *param)
4163 {
4164         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4165         struct ixgbe_adapter *ad = dev->data->dev_private;
4166         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4167         struct ixgbe_interrupt *intr =
4168                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4169         u32 speed;
4170         bool autoneg = false;
4171
4172         pthread_detach(pthread_self());
4173         speed = hw->phy.autoneg_advertised;
4174         if (!speed)
4175                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4176
4177         ixgbe_setup_link(hw, speed, true);
4178
4179         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4180         rte_atomic32_clear(&ad->link_thread_running);
4181         return NULL;
4182 }
4183
4184 /*
4185  * In freebsd environment, nic_uio drivers do not support interrupts,
4186  * rte_intr_callback_register() will fail to register interrupts.
4187  * We can not make link status to change from down to up by interrupt
4188  * callback. So we need to wait for the controller to acquire link
4189  * when ports start.
4190  * It returns 0 on link up.
4191  */
4192 static int
4193 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4194 {
4195 #ifdef RTE_EXEC_ENV_FREEBSD
4196         int err, i;
4197         bool link_up = false;
4198         uint32_t speed = 0;
4199         const int nb_iter = 25;
4200
4201         for (i = 0; i < nb_iter; i++) {
4202                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4203                 if (err)
4204                         return err;
4205                 if (link_up)
4206                         return 0;
4207                 msec_delay(200);
4208         }
4209
4210         return 0;
4211 #else
4212         RTE_SET_USED(hw);
4213         return 0;
4214 #endif
4215 }
4216
4217 /* return 0 means link status changed, -1 means not changed */
4218 int
4219 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4220                             int wait_to_complete, int vf)
4221 {
4222         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4223         struct ixgbe_adapter *ad = dev->data->dev_private;
4224         struct rte_eth_link link;
4225         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4226         struct ixgbe_interrupt *intr =
4227                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4228         bool link_up;
4229         int diag;
4230         int wait = 1;
4231         u32 esdp_reg;
4232
4233         memset(&link, 0, sizeof(link));
4234         link.link_status = ETH_LINK_DOWN;
4235         link.link_speed = ETH_SPEED_NUM_NONE;
4236         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4237         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4238                         ETH_LINK_SPEED_FIXED);
4239
4240         hw->mac.get_link_status = true;
4241
4242         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4243                 return rte_eth_linkstatus_set(dev, &link);
4244
4245         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4246         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4247                 wait = 0;
4248
4249 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4250 #ifdef RTE_EXEC_ENV_FREEBSD
4251         wait = 1;
4252 #endif
4253
4254         if (vf)
4255                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4256         else
4257                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4258
4259         if (diag != 0) {
4260                 link.link_speed = ETH_SPEED_NUM_100M;
4261                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4262                 return rte_eth_linkstatus_set(dev, &link);
4263         }
4264
4265         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4266                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4267                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4268                         link_up = 0;
4269         }
4270
4271         if (link_up == 0) {
4272                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4273                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4274                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4275                                 /* To avoid race condition between threads, set
4276                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4277                                  * when there is no link thread running.
4278                                  */
4279                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4280                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4281                                         "ixgbe-link-handler",
4282                                         NULL,
4283                                         ixgbe_dev_setup_link_thread_handler,
4284                                         dev) < 0) {
4285                                         PMD_DRV_LOG(ERR,
4286                                                 "Create link thread failed!");
4287                                         rte_atomic32_clear(&ad->link_thread_running);
4288                                 }
4289                         } else {
4290                                 PMD_DRV_LOG(ERR,
4291                                         "Other link thread is running now!");
4292                         }
4293                 }
4294                 return rte_eth_linkstatus_set(dev, &link);
4295         }
4296
4297         link.link_status = ETH_LINK_UP;
4298         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4299
4300         switch (link_speed) {
4301         default:
4302         case IXGBE_LINK_SPEED_UNKNOWN:
4303                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4304                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4305                         link.link_speed = ETH_SPEED_NUM_10M;
4306                 else
4307                         link.link_speed = ETH_SPEED_NUM_100M;
4308                 break;
4309
4310         case IXGBE_LINK_SPEED_10_FULL:
4311                 link.link_speed = ETH_SPEED_NUM_10M;
4312                 break;
4313
4314         case IXGBE_LINK_SPEED_100_FULL:
4315                 link.link_speed = ETH_SPEED_NUM_100M;
4316                 break;
4317
4318         case IXGBE_LINK_SPEED_1GB_FULL:
4319                 link.link_speed = ETH_SPEED_NUM_1G;
4320                 break;
4321
4322         case IXGBE_LINK_SPEED_2_5GB_FULL:
4323                 link.link_speed = ETH_SPEED_NUM_2_5G;
4324                 break;
4325
4326         case IXGBE_LINK_SPEED_5GB_FULL:
4327                 link.link_speed = ETH_SPEED_NUM_5G;
4328                 break;
4329
4330         case IXGBE_LINK_SPEED_10GB_FULL:
4331                 link.link_speed = ETH_SPEED_NUM_10G;
4332                 break;
4333         }
4334
4335         return rte_eth_linkstatus_set(dev, &link);
4336 }
4337
4338 static int
4339 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4340 {
4341         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4342 }
4343
4344 static int
4345 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4346 {
4347         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4348 }
4349
4350 static int
4351 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4352 {
4353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4354         uint32_t fctrl;
4355
4356         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4357         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4358         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4359
4360         return 0;
4361 }
4362
4363 static int
4364 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4365 {
4366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4367         uint32_t fctrl;
4368
4369         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4370         fctrl &= (~IXGBE_FCTRL_UPE);
4371         if (dev->data->all_multicast == 1)
4372                 fctrl |= IXGBE_FCTRL_MPE;
4373         else
4374                 fctrl &= (~IXGBE_FCTRL_MPE);
4375         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4376
4377         return 0;
4378 }
4379
4380 static int
4381 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4382 {
4383         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4384         uint32_t fctrl;
4385
4386         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4387         fctrl |= IXGBE_FCTRL_MPE;
4388         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4389
4390         return 0;
4391 }
4392
4393 static int
4394 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4395 {
4396         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4397         uint32_t fctrl;
4398
4399         if (dev->data->promiscuous == 1)
4400                 return 0; /* must remain in all_multicast mode */
4401
4402         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4403         fctrl &= (~IXGBE_FCTRL_MPE);
4404         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4405
4406         return 0;
4407 }
4408
4409 /**
4410  * It clears the interrupt causes and enables the interrupt.
4411  * It will be called once only during nic initialized.
4412  *
4413  * @param dev
4414  *  Pointer to struct rte_eth_dev.
4415  * @param on
4416  *  Enable or Disable.
4417  *
4418  * @return
4419  *  - On success, zero.
4420  *  - On failure, a negative value.
4421  */
4422 static int
4423 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4424 {
4425         struct ixgbe_interrupt *intr =
4426                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4427
4428         ixgbe_dev_link_status_print(dev);
4429         if (on)
4430                 intr->mask |= IXGBE_EICR_LSC;
4431         else
4432                 intr->mask &= ~IXGBE_EICR_LSC;
4433
4434         return 0;
4435 }
4436
4437 /**
4438  * It clears the interrupt causes and enables the interrupt.
4439  * It will be called once only during nic initialized.
4440  *
4441  * @param dev
4442  *  Pointer to struct rte_eth_dev.
4443  *
4444  * @return
4445  *  - On success, zero.
4446  *  - On failure, a negative value.
4447  */
4448 static int
4449 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4450 {
4451         struct ixgbe_interrupt *intr =
4452                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4453
4454         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4455
4456         return 0;
4457 }
4458
4459 /**
4460  * It clears the interrupt causes and enables the interrupt.
4461  * It will be called once only during nic initialized.
4462  *
4463  * @param dev
4464  *  Pointer to struct rte_eth_dev.
4465  *
4466  * @return
4467  *  - On success, zero.
4468  *  - On failure, a negative value.
4469  */
4470 static int
4471 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4472 {
4473         struct ixgbe_interrupt *intr =
4474                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4475
4476         intr->mask |= IXGBE_EICR_LINKSEC;
4477
4478         return 0;
4479 }
4480
4481 /*
4482  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4483  *
4484  * @param dev
4485  *  Pointer to struct rte_eth_dev.
4486  *
4487  * @return
4488  *  - On success, zero.
4489  *  - On failure, a negative value.
4490  */
4491 static int
4492 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4493 {
4494         uint32_t eicr;
4495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496         struct ixgbe_interrupt *intr =
4497                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4498
4499         /* clear all cause mask */
4500         ixgbe_disable_intr(hw);
4501
4502         /* read-on-clear nic registers here */
4503         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4504         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4505
4506         intr->flags = 0;
4507
4508         /* set flag for async link update */
4509         if (eicr & IXGBE_EICR_LSC)
4510                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4511
4512         if (eicr & IXGBE_EICR_MAILBOX)
4513                 intr->flags |= IXGBE_FLAG_MAILBOX;
4514
4515         if (eicr & IXGBE_EICR_LINKSEC)
4516                 intr->flags |= IXGBE_FLAG_MACSEC;
4517
4518         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4519             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4520             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4521                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4522
4523         return 0;
4524 }
4525
4526 /**
4527  * It gets and then prints the link status.
4528  *
4529  * @param dev
4530  *  Pointer to struct rte_eth_dev.
4531  *
4532  * @return
4533  *  - On success, zero.
4534  *  - On failure, a negative value.
4535  */
4536 static void
4537 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4538 {
4539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4540         struct rte_eth_link link;
4541
4542         rte_eth_linkstatus_get(dev, &link);
4543
4544         if (link.link_status) {
4545                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4546                                         (int)(dev->data->port_id),
4547                                         (unsigned)link.link_speed,
4548                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4549                                         "full-duplex" : "half-duplex");
4550         } else {
4551                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4552                                 (int)(dev->data->port_id));
4553         }
4554         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4555                                 pci_dev->addr.domain,
4556                                 pci_dev->addr.bus,
4557                                 pci_dev->addr.devid,
4558                                 pci_dev->addr.function);
4559 }
4560
4561 /*
4562  * It executes link_update after knowing an interrupt occurred.
4563  *
4564  * @param dev
4565  *  Pointer to struct rte_eth_dev.
4566  *
4567  * @return
4568  *  - On success, zero.
4569  *  - On failure, a negative value.
4570  */
4571 static int
4572 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4573 {
4574         struct ixgbe_interrupt *intr =
4575                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4576         int64_t timeout;
4577         struct ixgbe_hw *hw =
4578                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4579
4580         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4581
4582         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4583                 ixgbe_pf_mbx_process(dev);
4584                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4585         }
4586
4587         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4588                 ixgbe_handle_lasi(hw);
4589                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4590         }
4591
4592         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4593                 struct rte_eth_link link;
4594
4595                 /* get the link status before link update, for predicting later */
4596                 rte_eth_linkstatus_get(dev, &link);
4597
4598                 ixgbe_dev_link_update(dev, 0);
4599
4600                 /* likely to up */
4601                 if (!link.link_status)
4602                         /* handle it 1 sec later, wait it being stable */
4603                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4604                 /* likely to down */
4605                 else
4606                         /* handle it 4 sec later, wait it being stable */
4607                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4608
4609                 ixgbe_dev_link_status_print(dev);
4610                 if (rte_eal_alarm_set(timeout * 1000,
4611                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4612                         PMD_DRV_LOG(ERR, "Error setting alarm");
4613                 else {
4614                         /* remember original mask */
4615                         intr->mask_original = intr->mask;
4616                         /* only disable lsc interrupt */
4617                         intr->mask &= ~IXGBE_EIMS_LSC;
4618                 }
4619         }
4620
4621         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4622         ixgbe_enable_intr(dev);
4623
4624         return 0;
4625 }
4626
4627 /**
4628  * Interrupt handler which shall be registered for alarm callback for delayed
4629  * handling specific interrupt to wait for the stable nic state. As the
4630  * NIC interrupt state is not stable for ixgbe after link is just down,
4631  * it needs to wait 4 seconds to get the stable status.
4632  *
4633  * @param handle
4634  *  Pointer to interrupt handle.
4635  * @param param
4636  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4637  *
4638  * @return
4639  *  void
4640  */
4641 static void
4642 ixgbe_dev_interrupt_delayed_handler(void *param)
4643 {
4644         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4645         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4646         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4647         struct ixgbe_interrupt *intr =
4648                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4649         struct ixgbe_hw *hw =
4650                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4651         uint32_t eicr;
4652
4653         ixgbe_disable_intr(hw);
4654
4655         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4656         if (eicr & IXGBE_EICR_MAILBOX)
4657                 ixgbe_pf_mbx_process(dev);
4658
4659         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4660                 ixgbe_handle_lasi(hw);
4661                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4662         }
4663
4664         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4665                 ixgbe_dev_link_update(dev, 0);
4666                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4667                 ixgbe_dev_link_status_print(dev);
4668                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4669                                               NULL);
4670         }
4671
4672         if (intr->flags & IXGBE_FLAG_MACSEC) {
4673                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4674                                               NULL);
4675                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4676         }
4677
4678         /* restore original mask */
4679         intr->mask = intr->mask_original;
4680         intr->mask_original = 0;
4681
4682         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4683         ixgbe_enable_intr(dev);
4684         rte_intr_ack(intr_handle);
4685 }
4686
4687 /**
4688  * Interrupt handler triggered by NIC  for handling
4689  * specific interrupt.
4690  *
4691  * @param handle
4692  *  Pointer to interrupt handle.
4693  * @param param
4694  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4695  *
4696  * @return
4697  *  void
4698  */
4699 static void
4700 ixgbe_dev_interrupt_handler(void *param)
4701 {
4702         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4703
4704         ixgbe_dev_interrupt_get_status(dev);
4705         ixgbe_dev_interrupt_action(dev);
4706 }
4707
4708 static int
4709 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4710 {
4711         struct ixgbe_hw *hw;
4712
4713         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4714         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4715 }
4716
4717 static int
4718 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4719 {
4720         struct ixgbe_hw *hw;
4721
4722         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4723         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4724 }
4725
4726 static int
4727 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4728 {
4729         struct ixgbe_hw *hw;
4730         uint32_t mflcn_reg;
4731         uint32_t fccfg_reg;
4732         int rx_pause;
4733         int tx_pause;
4734
4735         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4736
4737         fc_conf->pause_time = hw->fc.pause_time;
4738         fc_conf->high_water = hw->fc.high_water[0];
4739         fc_conf->low_water = hw->fc.low_water[0];
4740         fc_conf->send_xon = hw->fc.send_xon;
4741         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4742
4743         /*
4744          * Return rx_pause status according to actual setting of
4745          * MFLCN register.
4746          */
4747         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4748         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4749                 rx_pause = 1;
4750         else
4751                 rx_pause = 0;
4752
4753         /*
4754          * Return tx_pause status according to actual setting of
4755          * FCCFG register.
4756          */
4757         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4758         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4759                 tx_pause = 1;
4760         else
4761                 tx_pause = 0;
4762
4763         if (rx_pause && tx_pause)
4764                 fc_conf->mode = RTE_FC_FULL;
4765         else if (rx_pause)
4766                 fc_conf->mode = RTE_FC_RX_PAUSE;
4767         else if (tx_pause)
4768                 fc_conf->mode = RTE_FC_TX_PAUSE;
4769         else
4770                 fc_conf->mode = RTE_FC_NONE;
4771
4772         return 0;
4773 }
4774
4775 static int
4776 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4777 {
4778         struct ixgbe_hw *hw;
4779         struct ixgbe_adapter *adapter = dev->data->dev_private;
4780         int err;
4781         uint32_t rx_buf_size;
4782         uint32_t max_high_water;
4783         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4784                 ixgbe_fc_none,
4785                 ixgbe_fc_rx_pause,
4786                 ixgbe_fc_tx_pause,
4787                 ixgbe_fc_full
4788         };
4789
4790         PMD_INIT_FUNC_TRACE();
4791
4792         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4793         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4794         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4795
4796         /*
4797          * At least reserve one Ethernet frame for watermark
4798          * high_water/low_water in kilo bytes for ixgbe
4799          */
4800         max_high_water = (rx_buf_size -
4801                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4802         if ((fc_conf->high_water > max_high_water) ||
4803                 (fc_conf->high_water < fc_conf->low_water)) {
4804                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4805                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4806                 return -EINVAL;
4807         }
4808
4809         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4810         hw->fc.pause_time     = fc_conf->pause_time;
4811         hw->fc.high_water[0]  = fc_conf->high_water;
4812         hw->fc.low_water[0]   = fc_conf->low_water;
4813         hw->fc.send_xon       = fc_conf->send_xon;
4814         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4815         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4816
4817         err = ixgbe_flow_ctrl_enable(dev, hw);
4818         if (err < 0) {
4819                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4820                 return -EIO;
4821         }
4822         return err;
4823 }
4824
4825 /**
4826  *  ixgbe_pfc_enable_generic - Enable flow control
4827  *  @hw: pointer to hardware structure
4828  *  @tc_num: traffic class number
4829  *  Enable flow control according to the current settings.
4830  */
4831 static int
4832 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4833 {
4834         int ret_val = 0;
4835         uint32_t mflcn_reg, fccfg_reg;
4836         uint32_t reg;
4837         uint32_t fcrtl, fcrth;
4838         uint8_t i;
4839         uint8_t nb_rx_en;
4840
4841         /* Validate the water mark configuration */
4842         if (!hw->fc.pause_time) {
4843                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4844                 goto out;
4845         }
4846
4847         /* Low water mark of zero causes XOFF floods */
4848         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4849                  /* High/Low water can not be 0 */
4850                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4851                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4852                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4853                         goto out;
4854                 }
4855
4856                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4857                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4858                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4859                         goto out;
4860                 }
4861         }
4862         /* Negotiate the fc mode to use */
4863         ixgbe_fc_autoneg(hw);
4864
4865         /* Disable any previous flow control settings */
4866         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4867         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4868
4869         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4870         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4871
4872         switch (hw->fc.current_mode) {
4873         case ixgbe_fc_none:
4874                 /*
4875                  * If the count of enabled RX Priority Flow control >1,
4876                  * and the TX pause can not be disabled
4877                  */
4878                 nb_rx_en = 0;
4879                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4880                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4881                         if (reg & IXGBE_FCRTH_FCEN)
4882                                 nb_rx_en++;
4883                 }
4884                 if (nb_rx_en > 1)
4885                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4886                 break;
4887         case ixgbe_fc_rx_pause:
4888                 /*
4889                  * Rx Flow control is enabled and Tx Flow control is
4890                  * disabled by software override. Since there really
4891                  * isn't a way to advertise that we are capable of RX
4892                  * Pause ONLY, we will advertise that we support both
4893                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4894                  * disable the adapter's ability to send PAUSE frames.
4895                  */
4896                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4897                 /*
4898                  * If the count of enabled RX Priority Flow control >1,
4899                  * and the TX pause can not be disabled
4900                  */
4901                 nb_rx_en = 0;
4902                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4903                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4904                         if (reg & IXGBE_FCRTH_FCEN)
4905                                 nb_rx_en++;
4906                 }
4907                 if (nb_rx_en > 1)
4908                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4909                 break;
4910         case ixgbe_fc_tx_pause:
4911                 /*
4912                  * Tx Flow control is enabled, and Rx Flow control is
4913                  * disabled by software override.
4914                  */
4915                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4916                 break;
4917         case ixgbe_fc_full:
4918                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4919                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4920                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4921                 break;
4922         default:
4923                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4924                 ret_val = IXGBE_ERR_CONFIG;
4925                 goto out;
4926         }
4927
4928         /* Set 802.3x based flow control settings. */
4929         mflcn_reg |= IXGBE_MFLCN_DPF;
4930         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4931         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4932
4933         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4934         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4935                 hw->fc.high_water[tc_num]) {
4936                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4937                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4938                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4939         } else {
4940                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4941                 /*
4942                  * In order to prevent Tx hangs when the internal Tx
4943                  * switch is enabled we must set the high water mark
4944                  * to the maximum FCRTH value.  This allows the Tx
4945                  * switch to function even under heavy Rx workloads.
4946                  */
4947                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4948         }
4949         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4950
4951         /* Configure pause time (2 TCs per register) */
4952         reg = hw->fc.pause_time * 0x00010001;
4953         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4954                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4955
4956         /* Configure flow control refresh threshold value */
4957         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4958
4959 out:
4960         return ret_val;
4961 }
4962
4963 static int
4964 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4965 {
4966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4968
4969         if (hw->mac.type != ixgbe_mac_82598EB) {
4970                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4971         }
4972         return ret_val;
4973 }
4974
4975 static int
4976 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4977 {
4978         int err;
4979         uint32_t rx_buf_size;
4980         uint32_t max_high_water;
4981         uint8_t tc_num;
4982         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4983         struct ixgbe_hw *hw =
4984                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4985         struct ixgbe_dcb_config *dcb_config =
4986                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4987
4988         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4989                 ixgbe_fc_none,
4990                 ixgbe_fc_rx_pause,
4991                 ixgbe_fc_tx_pause,
4992                 ixgbe_fc_full
4993         };
4994
4995         PMD_INIT_FUNC_TRACE();
4996
4997         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4998         tc_num = map[pfc_conf->priority];
4999         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
5000         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
5001         /*
5002          * At least reserve one Ethernet frame for watermark
5003          * high_water/low_water in kilo bytes for ixgbe
5004          */
5005         max_high_water = (rx_buf_size -
5006                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5007         if ((pfc_conf->fc.high_water > max_high_water) ||
5008             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5009                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5010                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5011                 return -EINVAL;
5012         }
5013
5014         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5015         hw->fc.pause_time = pfc_conf->fc.pause_time;
5016         hw->fc.send_xon = pfc_conf->fc.send_xon;
5017         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5018         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5019
5020         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5021
5022         /* Not negotiated is not an error case */
5023         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5024                 return 0;
5025
5026         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5027         return -EIO;
5028 }
5029
5030 static int
5031 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5032                           struct rte_eth_rss_reta_entry64 *reta_conf,
5033                           uint16_t reta_size)
5034 {
5035         uint16_t i, sp_reta_size;
5036         uint8_t j, mask;
5037         uint32_t reta, r;
5038         uint16_t idx, shift;
5039         struct ixgbe_adapter *adapter = dev->data->dev_private;
5040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041         uint32_t reta_reg;
5042
5043         PMD_INIT_FUNC_TRACE();
5044
5045         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5046                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5047                         "NIC.");
5048                 return -ENOTSUP;
5049         }
5050
5051         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5052         if (reta_size != sp_reta_size) {
5053                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5054                         "(%d) doesn't match the number hardware can supported "
5055                         "(%d)", reta_size, sp_reta_size);
5056                 return -EINVAL;
5057         }
5058
5059         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5060                 idx = i / RTE_RETA_GROUP_SIZE;
5061                 shift = i % RTE_RETA_GROUP_SIZE;
5062                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5063                                                 IXGBE_4_BIT_MASK);
5064                 if (!mask)
5065                         continue;
5066                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5067                 if (mask == IXGBE_4_BIT_MASK)
5068                         r = 0;
5069                 else
5070                         r = IXGBE_READ_REG(hw, reta_reg);
5071                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5072                         if (mask & (0x1 << j))
5073                                 reta |= reta_conf[idx].reta[shift + j] <<
5074                                                         (CHAR_BIT * j);
5075                         else
5076                                 reta |= r & (IXGBE_8_BIT_MASK <<
5077                                                 (CHAR_BIT * j));
5078                 }
5079                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5080         }
5081         adapter->rss_reta_updated = 1;
5082
5083         return 0;
5084 }
5085
5086 static int
5087 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5088                          struct rte_eth_rss_reta_entry64 *reta_conf,
5089                          uint16_t reta_size)
5090 {
5091         uint16_t i, sp_reta_size;
5092         uint8_t j, mask;
5093         uint32_t reta;
5094         uint16_t idx, shift;
5095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5096         uint32_t reta_reg;
5097
5098         PMD_INIT_FUNC_TRACE();
5099         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5100         if (reta_size != sp_reta_size) {
5101                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5102                         "(%d) doesn't match the number hardware can supported "
5103                         "(%d)", reta_size, sp_reta_size);
5104                 return -EINVAL;
5105         }
5106
5107         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5108                 idx = i / RTE_RETA_GROUP_SIZE;
5109                 shift = i % RTE_RETA_GROUP_SIZE;
5110                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5111                                                 IXGBE_4_BIT_MASK);
5112                 if (!mask)
5113                         continue;
5114
5115                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5116                 reta = IXGBE_READ_REG(hw, reta_reg);
5117                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5118                         if (mask & (0x1 << j))
5119                                 reta_conf[idx].reta[shift + j] =
5120                                         ((reta >> (CHAR_BIT * j)) &
5121                                                 IXGBE_8_BIT_MASK);
5122                 }
5123         }
5124
5125         return 0;
5126 }
5127
5128 static int
5129 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5130                                 uint32_t index, uint32_t pool)
5131 {
5132         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5133         uint32_t enable_addr = 1;
5134
5135         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5136                              pool, enable_addr);
5137 }
5138
5139 static void
5140 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5141 {
5142         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5143
5144         ixgbe_clear_rar(hw, index);
5145 }
5146
5147 static int
5148 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5149 {
5150         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5151
5152         ixgbe_remove_rar(dev, 0);
5153         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5154
5155         return 0;
5156 }
5157
5158 static bool
5159 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5160 {
5161         if (strcmp(dev->device->driver->name, drv->driver.name))
5162                 return false;
5163
5164         return true;
5165 }
5166
5167 bool
5168 is_ixgbe_supported(struct rte_eth_dev *dev)
5169 {
5170         return is_device_supported(dev, &rte_ixgbe_pmd);
5171 }
5172
5173 static int
5174 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5175 {
5176         uint32_t hlreg0;
5177         uint32_t maxfrs;
5178         struct ixgbe_hw *hw;
5179         struct rte_eth_dev_info dev_info;
5180         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5181         struct rte_eth_dev_data *dev_data = dev->data;
5182         int ret;
5183
5184         ret = ixgbe_dev_info_get(dev, &dev_info);
5185         if (ret != 0)
5186                 return ret;
5187
5188         /* check that mtu is within the allowed range */
5189         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5190                 return -EINVAL;
5191
5192         /* If device is started, refuse mtu that requires the support of
5193          * scattered packets when this feature has not been enabled before.
5194          */
5195         if (dev_data->dev_started && !dev_data->scattered_rx &&
5196             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5197              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5198                 PMD_INIT_LOG(ERR, "Stop port first.");
5199                 return -EINVAL;
5200         }
5201
5202         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5204
5205         /* switch to jumbo mode if needed */
5206         if (frame_size > RTE_ETHER_MAX_LEN) {
5207                 dev->data->dev_conf.rxmode.offloads |=
5208                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5209                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5210         } else {
5211                 dev->data->dev_conf.rxmode.offloads &=
5212                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5213                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5214         }
5215         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5216
5217         /* update max frame size */
5218         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5219
5220         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5221         maxfrs &= 0x0000FFFF;
5222         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5223         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5224
5225         return 0;
5226 }
5227
5228 /*
5229  * Virtual Function operations
5230  */
5231 static void
5232 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5233 {
5234         struct ixgbe_interrupt *intr =
5235                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5236         struct ixgbe_hw *hw =
5237                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238
5239         PMD_INIT_FUNC_TRACE();
5240
5241         /* Clear interrupt mask to stop from interrupts being generated */
5242         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5243
5244         IXGBE_WRITE_FLUSH(hw);
5245
5246         /* Clear mask value. */
5247         intr->mask = 0;
5248 }
5249
5250 static void
5251 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5252 {
5253         struct ixgbe_interrupt *intr =
5254                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5255         struct ixgbe_hw *hw =
5256                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5257
5258         PMD_INIT_FUNC_TRACE();
5259
5260         /* VF enable interrupt autoclean */
5261         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5262         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5263         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5264
5265         IXGBE_WRITE_FLUSH(hw);
5266
5267         /* Save IXGBE_VTEIMS value to mask. */
5268         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5269 }
5270
5271 static int
5272 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5273 {
5274         struct rte_eth_conf *conf = &dev->data->dev_conf;
5275         struct ixgbe_adapter *adapter = dev->data->dev_private;
5276
5277         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5278                      dev->data->port_id);
5279
5280         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5281                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5282
5283         /*
5284          * VF has no ability to enable/disable HW CRC
5285          * Keep the persistent behavior the same as Host PF
5286          */
5287 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5288         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5289                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5290                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5291         }
5292 #else
5293         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5294                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5295                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5296         }
5297 #endif
5298
5299         /*
5300          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5301          * allocation or vector Rx preconditions we will reset it.
5302          */
5303         adapter->rx_bulk_alloc_allowed = true;
5304         adapter->rx_vec_allowed = true;
5305
5306         return 0;
5307 }
5308
5309 static int
5310 ixgbevf_dev_start(struct rte_eth_dev *dev)
5311 {
5312         struct ixgbe_hw *hw =
5313                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5314         uint32_t intr_vector = 0;
5315         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5316         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5317
5318         int err, mask = 0;
5319
5320         PMD_INIT_FUNC_TRACE();
5321
5322         /* Stop the link setup handler before resetting the HW. */
5323         ixgbe_dev_wait_setup_link_complete(dev, 0);
5324
5325         err = hw->mac.ops.reset_hw(hw);
5326         if (err) {
5327                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5328                 return err;
5329         }
5330         hw->mac.get_link_status = true;
5331
5332         /* negotiate mailbox API version to use with the PF. */
5333         ixgbevf_negotiate_api(hw);
5334
5335         ixgbevf_dev_tx_init(dev);
5336
5337         /* This can fail when allocating mbufs for descriptor rings */
5338         err = ixgbevf_dev_rx_init(dev);
5339         if (err) {
5340                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5341                 ixgbe_dev_clear_queues(dev);
5342                 return err;
5343         }
5344
5345         /* Set vfta */
5346         ixgbevf_set_vfta_all(dev, 1);
5347
5348         /* Set HW strip */
5349         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5350                 ETH_VLAN_EXTEND_MASK;
5351         err = ixgbevf_vlan_offload_config(dev, mask);
5352         if (err) {
5353                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5354                 ixgbe_dev_clear_queues(dev);
5355                 return err;
5356         }
5357
5358         ixgbevf_dev_rxtx_start(dev);
5359
5360         /* check and configure queue intr-vector mapping */
5361         if (rte_intr_cap_multiple(intr_handle) &&
5362             dev->data->dev_conf.intr_conf.rxq) {
5363                 /* According to datasheet, only vector 0/1/2 can be used,
5364                  * now only one vector is used for Rx queue
5365                  */
5366                 intr_vector = 1;
5367                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5368                         return -1;
5369         }
5370
5371         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5372                 intr_handle->intr_vec =
5373                         rte_zmalloc("intr_vec",
5374                                     dev->data->nb_rx_queues * sizeof(int), 0);
5375                 if (intr_handle->intr_vec == NULL) {
5376                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5377                                      " intr_vec", dev->data->nb_rx_queues);
5378                         return -ENOMEM;
5379                 }
5380         }
5381         ixgbevf_configure_msix(dev);
5382
5383         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5384          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5385          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5386          * is not cleared, it will fail when following rte_intr_enable( ) tries
5387          * to map Rx queue interrupt to other VFIO vectors.
5388          * So clear uio/vfio intr/evevnfd first to avoid failure.
5389          */
5390         rte_intr_disable(intr_handle);
5391
5392         rte_intr_enable(intr_handle);
5393
5394         /* Re-enable interrupt for VF */
5395         ixgbevf_intr_enable(dev);
5396
5397         /*
5398          * Update link status right before return, because it may
5399          * start link configuration process in a separate thread.
5400          */
5401         ixgbevf_dev_link_update(dev, 0);
5402
5403         hw->adapter_stopped = false;
5404
5405         return 0;
5406 }
5407
5408 static void
5409 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5410 {
5411         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5412         struct ixgbe_adapter *adapter = dev->data->dev_private;
5413         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5414         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5415
5416         if (hw->adapter_stopped)
5417                 return;
5418
5419         PMD_INIT_FUNC_TRACE();
5420
5421         ixgbe_dev_wait_setup_link_complete(dev, 0);
5422
5423         ixgbevf_intr_disable(dev);
5424
5425         hw->adapter_stopped = 1;
5426         ixgbe_stop_adapter(hw);
5427
5428         /*
5429           * Clear what we set, but we still keep shadow_vfta to
5430           * restore after device starts
5431           */
5432         ixgbevf_set_vfta_all(dev, 0);
5433
5434         /* Clear stored conf */
5435         dev->data->scattered_rx = 0;
5436
5437         ixgbe_dev_clear_queues(dev);
5438
5439         /* Clean datapath event and queue/vec mapping */
5440         rte_intr_efd_disable(intr_handle);
5441         if (intr_handle->intr_vec != NULL) {
5442                 rte_free(intr_handle->intr_vec);
5443                 intr_handle->intr_vec = NULL;
5444         }
5445
5446         adapter->rss_reta_updated = 0;
5447 }
5448
5449 static void
5450 ixgbevf_dev_close(struct rte_eth_dev *dev)
5451 {
5452         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5453         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5454         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5455
5456         PMD_INIT_FUNC_TRACE();
5457
5458         ixgbe_reset_hw(hw);
5459
5460         ixgbevf_dev_stop(dev);
5461
5462         ixgbe_dev_free_queues(dev);
5463
5464         /**
5465          * Remove the VF MAC address ro ensure
5466          * that the VF traffic goes to the PF
5467          * after stop, close and detach of the VF
5468          **/
5469         ixgbevf_remove_mac_addr(dev, 0);
5470
5471         dev->dev_ops = NULL;
5472         dev->rx_pkt_burst = NULL;
5473         dev->tx_pkt_burst = NULL;
5474
5475         rte_intr_disable(intr_handle);
5476         rte_intr_callback_unregister(intr_handle,
5477                                      ixgbevf_dev_interrupt_handler, dev);
5478 }
5479
5480 /*
5481  * Reset VF device
5482  */
5483 static int
5484 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5485 {
5486         int ret;
5487
5488         ret = eth_ixgbevf_dev_uninit(dev);
5489         if (ret)
5490                 return ret;
5491
5492         ret = eth_ixgbevf_dev_init(dev);
5493
5494         return ret;
5495 }
5496
5497 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5498 {
5499         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5500         struct ixgbe_vfta *shadow_vfta =
5501                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5502         int i = 0, j = 0, vfta = 0, mask = 1;
5503
5504         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5505                 vfta = shadow_vfta->vfta[i];
5506                 if (vfta) {
5507                         mask = 1;
5508                         for (j = 0; j < 32; j++) {
5509                                 if (vfta & mask)
5510                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5511                                                        on, false);
5512                                 mask <<= 1;
5513                         }
5514                 }
5515         }
5516
5517 }
5518
5519 static int
5520 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5521 {
5522         struct ixgbe_hw *hw =
5523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524         struct ixgbe_vfta *shadow_vfta =
5525                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5526         uint32_t vid_idx = 0;
5527         uint32_t vid_bit = 0;
5528         int ret = 0;
5529
5530         PMD_INIT_FUNC_TRACE();
5531
5532         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5533         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5534         if (ret) {
5535                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5536                 return ret;
5537         }
5538         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5539         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5540
5541         /* Save what we set and retore it after device reset */
5542         if (on)
5543                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5544         else
5545                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5546
5547         return 0;
5548 }
5549
5550 static void
5551 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5552 {
5553         struct ixgbe_hw *hw =
5554                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5555         uint32_t ctrl;
5556
5557         PMD_INIT_FUNC_TRACE();
5558
5559         if (queue >= hw->mac.max_rx_queues)
5560                 return;
5561
5562         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5563         if (on)
5564                 ctrl |= IXGBE_RXDCTL_VME;
5565         else
5566                 ctrl &= ~IXGBE_RXDCTL_VME;
5567         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5568
5569         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5570 }
5571
5572 static int
5573 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5574 {
5575         struct ixgbe_rx_queue *rxq;
5576         uint16_t i;
5577         int on = 0;
5578
5579         /* VF function only support hw strip feature, others are not support */
5580         if (mask & ETH_VLAN_STRIP_MASK) {
5581                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5582                         rxq = dev->data->rx_queues[i];
5583                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5584                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5585                 }
5586         }
5587
5588         return 0;
5589 }
5590
5591 static int
5592 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5593 {
5594         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5595
5596         ixgbevf_vlan_offload_config(dev, mask);
5597
5598         return 0;
5599 }
5600
5601 int
5602 ixgbe_vt_check(struct ixgbe_hw *hw)
5603 {
5604         uint32_t reg_val;
5605
5606         /* if Virtualization Technology is enabled */
5607         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5608         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5609                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5610                 return -1;
5611         }
5612
5613         return 0;
5614 }
5615
5616 static uint32_t
5617 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5618 {
5619         uint32_t vector = 0;
5620
5621         switch (hw->mac.mc_filter_type) {
5622         case 0:   /* use bits [47:36] of the address */
5623                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5624                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5625                 break;
5626         case 1:   /* use bits [46:35] of the address */
5627                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5628                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5629                 break;
5630         case 2:   /* use bits [45:34] of the address */
5631                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5632                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5633                 break;
5634         case 3:   /* use bits [43:32] of the address */
5635                 vector = ((uc_addr->addr_bytes[4]) |
5636                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5637                 break;
5638         default:  /* Invalid mc_filter_type */
5639                 break;
5640         }
5641
5642         /* vector can only be 12-bits or boundary will be exceeded */
5643         vector &= 0xFFF;
5644         return vector;
5645 }
5646
5647 static int
5648 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5649                         struct rte_ether_addr *mac_addr, uint8_t on)
5650 {
5651         uint32_t vector;
5652         uint32_t uta_idx;
5653         uint32_t reg_val;
5654         uint32_t uta_shift;
5655         uint32_t rc;
5656         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5657         const uint32_t ixgbe_uta_bit_shift = 5;
5658         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5659         const uint32_t bit1 = 0x1;
5660
5661         struct ixgbe_hw *hw =
5662                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5663         struct ixgbe_uta_info *uta_info =
5664                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5665
5666         /* The UTA table only exists on 82599 hardware and newer */
5667         if (hw->mac.type < ixgbe_mac_82599EB)
5668                 return -ENOTSUP;
5669
5670         vector = ixgbe_uta_vector(hw, mac_addr);
5671         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5672         uta_shift = vector & ixgbe_uta_bit_mask;
5673
5674         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5675         if (rc == on)
5676                 return 0;
5677
5678         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5679         if (on) {
5680                 uta_info->uta_in_use++;
5681                 reg_val |= (bit1 << uta_shift);
5682                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5683         } else {
5684                 uta_info->uta_in_use--;
5685                 reg_val &= ~(bit1 << uta_shift);
5686                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5687         }
5688
5689         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5690
5691         if (uta_info->uta_in_use > 0)
5692                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5693                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5694         else
5695                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5696
5697         return 0;
5698 }
5699
5700 static int
5701 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5702 {
5703         int i;
5704         struct ixgbe_hw *hw =
5705                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5706         struct ixgbe_uta_info *uta_info =
5707                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5708
5709         /* The UTA table only exists on 82599 hardware and newer */
5710         if (hw->mac.type < ixgbe_mac_82599EB)
5711                 return -ENOTSUP;
5712
5713         if (on) {
5714                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5715                         uta_info->uta_shadow[i] = ~0;
5716                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5717                 }
5718         } else {
5719                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5720                         uta_info->uta_shadow[i] = 0;
5721                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5722                 }
5723         }
5724         return 0;
5725
5726 }
5727
5728 uint32_t
5729 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5730 {
5731         uint32_t new_val = orig_val;
5732
5733         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5734                 new_val |= IXGBE_VMOLR_AUPE;
5735         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5736                 new_val |= IXGBE_VMOLR_ROMPE;
5737         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5738                 new_val |= IXGBE_VMOLR_ROPE;
5739         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5740                 new_val |= IXGBE_VMOLR_BAM;
5741         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5742                 new_val |= IXGBE_VMOLR_MPE;
5743
5744         return new_val;
5745 }
5746
5747 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5748 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5749 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5750 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5751 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5752         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5753         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5754
5755 static int
5756 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5757                       struct rte_eth_mirror_conf *mirror_conf,
5758                       uint8_t rule_id, uint8_t on)
5759 {
5760         uint32_t mr_ctl, vlvf;
5761         uint32_t mp_lsb = 0;
5762         uint32_t mv_msb = 0;
5763         uint32_t mv_lsb = 0;
5764         uint32_t mp_msb = 0;
5765         uint8_t i = 0;
5766         int reg_index = 0;
5767         uint64_t vlan_mask = 0;
5768
5769         const uint8_t pool_mask_offset = 32;
5770         const uint8_t vlan_mask_offset = 32;
5771         const uint8_t dst_pool_offset = 8;
5772         const uint8_t rule_mr_offset  = 4;
5773         const uint8_t mirror_rule_mask = 0x0F;
5774
5775         struct ixgbe_mirror_info *mr_info =
5776                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5777         struct ixgbe_hw *hw =
5778                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5779         uint8_t mirror_type = 0;
5780
5781         if (ixgbe_vt_check(hw) < 0)
5782                 return -ENOTSUP;
5783
5784         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5785                 return -EINVAL;
5786
5787         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5788                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5789                             mirror_conf->rule_type);
5790                 return -EINVAL;
5791         }
5792
5793         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5794                 mirror_type |= IXGBE_MRCTL_VLME;
5795                 /* Check if vlan id is valid and find conresponding VLAN ID
5796                  * index in VLVF
5797                  */
5798                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5799                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5800                                 /* search vlan id related pool vlan filter
5801                                  * index
5802                                  */
5803                                 reg_index = ixgbe_find_vlvf_slot(
5804                                                 hw,
5805                                                 mirror_conf->vlan.vlan_id[i],
5806                                                 false);
5807                                 if (reg_index < 0)
5808                                         return -EINVAL;
5809                                 vlvf = IXGBE_READ_REG(hw,
5810                                                       IXGBE_VLVF(reg_index));
5811                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5812                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5813                                       mirror_conf->vlan.vlan_id[i]))
5814                                         vlan_mask |= (1ULL << reg_index);
5815                                 else
5816                                         return -EINVAL;
5817                         }
5818                 }
5819
5820                 if (on) {
5821                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5822                         mv_msb = vlan_mask >> vlan_mask_offset;
5823
5824                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5825                                                 mirror_conf->vlan.vlan_mask;
5826                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5827                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5828                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5829                                                 mirror_conf->vlan.vlan_id[i];
5830                         }
5831                 } else {
5832                         mv_lsb = 0;
5833                         mv_msb = 0;
5834                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5835                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5836                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5837                 }
5838         }
5839
5840         /**
5841          * if enable pool mirror, write related pool mask register,if disable
5842          * pool mirror, clear PFMRVM register
5843          */
5844         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5845                 mirror_type |= IXGBE_MRCTL_VPME;
5846                 if (on) {
5847                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5848                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5849                         mr_info->mr_conf[rule_id].pool_mask =
5850                                         mirror_conf->pool_mask;
5851
5852                 } else {
5853                         mp_lsb = 0;
5854                         mp_msb = 0;
5855                         mr_info->mr_conf[rule_id].pool_mask = 0;
5856                 }
5857         }
5858         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5859                 mirror_type |= IXGBE_MRCTL_UPME;
5860         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5861                 mirror_type |= IXGBE_MRCTL_DPME;
5862
5863         /* read  mirror control register and recalculate it */
5864         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5865
5866         if (on) {
5867                 mr_ctl |= mirror_type;
5868                 mr_ctl &= mirror_rule_mask;
5869                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5870         } else {
5871                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5872         }
5873
5874         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5875         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5876
5877         /* write mirrror control  register */
5878         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5879
5880         /* write pool mirrror control  register */
5881         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5882                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5883                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5884                                 mp_msb);
5885         }
5886         /* write VLAN mirrror control  register */
5887         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5888                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5889                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5890                                 mv_msb);
5891         }
5892
5893         return 0;
5894 }
5895
5896 static int
5897 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5898 {
5899         int mr_ctl = 0;
5900         uint32_t lsb_val = 0;
5901         uint32_t msb_val = 0;
5902         const uint8_t rule_mr_offset = 4;
5903
5904         struct ixgbe_hw *hw =
5905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906         struct ixgbe_mirror_info *mr_info =
5907                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5908
5909         if (ixgbe_vt_check(hw) < 0)
5910                 return -ENOTSUP;
5911
5912         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5913                 return -EINVAL;
5914
5915         memset(&mr_info->mr_conf[rule_id], 0,
5916                sizeof(struct rte_eth_mirror_conf));
5917
5918         /* clear PFVMCTL register */
5919         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5920
5921         /* clear pool mask register */
5922         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5923         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5924
5925         /* clear vlan mask register */
5926         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5927         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5928
5929         return 0;
5930 }
5931
5932 static int
5933 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5934 {
5935         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5936         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5937         struct ixgbe_interrupt *intr =
5938                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5939         struct ixgbe_hw *hw =
5940                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5941         uint32_t vec = IXGBE_MISC_VEC_ID;
5942
5943         if (rte_intr_allow_others(intr_handle))
5944                 vec = IXGBE_RX_VEC_START;
5945         intr->mask |= (1 << vec);
5946         RTE_SET_USED(queue_id);
5947         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5948
5949         rte_intr_ack(intr_handle);
5950
5951         return 0;
5952 }
5953
5954 static int
5955 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5956 {
5957         struct ixgbe_interrupt *intr =
5958                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5959         struct ixgbe_hw *hw =
5960                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5961         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5962         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5963         uint32_t vec = IXGBE_MISC_VEC_ID;
5964
5965         if (rte_intr_allow_others(intr_handle))
5966                 vec = IXGBE_RX_VEC_START;
5967         intr->mask &= ~(1 << vec);
5968         RTE_SET_USED(queue_id);
5969         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5970
5971         return 0;
5972 }
5973
5974 static int
5975 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5976 {
5977         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5978         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5979         uint32_t mask;
5980         struct ixgbe_hw *hw =
5981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5982         struct ixgbe_interrupt *intr =
5983                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5984
5985         if (queue_id < 16) {
5986                 ixgbe_disable_intr(hw);
5987                 intr->mask |= (1 << queue_id);
5988                 ixgbe_enable_intr(dev);
5989         } else if (queue_id < 32) {
5990                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5991                 mask &= (1 << queue_id);
5992                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5993         } else if (queue_id < 64) {
5994                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5995                 mask &= (1 << (queue_id - 32));
5996                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5997         }
5998         rte_intr_ack(intr_handle);
5999
6000         return 0;
6001 }
6002
6003 static int
6004 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6005 {
6006         uint32_t mask;
6007         struct ixgbe_hw *hw =
6008                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009         struct ixgbe_interrupt *intr =
6010                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6011
6012         if (queue_id < 16) {
6013                 ixgbe_disable_intr(hw);
6014                 intr->mask &= ~(1 << queue_id);
6015                 ixgbe_enable_intr(dev);
6016         } else if (queue_id < 32) {
6017                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6018                 mask &= ~(1 << queue_id);
6019                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6020         } else if (queue_id < 64) {
6021                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6022                 mask &= ~(1 << (queue_id - 32));
6023                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6024         }
6025
6026         return 0;
6027 }
6028
6029 static void
6030 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6031                      uint8_t queue, uint8_t msix_vector)
6032 {
6033         uint32_t tmp, idx;
6034
6035         if (direction == -1) {
6036                 /* other causes */
6037                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6038                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6039                 tmp &= ~0xFF;
6040                 tmp |= msix_vector;
6041                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6042         } else {
6043                 /* rx or tx cause */
6044                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6045                 idx = ((16 * (queue & 1)) + (8 * direction));
6046                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6047                 tmp &= ~(0xFF << idx);
6048                 tmp |= (msix_vector << idx);
6049                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6050         }
6051 }
6052
6053 /**
6054  * set the IVAR registers, mapping interrupt causes to vectors
6055  * @param hw
6056  *  pointer to ixgbe_hw struct
6057  * @direction
6058  *  0 for Rx, 1 for Tx, -1 for other causes
6059  * @queue
6060  *  queue to map the corresponding interrupt to
6061  * @msix_vector
6062  *  the vector to map to the corresponding queue
6063  */
6064 static void
6065 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6066                    uint8_t queue, uint8_t msix_vector)
6067 {
6068         uint32_t tmp, idx;
6069
6070         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6071         if (hw->mac.type == ixgbe_mac_82598EB) {
6072                 if (direction == -1)
6073                         direction = 0;
6074                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6075                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6076                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6077                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6078                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6079         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6080                         (hw->mac.type == ixgbe_mac_X540) ||
6081                         (hw->mac.type == ixgbe_mac_X550) ||
6082                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6083                 if (direction == -1) {
6084                         /* other causes */
6085                         idx = ((queue & 1) * 8);
6086                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6087                         tmp &= ~(0xFF << idx);
6088                         tmp |= (msix_vector << idx);
6089                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6090                 } else {
6091                         /* rx or tx causes */
6092                         idx = ((16 * (queue & 1)) + (8 * direction));
6093                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6094                         tmp &= ~(0xFF << idx);
6095                         tmp |= (msix_vector << idx);
6096                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6097                 }
6098         }
6099 }
6100
6101 static void
6102 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6103 {
6104         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6105         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6106         struct ixgbe_hw *hw =
6107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6108         uint32_t q_idx;
6109         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6110         uint32_t base = IXGBE_MISC_VEC_ID;
6111
6112         /* Configure VF other cause ivar */
6113         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6114
6115         /* won't configure msix register if no mapping is done
6116          * between intr vector and event fd.
6117          */
6118         if (!rte_intr_dp_is_en(intr_handle))
6119                 return;
6120
6121         if (rte_intr_allow_others(intr_handle)) {
6122                 base = IXGBE_RX_VEC_START;
6123                 vector_idx = IXGBE_RX_VEC_START;
6124         }
6125
6126         /* Configure all RX queues of VF */
6127         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6128                 /* Force all queue use vector 0,
6129                  * as IXGBE_VF_MAXMSIVECOTR = 1
6130                  */
6131                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6132                 intr_handle->intr_vec[q_idx] = vector_idx;
6133                 if (vector_idx < base + intr_handle->nb_efd - 1)
6134                         vector_idx++;
6135         }
6136
6137         /* As RX queue setting above show, all queues use the vector 0.
6138          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6139          */
6140         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6141                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6142                         | IXGBE_EITR_CNT_WDIS);
6143 }
6144
6145 /**
6146  * Sets up the hardware to properly generate MSI-X interrupts
6147  * @hw
6148  *  board private structure
6149  */
6150 static void
6151 ixgbe_configure_msix(struct rte_eth_dev *dev)
6152 {
6153         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6154         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6155         struct ixgbe_hw *hw =
6156                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6157         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6158         uint32_t vec = IXGBE_MISC_VEC_ID;
6159         uint32_t mask;
6160         uint32_t gpie;
6161
6162         /* won't configure msix register if no mapping is done
6163          * between intr vector and event fd
6164          * but if misx has been enabled already, need to configure
6165          * auto clean, auto mask and throttling.
6166          */
6167         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6168         if (!rte_intr_dp_is_en(intr_handle) &&
6169             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6170                 return;
6171
6172         if (rte_intr_allow_others(intr_handle))
6173                 vec = base = IXGBE_RX_VEC_START;
6174
6175         /* setup GPIE for MSI-x mode */
6176         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6177         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6178                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6179         /* auto clearing and auto setting corresponding bits in EIMS
6180          * when MSI-X interrupt is triggered
6181          */
6182         if (hw->mac.type == ixgbe_mac_82598EB) {
6183                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6184         } else {
6185                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6186                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6187         }
6188         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6189
6190         /* Populate the IVAR table and set the ITR values to the
6191          * corresponding register.
6192          */
6193         if (rte_intr_dp_is_en(intr_handle)) {
6194                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6195                         queue_id++) {
6196                         /* by default, 1:1 mapping */
6197                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6198                         intr_handle->intr_vec[queue_id] = vec;
6199                         if (vec < base + intr_handle->nb_efd - 1)
6200                                 vec++;
6201                 }
6202
6203                 switch (hw->mac.type) {
6204                 case ixgbe_mac_82598EB:
6205                         ixgbe_set_ivar_map(hw, -1,
6206                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6207                                            IXGBE_MISC_VEC_ID);
6208                         break;
6209                 case ixgbe_mac_82599EB:
6210                 case ixgbe_mac_X540:
6211                 case ixgbe_mac_X550:
6212                 case ixgbe_mac_X550EM_x:
6213                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6214                         break;
6215                 default:
6216                         break;
6217                 }
6218         }
6219         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6220                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6221                         | IXGBE_EITR_CNT_WDIS);
6222
6223         /* set up to autoclear timer, and the vectors */
6224         mask = IXGBE_EIMS_ENABLE_MASK;
6225         mask &= ~(IXGBE_EIMS_OTHER |
6226                   IXGBE_EIMS_MAILBOX |
6227                   IXGBE_EIMS_LSC);
6228
6229         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6230 }
6231
6232 int
6233 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6234                            uint16_t queue_idx, uint16_t tx_rate)
6235 {
6236         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6237         struct rte_eth_rxmode *rxmode;
6238         uint32_t rf_dec, rf_int;
6239         uint32_t bcnrc_val;
6240         uint16_t link_speed = dev->data->dev_link.link_speed;
6241
6242         if (queue_idx >= hw->mac.max_tx_queues)
6243                 return -EINVAL;
6244
6245         if (tx_rate != 0) {
6246                 /* Calculate the rate factor values to set */
6247                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6248                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6249                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6250
6251                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6252                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6253                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6254                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6255         } else {
6256                 bcnrc_val = 0;
6257         }
6258
6259         rxmode = &dev->data->dev_conf.rxmode;
6260         /*
6261          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6262          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6263          * set as 0x4.
6264          */
6265         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6266             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6267                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6268                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6269         else
6270                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6271                         IXGBE_MMW_SIZE_DEFAULT);
6272
6273         /* Set RTTBCNRC of queue X */
6274         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6275         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6276         IXGBE_WRITE_FLUSH(hw);
6277
6278         return 0;
6279 }
6280
6281 static int
6282 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6283                      __rte_unused uint32_t index,
6284                      __rte_unused uint32_t pool)
6285 {
6286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6287         int diag;
6288
6289         /*
6290          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6291          * operation. Trap this case to avoid exhausting the [very limited]
6292          * set of PF resources used to store VF MAC addresses.
6293          */
6294         if (memcmp(hw->mac.perm_addr, mac_addr,
6295                         sizeof(struct rte_ether_addr)) == 0)
6296                 return -1;
6297         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6298         if (diag != 0)
6299                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6300                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6301                             mac_addr->addr_bytes[0],
6302                             mac_addr->addr_bytes[1],
6303                             mac_addr->addr_bytes[2],
6304                             mac_addr->addr_bytes[3],
6305                             mac_addr->addr_bytes[4],
6306                             mac_addr->addr_bytes[5],
6307                             diag);
6308         return diag;
6309 }
6310
6311 static void
6312 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6313 {
6314         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6315         struct rte_ether_addr *perm_addr =
6316                 (struct rte_ether_addr *)hw->mac.perm_addr;
6317         struct rte_ether_addr *mac_addr;
6318         uint32_t i;
6319         int diag;
6320
6321         /*
6322          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6323          * not support the deletion of a given MAC address.
6324          * Instead, it imposes to delete all MAC addresses, then to add again
6325          * all MAC addresses with the exception of the one to be deleted.
6326          */
6327         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6328
6329         /*
6330          * Add again all MAC addresses, with the exception of the deleted one
6331          * and of the permanent MAC address.
6332          */
6333         for (i = 0, mac_addr = dev->data->mac_addrs;
6334              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6335                 /* Skip the deleted MAC address */
6336                 if (i == index)
6337                         continue;
6338                 /* Skip NULL MAC addresses */
6339                 if (rte_is_zero_ether_addr(mac_addr))
6340                         continue;
6341                 /* Skip the permanent MAC address */
6342                 if (memcmp(perm_addr, mac_addr,
6343                                 sizeof(struct rte_ether_addr)) == 0)
6344                         continue;
6345                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6346                 if (diag != 0)
6347                         PMD_DRV_LOG(ERR,
6348                                     "Adding again MAC address "
6349                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6350                                     "diag=%d",
6351                                     mac_addr->addr_bytes[0],
6352                                     mac_addr->addr_bytes[1],
6353                                     mac_addr->addr_bytes[2],
6354                                     mac_addr->addr_bytes[3],
6355                                     mac_addr->addr_bytes[4],
6356                                     mac_addr->addr_bytes[5],
6357                                     diag);
6358         }
6359 }
6360
6361 static int
6362 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6363                         struct rte_ether_addr *addr)
6364 {
6365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366
6367         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6368
6369         return 0;
6370 }
6371
6372 int
6373 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6374                         struct rte_eth_syn_filter *filter,
6375                         bool add)
6376 {
6377         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6378         struct ixgbe_filter_info *filter_info =
6379                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6380         uint32_t syn_info;
6381         uint32_t synqf;
6382
6383         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6384                 return -EINVAL;
6385
6386         syn_info = filter_info->syn_info;
6387
6388         if (add) {
6389                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6390                         return -EINVAL;
6391                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6392                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6393
6394                 if (filter->hig_pri)
6395                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6396                 else
6397                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6398         } else {
6399                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6400                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6401                         return -ENOENT;
6402                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6403         }
6404
6405         filter_info->syn_info = synqf;
6406         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6407         IXGBE_WRITE_FLUSH(hw);
6408         return 0;
6409 }
6410
6411 static int
6412 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6413                         struct rte_eth_syn_filter *filter)
6414 {
6415         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6416         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6417
6418         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6419                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6420                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6421                 return 0;
6422         }
6423         return -ENOENT;
6424 }
6425
6426 static int
6427 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6428                         enum rte_filter_op filter_op,
6429                         void *arg)
6430 {
6431         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6432         int ret;
6433
6434         MAC_TYPE_FILTER_SUP(hw->mac.type);
6435
6436         if (filter_op == RTE_ETH_FILTER_NOP)
6437                 return 0;
6438
6439         if (arg == NULL) {
6440                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6441                             filter_op);
6442                 return -EINVAL;
6443         }
6444
6445         switch (filter_op) {
6446         case RTE_ETH_FILTER_ADD:
6447                 ret = ixgbe_syn_filter_set(dev,
6448                                 (struct rte_eth_syn_filter *)arg,
6449                                 TRUE);
6450                 break;
6451         case RTE_ETH_FILTER_DELETE:
6452                 ret = ixgbe_syn_filter_set(dev,
6453                                 (struct rte_eth_syn_filter *)arg,
6454                                 FALSE);
6455                 break;
6456         case RTE_ETH_FILTER_GET:
6457                 ret = ixgbe_syn_filter_get(dev,
6458                                 (struct rte_eth_syn_filter *)arg);
6459                 break;
6460         default:
6461                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6462                 ret = -EINVAL;
6463                 break;
6464         }
6465
6466         return ret;
6467 }
6468
6469
6470 static inline enum ixgbe_5tuple_protocol
6471 convert_protocol_type(uint8_t protocol_value)
6472 {
6473         if (protocol_value == IPPROTO_TCP)
6474                 return IXGBE_FILTER_PROTOCOL_TCP;
6475         else if (protocol_value == IPPROTO_UDP)
6476                 return IXGBE_FILTER_PROTOCOL_UDP;
6477         else if (protocol_value == IPPROTO_SCTP)
6478                 return IXGBE_FILTER_PROTOCOL_SCTP;
6479         else
6480                 return IXGBE_FILTER_PROTOCOL_NONE;
6481 }
6482
6483 /* inject a 5-tuple filter to HW */
6484 static inline void
6485 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6486                            struct ixgbe_5tuple_filter *filter)
6487 {
6488         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6489         int i;
6490         uint32_t ftqf, sdpqf;
6491         uint32_t l34timir = 0;
6492         uint8_t mask = 0xff;
6493
6494         i = filter->index;
6495
6496         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6497                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6498         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6499
6500         ftqf = (uint32_t)(filter->filter_info.proto &
6501                 IXGBE_FTQF_PROTOCOL_MASK);
6502         ftqf |= (uint32_t)((filter->filter_info.priority &
6503                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6504         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6505                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6506         if (filter->filter_info.dst_ip_mask == 0)
6507                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6508         if (filter->filter_info.src_port_mask == 0)
6509                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6510         if (filter->filter_info.dst_port_mask == 0)
6511                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6512         if (filter->filter_info.proto_mask == 0)
6513                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6514         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6515         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6516         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6517
6518         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6519         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6520         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6521         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6522
6523         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6524         l34timir |= (uint32_t)(filter->queue <<
6525                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6526         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6527 }
6528
6529 /*
6530  * add a 5tuple filter
6531  *
6532  * @param
6533  * dev: Pointer to struct rte_eth_dev.
6534  * index: the index the filter allocates.
6535  * filter: ponter to the filter that will be added.
6536  * rx_queue: the queue id the filter assigned to.
6537  *
6538  * @return
6539  *    - On success, zero.
6540  *    - On failure, a negative value.
6541  */
6542 static int
6543 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6544                         struct ixgbe_5tuple_filter *filter)
6545 {
6546         struct ixgbe_filter_info *filter_info =
6547                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6548         int i, idx, shift;
6549
6550         /*
6551          * look for an unused 5tuple filter index,
6552          * and insert the filter to list.
6553          */
6554         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6555                 idx = i / (sizeof(uint32_t) * NBBY);
6556                 shift = i % (sizeof(uint32_t) * NBBY);
6557                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6558                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6559                         filter->index = i;
6560                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6561                                           filter,
6562                                           entries);
6563                         break;
6564                 }
6565         }
6566         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6567                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6568                 return -ENOSYS;
6569         }
6570
6571         ixgbe_inject_5tuple_filter(dev, filter);
6572
6573         return 0;
6574 }
6575
6576 /*
6577  * remove a 5tuple filter
6578  *
6579  * @param
6580  * dev: Pointer to struct rte_eth_dev.
6581  * filter: the pointer of the filter will be removed.
6582  */
6583 static void
6584 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6585                         struct ixgbe_5tuple_filter *filter)
6586 {
6587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6588         struct ixgbe_filter_info *filter_info =
6589                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6590         uint16_t index = filter->index;
6591
6592         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6593                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6594         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6595         rte_free(filter);
6596
6597         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6598         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6599         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6600         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6601         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6602 }
6603
6604 static int
6605 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6606 {
6607         struct ixgbe_hw *hw;
6608         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6609         struct rte_eth_dev_data *dev_data = dev->data;
6610
6611         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6612
6613         if (mtu < RTE_ETHER_MIN_MTU ||
6614                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6615                 return -EINVAL;
6616
6617         /* If device is started, refuse mtu that requires the support of
6618          * scattered packets when this feature has not been enabled before.
6619          */
6620         if (dev_data->dev_started && !dev_data->scattered_rx &&
6621             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6622              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6623                 PMD_INIT_LOG(ERR, "Stop port first.");
6624                 return -EINVAL;
6625         }
6626
6627         /*
6628          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6629          * request of the version 2.0 of the mailbox API.
6630          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6631          * of the mailbox API.
6632          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6633          * prior to 3.11.33 which contains the following change:
6634          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6635          */
6636         ixgbevf_rlpml_set_vf(hw, max_frame);
6637
6638         /* update max frame size */
6639         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6640         return 0;
6641 }
6642
6643 static inline struct ixgbe_5tuple_filter *
6644 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6645                         struct ixgbe_5tuple_filter_info *key)
6646 {
6647         struct ixgbe_5tuple_filter *it;
6648
6649         TAILQ_FOREACH(it, filter_list, entries) {
6650                 if (memcmp(key, &it->filter_info,
6651                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6652                         return it;
6653                 }
6654         }
6655         return NULL;
6656 }
6657
6658 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6659 static inline int
6660 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6661                         struct ixgbe_5tuple_filter_info *filter_info)
6662 {
6663         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6664                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6665                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6666                 return -EINVAL;
6667
6668         switch (filter->dst_ip_mask) {
6669         case UINT32_MAX:
6670                 filter_info->dst_ip_mask = 0;
6671                 filter_info->dst_ip = filter->dst_ip;
6672                 break;
6673         case 0:
6674                 filter_info->dst_ip_mask = 1;
6675                 break;
6676         default:
6677                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6678                 return -EINVAL;
6679         }
6680
6681         switch (filter->src_ip_mask) {
6682         case UINT32_MAX:
6683                 filter_info->src_ip_mask = 0;
6684                 filter_info->src_ip = filter->src_ip;
6685                 break;
6686         case 0:
6687                 filter_info->src_ip_mask = 1;
6688                 break;
6689         default:
6690                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6691                 return -EINVAL;
6692         }
6693
6694         switch (filter->dst_port_mask) {
6695         case UINT16_MAX:
6696                 filter_info->dst_port_mask = 0;
6697                 filter_info->dst_port = filter->dst_port;
6698                 break;
6699         case 0:
6700                 filter_info->dst_port_mask = 1;
6701                 break;
6702         default:
6703                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6704                 return -EINVAL;
6705         }
6706
6707         switch (filter->src_port_mask) {
6708         case UINT16_MAX:
6709                 filter_info->src_port_mask = 0;
6710                 filter_info->src_port = filter->src_port;
6711                 break;
6712         case 0:
6713                 filter_info->src_port_mask = 1;
6714                 break;
6715         default:
6716                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6717                 return -EINVAL;
6718         }
6719
6720         switch (filter->proto_mask) {
6721         case UINT8_MAX:
6722                 filter_info->proto_mask = 0;
6723                 filter_info->proto =
6724                         convert_protocol_type(filter->proto);
6725                 break;
6726         case 0:
6727                 filter_info->proto_mask = 1;
6728                 break;
6729         default:
6730                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6731                 return -EINVAL;
6732         }
6733
6734         filter_info->priority = (uint8_t)filter->priority;
6735         return 0;
6736 }
6737
6738 /*
6739  * add or delete a ntuple filter
6740  *
6741  * @param
6742  * dev: Pointer to struct rte_eth_dev.
6743  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6744  * add: if true, add filter, if false, remove filter
6745  *
6746  * @return
6747  *    - On success, zero.
6748  *    - On failure, a negative value.
6749  */
6750 int
6751 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6752                         struct rte_eth_ntuple_filter *ntuple_filter,
6753                         bool add)
6754 {
6755         struct ixgbe_filter_info *filter_info =
6756                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6757         struct ixgbe_5tuple_filter_info filter_5tuple;
6758         struct ixgbe_5tuple_filter *filter;
6759         int ret;
6760
6761         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6762                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6763                 return -EINVAL;
6764         }
6765
6766         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6767         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6768         if (ret < 0)
6769                 return ret;
6770
6771         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6772                                          &filter_5tuple);
6773         if (filter != NULL && add) {
6774                 PMD_DRV_LOG(ERR, "filter exists.");
6775                 return -EEXIST;
6776         }
6777         if (filter == NULL && !add) {
6778                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6779                 return -ENOENT;
6780         }
6781
6782         if (add) {
6783                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6784                                 sizeof(struct ixgbe_5tuple_filter), 0);
6785                 if (filter == NULL)
6786                         return -ENOMEM;
6787                 rte_memcpy(&filter->filter_info,
6788                                  &filter_5tuple,
6789                                  sizeof(struct ixgbe_5tuple_filter_info));
6790                 filter->queue = ntuple_filter->queue;
6791                 ret = ixgbe_add_5tuple_filter(dev, filter);
6792                 if (ret < 0) {
6793                         rte_free(filter);
6794                         return ret;
6795                 }
6796         } else
6797                 ixgbe_remove_5tuple_filter(dev, filter);
6798
6799         return 0;
6800 }
6801
6802 /*
6803  * get a ntuple filter
6804  *
6805  * @param
6806  * dev: Pointer to struct rte_eth_dev.
6807  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6808  *
6809  * @return
6810  *    - On success, zero.
6811  *    - On failure, a negative value.
6812  */
6813 static int
6814 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6815                         struct rte_eth_ntuple_filter *ntuple_filter)
6816 {
6817         struct ixgbe_filter_info *filter_info =
6818                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6819         struct ixgbe_5tuple_filter_info filter_5tuple;
6820         struct ixgbe_5tuple_filter *filter;
6821         int ret;
6822
6823         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6824                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6825                 return -EINVAL;
6826         }
6827
6828         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6829         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6830         if (ret < 0)
6831                 return ret;
6832
6833         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6834                                          &filter_5tuple);
6835         if (filter == NULL) {
6836                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6837                 return -ENOENT;
6838         }
6839         ntuple_filter->queue = filter->queue;
6840         return 0;
6841 }
6842
6843 /*
6844  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6845  * @dev: pointer to rte_eth_dev structure
6846  * @filter_op:operation will be taken.
6847  * @arg: a pointer to specific structure corresponding to the filter_op
6848  *
6849  * @return
6850  *    - On success, zero.
6851  *    - On failure, a negative value.
6852  */
6853 static int
6854 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6855                                 enum rte_filter_op filter_op,
6856                                 void *arg)
6857 {
6858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6859         int ret;
6860
6861         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6862
6863         if (filter_op == RTE_ETH_FILTER_NOP)
6864                 return 0;
6865
6866         if (arg == NULL) {
6867                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6868                             filter_op);
6869                 return -EINVAL;
6870         }
6871
6872         switch (filter_op) {
6873         case RTE_ETH_FILTER_ADD:
6874                 ret = ixgbe_add_del_ntuple_filter(dev,
6875                         (struct rte_eth_ntuple_filter *)arg,
6876                         TRUE);
6877                 break;
6878         case RTE_ETH_FILTER_DELETE:
6879                 ret = ixgbe_add_del_ntuple_filter(dev,
6880                         (struct rte_eth_ntuple_filter *)arg,
6881                         FALSE);
6882                 break;
6883         case RTE_ETH_FILTER_GET:
6884                 ret = ixgbe_get_ntuple_filter(dev,
6885                         (struct rte_eth_ntuple_filter *)arg);
6886                 break;
6887         default:
6888                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6889                 ret = -EINVAL;
6890                 break;
6891         }
6892         return ret;
6893 }
6894
6895 int
6896 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6897                         struct rte_eth_ethertype_filter *filter,
6898                         bool add)
6899 {
6900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6901         struct ixgbe_filter_info *filter_info =
6902                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6903         uint32_t etqf = 0;
6904         uint32_t etqs = 0;
6905         int ret;
6906         struct ixgbe_ethertype_filter ethertype_filter;
6907
6908         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6909                 return -EINVAL;
6910
6911         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6912                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6913                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6914                         " ethertype filter.", filter->ether_type);
6915                 return -EINVAL;
6916         }
6917
6918         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6919                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6920                 return -EINVAL;
6921         }
6922         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6923                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6924                 return -EINVAL;
6925         }
6926
6927         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6928         if (ret >= 0 && add) {
6929                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6930                             filter->ether_type);
6931                 return -EEXIST;
6932         }
6933         if (ret < 0 && !add) {
6934                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6935                             filter->ether_type);
6936                 return -ENOENT;
6937         }
6938
6939         if (add) {
6940                 etqf = IXGBE_ETQF_FILTER_EN;
6941                 etqf |= (uint32_t)filter->ether_type;
6942                 etqs |= (uint32_t)((filter->queue <<
6943                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6944                                     IXGBE_ETQS_RX_QUEUE);
6945                 etqs |= IXGBE_ETQS_QUEUE_EN;
6946
6947                 ethertype_filter.ethertype = filter->ether_type;
6948                 ethertype_filter.etqf = etqf;
6949                 ethertype_filter.etqs = etqs;
6950                 ethertype_filter.conf = FALSE;
6951                 ret = ixgbe_ethertype_filter_insert(filter_info,
6952                                                     &ethertype_filter);
6953                 if (ret < 0) {
6954                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6955                         return -ENOSPC;
6956                 }
6957         } else {
6958                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6959                 if (ret < 0)
6960                         return -ENOSYS;
6961         }
6962         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6963         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6964         IXGBE_WRITE_FLUSH(hw);
6965
6966         return 0;
6967 }
6968
6969 static int
6970 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6971                         struct rte_eth_ethertype_filter *filter)
6972 {
6973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6974         struct ixgbe_filter_info *filter_info =
6975                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6976         uint32_t etqf, etqs;
6977         int ret;
6978
6979         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6980         if (ret < 0) {
6981                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6982                             filter->ether_type);
6983                 return -ENOENT;
6984         }
6985
6986         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6987         if (etqf & IXGBE_ETQF_FILTER_EN) {
6988                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6989                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6990                 filter->flags = 0;
6991                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6992                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6993                 return 0;
6994         }
6995         return -ENOENT;
6996 }
6997
6998 /*
6999  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7000  * @dev: pointer to rte_eth_dev structure
7001  * @filter_op:operation will be taken.
7002  * @arg: a pointer to specific structure corresponding to the filter_op
7003  */
7004 static int
7005 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7006                                 enum rte_filter_op filter_op,
7007                                 void *arg)
7008 {
7009         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7010         int ret;
7011
7012         MAC_TYPE_FILTER_SUP(hw->mac.type);
7013
7014         if (filter_op == RTE_ETH_FILTER_NOP)
7015                 return 0;
7016
7017         if (arg == NULL) {
7018                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7019                             filter_op);
7020                 return -EINVAL;
7021         }
7022
7023         switch (filter_op) {
7024         case RTE_ETH_FILTER_ADD:
7025                 ret = ixgbe_add_del_ethertype_filter(dev,
7026                         (struct rte_eth_ethertype_filter *)arg,
7027                         TRUE);
7028                 break;
7029         case RTE_ETH_FILTER_DELETE:
7030                 ret = ixgbe_add_del_ethertype_filter(dev,
7031                         (struct rte_eth_ethertype_filter *)arg,
7032                         FALSE);
7033                 break;
7034         case RTE_ETH_FILTER_GET:
7035                 ret = ixgbe_get_ethertype_filter(dev,
7036                         (struct rte_eth_ethertype_filter *)arg);
7037                 break;
7038         default:
7039                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7040                 ret = -EINVAL;
7041                 break;
7042         }
7043         return ret;
7044 }
7045
7046 static int
7047 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7048                      enum rte_filter_type filter_type,
7049                      enum rte_filter_op filter_op,
7050                      void *arg)
7051 {
7052         int ret = 0;
7053
7054         switch (filter_type) {
7055         case RTE_ETH_FILTER_NTUPLE:
7056                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7057                 break;
7058         case RTE_ETH_FILTER_ETHERTYPE:
7059                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7060                 break;
7061         case RTE_ETH_FILTER_SYN:
7062                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7063                 break;
7064         case RTE_ETH_FILTER_FDIR:
7065                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7066                 break;
7067         case RTE_ETH_FILTER_L2_TUNNEL:
7068                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7069                 break;
7070         case RTE_ETH_FILTER_GENERIC:
7071                 if (filter_op != RTE_ETH_FILTER_GET)
7072                         return -EINVAL;
7073                 *(const void **)arg = &ixgbe_flow_ops;
7074                 break;
7075         default:
7076                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7077                                                         filter_type);
7078                 ret = -EINVAL;
7079                 break;
7080         }
7081
7082         return ret;
7083 }
7084
7085 static u8 *
7086 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7087                         u8 **mc_addr_ptr, u32 *vmdq)
7088 {
7089         u8 *mc_addr;
7090
7091         *vmdq = 0;
7092         mc_addr = *mc_addr_ptr;
7093         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7094         return mc_addr;
7095 }
7096
7097 static int
7098 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7099                           struct rte_ether_addr *mc_addr_set,
7100                           uint32_t nb_mc_addr)
7101 {
7102         struct ixgbe_hw *hw;
7103         u8 *mc_addr_list;
7104
7105         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7106         mc_addr_list = (u8 *)mc_addr_set;
7107         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7108                                          ixgbe_dev_addr_list_itr, TRUE);
7109 }
7110
7111 static uint64_t
7112 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7113 {
7114         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7115         uint64_t systime_cycles;
7116
7117         switch (hw->mac.type) {
7118         case ixgbe_mac_X550:
7119         case ixgbe_mac_X550EM_x:
7120         case ixgbe_mac_X550EM_a:
7121                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7122                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7123                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7124                                 * NSEC_PER_SEC;
7125                 break;
7126         default:
7127                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7128                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7129                                 << 32;
7130         }
7131
7132         return systime_cycles;
7133 }
7134
7135 static uint64_t
7136 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7137 {
7138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7139         uint64_t rx_tstamp_cycles;
7140
7141         switch (hw->mac.type) {
7142         case ixgbe_mac_X550:
7143         case ixgbe_mac_X550EM_x:
7144         case ixgbe_mac_X550EM_a:
7145                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7146                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7147                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7148                                 * NSEC_PER_SEC;
7149                 break;
7150         default:
7151                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7152                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7153                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7154                                 << 32;
7155         }
7156
7157         return rx_tstamp_cycles;
7158 }
7159
7160 static uint64_t
7161 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7162 {
7163         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7164         uint64_t tx_tstamp_cycles;
7165
7166         switch (hw->mac.type) {
7167         case ixgbe_mac_X550:
7168         case ixgbe_mac_X550EM_x:
7169         case ixgbe_mac_X550EM_a:
7170                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7171                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7172                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7173                                 * NSEC_PER_SEC;
7174                 break;
7175         default:
7176                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7177                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7178                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7179                                 << 32;
7180         }
7181
7182         return tx_tstamp_cycles;
7183 }
7184
7185 static void
7186 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7187 {
7188         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7189         struct ixgbe_adapter *adapter = dev->data->dev_private;
7190         struct rte_eth_link link;
7191         uint32_t incval = 0;
7192         uint32_t shift = 0;
7193
7194         /* Get current link speed. */
7195         ixgbe_dev_link_update(dev, 1);
7196         rte_eth_linkstatus_get(dev, &link);
7197
7198         switch (link.link_speed) {
7199         case ETH_SPEED_NUM_100M:
7200                 incval = IXGBE_INCVAL_100;
7201                 shift = IXGBE_INCVAL_SHIFT_100;
7202                 break;
7203         case ETH_SPEED_NUM_1G:
7204                 incval = IXGBE_INCVAL_1GB;
7205                 shift = IXGBE_INCVAL_SHIFT_1GB;
7206                 break;
7207         case ETH_SPEED_NUM_10G:
7208         default:
7209                 incval = IXGBE_INCVAL_10GB;
7210                 shift = IXGBE_INCVAL_SHIFT_10GB;
7211                 break;
7212         }
7213
7214         switch (hw->mac.type) {
7215         case ixgbe_mac_X550:
7216         case ixgbe_mac_X550EM_x:
7217         case ixgbe_mac_X550EM_a:
7218                 /* Independent of link speed. */
7219                 incval = 1;
7220                 /* Cycles read will be interpreted as ns. */
7221                 shift = 0;
7222                 /* Fall-through */
7223         case ixgbe_mac_X540:
7224                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7225                 break;
7226         case ixgbe_mac_82599EB:
7227                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7228                 shift -= IXGBE_INCVAL_SHIFT_82599;
7229                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7230                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7231                 break;
7232         default:
7233                 /* Not supported. */
7234                 return;
7235         }
7236
7237         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7238         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7239         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7240
7241         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7242         adapter->systime_tc.cc_shift = shift;
7243         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7244
7245         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7246         adapter->rx_tstamp_tc.cc_shift = shift;
7247         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7248
7249         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7250         adapter->tx_tstamp_tc.cc_shift = shift;
7251         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7252 }
7253
7254 static int
7255 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7256 {
7257         struct ixgbe_adapter *adapter = dev->data->dev_private;
7258
7259         adapter->systime_tc.nsec += delta;
7260         adapter->rx_tstamp_tc.nsec += delta;
7261         adapter->tx_tstamp_tc.nsec += delta;
7262
7263         return 0;
7264 }
7265
7266 static int
7267 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7268 {
7269         uint64_t ns;
7270         struct ixgbe_adapter *adapter = dev->data->dev_private;
7271
7272         ns = rte_timespec_to_ns(ts);
7273         /* Set the timecounters to a new value. */
7274         adapter->systime_tc.nsec = ns;
7275         adapter->rx_tstamp_tc.nsec = ns;
7276         adapter->tx_tstamp_tc.nsec = ns;
7277
7278         return 0;
7279 }
7280
7281 static int
7282 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7283 {
7284         uint64_t ns, systime_cycles;
7285         struct ixgbe_adapter *adapter = dev->data->dev_private;
7286
7287         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7288         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7289         *ts = rte_ns_to_timespec(ns);
7290
7291         return 0;
7292 }
7293
7294 static int
7295 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7296 {
7297         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7298         uint32_t tsync_ctl;
7299         uint32_t tsauxc;
7300
7301         /* Stop the timesync system time. */
7302         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7303         /* Reset the timesync system time value. */
7304         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7305         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7306
7307         /* Enable system time for platforms where it isn't on by default. */
7308         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7309         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7310         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7311
7312         ixgbe_start_timecounters(dev);
7313
7314         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7315         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7316                         (RTE_ETHER_TYPE_1588 |
7317                          IXGBE_ETQF_FILTER_EN |
7318                          IXGBE_ETQF_1588));
7319
7320         /* Enable timestamping of received PTP packets. */
7321         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7322         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7323         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7324
7325         /* Enable timestamping of transmitted PTP packets. */
7326         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7327         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7328         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7329
7330         IXGBE_WRITE_FLUSH(hw);
7331
7332         return 0;
7333 }
7334
7335 static int
7336 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7337 {
7338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7339         uint32_t tsync_ctl;
7340
7341         /* Disable timestamping of transmitted PTP packets. */
7342         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7343         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7344         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7345
7346         /* Disable timestamping of received PTP packets. */
7347         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7348         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7349         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7350
7351         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7352         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7353
7354         /* Stop incrementating the System Time registers. */
7355         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7356
7357         return 0;
7358 }
7359
7360 static int
7361 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7362                                  struct timespec *timestamp,
7363                                  uint32_t flags __rte_unused)
7364 {
7365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7366         struct ixgbe_adapter *adapter = dev->data->dev_private;
7367         uint32_t tsync_rxctl;
7368         uint64_t rx_tstamp_cycles;
7369         uint64_t ns;
7370
7371         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7372         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7373                 return -EINVAL;
7374
7375         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7376         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7377         *timestamp = rte_ns_to_timespec(ns);
7378
7379         return  0;
7380 }
7381
7382 static int
7383 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7384                                  struct timespec *timestamp)
7385 {
7386         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7387         struct ixgbe_adapter *adapter = dev->data->dev_private;
7388         uint32_t tsync_txctl;
7389         uint64_t tx_tstamp_cycles;
7390         uint64_t ns;
7391
7392         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7393         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7394                 return -EINVAL;
7395
7396         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7397         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7398         *timestamp = rte_ns_to_timespec(ns);
7399
7400         return 0;
7401 }
7402
7403 static int
7404 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7405 {
7406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7407         int count = 0;
7408         int g_ind = 0;
7409         const struct reg_info *reg_group;
7410         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7411                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7412
7413         while ((reg_group = reg_set[g_ind++]))
7414                 count += ixgbe_regs_group_count(reg_group);
7415
7416         return count;
7417 }
7418
7419 static int
7420 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7421 {
7422         int count = 0;
7423         int g_ind = 0;
7424         const struct reg_info *reg_group;
7425
7426         while ((reg_group = ixgbevf_regs[g_ind++]))
7427                 count += ixgbe_regs_group_count(reg_group);
7428
7429         return count;
7430 }
7431
7432 static int
7433 ixgbe_get_regs(struct rte_eth_dev *dev,
7434               struct rte_dev_reg_info *regs)
7435 {
7436         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7437         uint32_t *data = regs->data;
7438         int g_ind = 0;
7439         int count = 0;
7440         const struct reg_info *reg_group;
7441         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7442                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7443
7444         if (data == NULL) {
7445                 regs->length = ixgbe_get_reg_length(dev);
7446                 regs->width = sizeof(uint32_t);
7447                 return 0;
7448         }
7449
7450         /* Support only full register dump */
7451         if ((regs->length == 0) ||
7452             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7453                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7454                         hw->device_id;
7455                 while ((reg_group = reg_set[g_ind++]))
7456                         count += ixgbe_read_regs_group(dev, &data[count],
7457                                 reg_group);
7458                 return 0;
7459         }
7460
7461         return -ENOTSUP;
7462 }
7463
7464 static int
7465 ixgbevf_get_regs(struct rte_eth_dev *dev,
7466                 struct rte_dev_reg_info *regs)
7467 {
7468         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7469         uint32_t *data = regs->data;
7470         int g_ind = 0;
7471         int count = 0;
7472         const struct reg_info *reg_group;
7473
7474         if (data == NULL) {
7475                 regs->length = ixgbevf_get_reg_length(dev);
7476                 regs->width = sizeof(uint32_t);
7477                 return 0;
7478         }
7479
7480         /* Support only full register dump */
7481         if ((regs->length == 0) ||
7482             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7483                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7484                         hw->device_id;
7485                 while ((reg_group = ixgbevf_regs[g_ind++]))
7486                         count += ixgbe_read_regs_group(dev, &data[count],
7487                                                       reg_group);
7488                 return 0;
7489         }
7490
7491         return -ENOTSUP;
7492 }
7493
7494 static int
7495 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7496 {
7497         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7498
7499         /* Return unit is byte count */
7500         return hw->eeprom.word_size * 2;
7501 }
7502
7503 static int
7504 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7505                 struct rte_dev_eeprom_info *in_eeprom)
7506 {
7507         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7508         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7509         uint16_t *data = in_eeprom->data;
7510         int first, length;
7511
7512         first = in_eeprom->offset >> 1;
7513         length = in_eeprom->length >> 1;
7514         if ((first > hw->eeprom.word_size) ||
7515             ((first + length) > hw->eeprom.word_size))
7516                 return -EINVAL;
7517
7518         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7519
7520         return eeprom->ops.read_buffer(hw, first, length, data);
7521 }
7522
7523 static int
7524 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7525                 struct rte_dev_eeprom_info *in_eeprom)
7526 {
7527         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7528         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7529         uint16_t *data = in_eeprom->data;
7530         int first, length;
7531
7532         first = in_eeprom->offset >> 1;
7533         length = in_eeprom->length >> 1;
7534         if ((first > hw->eeprom.word_size) ||
7535             ((first + length) > hw->eeprom.word_size))
7536                 return -EINVAL;
7537
7538         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7539
7540         return eeprom->ops.write_buffer(hw,  first, length, data);
7541 }
7542
7543 static int
7544 ixgbe_get_module_info(struct rte_eth_dev *dev,
7545                       struct rte_eth_dev_module_info *modinfo)
7546 {
7547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7548         uint32_t status;
7549         uint8_t sff8472_rev, addr_mode;
7550         bool page_swap = false;
7551
7552         /* Check whether we support SFF-8472 or not */
7553         status = hw->phy.ops.read_i2c_eeprom(hw,
7554                                              IXGBE_SFF_SFF_8472_COMP,
7555                                              &sff8472_rev);
7556         if (status != 0)
7557                 return -EIO;
7558
7559         /* addressing mode is not supported */
7560         status = hw->phy.ops.read_i2c_eeprom(hw,
7561                                              IXGBE_SFF_SFF_8472_SWAP,
7562                                              &addr_mode);
7563         if (status != 0)
7564                 return -EIO;
7565
7566         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7567                 PMD_DRV_LOG(ERR,
7568                             "Address change required to access page 0xA2, "
7569                             "but not supported. Please report the module "
7570                             "type to the driver maintainers.");
7571                 page_swap = true;
7572         }
7573
7574         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7575                 /* We have a SFP, but it does not support SFF-8472 */
7576                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7577                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7578         } else {
7579                 /* We have a SFP which supports a revision of SFF-8472. */
7580                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7581                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7582         }
7583
7584         return 0;
7585 }
7586
7587 static int
7588 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7589                         struct rte_dev_eeprom_info *info)
7590 {
7591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7592         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7593         uint8_t databyte = 0xFF;
7594         uint8_t *data = info->data;
7595         uint32_t i = 0;
7596
7597         if (info->length == 0)
7598                 return -EINVAL;
7599
7600         for (i = info->offset; i < info->offset + info->length; i++) {
7601                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7602                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7603                 else
7604                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7605
7606                 if (status != 0)
7607                         return -EIO;
7608
7609                 data[i - info->offset] = databyte;
7610         }
7611
7612         return 0;
7613 }
7614
7615 uint16_t
7616 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7617         switch (mac_type) {
7618         case ixgbe_mac_X550:
7619         case ixgbe_mac_X550EM_x:
7620         case ixgbe_mac_X550EM_a:
7621                 return ETH_RSS_RETA_SIZE_512;
7622         case ixgbe_mac_X550_vf:
7623         case ixgbe_mac_X550EM_x_vf:
7624         case ixgbe_mac_X550EM_a_vf:
7625                 return ETH_RSS_RETA_SIZE_64;
7626         case ixgbe_mac_X540_vf:
7627         case ixgbe_mac_82599_vf:
7628                 return 0;
7629         default:
7630                 return ETH_RSS_RETA_SIZE_128;
7631         }
7632 }
7633
7634 uint32_t
7635 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7636         switch (mac_type) {
7637         case ixgbe_mac_X550:
7638         case ixgbe_mac_X550EM_x:
7639         case ixgbe_mac_X550EM_a:
7640                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7641                         return IXGBE_RETA(reta_idx >> 2);
7642                 else
7643                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7644         case ixgbe_mac_X550_vf:
7645         case ixgbe_mac_X550EM_x_vf:
7646         case ixgbe_mac_X550EM_a_vf:
7647                 return IXGBE_VFRETA(reta_idx >> 2);
7648         default:
7649                 return IXGBE_RETA(reta_idx >> 2);
7650         }
7651 }
7652
7653 uint32_t
7654 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7655         switch (mac_type) {
7656         case ixgbe_mac_X550_vf:
7657         case ixgbe_mac_X550EM_x_vf:
7658         case ixgbe_mac_X550EM_a_vf:
7659                 return IXGBE_VFMRQC;
7660         default:
7661                 return IXGBE_MRQC;
7662         }
7663 }
7664
7665 uint32_t
7666 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7667         switch (mac_type) {
7668         case ixgbe_mac_X550_vf:
7669         case ixgbe_mac_X550EM_x_vf:
7670         case ixgbe_mac_X550EM_a_vf:
7671                 return IXGBE_VFRSSRK(i);
7672         default:
7673                 return IXGBE_RSSRK(i);
7674         }
7675 }
7676
7677 bool
7678 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7679         switch (mac_type) {
7680         case ixgbe_mac_82599_vf:
7681         case ixgbe_mac_X540_vf:
7682                 return 0;
7683         default:
7684                 return 1;
7685         }
7686 }
7687
7688 static int
7689 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7690                         struct rte_eth_dcb_info *dcb_info)
7691 {
7692         struct ixgbe_dcb_config *dcb_config =
7693                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7694         struct ixgbe_dcb_tc_config *tc;
7695         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7696         uint8_t nb_tcs;
7697         uint8_t i, j;
7698
7699         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7700                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7701         else
7702                 dcb_info->nb_tcs = 1;
7703
7704         tc_queue = &dcb_info->tc_queue;
7705         nb_tcs = dcb_info->nb_tcs;
7706
7707         if (dcb_config->vt_mode) { /* vt is enabled*/
7708                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7709                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7710                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7711                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7712                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7713                         for (j = 0; j < nb_tcs; j++) {
7714                                 tc_queue->tc_rxq[0][j].base = j;
7715                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7716                                 tc_queue->tc_txq[0][j].base = j;
7717                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7718                         }
7719                 } else {
7720                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7721                                 for (j = 0; j < nb_tcs; j++) {
7722                                         tc_queue->tc_rxq[i][j].base =
7723                                                 i * nb_tcs + j;
7724                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7725                                         tc_queue->tc_txq[i][j].base =
7726                                                 i * nb_tcs + j;
7727                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7728                                 }
7729                         }
7730                 }
7731         } else { /* vt is disabled*/
7732                 struct rte_eth_dcb_rx_conf *rx_conf =
7733                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7734                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7735                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7736                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7737                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7738                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7739                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7740                         }
7741                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7742                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7743                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7744                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7745                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7746                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7747                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7748                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7749                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7750                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7751                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7752                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7753                         }
7754                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7755                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7756                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7757                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7758                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7759                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7760                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7761                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7762                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7763                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7764                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7765                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7766                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7767                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7768                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7769                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7770                 }
7771         }
7772         for (i = 0; i < dcb_info->nb_tcs; i++) {
7773                 tc = &dcb_config->tc_config[i];
7774                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7775         }
7776         return 0;
7777 }
7778
7779 /* Update e-tag ether type */
7780 static int
7781 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7782                             uint16_t ether_type)
7783 {
7784         uint32_t etag_etype;
7785
7786         if (hw->mac.type != ixgbe_mac_X550 &&
7787             hw->mac.type != ixgbe_mac_X550EM_x &&
7788             hw->mac.type != ixgbe_mac_X550EM_a) {
7789                 return -ENOTSUP;
7790         }
7791
7792         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7793         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7794         etag_etype |= ether_type;
7795         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7796         IXGBE_WRITE_FLUSH(hw);
7797
7798         return 0;
7799 }
7800
7801 /* Config l2 tunnel ether type */
7802 static int
7803 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7804                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7805 {
7806         int ret = 0;
7807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7808         struct ixgbe_l2_tn_info *l2_tn_info =
7809                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7810
7811         if (l2_tunnel == NULL)
7812                 return -EINVAL;
7813
7814         switch (l2_tunnel->l2_tunnel_type) {
7815         case RTE_L2_TUNNEL_TYPE_E_TAG:
7816                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7817                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7818                 break;
7819         default:
7820                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7821                 ret = -EINVAL;
7822                 break;
7823         }
7824
7825         return ret;
7826 }
7827
7828 /* Enable e-tag tunnel */
7829 static int
7830 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7831 {
7832         uint32_t etag_etype;
7833
7834         if (hw->mac.type != ixgbe_mac_X550 &&
7835             hw->mac.type != ixgbe_mac_X550EM_x &&
7836             hw->mac.type != ixgbe_mac_X550EM_a) {
7837                 return -ENOTSUP;
7838         }
7839
7840         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7841         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7842         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7843         IXGBE_WRITE_FLUSH(hw);
7844
7845         return 0;
7846 }
7847
7848 /* Enable l2 tunnel */
7849 static int
7850 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7851                            enum rte_eth_tunnel_type l2_tunnel_type)
7852 {
7853         int ret = 0;
7854         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7855         struct ixgbe_l2_tn_info *l2_tn_info =
7856                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7857
7858         switch (l2_tunnel_type) {
7859         case RTE_L2_TUNNEL_TYPE_E_TAG:
7860                 l2_tn_info->e_tag_en = TRUE;
7861                 ret = ixgbe_e_tag_enable(hw);
7862                 break;
7863         default:
7864                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7865                 ret = -EINVAL;
7866                 break;
7867         }
7868
7869         return ret;
7870 }
7871
7872 /* Disable e-tag tunnel */
7873 static int
7874 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7875 {
7876         uint32_t etag_etype;
7877
7878         if (hw->mac.type != ixgbe_mac_X550 &&
7879             hw->mac.type != ixgbe_mac_X550EM_x &&
7880             hw->mac.type != ixgbe_mac_X550EM_a) {
7881                 return -ENOTSUP;
7882         }
7883
7884         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7885         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7886         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7887         IXGBE_WRITE_FLUSH(hw);
7888
7889         return 0;
7890 }
7891
7892 /* Disable l2 tunnel */
7893 static int
7894 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7895                             enum rte_eth_tunnel_type l2_tunnel_type)
7896 {
7897         int ret = 0;
7898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7899         struct ixgbe_l2_tn_info *l2_tn_info =
7900                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7901
7902         switch (l2_tunnel_type) {
7903         case RTE_L2_TUNNEL_TYPE_E_TAG:
7904                 l2_tn_info->e_tag_en = FALSE;
7905                 ret = ixgbe_e_tag_disable(hw);
7906                 break;
7907         default:
7908                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7909                 ret = -EINVAL;
7910                 break;
7911         }
7912
7913         return ret;
7914 }
7915
7916 static int
7917 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7918                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7919 {
7920         int ret = 0;
7921         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7922         uint32_t i, rar_entries;
7923         uint32_t rar_low, rar_high;
7924
7925         if (hw->mac.type != ixgbe_mac_X550 &&
7926             hw->mac.type != ixgbe_mac_X550EM_x &&
7927             hw->mac.type != ixgbe_mac_X550EM_a) {
7928                 return -ENOTSUP;
7929         }
7930
7931         rar_entries = ixgbe_get_num_rx_addrs(hw);
7932
7933         for (i = 1; i < rar_entries; i++) {
7934                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7935                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7936                 if ((rar_high & IXGBE_RAH_AV) &&
7937                     (rar_high & IXGBE_RAH_ADTYPE) &&
7938                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7939                      l2_tunnel->tunnel_id)) {
7940                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7941                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7942
7943                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7944
7945                         return ret;
7946                 }
7947         }
7948
7949         return ret;
7950 }
7951
7952 static int
7953 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7954                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7955 {
7956         int ret = 0;
7957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7958         uint32_t i, rar_entries;
7959         uint32_t rar_low, rar_high;
7960
7961         if (hw->mac.type != ixgbe_mac_X550 &&
7962             hw->mac.type != ixgbe_mac_X550EM_x &&
7963             hw->mac.type != ixgbe_mac_X550EM_a) {
7964                 return -ENOTSUP;
7965         }
7966
7967         /* One entry for one tunnel. Try to remove potential existing entry. */
7968         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7969
7970         rar_entries = ixgbe_get_num_rx_addrs(hw);
7971
7972         for (i = 1; i < rar_entries; i++) {
7973                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7974                 if (rar_high & IXGBE_RAH_AV) {
7975                         continue;
7976                 } else {
7977                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7978                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7979                         rar_low = l2_tunnel->tunnel_id;
7980
7981                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7982                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7983
7984                         return ret;
7985                 }
7986         }
7987
7988         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7989                      " Please remove a rule before adding a new one.");
7990         return -EINVAL;
7991 }
7992
7993 static inline struct ixgbe_l2_tn_filter *
7994 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7995                           struct ixgbe_l2_tn_key *key)
7996 {
7997         int ret;
7998
7999         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8000         if (ret < 0)
8001                 return NULL;
8002
8003         return l2_tn_info->hash_map[ret];
8004 }
8005
8006 static inline int
8007 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8008                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8009 {
8010         int ret;
8011
8012         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8013                                &l2_tn_filter->key);
8014
8015         if (ret < 0) {
8016                 PMD_DRV_LOG(ERR,
8017                             "Failed to insert L2 tunnel filter"
8018                             " to hash table %d!",
8019                             ret);
8020                 return ret;
8021         }
8022
8023         l2_tn_info->hash_map[ret] = l2_tn_filter;
8024
8025         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8026
8027         return 0;
8028 }
8029
8030 static inline int
8031 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8032                           struct ixgbe_l2_tn_key *key)
8033 {
8034         int ret;
8035         struct ixgbe_l2_tn_filter *l2_tn_filter;
8036
8037         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8038
8039         if (ret < 0) {
8040                 PMD_DRV_LOG(ERR,
8041                             "No such L2 tunnel filter to delete %d!",
8042                             ret);
8043                 return ret;
8044         }
8045
8046         l2_tn_filter = l2_tn_info->hash_map[ret];
8047         l2_tn_info->hash_map[ret] = NULL;
8048
8049         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8050         rte_free(l2_tn_filter);
8051
8052         return 0;
8053 }
8054
8055 /* Add l2 tunnel filter */
8056 int
8057 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8058                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8059                                bool restore)
8060 {
8061         int ret;
8062         struct ixgbe_l2_tn_info *l2_tn_info =
8063                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8064         struct ixgbe_l2_tn_key key;
8065         struct ixgbe_l2_tn_filter *node;
8066
8067         if (!restore) {
8068                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8069                 key.tn_id = l2_tunnel->tunnel_id;
8070
8071                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8072
8073                 if (node) {
8074                         PMD_DRV_LOG(ERR,
8075                                     "The L2 tunnel filter already exists!");
8076                         return -EINVAL;
8077                 }
8078
8079                 node = rte_zmalloc("ixgbe_l2_tn",
8080                                    sizeof(struct ixgbe_l2_tn_filter),
8081                                    0);
8082                 if (!node)
8083                         return -ENOMEM;
8084
8085                 rte_memcpy(&node->key,
8086                                  &key,
8087                                  sizeof(struct ixgbe_l2_tn_key));
8088                 node->pool = l2_tunnel->pool;
8089                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8090                 if (ret < 0) {
8091                         rte_free(node);
8092                         return ret;
8093                 }
8094         }
8095
8096         switch (l2_tunnel->l2_tunnel_type) {
8097         case RTE_L2_TUNNEL_TYPE_E_TAG:
8098                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8099                 break;
8100         default:
8101                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8102                 ret = -EINVAL;
8103                 break;
8104         }
8105
8106         if ((!restore) && (ret < 0))
8107                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8108
8109         return ret;
8110 }
8111
8112 /* Delete l2 tunnel filter */
8113 int
8114 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8115                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8116 {
8117         int ret;
8118         struct ixgbe_l2_tn_info *l2_tn_info =
8119                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8120         struct ixgbe_l2_tn_key key;
8121
8122         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8123         key.tn_id = l2_tunnel->tunnel_id;
8124         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8125         if (ret < 0)
8126                 return ret;
8127
8128         switch (l2_tunnel->l2_tunnel_type) {
8129         case RTE_L2_TUNNEL_TYPE_E_TAG:
8130                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8131                 break;
8132         default:
8133                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8134                 ret = -EINVAL;
8135                 break;
8136         }
8137
8138         return ret;
8139 }
8140
8141 /**
8142  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8143  * @dev: pointer to rte_eth_dev structure
8144  * @filter_op:operation will be taken.
8145  * @arg: a pointer to specific structure corresponding to the filter_op
8146  */
8147 static int
8148 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8149                                   enum rte_filter_op filter_op,
8150                                   void *arg)
8151 {
8152         int ret;
8153
8154         if (filter_op == RTE_ETH_FILTER_NOP)
8155                 return 0;
8156
8157         if (arg == NULL) {
8158                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8159                             filter_op);
8160                 return -EINVAL;
8161         }
8162
8163         switch (filter_op) {
8164         case RTE_ETH_FILTER_ADD:
8165                 ret = ixgbe_dev_l2_tunnel_filter_add
8166                         (dev,
8167                          (struct rte_eth_l2_tunnel_conf *)arg,
8168                          FALSE);
8169                 break;
8170         case RTE_ETH_FILTER_DELETE:
8171                 ret = ixgbe_dev_l2_tunnel_filter_del
8172                         (dev,
8173                          (struct rte_eth_l2_tunnel_conf *)arg);
8174                 break;
8175         default:
8176                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8177                 ret = -EINVAL;
8178                 break;
8179         }
8180         return ret;
8181 }
8182
8183 static int
8184 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8185 {
8186         int ret = 0;
8187         uint32_t ctrl;
8188         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8189
8190         if (hw->mac.type != ixgbe_mac_X550 &&
8191             hw->mac.type != ixgbe_mac_X550EM_x &&
8192             hw->mac.type != ixgbe_mac_X550EM_a) {
8193                 return -ENOTSUP;
8194         }
8195
8196         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8197         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8198         if (en)
8199                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8200         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8201
8202         return ret;
8203 }
8204
8205 /* Enable l2 tunnel forwarding */
8206 static int
8207 ixgbe_dev_l2_tunnel_forwarding_enable
8208         (struct rte_eth_dev *dev,
8209          enum rte_eth_tunnel_type l2_tunnel_type)
8210 {
8211         struct ixgbe_l2_tn_info *l2_tn_info =
8212                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8213         int ret = 0;
8214
8215         switch (l2_tunnel_type) {
8216         case RTE_L2_TUNNEL_TYPE_E_TAG:
8217                 l2_tn_info->e_tag_fwd_en = TRUE;
8218                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8219                 break;
8220         default:
8221                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8222                 ret = -EINVAL;
8223                 break;
8224         }
8225
8226         return ret;
8227 }
8228
8229 /* Disable l2 tunnel forwarding */
8230 static int
8231 ixgbe_dev_l2_tunnel_forwarding_disable
8232         (struct rte_eth_dev *dev,
8233          enum rte_eth_tunnel_type l2_tunnel_type)
8234 {
8235         struct ixgbe_l2_tn_info *l2_tn_info =
8236                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8237         int ret = 0;
8238
8239         switch (l2_tunnel_type) {
8240         case RTE_L2_TUNNEL_TYPE_E_TAG:
8241                 l2_tn_info->e_tag_fwd_en = FALSE;
8242                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8243                 break;
8244         default:
8245                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8246                 ret = -EINVAL;
8247                 break;
8248         }
8249
8250         return ret;
8251 }
8252
8253 static int
8254 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8255                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8256                              bool en)
8257 {
8258         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8259         int ret = 0;
8260         uint32_t vmtir, vmvir;
8261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8262
8263         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8264                 PMD_DRV_LOG(ERR,
8265                             "VF id %u should be less than %u",
8266                             l2_tunnel->vf_id,
8267                             pci_dev->max_vfs);
8268                 return -EINVAL;
8269         }
8270
8271         if (hw->mac.type != ixgbe_mac_X550 &&
8272             hw->mac.type != ixgbe_mac_X550EM_x &&
8273             hw->mac.type != ixgbe_mac_X550EM_a) {
8274                 return -ENOTSUP;
8275         }
8276
8277         if (en)
8278                 vmtir = l2_tunnel->tunnel_id;
8279         else
8280                 vmtir = 0;
8281
8282         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8283
8284         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8285         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8286         if (en)
8287                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8288         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8289
8290         return ret;
8291 }
8292
8293 /* Enable l2 tunnel tag insertion */
8294 static int
8295 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8296                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8297 {
8298         int ret = 0;
8299
8300         switch (l2_tunnel->l2_tunnel_type) {
8301         case RTE_L2_TUNNEL_TYPE_E_TAG:
8302                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8303                 break;
8304         default:
8305                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8306                 ret = -EINVAL;
8307                 break;
8308         }
8309
8310         return ret;
8311 }
8312
8313 /* Disable l2 tunnel tag insertion */
8314 static int
8315 ixgbe_dev_l2_tunnel_insertion_disable
8316         (struct rte_eth_dev *dev,
8317          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8318 {
8319         int ret = 0;
8320
8321         switch (l2_tunnel->l2_tunnel_type) {
8322         case RTE_L2_TUNNEL_TYPE_E_TAG:
8323                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8324                 break;
8325         default:
8326                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8327                 ret = -EINVAL;
8328                 break;
8329         }
8330
8331         return ret;
8332 }
8333
8334 static int
8335 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8336                              bool en)
8337 {
8338         int ret = 0;
8339         uint32_t qde;
8340         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8341
8342         if (hw->mac.type != ixgbe_mac_X550 &&
8343             hw->mac.type != ixgbe_mac_X550EM_x &&
8344             hw->mac.type != ixgbe_mac_X550EM_a) {
8345                 return -ENOTSUP;
8346         }
8347
8348         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8349         if (en)
8350                 qde |= IXGBE_QDE_STRIP_TAG;
8351         else
8352                 qde &= ~IXGBE_QDE_STRIP_TAG;
8353         qde &= ~IXGBE_QDE_READ;
8354         qde |= IXGBE_QDE_WRITE;
8355         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8356
8357         return ret;
8358 }
8359
8360 /* Enable l2 tunnel tag stripping */
8361 static int
8362 ixgbe_dev_l2_tunnel_stripping_enable
8363         (struct rte_eth_dev *dev,
8364          enum rte_eth_tunnel_type l2_tunnel_type)
8365 {
8366         int ret = 0;
8367
8368         switch (l2_tunnel_type) {
8369         case RTE_L2_TUNNEL_TYPE_E_TAG:
8370                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8371                 break;
8372         default:
8373                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8374                 ret = -EINVAL;
8375                 break;
8376         }
8377
8378         return ret;
8379 }
8380
8381 /* Disable l2 tunnel tag stripping */
8382 static int
8383 ixgbe_dev_l2_tunnel_stripping_disable
8384         (struct rte_eth_dev *dev,
8385          enum rte_eth_tunnel_type l2_tunnel_type)
8386 {
8387         int ret = 0;
8388
8389         switch (l2_tunnel_type) {
8390         case RTE_L2_TUNNEL_TYPE_E_TAG:
8391                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8392                 break;
8393         default:
8394                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8395                 ret = -EINVAL;
8396                 break;
8397         }
8398
8399         return ret;
8400 }
8401
8402 /* Enable/disable l2 tunnel offload functions */
8403 static int
8404 ixgbe_dev_l2_tunnel_offload_set
8405         (struct rte_eth_dev *dev,
8406          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8407          uint32_t mask,
8408          uint8_t en)
8409 {
8410         int ret = 0;
8411
8412         if (l2_tunnel == NULL)
8413                 return -EINVAL;
8414
8415         ret = -EINVAL;
8416         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8417                 if (en)
8418                         ret = ixgbe_dev_l2_tunnel_enable(
8419                                 dev,
8420                                 l2_tunnel->l2_tunnel_type);
8421                 else
8422                         ret = ixgbe_dev_l2_tunnel_disable(
8423                                 dev,
8424                                 l2_tunnel->l2_tunnel_type);
8425         }
8426
8427         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8428                 if (en)
8429                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8430                                 dev,
8431                                 l2_tunnel);
8432                 else
8433                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8434                                 dev,
8435                                 l2_tunnel);
8436         }
8437
8438         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8439                 if (en)
8440                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8441                                 dev,
8442                                 l2_tunnel->l2_tunnel_type);
8443                 else
8444                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8445                                 dev,
8446                                 l2_tunnel->l2_tunnel_type);
8447         }
8448
8449         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8450                 if (en)
8451                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8452                                 dev,
8453                                 l2_tunnel->l2_tunnel_type);
8454                 else
8455                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8456                                 dev,
8457                                 l2_tunnel->l2_tunnel_type);
8458         }
8459
8460         return ret;
8461 }
8462
8463 static int
8464 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8465                         uint16_t port)
8466 {
8467         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8468         IXGBE_WRITE_FLUSH(hw);
8469
8470         return 0;
8471 }
8472
8473 /* There's only one register for VxLAN UDP port.
8474  * So, we cannot add several ports. Will update it.
8475  */
8476 static int
8477 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8478                      uint16_t port)
8479 {
8480         if (port == 0) {
8481                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8482                 return -EINVAL;
8483         }
8484
8485         return ixgbe_update_vxlan_port(hw, port);
8486 }
8487
8488 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8489  * UDP port, it must have a value.
8490  * So, will reset it to the original value 0.
8491  */
8492 static int
8493 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8494                      uint16_t port)
8495 {
8496         uint16_t cur_port;
8497
8498         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8499
8500         if (cur_port != port) {
8501                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8502                 return -EINVAL;
8503         }
8504
8505         return ixgbe_update_vxlan_port(hw, 0);
8506 }
8507
8508 /* Add UDP tunneling port */
8509 static int
8510 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8511                               struct rte_eth_udp_tunnel *udp_tunnel)
8512 {
8513         int ret = 0;
8514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8515
8516         if (hw->mac.type != ixgbe_mac_X550 &&
8517             hw->mac.type != ixgbe_mac_X550EM_x &&
8518             hw->mac.type != ixgbe_mac_X550EM_a) {
8519                 return -ENOTSUP;
8520         }
8521
8522         if (udp_tunnel == NULL)
8523                 return -EINVAL;
8524
8525         switch (udp_tunnel->prot_type) {
8526         case RTE_TUNNEL_TYPE_VXLAN:
8527                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8528                 break;
8529
8530         case RTE_TUNNEL_TYPE_GENEVE:
8531         case RTE_TUNNEL_TYPE_TEREDO:
8532                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8533                 ret = -EINVAL;
8534                 break;
8535
8536         default:
8537                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8538                 ret = -EINVAL;
8539                 break;
8540         }
8541
8542         return ret;
8543 }
8544
8545 /* Remove UDP tunneling port */
8546 static int
8547 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8548                               struct rte_eth_udp_tunnel *udp_tunnel)
8549 {
8550         int ret = 0;
8551         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8552
8553         if (hw->mac.type != ixgbe_mac_X550 &&
8554             hw->mac.type != ixgbe_mac_X550EM_x &&
8555             hw->mac.type != ixgbe_mac_X550EM_a) {
8556                 return -ENOTSUP;
8557         }
8558
8559         if (udp_tunnel == NULL)
8560                 return -EINVAL;
8561
8562         switch (udp_tunnel->prot_type) {
8563         case RTE_TUNNEL_TYPE_VXLAN:
8564                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8565                 break;
8566         case RTE_TUNNEL_TYPE_GENEVE:
8567         case RTE_TUNNEL_TYPE_TEREDO:
8568                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8569                 ret = -EINVAL;
8570                 break;
8571         default:
8572                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8573                 ret = -EINVAL;
8574                 break;
8575         }
8576
8577         return ret;
8578 }
8579
8580 static int
8581 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8582 {
8583         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8584         int ret;
8585
8586         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8587         case IXGBE_SUCCESS:
8588                 ret = 0;
8589                 break;
8590         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8591                 ret = -ENOTSUP;
8592                 break;
8593         default:
8594                 ret = -EAGAIN;
8595                 break;
8596         }
8597
8598         return ret;
8599 }
8600
8601 static int
8602 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8603 {
8604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8605         int ret;
8606
8607         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8608         case IXGBE_SUCCESS:
8609                 ret = 0;
8610                 break;
8611         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8612                 ret = -ENOTSUP;
8613                 break;
8614         default:
8615                 ret = -EAGAIN;
8616                 break;
8617         }
8618
8619         return ret;
8620 }
8621
8622 static int
8623 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8624 {
8625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8626         int ret;
8627         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8628
8629         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8630         case IXGBE_SUCCESS:
8631                 ret = 0;
8632                 break;
8633         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8634                 ret = -ENOTSUP;
8635                 break;
8636         default:
8637                 ret = -EAGAIN;
8638                 break;
8639         }
8640
8641         return ret;
8642 }
8643
8644 static int
8645 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8646 {
8647         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8648         int ret;
8649
8650         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8651         case IXGBE_SUCCESS:
8652                 ret = 0;
8653                 break;
8654         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8655                 ret = -ENOTSUP;
8656                 break;
8657         default:
8658                 ret = -EAGAIN;
8659                 break;
8660         }
8661
8662         return ret;
8663 }
8664
8665 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8666 {
8667         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8668         u32 in_msg = 0;
8669
8670         /* peek the message first */
8671         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8672
8673         /* PF reset VF event */
8674         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8675                 /* dummy mbx read to ack pf */
8676                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8677                         return;
8678                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8679                                               NULL);
8680         }
8681 }
8682
8683 static int
8684 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8685 {
8686         uint32_t eicr;
8687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8688         struct ixgbe_interrupt *intr =
8689                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8690         ixgbevf_intr_disable(dev);
8691
8692         /* read-on-clear nic registers here */
8693         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8694         intr->flags = 0;
8695
8696         /* only one misc vector supported - mailbox */
8697         eicr &= IXGBE_VTEICR_MASK;
8698         if (eicr == IXGBE_MISC_VEC_ID)
8699                 intr->flags |= IXGBE_FLAG_MAILBOX;
8700
8701         return 0;
8702 }
8703
8704 static int
8705 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8706 {
8707         struct ixgbe_interrupt *intr =
8708                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8709
8710         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8711                 ixgbevf_mbx_process(dev);
8712                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8713         }
8714
8715         ixgbevf_intr_enable(dev);
8716
8717         return 0;
8718 }
8719
8720 static void
8721 ixgbevf_dev_interrupt_handler(void *param)
8722 {
8723         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8724
8725         ixgbevf_dev_interrupt_get_status(dev);
8726         ixgbevf_dev_interrupt_action(dev);
8727 }
8728
8729 /**
8730  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8731  *  @hw: pointer to hardware structure
8732  *
8733  *  Stops the transmit data path and waits for the HW to internally empty
8734  *  the Tx security block
8735  **/
8736 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8737 {
8738 #define IXGBE_MAX_SECTX_POLL 40
8739
8740         int i;
8741         int sectxreg;
8742
8743         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8744         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8745         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8746         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8747                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8748                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8749                         break;
8750                 /* Use interrupt-safe sleep just in case */
8751                 usec_delay(1000);
8752         }
8753
8754         /* For informational purposes only */
8755         if (i >= IXGBE_MAX_SECTX_POLL)
8756                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8757                          "path fully disabled.  Continuing with init.");
8758
8759         return IXGBE_SUCCESS;
8760 }
8761
8762 /**
8763  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8764  *  @hw: pointer to hardware structure
8765  *
8766  *  Enables the transmit data path.
8767  **/
8768 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8769 {
8770         uint32_t sectxreg;
8771
8772         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8773         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8774         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8775         IXGBE_WRITE_FLUSH(hw);
8776
8777         return IXGBE_SUCCESS;
8778 }
8779
8780 /* restore n-tuple filter */
8781 static inline void
8782 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8783 {
8784         struct ixgbe_filter_info *filter_info =
8785                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8786         struct ixgbe_5tuple_filter *node;
8787
8788         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8789                 ixgbe_inject_5tuple_filter(dev, node);
8790         }
8791 }
8792
8793 /* restore ethernet type filter */
8794 static inline void
8795 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8796 {
8797         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8798         struct ixgbe_filter_info *filter_info =
8799                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8800         int i;
8801
8802         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8803                 if (filter_info->ethertype_mask & (1 << i)) {
8804                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8805                                         filter_info->ethertype_filters[i].etqf);
8806                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8807                                         filter_info->ethertype_filters[i].etqs);
8808                         IXGBE_WRITE_FLUSH(hw);
8809                 }
8810         }
8811 }
8812
8813 /* restore SYN filter */
8814 static inline void
8815 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8816 {
8817         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8818         struct ixgbe_filter_info *filter_info =
8819                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8820         uint32_t synqf;
8821
8822         synqf = filter_info->syn_info;
8823
8824         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8825                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8826                 IXGBE_WRITE_FLUSH(hw);
8827         }
8828 }
8829
8830 /* restore L2 tunnel filter */
8831 static inline void
8832 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8833 {
8834         struct ixgbe_l2_tn_info *l2_tn_info =
8835                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8836         struct ixgbe_l2_tn_filter *node;
8837         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8838
8839         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8840                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8841                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8842                 l2_tn_conf.pool           = node->pool;
8843                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8844         }
8845 }
8846
8847 /* restore rss filter */
8848 static inline void
8849 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8850 {
8851         struct ixgbe_filter_info *filter_info =
8852                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8853
8854         if (filter_info->rss_info.conf.queue_num)
8855                 ixgbe_config_rss_filter(dev,
8856                         &filter_info->rss_info, TRUE);
8857 }
8858
8859 static int
8860 ixgbe_filter_restore(struct rte_eth_dev *dev)
8861 {
8862         ixgbe_ntuple_filter_restore(dev);
8863         ixgbe_ethertype_filter_restore(dev);
8864         ixgbe_syn_filter_restore(dev);
8865         ixgbe_fdir_filter_restore(dev);
8866         ixgbe_l2_tn_filter_restore(dev);
8867         ixgbe_rss_filter_restore(dev);
8868
8869         return 0;
8870 }
8871
8872 static void
8873 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8874 {
8875         struct ixgbe_l2_tn_info *l2_tn_info =
8876                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8877         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8878
8879         if (l2_tn_info->e_tag_en)
8880                 (void)ixgbe_e_tag_enable(hw);
8881
8882         if (l2_tn_info->e_tag_fwd_en)
8883                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8884
8885         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8886 }
8887
8888 /* remove all the n-tuple filters */
8889 void
8890 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8891 {
8892         struct ixgbe_filter_info *filter_info =
8893                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8894         struct ixgbe_5tuple_filter *p_5tuple;
8895
8896         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8897                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8898 }
8899
8900 /* remove all the ether type filters */
8901 void
8902 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8903 {
8904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8905         struct ixgbe_filter_info *filter_info =
8906                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8907         int i;
8908
8909         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8910                 if (filter_info->ethertype_mask & (1 << i) &&
8911                     !filter_info->ethertype_filters[i].conf) {
8912                         (void)ixgbe_ethertype_filter_remove(filter_info,
8913                                                             (uint8_t)i);
8914                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8915                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8916                         IXGBE_WRITE_FLUSH(hw);
8917                 }
8918         }
8919 }
8920
8921 /* remove the SYN filter */
8922 void
8923 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8924 {
8925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8926         struct ixgbe_filter_info *filter_info =
8927                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8928
8929         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8930                 filter_info->syn_info = 0;
8931
8932                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8933                 IXGBE_WRITE_FLUSH(hw);
8934         }
8935 }
8936
8937 /* remove all the L2 tunnel filters */
8938 int
8939 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8940 {
8941         struct ixgbe_l2_tn_info *l2_tn_info =
8942                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8943         struct ixgbe_l2_tn_filter *l2_tn_filter;
8944         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8945         int ret = 0;
8946
8947         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8948                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8949                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8950                 l2_tn_conf.pool           = l2_tn_filter->pool;
8951                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8952                 if (ret < 0)
8953                         return ret;
8954         }
8955
8956         return 0;
8957 }
8958
8959 void
8960 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8961                                 struct ixgbe_macsec_setting *macsec_setting)
8962 {
8963         struct ixgbe_macsec_setting *macsec =
8964                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8965
8966         macsec->offload_en = macsec_setting->offload_en;
8967         macsec->encrypt_en = macsec_setting->encrypt_en;
8968         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8969 }
8970
8971 void
8972 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8973 {
8974         struct ixgbe_macsec_setting *macsec =
8975                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8976
8977         macsec->offload_en = 0;
8978         macsec->encrypt_en = 0;
8979         macsec->replayprotect_en = 0;
8980 }
8981
8982 void
8983 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8984                                 struct ixgbe_macsec_setting *macsec_setting)
8985 {
8986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8987         uint32_t ctrl;
8988         uint8_t en = macsec_setting->encrypt_en;
8989         uint8_t rp = macsec_setting->replayprotect_en;
8990
8991         /**
8992          * Workaround:
8993          * As no ixgbe_disable_sec_rx_path equivalent is
8994          * implemented for tx in the base code, and we are
8995          * not allowed to modify the base code in DPDK, so
8996          * just call the hand-written one directly for now.
8997          * The hardware support has been checked by
8998          * ixgbe_disable_sec_rx_path().
8999          */
9000         ixgbe_disable_sec_tx_path_generic(hw);
9001
9002         /* Enable Ethernet CRC (required by MACsec offload) */
9003         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9004         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9005         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9006
9007         /* Enable the TX and RX crypto engines */
9008         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9009         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9010         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9011
9012         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9013         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9014         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9015
9016         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9017         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9018         ctrl |= 0x3;
9019         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9020
9021         /* Enable SA lookup */
9022         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9023         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9024         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9025                      IXGBE_LSECTXCTRL_AUTH;
9026         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9027         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9028         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9029         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9030
9031         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9032         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9033         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9034         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9035         if (rp)
9036                 ctrl |= IXGBE_LSECRXCTRL_RP;
9037         else
9038                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9039         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9040
9041         /* Start the data paths */
9042         ixgbe_enable_sec_rx_path(hw);
9043         /**
9044          * Workaround:
9045          * As no ixgbe_enable_sec_rx_path equivalent is
9046          * implemented for tx in the base code, and we are
9047          * not allowed to modify the base code in DPDK, so
9048          * just call the hand-written one directly for now.
9049          */
9050         ixgbe_enable_sec_tx_path_generic(hw);
9051 }
9052
9053 void
9054 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9055 {
9056         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9057         uint32_t ctrl;
9058
9059         /**
9060          * Workaround:
9061          * As no ixgbe_disable_sec_rx_path equivalent is
9062          * implemented for tx in the base code, and we are
9063          * not allowed to modify the base code in DPDK, so
9064          * just call the hand-written one directly for now.
9065          * The hardware support has been checked by
9066          * ixgbe_disable_sec_rx_path().
9067          */
9068         ixgbe_disable_sec_tx_path_generic(hw);
9069
9070         /* Disable the TX and RX crypto engines */
9071         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9072         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9073         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9074
9075         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9076         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9077         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9078
9079         /* Disable SA lookup */
9080         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9081         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9082         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9083         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9084
9085         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9086         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9087         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9088         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9089
9090         /* Start the data paths */
9091         ixgbe_enable_sec_rx_path(hw);
9092         /**
9093          * Workaround:
9094          * As no ixgbe_enable_sec_rx_path equivalent is
9095          * implemented for tx in the base code, and we are
9096          * not allowed to modify the base code in DPDK, so
9097          * just call the hand-written one directly for now.
9098          */
9099         ixgbe_enable_sec_tx_path_generic(hw);
9100 }
9101
9102 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9103 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9104 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9105 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9106 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9107 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9108 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9109                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9110
9111 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9112 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9113
9114 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9115 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9116 #endif
9117 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9118 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9119 #endif
9120 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9121 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9122 #endif