drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_eal.h>
  26 #include <rte_alarm.h>
  27 #include <rte_ether.h>
  28 #include <rte_ethdev_driver.h>
  29 #include <rte_ethdev_pci.h>
  30 #include <rte_malloc.h>
  31 #include <rte_random.h>
  32 #include <rte_dev.h>
  33 #include <rte_hash_crc.h>
  34 #ifdef RTE_LIBRTE_SECURITY
  35 #include <rte_security_driver.h>
  36 #endif
  37
  38 #include "ixgbe_logs.h"
  39 #include "base/ixgbe_api.h"
  40 #include "base/ixgbe_vf.h"
  41 #include "base/ixgbe_common.h"
  42 #include "ixgbe_ethdev.h"
  43 #include "ixgbe_bypass.h"
  44 #include "ixgbe_rxtx.h"
  45 #include "base/ixgbe_type.h"
  46 #include "base/ixgbe_phy.h"
  47 #include "ixgbe_regs.h"
  48
  49 /*
  50  * High threshold controlling when to start sending XOFF frames. Must be at
  51  * least 8 bytes less than receive packet buffer size. This value is in units
  52  * of 1024 bytes.
  53  */
  54 #define IXGBE_FC_HI    0x80
  55
  56 /*
  57  * Low threshold controlling when to start sending XON frames. This value is
  58  * in units of 1024 bytes.
  59  */
  60 #define IXGBE_FC_LO    0x40
  61
  62 /* Default minimum inter-interrupt interval for EITR configuration */
  63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  64
  65 /* Timer value included in XOFF frames. */
  66 #define IXGBE_FC_PAUSE 0x680
  67
  68 /*Default value of Max Rx Queue*/
  69 #define IXGBE_MAX_RX_QUEUE_NUM 128
  70
  71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  72 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  73 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  74
  75 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  76 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  77 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  78
  79 /*
  80  *  Default values for RX/TX configuration
  81  */
  82 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  83 #define IXGBE_DEFAULT_RX_PTHRESH      8
  84 #define IXGBE_DEFAULT_RX_HTHRESH      8
  85 #define IXGBE_DEFAULT_RX_WTHRESH      0
  86
  87 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  88 #define IXGBE_DEFAULT_TX_PTHRESH      32
  89 #define IXGBE_DEFAULT_TX_HTHRESH      0
  90 #define IXGBE_DEFAULT_TX_WTHRESH      0
  91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  92
  93 /* Bit shift and mask */
  94 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  95 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  96 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  97 #define IXGBE_8_BIT_MASK   UINT8_MAX
  98
  99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 100
 101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 102
 103 #define IXGBE_HKEY_MAX_INDEX 10
 104
 105 /* Additional timesync values. */
 106 #define NSEC_PER_SEC             1000000000L
 107 #define IXGBE_INCVAL_10GB        0x66666666
 108 #define IXGBE_INCVAL_1GB         0x40000000
 109 #define IXGBE_INCVAL_100         0x50000000
 110 #define IXGBE_INCVAL_SHIFT_10GB  28
 111 #define IXGBE_INCVAL_SHIFT_1GB   24
 112 #define IXGBE_INCVAL_SHIFT_100   21
 113 #define IXGBE_INCVAL_SHIFT_82599 7
 114 #define IXGBE_INCPER_SHIFT_82599 24
 115
 116 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 120 #define DEFAULT_ETAG_ETYPE                     0x893f
 121 #define IXGBE_ETAG_ETYPE                       0x00005084
 122 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 123 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 124 #define IXGBE_RAH_ADTYPE                       0x40000000
 125 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 126 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 129 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 130 #define IXGBE_VTEICR_MASK                      0x07
 131
 132 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 133 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 134
 135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 143 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 145 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstat *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstat *xstats, unsigned n);
 161 static int
 162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 163                 uint64_t *values, unsigned int n);
 164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 167         struct rte_eth_xstat_name *xstats_names,
 168         unsigned int size);
 169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 171 static int ixgbe_dev_xstats_get_names_by_id(
 172         struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names,
 174         const uint64_t *ids,
 175         unsigned int limit);
 176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 177                                              uint16_t queue_id,
 178                                              uint8_t stat_idx,
 179                                              uint8_t is_rx);
 180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 181                                  size_t fw_size);
 182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 183                                struct rte_eth_dev_info *dev_info);
 184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 186                                  struct rte_eth_dev_info *dev_info);
 187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 188
 189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 190                 uint16_t vlan_id, int on);
 191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 192                                enum rte_vlan_type vlan_type,
 193                                uint16_t tpid_id);
 194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 195                 uint16_t queue, bool on);
 196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 197                 int on);
 198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 203
 204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 207                                struct rte_eth_fc_conf *fc_conf);
 208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 209                                struct rte_eth_fc_conf *fc_conf);
 210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 211                 struct rte_eth_pfc_conf *pfc_conf);
 212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 213                         struct rte_eth_rss_reta_entry64 *reta_conf,
 214                         uint16_t reta_size);
 215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 216                         struct rte_eth_rss_reta_entry64 *reta_conf,
 217                         uint16_t reta_size);
 218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 224                                       struct rte_intr_handle *handle);
 225 static void ixgbe_dev_interrupt_handler(void *param);
 226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 228                          uint32_t index, uint32_t pool);
 229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 230 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 231                                            struct ether_addr *mac_addr);
 232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 233 static bool is_device_supported(struct rte_eth_dev *dev,
 234                                 struct rte_pci_driver *drv);
 235
 236 /* For Virtual Function support */
 237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 239 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 240 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 242                                    int wait_to_complete);
 243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 245 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 249                 struct rte_eth_stats *stats);
 250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 252                 uint16_t vlan_id, int on);
 253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                 uint16_t queue, int on);
 255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 258                                             uint16_t queue_id);
 259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 260                                              uint16_t queue_id);
 261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 262                                  uint8_t queue, uint8_t msix_vector);
 263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 266
 267 /* For Eth VMDQ APIs support */
 268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 269                 ether_addr * mac_addr, uint8_t on);
 270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 272                 struct rte_eth_mirror_conf *mirror_conf,
 273                 uint8_t rule_id, uint8_t on);
 274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 275                 uint8_t rule_id);
 276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                           uint16_t queue_id);
 278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                            uint16_t queue_id);
 280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                uint8_t queue, uint8_t msix_vector);
 282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 283
 284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 285                                 struct ether_addr *mac_addr,
 286                                 uint32_t index, uint32_t pool);
 287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 288 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 289                                              struct ether_addr *mac_addr);
 290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 291                         struct rte_eth_syn_filter *filter);
 292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 293                         enum rte_filter_op filter_op,
 294                         void *arg);
 295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 296                         struct ixgbe_5tuple_filter *filter);
 297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 298                         struct ixgbe_5tuple_filter *filter);
 299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 300                                 enum rte_filter_op filter_op,
 301                                 void *arg);
 302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 303                         struct rte_eth_ntuple_filter *filter);
 304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 305                                 enum rte_filter_op filter_op,
 306                                 void *arg);
 307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 308                         struct rte_eth_ethertype_filter *filter);
 309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 310                      enum rte_filter_type filter_type,
 311                      enum rte_filter_op filter_op,
 312                      void *arg);
 313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 314
 315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 316                                       struct ether_addr *mc_addr_set,
 317                                       uint32_t nb_mc_addr);
 318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 319                                    struct rte_eth_dcb_info *dcb_info);
 320
 321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 323                             struct rte_dev_reg_info *regs);
 324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 328                                 struct rte_dev_eeprom_info *eeprom);
 329
 330 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 331                                  struct rte_eth_dev_module_info *modinfo);
 332 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 333                                    struct rte_dev_eeprom_info *info);
 334
 335 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 336 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 337                                 struct rte_dev_reg_info *regs);
 338
 339 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 340 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 341 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 342                                             struct timespec *timestamp,
 343                                             uint32_t flags);
 344 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 345                                             struct timespec *timestamp);
 346 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 347 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 348                                    struct timespec *timestamp);
 349 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 350                                    const struct timespec *timestamp);
 351 static void ixgbevf_dev_interrupt_handler(void *param);
 352
 353 static int ixgbe_dev_l2_tunnel_eth_type_conf
 354         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 355 static int ixgbe_dev_l2_tunnel_offload_set
 356         (struct rte_eth_dev *dev,
 357          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 358          uint32_t mask,
 359          uint8_t en);
 360 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 361                                              enum rte_filter_op filter_op,
 362                                              void *arg);
 363
 364 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 365                                          struct rte_eth_udp_tunnel *udp_tunnel);
 366 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 367                                          struct rte_eth_udp_tunnel *udp_tunnel);
 368 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 369 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 370
 371 /*
 372  * Define VF Stats MACRO for Non "cleared on read" register
 373  */
 374 #define UPDATE_VF_STAT(reg, last, cur)                          \
 375 {                                                               \
 376         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 377         cur += (latest - last) & UINT_MAX;                      \
 378         last = latest;                                          \
 379 }
 380
 381 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 382 {                                                                \
 383         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 384         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 385         u64 latest = ((new_msb << 32) | new_lsb);                \
 386         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 387         last = latest;                                           \
 388 }
 389
 390 #define IXGBE_SET_HWSTRIP(h, q) do {\
 391                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 392                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 393                 (h)->bitmap[idx] |= 1 << bit;\
 394         } while (0)
 395
 396 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 397                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 398                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 399                 (h)->bitmap[idx] &= ~(1 << bit);\
 400         } while (0)
 401
 402 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 403                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 404                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 405                 (r) = (h)->bitmap[idx] >> bit & 1;\
 406         } while (0)
 407
 408 int ixgbe_logtype_init;
 409 int ixgbe_logtype_driver;
 410
 411 /*
 412  * The set of PCI devices this driver supports
 413  */
 414 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 463 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 465 #endif
 466         { .vendor_id = 0, /* sentinel */ },
 467 };
 468
 469 /*
 470  * The set of PCI devices this driver supports (for 82599 VF)
 471  */
 472 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 483         { .vendor_id = 0, /* sentinel */ },
 484 };
 485
 486 static const struct rte_eth_desc_lim rx_desc_lim = {
 487         .nb_max = IXGBE_MAX_RING_DESC,
 488         .nb_min = IXGBE_MIN_RING_DESC,
 489         .nb_align = IXGBE_RXD_ALIGN,
 490 };
 491
 492 static const struct rte_eth_desc_lim tx_desc_lim = {
 493         .nb_max = IXGBE_MAX_RING_DESC,
 494         .nb_min = IXGBE_MIN_RING_DESC,
 495         .nb_align = IXGBE_TXD_ALIGN,
 496         .nb_seg_max = IXGBE_TX_MAX_SEG,
 497         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 498 };
 499
 500 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 501         .dev_configure        = ixgbe_dev_configure,
 502         .dev_start            = ixgbe_dev_start,
 503         .dev_stop             = ixgbe_dev_stop,
 504         .dev_set_link_up    = ixgbe_dev_set_link_up,
 505         .dev_set_link_down  = ixgbe_dev_set_link_down,
 506         .dev_close            = ixgbe_dev_close,
 507         .dev_reset            = ixgbe_dev_reset,
 508         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 509         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 510         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 511         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 512         .link_update          = ixgbe_dev_link_update,
 513         .stats_get            = ixgbe_dev_stats_get,
 514         .xstats_get           = ixgbe_dev_xstats_get,
 515         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 516         .stats_reset          = ixgbe_dev_stats_reset,
 517         .xstats_reset         = ixgbe_dev_xstats_reset,
 518         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 519         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 520         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 521         .fw_version_get       = ixgbe_fw_version_get,
 522         .dev_infos_get        = ixgbe_dev_info_get,
 523         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 524         .mtu_set              = ixgbe_dev_mtu_set,
 525         .vlan_filter_set      = ixgbe_vlan_filter_set,
 526         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 527         .vlan_offload_set     = ixgbe_vlan_offload_set,
 528         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 529         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 530         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 531         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 532         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 533         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 534         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 535         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 536         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 537         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 538         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 539         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 540         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 541         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 542         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 543         .dev_led_on           = ixgbe_dev_led_on,
 544         .dev_led_off          = ixgbe_dev_led_off,
 545         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 546         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 547         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 548         .mac_addr_add         = ixgbe_add_rar,
 549         .mac_addr_remove      = ixgbe_remove_rar,
 550         .mac_addr_set         = ixgbe_set_default_mac_addr,
 551         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 552         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 553         .mirror_rule_set      = ixgbe_mirror_rule_set,
 554         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 555         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 556         .reta_update          = ixgbe_dev_rss_reta_update,
 557         .reta_query           = ixgbe_dev_rss_reta_query,
 558         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 559         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 560         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 561         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 562         .rxq_info_get         = ixgbe_rxq_info_get,
 563         .txq_info_get         = ixgbe_txq_info_get,
 564         .timesync_enable      = ixgbe_timesync_enable,
 565         .timesync_disable     = ixgbe_timesync_disable,
 566         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 567         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 568         .get_reg              = ixgbe_get_regs,
 569         .get_eeprom_length    = ixgbe_get_eeprom_length,
 570         .get_eeprom           = ixgbe_get_eeprom,
 571         .set_eeprom           = ixgbe_set_eeprom,
 572         .get_module_info      = ixgbe_get_module_info,
 573         .get_module_eeprom    = ixgbe_get_module_eeprom,
 574         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 575         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 576         .timesync_read_time   = ixgbe_timesync_read_time,
 577         .timesync_write_time  = ixgbe_timesync_write_time,
 578         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 579         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 580         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 581         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 582         .tm_ops_get           = ixgbe_tm_ops_get,
 583 };
 584
 585 /*
 586  * dev_ops for virtual function, bare necessities for basic vf
 587  * operation have been implemented
 588  */
 589 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 590         .dev_configure        = ixgbevf_dev_configure,
 591         .dev_start            = ixgbevf_dev_start,
 592         .dev_stop             = ixgbevf_dev_stop,
 593         .link_update          = ixgbevf_dev_link_update,
 594         .stats_get            = ixgbevf_dev_stats_get,
 595         .xstats_get           = ixgbevf_dev_xstats_get,
 596         .stats_reset          = ixgbevf_dev_stats_reset,
 597         .xstats_reset         = ixgbevf_dev_stats_reset,
 598         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 599         .dev_close            = ixgbevf_dev_close,
 600         .dev_reset            = ixgbevf_dev_reset,
 601         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 602         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 603         .dev_infos_get        = ixgbevf_dev_info_get,
 604         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 605         .mtu_set              = ixgbevf_dev_set_mtu,
 606         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 607         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 608         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 609         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 610         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 611         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 612         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 613         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 614         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 615         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 616         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 617         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 618         .mac_addr_add         = ixgbevf_add_mac_addr,
 619         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 620         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 621         .rxq_info_get         = ixgbe_rxq_info_get,
 622         .txq_info_get         = ixgbe_txq_info_get,
 623         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 624         .get_reg              = ixgbevf_get_regs,
 625         .reta_update          = ixgbe_dev_rss_reta_update,
 626         .reta_query           = ixgbe_dev_rss_reta_query,
 627         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 628         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 629 };
 630
 631 /* store statistics names and its offset in stats structure */
 632 struct rte_ixgbe_xstats_name_off {
 633         char name[RTE_ETH_XSTATS_NAME_SIZE];
 634         unsigned offset;
 635 };
 636
 637 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 638         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 639         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 640         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 641         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 642         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 643         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 644         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 645         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 646         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 647         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 648         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 649         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 650         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 651         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 652         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 653                 prc1023)},
 654         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 655                 prc1522)},
 656         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 657         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 658         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 659         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 660         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 661         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 662         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 663         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 664         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 665         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 666         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 667         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 668         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 669         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 670         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 671         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 672         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 673                 ptc1023)},
 674         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 675                 ptc1522)},
 676         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 677         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 678         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 679         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 680
 681         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 682                 fdirustat_add)},
 683         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 684                 fdirustat_remove)},
 685         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 686                 fdirfstat_fadd)},
 687         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 688                 fdirfstat_fremove)},
 689         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 690                 fdirmatch)},
 691         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 692                 fdirmiss)},
 693
 694         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 695         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 696         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 697                 fclast)},
 698         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 699         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 700         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 701         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 702         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 703                 fcoe_noddp)},
 704         {"rx_fcoe_no_direct_data_placement_ext_buff",
 705                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 706
 707         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 708                 lxontxc)},
 709         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 710                 lxonrxc)},
 711         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 712                 lxofftxc)},
 713         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 714                 lxoffrxc)},
 715         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 716 };
 717
 718 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 719                            sizeof(rte_ixgbe_stats_strings[0]))
 720
 721 /* MACsec statistics */
 722 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 723         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 724                 out_pkts_untagged)},
 725         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 726                 out_pkts_encrypted)},
 727         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 728                 out_pkts_protected)},
 729         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 730                 out_octets_encrypted)},
 731         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 732                 out_octets_protected)},
 733         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 734                 in_pkts_untagged)},
 735         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 736                 in_pkts_badtag)},
 737         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 738                 in_pkts_nosci)},
 739         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 740                 in_pkts_unknownsci)},
 741         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 742                 in_octets_decrypted)},
 743         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 744                 in_octets_validated)},
 745         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 746                 in_pkts_unchecked)},
 747         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 748                 in_pkts_delayed)},
 749         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 750                 in_pkts_late)},
 751         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 752                 in_pkts_ok)},
 753         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_invalid)},
 755         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_notvalid)},
 757         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_unusedsa)},
 759         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_notusingsa)},
 761 };
 762
 763 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 764                            sizeof(rte_ixgbe_macsec_strings[0]))
 765
 766 /* Per-queue statistics */
 767 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 768         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 769         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 770         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 771         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 772 };
 773
 774 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 775                            sizeof(rte_ixgbe_rxq_strings[0]))
 776 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 777
 778 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 779         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 780         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 781         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 782                 pxon2offc)},
 783 };
 784
 785 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 786                            sizeof(rte_ixgbe_txq_strings[0]))
 787 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 788
 789 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 790         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 791 };
 792
 793 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 794                 sizeof(rte_ixgbevf_stats_strings[0]))
 795
 796 /*
 797  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 798  */
 799 static inline int
 800 ixgbe_is_sfp(struct ixgbe_hw *hw)
 801 {
 802         switch (hw->phy.type) {
 803         case ixgbe_phy_sfp_avago:
 804         case ixgbe_phy_sfp_ftl:
 805         case ixgbe_phy_sfp_intel:
 806         case ixgbe_phy_sfp_unknown:
 807         case ixgbe_phy_sfp_passive_tyco:
 808         case ixgbe_phy_sfp_passive_unknown:
 809                 return 1;
 810         default:
 811                 return 0;
 812         }
 813 }
 814
 815 static inline int32_t
 816 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 817 {
 818         uint32_t ctrl_ext;
 819         int32_t status;
 820
 821         status = ixgbe_reset_hw(hw);
 822
 823         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 824         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 825         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 826         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 827         IXGBE_WRITE_FLUSH(hw);
 828
 829         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 830                 status = IXGBE_SUCCESS;
 831         return status;
 832 }
 833
 834 static inline void
 835 ixgbe_enable_intr(struct rte_eth_dev *dev)
 836 {
 837         struct ixgbe_interrupt *intr =
 838                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 839         struct ixgbe_hw *hw =
 840                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 841
 842         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 843         IXGBE_WRITE_FLUSH(hw);
 844 }
 845
 846 /*
 847  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 848  */
 849 static void
 850 ixgbe_disable_intr(struct ixgbe_hw *hw)
 851 {
 852         PMD_INIT_FUNC_TRACE();
 853
 854         if (hw->mac.type == ixgbe_mac_82598EB) {
 855                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 856         } else {
 857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 858                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 859                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 860         }
 861         IXGBE_WRITE_FLUSH(hw);
 862 }
 863
 864 /*
 865  * This function resets queue statistics mapping registers.
 866  * From Niantic datasheet, Initialization of Statistics section:
 867  * "...if software requires the queue counters, the RQSMR and TQSM registers
 868  * must be re-programmed following a device reset.
 869  */
 870 static void
 871 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 872 {
 873         uint32_t i;
 874
 875         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 876                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 877                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 878         }
 879 }
 880
 881
 882 static int
 883 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 884                                   uint16_t queue_id,
 885                                   uint8_t stat_idx,
 886                                   uint8_t is_rx)
 887 {
 888 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 889 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 890 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 891
 892         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 893         struct ixgbe_stat_mapping_registers *stat_mappings =
 894                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 895         uint32_t qsmr_mask = 0;
 896         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 897         uint32_t q_map;
 898         uint8_t n, offset;
 899
 900         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 901                 (hw->mac.type != ixgbe_mac_X540) &&
 902                 (hw->mac.type != ixgbe_mac_X550) &&
 903                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 904                 (hw->mac.type != ixgbe_mac_X550EM_a))
 905                 return -ENOSYS;
 906
 907         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 908                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 909                      queue_id, stat_idx);
 910
 911         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 912         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 913                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 914                 return -EIO;
 915         }
 916         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 917
 918         /* Now clear any previous stat_idx set */
 919         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 920         if (!is_rx)
 921                 stat_mappings->tqsm[n] &= ~clearing_mask;
 922         else
 923                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 924
 925         q_map = (uint32_t)stat_idx;
 926         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 927         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 928         if (!is_rx)
 929                 stat_mappings->tqsm[n] |= qsmr_mask;
 930         else
 931                 stat_mappings->rqsmr[n] |= qsmr_mask;
 932
 933         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 934                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 935                      queue_id, stat_idx);
 936         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 937                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 938
 939         /* Now write the mapping in the appropriate register */
 940         if (is_rx) {
 941                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 942                              stat_mappings->rqsmr[n], n);
 943                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 944         } else {
 945                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 946                              stat_mappings->tqsm[n], n);
 947                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 948         }
 949         return 0;
 950 }
 951
 952 static void
 953 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 954 {
 955         struct ixgbe_stat_mapping_registers *stat_mappings =
 956                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 957         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 958         int i;
 959
 960         /* write whatever was in stat mapping table to the NIC */
 961         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 962                 /* rx */
 963                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 964
 965                 /* tx */
 966                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 967         }
 968 }
 969
 970 static void
 971 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 972 {
 973         uint8_t i;
 974         struct ixgbe_dcb_tc_config *tc;
 975         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 976
 977         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 978         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 979         for (i = 0; i < dcb_max_tc; i++) {
 980                 tc = &dcb_config->tc_config[i];
 981                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 982                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 983                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 984                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 985                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 986                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 987                 tc->pfc = ixgbe_dcb_pfc_disabled;
 988         }
 989
 990         /* Initialize default user to priority mapping, UPx->TC0 */
 991         tc = &dcb_config->tc_config[0];
 992         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 993         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 994         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 995                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 996                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 997         }
 998         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 999         dcb_config->pfc_mode_enable = false;
1000         dcb_config->vt_mode = true;
1001         dcb_config->round_robin_enable = false;
1002         /* support all DCB capabilities in 82599 */
1003         dcb_config->support.capabilities = 0xFF;
1004
1005         /*we only support 4 Tcs for X540, X550 */
1006         if (hw->mac.type == ixgbe_mac_X540 ||
1007                 hw->mac.type == ixgbe_mac_X550 ||
1008                 hw->mac.type == ixgbe_mac_X550EM_x ||
1009                 hw->mac.type == ixgbe_mac_X550EM_a) {
1010                 dcb_config->num_tcs.pg_tcs = 4;
1011                 dcb_config->num_tcs.pfc_tcs = 4;
1012         }
1013 }
1014
1015 /*
1016  * Ensure that all locks are released before first NVM or PHY access
1017  */
1018 static void
1019 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1020 {
1021         uint16_t mask;
1022
1023         /*
1024          * Phy lock should not fail in this early stage. If this is the case,
1025          * it is due to an improper exit of the application.
1026          * So force the release of the faulty lock. Release of common lock
1027          * is done automatically by swfw_sync function.
1028          */
1029         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1030         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1031                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1032         }
1033         ixgbe_release_swfw_semaphore(hw, mask);
1034
1035         /*
1036          * These ones are more tricky since they are common to all ports; but
1037          * swfw_sync retries last long enough (1s) to be almost sure that if
1038          * lock can not be taken it is due to an improper lock of the
1039          * semaphore.
1040          */
1041         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1042         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1043                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1044         }
1045         ixgbe_release_swfw_semaphore(hw, mask);
1046 }
1047
1048 /*
1049  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1050  * It returns 0 on success.
1051  */
1052 static int
1053 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1054 {
1055         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1056         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1057         struct ixgbe_hw *hw =
1058                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1059         struct ixgbe_vfta *shadow_vfta =
1060                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1061         struct ixgbe_hwstrip *hwstrip =
1062                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1063         struct ixgbe_dcb_config *dcb_config =
1064                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1065         struct ixgbe_filter_info *filter_info =
1066                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1067         struct ixgbe_bw_conf *bw_conf =
1068                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1069         uint32_t ctrl_ext;
1070         uint16_t csum;
1071         int diag, i;
1072
1073         PMD_INIT_FUNC_TRACE();
1074
1075         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1076         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1077         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1078         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1079
1080         /*
1081          * For secondary processes, we don't initialise any further as primary
1082          * has already done this work. Only check we don't need a different
1083          * RX and TX function.
1084          */
1085         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1086                 struct ixgbe_tx_queue *txq;
1087                 /* TX queue function in primary, set by last queue initialized
1088                  * Tx queue may not initialized by primary process
1089                  */
1090                 if (eth_dev->data->tx_queues) {
1091                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1092                         ixgbe_set_tx_function(eth_dev, txq);
1093                 } else {
1094                         /* Use default TX function if we get here */
1095                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1096                                      "Using default TX function.");
1097                 }
1098
1099                 ixgbe_set_rx_function(eth_dev);
1100
1101                 return 0;
1102         }
1103
1104         rte_eth_copy_pci_info(eth_dev, pci_dev);
1105
1106         /* Vendor and Device ID need to be set before init of shared code */
1107         hw->device_id = pci_dev->id.device_id;
1108         hw->vendor_id = pci_dev->id.vendor_id;
1109         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1110         hw->allow_unsupported_sfp = 1;
1111
1112         /* Initialize the shared code (base driver) */
1113 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1114         diag = ixgbe_bypass_init_shared_code(hw);
1115 #else
1116         diag = ixgbe_init_shared_code(hw);
1117 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1118
1119         if (diag != IXGBE_SUCCESS) {
1120                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1121                 return -EIO;
1122         }
1123
1124         /* pick up the PCI bus settings for reporting later */
1125         ixgbe_get_bus_info(hw);
1126
1127         /* Unlock any pending hardware semaphore */
1128         ixgbe_swfw_lock_reset(hw);
1129
1130 #ifdef RTE_LIBRTE_SECURITY
1131         /* Initialize security_ctx only for primary process*/
1132         if (ixgbe_ipsec_ctx_create(eth_dev))
1133                 return -ENOMEM;
1134 #endif
1135
1136         /* Initialize DCB configuration*/
1137         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1138         ixgbe_dcb_init(hw, dcb_config);
1139         /* Get Hardware Flow Control setting */
1140         hw->fc.requested_mode = ixgbe_fc_full;
1141         hw->fc.current_mode = ixgbe_fc_full;
1142         hw->fc.pause_time = IXGBE_FC_PAUSE;
1143         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1144                 hw->fc.low_water[i] = IXGBE_FC_LO;
1145                 hw->fc.high_water[i] = IXGBE_FC_HI;
1146         }
1147         hw->fc.send_xon = 1;
1148
1149         /* Make sure we have a good EEPROM before we read from it */
1150         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1151         if (diag != IXGBE_SUCCESS) {
1152                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1153                 return -EIO;
1154         }
1155
1156 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1157         diag = ixgbe_bypass_init_hw(hw);
1158 #else
1159         diag = ixgbe_init_hw(hw);
1160 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1161
1162         /*
1163          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1164          * is called too soon after the kernel driver unbinding/binding occurs.
1165          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1166          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1167          * also called. See ixgbe_identify_phy_82599(). The reason for the
1168          * failure is not known, and only occuts when virtualisation features
1169          * are disabled in the bios. A delay of 100ms  was found to be enough by
1170          * trial-and-error, and is doubled to be safe.
1171          */
1172         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1173                 rte_delay_ms(200);
1174                 diag = ixgbe_init_hw(hw);
1175         }
1176
1177         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1178                 diag = IXGBE_SUCCESS;
1179
1180         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1181                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1182                              "LOM.  Please be aware there may be issues associated "
1183                              "with your hardware.");
1184                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1185                              "please contact your Intel or hardware representative "
1186                              "who provided you with this hardware.");
1187         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1188                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1189         if (diag) {
1190                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1191                 return -EIO;
1192         }
1193
1194         /* Reset the hw statistics */
1195         ixgbe_dev_stats_reset(eth_dev);
1196
1197         /* disable interrupt */
1198         ixgbe_disable_intr(hw);
1199
1200         /* reset mappings for queue statistics hw counters*/
1201         ixgbe_reset_qstat_mappings(hw);
1202
1203         /* Allocate memory for storing MAC addresses */
1204         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1205                                                hw->mac.num_rar_entries, 0);
1206         if (eth_dev->data->mac_addrs == NULL) {
1207                 PMD_INIT_LOG(ERR,
1208                              "Failed to allocate %u bytes needed to store "
1209                              "MAC addresses",
1210                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1211                 return -ENOMEM;
1212         }
1213         /* Copy the permanent MAC address */
1214         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1215                         &eth_dev->data->mac_addrs[0]);
1216
1217         /* Allocate memory for storing hash filter MAC addresses */
1218         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1219                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1220         if (eth_dev->data->hash_mac_addrs == NULL) {
1221                 PMD_INIT_LOG(ERR,
1222                              "Failed to allocate %d bytes needed to store MAC addresses",
1223                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1224                 return -ENOMEM;
1225         }
1226
1227         /* initialize the vfta */
1228         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1229
1230         /* initialize the hw strip bitmap*/
1231         memset(hwstrip, 0, sizeof(*hwstrip));
1232
1233         /* initialize PF if max_vfs not zero */
1234         ixgbe_pf_host_init(eth_dev);
1235
1236         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1237         /* let hardware know driver is loaded */
1238         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1239         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1240         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1241         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1242         IXGBE_WRITE_FLUSH(hw);
1243
1244         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1245                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1246                              (int) hw->mac.type, (int) hw->phy.type,
1247                              (int) hw->phy.sfp_type);
1248         else
1249                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1250                              (int) hw->mac.type, (int) hw->phy.type);
1251
1252         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1253                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1254                      pci_dev->id.device_id);
1255
1256         rte_intr_callback_register(intr_handle,
1257                                    ixgbe_dev_interrupt_handler, eth_dev);
1258
1259         /* enable uio/vfio intr/eventfd mapping */
1260         rte_intr_enable(intr_handle);
1261
1262         /* enable support intr */
1263         ixgbe_enable_intr(eth_dev);
1264
1265         /* initialize filter info */
1266         memset(filter_info, 0,
1267                sizeof(struct ixgbe_filter_info));
1268
1269         /* initialize 5tuple filter list */
1270         TAILQ_INIT(&filter_info->fivetuple_list);
1271
1272         /* initialize flow director filter list & hash */
1273         ixgbe_fdir_filter_init(eth_dev);
1274
1275         /* initialize l2 tunnel filter list & hash */
1276         ixgbe_l2_tn_filter_init(eth_dev);
1277
1278         /* initialize flow filter lists */
1279         ixgbe_filterlist_init();
1280
1281         /* initialize bandwidth configuration info */
1282         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1283
1284         /* initialize Traffic Manager configuration */
1285         ixgbe_tm_conf_init(eth_dev);
1286
1287         return 0;
1288 }
1289
1290 static int
1291 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1292 {
1293         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1294         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1295         struct ixgbe_hw *hw;
1296         int retries = 0;
1297         int ret;
1298
1299         PMD_INIT_FUNC_TRACE();
1300
1301         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1302                 return -EPERM;
1303
1304         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1305
1306         if (hw->adapter_stopped == 0)
1307                 ixgbe_dev_close(eth_dev);
1308
1309         eth_dev->dev_ops = NULL;
1310         eth_dev->rx_pkt_burst = NULL;
1311         eth_dev->tx_pkt_burst = NULL;
1312
1313         /* Unlock any pending hardware semaphore */
1314         ixgbe_swfw_lock_reset(hw);
1315
1316         /* disable uio intr before callback unregister */
1317         rte_intr_disable(intr_handle);
1318
1319         do {
1320                 ret = rte_intr_callback_unregister(intr_handle,
1321                                 ixgbe_dev_interrupt_handler, eth_dev);
1322                 if (ret >= 0) {
1323                         break;
1324                 } else if (ret != -EAGAIN) {
1325                         PMD_INIT_LOG(ERR,
1326                                 "intr callback unregister failed: %d",
1327                                 ret);
1328                         return ret;
1329                 }
1330                 rte_delay_ms(100);
1331         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1332
1333         /* uninitialize PF if max_vfs not zero */
1334         ixgbe_pf_host_uninit(eth_dev);
1335
1336         rte_free(eth_dev->data->mac_addrs);
1337         eth_dev->data->mac_addrs = NULL;
1338
1339         rte_free(eth_dev->data->hash_mac_addrs);
1340         eth_dev->data->hash_mac_addrs = NULL;
1341
1342         /* remove all the fdir filters & hash */
1343         ixgbe_fdir_filter_uninit(eth_dev);
1344
1345         /* remove all the L2 tunnel filters & hash */
1346         ixgbe_l2_tn_filter_uninit(eth_dev);
1347
1348         /* Remove all ntuple filters of the device */
1349         ixgbe_ntuple_filter_uninit(eth_dev);
1350
1351         /* clear all the filters list */
1352         ixgbe_filterlist_flush();
1353
1354         /* Remove all Traffic Manager configuration */
1355         ixgbe_tm_conf_uninit(eth_dev);
1356
1357 #ifdef RTE_LIBRTE_SECURITY
1358         rte_free(eth_dev->security_ctx);
1359 #endif
1360
1361         return 0;
1362 }
1363
1364 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1365 {
1366         struct ixgbe_filter_info *filter_info =
1367                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1368         struct ixgbe_5tuple_filter *p_5tuple;
1369
1370         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1371                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1372                              p_5tuple,
1373                              entries);
1374                 rte_free(p_5tuple);
1375         }
1376         memset(filter_info->fivetuple_mask, 0,
1377                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1378
1379         return 0;
1380 }
1381
1382 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1383 {
1384         struct ixgbe_hw_fdir_info *fdir_info =
1385                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1386         struct ixgbe_fdir_filter *fdir_filter;
1387
1388                 if (fdir_info->hash_map)
1389                 rte_free(fdir_info->hash_map);
1390         if (fdir_info->hash_handle)
1391                 rte_hash_free(fdir_info->hash_handle);
1392
1393         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1394                 TAILQ_REMOVE(&fdir_info->fdir_list,
1395                              fdir_filter,
1396                              entries);
1397                 rte_free(fdir_filter);
1398         }
1399
1400         return 0;
1401 }
1402
1403 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1404 {
1405         struct ixgbe_l2_tn_info *l2_tn_info =
1406                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1407         struct ixgbe_l2_tn_filter *l2_tn_filter;
1408
1409         if (l2_tn_info->hash_map)
1410                 rte_free(l2_tn_info->hash_map);
1411         if (l2_tn_info->hash_handle)
1412                 rte_hash_free(l2_tn_info->hash_handle);
1413
1414         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1415                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1416                              l2_tn_filter,
1417                              entries);
1418                 rte_free(l2_tn_filter);
1419         }
1420
1421         return 0;
1422 }
1423
1424 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1425 {
1426         struct ixgbe_hw_fdir_info *fdir_info =
1427                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1428         char fdir_hash_name[RTE_HASH_NAMESIZE];
1429         struct rte_hash_parameters fdir_hash_params = {
1430                 .name = fdir_hash_name,
1431                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1432                 .key_len = sizeof(union ixgbe_atr_input),
1433                 .hash_func = rte_hash_crc,
1434                 .hash_func_init_val = 0,
1435                 .socket_id = rte_socket_id(),
1436         };
1437
1438         TAILQ_INIT(&fdir_info->fdir_list);
1439         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1440                  "fdir_%s", eth_dev->device->name);
1441         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1442         if (!fdir_info->hash_handle) {
1443                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1444                 return -EINVAL;
1445         }
1446         fdir_info->hash_map = rte_zmalloc("ixgbe",
1447                                           sizeof(struct ixgbe_fdir_filter *) *
1448                                           IXGBE_MAX_FDIR_FILTER_NUM,
1449                                           0);
1450         if (!fdir_info->hash_map) {
1451                 PMD_INIT_LOG(ERR,
1452                              "Failed to allocate memory for fdir hash map!");
1453                 return -ENOMEM;
1454         }
1455         fdir_info->mask_added = FALSE;
1456
1457         return 0;
1458 }
1459
1460 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1461 {
1462         struct ixgbe_l2_tn_info *l2_tn_info =
1463                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1464         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1465         struct rte_hash_parameters l2_tn_hash_params = {
1466                 .name = l2_tn_hash_name,
1467                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1468                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1469                 .hash_func = rte_hash_crc,
1470                 .hash_func_init_val = 0,
1471                 .socket_id = rte_socket_id(),
1472         };
1473
1474         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1475         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1476                  "l2_tn_%s", eth_dev->device->name);
1477         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1478         if (!l2_tn_info->hash_handle) {
1479                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1480                 return -EINVAL;
1481         }
1482         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1483                                    sizeof(struct ixgbe_l2_tn_filter *) *
1484                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1485                                    0);
1486         if (!l2_tn_info->hash_map) {
1487                 PMD_INIT_LOG(ERR,
1488                         "Failed to allocate memory for L2 TN hash map!");
1489                 return -ENOMEM;
1490         }
1491         l2_tn_info->e_tag_en = FALSE;
1492         l2_tn_info->e_tag_fwd_en = FALSE;
1493         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1494
1495         return 0;
1496 }
1497 /*
1498  * Negotiate mailbox API version with the PF.
1499  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1500  * Then we try to negotiate starting with the most recent one.
1501  * If all negotiation attempts fail, then we will proceed with
1502  * the default one (ixgbe_mbox_api_10).
1503  */
1504 static void
1505 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1506 {
1507         int32_t i;
1508
1509         /* start with highest supported, proceed down */
1510         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1511                 ixgbe_mbox_api_12,
1512                 ixgbe_mbox_api_11,
1513                 ixgbe_mbox_api_10,
1514         };
1515
1516         for (i = 0;
1517                         i != RTE_DIM(sup_ver) &&
1518                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1519                         i++)
1520                 ;
1521 }
1522
1523 static void
1524 generate_random_mac_addr(struct ether_addr *mac_addr)
1525 {
1526         uint64_t random;
1527
1528         /* Set Organizationally Unique Identifier (OUI) prefix. */
1529         mac_addr->addr_bytes[0] = 0x00;
1530         mac_addr->addr_bytes[1] = 0x09;
1531         mac_addr->addr_bytes[2] = 0xC0;
1532         /* Force indication of locally assigned MAC address. */
1533         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1534         /* Generate the last 3 bytes of the MAC address with a random number. */
1535         random = rte_rand();
1536         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1537 }
1538
1539 /*
1540  * Virtual Function device init
1541  */
1542 static int
1543 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1544 {
1545         int diag;
1546         uint32_t tc, tcs;
1547         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1549         struct ixgbe_hw *hw =
1550                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1551         struct ixgbe_vfta *shadow_vfta =
1552                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1553         struct ixgbe_hwstrip *hwstrip =
1554                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1555         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1556
1557         PMD_INIT_FUNC_TRACE();
1558
1559         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1560         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1561         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1562
1563         /* for secondary processes, we don't initialise any further as primary
1564          * has already done this work. Only check we don't need a different
1565          * RX function
1566          */
1567         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1568                 struct ixgbe_tx_queue *txq;
1569                 /* TX queue function in primary, set by last queue initialized
1570                  * Tx queue may not initialized by primary process
1571                  */
1572                 if (eth_dev->data->tx_queues) {
1573                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1574                         ixgbe_set_tx_function(eth_dev, txq);
1575                 } else {
1576                         /* Use default TX function if we get here */
1577                         PMD_INIT_LOG(NOTICE,
1578                                      "No TX queues configured yet. Using default TX function.");
1579                 }
1580
1581                 ixgbe_set_rx_function(eth_dev);
1582
1583                 return 0;
1584         }
1585
1586         rte_eth_copy_pci_info(eth_dev, pci_dev);
1587
1588         hw->device_id = pci_dev->id.device_id;
1589         hw->vendor_id = pci_dev->id.vendor_id;
1590         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1591
1592         /* initialize the vfta */
1593         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1594
1595         /* initialize the hw strip bitmap*/
1596         memset(hwstrip, 0, sizeof(*hwstrip));
1597
1598         /* Initialize the shared code (base driver) */
1599         diag = ixgbe_init_shared_code(hw);
1600         if (diag != IXGBE_SUCCESS) {
1601                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1602                 return -EIO;
1603         }
1604
1605         /* init_mailbox_params */
1606         hw->mbx.ops.init_params(hw);
1607
1608         /* Reset the hw statistics */
1609         ixgbevf_dev_stats_reset(eth_dev);
1610
1611         /* Disable the interrupts for VF */
1612         ixgbevf_intr_disable(hw);
1613
1614         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1615         diag = hw->mac.ops.reset_hw(hw);
1616
1617         /*
1618          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1619          * the underlying PF driver has not assigned a MAC address to the VF.
1620          * In this case, assign a random MAC address.
1621          */
1622         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1623                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1624                 return diag;
1625         }
1626
1627         /* negotiate mailbox API version to use with the PF. */
1628         ixgbevf_negotiate_api(hw);
1629
1630         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1631         ixgbevf_get_queues(hw, &tcs, &tc);
1632
1633         /* Allocate memory for storing MAC addresses */
1634         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1635                                                hw->mac.num_rar_entries, 0);
1636         if (eth_dev->data->mac_addrs == NULL) {
1637                 PMD_INIT_LOG(ERR,
1638                              "Failed to allocate %u bytes needed to store "
1639                              "MAC addresses",
1640                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1641                 return -ENOMEM;
1642         }
1643
1644         /* Generate a random MAC address, if none was assigned by PF. */
1645         if (is_zero_ether_addr(perm_addr)) {
1646                 generate_random_mac_addr(perm_addr);
1647                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1648                 if (diag) {
1649                         rte_free(eth_dev->data->mac_addrs);
1650                         eth_dev->data->mac_addrs = NULL;
1651                         return diag;
1652                 }
1653                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1654                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1655                              "%02x:%02x:%02x:%02x:%02x:%02x",
1656                              perm_addr->addr_bytes[0],
1657                              perm_addr->addr_bytes[1],
1658                              perm_addr->addr_bytes[2],
1659                              perm_addr->addr_bytes[3],
1660                              perm_addr->addr_bytes[4],
1661                              perm_addr->addr_bytes[5]);
1662         }
1663
1664         /* Copy the permanent MAC address */
1665         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1666
1667         /* reset the hardware with the new settings */
1668         diag = hw->mac.ops.start_hw(hw);
1669         switch (diag) {
1670         case  0:
1671                 break;
1672
1673         default:
1674                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1675                 return -EIO;
1676         }
1677
1678         rte_intr_callback_register(intr_handle,
1679                                    ixgbevf_dev_interrupt_handler, eth_dev);
1680         rte_intr_enable(intr_handle);
1681         ixgbevf_intr_enable(hw);
1682
1683         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1684                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1685                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1686
1687         return 0;
1688 }
1689
1690 /* Virtual Function device uninit */
1691
1692 static int
1693 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1694 {
1695         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1696         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1697         struct ixgbe_hw *hw;
1698
1699         PMD_INIT_FUNC_TRACE();
1700
1701         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1702                 return -EPERM;
1703
1704         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1705
1706         if (hw->adapter_stopped == 0)
1707                 ixgbevf_dev_close(eth_dev);
1708
1709         eth_dev->dev_ops = NULL;
1710         eth_dev->rx_pkt_burst = NULL;
1711         eth_dev->tx_pkt_burst = NULL;
1712
1713         /* Disable the interrupts for VF */
1714         ixgbevf_intr_disable(hw);
1715
1716         rte_free(eth_dev->data->mac_addrs);
1717         eth_dev->data->mac_addrs = NULL;
1718
1719         rte_intr_disable(intr_handle);
1720         rte_intr_callback_unregister(intr_handle,
1721                                      ixgbevf_dev_interrupt_handler, eth_dev);
1722
1723         return 0;
1724 }
1725
1726 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1727         struct rte_pci_device *pci_dev)
1728 {
1729         return rte_eth_dev_pci_generic_probe(pci_dev,
1730                 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1731 }
1732
1733 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1734 {
1735         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1736 }
1737
1738 static struct rte_pci_driver rte_ixgbe_pmd = {
1739         .id_table = pci_id_ixgbe_map,
1740         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1741                      RTE_PCI_DRV_IOVA_AS_VA,
1742         .probe = eth_ixgbe_pci_probe,
1743         .remove = eth_ixgbe_pci_remove,
1744 };
1745
1746 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1747         struct rte_pci_device *pci_dev)
1748 {
1749         return rte_eth_dev_pci_generic_probe(pci_dev,
1750                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1751 }
1752
1753 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1754 {
1755         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1756 }
1757
1758 /*
1759  * virtual function driver struct
1760  */
1761 static struct rte_pci_driver rte_ixgbevf_pmd = {
1762         .id_table = pci_id_ixgbevf_map,
1763         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1764         .probe = eth_ixgbevf_pci_probe,
1765         .remove = eth_ixgbevf_pci_remove,
1766 };
1767
1768 static int
1769 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1770 {
1771         struct ixgbe_hw *hw =
1772                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773         struct ixgbe_vfta *shadow_vfta =
1774                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1775         uint32_t vfta;
1776         uint32_t vid_idx;
1777         uint32_t vid_bit;
1778
1779         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1780         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1781         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1782         if (on)
1783                 vfta |= vid_bit;
1784         else
1785                 vfta &= ~vid_bit;
1786         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1787
1788         /* update local VFTA copy */
1789         shadow_vfta->vfta[vid_idx] = vfta;
1790
1791         return 0;
1792 }
1793
1794 static void
1795 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1796 {
1797         if (on)
1798                 ixgbe_vlan_hw_strip_enable(dev, queue);
1799         else
1800                 ixgbe_vlan_hw_strip_disable(dev, queue);
1801 }
1802
1803 static int
1804 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1805                     enum rte_vlan_type vlan_type,
1806                     uint16_t tpid)
1807 {
1808         struct ixgbe_hw *hw =
1809                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1810         int ret = 0;
1811         uint32_t reg;
1812         uint32_t qinq;
1813
1814         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1815         qinq &= IXGBE_DMATXCTL_GDV;
1816
1817         switch (vlan_type) {
1818         case ETH_VLAN_TYPE_INNER:
1819                 if (qinq) {
1820                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1821                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1822                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1823                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1824                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1825                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1826                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1827                 } else {
1828                         ret = -ENOTSUP;
1829                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1830                                     " by single VLAN");
1831                 }
1832                 break;
1833         case ETH_VLAN_TYPE_OUTER:
1834                 if (qinq) {
1835                         /* Only the high 16-bits is valid */
1836                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1837                                         IXGBE_EXVET_VET_EXT_SHIFT);
1838                 } else {
1839                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1840                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1841                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1842                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1843                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1844                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1845                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1846                 }
1847
1848                 break;
1849         default:
1850                 ret = -EINVAL;
1851                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1852                 break;
1853         }
1854
1855         return ret;
1856 }
1857
1858 void
1859 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1860 {
1861         struct ixgbe_hw *hw =
1862                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863         uint32_t vlnctrl;
1864
1865         PMD_INIT_FUNC_TRACE();
1866
1867         /* Filter Table Disable */
1868         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1869         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1870
1871         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1872 }
1873
1874 void
1875 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1876 {
1877         struct ixgbe_hw *hw =
1878                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         struct ixgbe_vfta *shadow_vfta =
1880                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1881         uint32_t vlnctrl;
1882         uint16_t i;
1883
1884         PMD_INIT_FUNC_TRACE();
1885
1886         /* Filter Table Enable */
1887         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1888         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1889         vlnctrl |= IXGBE_VLNCTRL_VFE;
1890
1891         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1892
1893         /* write whatever is in local vfta copy */
1894         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1895                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1896 }
1897
1898 static void
1899 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1900 {
1901         struct ixgbe_hwstrip *hwstrip =
1902                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1903         struct ixgbe_rx_queue *rxq;
1904
1905         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1906                 return;
1907
1908         if (on)
1909                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1910         else
1911                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1912
1913         if (queue >= dev->data->nb_rx_queues)
1914                 return;
1915
1916         rxq = dev->data->rx_queues[queue];
1917
1918         if (on)
1919                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1920         else
1921                 rxq->vlan_flags = PKT_RX_VLAN;
1922 }
1923
1924 static void
1925 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1926 {
1927         struct ixgbe_hw *hw =
1928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         uint32_t ctrl;
1930
1931         PMD_INIT_FUNC_TRACE();
1932
1933         if (hw->mac.type == ixgbe_mac_82598EB) {
1934                 /* No queue level support */
1935                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1936                 return;
1937         }
1938
1939         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1940         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1941         ctrl &= ~IXGBE_RXDCTL_VME;
1942         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1943
1944         /* record those setting for HW strip per queue */
1945         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1946 }
1947
1948 static void
1949 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1950 {
1951         struct ixgbe_hw *hw =
1952                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953         uint32_t ctrl;
1954
1955         PMD_INIT_FUNC_TRACE();
1956
1957         if (hw->mac.type == ixgbe_mac_82598EB) {
1958                 /* No queue level supported */
1959                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1960                 return;
1961         }
1962
1963         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1964         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1965         ctrl |= IXGBE_RXDCTL_VME;
1966         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1967
1968         /* record those setting for HW strip per queue */
1969         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1970 }
1971
1972 static void
1973 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1974 {
1975         struct ixgbe_hw *hw =
1976                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1977         uint32_t ctrl;
1978
1979         PMD_INIT_FUNC_TRACE();
1980
1981         /* DMATXCTRL: Geric Double VLAN Disable */
1982         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1983         ctrl &= ~IXGBE_DMATXCTL_GDV;
1984         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1985
1986         /* CTRL_EXT: Global Double VLAN Disable */
1987         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1988         ctrl &= ~IXGBE_EXTENDED_VLAN;
1989         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1990
1991 }
1992
1993 static void
1994 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1995 {
1996         struct ixgbe_hw *hw =
1997                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998         uint32_t ctrl;
1999
2000         PMD_INIT_FUNC_TRACE();
2001
2002         /* DMATXCTRL: Geric Double VLAN Enable */
2003         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2004         ctrl |= IXGBE_DMATXCTL_GDV;
2005         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2006
2007         /* CTRL_EXT: Global Double VLAN Enable */
2008         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2009         ctrl |= IXGBE_EXTENDED_VLAN;
2010         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2011
2012         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2013         if (hw->mac.type == ixgbe_mac_X550 ||
2014             hw->mac.type == ixgbe_mac_X550EM_x ||
2015             hw->mac.type == ixgbe_mac_X550EM_a) {
2016                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2017                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2018                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2019         }
2020
2021         /*
2022          * VET EXT field in the EXVET register = 0x8100 by default
2023          * So no need to change. Same to VT field of DMATXCTL register
2024          */
2025 }
2026
2027 void
2028 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2029 {
2030         struct ixgbe_hw *hw =
2031                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2033         uint32_t ctrl;
2034         uint16_t i;
2035         struct ixgbe_rx_queue *rxq;
2036         bool on;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         if (hw->mac.type == ixgbe_mac_82598EB) {
2041                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2042                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2043                         ctrl |= IXGBE_VLNCTRL_VME;
2044                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2045                 } else {
2046                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2047                         ctrl &= ~IXGBE_VLNCTRL_VME;
2048                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2049                 }
2050         } else {
2051                 /*
2052                  * Other 10G NIC, the VLAN strip can be setup
2053                  * per queue in RXDCTL
2054                  */
2055                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2056                         rxq = dev->data->rx_queues[i];
2057                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2058                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2059                                 ctrl |= IXGBE_RXDCTL_VME;
2060                                 on = TRUE;
2061                         } else {
2062                                 ctrl &= ~IXGBE_RXDCTL_VME;
2063                                 on = FALSE;
2064                         }
2065                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2066
2067                         /* record those setting for HW strip per queue */
2068                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2069                 }
2070         }
2071 }
2072
2073 static int
2074 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2075 {
2076         struct rte_eth_rxmode *rxmode;
2077         rxmode = &dev->data->dev_conf.rxmode;
2078
2079         if (mask & ETH_VLAN_STRIP_MASK) {
2080                 ixgbe_vlan_hw_strip_config(dev);
2081         }
2082
2083         if (mask & ETH_VLAN_FILTER_MASK) {
2084                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2085                         ixgbe_vlan_hw_filter_enable(dev);
2086                 else
2087                         ixgbe_vlan_hw_filter_disable(dev);
2088         }
2089
2090         if (mask & ETH_VLAN_EXTEND_MASK) {
2091                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2092                         ixgbe_vlan_hw_extend_enable(dev);
2093                 else
2094                         ixgbe_vlan_hw_extend_disable(dev);
2095         }
2096
2097         return 0;
2098 }
2099
2100 static void
2101 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2102 {
2103         struct ixgbe_hw *hw =
2104                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2106         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2107
2108         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2109         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2110 }
2111
2112 static int
2113 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2114 {
2115         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2116
2117         switch (nb_rx_q) {
2118         case 1:
2119         case 2:
2120                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2121                 break;
2122         case 4:
2123                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2124                 break;
2125         default:
2126                 return -EINVAL;
2127         }
2128
2129         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2130                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2131         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2132                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2133         return 0;
2134 }
2135
2136 static int
2137 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2138 {
2139         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2141         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2142         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2143
2144         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2145                 /* check multi-queue mode */
2146                 switch (dev_conf->rxmode.mq_mode) {
2147                 case ETH_MQ_RX_VMDQ_DCB:
2148                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2149                         break;
2150                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2151                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2152                         PMD_INIT_LOG(ERR, "SRIOV active,"
2153                                         " unsupported mq_mode rx %d.",
2154                                         dev_conf->rxmode.mq_mode);
2155                         return -EINVAL;
2156                 case ETH_MQ_RX_RSS:
2157                 case ETH_MQ_RX_VMDQ_RSS:
2158                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2159                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2160                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2161                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2162                                                 " invalid queue number"
2163                                                 " for VMDQ RSS, allowed"
2164                                                 " value are 1, 2 or 4.");
2165                                         return -EINVAL;
2166                                 }
2167                         break;
2168                 case ETH_MQ_RX_VMDQ_ONLY:
2169                 case ETH_MQ_RX_NONE:
2170                         /* if nothing mq mode configure, use default scheme */
2171                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2172                         break;
2173                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2174                         /* SRIOV only works in VMDq enable mode */
2175                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2176                                         " wrong mq_mode rx %d.",
2177                                         dev_conf->rxmode.mq_mode);
2178                         return -EINVAL;
2179                 }
2180
2181                 switch (dev_conf->txmode.mq_mode) {
2182                 case ETH_MQ_TX_VMDQ_DCB:
2183                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2184                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2185                         break;
2186                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2187                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2188                         break;
2189                 }
2190
2191                 /* check valid queue number */
2192                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2193                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2194                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2195                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2196                                         " must be less than or equal to %d.",
2197                                         nb_rx_q, nb_tx_q,
2198                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2199                         return -EINVAL;
2200                 }
2201         } else {
2202                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2203                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2204                                           " not supported.");
2205                         return -EINVAL;
2206                 }
2207                 /* check configuration for vmdb+dcb mode */
2208                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2209                         const struct rte_eth_vmdq_dcb_conf *conf;
2210
2211                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2212                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2213                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2214                                 return -EINVAL;
2215                         }
2216                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2217                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2218                                conf->nb_queue_pools == ETH_32_POOLS)) {
2219                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2220                                                 " nb_queue_pools must be %d or %d.",
2221                                                 ETH_16_POOLS, ETH_32_POOLS);
2222                                 return -EINVAL;
2223                         }
2224                 }
2225                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2226                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2227
2228                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2229                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2230                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2231                                 return -EINVAL;
2232                         }
2233                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2234                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2235                                conf->nb_queue_pools == ETH_32_POOLS)) {
2236                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2237                                                 " nb_queue_pools != %d and"
2238                                                 " nb_queue_pools != %d.",
2239                                                 ETH_16_POOLS, ETH_32_POOLS);
2240                                 return -EINVAL;
2241                         }
2242                 }
2243
2244                 /* For DCB mode check our configuration before we go further */
2245                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2246                         const struct rte_eth_dcb_rx_conf *conf;
2247
2248                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2249                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2250                                                  IXGBE_DCB_NB_QUEUES);
2251                                 return -EINVAL;
2252                         }
2253                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2254                         if (!(conf->nb_tcs == ETH_4_TCS ||
2255                                conf->nb_tcs == ETH_8_TCS)) {
2256                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2257                                                 " and nb_tcs != %d.",
2258                                                 ETH_4_TCS, ETH_8_TCS);
2259                                 return -EINVAL;
2260                         }
2261                 }
2262
2263                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2264                         const struct rte_eth_dcb_tx_conf *conf;
2265
2266                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2267                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2268                                                  IXGBE_DCB_NB_QUEUES);
2269                                 return -EINVAL;
2270                         }
2271                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2272                         if (!(conf->nb_tcs == ETH_4_TCS ||
2273                                conf->nb_tcs == ETH_8_TCS)) {
2274                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2275                                                 " and nb_tcs != %d.",
2276                                                 ETH_4_TCS, ETH_8_TCS);
2277                                 return -EINVAL;
2278                         }
2279                 }
2280
2281                 /*
2282                  * When DCB/VT is off, maximum number of queues changes,
2283                  * except for 82598EB, which remains constant.
2284                  */
2285                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2286                                 hw->mac.type != ixgbe_mac_82598EB) {
2287                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2288                                 PMD_INIT_LOG(ERR,
2289                                              "Neither VT nor DCB are enabled, "
2290                                              "nb_tx_q > %d.",
2291                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2292                                 return -EINVAL;
2293                         }
2294                 }
2295         }
2296         return 0;
2297 }
2298
2299 static int
2300 ixgbe_dev_configure(struct rte_eth_dev *dev)
2301 {
2302         struct ixgbe_interrupt *intr =
2303                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2304         struct ixgbe_adapter *adapter =
2305                 (struct ixgbe_adapter *)dev->data->dev_private;
2306         struct rte_eth_dev_info dev_info;
2307         uint64_t rx_offloads;
2308         uint64_t tx_offloads;
2309         int ret;
2310
2311         PMD_INIT_FUNC_TRACE();
2312         /* multipe queue mode checking */
2313         ret  = ixgbe_check_mq_mode(dev);
2314         if (ret != 0) {
2315                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2316                             ret);
2317                 return ret;
2318         }
2319
2320         ixgbe_dev_info_get(dev, &dev_info);
2321         rx_offloads = dev->data->dev_conf.rxmode.offloads;
2322         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2323                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2324                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2325                             rx_offloads, dev_info.rx_offload_capa);
2326                 return -ENOTSUP;
2327         }
2328         tx_offloads = dev->data->dev_conf.txmode.offloads;
2329         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
2330                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
2331                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2332                             tx_offloads, dev_info.tx_offload_capa);
2333                 return -ENOTSUP;
2334         }
2335
2336         /* set flag to update link status after init */
2337         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2338
2339         /*
2340          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2341          * allocation or vector Rx preconditions we will reset it.
2342          */
2343         adapter->rx_bulk_alloc_allowed = true;
2344         adapter->rx_vec_allowed = true;
2345
2346         return 0;
2347 }
2348
2349 static void
2350 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2351 {
2352         struct ixgbe_hw *hw =
2353                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         struct ixgbe_interrupt *intr =
2355                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2356         uint32_t gpie;
2357
2358         /* only set up it on X550EM_X */
2359         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2360                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2361                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2362                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2363                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2364                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2365         }
2366 }
2367
2368 int
2369 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2370                         uint16_t tx_rate, uint64_t q_msk)
2371 {
2372         struct ixgbe_hw *hw;
2373         struct ixgbe_vf_info *vfinfo;
2374         struct rte_eth_link link;
2375         uint8_t  nb_q_per_pool;
2376         uint32_t queue_stride;
2377         uint32_t queue_idx, idx = 0, vf_idx;
2378         uint32_t queue_end;
2379         uint16_t total_rate = 0;
2380         struct rte_pci_device *pci_dev;
2381
2382         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2383         rte_eth_link_get_nowait(dev->data->port_id, &link);
2384
2385         if (vf >= pci_dev->max_vfs)
2386                 return -EINVAL;
2387
2388         if (tx_rate > link.link_speed)
2389                 return -EINVAL;
2390
2391         if (q_msk == 0)
2392                 return 0;
2393
2394         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2396         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2397         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2398         queue_idx = vf * queue_stride;
2399         queue_end = queue_idx + nb_q_per_pool - 1;
2400         if (queue_end >= hw->mac.max_tx_queues)
2401                 return -EINVAL;
2402
2403         if (vfinfo) {
2404                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2405                         if (vf_idx == vf)
2406                                 continue;
2407                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2408                                 idx++)
2409                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2410                 }
2411         } else {
2412                 return -EINVAL;
2413         }
2414
2415         /* Store tx_rate for this vf. */
2416         for (idx = 0; idx < nb_q_per_pool; idx++) {
2417                 if (((uint64_t)0x1 << idx) & q_msk) {
2418                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2419                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2420                         total_rate += tx_rate;
2421                 }
2422         }
2423
2424         if (total_rate > dev->data->dev_link.link_speed) {
2425                 /* Reset stored TX rate of the VF if it causes exceed
2426                  * link speed.
2427                  */
2428                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2429                 return -EINVAL;
2430         }
2431
2432         /* Set RTTBCNRC of each queue/pool for vf X  */
2433         for (; queue_idx <= queue_end; queue_idx++) {
2434                 if (0x1 & q_msk)
2435                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2436                 q_msk = q_msk >> 1;
2437         }
2438
2439         return 0;
2440 }
2441
2442 /*
2443  * Configure device link speed and setup link.
2444  * It returns 0 on success.
2445  */
2446 static int
2447 ixgbe_dev_start(struct rte_eth_dev *dev)
2448 {
2449         struct ixgbe_hw *hw =
2450                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2451         struct ixgbe_vf_info *vfinfo =
2452                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2453         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2454         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2455         uint32_t intr_vector = 0;
2456         int err, link_up = 0, negotiate = 0;
2457         uint32_t speed = 0;
2458         uint32_t allowed_speeds = 0;
2459         int mask = 0;
2460         int status;
2461         uint16_t vf, idx;
2462         uint32_t *link_speeds;
2463         struct ixgbe_tm_conf *tm_conf =
2464                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2465
2466         PMD_INIT_FUNC_TRACE();
2467
2468         /* IXGBE devices don't support:
2469         *    - half duplex (checked afterwards for valid speeds)
2470         *    - fixed speed: TODO implement
2471         */
2472         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2473                 PMD_INIT_LOG(ERR,
2474                 "Invalid link_speeds for port %u, fix speed not supported",
2475                                 dev->data->port_id);
2476                 return -EINVAL;
2477         }
2478
2479         /* disable uio/vfio intr/eventfd mapping */
2480         rte_intr_disable(intr_handle);
2481
2482         /* stop adapter */
2483         hw->adapter_stopped = 0;
2484         ixgbe_stop_adapter(hw);
2485
2486         /* reinitialize adapter
2487          * this calls reset and start
2488          */
2489         status = ixgbe_pf_reset_hw(hw);
2490         if (status != 0)
2491                 return -1;
2492         hw->mac.ops.start_hw(hw);
2493         hw->mac.get_link_status = true;
2494
2495         /* configure PF module if SRIOV enabled */
2496         ixgbe_pf_host_configure(dev);
2497
2498         ixgbe_dev_phy_intr_setup(dev);
2499
2500         /* check and configure queue intr-vector mapping */
2501         if ((rte_intr_cap_multiple(intr_handle) ||
2502              !RTE_ETH_DEV_SRIOV(dev).active) &&
2503             dev->data->dev_conf.intr_conf.rxq != 0) {
2504                 intr_vector = dev->data->nb_rx_queues;
2505                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2506                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2507                                         IXGBE_MAX_INTR_QUEUE_NUM);
2508                         return -ENOTSUP;
2509                 }
2510                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2511                         return -1;
2512         }
2513
2514         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2515                 intr_handle->intr_vec =
2516                         rte_zmalloc("intr_vec",
2517                                     dev->data->nb_rx_queues * sizeof(int), 0);
2518                 if (intr_handle->intr_vec == NULL) {
2519                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2520                                      " intr_vec", dev->data->nb_rx_queues);
2521                         return -ENOMEM;
2522                 }
2523         }
2524
2525         /* confiugre msix for sleep until rx interrupt */
2526         ixgbe_configure_msix(dev);
2527
2528         /* initialize transmission unit */
2529         ixgbe_dev_tx_init(dev);
2530
2531         /* This can fail when allocating mbufs for descriptor rings */
2532         err = ixgbe_dev_rx_init(dev);
2533         if (err) {
2534                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2535                 goto error;
2536         }
2537
2538         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2539                 ETH_VLAN_EXTEND_MASK;
2540         err = ixgbe_vlan_offload_set(dev, mask);
2541         if (err) {
2542                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2543                 goto error;
2544         }
2545
2546         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2547                 /* Enable vlan filtering for VMDq */
2548                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2549         }
2550
2551         /* Configure DCB hw */
2552         ixgbe_configure_dcb(dev);
2553
2554         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2555                 err = ixgbe_fdir_configure(dev);
2556                 if (err)
2557                         goto error;
2558         }
2559
2560         /* Restore vf rate limit */
2561         if (vfinfo != NULL) {
2562                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2563                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2564                                 if (vfinfo[vf].tx_rate[idx] != 0)
2565                                         ixgbe_set_vf_rate_limit(
2566                                                 dev, vf,
2567                                                 vfinfo[vf].tx_rate[idx],
2568                                                 1 << idx);
2569         }
2570
2571         ixgbe_restore_statistics_mapping(dev);
2572
2573         err = ixgbe_dev_rxtx_start(dev);
2574         if (err < 0) {
2575                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2576                 goto error;
2577         }
2578
2579         /* Skip link setup if loopback mode is enabled for 82599. */
2580         if (hw->mac.type == ixgbe_mac_82599EB &&
2581                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2582                 goto skip_link_setup;
2583
2584         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2585                 err = hw->mac.ops.setup_sfp(hw);
2586                 if (err)
2587                         goto error;
2588         }
2589
2590         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2591                 /* Turn on the copper */
2592                 ixgbe_set_phy_power(hw, true);
2593         } else {
2594                 /* Turn on the laser */
2595                 ixgbe_enable_tx_laser(hw);
2596         }
2597
2598         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2599         if (err)
2600                 goto error;
2601         dev->data->dev_link.link_status = link_up;
2602
2603         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2604         if (err)
2605                 goto error;
2606
2607         switch (hw->mac.type) {
2608         case ixgbe_mac_X550:
2609         case ixgbe_mac_X550EM_x:
2610         case ixgbe_mac_X550EM_a:
2611                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2612                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2613                         ETH_LINK_SPEED_10G;
2614                 break;
2615         default:
2616                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2617                         ETH_LINK_SPEED_10G;
2618         }
2619
2620         link_speeds = &dev->data->dev_conf.link_speeds;
2621         if (*link_speeds & ~allowed_speeds) {
2622                 PMD_INIT_LOG(ERR, "Invalid link setting");
2623                 goto error;
2624         }
2625
2626         speed = 0x0;
2627         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2628                 switch (hw->mac.type) {
2629                 case ixgbe_mac_82598EB:
2630                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2631                         break;
2632                 case ixgbe_mac_82599EB:
2633                 case ixgbe_mac_X540:
2634                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2635                         break;
2636                 case ixgbe_mac_X550:
2637                 case ixgbe_mac_X550EM_x:
2638                 case ixgbe_mac_X550EM_a:
2639                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2640                         break;
2641                 default:
2642                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2643                 }
2644         } else {
2645                 if (*link_speeds & ETH_LINK_SPEED_10G)
2646                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2647                 if (*link_speeds & ETH_LINK_SPEED_5G)
2648                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2649                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2650                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2651                 if (*link_speeds & ETH_LINK_SPEED_1G)
2652                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2653                 if (*link_speeds & ETH_LINK_SPEED_100M)
2654                         speed |= IXGBE_LINK_SPEED_100_FULL;
2655         }
2656
2657         err = ixgbe_setup_link(hw, speed, link_up);
2658         if (err)
2659                 goto error;
2660
2661         ixgbe_dev_link_update(dev, 0);
2662
2663 skip_link_setup:
2664
2665         if (rte_intr_allow_others(intr_handle)) {
2666                 /* check if lsc interrupt is enabled */
2667                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2668                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2669                 else
2670                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2671                 ixgbe_dev_macsec_interrupt_setup(dev);
2672         } else {
2673                 rte_intr_callback_unregister(intr_handle,
2674                                              ixgbe_dev_interrupt_handler, dev);
2675                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2676                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2677                                      " no intr multiplex");
2678         }
2679
2680         /* check if rxq interrupt is enabled */
2681         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2682             rte_intr_dp_is_en(intr_handle))
2683                 ixgbe_dev_rxq_interrupt_setup(dev);
2684
2685         /* enable uio/vfio intr/eventfd mapping */
2686         rte_intr_enable(intr_handle);
2687
2688         /* resume enabled intr since hw reset */
2689         ixgbe_enable_intr(dev);
2690         ixgbe_l2_tunnel_conf(dev);
2691         ixgbe_filter_restore(dev);
2692
2693         if (tm_conf->root && !tm_conf->committed)
2694                 PMD_DRV_LOG(WARNING,
2695                             "please call hierarchy_commit() "
2696                             "before starting the port");
2697
2698         return 0;
2699
2700 error:
2701         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2702         ixgbe_dev_clear_queues(dev);
2703         return -EIO;
2704 }
2705
2706 /*
2707  * Stop device: disable rx and tx functions to allow for reconfiguring.
2708  */
2709 static void
2710 ixgbe_dev_stop(struct rte_eth_dev *dev)
2711 {
2712         struct rte_eth_link link;
2713         struct ixgbe_hw *hw =
2714                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2715         struct ixgbe_vf_info *vfinfo =
2716                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2717         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2718         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2719         int vf;
2720         struct ixgbe_tm_conf *tm_conf =
2721                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2722
2723         PMD_INIT_FUNC_TRACE();
2724
2725         /* disable interrupts */
2726         ixgbe_disable_intr(hw);
2727
2728         /* reset the NIC */
2729         ixgbe_pf_reset_hw(hw);
2730         hw->adapter_stopped = 0;
2731
2732         /* stop adapter */
2733         ixgbe_stop_adapter(hw);
2734
2735         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2736                 vfinfo[vf].clear_to_send = false;
2737
2738         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2739                 /* Turn off the copper */
2740                 ixgbe_set_phy_power(hw, false);
2741         } else {
2742                 /* Turn off the laser */
2743                 ixgbe_disable_tx_laser(hw);
2744         }
2745
2746         ixgbe_dev_clear_queues(dev);
2747
2748         /* Clear stored conf */
2749         dev->data->scattered_rx = 0;
2750         dev->data->lro = 0;
2751
2752         /* Clear recorded link status */
2753         memset(&link, 0, sizeof(link));
2754         rte_eth_linkstatus_set(dev, &link);
2755
2756         if (!rte_intr_allow_others(intr_handle))
2757                 /* resume to the default handler */
2758                 rte_intr_callback_register(intr_handle,
2759                                            ixgbe_dev_interrupt_handler,
2760                                            (void *)dev);
2761
2762         /* Clean datapath event and queue/vec mapping */
2763         rte_intr_efd_disable(intr_handle);
2764         if (intr_handle->intr_vec != NULL) {
2765                 rte_free(intr_handle->intr_vec);
2766                 intr_handle->intr_vec = NULL;
2767         }
2768
2769         /* reset hierarchy commit */
2770         tm_conf->committed = false;
2771 }
2772
2773 /*
2774  * Set device link up: enable tx.
2775  */
2776 static int
2777 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2778 {
2779         struct ixgbe_hw *hw =
2780                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2781         if (hw->mac.type == ixgbe_mac_82599EB) {
2782 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2783                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2784                         /* Not suported in bypass mode */
2785                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2786                                      "by device id 0x%x", hw->device_id);
2787                         return -ENOTSUP;
2788                 }
2789 #endif
2790         }
2791
2792         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2793                 /* Turn on the copper */
2794                 ixgbe_set_phy_power(hw, true);
2795         } else {
2796                 /* Turn on the laser */
2797                 ixgbe_enable_tx_laser(hw);
2798         }
2799
2800         return 0;
2801 }
2802
2803 /*
2804  * Set device link down: disable tx.
2805  */
2806 static int
2807 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2808 {
2809         struct ixgbe_hw *hw =
2810                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811         if (hw->mac.type == ixgbe_mac_82599EB) {
2812 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2813                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2814                         /* Not suported in bypass mode */
2815                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2816                                      "by device id 0x%x", hw->device_id);
2817                         return -ENOTSUP;
2818                 }
2819 #endif
2820         }
2821
2822         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2823                 /* Turn off the copper */
2824                 ixgbe_set_phy_power(hw, false);
2825         } else {
2826                 /* Turn off the laser */
2827                 ixgbe_disable_tx_laser(hw);
2828         }
2829
2830         return 0;
2831 }
2832
2833 /*
2834  * Reset and stop device.
2835  */
2836 static void
2837 ixgbe_dev_close(struct rte_eth_dev *dev)
2838 {
2839         struct ixgbe_hw *hw =
2840                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841
2842         PMD_INIT_FUNC_TRACE();
2843
2844         ixgbe_pf_reset_hw(hw);
2845
2846         ixgbe_dev_stop(dev);
2847         hw->adapter_stopped = 1;
2848
2849         ixgbe_dev_free_queues(dev);
2850
2851         ixgbe_disable_pcie_master(hw);
2852
2853         /* reprogram the RAR[0] in case user changed it. */
2854         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2855 }
2856
2857 /*
2858  * Reset PF device.
2859  */
2860 static int
2861 ixgbe_dev_reset(struct rte_eth_dev *dev)
2862 {
2863         int ret;
2864
2865         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2866          * its VF to make them align with it. The detailed notification
2867          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2868          * To avoid unexpected behavior in VF, currently reset of PF with
2869          * SR-IOV activation is not supported. It might be supported later.
2870          */
2871         if (dev->data->sriov.active)
2872                 return -ENOTSUP;
2873
2874         ret = eth_ixgbe_dev_uninit(dev);
2875         if (ret)
2876                 return ret;
2877
2878         ret = eth_ixgbe_dev_init(dev);
2879
2880         return ret;
2881 }
2882
2883 static void
2884 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2885                            struct ixgbe_hw_stats *hw_stats,
2886                            struct ixgbe_macsec_stats *macsec_stats,
2887                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2888                            uint64_t *total_qprc, uint64_t *total_qprdc)
2889 {
2890         uint32_t bprc, lxon, lxoff, total;
2891         uint32_t delta_gprc = 0;
2892         unsigned i;
2893         /* Workaround for RX byte count not including CRC bytes when CRC
2894          * strip is enabled. CRC bytes are removed from counters when crc_strip
2895          * is disabled.
2896          */
2897         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2898                         IXGBE_HLREG0_RXCRCSTRP);
2899
2900         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2901         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2902         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2903         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2904
2905         for (i = 0; i < 8; i++) {
2906                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2907
2908                 /* global total per queue */
2909                 hw_stats->mpc[i] += mp;
2910                 /* Running comprehensive total for stats display */
2911                 *total_missed_rx += hw_stats->mpc[i];
2912                 if (hw->mac.type == ixgbe_mac_82598EB) {
2913                         hw_stats->rnbc[i] +=
2914                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2915                         hw_stats->pxonrxc[i] +=
2916                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2917                         hw_stats->pxoffrxc[i] +=
2918                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2919                 } else {
2920                         hw_stats->pxonrxc[i] +=
2921                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2922                         hw_stats->pxoffrxc[i] +=
2923                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2924                         hw_stats->pxon2offc[i] +=
2925                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2926                 }
2927                 hw_stats->pxontxc[i] +=
2928                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2929                 hw_stats->pxofftxc[i] +=
2930                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2931         }
2932         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2933                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2934                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2935                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2936
2937                 delta_gprc += delta_qprc;
2938
2939                 hw_stats->qprc[i] += delta_qprc;
2940                 hw_stats->qptc[i] += delta_qptc;
2941
2942                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2943                 hw_stats->qbrc[i] +=
2944                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2945                 if (crc_strip == 0)
2946                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2947
2948                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2949                 hw_stats->qbtc[i] +=
2950                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2951
2952                 hw_stats->qprdc[i] += delta_qprdc;
2953                 *total_qprdc += hw_stats->qprdc[i];
2954
2955                 *total_qprc += hw_stats->qprc[i];
2956                 *total_qbrc += hw_stats->qbrc[i];
2957         }
2958         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2959         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2960         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2961
2962         /*
2963          * An errata states that gprc actually counts good + missed packets:
2964          * Workaround to set gprc to summated queue packet receives
2965          */
2966         hw_stats->gprc = *total_qprc;
2967
2968         if (hw->mac.type != ixgbe_mac_82598EB) {
2969                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2970                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2971                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2972                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2973                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2974                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2975                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2976                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2977         } else {
2978                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2979                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2980                 /* 82598 only has a counter in the high register */
2981                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2982                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2983                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2984         }
2985         uint64_t old_tpr = hw_stats->tpr;
2986
2987         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2988         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2989
2990         if (crc_strip == 0)
2991                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2992
2993         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2994         hw_stats->gptc += delta_gptc;
2995         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2996         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2997
2998         /*
2999          * Workaround: mprc hardware is incorrectly counting
3000          * broadcasts, so for now we subtract those.
3001          */
3002         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3003         hw_stats->bprc += bprc;
3004         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3005         if (hw->mac.type == ixgbe_mac_82598EB)
3006                 hw_stats->mprc -= bprc;
3007
3008         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3009         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3010         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3011         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3012         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3013         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3014
3015         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3016         hw_stats->lxontxc += lxon;
3017         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3018         hw_stats->lxofftxc += lxoff;
3019         total = lxon + lxoff;
3020
3021         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3022         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3023         hw_stats->gptc -= total;
3024         hw_stats->mptc -= total;
3025         hw_stats->ptc64 -= total;
3026         hw_stats->gotc -= total * ETHER_MIN_LEN;
3027
3028         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3029         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3030         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3031         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3032         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3033         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3034         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3035         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3036         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3037         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3038         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3039         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3040         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3041         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3042         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3043         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3044         /* Only read FCOE on 82599 */
3045         if (hw->mac.type != ixgbe_mac_82598EB) {
3046                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3047                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3048                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3049                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3050                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3051         }
3052
3053         /* Flow Director Stats registers */
3054         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3055         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3056
3057         /* MACsec Stats registers */
3058         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3059         macsec_stats->out_pkts_encrypted +=
3060                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3061         macsec_stats->out_pkts_protected +=
3062                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3063         macsec_stats->out_octets_encrypted +=
3064                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3065         macsec_stats->out_octets_protected +=
3066                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3067         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3068         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3069         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3070         macsec_stats->in_pkts_unknownsci +=
3071                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3072         macsec_stats->in_octets_decrypted +=
3073                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3074         macsec_stats->in_octets_validated +=
3075                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3076         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3077         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3078         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3079         for (i = 0; i < 2; i++) {
3080                 macsec_stats->in_pkts_ok +=
3081                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3082                 macsec_stats->in_pkts_invalid +=
3083                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3084                 macsec_stats->in_pkts_notvalid +=
3085                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3086         }
3087         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3088         macsec_stats->in_pkts_notusingsa +=
3089                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3090 }
3091
3092 /*
3093  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3094  */
3095 static int
3096 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3097 {
3098         struct ixgbe_hw *hw =
3099                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3100         struct ixgbe_hw_stats *hw_stats =
3101                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3102         struct ixgbe_macsec_stats *macsec_stats =
3103                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3104                                 dev->data->dev_private);
3105         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3106         unsigned i;
3107
3108         total_missed_rx = 0;
3109         total_qbrc = 0;
3110         total_qprc = 0;
3111         total_qprdc = 0;
3112
3113         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3114                         &total_qbrc, &total_qprc, &total_qprdc);
3115
3116         if (stats == NULL)
3117                 return -EINVAL;
3118
3119         /* Fill out the rte_eth_stats statistics structure */
3120         stats->ipackets = total_qprc;
3121         stats->ibytes = total_qbrc;
3122         stats->opackets = hw_stats->gptc;
3123         stats->obytes = hw_stats->gotc;
3124
3125         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3126                 stats->q_ipackets[i] = hw_stats->qprc[i];
3127                 stats->q_opackets[i] = hw_stats->qptc[i];
3128                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3129                 stats->q_obytes[i] = hw_stats->qbtc[i];
3130                 stats->q_errors[i] = hw_stats->qprdc[i];
3131         }
3132
3133         /* Rx Errors */
3134         stats->imissed  = total_missed_rx;
3135         stats->ierrors  = hw_stats->crcerrs +
3136                           hw_stats->mspdc +
3137                           hw_stats->rlec +
3138                           hw_stats->ruc +
3139                           hw_stats->roc +
3140                           hw_stats->illerrc +
3141                           hw_stats->errbc +
3142                           hw_stats->rfc +
3143                           hw_stats->fccrc +
3144                           hw_stats->fclast;
3145
3146         /* Tx Errors */
3147         stats->oerrors  = 0;
3148         return 0;
3149 }
3150
3151 static void
3152 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3153 {
3154         struct ixgbe_hw_stats *stats =
3155                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3156
3157         /* HW registers are cleared on read */
3158         ixgbe_dev_stats_get(dev, NULL);
3159
3160         /* Reset software totals */
3161         memset(stats, 0, sizeof(*stats));
3162 }
3163
3164 /* This function calculates the number of xstats based on the current config */
3165 static unsigned
3166 ixgbe_xstats_calc_num(void) {
3167         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3168                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3169                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3170 }
3171
3172 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3173         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3174 {
3175         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3176         unsigned stat, i, count;
3177
3178         if (xstats_names != NULL) {
3179                 count = 0;
3180
3181                 /* Note: limit >= cnt_stats checked upstream
3182                  * in rte_eth_xstats_names()
3183                  */
3184
3185                 /* Extended stats from ixgbe_hw_stats */
3186                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3187                         snprintf(xstats_names[count].name,
3188                                 sizeof(xstats_names[count].name),
3189                                 "%s",
3190                                 rte_ixgbe_stats_strings[i].name);
3191                         count++;
3192                 }
3193
3194                 /* MACsec Stats */
3195                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3196                         snprintf(xstats_names[count].name,
3197                                 sizeof(xstats_names[count].name),
3198                                 "%s",
3199                                 rte_ixgbe_macsec_strings[i].name);
3200                         count++;
3201                 }
3202
3203                 /* RX Priority Stats */
3204                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3205                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3206                                 snprintf(xstats_names[count].name,
3207                                         sizeof(xstats_names[count].name),
3208                                         "rx_priority%u_%s", i,
3209                                         rte_ixgbe_rxq_strings[stat].name);
3210                                 count++;
3211                         }
3212                 }
3213
3214                 /* TX Priority Stats */
3215                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3216                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3217                                 snprintf(xstats_names[count].name,
3218                                         sizeof(xstats_names[count].name),
3219                                         "tx_priority%u_%s", i,
3220                                         rte_ixgbe_txq_strings[stat].name);
3221                                 count++;
3222                         }
3223                 }
3224         }
3225         return cnt_stats;
3226 }
3227
3228 static int ixgbe_dev_xstats_get_names_by_id(
3229         struct rte_eth_dev *dev,
3230         struct rte_eth_xstat_name *xstats_names,
3231         const uint64_t *ids,
3232         unsigned int limit)
3233 {
3234         if (!ids) {
3235                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3236                 unsigned int stat, i, count;
3237
3238                 if (xstats_names != NULL) {
3239                         count = 0;
3240
3241                         /* Note: limit >= cnt_stats checked upstream
3242                          * in rte_eth_xstats_names()
3243                          */
3244
3245                         /* Extended stats from ixgbe_hw_stats */
3246                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3247                                 snprintf(xstats_names[count].name,
3248                                         sizeof(xstats_names[count].name),
3249                                         "%s",
3250                                         rte_ixgbe_stats_strings[i].name);
3251                                 count++;
3252                         }
3253
3254                         /* MACsec Stats */
3255                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3256                                 snprintf(xstats_names[count].name,
3257                                         sizeof(xstats_names[count].name),
3258                                         "%s",
3259                                         rte_ixgbe_macsec_strings[i].name);
3260                                 count++;
3261                         }
3262
3263                         /* RX Priority Stats */
3264                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3265                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3266                                         snprintf(xstats_names[count].name,
3267                                             sizeof(xstats_names[count].name),
3268                                             "rx_priority%u_%s", i,
3269                                             rte_ixgbe_rxq_strings[stat].name);
3270                                         count++;
3271                                 }
3272                         }
3273
3274                         /* TX Priority Stats */
3275                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3276                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3277                                         snprintf(xstats_names[count].name,
3278                                             sizeof(xstats_names[count].name),
3279                                             "tx_priority%u_%s", i,
3280                                             rte_ixgbe_txq_strings[stat].name);
3281                                         count++;
3282                                 }
3283                         }
3284                 }
3285                 return cnt_stats;
3286         }
3287
3288         uint16_t i;
3289         uint16_t size = ixgbe_xstats_calc_num();
3290         struct rte_eth_xstat_name xstats_names_copy[size];
3291
3292         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3293                         size);
3294
3295         for (i = 0; i < limit; i++) {
3296                 if (ids[i] >= size) {
3297                         PMD_INIT_LOG(ERR, "id value isn't valid");
3298                         return -1;
3299                 }
3300                 strcpy(xstats_names[i].name,
3301                                 xstats_names_copy[ids[i]].name);
3302         }
3303         return limit;
3304 }
3305
3306 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3307         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3308 {
3309         unsigned i;
3310
3311         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3312                 return -ENOMEM;
3313
3314         if (xstats_names != NULL)
3315                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3316                         snprintf(xstats_names[i].name,
3317                                 sizeof(xstats_names[i].name),
3318                                 "%s", rte_ixgbevf_stats_strings[i].name);
3319         return IXGBEVF_NB_XSTATS;
3320 }
3321
3322 static int
3323 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3324                                          unsigned n)
3325 {
3326         struct ixgbe_hw *hw =
3327                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3328         struct ixgbe_hw_stats *hw_stats =
3329                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3330         struct ixgbe_macsec_stats *macsec_stats =
3331                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3332                                 dev->data->dev_private);
3333         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3334         unsigned i, stat, count = 0;
3335
3336         count = ixgbe_xstats_calc_num();
3337
3338         if (n < count)
3339                 return count;
3340
3341         total_missed_rx = 0;
3342         total_qbrc = 0;
3343         total_qprc = 0;
3344         total_qprdc = 0;
3345
3346         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3347                         &total_qbrc, &total_qprc, &total_qprdc);
3348
3349         /* If this is a reset xstats is NULL, and we have cleared the
3350          * registers by reading them.
3351          */
3352         if (!xstats)
3353                 return 0;
3354
3355         /* Extended stats from ixgbe_hw_stats */
3356         count = 0;
3357         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3358                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3359                                 rte_ixgbe_stats_strings[i].offset);
3360                 xstats[count].id = count;
3361                 count++;
3362         }
3363
3364         /* MACsec Stats */
3365         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3366                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3367                                 rte_ixgbe_macsec_strings[i].offset);
3368                 xstats[count].id = count;
3369                 count++;
3370         }
3371
3372         /* RX Priority Stats */
3373         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3374                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3375                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3376                                         rte_ixgbe_rxq_strings[stat].offset +
3377                                         (sizeof(uint64_t) * i));
3378                         xstats[count].id = count;
3379                         count++;
3380                 }
3381         }
3382
3383         /* TX Priority Stats */
3384         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3385                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3386                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3387                                         rte_ixgbe_txq_strings[stat].offset +
3388                                         (sizeof(uint64_t) * i));
3389                         xstats[count].id = count;
3390                         count++;
3391                 }
3392         }
3393         return count;
3394 }
3395
3396 static int
3397 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3398                 uint64_t *values, unsigned int n)
3399 {
3400         if (!ids) {
3401                 struct ixgbe_hw *hw =
3402                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3403                 struct ixgbe_hw_stats *hw_stats =
3404                                 IXGBE_DEV_PRIVATE_TO_STATS(
3405                                                 dev->data->dev_private);
3406                 struct ixgbe_macsec_stats *macsec_stats =
3407                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3408                                         dev->data->dev_private);
3409                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3410                 unsigned int i, stat, count = 0;
3411
3412                 count = ixgbe_xstats_calc_num();
3413
3414                 if (!ids && n < count)
3415                         return count;
3416
3417                 total_missed_rx = 0;
3418                 total_qbrc = 0;
3419                 total_qprc = 0;
3420                 total_qprdc = 0;
3421
3422                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3423                                 &total_missed_rx, &total_qbrc, &total_qprc,
3424                                 &total_qprdc);
3425
3426                 /* If this is a reset xstats is NULL, and we have cleared the
3427                  * registers by reading them.
3428                  */
3429                 if (!ids && !values)
3430                         return 0;
3431
3432                 /* Extended stats from ixgbe_hw_stats */
3433                 count = 0;
3434                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3435                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3436                                         rte_ixgbe_stats_strings[i].offset);
3437                         count++;
3438                 }
3439
3440                 /* MACsec Stats */
3441                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3442                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3443                                         rte_ixgbe_macsec_strings[i].offset);
3444                         count++;
3445                 }
3446
3447                 /* RX Priority Stats */
3448                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3449                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3450                                 values[count] =
3451                                         *(uint64_t *)(((char *)hw_stats) +
3452                                         rte_ixgbe_rxq_strings[stat].offset +
3453                                         (sizeof(uint64_t) * i));
3454                                 count++;
3455                         }
3456                 }
3457
3458                 /* TX Priority Stats */
3459                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3460                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3461                                 values[count] =
3462                                         *(uint64_t *)(((char *)hw_stats) +
3463                                         rte_ixgbe_txq_strings[stat].offset +
3464                                         (sizeof(uint64_t) * i));
3465                                 count++;
3466                         }
3467                 }
3468                 return count;
3469         }
3470
3471         uint16_t i;
3472         uint16_t size = ixgbe_xstats_calc_num();
3473         uint64_t values_copy[size];
3474
3475         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3476
3477         for (i = 0; i < n; i++) {
3478                 if (ids[i] >= size) {
3479                         PMD_INIT_LOG(ERR, "id value isn't valid");
3480                         return -1;
3481                 }
3482                 values[i] = values_copy[ids[i]];
3483         }
3484         return n;
3485 }
3486
3487 static void
3488 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3489 {
3490         struct ixgbe_hw_stats *stats =
3491                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3492         struct ixgbe_macsec_stats *macsec_stats =
3493                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3494                                 dev->data->dev_private);
3495
3496         unsigned count = ixgbe_xstats_calc_num();
3497
3498         /* HW registers are cleared on read */
3499         ixgbe_dev_xstats_get(dev, NULL, count);
3500
3501         /* Reset software totals */
3502         memset(stats, 0, sizeof(*stats));
3503         memset(macsec_stats, 0, sizeof(*macsec_stats));
3504 }
3505
3506 static void
3507 ixgbevf_update_stats(struct rte_eth_dev *dev)
3508 {
3509         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3511                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3512
3513         /* Good Rx packet, include VF loopback */
3514         UPDATE_VF_STAT(IXGBE_VFGPRC,
3515             hw_stats->last_vfgprc, hw_stats->vfgprc);
3516
3517         /* Good Rx octets, include VF loopback */
3518         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3519             hw_stats->last_vfgorc, hw_stats->vfgorc);
3520
3521         /* Good Tx packet, include VF loopback */
3522         UPDATE_VF_STAT(IXGBE_VFGPTC,
3523             hw_stats->last_vfgptc, hw_stats->vfgptc);
3524
3525         /* Good Tx octets, include VF loopback */
3526         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3527             hw_stats->last_vfgotc, hw_stats->vfgotc);
3528
3529         /* Rx Multicst Packet */
3530         UPDATE_VF_STAT(IXGBE_VFMPRC,
3531             hw_stats->last_vfmprc, hw_stats->vfmprc);
3532 }
3533
3534 static int
3535 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3536                        unsigned n)
3537 {
3538         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3539                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3540         unsigned i;
3541
3542         if (n < IXGBEVF_NB_XSTATS)
3543                 return IXGBEVF_NB_XSTATS;
3544
3545         ixgbevf_update_stats(dev);
3546
3547         if (!xstats)
3548                 return 0;
3549
3550         /* Extended stats */
3551         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3552                 xstats[i].id = i;
3553                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3554                         rte_ixgbevf_stats_strings[i].offset);
3555         }
3556
3557         return IXGBEVF_NB_XSTATS;
3558 }
3559
3560 static int
3561 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3562 {
3563         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3564                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3565
3566         ixgbevf_update_stats(dev);
3567
3568         if (stats == NULL)
3569                 return -EINVAL;
3570
3571         stats->ipackets = hw_stats->vfgprc;
3572         stats->ibytes = hw_stats->vfgorc;
3573         stats->opackets = hw_stats->vfgptc;
3574         stats->obytes = hw_stats->vfgotc;
3575         return 0;
3576 }
3577
3578 static void
3579 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3580 {
3581         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3582                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3583
3584         /* Sync HW register to the last stats */
3585         ixgbevf_dev_stats_get(dev, NULL);
3586
3587         /* reset HW current stats*/
3588         hw_stats->vfgprc = 0;
3589         hw_stats->vfgorc = 0;
3590         hw_stats->vfgptc = 0;
3591         hw_stats->vfgotc = 0;
3592 }
3593
3594 static int
3595 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3596 {
3597         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598         u16 eeprom_verh, eeprom_verl;
3599         u32 etrack_id;
3600         int ret;
3601
3602         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3603         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3604
3605         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3606         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3607
3608         ret += 1; /* add the size of '\0' */
3609         if (fw_size < (u32)ret)
3610                 return ret;
3611         else
3612                 return 0;
3613 }
3614
3615 static void
3616 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3617 {
3618         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3621
3622         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3623         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3624         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3625                 /*
3626                  * When DCB/VT is off, maximum number of queues changes,
3627                  * except for 82598EB, which remains constant.
3628                  */
3629                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3630                                 hw->mac.type != ixgbe_mac_82598EB)
3631                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3632         }
3633         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3634         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3635         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3636         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3637         dev_info->max_vfs = pci_dev->max_vfs;
3638         if (hw->mac.type == ixgbe_mac_82598EB)
3639                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3640         else
3641                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3642         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3643         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3644         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3645                                      dev_info->rx_queue_offload_capa);
3646         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3647         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3648
3649         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3650                 .rx_thresh = {
3651                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3652                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3653                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3654                 },
3655                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3656                 .rx_drop_en = 0,
3657                 .offloads = 0,
3658         };
3659
3660         dev_info->default_txconf = (struct rte_eth_txconf) {
3661                 .tx_thresh = {
3662                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3663                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3664                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3665                 },
3666                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3667                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3668                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3669                              ETH_TXQ_FLAGS_NOOFFLOADS |
3670                              ETH_TXQ_FLAGS_IGNORE,
3671                 .offloads = 0,
3672         };
3673
3674         dev_info->rx_desc_lim = rx_desc_lim;
3675         dev_info->tx_desc_lim = tx_desc_lim;
3676
3677         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3678         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3679         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3680
3681         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3682         if (hw->mac.type == ixgbe_mac_X540 ||
3683             hw->mac.type == ixgbe_mac_X540_vf ||
3684             hw->mac.type == ixgbe_mac_X550 ||
3685             hw->mac.type == ixgbe_mac_X550_vf) {
3686                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3687         }
3688         if (hw->mac.type == ixgbe_mac_X550) {
3689                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3690                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3691         }
3692 }
3693
3694 static const uint32_t *
3695 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3696 {
3697         static const uint32_t ptypes[] = {
3698                 /* For non-vec functions,
3699                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3700                  * for vec functions,
3701                  * refers to _recv_raw_pkts_vec().
3702                  */
3703                 RTE_PTYPE_L2_ETHER,
3704                 RTE_PTYPE_L3_IPV4,
3705                 RTE_PTYPE_L3_IPV4_EXT,
3706                 RTE_PTYPE_L3_IPV6,
3707                 RTE_PTYPE_L3_IPV6_EXT,
3708                 RTE_PTYPE_L4_SCTP,
3709                 RTE_PTYPE_L4_TCP,
3710                 RTE_PTYPE_L4_UDP,
3711                 RTE_PTYPE_TUNNEL_IP,
3712                 RTE_PTYPE_INNER_L3_IPV6,
3713                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3714                 RTE_PTYPE_INNER_L4_TCP,
3715                 RTE_PTYPE_INNER_L4_UDP,
3716                 RTE_PTYPE_UNKNOWN
3717         };
3718
3719         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3720             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3721             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3722             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3723                 return ptypes;
3724
3725 #if defined(RTE_ARCH_X86)
3726         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3727             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3728                 return ptypes;
3729 #endif
3730         return NULL;
3731 }
3732
3733 static void
3734 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3735                      struct rte_eth_dev_info *dev_info)
3736 {
3737         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3738         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3739
3740         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3741         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3742         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3743         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3744         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3745         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3746         dev_info->max_vfs = pci_dev->max_vfs;
3747         if (hw->mac.type == ixgbe_mac_82598EB)
3748                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3749         else
3750                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3751         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3752         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3753                                      dev_info->rx_queue_offload_capa);
3754         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3755         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3756
3757         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3758                 .rx_thresh = {
3759                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3760                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3761                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3762                 },
3763                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3764                 .rx_drop_en = 0,
3765                 .offloads = 0,
3766         };
3767
3768         dev_info->default_txconf = (struct rte_eth_txconf) {
3769                 .tx_thresh = {
3770                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3771                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3772                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3773                 },
3774                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3775                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3776                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3777                              ETH_TXQ_FLAGS_NOOFFLOADS |
3778                              ETH_TXQ_FLAGS_IGNORE,
3779                 .offloads = 0,
3780         };
3781
3782         dev_info->rx_desc_lim = rx_desc_lim;
3783         dev_info->tx_desc_lim = tx_desc_lim;
3784 }
3785
3786 static int
3787 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3788                    int *link_up, int wait_to_complete)
3789 {
3790         /**
3791          * for a quick link status checking, wait_to_compelet == 0,
3792          * skip PF link status checking
3793          */
3794         bool no_pflink_check = wait_to_complete == 0;
3795         struct ixgbe_mbx_info *mbx = &hw->mbx;
3796         struct ixgbe_mac_info *mac = &hw->mac;
3797         uint32_t links_reg, in_msg;
3798         int ret_val = 0;
3799
3800         /* If we were hit with a reset drop the link */
3801         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3802                 mac->get_link_status = true;
3803
3804         if (!mac->get_link_status)
3805                 goto out;
3806
3807         /* if link status is down no point in checking to see if pf is up */
3808         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3809         if (!(links_reg & IXGBE_LINKS_UP))
3810                 goto out;
3811
3812         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3813          * before the link status is correct
3814          */
3815         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3816                 int i;
3817
3818                 for (i = 0; i < 5; i++) {
3819                         rte_delay_us(100);
3820                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3821
3822                         if (!(links_reg & IXGBE_LINKS_UP))
3823                                 goto out;
3824                 }
3825         }
3826
3827         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3828         case IXGBE_LINKS_SPEED_10G_82599:
3829                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3830                 if (hw->mac.type >= ixgbe_mac_X550) {
3831                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3832                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3833                 }
3834                 break;
3835         case IXGBE_LINKS_SPEED_1G_82599:
3836                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3837                 break;
3838         case IXGBE_LINKS_SPEED_100_82599:
3839                 *speed = IXGBE_LINK_SPEED_100_FULL;
3840                 if (hw->mac.type == ixgbe_mac_X550) {
3841                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3842                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3843                 }
3844                 break;
3845         case IXGBE_LINKS_SPEED_10_X550EM_A:
3846                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3847                 /* Since Reserved in older MAC's */
3848                 if (hw->mac.type >= ixgbe_mac_X550)
3849                         *speed = IXGBE_LINK_SPEED_10_FULL;
3850                 break;
3851         default:
3852                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3853         }
3854
3855         if (no_pflink_check) {
3856                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3857                         mac->get_link_status = true;
3858                 else
3859                         mac->get_link_status = false;
3860
3861                 goto out;
3862         }
3863         /* if the read failed it could just be a mailbox collision, best wait
3864          * until we are called again and don't report an error
3865          */
3866         if (mbx->ops.read(hw, &in_msg, 1, 0))
3867                 goto out;
3868
3869         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3870                 /* msg is not CTS and is NACK we must have lost CTS status */
3871                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3872                         ret_val = -1;
3873                 goto out;
3874         }
3875
3876         /* the pf is talking, if we timed out in the past we reinit */
3877         if (!mbx->timeout) {
3878                 ret_val = -1;
3879                 goto out;
3880         }
3881
3882         /* if we passed all the tests above then the link is up and we no
3883          * longer need to check for link
3884          */
3885         mac->get_link_status = false;
3886
3887 out:
3888         *link_up = !mac->get_link_status;
3889         return ret_val;
3890 }
3891
3892 /* return 0 means link status changed, -1 means not changed */
3893 static int
3894 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3895                             int wait_to_complete, int vf)
3896 {
3897         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3898         struct rte_eth_link link;
3899         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3900         struct ixgbe_interrupt *intr =
3901                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3902         int link_up;
3903         int diag;
3904         u32 speed = 0;
3905         int wait = 1;
3906         bool autoneg = false;
3907
3908         memset(&link, 0, sizeof(link));
3909         link.link_status = ETH_LINK_DOWN;
3910         link.link_speed = ETH_SPEED_NUM_NONE;
3911         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3912         link.link_autoneg = ETH_LINK_AUTONEG;
3913
3914         hw->mac.get_link_status = true;
3915
3916         if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3917                 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3918                 speed = hw->phy.autoneg_advertised;
3919                 if (!speed)
3920                         ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3921                 ixgbe_setup_link(hw, speed, true);
3922         }
3923
3924         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3925         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3926                 wait = 0;
3927
3928         if (vf)
3929                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3930         else
3931                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3932
3933         if (diag != 0) {
3934                 link.link_speed = ETH_SPEED_NUM_100M;
3935                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3936                 return rte_eth_linkstatus_set(dev, &link);
3937         }
3938
3939         if (link_up == 0) {
3940                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3941                 return rte_eth_linkstatus_set(dev, &link);
3942         }
3943
3944         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3945         link.link_status = ETH_LINK_UP;
3946         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3947
3948         switch (link_speed) {
3949         default:
3950         case IXGBE_LINK_SPEED_UNKNOWN:
3951                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3952                 link.link_speed = ETH_SPEED_NUM_100M;
3953                 break;
3954
3955         case IXGBE_LINK_SPEED_100_FULL:
3956                 link.link_speed = ETH_SPEED_NUM_100M;
3957                 break;
3958
3959         case IXGBE_LINK_SPEED_1GB_FULL:
3960                 link.link_speed = ETH_SPEED_NUM_1G;
3961                 break;
3962
3963         case IXGBE_LINK_SPEED_2_5GB_FULL:
3964                 link.link_speed = ETH_SPEED_NUM_2_5G;
3965                 break;
3966
3967         case IXGBE_LINK_SPEED_5GB_FULL:
3968                 link.link_speed = ETH_SPEED_NUM_5G;
3969                 break;
3970
3971         case IXGBE_LINK_SPEED_10GB_FULL:
3972                 link.link_speed = ETH_SPEED_NUM_10G;
3973                 break;
3974         }
3975
3976         return rte_eth_linkstatus_set(dev, &link);
3977 }
3978
3979 static int
3980 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3981 {
3982         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3983 }
3984
3985 static int
3986 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3987 {
3988         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3989 }
3990
3991 static void
3992 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3993 {
3994         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3995         uint32_t fctrl;
3996
3997         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3998         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3999         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4000 }
4001
4002 static void
4003 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4004 {
4005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4006         uint32_t fctrl;
4007
4008         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4009         fctrl &= (~IXGBE_FCTRL_UPE);
4010         if (dev->data->all_multicast == 1)
4011                 fctrl |= IXGBE_FCTRL_MPE;
4012         else
4013                 fctrl &= (~IXGBE_FCTRL_MPE);
4014         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4015 }
4016
4017 static void
4018 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4019 {
4020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4021         uint32_t fctrl;
4022
4023         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4024         fctrl |= IXGBE_FCTRL_MPE;
4025         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4026 }
4027
4028 static void
4029 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4030 {
4031         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4032         uint32_t fctrl;
4033
4034         if (dev->data->promiscuous == 1)
4035                 return; /* must remain in all_multicast mode */
4036
4037         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4038         fctrl &= (~IXGBE_FCTRL_MPE);
4039         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4040 }
4041
4042 /**
4043  * It clears the interrupt causes and enables the interrupt.
4044  * It will be called once only during nic initialized.
4045  *
4046  * @param dev
4047  *  Pointer to struct rte_eth_dev.
4048  * @param on
4049  *  Enable or Disable.
4050  *
4051  * @return
4052  *  - On success, zero.
4053  *  - On failure, a negative value.
4054  */
4055 static int
4056 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4057 {
4058         struct ixgbe_interrupt *intr =
4059                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4060
4061         ixgbe_dev_link_status_print(dev);
4062         if (on)
4063                 intr->mask |= IXGBE_EICR_LSC;
4064         else
4065                 intr->mask &= ~IXGBE_EICR_LSC;
4066
4067         return 0;
4068 }
4069
4070 /**
4071  * It clears the interrupt causes and enables the interrupt.
4072  * It will be called once only during nic initialized.
4073  *
4074  * @param dev
4075  *  Pointer to struct rte_eth_dev.
4076  *
4077  * @return
4078  *  - On success, zero.
4079  *  - On failure, a negative value.
4080  */
4081 static int
4082 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4083 {
4084         struct ixgbe_interrupt *intr =
4085                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4086
4087         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4088
4089         return 0;
4090 }
4091
4092 /**
4093  * It clears the interrupt causes and enables the interrupt.
4094  * It will be called once only during nic initialized.
4095  *
4096  * @param dev
4097  *  Pointer to struct rte_eth_dev.
4098  *
4099  * @return
4100  *  - On success, zero.
4101  *  - On failure, a negative value.
4102  */
4103 static int
4104 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4105 {
4106         struct ixgbe_interrupt *intr =
4107                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4108
4109         intr->mask |= IXGBE_EICR_LINKSEC;
4110
4111         return 0;
4112 }
4113
4114 /*
4115  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4116  *
4117  * @param dev
4118  *  Pointer to struct rte_eth_dev.
4119  *
4120  * @return
4121  *  - On success, zero.
4122  *  - On failure, a negative value.
4123  */
4124 static int
4125 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4126 {
4127         uint32_t eicr;
4128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         struct ixgbe_interrupt *intr =
4130                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4131
4132         /* clear all cause mask */
4133         ixgbe_disable_intr(hw);
4134
4135         /* read-on-clear nic registers here */
4136         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4137         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4138
4139         intr->flags = 0;
4140
4141         /* set flag for async link update */
4142         if (eicr & IXGBE_EICR_LSC)
4143                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4144
4145         if (eicr & IXGBE_EICR_MAILBOX)
4146                 intr->flags |= IXGBE_FLAG_MAILBOX;
4147
4148         if (eicr & IXGBE_EICR_LINKSEC)
4149                 intr->flags |= IXGBE_FLAG_MACSEC;
4150
4151         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4152             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4153             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4154                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4155
4156         return 0;
4157 }
4158
4159 /**
4160  * It gets and then prints the link status.
4161  *
4162  * @param dev
4163  *  Pointer to struct rte_eth_dev.
4164  *
4165  * @return
4166  *  - On success, zero.
4167  *  - On failure, a negative value.
4168  */
4169 static void
4170 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4171 {
4172         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4173         struct rte_eth_link link;
4174
4175         rte_eth_linkstatus_get(dev, &link);
4176
4177         if (link.link_status) {
4178                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4179                                         (int)(dev->data->port_id),
4180                                         (unsigned)link.link_speed,
4181                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4182                                         "full-duplex" : "half-duplex");
4183         } else {
4184                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4185                                 (int)(dev->data->port_id));
4186         }
4187         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4188                                 pci_dev->addr.domain,
4189                                 pci_dev->addr.bus,
4190                                 pci_dev->addr.devid,
4191                                 pci_dev->addr.function);
4192 }
4193
4194 /*
4195  * It executes link_update after knowing an interrupt occurred.
4196  *
4197  * @param dev
4198  *  Pointer to struct rte_eth_dev.
4199  *
4200  * @return
4201  *  - On success, zero.
4202  *  - On failure, a negative value.
4203  */
4204 static int
4205 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4206                            struct rte_intr_handle *intr_handle)
4207 {
4208         struct ixgbe_interrupt *intr =
4209                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4210         int64_t timeout;
4211         struct ixgbe_hw *hw =
4212                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213
4214         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4215
4216         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4217                 ixgbe_pf_mbx_process(dev);
4218                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4219         }
4220
4221         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4222                 ixgbe_handle_lasi(hw);
4223                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4224         }
4225
4226         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4227                 struct rte_eth_link link;
4228
4229                 /* get the link status before link update, for predicting later */
4230                 rte_eth_linkstatus_get(dev, &link);
4231
4232                 ixgbe_dev_link_update(dev, 0);
4233
4234                 /* likely to up */
4235                 if (!link.link_status)
4236                         /* handle it 1 sec later, wait it being stable */
4237                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4238                 /* likely to down */
4239                 else
4240                         /* handle it 4 sec later, wait it being stable */
4241                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4242
4243                 ixgbe_dev_link_status_print(dev);
4244                 if (rte_eal_alarm_set(timeout * 1000,
4245                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4246                         PMD_DRV_LOG(ERR, "Error setting alarm");
4247                 else {
4248                         /* remember original mask */
4249                         intr->mask_original = intr->mask;
4250                         /* only disable lsc interrupt */
4251                         intr->mask &= ~IXGBE_EIMS_LSC;
4252                 }
4253         }
4254
4255         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4256         ixgbe_enable_intr(dev);
4257         rte_intr_enable(intr_handle);
4258
4259         return 0;
4260 }
4261
4262 /**
4263  * Interrupt handler which shall be registered for alarm callback for delayed
4264  * handling specific interrupt to wait for the stable nic state. As the
4265  * NIC interrupt state is not stable for ixgbe after link is just down,
4266  * it needs to wait 4 seconds to get the stable status.
4267  *
4268  * @param handle
4269  *  Pointer to interrupt handle.
4270  * @param param
4271  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4272  *
4273  * @return
4274  *  void
4275  */
4276 static void
4277 ixgbe_dev_interrupt_delayed_handler(void *param)
4278 {
4279         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4281         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4282         struct ixgbe_interrupt *intr =
4283                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4284         struct ixgbe_hw *hw =
4285                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4286         uint32_t eicr;
4287
4288         ixgbe_disable_intr(hw);
4289
4290         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4291         if (eicr & IXGBE_EICR_MAILBOX)
4292                 ixgbe_pf_mbx_process(dev);
4293
4294         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4295                 ixgbe_handle_lasi(hw);
4296                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4297         }
4298
4299         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4300                 ixgbe_dev_link_update(dev, 0);
4301                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4302                 ixgbe_dev_link_status_print(dev);
4303                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4304                                               NULL);
4305         }
4306
4307         if (intr->flags & IXGBE_FLAG_MACSEC) {
4308                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4309                                               NULL);
4310                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4311         }
4312
4313         /* restore original mask */
4314         intr->mask = intr->mask_original;
4315         intr->mask_original = 0;
4316
4317         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4318         ixgbe_enable_intr(dev);
4319         rte_intr_enable(intr_handle);
4320 }
4321
4322 /**
4323  * Interrupt handler triggered by NIC  for handling
4324  * specific interrupt.
4325  *
4326  * @param handle
4327  *  Pointer to interrupt handle.
4328  * @param param
4329  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4330  *
4331  * @return
4332  *  void
4333  */
4334 static void
4335 ixgbe_dev_interrupt_handler(void *param)
4336 {
4337         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4338
4339         ixgbe_dev_interrupt_get_status(dev);
4340         ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4341 }
4342
4343 static int
4344 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4345 {
4346         struct ixgbe_hw *hw;
4347
4348         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4349         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4350 }
4351
4352 static int
4353 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4354 {
4355         struct ixgbe_hw *hw;
4356
4357         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4359 }
4360
4361 static int
4362 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4363 {
4364         struct ixgbe_hw *hw;
4365         uint32_t mflcn_reg;
4366         uint32_t fccfg_reg;
4367         int rx_pause;
4368         int tx_pause;
4369
4370         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371
4372         fc_conf->pause_time = hw->fc.pause_time;
4373         fc_conf->high_water = hw->fc.high_water[0];
4374         fc_conf->low_water = hw->fc.low_water[0];
4375         fc_conf->send_xon = hw->fc.send_xon;
4376         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4377
4378         /*
4379          * Return rx_pause status according to actual setting of
4380          * MFLCN register.
4381          */
4382         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4383         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4384                 rx_pause = 1;
4385         else
4386                 rx_pause = 0;
4387
4388         /*
4389          * Return tx_pause status according to actual setting of
4390          * FCCFG register.
4391          */
4392         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4393         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4394                 tx_pause = 1;
4395         else
4396                 tx_pause = 0;
4397
4398         if (rx_pause && tx_pause)
4399                 fc_conf->mode = RTE_FC_FULL;
4400         else if (rx_pause)
4401                 fc_conf->mode = RTE_FC_RX_PAUSE;
4402         else if (tx_pause)
4403                 fc_conf->mode = RTE_FC_TX_PAUSE;
4404         else
4405                 fc_conf->mode = RTE_FC_NONE;
4406
4407         return 0;
4408 }
4409
4410 static int
4411 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4412 {
4413         struct ixgbe_hw *hw;
4414         int err;
4415         uint32_t rx_buf_size;
4416         uint32_t max_high_water;
4417         uint32_t mflcn;
4418         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4419                 ixgbe_fc_none,
4420                 ixgbe_fc_rx_pause,
4421                 ixgbe_fc_tx_pause,
4422                 ixgbe_fc_full
4423         };
4424
4425         PMD_INIT_FUNC_TRACE();
4426
4427         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4428         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4429         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4430
4431         /*
4432          * At least reserve one Ethernet frame for watermark
4433          * high_water/low_water in kilo bytes for ixgbe
4434          */
4435         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4436         if ((fc_conf->high_water > max_high_water) ||
4437                 (fc_conf->high_water < fc_conf->low_water)) {
4438                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4439                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4440                 return -EINVAL;
4441         }
4442
4443         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4444         hw->fc.pause_time     = fc_conf->pause_time;
4445         hw->fc.high_water[0]  = fc_conf->high_water;
4446         hw->fc.low_water[0]   = fc_conf->low_water;
4447         hw->fc.send_xon       = fc_conf->send_xon;
4448         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4449
4450         err = ixgbe_fc_enable(hw);
4451
4452         /* Not negotiated is not an error case */
4453         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4454
4455                 /* check if we want to forward MAC frames - driver doesn't have native
4456                  * capability to do that, so we'll write the registers ourselves */
4457
4458                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4459
4460                 /* set or clear MFLCN.PMCF bit depending on configuration */
4461                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4462                         mflcn |= IXGBE_MFLCN_PMCF;
4463                 else
4464                         mflcn &= ~IXGBE_MFLCN_PMCF;
4465
4466                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4467                 IXGBE_WRITE_FLUSH(hw);
4468
4469                 return 0;
4470         }
4471
4472         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4473         return -EIO;
4474 }
4475
4476 /**
4477  *  ixgbe_pfc_enable_generic - Enable flow control
4478  *  @hw: pointer to hardware structure
4479  *  @tc_num: traffic class number
4480  *  Enable flow control according to the current settings.
4481  */
4482 static int
4483 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4484 {
4485         int ret_val = 0;
4486         uint32_t mflcn_reg, fccfg_reg;
4487         uint32_t reg;
4488         uint32_t fcrtl, fcrth;
4489         uint8_t i;
4490         uint8_t nb_rx_en;
4491
4492         /* Validate the water mark configuration */
4493         if (!hw->fc.pause_time) {
4494                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4495                 goto out;
4496         }
4497
4498         /* Low water mark of zero causes XOFF floods */
4499         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4500                  /* High/Low water can not be 0 */
4501                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4502                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4503                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4504                         goto out;
4505                 }
4506
4507                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4508                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4509                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4510                         goto out;
4511                 }
4512         }
4513         /* Negotiate the fc mode to use */
4514         ixgbe_fc_autoneg(hw);
4515
4516         /* Disable any previous flow control settings */
4517         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4518         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4519
4520         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4521         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4522
4523         switch (hw->fc.current_mode) {
4524         case ixgbe_fc_none:
4525                 /*
4526                  * If the count of enabled RX Priority Flow control >1,
4527                  * and the TX pause can not be disabled
4528                  */
4529                 nb_rx_en = 0;
4530                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4531                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4532                         if (reg & IXGBE_FCRTH_FCEN)
4533                                 nb_rx_en++;
4534                 }
4535                 if (nb_rx_en > 1)
4536                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4537                 break;
4538         case ixgbe_fc_rx_pause:
4539                 /*
4540                  * Rx Flow control is enabled and Tx Flow control is
4541                  * disabled by software override. Since there really
4542                  * isn't a way to advertise that we are capable of RX
4543                  * Pause ONLY, we will advertise that we support both
4544                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4545                  * disable the adapter's ability to send PAUSE frames.
4546                  */
4547                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4548                 /*
4549                  * If the count of enabled RX Priority Flow control >1,
4550                  * and the TX pause can not be disabled
4551                  */
4552                 nb_rx_en = 0;
4553                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4554                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4555                         if (reg & IXGBE_FCRTH_FCEN)
4556                                 nb_rx_en++;
4557                 }
4558                 if (nb_rx_en > 1)
4559                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4560                 break;
4561         case ixgbe_fc_tx_pause:
4562                 /*
4563                  * Tx Flow control is enabled, and Rx Flow control is
4564                  * disabled by software override.
4565                  */
4566                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4567                 break;
4568         case ixgbe_fc_full:
4569                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4570                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4571                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4572                 break;
4573         default:
4574                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4575                 ret_val = IXGBE_ERR_CONFIG;
4576                 goto out;
4577         }
4578
4579         /* Set 802.3x based flow control settings. */
4580         mflcn_reg |= IXGBE_MFLCN_DPF;
4581         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4582         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4583
4584         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4585         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4586                 hw->fc.high_water[tc_num]) {
4587                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4588                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4589                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4590         } else {
4591                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4592                 /*
4593                  * In order to prevent Tx hangs when the internal Tx
4594                  * switch is enabled we must set the high water mark
4595                  * to the maximum FCRTH value.  This allows the Tx
4596                  * switch to function even under heavy Rx workloads.
4597                  */
4598                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4599         }
4600         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4601
4602         /* Configure pause time (2 TCs per register) */
4603         reg = hw->fc.pause_time * 0x00010001;
4604         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4605                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4606
4607         /* Configure flow control refresh threshold value */
4608         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4609
4610 out:
4611         return ret_val;
4612 }
4613
4614 static int
4615 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4616 {
4617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4618         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4619
4620         if (hw->mac.type != ixgbe_mac_82598EB) {
4621                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4622         }
4623         return ret_val;
4624 }
4625
4626 static int
4627 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4628 {
4629         int err;
4630         uint32_t rx_buf_size;
4631         uint32_t max_high_water;
4632         uint8_t tc_num;
4633         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4634         struct ixgbe_hw *hw =
4635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4636         struct ixgbe_dcb_config *dcb_config =
4637                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4638
4639         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4640                 ixgbe_fc_none,
4641                 ixgbe_fc_rx_pause,
4642                 ixgbe_fc_tx_pause,
4643                 ixgbe_fc_full
4644         };
4645
4646         PMD_INIT_FUNC_TRACE();
4647
4648         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4649         tc_num = map[pfc_conf->priority];
4650         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4651         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4652         /*
4653          * At least reserve one Ethernet frame for watermark
4654          * high_water/low_water in kilo bytes for ixgbe
4655          */
4656         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4657         if ((pfc_conf->fc.high_water > max_high_water) ||
4658             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4659                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4660                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4661                 return -EINVAL;
4662         }
4663
4664         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4665         hw->fc.pause_time = pfc_conf->fc.pause_time;
4666         hw->fc.send_xon = pfc_conf->fc.send_xon;
4667         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4668         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4669
4670         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4671
4672         /* Not negotiated is not an error case */
4673         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4674                 return 0;
4675
4676         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4677         return -EIO;
4678 }
4679
4680 static int
4681 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4682                           struct rte_eth_rss_reta_entry64 *reta_conf,
4683                           uint16_t reta_size)
4684 {
4685         uint16_t i, sp_reta_size;
4686         uint8_t j, mask;
4687         uint32_t reta, r;
4688         uint16_t idx, shift;
4689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4690         uint32_t reta_reg;
4691
4692         PMD_INIT_FUNC_TRACE();
4693
4694         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4695                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4696                         "NIC.");
4697                 return -ENOTSUP;
4698         }
4699
4700         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4701         if (reta_size != sp_reta_size) {
4702                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4703                         "(%d) doesn't match the number hardware can supported "
4704                         "(%d)", reta_size, sp_reta_size);
4705                 return -EINVAL;
4706         }
4707
4708         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4709                 idx = i / RTE_RETA_GROUP_SIZE;
4710                 shift = i % RTE_RETA_GROUP_SIZE;
4711                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4712                                                 IXGBE_4_BIT_MASK);
4713                 if (!mask)
4714                         continue;
4715                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4716                 if (mask == IXGBE_4_BIT_MASK)
4717                         r = 0;
4718                 else
4719                         r = IXGBE_READ_REG(hw, reta_reg);
4720                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4721                         if (mask & (0x1 << j))
4722                                 reta |= reta_conf[idx].reta[shift + j] <<
4723                                                         (CHAR_BIT * j);
4724                         else
4725                                 reta |= r & (IXGBE_8_BIT_MASK <<
4726                                                 (CHAR_BIT * j));
4727                 }
4728                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4729         }
4730
4731         return 0;
4732 }
4733
4734 static int
4735 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4736                          struct rte_eth_rss_reta_entry64 *reta_conf,
4737                          uint16_t reta_size)
4738 {
4739         uint16_t i, sp_reta_size;
4740         uint8_t j, mask;
4741         uint32_t reta;
4742         uint16_t idx, shift;
4743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744         uint32_t reta_reg;
4745
4746         PMD_INIT_FUNC_TRACE();
4747         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4748         if (reta_size != sp_reta_size) {
4749                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4750                         "(%d) doesn't match the number hardware can supported "
4751                         "(%d)", reta_size, sp_reta_size);
4752                 return -EINVAL;
4753         }
4754
4755         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4756                 idx = i / RTE_RETA_GROUP_SIZE;
4757                 shift = i % RTE_RETA_GROUP_SIZE;
4758                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4759                                                 IXGBE_4_BIT_MASK);
4760                 if (!mask)
4761                         continue;
4762
4763                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4764                 reta = IXGBE_READ_REG(hw, reta_reg);
4765                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4766                         if (mask & (0x1 << j))
4767                                 reta_conf[idx].reta[shift + j] =
4768                                         ((reta >> (CHAR_BIT * j)) &
4769                                                 IXGBE_8_BIT_MASK);
4770                 }
4771         }
4772
4773         return 0;
4774 }
4775
4776 static int
4777 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4778                                 uint32_t index, uint32_t pool)
4779 {
4780         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4781         uint32_t enable_addr = 1;
4782
4783         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4784                              pool, enable_addr);
4785 }
4786
4787 static void
4788 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4789 {
4790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791
4792         ixgbe_clear_rar(hw, index);
4793 }
4794
4795 static int
4796 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4797 {
4798         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4799
4800         ixgbe_remove_rar(dev, 0);
4801         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4802
4803         return 0;
4804 }
4805
4806 static bool
4807 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4808 {
4809         if (strcmp(dev->device->driver->name, drv->driver.name))
4810                 return false;
4811
4812         return true;
4813 }
4814
4815 bool
4816 is_ixgbe_supported(struct rte_eth_dev *dev)
4817 {
4818         return is_device_supported(dev, &rte_ixgbe_pmd);
4819 }
4820
4821 static int
4822 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4823 {
4824         uint32_t hlreg0;
4825         uint32_t maxfrs;
4826         struct ixgbe_hw *hw;
4827         struct rte_eth_dev_info dev_info;
4828         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4829         struct rte_eth_dev_data *dev_data = dev->data;
4830
4831         ixgbe_dev_info_get(dev, &dev_info);
4832
4833         /* check that mtu is within the allowed range */
4834         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4835                 return -EINVAL;
4836
4837         /* If device is started, refuse mtu that requires the support of
4838          * scattered packets when this feature has not been enabled before.
4839          */
4840         if (dev_data->dev_started && !dev_data->scattered_rx &&
4841             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4842              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4843                 PMD_INIT_LOG(ERR, "Stop port first.");
4844                 return -EINVAL;
4845         }
4846
4847         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4849
4850         /* switch to jumbo mode if needed */
4851         if (frame_size > ETHER_MAX_LEN) {
4852                 dev->data->dev_conf.rxmode.offloads |=
4853                         DEV_RX_OFFLOAD_JUMBO_FRAME;
4854                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4855         } else {
4856                 dev->data->dev_conf.rxmode.offloads &=
4857                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4858                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4859         }
4860         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4861
4862         /* update max frame size */
4863         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4864
4865         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4866         maxfrs &= 0x0000FFFF;
4867         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4868         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4869
4870         return 0;
4871 }
4872
4873 /*
4874  * Virtual Function operations
4875  */
4876 static void
4877 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4878 {
4879         PMD_INIT_FUNC_TRACE();
4880
4881         /* Clear interrupt mask to stop from interrupts being generated */
4882         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4883
4884         IXGBE_WRITE_FLUSH(hw);
4885 }
4886
4887 static void
4888 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4889 {
4890         PMD_INIT_FUNC_TRACE();
4891
4892         /* VF enable interrupt autoclean */
4893         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4894         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4895         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4896
4897         IXGBE_WRITE_FLUSH(hw);
4898 }
4899
4900 static int
4901 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4902 {
4903         struct rte_eth_conf *conf = &dev->data->dev_conf;
4904         struct ixgbe_adapter *adapter =
4905                         (struct ixgbe_adapter *)dev->data->dev_private;
4906         struct rte_eth_dev_info dev_info;
4907         uint64_t rx_offloads;
4908         uint64_t tx_offloads;
4909
4910         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4911                      dev->data->port_id);
4912
4913         ixgbevf_dev_info_get(dev, &dev_info);
4914         rx_offloads = dev->data->dev_conf.rxmode.offloads;
4915         if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4916                 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4917                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4918                             rx_offloads, dev_info.rx_offload_capa);
4919                 return -ENOTSUP;
4920         }
4921         tx_offloads = dev->data->dev_conf.txmode.offloads;
4922         if ((tx_offloads & dev_info.tx_offload_capa) != tx_offloads) {
4923                 PMD_DRV_LOG(ERR, "Some Tx offloads are not supported "
4924                             "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4925                             tx_offloads, dev_info.tx_offload_capa);
4926                 return -ENOTSUP;
4927         }
4928
4929         /*
4930          * VF has no ability to enable/disable HW CRC
4931          * Keep the persistent behavior the same as Host PF
4932          */
4933 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4934         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4935                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4936                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4937         }
4938 #else
4939         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4940                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4941                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4942         }
4943 #endif
4944
4945         /*
4946          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4947          * allocation or vector Rx preconditions we will reset it.
4948          */
4949         adapter->rx_bulk_alloc_allowed = true;
4950         adapter->rx_vec_allowed = true;
4951
4952         return 0;
4953 }
4954
4955 static int
4956 ixgbevf_dev_start(struct rte_eth_dev *dev)
4957 {
4958         struct ixgbe_hw *hw =
4959                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4960         uint32_t intr_vector = 0;
4961         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4962         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4963
4964         int err, mask = 0;
4965
4966         PMD_INIT_FUNC_TRACE();
4967
4968         err = hw->mac.ops.reset_hw(hw);
4969         if (err) {
4970                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4971                 return err;
4972         }
4973         hw->mac.get_link_status = true;
4974
4975         /* negotiate mailbox API version to use with the PF. */
4976         ixgbevf_negotiate_api(hw);
4977
4978         ixgbevf_dev_tx_init(dev);
4979
4980         /* This can fail when allocating mbufs for descriptor rings */
4981         err = ixgbevf_dev_rx_init(dev);
4982         if (err) {
4983                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4984                 ixgbe_dev_clear_queues(dev);
4985                 return err;
4986         }
4987
4988         /* Set vfta */
4989         ixgbevf_set_vfta_all(dev, 1);
4990
4991         /* Set HW strip */
4992         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4993                 ETH_VLAN_EXTEND_MASK;
4994         err = ixgbevf_vlan_offload_set(dev, mask);
4995         if (err) {
4996                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4997                 ixgbe_dev_clear_queues(dev);
4998                 return err;
4999         }
5000
5001         ixgbevf_dev_rxtx_start(dev);
5002
5003         ixgbevf_dev_link_update(dev, 0);
5004
5005         /* check and configure queue intr-vector mapping */
5006         if (rte_intr_cap_multiple(intr_handle) &&
5007             dev->data->dev_conf.intr_conf.rxq) {
5008                 /* According to datasheet, only vector 0/1/2 can be used,
5009                  * now only one vector is used for Rx queue
5010                  */
5011                 intr_vector = 1;
5012                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5013                         return -1;
5014         }
5015
5016         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5017                 intr_handle->intr_vec =
5018                         rte_zmalloc("intr_vec",
5019                                     dev->data->nb_rx_queues * sizeof(int), 0);
5020                 if (intr_handle->intr_vec == NULL) {
5021                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5022                                      " intr_vec", dev->data->nb_rx_queues);
5023                         return -ENOMEM;
5024                 }
5025         }
5026         ixgbevf_configure_msix(dev);
5027
5028         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5029          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5030          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5031          * is not cleared, it will fail when following rte_intr_enable( ) tries
5032          * to map Rx queue interrupt to other VFIO vectors.
5033          * So clear uio/vfio intr/evevnfd first to avoid failure.
5034          */
5035         rte_intr_disable(intr_handle);
5036
5037         rte_intr_enable(intr_handle);
5038
5039         /* Re-enable interrupt for VF */
5040         ixgbevf_intr_enable(hw);
5041
5042         return 0;
5043 }
5044
5045 static void
5046 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5047 {
5048         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5049         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5050         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5051
5052         PMD_INIT_FUNC_TRACE();
5053
5054         ixgbevf_intr_disable(hw);
5055
5056         hw->adapter_stopped = 1;
5057         ixgbe_stop_adapter(hw);
5058
5059         /*
5060           * Clear what we set, but we still keep shadow_vfta to
5061           * restore after device starts
5062           */
5063         ixgbevf_set_vfta_all(dev, 0);
5064
5065         /* Clear stored conf */
5066         dev->data->scattered_rx = 0;
5067
5068         ixgbe_dev_clear_queues(dev);
5069
5070         /* Clean datapath event and queue/vec mapping */
5071         rte_intr_efd_disable(intr_handle);
5072         if (intr_handle->intr_vec != NULL) {
5073                 rte_free(intr_handle->intr_vec);
5074                 intr_handle->intr_vec = NULL;
5075         }
5076 }
5077
5078 static void
5079 ixgbevf_dev_close(struct rte_eth_dev *dev)
5080 {
5081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082
5083         PMD_INIT_FUNC_TRACE();
5084
5085         ixgbe_reset_hw(hw);
5086
5087         ixgbevf_dev_stop(dev);
5088
5089         ixgbe_dev_free_queues(dev);
5090
5091         /**
5092          * Remove the VF MAC address ro ensure
5093          * that the VF traffic goes to the PF
5094          * after stop, close and detach of the VF
5095          **/
5096         ixgbevf_remove_mac_addr(dev, 0);
5097 }
5098
5099 /*
5100  * Reset VF device
5101  */
5102 static int
5103 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5104 {
5105         int ret;
5106
5107         ret = eth_ixgbevf_dev_uninit(dev);
5108         if (ret)
5109                 return ret;
5110
5111         ret = eth_ixgbevf_dev_init(dev);
5112
5113         return ret;
5114 }
5115
5116 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5117 {
5118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5119         struct ixgbe_vfta *shadow_vfta =
5120                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5121         int i = 0, j = 0, vfta = 0, mask = 1;
5122
5123         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5124                 vfta = shadow_vfta->vfta[i];
5125                 if (vfta) {
5126                         mask = 1;
5127                         for (j = 0; j < 32; j++) {
5128                                 if (vfta & mask)
5129                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5130                                                        on, false);
5131                                 mask <<= 1;
5132                         }
5133                 }
5134         }
5135
5136 }
5137
5138 static int
5139 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5140 {
5141         struct ixgbe_hw *hw =
5142                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5143         struct ixgbe_vfta *shadow_vfta =
5144                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5145         uint32_t vid_idx = 0;
5146         uint32_t vid_bit = 0;
5147         int ret = 0;
5148
5149         PMD_INIT_FUNC_TRACE();
5150
5151         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5152         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5153         if (ret) {
5154                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5155                 return ret;
5156         }
5157         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5158         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5159
5160         /* Save what we set and retore it after device reset */
5161         if (on)
5162                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5163         else
5164                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5165
5166         return 0;
5167 }
5168
5169 static void
5170 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5171 {
5172         struct ixgbe_hw *hw =
5173                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174         uint32_t ctrl;
5175
5176         PMD_INIT_FUNC_TRACE();
5177
5178         if (queue >= hw->mac.max_rx_queues)
5179                 return;
5180
5181         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5182         if (on)
5183                 ctrl |= IXGBE_RXDCTL_VME;
5184         else
5185                 ctrl &= ~IXGBE_RXDCTL_VME;
5186         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5187
5188         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5189 }
5190
5191 static int
5192 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5193 {
5194         struct ixgbe_rx_queue *rxq;
5195         uint16_t i;
5196         int on = 0;
5197
5198         /* VF function only support hw strip feature, others are not support */
5199         if (mask & ETH_VLAN_STRIP_MASK) {
5200                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5201                         rxq = dev->data->rx_queues[i];
5202                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5203                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5204                 }
5205         }
5206
5207         return 0;
5208 }
5209
5210 int
5211 ixgbe_vt_check(struct ixgbe_hw *hw)
5212 {
5213         uint32_t reg_val;
5214
5215         /* if Virtualization Technology is enabled */
5216         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5217         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5218                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5219                 return -1;
5220         }
5221
5222         return 0;
5223 }
5224
5225 static uint32_t
5226 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5227 {
5228         uint32_t vector = 0;
5229
5230         switch (hw->mac.mc_filter_type) {
5231         case 0:   /* use bits [47:36] of the address */
5232                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5233                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5234                 break;
5235         case 1:   /* use bits [46:35] of the address */
5236                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5237                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5238                 break;
5239         case 2:   /* use bits [45:34] of the address */
5240                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5241                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5242                 break;
5243         case 3:   /* use bits [43:32] of the address */
5244                 vector = ((uc_addr->addr_bytes[4]) |
5245                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5246                 break;
5247         default:  /* Invalid mc_filter_type */
5248                 break;
5249         }
5250
5251         /* vector can only be 12-bits or boundary will be exceeded */
5252         vector &= 0xFFF;
5253         return vector;
5254 }
5255
5256 static int
5257 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5258                         uint8_t on)
5259 {
5260         uint32_t vector;
5261         uint32_t uta_idx;
5262         uint32_t reg_val;
5263         uint32_t uta_shift;
5264         uint32_t rc;
5265         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5266         const uint32_t ixgbe_uta_bit_shift = 5;
5267         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5268         const uint32_t bit1 = 0x1;
5269
5270         struct ixgbe_hw *hw =
5271                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5272         struct ixgbe_uta_info *uta_info =
5273                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5274
5275         /* The UTA table only exists on 82599 hardware and newer */
5276         if (hw->mac.type < ixgbe_mac_82599EB)
5277                 return -ENOTSUP;
5278
5279         vector = ixgbe_uta_vector(hw, mac_addr);
5280         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5281         uta_shift = vector & ixgbe_uta_bit_mask;
5282
5283         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5284         if (rc == on)
5285                 return 0;
5286
5287         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5288         if (on) {
5289                 uta_info->uta_in_use++;
5290                 reg_val |= (bit1 << uta_shift);
5291                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5292         } else {
5293                 uta_info->uta_in_use--;
5294                 reg_val &= ~(bit1 << uta_shift);
5295                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5296         }
5297
5298         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5299
5300         if (uta_info->uta_in_use > 0)
5301                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5302                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5303         else
5304                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5305
5306         return 0;
5307 }
5308
5309 static int
5310 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5311 {
5312         int i;
5313         struct ixgbe_hw *hw =
5314                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5315         struct ixgbe_uta_info *uta_info =
5316                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5317
5318         /* The UTA table only exists on 82599 hardware and newer */
5319         if (hw->mac.type < ixgbe_mac_82599EB)
5320                 return -ENOTSUP;
5321
5322         if (on) {
5323                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5324                         uta_info->uta_shadow[i] = ~0;
5325                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5326                 }
5327         } else {
5328                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5329                         uta_info->uta_shadow[i] = 0;
5330                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5331                 }
5332         }
5333         return 0;
5334
5335 }
5336
5337 uint32_t
5338 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5339 {
5340         uint32_t new_val = orig_val;
5341
5342         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5343                 new_val |= IXGBE_VMOLR_AUPE;
5344         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5345                 new_val |= IXGBE_VMOLR_ROMPE;
5346         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5347                 new_val |= IXGBE_VMOLR_ROPE;
5348         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5349                 new_val |= IXGBE_VMOLR_BAM;
5350         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5351                 new_val |= IXGBE_VMOLR_MPE;
5352
5353         return new_val;
5354 }
5355
5356 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5357 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5358 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5359 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5360 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5361         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5362         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5363
5364 static int
5365 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5366                       struct rte_eth_mirror_conf *mirror_conf,
5367                       uint8_t rule_id, uint8_t on)
5368 {
5369         uint32_t mr_ctl, vlvf;
5370         uint32_t mp_lsb = 0;
5371         uint32_t mv_msb = 0;
5372         uint32_t mv_lsb = 0;
5373         uint32_t mp_msb = 0;
5374         uint8_t i = 0;
5375         int reg_index = 0;
5376         uint64_t vlan_mask = 0;
5377
5378         const uint8_t pool_mask_offset = 32;
5379         const uint8_t vlan_mask_offset = 32;
5380         const uint8_t dst_pool_offset = 8;
5381         const uint8_t rule_mr_offset  = 4;
5382         const uint8_t mirror_rule_mask = 0x0F;
5383
5384         struct ixgbe_mirror_info *mr_info =
5385                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5386         struct ixgbe_hw *hw =
5387                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5388         uint8_t mirror_type = 0;
5389
5390         if (ixgbe_vt_check(hw) < 0)
5391                 return -ENOTSUP;
5392
5393         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5394                 return -EINVAL;
5395
5396         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5397                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5398                             mirror_conf->rule_type);
5399                 return -EINVAL;
5400         }
5401
5402         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5403                 mirror_type |= IXGBE_MRCTL_VLME;
5404                 /* Check if vlan id is valid and find conresponding VLAN ID
5405                  * index in VLVF
5406                  */
5407                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5408                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5409                                 /* search vlan id related pool vlan filter
5410                                  * index
5411                                  */
5412                                 reg_index = ixgbe_find_vlvf_slot(
5413                                                 hw,
5414                                                 mirror_conf->vlan.vlan_id[i],
5415                                                 false);
5416                                 if (reg_index < 0)
5417                                         return -EINVAL;
5418                                 vlvf = IXGBE_READ_REG(hw,
5419                                                       IXGBE_VLVF(reg_index));
5420                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5421                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5422                                       mirror_conf->vlan.vlan_id[i]))
5423                                         vlan_mask |= (1ULL << reg_index);
5424                                 else
5425                                         return -EINVAL;
5426                         }
5427                 }
5428
5429                 if (on) {
5430                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5431                         mv_msb = vlan_mask >> vlan_mask_offset;
5432
5433                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5434                                                 mirror_conf->vlan.vlan_mask;
5435                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5436                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5437                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5438                                                 mirror_conf->vlan.vlan_id[i];
5439                         }
5440                 } else {
5441                         mv_lsb = 0;
5442                         mv_msb = 0;
5443                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5444                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5445                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5446                 }
5447         }
5448
5449         /**
5450          * if enable pool mirror, write related pool mask register,if disable
5451          * pool mirror, clear PFMRVM register
5452          */
5453         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5454                 mirror_type |= IXGBE_MRCTL_VPME;
5455                 if (on) {
5456                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5457                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5458                         mr_info->mr_conf[rule_id].pool_mask =
5459                                         mirror_conf->pool_mask;
5460
5461                 } else {
5462                         mp_lsb = 0;
5463                         mp_msb = 0;
5464                         mr_info->mr_conf[rule_id].pool_mask = 0;
5465                 }
5466         }
5467         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5468                 mirror_type |= IXGBE_MRCTL_UPME;
5469         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5470                 mirror_type |= IXGBE_MRCTL_DPME;
5471
5472         /* read  mirror control register and recalculate it */
5473         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5474
5475         if (on) {
5476                 mr_ctl |= mirror_type;
5477                 mr_ctl &= mirror_rule_mask;
5478                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5479         } else {
5480                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5481         }
5482
5483         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5484         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5485
5486         /* write mirrror control  register */
5487         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5488
5489         /* write pool mirrror control  register */
5490         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5491                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5492                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5493                                 mp_msb);
5494         }
5495         /* write VLAN mirrror control  register */
5496         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5497                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5498                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5499                                 mv_msb);
5500         }
5501
5502         return 0;
5503 }
5504
5505 static int
5506 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5507 {
5508         int mr_ctl = 0;
5509         uint32_t lsb_val = 0;
5510         uint32_t msb_val = 0;
5511         const uint8_t rule_mr_offset = 4;
5512
5513         struct ixgbe_hw *hw =
5514                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5515         struct ixgbe_mirror_info *mr_info =
5516                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5517
5518         if (ixgbe_vt_check(hw) < 0)
5519                 return -ENOTSUP;
5520
5521         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5522                 return -EINVAL;
5523
5524         memset(&mr_info->mr_conf[rule_id], 0,
5525                sizeof(struct rte_eth_mirror_conf));
5526
5527         /* clear PFVMCTL register */
5528         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5529
5530         /* clear pool mask register */
5531         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5532         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5533
5534         /* clear vlan mask register */
5535         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5536         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5537
5538         return 0;
5539 }
5540
5541 static int
5542 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5543 {
5544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5545         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5546         uint32_t mask;
5547         struct ixgbe_hw *hw =
5548                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549         uint32_t vec = IXGBE_MISC_VEC_ID;
5550
5551         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5552         if (rte_intr_allow_others(intr_handle))
5553                 vec = IXGBE_RX_VEC_START;
5554         mask |= (1 << vec);
5555         RTE_SET_USED(queue_id);
5556         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5557
5558         rte_intr_enable(intr_handle);
5559
5560         return 0;
5561 }
5562
5563 static int
5564 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5565 {
5566         uint32_t mask;
5567         struct ixgbe_hw *hw =
5568                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5569         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5570         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5571         uint32_t vec = IXGBE_MISC_VEC_ID;
5572
5573         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5574         if (rte_intr_allow_others(intr_handle))
5575                 vec = IXGBE_RX_VEC_START;
5576         mask &= ~(1 << vec);
5577         RTE_SET_USED(queue_id);
5578         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5579
5580         return 0;
5581 }
5582
5583 static int
5584 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5585 {
5586         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5588         uint32_t mask;
5589         struct ixgbe_hw *hw =
5590                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5591         struct ixgbe_interrupt *intr =
5592                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5593
5594         if (queue_id < 16) {
5595                 ixgbe_disable_intr(hw);
5596                 intr->mask |= (1 << queue_id);
5597                 ixgbe_enable_intr(dev);
5598         } else if (queue_id < 32) {
5599                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5600                 mask &= (1 << queue_id);
5601                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5602         } else if (queue_id < 64) {
5603                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5604                 mask &= (1 << (queue_id - 32));
5605                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5606         }
5607         rte_intr_enable(intr_handle);
5608
5609         return 0;
5610 }
5611
5612 static int
5613 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5614 {
5615         uint32_t mask;
5616         struct ixgbe_hw *hw =
5617                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5618         struct ixgbe_interrupt *intr =
5619                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5620
5621         if (queue_id < 16) {
5622                 ixgbe_disable_intr(hw);
5623                 intr->mask &= ~(1 << queue_id);
5624                 ixgbe_enable_intr(dev);
5625         } else if (queue_id < 32) {
5626                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5627                 mask &= ~(1 << queue_id);
5628                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5629         } else if (queue_id < 64) {
5630                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5631                 mask &= ~(1 << (queue_id - 32));
5632                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5633         }
5634
5635         return 0;
5636 }
5637
5638 static void
5639 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5640                      uint8_t queue, uint8_t msix_vector)
5641 {
5642         uint32_t tmp, idx;
5643
5644         if (direction == -1) {
5645                 /* other causes */
5646                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5647                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5648                 tmp &= ~0xFF;
5649                 tmp |= msix_vector;
5650                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5651         } else {
5652                 /* rx or tx cause */
5653                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5654                 idx = ((16 * (queue & 1)) + (8 * direction));
5655                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5656                 tmp &= ~(0xFF << idx);
5657                 tmp |= (msix_vector << idx);
5658                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5659         }
5660 }
5661
5662 /**
5663  * set the IVAR registers, mapping interrupt causes to vectors
5664  * @param hw
5665  *  pointer to ixgbe_hw struct
5666  * @direction
5667  *  0 for Rx, 1 for Tx, -1 for other causes
5668  * @queue
5669  *  queue to map the corresponding interrupt to
5670  * @msix_vector
5671  *  the vector to map to the corresponding queue
5672  */
5673 static void
5674 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5675                    uint8_t queue, uint8_t msix_vector)
5676 {
5677         uint32_t tmp, idx;
5678
5679         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5680         if (hw->mac.type == ixgbe_mac_82598EB) {
5681                 if (direction == -1)
5682                         direction = 0;
5683                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5684                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5685                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5686                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5687                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5688         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5689                         (hw->mac.type == ixgbe_mac_X540) ||
5690                         (hw->mac.type == ixgbe_mac_X550)) {
5691                 if (direction == -1) {
5692                         /* other causes */
5693                         idx = ((queue & 1) * 8);
5694                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5695                         tmp &= ~(0xFF << idx);
5696                         tmp |= (msix_vector << idx);
5697                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5698                 } else {
5699                         /* rx or tx causes */
5700                         idx = ((16 * (queue & 1)) + (8 * direction));
5701                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5702                         tmp &= ~(0xFF << idx);
5703                         tmp |= (msix_vector << idx);
5704                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5705                 }
5706         }
5707 }
5708
5709 static void
5710 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5711 {
5712         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5713         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5714         struct ixgbe_hw *hw =
5715                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5716         uint32_t q_idx;
5717         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5718         uint32_t base = IXGBE_MISC_VEC_ID;
5719
5720         /* Configure VF other cause ivar */
5721         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5722
5723         /* won't configure msix register if no mapping is done
5724          * between intr vector and event fd.
5725          */
5726         if (!rte_intr_dp_is_en(intr_handle))
5727                 return;
5728
5729         if (rte_intr_allow_others(intr_handle)) {
5730                 base = IXGBE_RX_VEC_START;
5731                 vector_idx = IXGBE_RX_VEC_START;
5732         }
5733
5734         /* Configure all RX queues of VF */
5735         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5736                 /* Force all queue use vector 0,
5737                  * as IXGBE_VF_MAXMSIVECOTR = 1
5738                  */
5739                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5740                 intr_handle->intr_vec[q_idx] = vector_idx;
5741                 if (vector_idx < base + intr_handle->nb_efd - 1)
5742                         vector_idx++;
5743         }
5744 }
5745
5746 /**
5747  * Sets up the hardware to properly generate MSI-X interrupts
5748  * @hw
5749  *  board private structure
5750  */
5751 static void
5752 ixgbe_configure_msix(struct rte_eth_dev *dev)
5753 {
5754         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5755         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5756         struct ixgbe_hw *hw =
5757                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5758         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5759         uint32_t vec = IXGBE_MISC_VEC_ID;
5760         uint32_t mask;
5761         uint32_t gpie;
5762
5763         /* won't configure msix register if no mapping is done
5764          * between intr vector and event fd
5765          */
5766         if (!rte_intr_dp_is_en(intr_handle))
5767                 return;
5768
5769         if (rte_intr_allow_others(intr_handle))
5770                 vec = base = IXGBE_RX_VEC_START;
5771
5772         /* setup GPIE for MSI-x mode */
5773         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5774         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5775                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5776         /* auto clearing and auto setting corresponding bits in EIMS
5777          * when MSI-X interrupt is triggered
5778          */
5779         if (hw->mac.type == ixgbe_mac_82598EB) {
5780                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5781         } else {
5782                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5783                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5784         }
5785         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5786
5787         /* Populate the IVAR table and set the ITR values to the
5788          * corresponding register.
5789          */
5790         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5791              queue_id++) {
5792                 /* by default, 1:1 mapping */
5793                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5794                 intr_handle->intr_vec[queue_id] = vec;
5795                 if (vec < base + intr_handle->nb_efd - 1)
5796                         vec++;
5797         }
5798
5799         switch (hw->mac.type) {
5800         case ixgbe_mac_82598EB:
5801                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5802                                    IXGBE_MISC_VEC_ID);
5803                 break;
5804         case ixgbe_mac_82599EB:
5805         case ixgbe_mac_X540:
5806         case ixgbe_mac_X550:
5807                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5808                 break;
5809         default:
5810                 break;
5811         }
5812         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5813                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5814
5815         /* set up to autoclear timer, and the vectors */
5816         mask = IXGBE_EIMS_ENABLE_MASK;
5817         mask &= ~(IXGBE_EIMS_OTHER |
5818                   IXGBE_EIMS_MAILBOX |
5819                   IXGBE_EIMS_LSC);
5820
5821         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5822 }
5823
5824 int
5825 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5826                            uint16_t queue_idx, uint16_t tx_rate)
5827 {
5828         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5829         struct rte_eth_rxmode *rxmode;
5830         uint32_t rf_dec, rf_int;
5831         uint32_t bcnrc_val;
5832         uint16_t link_speed = dev->data->dev_link.link_speed;
5833
5834         if (queue_idx >= hw->mac.max_tx_queues)
5835                 return -EINVAL;
5836
5837         if (tx_rate != 0) {
5838                 /* Calculate the rate factor values to set */
5839                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5840                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5841                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5842
5843                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5844                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5845                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5846                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5847         } else {
5848                 bcnrc_val = 0;
5849         }
5850
5851         rxmode = &dev->data->dev_conf.rxmode;
5852         /*
5853          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5854          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5855          * set as 0x4.
5856          */
5857         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5858             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5859                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5860                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5861         else
5862                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5863                         IXGBE_MMW_SIZE_DEFAULT);
5864
5865         /* Set RTTBCNRC of queue X */
5866         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5867         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5868         IXGBE_WRITE_FLUSH(hw);
5869
5870         return 0;
5871 }
5872
5873 static int
5874 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5875                      __attribute__((unused)) uint32_t index,
5876                      __attribute__((unused)) uint32_t pool)
5877 {
5878         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5879         int diag;
5880
5881         /*
5882          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5883          * operation. Trap this case to avoid exhausting the [very limited]
5884          * set of PF resources used to store VF MAC addresses.
5885          */
5886         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5887                 return -1;
5888         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5889         if (diag != 0)
5890                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5891                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5892                             mac_addr->addr_bytes[0],
5893                             mac_addr->addr_bytes[1],
5894                             mac_addr->addr_bytes[2],
5895                             mac_addr->addr_bytes[3],
5896                             mac_addr->addr_bytes[4],
5897                             mac_addr->addr_bytes[5],
5898                             diag);
5899         return diag;
5900 }
5901
5902 static void
5903 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5904 {
5905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5907         struct ether_addr *mac_addr;
5908         uint32_t i;
5909         int diag;
5910
5911         /*
5912          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5913          * not support the deletion of a given MAC address.
5914          * Instead, it imposes to delete all MAC addresses, then to add again
5915          * all MAC addresses with the exception of the one to be deleted.
5916          */
5917         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5918
5919         /*
5920          * Add again all MAC addresses, with the exception of the deleted one
5921          * and of the permanent MAC address.
5922          */
5923         for (i = 0, mac_addr = dev->data->mac_addrs;
5924              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5925                 /* Skip the deleted MAC address */
5926                 if (i == index)
5927                         continue;
5928                 /* Skip NULL MAC addresses */
5929                 if (is_zero_ether_addr(mac_addr))
5930                         continue;
5931                 /* Skip the permanent MAC address */
5932                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5933                         continue;
5934                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5935                 if (diag != 0)
5936                         PMD_DRV_LOG(ERR,
5937                                     "Adding again MAC address "
5938                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5939                                     "diag=%d",
5940                                     mac_addr->addr_bytes[0],
5941                                     mac_addr->addr_bytes[1],
5942                                     mac_addr->addr_bytes[2],
5943                                     mac_addr->addr_bytes[3],
5944                                     mac_addr->addr_bytes[4],
5945                                     mac_addr->addr_bytes[5],
5946                                     diag);
5947         }
5948 }
5949
5950 static int
5951 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5952 {
5953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5954
5955         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5956
5957         return 0;
5958 }
5959
5960 int
5961 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5962                         struct rte_eth_syn_filter *filter,
5963                         bool add)
5964 {
5965         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5966         struct ixgbe_filter_info *filter_info =
5967                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5968         uint32_t syn_info;
5969         uint32_t synqf;
5970
5971         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5972                 return -EINVAL;
5973
5974         syn_info = filter_info->syn_info;
5975
5976         if (add) {
5977                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5978                         return -EINVAL;
5979                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5980                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5981
5982                 if (filter->hig_pri)
5983                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5984                 else
5985                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5986         } else {
5987                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5988                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5989                         return -ENOENT;
5990                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5991         }
5992
5993         filter_info->syn_info = synqf;
5994         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5995         IXGBE_WRITE_FLUSH(hw);
5996         return 0;
5997 }
5998
5999 static int
6000 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6001                         struct rte_eth_syn_filter *filter)
6002 {
6003         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6004         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6005
6006         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6007                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6008                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6009                 return 0;
6010         }
6011         return -ENOENT;
6012 }
6013
6014 static int
6015 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6016                         enum rte_filter_op filter_op,
6017                         void *arg)
6018 {
6019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6020         int ret;
6021
6022         MAC_TYPE_FILTER_SUP(hw->mac.type);
6023
6024         if (filter_op == RTE_ETH_FILTER_NOP)
6025                 return 0;
6026
6027         if (arg == NULL) {
6028                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6029                             filter_op);
6030                 return -EINVAL;
6031         }
6032
6033         switch (filter_op) {
6034         case RTE_ETH_FILTER_ADD:
6035                 ret = ixgbe_syn_filter_set(dev,
6036                                 (struct rte_eth_syn_filter *)arg,
6037                                 TRUE);
6038                 break;
6039         case RTE_ETH_FILTER_DELETE:
6040                 ret = ixgbe_syn_filter_set(dev,
6041                                 (struct rte_eth_syn_filter *)arg,
6042                                 FALSE);
6043                 break;
6044         case RTE_ETH_FILTER_GET:
6045                 ret = ixgbe_syn_filter_get(dev,
6046                                 (struct rte_eth_syn_filter *)arg);
6047                 break;
6048         default:
6049                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6050                 ret = -EINVAL;
6051                 break;
6052         }
6053
6054         return ret;
6055 }
6056
6057
6058 static inline enum ixgbe_5tuple_protocol
6059 convert_protocol_type(uint8_t protocol_value)
6060 {
6061         if (protocol_value == IPPROTO_TCP)
6062                 return IXGBE_FILTER_PROTOCOL_TCP;
6063         else if (protocol_value == IPPROTO_UDP)
6064                 return IXGBE_FILTER_PROTOCOL_UDP;
6065         else if (protocol_value == IPPROTO_SCTP)
6066                 return IXGBE_FILTER_PROTOCOL_SCTP;
6067         else
6068                 return IXGBE_FILTER_PROTOCOL_NONE;
6069 }
6070
6071 /* inject a 5-tuple filter to HW */
6072 static inline void
6073 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6074                            struct ixgbe_5tuple_filter *filter)
6075 {
6076         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6077         int i;
6078         uint32_t ftqf, sdpqf;
6079         uint32_t l34timir = 0;
6080         uint8_t mask = 0xff;
6081
6082         i = filter->index;
6083
6084         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6085                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6086         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6087
6088         ftqf = (uint32_t)(filter->filter_info.proto &
6089                 IXGBE_FTQF_PROTOCOL_MASK);
6090         ftqf |= (uint32_t)((filter->filter_info.priority &
6091                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6092         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6093                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6094         if (filter->filter_info.dst_ip_mask == 0)
6095                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6096         if (filter->filter_info.src_port_mask == 0)
6097                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6098         if (filter->filter_info.dst_port_mask == 0)
6099                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6100         if (filter->filter_info.proto_mask == 0)
6101                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6102         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6103         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6104         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6105
6106         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6107         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6108         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6109         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6110
6111         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6112         l34timir |= (uint32_t)(filter->queue <<
6113                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6114         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6115 }
6116
6117 /*
6118  * add a 5tuple filter
6119  *
6120  * @param
6121  * dev: Pointer to struct rte_eth_dev.
6122  * index: the index the filter allocates.
6123  * filter: ponter to the filter that will be added.
6124  * rx_queue: the queue id the filter assigned to.
6125  *
6126  * @return
6127  *    - On success, zero.
6128  *    - On failure, a negative value.
6129  */
6130 static int
6131 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6132                         struct ixgbe_5tuple_filter *filter)
6133 {
6134         struct ixgbe_filter_info *filter_info =
6135                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6136         int i, idx, shift;
6137
6138         /*
6139          * look for an unused 5tuple filter index,
6140          * and insert the filter to list.
6141          */
6142         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6143                 idx = i / (sizeof(uint32_t) * NBBY);
6144                 shift = i % (sizeof(uint32_t) * NBBY);
6145                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6146                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6147                         filter->index = i;
6148                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6149                                           filter,
6150                                           entries);
6151                         break;
6152                 }
6153         }
6154         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6155                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6156                 return -ENOSYS;
6157         }
6158
6159         ixgbe_inject_5tuple_filter(dev, filter);
6160
6161         return 0;
6162 }
6163
6164 /*
6165  * remove a 5tuple filter
6166  *
6167  * @param
6168  * dev: Pointer to struct rte_eth_dev.
6169  * filter: the pointer of the filter will be removed.
6170  */
6171 static void
6172 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6173                         struct ixgbe_5tuple_filter *filter)
6174 {
6175         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6176         struct ixgbe_filter_info *filter_info =
6177                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6178         uint16_t index = filter->index;
6179
6180         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6181                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6182         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6183         rte_free(filter);
6184
6185         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6186         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6187         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6188         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6189         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6190 }
6191
6192 static int
6193 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6194 {
6195         struct ixgbe_hw *hw;
6196         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6197         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6198
6199         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6200
6201         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6202                 return -EINVAL;
6203
6204         /* refuse mtu that requires the support of scattered packets when this
6205          * feature has not been enabled before.
6206          */
6207         if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6208             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6209              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6210                 return -EINVAL;
6211
6212         /*
6213          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6214          * request of the version 2.0 of the mailbox API.
6215          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6216          * of the mailbox API.
6217          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6218          * prior to 3.11.33 which contains the following change:
6219          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6220          */
6221         ixgbevf_rlpml_set_vf(hw, max_frame);
6222
6223         /* update max frame size */
6224         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6225         return 0;
6226 }
6227
6228 static inline struct ixgbe_5tuple_filter *
6229 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6230                         struct ixgbe_5tuple_filter_info *key)
6231 {
6232         struct ixgbe_5tuple_filter *it;
6233
6234         TAILQ_FOREACH(it, filter_list, entries) {
6235                 if (memcmp(key, &it->filter_info,
6236                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6237                         return it;
6238                 }
6239         }
6240         return NULL;
6241 }
6242
6243 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6244 static inline int
6245 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6246                         struct ixgbe_5tuple_filter_info *filter_info)
6247 {
6248         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6249                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6250                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6251                 return -EINVAL;
6252
6253         switch (filter->dst_ip_mask) {
6254         case UINT32_MAX:
6255                 filter_info->dst_ip_mask = 0;
6256                 filter_info->dst_ip = filter->dst_ip;
6257                 break;
6258         case 0:
6259                 filter_info->dst_ip_mask = 1;
6260                 break;
6261         default:
6262                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6263                 return -EINVAL;
6264         }
6265
6266         switch (filter->src_ip_mask) {
6267         case UINT32_MAX:
6268                 filter_info->src_ip_mask = 0;
6269                 filter_info->src_ip = filter->src_ip;
6270                 break;
6271         case 0:
6272                 filter_info->src_ip_mask = 1;
6273                 break;
6274         default:
6275                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6276                 return -EINVAL;
6277         }
6278
6279         switch (filter->dst_port_mask) {
6280         case UINT16_MAX:
6281                 filter_info->dst_port_mask = 0;
6282                 filter_info->dst_port = filter->dst_port;
6283                 break;
6284         case 0:
6285                 filter_info->dst_port_mask = 1;
6286                 break;
6287         default:
6288                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6289                 return -EINVAL;
6290         }
6291
6292         switch (filter->src_port_mask) {
6293         case UINT16_MAX:
6294                 filter_info->src_port_mask = 0;
6295                 filter_info->src_port = filter->src_port;
6296                 break;
6297         case 0:
6298                 filter_info->src_port_mask = 1;
6299                 break;
6300         default:
6301                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6302                 return -EINVAL;
6303         }
6304
6305         switch (filter->proto_mask) {
6306         case UINT8_MAX:
6307                 filter_info->proto_mask = 0;
6308                 filter_info->proto =
6309                         convert_protocol_type(filter->proto);
6310                 break;
6311         case 0:
6312                 filter_info->proto_mask = 1;
6313                 break;
6314         default:
6315                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6316                 return -EINVAL;
6317         }
6318
6319         filter_info->priority = (uint8_t)filter->priority;
6320         return 0;
6321 }
6322
6323 /*
6324  * add or delete a ntuple filter
6325  *
6326  * @param
6327  * dev: Pointer to struct rte_eth_dev.
6328  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6329  * add: if true, add filter, if false, remove filter
6330  *
6331  * @return
6332  *    - On success, zero.
6333  *    - On failure, a negative value.
6334  */
6335 int
6336 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6337                         struct rte_eth_ntuple_filter *ntuple_filter,
6338                         bool add)
6339 {
6340         struct ixgbe_filter_info *filter_info =
6341                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6342         struct ixgbe_5tuple_filter_info filter_5tuple;
6343         struct ixgbe_5tuple_filter *filter;
6344         int ret;
6345
6346         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6347                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6348                 return -EINVAL;
6349         }
6350
6351         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6352         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6353         if (ret < 0)
6354                 return ret;
6355
6356         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6357                                          &filter_5tuple);
6358         if (filter != NULL && add) {
6359                 PMD_DRV_LOG(ERR, "filter exists.");
6360                 return -EEXIST;
6361         }
6362         if (filter == NULL && !add) {
6363                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6364                 return -ENOENT;
6365         }
6366
6367         if (add) {
6368                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6369                                 sizeof(struct ixgbe_5tuple_filter), 0);
6370                 if (filter == NULL)
6371                         return -ENOMEM;
6372                 rte_memcpy(&filter->filter_info,
6373                                  &filter_5tuple,
6374                                  sizeof(struct ixgbe_5tuple_filter_info));
6375                 filter->queue = ntuple_filter->queue;
6376                 ret = ixgbe_add_5tuple_filter(dev, filter);
6377                 if (ret < 0) {
6378                         rte_free(filter);
6379                         return ret;
6380                 }
6381         } else
6382                 ixgbe_remove_5tuple_filter(dev, filter);
6383
6384         return 0;
6385 }
6386
6387 /*
6388  * get a ntuple filter
6389  *
6390  * @param
6391  * dev: Pointer to struct rte_eth_dev.
6392  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6393  *
6394  * @return
6395  *    - On success, zero.
6396  *    - On failure, a negative value.
6397  */
6398 static int
6399 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6400                         struct rte_eth_ntuple_filter *ntuple_filter)
6401 {
6402         struct ixgbe_filter_info *filter_info =
6403                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6404         struct ixgbe_5tuple_filter_info filter_5tuple;
6405         struct ixgbe_5tuple_filter *filter;
6406         int ret;
6407
6408         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6409                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6410                 return -EINVAL;
6411         }
6412
6413         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6414         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6415         if (ret < 0)
6416                 return ret;
6417
6418         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6419                                          &filter_5tuple);
6420         if (filter == NULL) {
6421                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6422                 return -ENOENT;
6423         }
6424         ntuple_filter->queue = filter->queue;
6425         return 0;
6426 }
6427
6428 /*
6429  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6430  * @dev: pointer to rte_eth_dev structure
6431  * @filter_op:operation will be taken.
6432  * @arg: a pointer to specific structure corresponding to the filter_op
6433  *
6434  * @return
6435  *    - On success, zero.
6436  *    - On failure, a negative value.
6437  */
6438 static int
6439 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6440                                 enum rte_filter_op filter_op,
6441                                 void *arg)
6442 {
6443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6444         int ret;
6445
6446         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6447
6448         if (filter_op == RTE_ETH_FILTER_NOP)
6449                 return 0;
6450
6451         if (arg == NULL) {
6452                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6453                             filter_op);
6454                 return -EINVAL;
6455         }
6456
6457         switch (filter_op) {
6458         case RTE_ETH_FILTER_ADD:
6459                 ret = ixgbe_add_del_ntuple_filter(dev,
6460                         (struct rte_eth_ntuple_filter *)arg,
6461                         TRUE);
6462                 break;
6463         case RTE_ETH_FILTER_DELETE:
6464                 ret = ixgbe_add_del_ntuple_filter(dev,
6465                         (struct rte_eth_ntuple_filter *)arg,
6466                         FALSE);
6467                 break;
6468         case RTE_ETH_FILTER_GET:
6469                 ret = ixgbe_get_ntuple_filter(dev,
6470                         (struct rte_eth_ntuple_filter *)arg);
6471                 break;
6472         default:
6473                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6474                 ret = -EINVAL;
6475                 break;
6476         }
6477         return ret;
6478 }
6479
6480 int
6481 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6482                         struct rte_eth_ethertype_filter *filter,
6483                         bool add)
6484 {
6485         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6486         struct ixgbe_filter_info *filter_info =
6487                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6488         uint32_t etqf = 0;
6489         uint32_t etqs = 0;
6490         int ret;
6491         struct ixgbe_ethertype_filter ethertype_filter;
6492
6493         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6494                 return -EINVAL;
6495
6496         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6497                 filter->ether_type == ETHER_TYPE_IPv6) {
6498                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6499                         " ethertype filter.", filter->ether_type);
6500                 return -EINVAL;
6501         }
6502
6503         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6504                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6505                 return -EINVAL;
6506         }
6507         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6508                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6509                 return -EINVAL;
6510         }
6511
6512         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6513         if (ret >= 0 && add) {
6514                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6515                             filter->ether_type);
6516                 return -EEXIST;
6517         }
6518         if (ret < 0 && !add) {
6519                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6520                             filter->ether_type);
6521                 return -ENOENT;
6522         }
6523
6524         if (add) {
6525                 etqf = IXGBE_ETQF_FILTER_EN;
6526                 etqf |= (uint32_t)filter->ether_type;
6527                 etqs |= (uint32_t)((filter->queue <<
6528                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6529                                     IXGBE_ETQS_RX_QUEUE);
6530                 etqs |= IXGBE_ETQS_QUEUE_EN;
6531
6532                 ethertype_filter.ethertype = filter->ether_type;
6533                 ethertype_filter.etqf = etqf;
6534                 ethertype_filter.etqs = etqs;
6535                 ethertype_filter.conf = FALSE;
6536                 ret = ixgbe_ethertype_filter_insert(filter_info,
6537                                                     &ethertype_filter);
6538                 if (ret < 0) {
6539                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6540                         return -ENOSPC;
6541                 }
6542         } else {
6543                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6544                 if (ret < 0)
6545                         return -ENOSYS;
6546         }
6547         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6548         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6549         IXGBE_WRITE_FLUSH(hw);
6550
6551         return 0;
6552 }
6553
6554 static int
6555 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6556                         struct rte_eth_ethertype_filter *filter)
6557 {
6558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6559         struct ixgbe_filter_info *filter_info =
6560                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6561         uint32_t etqf, etqs;
6562         int ret;
6563
6564         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6565         if (ret < 0) {
6566                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6567                             filter->ether_type);
6568                 return -ENOENT;
6569         }
6570
6571         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6572         if (etqf & IXGBE_ETQF_FILTER_EN) {
6573                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6574                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6575                 filter->flags = 0;
6576                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6577                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6578                 return 0;
6579         }
6580         return -ENOENT;
6581 }
6582
6583 /*
6584  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6585  * @dev: pointer to rte_eth_dev structure
6586  * @filter_op:operation will be taken.
6587  * @arg: a pointer to specific structure corresponding to the filter_op
6588  */
6589 static int
6590 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6591                                 enum rte_filter_op filter_op,
6592                                 void *arg)
6593 {
6594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6595         int ret;
6596
6597         MAC_TYPE_FILTER_SUP(hw->mac.type);
6598
6599         if (filter_op == RTE_ETH_FILTER_NOP)
6600                 return 0;
6601
6602         if (arg == NULL) {
6603                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6604                             filter_op);
6605                 return -EINVAL;
6606         }
6607
6608         switch (filter_op) {
6609         case RTE_ETH_FILTER_ADD:
6610                 ret = ixgbe_add_del_ethertype_filter(dev,
6611                         (struct rte_eth_ethertype_filter *)arg,
6612                         TRUE);
6613                 break;
6614         case RTE_ETH_FILTER_DELETE:
6615                 ret = ixgbe_add_del_ethertype_filter(dev,
6616                         (struct rte_eth_ethertype_filter *)arg,
6617                         FALSE);
6618                 break;
6619         case RTE_ETH_FILTER_GET:
6620                 ret = ixgbe_get_ethertype_filter(dev,
6621                         (struct rte_eth_ethertype_filter *)arg);
6622                 break;
6623         default:
6624                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6625                 ret = -EINVAL;
6626                 break;
6627         }
6628         return ret;
6629 }
6630
6631 static int
6632 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6633                      enum rte_filter_type filter_type,
6634                      enum rte_filter_op filter_op,
6635                      void *arg)
6636 {
6637         int ret = 0;
6638
6639         switch (filter_type) {
6640         case RTE_ETH_FILTER_NTUPLE:
6641                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6642                 break;
6643         case RTE_ETH_FILTER_ETHERTYPE:
6644                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6645                 break;
6646         case RTE_ETH_FILTER_SYN:
6647                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6648                 break;
6649         case RTE_ETH_FILTER_FDIR:
6650                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6651                 break;
6652         case RTE_ETH_FILTER_L2_TUNNEL:
6653                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6654                 break;
6655         case RTE_ETH_FILTER_GENERIC:
6656                 if (filter_op != RTE_ETH_FILTER_GET)
6657                         return -EINVAL;
6658                 *(const void **)arg = &ixgbe_flow_ops;
6659                 break;
6660         default:
6661                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6662                                                         filter_type);
6663                 ret = -EINVAL;
6664                 break;
6665         }
6666
6667         return ret;
6668 }
6669
6670 static u8 *
6671 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6672                         u8 **mc_addr_ptr, u32 *vmdq)
6673 {
6674         u8 *mc_addr;
6675
6676         *vmdq = 0;
6677         mc_addr = *mc_addr_ptr;
6678         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6679         return mc_addr;
6680 }
6681
6682 static int
6683 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6684                           struct ether_addr *mc_addr_set,
6685                           uint32_t nb_mc_addr)
6686 {
6687         struct ixgbe_hw *hw;
6688         u8 *mc_addr_list;
6689
6690         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6691         mc_addr_list = (u8 *)mc_addr_set;
6692         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6693                                          ixgbe_dev_addr_list_itr, TRUE);
6694 }
6695
6696 static uint64_t
6697 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6698 {
6699         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700         uint64_t systime_cycles;
6701
6702         switch (hw->mac.type) {
6703         case ixgbe_mac_X550:
6704         case ixgbe_mac_X550EM_x:
6705         case ixgbe_mac_X550EM_a:
6706                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6707                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6708                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6709                                 * NSEC_PER_SEC;
6710                 break;
6711         default:
6712                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6713                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6714                                 << 32;
6715         }
6716
6717         return systime_cycles;
6718 }
6719
6720 static uint64_t
6721 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6722 {
6723         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6724         uint64_t rx_tstamp_cycles;
6725
6726         switch (hw->mac.type) {
6727         case ixgbe_mac_X550:
6728         case ixgbe_mac_X550EM_x:
6729         case ixgbe_mac_X550EM_a:
6730                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6731                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6732                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6733                                 * NSEC_PER_SEC;
6734                 break;
6735         default:
6736                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6737                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6738                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6739                                 << 32;
6740         }
6741
6742         return rx_tstamp_cycles;
6743 }
6744
6745 static uint64_t
6746 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6747 {
6748         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6749         uint64_t tx_tstamp_cycles;
6750
6751         switch (hw->mac.type) {
6752         case ixgbe_mac_X550:
6753         case ixgbe_mac_X550EM_x:
6754         case ixgbe_mac_X550EM_a:
6755                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6756                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6757                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6758                                 * NSEC_PER_SEC;
6759                 break;
6760         default:
6761                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6762                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6763                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6764                                 << 32;
6765         }
6766
6767         return tx_tstamp_cycles;
6768 }
6769
6770 static void
6771 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6772 {
6773         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6774         struct ixgbe_adapter *adapter =
6775                 (struct ixgbe_adapter *)dev->data->dev_private;
6776         struct rte_eth_link link;
6777         uint32_t incval = 0;
6778         uint32_t shift = 0;
6779
6780         /* Get current link speed. */
6781         ixgbe_dev_link_update(dev, 1);
6782         rte_eth_linkstatus_get(dev, &link);
6783
6784         switch (link.link_speed) {
6785         case ETH_SPEED_NUM_100M:
6786                 incval = IXGBE_INCVAL_100;
6787                 shift = IXGBE_INCVAL_SHIFT_100;
6788                 break;
6789         case ETH_SPEED_NUM_1G:
6790                 incval = IXGBE_INCVAL_1GB;
6791                 shift = IXGBE_INCVAL_SHIFT_1GB;
6792                 break;
6793         case ETH_SPEED_NUM_10G:
6794         default:
6795                 incval = IXGBE_INCVAL_10GB;
6796                 shift = IXGBE_INCVAL_SHIFT_10GB;
6797                 break;
6798         }
6799
6800         switch (hw->mac.type) {
6801         case ixgbe_mac_X550:
6802         case ixgbe_mac_X550EM_x:
6803         case ixgbe_mac_X550EM_a:
6804                 /* Independent of link speed. */
6805                 incval = 1;
6806                 /* Cycles read will be interpreted as ns. */
6807                 shift = 0;
6808                 /* Fall-through */
6809         case ixgbe_mac_X540:
6810                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6811                 break;
6812         case ixgbe_mac_82599EB:
6813                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6814                 shift -= IXGBE_INCVAL_SHIFT_82599;
6815                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6816                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6817                 break;
6818         default:
6819                 /* Not supported. */
6820                 return;
6821         }
6822
6823         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6824         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6825         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6826
6827         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6828         adapter->systime_tc.cc_shift = shift;
6829         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6830
6831         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6832         adapter->rx_tstamp_tc.cc_shift = shift;
6833         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6834
6835         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6836         adapter->tx_tstamp_tc.cc_shift = shift;
6837         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6838 }
6839
6840 static int
6841 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6842 {
6843         struct ixgbe_adapter *adapter =
6844                         (struct ixgbe_adapter *)dev->data->dev_private;
6845
6846         adapter->systime_tc.nsec += delta;
6847         adapter->rx_tstamp_tc.nsec += delta;
6848         adapter->tx_tstamp_tc.nsec += delta;
6849
6850         return 0;
6851 }
6852
6853 static int
6854 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6855 {
6856         uint64_t ns;
6857         struct ixgbe_adapter *adapter =
6858                         (struct ixgbe_adapter *)dev->data->dev_private;
6859
6860         ns = rte_timespec_to_ns(ts);
6861         /* Set the timecounters to a new value. */
6862         adapter->systime_tc.nsec = ns;
6863         adapter->rx_tstamp_tc.nsec = ns;
6864         adapter->tx_tstamp_tc.nsec = ns;
6865
6866         return 0;
6867 }
6868
6869 static int
6870 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6871 {
6872         uint64_t ns, systime_cycles;
6873         struct ixgbe_adapter *adapter =
6874                         (struct ixgbe_adapter *)dev->data->dev_private;
6875
6876         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6877         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6878         *ts = rte_ns_to_timespec(ns);
6879
6880         return 0;
6881 }
6882
6883 static int
6884 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6885 {
6886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6887         uint32_t tsync_ctl;
6888         uint32_t tsauxc;
6889
6890         /* Stop the timesync system time. */
6891         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6892         /* Reset the timesync system time value. */
6893         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6894         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6895
6896         /* Enable system time for platforms where it isn't on by default. */
6897         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6898         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6899         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6900
6901         ixgbe_start_timecounters(dev);
6902
6903         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6904         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6905                         (ETHER_TYPE_1588 |
6906                          IXGBE_ETQF_FILTER_EN |
6907                          IXGBE_ETQF_1588));
6908
6909         /* Enable timestamping of received PTP packets. */
6910         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6911         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6912         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6913
6914         /* Enable timestamping of transmitted PTP packets. */
6915         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6916         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6917         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6918
6919         IXGBE_WRITE_FLUSH(hw);
6920
6921         return 0;
6922 }
6923
6924 static int
6925 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6926 {
6927         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6928         uint32_t tsync_ctl;
6929
6930         /* Disable timestamping of transmitted PTP packets. */
6931         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6932         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6933         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6934
6935         /* Disable timestamping of received PTP packets. */
6936         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6937         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6938         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6939
6940         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6941         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6942
6943         /* Stop incrementating the System Time registers. */
6944         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6945
6946         return 0;
6947 }
6948
6949 static int
6950 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6951                                  struct timespec *timestamp,
6952                                  uint32_t flags __rte_unused)
6953 {
6954         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6955         struct ixgbe_adapter *adapter =
6956                 (struct ixgbe_adapter *)dev->data->dev_private;
6957         uint32_t tsync_rxctl;
6958         uint64_t rx_tstamp_cycles;
6959         uint64_t ns;
6960
6961         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6962         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6963                 return -EINVAL;
6964
6965         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6966         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6967         *timestamp = rte_ns_to_timespec(ns);
6968
6969         return  0;
6970 }
6971
6972 static int
6973 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6974                                  struct timespec *timestamp)
6975 {
6976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6977         struct ixgbe_adapter *adapter =
6978                 (struct ixgbe_adapter *)dev->data->dev_private;
6979         uint32_t tsync_txctl;
6980         uint64_t tx_tstamp_cycles;
6981         uint64_t ns;
6982
6983         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6984         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6985                 return -EINVAL;
6986
6987         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6988         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6989         *timestamp = rte_ns_to_timespec(ns);
6990
6991         return 0;
6992 }
6993
6994 static int
6995 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6996 {
6997         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6998         int count = 0;
6999         int g_ind = 0;
7000         const struct reg_info *reg_group;
7001         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7002                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7003
7004         while ((reg_group = reg_set[g_ind++]))
7005                 count += ixgbe_regs_group_count(reg_group);
7006
7007         return count;
7008 }
7009
7010 static int
7011 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7012 {
7013         int count = 0;
7014         int g_ind = 0;
7015         const struct reg_info *reg_group;
7016
7017         while ((reg_group = ixgbevf_regs[g_ind++]))
7018                 count += ixgbe_regs_group_count(reg_group);
7019
7020         return count;
7021 }
7022
7023 static int
7024 ixgbe_get_regs(struct rte_eth_dev *dev,
7025               struct rte_dev_reg_info *regs)
7026 {
7027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7028         uint32_t *data = regs->data;
7029         int g_ind = 0;
7030         int count = 0;
7031         const struct reg_info *reg_group;
7032         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7033                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7034
7035         if (data == NULL) {
7036                 regs->length = ixgbe_get_reg_length(dev);
7037                 regs->width = sizeof(uint32_t);
7038                 return 0;
7039         }
7040
7041         /* Support only full register dump */
7042         if ((regs->length == 0) ||
7043             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7044                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7045                         hw->device_id;
7046                 while ((reg_group = reg_set[g_ind++]))
7047                         count += ixgbe_read_regs_group(dev, &data[count],
7048                                 reg_group);
7049                 return 0;
7050         }
7051
7052         return -ENOTSUP;
7053 }
7054
7055 static int
7056 ixgbevf_get_regs(struct rte_eth_dev *dev,
7057                 struct rte_dev_reg_info *regs)
7058 {
7059         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7060         uint32_t *data = regs->data;
7061         int g_ind = 0;
7062         int count = 0;
7063         const struct reg_info *reg_group;
7064
7065         if (data == NULL) {
7066                 regs->length = ixgbevf_get_reg_length(dev);
7067                 regs->width = sizeof(uint32_t);
7068                 return 0;
7069         }
7070
7071         /* Support only full register dump */
7072         if ((regs->length == 0) ||
7073             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7074                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7075                         hw->device_id;
7076                 while ((reg_group = ixgbevf_regs[g_ind++]))
7077                         count += ixgbe_read_regs_group(dev, &data[count],
7078                                                       reg_group);
7079                 return 0;
7080         }
7081
7082         return -ENOTSUP;
7083 }
7084
7085 static int
7086 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7087 {
7088         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7089
7090         /* Return unit is byte count */
7091         return hw->eeprom.word_size * 2;
7092 }
7093
7094 static int
7095 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7096                 struct rte_dev_eeprom_info *in_eeprom)
7097 {
7098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7099         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7100         uint16_t *data = in_eeprom->data;
7101         int first, length;
7102
7103         first = in_eeprom->offset >> 1;
7104         length = in_eeprom->length >> 1;
7105         if ((first > hw->eeprom.word_size) ||
7106             ((first + length) > hw->eeprom.word_size))
7107                 return -EINVAL;
7108
7109         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7110
7111         return eeprom->ops.read_buffer(hw, first, length, data);
7112 }
7113
7114 static int
7115 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7116                 struct rte_dev_eeprom_info *in_eeprom)
7117 {
7118         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7119         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7120         uint16_t *data = in_eeprom->data;
7121         int first, length;
7122
7123         first = in_eeprom->offset >> 1;
7124         length = in_eeprom->length >> 1;
7125         if ((first > hw->eeprom.word_size) ||
7126             ((first + length) > hw->eeprom.word_size))
7127                 return -EINVAL;
7128
7129         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7130
7131         return eeprom->ops.write_buffer(hw,  first, length, data);
7132 }
7133
7134 static int
7135 ixgbe_get_module_info(struct rte_eth_dev *dev,
7136                       struct rte_eth_dev_module_info *modinfo)
7137 {
7138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7139         uint32_t status;
7140         uint8_t sff8472_rev, addr_mode;
7141         bool page_swap = false;
7142
7143         /* Check whether we support SFF-8472 or not */
7144         status = hw->phy.ops.read_i2c_eeprom(hw,
7145                                              IXGBE_SFF_SFF_8472_COMP,
7146                                              &sff8472_rev);
7147         if (status != 0)
7148                 return -EIO;
7149
7150         /* addressing mode is not supported */
7151         status = hw->phy.ops.read_i2c_eeprom(hw,
7152                                              IXGBE_SFF_SFF_8472_SWAP,
7153                                              &addr_mode);
7154         if (status != 0)
7155                 return -EIO;
7156
7157         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7158                 PMD_DRV_LOG(ERR,
7159                             "Address change required to access page 0xA2, "
7160                             "but not supported. Please report the module "
7161                             "type to the driver maintainers.");
7162                 page_swap = true;
7163         }
7164
7165         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7166                 /* We have a SFP, but it does not support SFF-8472 */
7167                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7168                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7169         } else {
7170                 /* We have a SFP which supports a revision of SFF-8472. */
7171                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7172                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7173         }
7174
7175         return 0;
7176 }
7177
7178 static int
7179 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7180                         struct rte_dev_eeprom_info *info)
7181 {
7182         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7183         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7184         uint8_t databyte = 0xFF;
7185         uint8_t *data = info->data;
7186         uint32_t i = 0;
7187
7188         if (info->length == 0)
7189                 return -EINVAL;
7190
7191         for (i = info->offset; i < info->offset + info->length; i++) {
7192                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7193                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7194                 else
7195                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7196
7197                 if (status != 0)
7198                         return -EIO;
7199
7200                 data[i - info->offset] = databyte;
7201         }
7202
7203         return 0;
7204 }
7205
7206 uint16_t
7207 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7208         switch (mac_type) {
7209         case ixgbe_mac_X550:
7210         case ixgbe_mac_X550EM_x:
7211         case ixgbe_mac_X550EM_a:
7212                 return ETH_RSS_RETA_SIZE_512;
7213         case ixgbe_mac_X550_vf:
7214         case ixgbe_mac_X550EM_x_vf:
7215         case ixgbe_mac_X550EM_a_vf:
7216                 return ETH_RSS_RETA_SIZE_64;
7217         default:
7218                 return ETH_RSS_RETA_SIZE_128;
7219         }
7220 }
7221
7222 uint32_t
7223 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7224         switch (mac_type) {
7225         case ixgbe_mac_X550:
7226         case ixgbe_mac_X550EM_x:
7227         case ixgbe_mac_X550EM_a:
7228                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7229                         return IXGBE_RETA(reta_idx >> 2);
7230                 else
7231                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7232         case ixgbe_mac_X550_vf:
7233         case ixgbe_mac_X550EM_x_vf:
7234         case ixgbe_mac_X550EM_a_vf:
7235                 return IXGBE_VFRETA(reta_idx >> 2);
7236         default:
7237                 return IXGBE_RETA(reta_idx >> 2);
7238         }
7239 }
7240
7241 uint32_t
7242 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7243         switch (mac_type) {
7244         case ixgbe_mac_X550_vf:
7245         case ixgbe_mac_X550EM_x_vf:
7246         case ixgbe_mac_X550EM_a_vf:
7247                 return IXGBE_VFMRQC;
7248         default:
7249                 return IXGBE_MRQC;
7250         }
7251 }
7252
7253 uint32_t
7254 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7255         switch (mac_type) {
7256         case ixgbe_mac_X550_vf:
7257         case ixgbe_mac_X550EM_x_vf:
7258         case ixgbe_mac_X550EM_a_vf:
7259                 return IXGBE_VFRSSRK(i);
7260         default:
7261                 return IXGBE_RSSRK(i);
7262         }
7263 }
7264
7265 bool
7266 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7267         switch (mac_type) {
7268         case ixgbe_mac_82599_vf:
7269         case ixgbe_mac_X540_vf:
7270                 return 0;
7271         default:
7272                 return 1;
7273         }
7274 }
7275
7276 static int
7277 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7278                         struct rte_eth_dcb_info *dcb_info)
7279 {
7280         struct ixgbe_dcb_config *dcb_config =
7281                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7282         struct ixgbe_dcb_tc_config *tc;
7283         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7284         uint8_t nb_tcs;
7285         uint8_t i, j;
7286
7287         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7288                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7289         else
7290                 dcb_info->nb_tcs = 1;
7291
7292         tc_queue = &dcb_info->tc_queue;
7293         nb_tcs = dcb_info->nb_tcs;
7294
7295         if (dcb_config->vt_mode) { /* vt is enabled*/
7296                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7297                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7298                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7299                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7300                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7301                         for (j = 0; j < nb_tcs; j++) {
7302                                 tc_queue->tc_rxq[0][j].base = j;
7303                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7304                                 tc_queue->tc_txq[0][j].base = j;
7305                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7306                         }
7307                 } else {
7308                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7309                                 for (j = 0; j < nb_tcs; j++) {
7310                                         tc_queue->tc_rxq[i][j].base =
7311                                                 i * nb_tcs + j;
7312                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7313                                         tc_queue->tc_txq[i][j].base =
7314                                                 i * nb_tcs + j;
7315                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7316                                 }
7317                         }
7318                 }
7319         } else { /* vt is disabled*/
7320                 struct rte_eth_dcb_rx_conf *rx_conf =
7321                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7322                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7323                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7324                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7325                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7326                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7327                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7328                         }
7329                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7330                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7331                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7332                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7333                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7334                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7335                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7336                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7337                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7338                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7339                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7340                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7341                         }
7342                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7343                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7344                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7345                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7346                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7347                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7348                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7349                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7350                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7351                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7352                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7353                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7354                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7355                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7356                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7357                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7358                 }
7359         }
7360         for (i = 0; i < dcb_info->nb_tcs; i++) {
7361                 tc = &dcb_config->tc_config[i];
7362                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7363         }
7364         return 0;
7365 }
7366
7367 /* Update e-tag ether type */
7368 static int
7369 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7370                             uint16_t ether_type)
7371 {
7372         uint32_t etag_etype;
7373
7374         if (hw->mac.type != ixgbe_mac_X550 &&
7375             hw->mac.type != ixgbe_mac_X550EM_x &&
7376             hw->mac.type != ixgbe_mac_X550EM_a) {
7377                 return -ENOTSUP;
7378         }
7379
7380         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7381         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7382         etag_etype |= ether_type;
7383         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7384         IXGBE_WRITE_FLUSH(hw);
7385
7386         return 0;
7387 }
7388
7389 /* Config l2 tunnel ether type */
7390 static int
7391 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7392                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7393 {
7394         int ret = 0;
7395         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7396         struct ixgbe_l2_tn_info *l2_tn_info =
7397                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7398
7399         if (l2_tunnel == NULL)
7400                 return -EINVAL;
7401
7402         switch (l2_tunnel->l2_tunnel_type) {
7403         case RTE_L2_TUNNEL_TYPE_E_TAG:
7404                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7405                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7406                 break;
7407         default:
7408                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7409                 ret = -EINVAL;
7410                 break;
7411         }
7412
7413         return ret;
7414 }
7415
7416 /* Enable e-tag tunnel */
7417 static int
7418 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7419 {
7420         uint32_t etag_etype;
7421
7422         if (hw->mac.type != ixgbe_mac_X550 &&
7423             hw->mac.type != ixgbe_mac_X550EM_x &&
7424             hw->mac.type != ixgbe_mac_X550EM_a) {
7425                 return -ENOTSUP;
7426         }
7427
7428         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7429         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7430         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7431         IXGBE_WRITE_FLUSH(hw);
7432
7433         return 0;
7434 }
7435
7436 /* Enable l2 tunnel */
7437 static int
7438 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7439                            enum rte_eth_tunnel_type l2_tunnel_type)
7440 {
7441         int ret = 0;
7442         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7443         struct ixgbe_l2_tn_info *l2_tn_info =
7444                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7445
7446         switch (l2_tunnel_type) {
7447         case RTE_L2_TUNNEL_TYPE_E_TAG:
7448                 l2_tn_info->e_tag_en = TRUE;
7449                 ret = ixgbe_e_tag_enable(hw);
7450                 break;
7451         default:
7452                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7453                 ret = -EINVAL;
7454                 break;
7455         }
7456
7457         return ret;
7458 }
7459
7460 /* Disable e-tag tunnel */
7461 static int
7462 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7463 {
7464         uint32_t etag_etype;
7465
7466         if (hw->mac.type != ixgbe_mac_X550 &&
7467             hw->mac.type != ixgbe_mac_X550EM_x &&
7468             hw->mac.type != ixgbe_mac_X550EM_a) {
7469                 return -ENOTSUP;
7470         }
7471
7472         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7473         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7474         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7475         IXGBE_WRITE_FLUSH(hw);
7476
7477         return 0;
7478 }
7479
7480 /* Disable l2 tunnel */
7481 static int
7482 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7483                             enum rte_eth_tunnel_type l2_tunnel_type)
7484 {
7485         int ret = 0;
7486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7487         struct ixgbe_l2_tn_info *l2_tn_info =
7488                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7489
7490         switch (l2_tunnel_type) {
7491         case RTE_L2_TUNNEL_TYPE_E_TAG:
7492                 l2_tn_info->e_tag_en = FALSE;
7493                 ret = ixgbe_e_tag_disable(hw);
7494                 break;
7495         default:
7496                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7497                 ret = -EINVAL;
7498                 break;
7499         }
7500
7501         return ret;
7502 }
7503
7504 static int
7505 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7506                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7507 {
7508         int ret = 0;
7509         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7510         uint32_t i, rar_entries;
7511         uint32_t rar_low, rar_high;
7512
7513         if (hw->mac.type != ixgbe_mac_X550 &&
7514             hw->mac.type != ixgbe_mac_X550EM_x &&
7515             hw->mac.type != ixgbe_mac_X550EM_a) {
7516                 return -ENOTSUP;
7517         }
7518
7519         rar_entries = ixgbe_get_num_rx_addrs(hw);
7520
7521         for (i = 1; i < rar_entries; i++) {
7522                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7523                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7524                 if ((rar_high & IXGBE_RAH_AV) &&
7525                     (rar_high & IXGBE_RAH_ADTYPE) &&
7526                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7527                      l2_tunnel->tunnel_id)) {
7528                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7529                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7530
7531                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7532
7533                         return ret;
7534                 }
7535         }
7536
7537         return ret;
7538 }
7539
7540 static int
7541 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7542                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7543 {
7544         int ret = 0;
7545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7546         uint32_t i, rar_entries;
7547         uint32_t rar_low, rar_high;
7548
7549         if (hw->mac.type != ixgbe_mac_X550 &&
7550             hw->mac.type != ixgbe_mac_X550EM_x &&
7551             hw->mac.type != ixgbe_mac_X550EM_a) {
7552                 return -ENOTSUP;
7553         }
7554
7555         /* One entry for one tunnel. Try to remove potential existing entry. */
7556         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7557
7558         rar_entries = ixgbe_get_num_rx_addrs(hw);
7559
7560         for (i = 1; i < rar_entries; i++) {
7561                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7562                 if (rar_high & IXGBE_RAH_AV) {
7563                         continue;
7564                 } else {
7565                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7566                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7567                         rar_low = l2_tunnel->tunnel_id;
7568
7569                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7570                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7571
7572                         return ret;
7573                 }
7574         }
7575
7576         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7577                      " Please remove a rule before adding a new one.");
7578         return -EINVAL;
7579 }
7580
7581 static inline struct ixgbe_l2_tn_filter *
7582 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7583                           struct ixgbe_l2_tn_key *key)
7584 {
7585         int ret;
7586
7587         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7588         if (ret < 0)
7589                 return NULL;
7590
7591         return l2_tn_info->hash_map[ret];
7592 }
7593
7594 static inline int
7595 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7596                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7597 {
7598         int ret;
7599
7600         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7601                                &l2_tn_filter->key);
7602
7603         if (ret < 0) {
7604                 PMD_DRV_LOG(ERR,
7605                             "Failed to insert L2 tunnel filter"
7606                             " to hash table %d!",
7607                             ret);
7608                 return ret;
7609         }
7610
7611         l2_tn_info->hash_map[ret] = l2_tn_filter;
7612
7613         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7614
7615         return 0;
7616 }
7617
7618 static inline int
7619 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7620                           struct ixgbe_l2_tn_key *key)
7621 {
7622         int ret;
7623         struct ixgbe_l2_tn_filter *l2_tn_filter;
7624
7625         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7626
7627         if (ret < 0) {
7628                 PMD_DRV_LOG(ERR,
7629                             "No such L2 tunnel filter to delete %d!",
7630                             ret);
7631                 return ret;
7632         }
7633
7634         l2_tn_filter = l2_tn_info->hash_map[ret];
7635         l2_tn_info->hash_map[ret] = NULL;
7636
7637         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7638         rte_free(l2_tn_filter);
7639
7640         return 0;
7641 }
7642
7643 /* Add l2 tunnel filter */
7644 int
7645 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7646                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7647                                bool restore)
7648 {
7649         int ret;
7650         struct ixgbe_l2_tn_info *l2_tn_info =
7651                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7652         struct ixgbe_l2_tn_key key;
7653         struct ixgbe_l2_tn_filter *node;
7654
7655         if (!restore) {
7656                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7657                 key.tn_id = l2_tunnel->tunnel_id;
7658
7659                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7660
7661                 if (node) {
7662                         PMD_DRV_LOG(ERR,
7663                                     "The L2 tunnel filter already exists!");
7664                         return -EINVAL;
7665                 }
7666
7667                 node = rte_zmalloc("ixgbe_l2_tn",
7668                                    sizeof(struct ixgbe_l2_tn_filter),
7669                                    0);
7670                 if (!node)
7671                         return -ENOMEM;
7672
7673                 rte_memcpy(&node->key,
7674                                  &key,
7675                                  sizeof(struct ixgbe_l2_tn_key));
7676                 node->pool = l2_tunnel->pool;
7677                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7678                 if (ret < 0) {
7679                         rte_free(node);
7680                         return ret;
7681                 }
7682         }
7683
7684         switch (l2_tunnel->l2_tunnel_type) {
7685         case RTE_L2_TUNNEL_TYPE_E_TAG:
7686                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7687                 break;
7688         default:
7689                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7690                 ret = -EINVAL;
7691                 break;
7692         }
7693
7694         if ((!restore) && (ret < 0))
7695                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7696
7697         return ret;
7698 }
7699
7700 /* Delete l2 tunnel filter */
7701 int
7702 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7703                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7704 {
7705         int ret;
7706         struct ixgbe_l2_tn_info *l2_tn_info =
7707                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7708         struct ixgbe_l2_tn_key key;
7709
7710         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7711         key.tn_id = l2_tunnel->tunnel_id;
7712         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7713         if (ret < 0)
7714                 return ret;
7715
7716         switch (l2_tunnel->l2_tunnel_type) {
7717         case RTE_L2_TUNNEL_TYPE_E_TAG:
7718                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7719                 break;
7720         default:
7721                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7722                 ret = -EINVAL;
7723                 break;
7724         }
7725
7726         return ret;
7727 }
7728
7729 /**
7730  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7731  * @dev: pointer to rte_eth_dev structure
7732  * @filter_op:operation will be taken.
7733  * @arg: a pointer to specific structure corresponding to the filter_op
7734  */
7735 static int
7736 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7737                                   enum rte_filter_op filter_op,
7738                                   void *arg)
7739 {
7740         int ret;
7741
7742         if (filter_op == RTE_ETH_FILTER_NOP)
7743                 return 0;
7744
7745         if (arg == NULL) {
7746                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7747                             filter_op);
7748                 return -EINVAL;
7749         }
7750
7751         switch (filter_op) {
7752         case RTE_ETH_FILTER_ADD:
7753                 ret = ixgbe_dev_l2_tunnel_filter_add
7754                         (dev,
7755                          (struct rte_eth_l2_tunnel_conf *)arg,
7756                          FALSE);
7757                 break;
7758         case RTE_ETH_FILTER_DELETE:
7759                 ret = ixgbe_dev_l2_tunnel_filter_del
7760                         (dev,
7761                          (struct rte_eth_l2_tunnel_conf *)arg);
7762                 break;
7763         default:
7764                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7765                 ret = -EINVAL;
7766                 break;
7767         }
7768         return ret;
7769 }
7770
7771 static int
7772 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7773 {
7774         int ret = 0;
7775         uint32_t ctrl;
7776         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7777
7778         if (hw->mac.type != ixgbe_mac_X550 &&
7779             hw->mac.type != ixgbe_mac_X550EM_x &&
7780             hw->mac.type != ixgbe_mac_X550EM_a) {
7781                 return -ENOTSUP;
7782         }
7783
7784         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7785         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7786         if (en)
7787                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7788         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7789
7790         return ret;
7791 }
7792
7793 /* Enable l2 tunnel forwarding */
7794 static int
7795 ixgbe_dev_l2_tunnel_forwarding_enable
7796         (struct rte_eth_dev *dev,
7797          enum rte_eth_tunnel_type l2_tunnel_type)
7798 {
7799         struct ixgbe_l2_tn_info *l2_tn_info =
7800                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7801         int ret = 0;
7802
7803         switch (l2_tunnel_type) {
7804         case RTE_L2_TUNNEL_TYPE_E_TAG:
7805                 l2_tn_info->e_tag_fwd_en = TRUE;
7806                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7807                 break;
7808         default:
7809                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7810                 ret = -EINVAL;
7811                 break;
7812         }
7813
7814         return ret;
7815 }
7816
7817 /* Disable l2 tunnel forwarding */
7818 static int
7819 ixgbe_dev_l2_tunnel_forwarding_disable
7820         (struct rte_eth_dev *dev,
7821          enum rte_eth_tunnel_type l2_tunnel_type)
7822 {
7823         struct ixgbe_l2_tn_info *l2_tn_info =
7824                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7825         int ret = 0;
7826
7827         switch (l2_tunnel_type) {
7828         case RTE_L2_TUNNEL_TYPE_E_TAG:
7829                 l2_tn_info->e_tag_fwd_en = FALSE;
7830                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7831                 break;
7832         default:
7833                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7834                 ret = -EINVAL;
7835                 break;
7836         }
7837
7838         return ret;
7839 }
7840
7841 static int
7842 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7843                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7844                              bool en)
7845 {
7846         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7847         int ret = 0;
7848         uint32_t vmtir, vmvir;
7849         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7850
7851         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7852                 PMD_DRV_LOG(ERR,
7853                             "VF id %u should be less than %u",
7854                             l2_tunnel->vf_id,
7855                             pci_dev->max_vfs);
7856                 return -EINVAL;
7857         }
7858
7859         if (hw->mac.type != ixgbe_mac_X550 &&
7860             hw->mac.type != ixgbe_mac_X550EM_x &&
7861             hw->mac.type != ixgbe_mac_X550EM_a) {
7862                 return -ENOTSUP;
7863         }
7864
7865         if (en)
7866                 vmtir = l2_tunnel->tunnel_id;
7867         else
7868                 vmtir = 0;
7869
7870         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7871
7872         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7873         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7874         if (en)
7875                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7876         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7877
7878         return ret;
7879 }
7880
7881 /* Enable l2 tunnel tag insertion */
7882 static int
7883 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7884                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7885 {
7886         int ret = 0;
7887
7888         switch (l2_tunnel->l2_tunnel_type) {
7889         case RTE_L2_TUNNEL_TYPE_E_TAG:
7890                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7891                 break;
7892         default:
7893                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7894                 ret = -EINVAL;
7895                 break;
7896         }
7897
7898         return ret;
7899 }
7900
7901 /* Disable l2 tunnel tag insertion */
7902 static int
7903 ixgbe_dev_l2_tunnel_insertion_disable
7904         (struct rte_eth_dev *dev,
7905          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7906 {
7907         int ret = 0;
7908
7909         switch (l2_tunnel->l2_tunnel_type) {
7910         case RTE_L2_TUNNEL_TYPE_E_TAG:
7911                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7912                 break;
7913         default:
7914                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7915                 ret = -EINVAL;
7916                 break;
7917         }
7918
7919         return ret;
7920 }
7921
7922 static int
7923 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7924                              bool en)
7925 {
7926         int ret = 0;
7927         uint32_t qde;
7928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7929
7930         if (hw->mac.type != ixgbe_mac_X550 &&
7931             hw->mac.type != ixgbe_mac_X550EM_x &&
7932             hw->mac.type != ixgbe_mac_X550EM_a) {
7933                 return -ENOTSUP;
7934         }
7935
7936         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7937         if (en)
7938                 qde |= IXGBE_QDE_STRIP_TAG;
7939         else
7940                 qde &= ~IXGBE_QDE_STRIP_TAG;
7941         qde &= ~IXGBE_QDE_READ;
7942         qde |= IXGBE_QDE_WRITE;
7943         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7944
7945         return ret;
7946 }
7947
7948 /* Enable l2 tunnel tag stripping */
7949 static int
7950 ixgbe_dev_l2_tunnel_stripping_enable
7951         (struct rte_eth_dev *dev,
7952          enum rte_eth_tunnel_type l2_tunnel_type)
7953 {
7954         int ret = 0;
7955
7956         switch (l2_tunnel_type) {
7957         case RTE_L2_TUNNEL_TYPE_E_TAG:
7958                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7959                 break;
7960         default:
7961                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7962                 ret = -EINVAL;
7963                 break;
7964         }
7965
7966         return ret;
7967 }
7968
7969 /* Disable l2 tunnel tag stripping */
7970 static int
7971 ixgbe_dev_l2_tunnel_stripping_disable
7972         (struct rte_eth_dev *dev,
7973          enum rte_eth_tunnel_type l2_tunnel_type)
7974 {
7975         int ret = 0;
7976
7977         switch (l2_tunnel_type) {
7978         case RTE_L2_TUNNEL_TYPE_E_TAG:
7979                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7980                 break;
7981         default:
7982                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7983                 ret = -EINVAL;
7984                 break;
7985         }
7986
7987         return ret;
7988 }
7989
7990 /* Enable/disable l2 tunnel offload functions */
7991 static int
7992 ixgbe_dev_l2_tunnel_offload_set
7993         (struct rte_eth_dev *dev,
7994          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7995          uint32_t mask,
7996          uint8_t en)
7997 {
7998         int ret = 0;
7999
8000         if (l2_tunnel == NULL)
8001                 return -EINVAL;
8002
8003         ret = -EINVAL;
8004         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8005                 if (en)
8006                         ret = ixgbe_dev_l2_tunnel_enable(
8007                                 dev,
8008                                 l2_tunnel->l2_tunnel_type);
8009                 else
8010                         ret = ixgbe_dev_l2_tunnel_disable(
8011                                 dev,
8012                                 l2_tunnel->l2_tunnel_type);
8013         }
8014
8015         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8016                 if (en)
8017                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8018                                 dev,
8019                                 l2_tunnel);
8020                 else
8021                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8022                                 dev,
8023                                 l2_tunnel);
8024         }
8025
8026         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8027                 if (en)
8028                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8029                                 dev,
8030                                 l2_tunnel->l2_tunnel_type);
8031                 else
8032                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8033                                 dev,
8034                                 l2_tunnel->l2_tunnel_type);
8035         }
8036
8037         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8038                 if (en)
8039                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8040                                 dev,
8041                                 l2_tunnel->l2_tunnel_type);
8042                 else
8043                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8044                                 dev,
8045                                 l2_tunnel->l2_tunnel_type);
8046         }
8047
8048         return ret;
8049 }
8050
8051 static int
8052 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8053                         uint16_t port)
8054 {
8055         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8056         IXGBE_WRITE_FLUSH(hw);
8057
8058         return 0;
8059 }
8060
8061 /* There's only one register for VxLAN UDP port.
8062  * So, we cannot add several ports. Will update it.
8063  */
8064 static int
8065 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8066                      uint16_t port)
8067 {
8068         if (port == 0) {
8069                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8070                 return -EINVAL;
8071         }
8072
8073         return ixgbe_update_vxlan_port(hw, port);
8074 }
8075
8076 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8077  * UDP port, it must have a value.
8078  * So, will reset it to the original value 0.
8079  */
8080 static int
8081 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8082                      uint16_t port)
8083 {
8084         uint16_t cur_port;
8085
8086         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8087
8088         if (cur_port != port) {
8089                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8090                 return -EINVAL;
8091         }
8092
8093         return ixgbe_update_vxlan_port(hw, 0);
8094 }
8095
8096 /* Add UDP tunneling port */
8097 static int
8098 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8099                               struct rte_eth_udp_tunnel *udp_tunnel)
8100 {
8101         int ret = 0;
8102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8103
8104         if (hw->mac.type != ixgbe_mac_X550 &&
8105             hw->mac.type != ixgbe_mac_X550EM_x &&
8106             hw->mac.type != ixgbe_mac_X550EM_a) {
8107                 return -ENOTSUP;
8108         }
8109
8110         if (udp_tunnel == NULL)
8111                 return -EINVAL;
8112
8113         switch (udp_tunnel->prot_type) {
8114         case RTE_TUNNEL_TYPE_VXLAN:
8115                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8116                 break;
8117
8118         case RTE_TUNNEL_TYPE_GENEVE:
8119         case RTE_TUNNEL_TYPE_TEREDO:
8120                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8121                 ret = -EINVAL;
8122                 break;
8123
8124         default:
8125                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8126                 ret = -EINVAL;
8127                 break;
8128         }
8129
8130         return ret;
8131 }
8132
8133 /* Remove UDP tunneling port */
8134 static int
8135 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8136                               struct rte_eth_udp_tunnel *udp_tunnel)
8137 {
8138         int ret = 0;
8139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8140
8141         if (hw->mac.type != ixgbe_mac_X550 &&
8142             hw->mac.type != ixgbe_mac_X550EM_x &&
8143             hw->mac.type != ixgbe_mac_X550EM_a) {
8144                 return -ENOTSUP;
8145         }
8146
8147         if (udp_tunnel == NULL)
8148                 return -EINVAL;
8149
8150         switch (udp_tunnel->prot_type) {
8151         case RTE_TUNNEL_TYPE_VXLAN:
8152                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8153                 break;
8154         case RTE_TUNNEL_TYPE_GENEVE:
8155         case RTE_TUNNEL_TYPE_TEREDO:
8156                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8157                 ret = -EINVAL;
8158                 break;
8159         default:
8160                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8161                 ret = -EINVAL;
8162                 break;
8163         }
8164
8165         return ret;
8166 }
8167
8168 static void
8169 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8170 {
8171         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8172
8173         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8174 }
8175
8176 static void
8177 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8178 {
8179         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8180
8181         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8182 }
8183
8184 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8185 {
8186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8187         u32 in_msg = 0;
8188
8189         /* peek the message first */
8190         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8191
8192         /* PF reset VF event */
8193         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8194                 /* dummy mbx read to ack pf */
8195                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8196                         return;
8197                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8198                                               NULL);
8199         }
8200 }
8201
8202 static int
8203 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8204 {
8205         uint32_t eicr;
8206         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8207         struct ixgbe_interrupt *intr =
8208                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8209         ixgbevf_intr_disable(hw);
8210
8211         /* read-on-clear nic registers here */
8212         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8213         intr->flags = 0;
8214
8215         /* only one misc vector supported - mailbox */
8216         eicr &= IXGBE_VTEICR_MASK;
8217         if (eicr == IXGBE_MISC_VEC_ID)
8218                 intr->flags |= IXGBE_FLAG_MAILBOX;
8219
8220         return 0;
8221 }
8222
8223 static int
8224 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8225 {
8226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8227         struct ixgbe_interrupt *intr =
8228                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8229
8230         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8231                 ixgbevf_mbx_process(dev);
8232                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8233         }
8234
8235         ixgbevf_intr_enable(hw);
8236
8237         return 0;
8238 }
8239
8240 static void
8241 ixgbevf_dev_interrupt_handler(void *param)
8242 {
8243         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8244
8245         ixgbevf_dev_interrupt_get_status(dev);
8246         ixgbevf_dev_interrupt_action(dev);
8247 }
8248
8249 /**
8250  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8251  *  @hw: pointer to hardware structure
8252  *
8253  *  Stops the transmit data path and waits for the HW to internally empty
8254  *  the Tx security block
8255  **/
8256 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8257 {
8258 #define IXGBE_MAX_SECTX_POLL 40
8259
8260         int i;
8261         int sectxreg;
8262
8263         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8264         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8265         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8266         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8267                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8268                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8269                         break;
8270                 /* Use interrupt-safe sleep just in case */
8271                 usec_delay(1000);
8272         }
8273
8274         /* For informational purposes only */
8275         if (i >= IXGBE_MAX_SECTX_POLL)
8276                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8277                          "path fully disabled.  Continuing with init.");
8278
8279         return IXGBE_SUCCESS;
8280 }
8281
8282 /**
8283  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8284  *  @hw: pointer to hardware structure
8285  *
8286  *  Enables the transmit data path.
8287  **/
8288 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8289 {
8290         uint32_t sectxreg;
8291
8292         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8293         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8294         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8295         IXGBE_WRITE_FLUSH(hw);
8296
8297         return IXGBE_SUCCESS;
8298 }
8299
8300 /* restore n-tuple filter */
8301 static inline void
8302 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8303 {
8304         struct ixgbe_filter_info *filter_info =
8305                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8306         struct ixgbe_5tuple_filter *node;
8307
8308         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8309                 ixgbe_inject_5tuple_filter(dev, node);
8310         }
8311 }
8312
8313 /* restore ethernet type filter */
8314 static inline void
8315 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8316 {
8317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8318         struct ixgbe_filter_info *filter_info =
8319                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8320         int i;
8321
8322         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8323                 if (filter_info->ethertype_mask & (1 << i)) {
8324                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8325                                         filter_info->ethertype_filters[i].etqf);
8326                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8327                                         filter_info->ethertype_filters[i].etqs);
8328                         IXGBE_WRITE_FLUSH(hw);
8329                 }
8330         }
8331 }
8332
8333 /* restore SYN filter */
8334 static inline void
8335 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8336 {
8337         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8338         struct ixgbe_filter_info *filter_info =
8339                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8340         uint32_t synqf;
8341
8342         synqf = filter_info->syn_info;
8343
8344         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8345                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8346                 IXGBE_WRITE_FLUSH(hw);
8347         }
8348 }
8349
8350 /* restore L2 tunnel filter */
8351 static inline void
8352 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8353 {
8354         struct ixgbe_l2_tn_info *l2_tn_info =
8355                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8356         struct ixgbe_l2_tn_filter *node;
8357         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8358
8359         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8360                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8361                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8362                 l2_tn_conf.pool           = node->pool;
8363                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8364         }
8365 }
8366
8367 /* restore rss filter */
8368 static inline void
8369 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8370 {
8371         struct ixgbe_filter_info *filter_info =
8372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8373
8374         if (filter_info->rss_info.num)
8375                 ixgbe_config_rss_filter(dev,
8376                         &filter_info->rss_info, TRUE);
8377 }
8378
8379 static int
8380 ixgbe_filter_restore(struct rte_eth_dev *dev)
8381 {
8382         ixgbe_ntuple_filter_restore(dev);
8383         ixgbe_ethertype_filter_restore(dev);
8384         ixgbe_syn_filter_restore(dev);
8385         ixgbe_fdir_filter_restore(dev);
8386         ixgbe_l2_tn_filter_restore(dev);
8387         ixgbe_rss_filter_restore(dev);
8388
8389         return 0;
8390 }
8391
8392 static void
8393 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8394 {
8395         struct ixgbe_l2_tn_info *l2_tn_info =
8396                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8397         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8398
8399         if (l2_tn_info->e_tag_en)
8400                 (void)ixgbe_e_tag_enable(hw);
8401
8402         if (l2_tn_info->e_tag_fwd_en)
8403                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8404
8405         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8406 }
8407
8408 /* remove all the n-tuple filters */
8409 void
8410 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8411 {
8412         struct ixgbe_filter_info *filter_info =
8413                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8414         struct ixgbe_5tuple_filter *p_5tuple;
8415
8416         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8417                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8418 }
8419
8420 /* remove all the ether type filters */
8421 void
8422 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8423 {
8424         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8425         struct ixgbe_filter_info *filter_info =
8426                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8427         int i;
8428
8429         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8430                 if (filter_info->ethertype_mask & (1 << i) &&
8431                     !filter_info->ethertype_filters[i].conf) {
8432                         (void)ixgbe_ethertype_filter_remove(filter_info,
8433                                                             (uint8_t)i);
8434                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8435                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8436                         IXGBE_WRITE_FLUSH(hw);
8437                 }
8438         }
8439 }
8440
8441 /* remove the SYN filter */
8442 void
8443 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8444 {
8445         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8446         struct ixgbe_filter_info *filter_info =
8447                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8448
8449         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8450                 filter_info->syn_info = 0;
8451
8452                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8453                 IXGBE_WRITE_FLUSH(hw);
8454         }
8455 }
8456
8457 /* remove all the L2 tunnel filters */
8458 int
8459 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8460 {
8461         struct ixgbe_l2_tn_info *l2_tn_info =
8462                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8463         struct ixgbe_l2_tn_filter *l2_tn_filter;
8464         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8465         int ret = 0;
8466
8467         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8468                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8469                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8470                 l2_tn_conf.pool           = l2_tn_filter->pool;
8471                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8472                 if (ret < 0)
8473                         return ret;
8474         }
8475
8476         return 0;
8477 }
8478
8479 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8480 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8481 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8482 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8483 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8484 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8485
8486 RTE_INIT(ixgbe_init_log);
8487 static void
8488 ixgbe_init_log(void)
8489 {
8490         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8491         if (ixgbe_logtype_init >= 0)
8492                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8493         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8494         if (ixgbe_logtype_driver >= 0)
8495                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
8496 }