1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
31 #include <rte_random.h>
33 #include <rte_hash_crc.h>
34 #ifdef RTE_LIBRTE_SECURITY
35 #include <rte_security_driver.h>
38 #include "ixgbe_logs.h"
39 #include "base/ixgbe_api.h"
40 #include "base/ixgbe_vf.h"
41 #include "base/ixgbe_common.h"
42 #include "ixgbe_ethdev.h"
43 #include "ixgbe_bypass.h"
44 #include "ixgbe_rxtx.h"
45 #include "base/ixgbe_type.h"
46 #include "base/ixgbe_phy.h"
47 #include "ixgbe_regs.h"
50 * High threshold controlling when to start sending XOFF frames. Must be at
51 * least 8 bytes less than receive packet buffer size. This value is in units
54 #define IXGBE_FC_HI 0x80
57 * Low threshold controlling when to start sending XON frames. This value is
58 * in units of 1024 bytes.
60 #define IXGBE_FC_LO 0x40
62 /* Timer value included in XOFF frames. */
63 #define IXGBE_FC_PAUSE 0x680
65 /*Default value of Max Rx Queue*/
66 #define IXGBE_MAX_RX_QUEUE_NUM 128
68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
69 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
70 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
72 #define IXGBE_MMW_SIZE_DEFAULT 0x4
73 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
74 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
77 * Default values for RX/TX configuration
79 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
80 #define IXGBE_DEFAULT_RX_PTHRESH 8
81 #define IXGBE_DEFAULT_RX_HTHRESH 8
82 #define IXGBE_DEFAULT_RX_WTHRESH 0
84 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
85 #define IXGBE_DEFAULT_TX_PTHRESH 32
86 #define IXGBE_DEFAULT_TX_HTHRESH 0
87 #define IXGBE_DEFAULT_TX_WTHRESH 0
88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
90 /* Bit shift and mask */
91 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
92 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
93 #define IXGBE_8_BIT_WIDTH CHAR_BIT
94 #define IXGBE_8_BIT_MASK UINT8_MAX
96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
100 /* Additional timesync values. */
101 #define NSEC_PER_SEC 1000000000L
102 #define IXGBE_INCVAL_10GB 0x66666666
103 #define IXGBE_INCVAL_1GB 0x40000000
104 #define IXGBE_INCVAL_100 0x50000000
105 #define IXGBE_INCVAL_SHIFT_10GB 28
106 #define IXGBE_INCVAL_SHIFT_1GB 24
107 #define IXGBE_INCVAL_SHIFT_100 21
108 #define IXGBE_INCVAL_SHIFT_82599 7
109 #define IXGBE_INCPER_SHIFT_82599 24
111 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
113 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
115 #define IXGBE_ETAG_ETYPE 0x00005084
116 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
117 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
118 #define IXGBE_RAH_ADTYPE 0x40000000
119 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
120 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
123 #define IXGBE_QDE_STRIP_TAG 0x00000004
124 #define IXGBE_VTEICR_MASK 0x07
126 #define IXGBE_EXVET_VET_EXT_SHIFT 16
127 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
136 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
137 static int ixgbe_dev_start(struct rte_eth_dev *dev);
138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
142 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
148 int wait_to_complete);
149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
150 struct rte_eth_stats *stats);
151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
152 struct rte_eth_xstat *xstats, unsigned n);
153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
154 struct rte_eth_xstat *xstats, unsigned n);
156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
157 uint64_t *values, unsigned int n);
158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
161 struct rte_eth_xstat_name *xstats_names,
163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
164 struct rte_eth_xstat_name *xstats_names, unsigned limit);
165 static int ixgbe_dev_xstats_get_names_by_id(
166 struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names,
170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
177 struct rte_eth_dev_info *dev_info);
178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
180 struct rte_eth_dev_info *dev_info);
181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
184 uint16_t vlan_id, int on);
185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
186 enum rte_vlan_type vlan_type,
188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
189 uint16_t queue, bool on);
190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
204 struct rte_eth_fc_conf *fc_conf);
205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
206 struct rte_eth_fc_conf *fc_conf);
207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
208 struct rte_eth_pfc_conf *pfc_conf);
209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
210 struct rte_eth_rss_reta_entry64 *reta_conf,
212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
221 static void ixgbe_dev_interrupt_handler(void *param);
222 static void ixgbe_dev_interrupt_delayed_handler(void *param);
223 static void ixgbe_dev_setup_link_alarm_handler(void *param);
225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
226 uint32_t index, uint32_t pool);
227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
229 struct ether_addr *mac_addr);
230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
231 static bool is_device_supported(struct rte_eth_dev *dev,
232 struct rte_pci_driver *drv);
234 /* For Virtual Function support */
235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
237 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
238 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
240 int wait_to_complete);
241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
242 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
243 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
247 struct rte_eth_stats *stats);
248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
250 uint16_t vlan_id, int on);
251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
252 uint16_t queue, int on);
253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
261 uint8_t queue, uint8_t msix_vector);
262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
263 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
264 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
266 /* For Eth VMDQ APIs support */
267 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
268 ether_addr * mac_addr, uint8_t on);
269 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
270 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
271 struct rte_eth_mirror_conf *mirror_conf,
272 uint8_t rule_id, uint8_t on);
273 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
275 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
277 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
279 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
280 uint8_t queue, uint8_t msix_vector);
281 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
283 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
284 struct ether_addr *mac_addr,
285 uint32_t index, uint32_t pool);
286 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
287 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
288 struct ether_addr *mac_addr);
289 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
290 struct rte_eth_syn_filter *filter);
291 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
292 enum rte_filter_op filter_op,
294 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
295 struct ixgbe_5tuple_filter *filter);
296 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
297 struct ixgbe_5tuple_filter *filter);
298 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
299 enum rte_filter_op filter_op,
301 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
302 struct rte_eth_ntuple_filter *filter);
303 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
304 enum rte_filter_op filter_op,
306 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
307 struct rte_eth_ethertype_filter *filter);
308 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
309 enum rte_filter_type filter_type,
310 enum rte_filter_op filter_op,
312 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
314 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
315 struct ether_addr *mc_addr_set,
316 uint32_t nb_mc_addr);
317 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
318 struct rte_eth_dcb_info *dcb_info);
320 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
321 static int ixgbe_get_regs(struct rte_eth_dev *dev,
322 struct rte_dev_reg_info *regs);
323 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
324 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
325 struct rte_dev_eeprom_info *eeprom);
326 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
327 struct rte_dev_eeprom_info *eeprom);
329 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
330 struct rte_eth_dev_module_info *modinfo);
331 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
332 struct rte_dev_eeprom_info *info);
334 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
335 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
336 struct rte_dev_reg_info *regs);
338 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
339 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
340 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
341 struct timespec *timestamp,
343 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
344 struct timespec *timestamp);
345 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
346 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
347 struct timespec *timestamp);
348 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
349 const struct timespec *timestamp);
350 static void ixgbevf_dev_interrupt_handler(void *param);
352 static int ixgbe_dev_l2_tunnel_eth_type_conf
353 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
354 static int ixgbe_dev_l2_tunnel_offload_set
355 (struct rte_eth_dev *dev,
356 struct rte_eth_l2_tunnel_conf *l2_tunnel,
359 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
360 enum rte_filter_op filter_op,
363 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
364 struct rte_eth_udp_tunnel *udp_tunnel);
365 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
366 struct rte_eth_udp_tunnel *udp_tunnel);
367 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
368 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
371 * Define VF Stats MACRO for Non "cleared on read" register
373 #define UPDATE_VF_STAT(reg, last, cur) \
375 uint32_t latest = IXGBE_READ_REG(hw, reg); \
376 cur += (latest - last) & UINT_MAX; \
380 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
382 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
383 u64 new_msb = IXGBE_READ_REG(hw, msb); \
384 u64 latest = ((new_msb << 32) | new_lsb); \
385 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
389 #define IXGBE_SET_HWSTRIP(h, q) do {\
390 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
391 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
392 (h)->bitmap[idx] |= 1 << bit;\
395 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
396 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
397 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
398 (h)->bitmap[idx] &= ~(1 << bit);\
401 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
404 (r) = (h)->bitmap[idx] >> bit & 1;\
407 int ixgbe_logtype_init;
408 int ixgbe_logtype_driver;
411 * The set of PCI devices this driver supports
413 static const struct rte_pci_id pci_id_ixgbe_map[] = {
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
461 #ifdef RTE_LIBRTE_IXGBE_BYPASS
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
464 { .vendor_id = 0, /* sentinel */ },
468 * The set of PCI devices this driver supports (for 82599 VF)
470 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
481 { .vendor_id = 0, /* sentinel */ },
484 static const struct rte_eth_desc_lim rx_desc_lim = {
485 .nb_max = IXGBE_MAX_RING_DESC,
486 .nb_min = IXGBE_MIN_RING_DESC,
487 .nb_align = IXGBE_RXD_ALIGN,
490 static const struct rte_eth_desc_lim tx_desc_lim = {
491 .nb_max = IXGBE_MAX_RING_DESC,
492 .nb_min = IXGBE_MIN_RING_DESC,
493 .nb_align = IXGBE_TXD_ALIGN,
494 .nb_seg_max = IXGBE_TX_MAX_SEG,
495 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
498 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
499 .dev_configure = ixgbe_dev_configure,
500 .dev_start = ixgbe_dev_start,
501 .dev_stop = ixgbe_dev_stop,
502 .dev_set_link_up = ixgbe_dev_set_link_up,
503 .dev_set_link_down = ixgbe_dev_set_link_down,
504 .dev_close = ixgbe_dev_close,
505 .dev_reset = ixgbe_dev_reset,
506 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
507 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
508 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
509 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
510 .link_update = ixgbe_dev_link_update,
511 .stats_get = ixgbe_dev_stats_get,
512 .xstats_get = ixgbe_dev_xstats_get,
513 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
514 .stats_reset = ixgbe_dev_stats_reset,
515 .xstats_reset = ixgbe_dev_xstats_reset,
516 .xstats_get_names = ixgbe_dev_xstats_get_names,
517 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
518 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
519 .fw_version_get = ixgbe_fw_version_get,
520 .dev_infos_get = ixgbe_dev_info_get,
521 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
522 .mtu_set = ixgbe_dev_mtu_set,
523 .vlan_filter_set = ixgbe_vlan_filter_set,
524 .vlan_tpid_set = ixgbe_vlan_tpid_set,
525 .vlan_offload_set = ixgbe_vlan_offload_set,
526 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
527 .rx_queue_start = ixgbe_dev_rx_queue_start,
528 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
529 .tx_queue_start = ixgbe_dev_tx_queue_start,
530 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
531 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
532 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
533 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
534 .rx_queue_release = ixgbe_dev_rx_queue_release,
535 .rx_queue_count = ixgbe_dev_rx_queue_count,
536 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
537 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
538 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
539 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
540 .tx_queue_release = ixgbe_dev_tx_queue_release,
541 .dev_led_on = ixgbe_dev_led_on,
542 .dev_led_off = ixgbe_dev_led_off,
543 .flow_ctrl_get = ixgbe_flow_ctrl_get,
544 .flow_ctrl_set = ixgbe_flow_ctrl_set,
545 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
546 .mac_addr_add = ixgbe_add_rar,
547 .mac_addr_remove = ixgbe_remove_rar,
548 .mac_addr_set = ixgbe_set_default_mac_addr,
549 .uc_hash_table_set = ixgbe_uc_hash_table_set,
550 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
551 .mirror_rule_set = ixgbe_mirror_rule_set,
552 .mirror_rule_reset = ixgbe_mirror_rule_reset,
553 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
554 .reta_update = ixgbe_dev_rss_reta_update,
555 .reta_query = ixgbe_dev_rss_reta_query,
556 .rss_hash_update = ixgbe_dev_rss_hash_update,
557 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
558 .filter_ctrl = ixgbe_dev_filter_ctrl,
559 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
560 .rxq_info_get = ixgbe_rxq_info_get,
561 .txq_info_get = ixgbe_txq_info_get,
562 .timesync_enable = ixgbe_timesync_enable,
563 .timesync_disable = ixgbe_timesync_disable,
564 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
565 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
566 .get_reg = ixgbe_get_regs,
567 .get_eeprom_length = ixgbe_get_eeprom_length,
568 .get_eeprom = ixgbe_get_eeprom,
569 .set_eeprom = ixgbe_set_eeprom,
570 .get_module_info = ixgbe_get_module_info,
571 .get_module_eeprom = ixgbe_get_module_eeprom,
572 .get_dcb_info = ixgbe_dev_get_dcb_info,
573 .timesync_adjust_time = ixgbe_timesync_adjust_time,
574 .timesync_read_time = ixgbe_timesync_read_time,
575 .timesync_write_time = ixgbe_timesync_write_time,
576 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
577 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
578 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
579 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
580 .tm_ops_get = ixgbe_tm_ops_get,
584 * dev_ops for virtual function, bare necessities for basic vf
585 * operation have been implemented
587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
588 .dev_configure = ixgbevf_dev_configure,
589 .dev_start = ixgbevf_dev_start,
590 .dev_stop = ixgbevf_dev_stop,
591 .link_update = ixgbevf_dev_link_update,
592 .stats_get = ixgbevf_dev_stats_get,
593 .xstats_get = ixgbevf_dev_xstats_get,
594 .stats_reset = ixgbevf_dev_stats_reset,
595 .xstats_reset = ixgbevf_dev_stats_reset,
596 .xstats_get_names = ixgbevf_dev_xstats_get_names,
597 .dev_close = ixgbevf_dev_close,
598 .dev_reset = ixgbevf_dev_reset,
599 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
600 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
601 .dev_infos_get = ixgbevf_dev_info_get,
602 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
603 .mtu_set = ixgbevf_dev_set_mtu,
604 .vlan_filter_set = ixgbevf_vlan_filter_set,
605 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
606 .vlan_offload_set = ixgbevf_vlan_offload_set,
607 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
608 .rx_queue_release = ixgbe_dev_rx_queue_release,
609 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
610 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
611 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
612 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
613 .tx_queue_release = ixgbe_dev_tx_queue_release,
614 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
615 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
616 .mac_addr_add = ixgbevf_add_mac_addr,
617 .mac_addr_remove = ixgbevf_remove_mac_addr,
618 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
619 .rxq_info_get = ixgbe_rxq_info_get,
620 .txq_info_get = ixgbe_txq_info_get,
621 .mac_addr_set = ixgbevf_set_default_mac_addr,
622 .get_reg = ixgbevf_get_regs,
623 .reta_update = ixgbe_dev_rss_reta_update,
624 .reta_query = ixgbe_dev_rss_reta_query,
625 .rss_hash_update = ixgbe_dev_rss_hash_update,
626 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
629 /* store statistics names and its offset in stats structure */
630 struct rte_ixgbe_xstats_name_off {
631 char name[RTE_ETH_XSTATS_NAME_SIZE];
635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
636 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
637 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
638 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
639 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
640 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
641 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
642 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
643 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
644 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
645 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
646 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
647 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
648 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
649 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
650 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
652 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
654 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
655 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
656 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
657 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
658 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
659 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
660 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
661 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
662 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
663 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
664 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
665 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
666 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
667 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
668 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
669 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
670 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
672 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
674 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
675 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
676 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
677 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
679 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
681 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
683 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
685 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
687 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
689 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
692 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
693 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
694 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
696 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
697 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
698 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
699 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
700 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
702 {"rx_fcoe_no_direct_data_placement_ext_buff",
703 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
705 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
707 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
709 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
711 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
713 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
717 sizeof(rte_ixgbe_stats_strings[0]))
719 /* MACsec statistics */
720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
721 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
723 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
724 out_pkts_encrypted)},
725 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
726 out_pkts_protected)},
727 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
728 out_octets_encrypted)},
729 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
730 out_octets_protected)},
731 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
733 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
735 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
737 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
738 in_pkts_unknownsci)},
739 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
740 in_octets_decrypted)},
741 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
742 in_octets_validated)},
743 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
745 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
747 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
749 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
757 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
758 in_pkts_notusingsa)},
761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
762 sizeof(rte_ixgbe_macsec_strings[0]))
764 /* Per-queue statistics */
765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
766 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
767 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
768 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
769 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
773 sizeof(rte_ixgbe_rxq_strings[0]))
774 #define IXGBE_NB_RXQ_PRIO_VALUES 8
776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
777 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
778 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
779 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
784 sizeof(rte_ixgbe_txq_strings[0]))
785 #define IXGBE_NB_TXQ_PRIO_VALUES 8
787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
788 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
792 sizeof(rte_ixgbevf_stats_strings[0]))
795 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
798 ixgbe_is_sfp(struct ixgbe_hw *hw)
800 switch (hw->phy.type) {
801 case ixgbe_phy_sfp_avago:
802 case ixgbe_phy_sfp_ftl:
803 case ixgbe_phy_sfp_intel:
804 case ixgbe_phy_sfp_unknown:
805 case ixgbe_phy_sfp_passive_tyco:
806 case ixgbe_phy_sfp_passive_unknown:
813 static inline int32_t
814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
819 status = ixgbe_reset_hw(hw);
821 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
822 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
823 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
824 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
825 IXGBE_WRITE_FLUSH(hw);
827 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
828 status = IXGBE_SUCCESS;
833 ixgbe_enable_intr(struct rte_eth_dev *dev)
835 struct ixgbe_interrupt *intr =
836 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
837 struct ixgbe_hw *hw =
838 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
840 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
841 IXGBE_WRITE_FLUSH(hw);
845 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
848 ixgbe_disable_intr(struct ixgbe_hw *hw)
850 PMD_INIT_FUNC_TRACE();
852 if (hw->mac.type == ixgbe_mac_82598EB) {
853 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
855 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
856 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
857 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
859 IXGBE_WRITE_FLUSH(hw);
863 * This function resets queue statistics mapping registers.
864 * From Niantic datasheet, Initialization of Statistics section:
865 * "...if software requires the queue counters, the RQSMR and TQSM registers
866 * must be re-programmed following a device reset.
869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
873 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
874 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
875 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
887 #define NB_QMAP_FIELDS_PER_QSM_REG 4
888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
890 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
891 struct ixgbe_stat_mapping_registers *stat_mappings =
892 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
893 uint32_t qsmr_mask = 0;
894 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
898 if ((hw->mac.type != ixgbe_mac_82599EB) &&
899 (hw->mac.type != ixgbe_mac_X540) &&
900 (hw->mac.type != ixgbe_mac_X550) &&
901 (hw->mac.type != ixgbe_mac_X550EM_x) &&
902 (hw->mac.type != ixgbe_mac_X550EM_a))
905 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
906 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
909 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
910 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
911 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
914 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
916 /* Now clear any previous stat_idx set */
917 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
919 stat_mappings->tqsm[n] &= ~clearing_mask;
921 stat_mappings->rqsmr[n] &= ~clearing_mask;
923 q_map = (uint32_t)stat_idx;
924 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
925 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
927 stat_mappings->tqsm[n] |= qsmr_mask;
929 stat_mappings->rqsmr[n] |= qsmr_mask;
931 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
932 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
934 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
935 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
937 /* Now write the mapping in the appropriate register */
939 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
940 stat_mappings->rqsmr[n], n);
941 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
943 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
944 stat_mappings->tqsm[n], n);
945 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
953 struct ixgbe_stat_mapping_registers *stat_mappings =
954 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
958 /* write whatever was in stat mapping table to the NIC */
959 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
961 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
964 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
972 struct ixgbe_dcb_tc_config *tc;
973 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
975 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
976 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
977 for (i = 0; i < dcb_max_tc; i++) {
978 tc = &dcb_config->tc_config[i];
979 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
980 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
981 (uint8_t)(100/dcb_max_tc + (i & 1));
982 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
983 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
984 (uint8_t)(100/dcb_max_tc + (i & 1));
985 tc->pfc = ixgbe_dcb_pfc_disabled;
988 /* Initialize default user to priority mapping, UPx->TC0 */
989 tc = &dcb_config->tc_config[0];
990 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
991 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
992 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
993 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
994 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
996 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
997 dcb_config->pfc_mode_enable = false;
998 dcb_config->vt_mode = true;
999 dcb_config->round_robin_enable = false;
1000 /* support all DCB capabilities in 82599 */
1001 dcb_config->support.capabilities = 0xFF;
1003 /*we only support 4 Tcs for X540, X550 */
1004 if (hw->mac.type == ixgbe_mac_X540 ||
1005 hw->mac.type == ixgbe_mac_X550 ||
1006 hw->mac.type == ixgbe_mac_X550EM_x ||
1007 hw->mac.type == ixgbe_mac_X550EM_a) {
1008 dcb_config->num_tcs.pg_tcs = 4;
1009 dcb_config->num_tcs.pfc_tcs = 4;
1014 * Ensure that all locks are released before first NVM or PHY access
1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1022 * Phy lock should not fail in this early stage. If this is the case,
1023 * it is due to an improper exit of the application.
1024 * So force the release of the faulty lock. Release of common lock
1025 * is done automatically by swfw_sync function.
1027 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1028 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1029 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1031 ixgbe_release_swfw_semaphore(hw, mask);
1034 * These ones are more tricky since they are common to all ports; but
1035 * swfw_sync retries last long enough (1s) to be almost sure that if
1036 * lock can not be taken it is due to an improper lock of the
1039 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1040 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1041 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1043 ixgbe_release_swfw_semaphore(hw, mask);
1047 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1048 * It returns 0 on success.
1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1055 struct ixgbe_hw *hw =
1056 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1057 struct ixgbe_vfta *shadow_vfta =
1058 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1059 struct ixgbe_hwstrip *hwstrip =
1060 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1061 struct ixgbe_dcb_config *dcb_config =
1062 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1063 struct ixgbe_filter_info *filter_info =
1064 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1065 struct ixgbe_bw_conf *bw_conf =
1066 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1071 PMD_INIT_FUNC_TRACE();
1073 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1074 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1075 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1076 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1079 * For secondary processes, we don't initialise any further as primary
1080 * has already done this work. Only check we don't need a different
1081 * RX and TX function.
1083 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1084 struct ixgbe_tx_queue *txq;
1085 /* TX queue function in primary, set by last queue initialized
1086 * Tx queue may not initialized by primary process
1088 if (eth_dev->data->tx_queues) {
1089 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1090 ixgbe_set_tx_function(eth_dev, txq);
1092 /* Use default TX function if we get here */
1093 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1094 "Using default TX function.");
1097 ixgbe_set_rx_function(eth_dev);
1102 rte_eth_copy_pci_info(eth_dev, pci_dev);
1104 /* Vendor and Device ID need to be set before init of shared code */
1105 hw->device_id = pci_dev->id.device_id;
1106 hw->vendor_id = pci_dev->id.vendor_id;
1107 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1108 hw->allow_unsupported_sfp = 1;
1110 /* Initialize the shared code (base driver) */
1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1112 diag = ixgbe_bypass_init_shared_code(hw);
1114 diag = ixgbe_init_shared_code(hw);
1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1117 if (diag != IXGBE_SUCCESS) {
1118 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1122 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1123 PMD_INIT_LOG(ERR, "\nERROR: "
1124 "Firmware recovery mode detected. Limiting functionality.\n"
1125 "Refer to the Intel(R) Ethernet Adapters and Devices "
1126 "User Guide for details on firmware recovery mode.");
1130 /* pick up the PCI bus settings for reporting later */
1131 ixgbe_get_bus_info(hw);
1133 /* Unlock any pending hardware semaphore */
1134 ixgbe_swfw_lock_reset(hw);
1136 #ifdef RTE_LIBRTE_SECURITY
1137 /* Initialize security_ctx only for primary process*/
1138 if (ixgbe_ipsec_ctx_create(eth_dev))
1142 /* Initialize DCB configuration*/
1143 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1144 ixgbe_dcb_init(hw, dcb_config);
1145 /* Get Hardware Flow Control setting */
1146 hw->fc.requested_mode = ixgbe_fc_full;
1147 hw->fc.current_mode = ixgbe_fc_full;
1148 hw->fc.pause_time = IXGBE_FC_PAUSE;
1149 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1150 hw->fc.low_water[i] = IXGBE_FC_LO;
1151 hw->fc.high_water[i] = IXGBE_FC_HI;
1153 hw->fc.send_xon = 1;
1155 /* Make sure we have a good EEPROM before we read from it */
1156 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1157 if (diag != IXGBE_SUCCESS) {
1158 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1162 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1163 diag = ixgbe_bypass_init_hw(hw);
1165 diag = ixgbe_init_hw(hw);
1166 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1169 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1170 * is called too soon after the kernel driver unbinding/binding occurs.
1171 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1172 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1173 * also called. See ixgbe_identify_phy_82599(). The reason for the
1174 * failure is not known, and only occuts when virtualisation features
1175 * are disabled in the bios. A delay of 100ms was found to be enough by
1176 * trial-and-error, and is doubled to be safe.
1178 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1180 diag = ixgbe_init_hw(hw);
1183 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1184 diag = IXGBE_SUCCESS;
1186 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1187 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1188 "LOM. Please be aware there may be issues associated "
1189 "with your hardware.");
1190 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1191 "please contact your Intel or hardware representative "
1192 "who provided you with this hardware.");
1193 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1194 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1196 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1200 /* Reset the hw statistics */
1201 ixgbe_dev_stats_reset(eth_dev);
1203 /* disable interrupt */
1204 ixgbe_disable_intr(hw);
1206 /* reset mappings for queue statistics hw counters*/
1207 ixgbe_reset_qstat_mappings(hw);
1209 /* Allocate memory for storing MAC addresses */
1210 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1211 hw->mac.num_rar_entries, 0);
1212 if (eth_dev->data->mac_addrs == NULL) {
1214 "Failed to allocate %u bytes needed to store "
1216 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1219 /* Copy the permanent MAC address */
1220 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1221 ð_dev->data->mac_addrs[0]);
1223 /* Allocate memory for storing hash filter MAC addresses */
1224 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1225 IXGBE_VMDQ_NUM_UC_MAC, 0);
1226 if (eth_dev->data->hash_mac_addrs == NULL) {
1228 "Failed to allocate %d bytes needed to store MAC addresses",
1229 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1233 /* initialize the vfta */
1234 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1236 /* initialize the hw strip bitmap*/
1237 memset(hwstrip, 0, sizeof(*hwstrip));
1239 /* initialize PF if max_vfs not zero */
1240 ixgbe_pf_host_init(eth_dev);
1242 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1243 /* let hardware know driver is loaded */
1244 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1245 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1246 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1247 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1248 IXGBE_WRITE_FLUSH(hw);
1250 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1251 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1252 (int) hw->mac.type, (int) hw->phy.type,
1253 (int) hw->phy.sfp_type);
1255 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1256 (int) hw->mac.type, (int) hw->phy.type);
1258 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1259 eth_dev->data->port_id, pci_dev->id.vendor_id,
1260 pci_dev->id.device_id);
1262 rte_intr_callback_register(intr_handle,
1263 ixgbe_dev_interrupt_handler, eth_dev);
1265 /* enable uio/vfio intr/eventfd mapping */
1266 rte_intr_enable(intr_handle);
1268 /* enable support intr */
1269 ixgbe_enable_intr(eth_dev);
1271 /* initialize filter info */
1272 memset(filter_info, 0,
1273 sizeof(struct ixgbe_filter_info));
1275 /* initialize 5tuple filter list */
1276 TAILQ_INIT(&filter_info->fivetuple_list);
1278 /* initialize flow director filter list & hash */
1279 ixgbe_fdir_filter_init(eth_dev);
1281 /* initialize l2 tunnel filter list & hash */
1282 ixgbe_l2_tn_filter_init(eth_dev);
1284 /* initialize flow filter lists */
1285 ixgbe_filterlist_init();
1287 /* initialize bandwidth configuration info */
1288 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1290 /* initialize Traffic Manager configuration */
1291 ixgbe_tm_conf_init(eth_dev);
1297 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1299 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1300 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1301 struct ixgbe_hw *hw;
1305 PMD_INIT_FUNC_TRACE();
1307 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1310 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1312 if (hw->adapter_stopped == 0)
1313 ixgbe_dev_close(eth_dev);
1315 eth_dev->dev_ops = NULL;
1316 eth_dev->rx_pkt_burst = NULL;
1317 eth_dev->tx_pkt_burst = NULL;
1319 /* Unlock any pending hardware semaphore */
1320 ixgbe_swfw_lock_reset(hw);
1322 /* disable uio intr before callback unregister */
1323 rte_intr_disable(intr_handle);
1326 ret = rte_intr_callback_unregister(intr_handle,
1327 ixgbe_dev_interrupt_handler, eth_dev);
1330 } else if (ret != -EAGAIN) {
1332 "intr callback unregister failed: %d",
1337 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1339 /* cancel the delay handler before remove dev */
1340 rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, eth_dev);
1342 /* uninitialize PF if max_vfs not zero */
1343 ixgbe_pf_host_uninit(eth_dev);
1345 /* remove all the fdir filters & hash */
1346 ixgbe_fdir_filter_uninit(eth_dev);
1348 /* remove all the L2 tunnel filters & hash */
1349 ixgbe_l2_tn_filter_uninit(eth_dev);
1351 /* Remove all ntuple filters of the device */
1352 ixgbe_ntuple_filter_uninit(eth_dev);
1354 /* clear all the filters list */
1355 ixgbe_filterlist_flush();
1357 /* Remove all Traffic Manager configuration */
1358 ixgbe_tm_conf_uninit(eth_dev);
1360 #ifdef RTE_LIBRTE_SECURITY
1361 rte_free(eth_dev->security_ctx);
1367 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1369 struct ixgbe_filter_info *filter_info =
1370 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1371 struct ixgbe_5tuple_filter *p_5tuple;
1373 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1374 TAILQ_REMOVE(&filter_info->fivetuple_list,
1379 memset(filter_info->fivetuple_mask, 0,
1380 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1385 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1387 struct ixgbe_hw_fdir_info *fdir_info =
1388 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1389 struct ixgbe_fdir_filter *fdir_filter;
1391 if (fdir_info->hash_map)
1392 rte_free(fdir_info->hash_map);
1393 if (fdir_info->hash_handle)
1394 rte_hash_free(fdir_info->hash_handle);
1396 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1397 TAILQ_REMOVE(&fdir_info->fdir_list,
1400 rte_free(fdir_filter);
1406 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1408 struct ixgbe_l2_tn_info *l2_tn_info =
1409 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1410 struct ixgbe_l2_tn_filter *l2_tn_filter;
1412 if (l2_tn_info->hash_map)
1413 rte_free(l2_tn_info->hash_map);
1414 if (l2_tn_info->hash_handle)
1415 rte_hash_free(l2_tn_info->hash_handle);
1417 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1418 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1421 rte_free(l2_tn_filter);
1427 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1429 struct ixgbe_hw_fdir_info *fdir_info =
1430 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1431 char fdir_hash_name[RTE_HASH_NAMESIZE];
1432 struct rte_hash_parameters fdir_hash_params = {
1433 .name = fdir_hash_name,
1434 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1435 .key_len = sizeof(union ixgbe_atr_input),
1436 .hash_func = rte_hash_crc,
1437 .hash_func_init_val = 0,
1438 .socket_id = rte_socket_id(),
1441 TAILQ_INIT(&fdir_info->fdir_list);
1442 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1443 "fdir_%s", eth_dev->device->name);
1444 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1445 if (!fdir_info->hash_handle) {
1446 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1449 fdir_info->hash_map = rte_zmalloc("ixgbe",
1450 sizeof(struct ixgbe_fdir_filter *) *
1451 IXGBE_MAX_FDIR_FILTER_NUM,
1453 if (!fdir_info->hash_map) {
1455 "Failed to allocate memory for fdir hash map!");
1458 fdir_info->mask_added = FALSE;
1463 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1465 struct ixgbe_l2_tn_info *l2_tn_info =
1466 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1467 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1468 struct rte_hash_parameters l2_tn_hash_params = {
1469 .name = l2_tn_hash_name,
1470 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1471 .key_len = sizeof(struct ixgbe_l2_tn_key),
1472 .hash_func = rte_hash_crc,
1473 .hash_func_init_val = 0,
1474 .socket_id = rte_socket_id(),
1477 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1478 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1479 "l2_tn_%s", eth_dev->device->name);
1480 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1481 if (!l2_tn_info->hash_handle) {
1482 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1485 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1486 sizeof(struct ixgbe_l2_tn_filter *) *
1487 IXGBE_MAX_L2_TN_FILTER_NUM,
1489 if (!l2_tn_info->hash_map) {
1491 "Failed to allocate memory for L2 TN hash map!");
1494 l2_tn_info->e_tag_en = FALSE;
1495 l2_tn_info->e_tag_fwd_en = FALSE;
1496 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG;
1501 * Negotiate mailbox API version with the PF.
1502 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1503 * Then we try to negotiate starting with the most recent one.
1504 * If all negotiation attempts fail, then we will proceed with
1505 * the default one (ixgbe_mbox_api_10).
1508 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1512 /* start with highest supported, proceed down */
1513 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1520 i != RTE_DIM(sup_ver) &&
1521 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1527 generate_random_mac_addr(struct ether_addr *mac_addr)
1531 /* Set Organizationally Unique Identifier (OUI) prefix. */
1532 mac_addr->addr_bytes[0] = 0x00;
1533 mac_addr->addr_bytes[1] = 0x09;
1534 mac_addr->addr_bytes[2] = 0xC0;
1535 /* Force indication of locally assigned MAC address. */
1536 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1537 /* Generate the last 3 bytes of the MAC address with a random number. */
1538 random = rte_rand();
1539 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1543 * Virtual Function device init
1546 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1550 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552 struct ixgbe_hw *hw =
1553 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1554 struct ixgbe_vfta *shadow_vfta =
1555 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1556 struct ixgbe_hwstrip *hwstrip =
1557 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1558 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1560 PMD_INIT_FUNC_TRACE();
1562 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1563 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1564 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1566 /* for secondary processes, we don't initialise any further as primary
1567 * has already done this work. Only check we don't need a different
1570 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1571 struct ixgbe_tx_queue *txq;
1572 /* TX queue function in primary, set by last queue initialized
1573 * Tx queue may not initialized by primary process
1575 if (eth_dev->data->tx_queues) {
1576 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1577 ixgbe_set_tx_function(eth_dev, txq);
1579 /* Use default TX function if we get here */
1580 PMD_INIT_LOG(NOTICE,
1581 "No TX queues configured yet. Using default TX function.");
1584 ixgbe_set_rx_function(eth_dev);
1589 rte_eth_copy_pci_info(eth_dev, pci_dev);
1591 hw->device_id = pci_dev->id.device_id;
1592 hw->vendor_id = pci_dev->id.vendor_id;
1593 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1595 /* initialize the vfta */
1596 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1598 /* initialize the hw strip bitmap*/
1599 memset(hwstrip, 0, sizeof(*hwstrip));
1601 /* Initialize the shared code (base driver) */
1602 diag = ixgbe_init_shared_code(hw);
1603 if (diag != IXGBE_SUCCESS) {
1604 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1608 /* init_mailbox_params */
1609 hw->mbx.ops.init_params(hw);
1611 /* Reset the hw statistics */
1612 ixgbevf_dev_stats_reset(eth_dev);
1614 /* Disable the interrupts for VF */
1615 ixgbevf_intr_disable(eth_dev);
1617 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1618 diag = hw->mac.ops.reset_hw(hw);
1621 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1622 * the underlying PF driver has not assigned a MAC address to the VF.
1623 * In this case, assign a random MAC address.
1625 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1626 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1628 * This error code will be propagated to the app by
1629 * rte_eth_dev_reset, so use a public error code rather than
1630 * the internal-only IXGBE_ERR_RESET_FAILED
1635 /* negotiate mailbox API version to use with the PF. */
1636 ixgbevf_negotiate_api(hw);
1638 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1639 ixgbevf_get_queues(hw, &tcs, &tc);
1641 /* Allocate memory for storing MAC addresses */
1642 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1643 hw->mac.num_rar_entries, 0);
1644 if (eth_dev->data->mac_addrs == NULL) {
1646 "Failed to allocate %u bytes needed to store "
1648 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1652 /* Generate a random MAC address, if none was assigned by PF. */
1653 if (is_zero_ether_addr(perm_addr)) {
1654 generate_random_mac_addr(perm_addr);
1655 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1657 rte_free(eth_dev->data->mac_addrs);
1658 eth_dev->data->mac_addrs = NULL;
1661 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1662 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1663 "%02x:%02x:%02x:%02x:%02x:%02x",
1664 perm_addr->addr_bytes[0],
1665 perm_addr->addr_bytes[1],
1666 perm_addr->addr_bytes[2],
1667 perm_addr->addr_bytes[3],
1668 perm_addr->addr_bytes[4],
1669 perm_addr->addr_bytes[5]);
1672 /* Copy the permanent MAC address */
1673 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1675 /* reset the hardware with the new settings */
1676 diag = hw->mac.ops.start_hw(hw);
1682 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1686 rte_intr_callback_register(intr_handle,
1687 ixgbevf_dev_interrupt_handler, eth_dev);
1688 rte_intr_enable(intr_handle);
1689 ixgbevf_intr_enable(eth_dev);
1691 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1692 eth_dev->data->port_id, pci_dev->id.vendor_id,
1693 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1698 /* Virtual Function device uninit */
1701 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1703 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1704 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1705 struct ixgbe_hw *hw;
1707 PMD_INIT_FUNC_TRACE();
1709 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1712 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1714 if (hw->adapter_stopped == 0)
1715 ixgbevf_dev_close(eth_dev);
1717 eth_dev->dev_ops = NULL;
1718 eth_dev->rx_pkt_burst = NULL;
1719 eth_dev->tx_pkt_burst = NULL;
1721 /* Disable the interrupts for VF */
1722 ixgbevf_intr_disable(eth_dev);
1724 rte_intr_disable(intr_handle);
1725 rte_intr_callback_unregister(intr_handle,
1726 ixgbevf_dev_interrupt_handler, eth_dev);
1732 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1733 struct rte_pci_device *pci_dev)
1735 char name[RTE_ETH_NAME_MAX_LEN];
1736 struct rte_eth_dev *pf_ethdev;
1737 struct rte_eth_devargs eth_da;
1740 if (pci_dev->device.devargs) {
1741 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1746 memset(ð_da, 0, sizeof(eth_da));
1748 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1749 sizeof(struct ixgbe_adapter),
1750 eth_dev_pci_specific_init, pci_dev,
1751 eth_ixgbe_dev_init, NULL);
1753 if (retval || eth_da.nb_representor_ports < 1)
1756 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1757 if (pf_ethdev == NULL)
1760 /* probe VF representor ports */
1761 for (i = 0; i < eth_da.nb_representor_ports; i++) {
1762 struct ixgbe_vf_info *vfinfo;
1763 struct ixgbe_vf_representor representor;
1765 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1766 pf_ethdev->data->dev_private);
1767 if (vfinfo == NULL) {
1769 "no virtual functions supported by PF");
1773 representor.vf_id = eth_da.representor_ports[i];
1774 representor.switch_domain_id = vfinfo->switch_domain_id;
1775 representor.pf_ethdev = pf_ethdev;
1777 /* representor port net_bdf_port */
1778 snprintf(name, sizeof(name), "net_%s_representor_%d",
1779 pci_dev->device.name,
1780 eth_da.representor_ports[i]);
1782 retval = rte_eth_dev_create(&pci_dev->device, name,
1783 sizeof(struct ixgbe_vf_representor), NULL, NULL,
1784 ixgbe_vf_representor_init, &representor);
1787 PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1788 "representor %s.", name);
1794 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1796 struct rte_eth_dev *ethdev;
1798 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1802 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1803 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit);
1805 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit);
1808 static struct rte_pci_driver rte_ixgbe_pmd = {
1809 .id_table = pci_id_ixgbe_map,
1810 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1811 RTE_PCI_DRV_IOVA_AS_VA,
1812 .probe = eth_ixgbe_pci_probe,
1813 .remove = eth_ixgbe_pci_remove,
1816 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1817 struct rte_pci_device *pci_dev)
1819 return rte_eth_dev_pci_generic_probe(pci_dev,
1820 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1823 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1825 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1829 * virtual function driver struct
1831 static struct rte_pci_driver rte_ixgbevf_pmd = {
1832 .id_table = pci_id_ixgbevf_map,
1833 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1834 .probe = eth_ixgbevf_pci_probe,
1835 .remove = eth_ixgbevf_pci_remove,
1839 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1841 struct ixgbe_hw *hw =
1842 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843 struct ixgbe_vfta *shadow_vfta =
1844 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1849 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1850 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1851 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1856 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1858 /* update local VFTA copy */
1859 shadow_vfta->vfta[vid_idx] = vfta;
1865 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1868 ixgbe_vlan_hw_strip_enable(dev, queue);
1870 ixgbe_vlan_hw_strip_disable(dev, queue);
1874 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1875 enum rte_vlan_type vlan_type,
1878 struct ixgbe_hw *hw =
1879 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1885 qinq &= IXGBE_DMATXCTL_GDV;
1887 switch (vlan_type) {
1888 case ETH_VLAN_TYPE_INNER:
1890 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1891 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1892 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1893 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1894 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1895 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1896 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1899 PMD_DRV_LOG(ERR, "Inner type is not supported"
1903 case ETH_VLAN_TYPE_OUTER:
1905 /* Only the high 16-bits is valid */
1906 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1907 IXGBE_EXVET_VET_EXT_SHIFT);
1909 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1910 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1911 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1912 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1913 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1914 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1915 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1921 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1929 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1931 struct ixgbe_hw *hw =
1932 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935 PMD_INIT_FUNC_TRACE();
1937 /* Filter Table Disable */
1938 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1939 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1941 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1945 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1947 struct ixgbe_hw *hw =
1948 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949 struct ixgbe_vfta *shadow_vfta =
1950 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1954 PMD_INIT_FUNC_TRACE();
1956 /* Filter Table Enable */
1957 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1958 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1959 vlnctrl |= IXGBE_VLNCTRL_VFE;
1961 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1963 /* write whatever is in local vfta copy */
1964 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1965 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1969 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1971 struct ixgbe_hwstrip *hwstrip =
1972 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1973 struct ixgbe_rx_queue *rxq;
1975 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1979 IXGBE_SET_HWSTRIP(hwstrip, queue);
1981 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1983 if (queue >= dev->data->nb_rx_queues)
1986 rxq = dev->data->rx_queues[queue];
1989 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1990 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1992 rxq->vlan_flags = PKT_RX_VLAN;
1993 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1998 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2000 struct ixgbe_hw *hw =
2001 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004 PMD_INIT_FUNC_TRACE();
2006 if (hw->mac.type == ixgbe_mac_82598EB) {
2007 /* No queue level support */
2008 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2012 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2013 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2014 ctrl &= ~IXGBE_RXDCTL_VME;
2015 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2017 /* record those setting for HW strip per queue */
2018 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2022 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2024 struct ixgbe_hw *hw =
2025 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028 PMD_INIT_FUNC_TRACE();
2030 if (hw->mac.type == ixgbe_mac_82598EB) {
2031 /* No queue level supported */
2032 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2036 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2037 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2038 ctrl |= IXGBE_RXDCTL_VME;
2039 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2041 /* record those setting for HW strip per queue */
2042 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2046 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2048 struct ixgbe_hw *hw =
2049 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052 PMD_INIT_FUNC_TRACE();
2054 /* DMATXCTRL: Geric Double VLAN Disable */
2055 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2056 ctrl &= ~IXGBE_DMATXCTL_GDV;
2057 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2059 /* CTRL_EXT: Global Double VLAN Disable */
2060 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2061 ctrl &= ~IXGBE_EXTENDED_VLAN;
2062 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2067 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2069 struct ixgbe_hw *hw =
2070 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073 PMD_INIT_FUNC_TRACE();
2075 /* DMATXCTRL: Geric Double VLAN Enable */
2076 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2077 ctrl |= IXGBE_DMATXCTL_GDV;
2078 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2080 /* CTRL_EXT: Global Double VLAN Enable */
2081 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2082 ctrl |= IXGBE_EXTENDED_VLAN;
2083 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2085 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2086 if (hw->mac.type == ixgbe_mac_X550 ||
2087 hw->mac.type == ixgbe_mac_X550EM_x ||
2088 hw->mac.type == ixgbe_mac_X550EM_a) {
2089 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2090 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2091 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2095 * VET EXT field in the EXVET register = 0x8100 by default
2096 * So no need to change. Same to VT field of DMATXCTL register
2101 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2103 struct ixgbe_hw *hw =
2104 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2105 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2108 struct ixgbe_rx_queue *rxq;
2111 PMD_INIT_FUNC_TRACE();
2113 if (hw->mac.type == ixgbe_mac_82598EB) {
2114 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2115 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2116 ctrl |= IXGBE_VLNCTRL_VME;
2117 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2119 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2120 ctrl &= ~IXGBE_VLNCTRL_VME;
2121 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2125 * Other 10G NIC, the VLAN strip can be setup
2126 * per queue in RXDCTL
2128 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2129 rxq = dev->data->rx_queues[i];
2130 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2131 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2132 ctrl |= IXGBE_RXDCTL_VME;
2135 ctrl &= ~IXGBE_RXDCTL_VME;
2138 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2140 /* record those setting for HW strip per queue */
2141 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2147 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2150 struct rte_eth_rxmode *rxmode;
2151 struct ixgbe_rx_queue *rxq;
2153 if (mask & ETH_VLAN_STRIP_MASK) {
2154 rxmode = &dev->data->dev_conf.rxmode;
2155 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2156 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2157 rxq = dev->data->rx_queues[i];
2158 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2161 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2162 rxq = dev->data->rx_queues[i];
2163 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2169 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2171 struct rte_eth_rxmode *rxmode;
2172 rxmode = &dev->data->dev_conf.rxmode;
2174 if (mask & ETH_VLAN_STRIP_MASK) {
2175 ixgbe_vlan_hw_strip_config(dev);
2178 if (mask & ETH_VLAN_FILTER_MASK) {
2179 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2180 ixgbe_vlan_hw_filter_enable(dev);
2182 ixgbe_vlan_hw_filter_disable(dev);
2185 if (mask & ETH_VLAN_EXTEND_MASK) {
2186 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2187 ixgbe_vlan_hw_extend_enable(dev);
2189 ixgbe_vlan_hw_extend_disable(dev);
2196 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2198 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2200 ixgbe_vlan_offload_config(dev, mask);
2206 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2208 struct ixgbe_hw *hw =
2209 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2211 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2213 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2214 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2218 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2220 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2225 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2228 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2234 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2235 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2236 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2237 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2242 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2244 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2245 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2247 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2249 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2250 /* check multi-queue mode */
2251 switch (dev_conf->rxmode.mq_mode) {
2252 case ETH_MQ_RX_VMDQ_DCB:
2253 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2255 case ETH_MQ_RX_VMDQ_DCB_RSS:
2256 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2257 PMD_INIT_LOG(ERR, "SRIOV active,"
2258 " unsupported mq_mode rx %d.",
2259 dev_conf->rxmode.mq_mode);
2262 case ETH_MQ_RX_VMDQ_RSS:
2263 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2264 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2265 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2266 PMD_INIT_LOG(ERR, "SRIOV is active,"
2267 " invalid queue number"
2268 " for VMDQ RSS, allowed"
2269 " value are 1, 2 or 4.");
2273 case ETH_MQ_RX_VMDQ_ONLY:
2274 case ETH_MQ_RX_NONE:
2275 /* if nothing mq mode configure, use default scheme */
2276 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2278 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2279 /* SRIOV only works in VMDq enable mode */
2280 PMD_INIT_LOG(ERR, "SRIOV is active,"
2281 " wrong mq_mode rx %d.",
2282 dev_conf->rxmode.mq_mode);
2286 switch (dev_conf->txmode.mq_mode) {
2287 case ETH_MQ_TX_VMDQ_DCB:
2288 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2289 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2291 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2292 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2296 /* check valid queue number */
2297 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2298 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2299 PMD_INIT_LOG(ERR, "SRIOV is active,"
2300 " nb_rx_q=%d nb_tx_q=%d queue number"
2301 " must be less than or equal to %d.",
2303 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2307 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2308 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2312 /* check configuration for vmdb+dcb mode */
2313 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2314 const struct rte_eth_vmdq_dcb_conf *conf;
2316 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2317 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2318 IXGBE_VMDQ_DCB_NB_QUEUES);
2321 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2322 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2323 conf->nb_queue_pools == ETH_32_POOLS)) {
2324 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2325 " nb_queue_pools must be %d or %d.",
2326 ETH_16_POOLS, ETH_32_POOLS);
2330 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2331 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2333 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2334 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2335 IXGBE_VMDQ_DCB_NB_QUEUES);
2338 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2339 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2340 conf->nb_queue_pools == ETH_32_POOLS)) {
2341 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2342 " nb_queue_pools != %d and"
2343 " nb_queue_pools != %d.",
2344 ETH_16_POOLS, ETH_32_POOLS);
2349 /* For DCB mode check our configuration before we go further */
2350 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2351 const struct rte_eth_dcb_rx_conf *conf;
2353 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2354 if (!(conf->nb_tcs == ETH_4_TCS ||
2355 conf->nb_tcs == ETH_8_TCS)) {
2356 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2357 " and nb_tcs != %d.",
2358 ETH_4_TCS, ETH_8_TCS);
2363 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2364 const struct rte_eth_dcb_tx_conf *conf;
2366 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2367 if (!(conf->nb_tcs == ETH_4_TCS ||
2368 conf->nb_tcs == ETH_8_TCS)) {
2369 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2370 " and nb_tcs != %d.",
2371 ETH_4_TCS, ETH_8_TCS);
2377 * When DCB/VT is off, maximum number of queues changes,
2378 * except for 82598EB, which remains constant.
2380 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2381 hw->mac.type != ixgbe_mac_82598EB) {
2382 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2384 "Neither VT nor DCB are enabled, "
2386 IXGBE_NONE_MODE_TX_NB_QUEUES);
2395 ixgbe_dev_configure(struct rte_eth_dev *dev)
2397 struct ixgbe_interrupt *intr =
2398 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2399 struct ixgbe_adapter *adapter =
2400 (struct ixgbe_adapter *)dev->data->dev_private;
2403 PMD_INIT_FUNC_TRACE();
2404 /* multipe queue mode checking */
2405 ret = ixgbe_check_mq_mode(dev);
2407 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2412 /* set flag to update link status after init */
2413 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2416 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2417 * allocation or vector Rx preconditions we will reset it.
2419 adapter->rx_bulk_alloc_allowed = true;
2420 adapter->rx_vec_allowed = true;
2426 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2428 struct ixgbe_hw *hw =
2429 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430 struct ixgbe_interrupt *intr =
2431 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2434 /* only set up it on X550EM_X */
2435 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2436 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2437 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2438 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2439 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2440 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2445 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2446 uint16_t tx_rate, uint64_t q_msk)
2448 struct ixgbe_hw *hw;
2449 struct ixgbe_vf_info *vfinfo;
2450 struct rte_eth_link link;
2451 uint8_t nb_q_per_pool;
2452 uint32_t queue_stride;
2453 uint32_t queue_idx, idx = 0, vf_idx;
2455 uint16_t total_rate = 0;
2456 struct rte_pci_device *pci_dev;
2458 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2459 rte_eth_link_get_nowait(dev->data->port_id, &link);
2461 if (vf >= pci_dev->max_vfs)
2464 if (tx_rate > link.link_speed)
2470 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2472 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2473 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2474 queue_idx = vf * queue_stride;
2475 queue_end = queue_idx + nb_q_per_pool - 1;
2476 if (queue_end >= hw->mac.max_tx_queues)
2480 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2483 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2485 total_rate += vfinfo[vf_idx].tx_rate[idx];
2491 /* Store tx_rate for this vf. */
2492 for (idx = 0; idx < nb_q_per_pool; idx++) {
2493 if (((uint64_t)0x1 << idx) & q_msk) {
2494 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2495 vfinfo[vf].tx_rate[idx] = tx_rate;
2496 total_rate += tx_rate;
2500 if (total_rate > dev->data->dev_link.link_speed) {
2501 /* Reset stored TX rate of the VF if it causes exceed
2504 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2508 /* Set RTTBCNRC of each queue/pool for vf X */
2509 for (; queue_idx <= queue_end; queue_idx++) {
2511 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2519 * Configure device link speed and setup link.
2520 * It returns 0 on success.
2523 ixgbe_dev_start(struct rte_eth_dev *dev)
2525 struct ixgbe_hw *hw =
2526 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527 struct ixgbe_vf_info *vfinfo =
2528 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2529 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2530 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2531 uint32_t intr_vector = 0;
2532 int err, link_up = 0, negotiate = 0;
2534 uint32_t allowed_speeds = 0;
2538 uint32_t *link_speeds;
2539 struct ixgbe_tm_conf *tm_conf =
2540 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2542 PMD_INIT_FUNC_TRACE();
2544 /* IXGBE devices don't support:
2545 * - half duplex (checked afterwards for valid speeds)
2546 * - fixed speed: TODO implement
2548 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2550 "Invalid link_speeds for port %u, fix speed not supported",
2551 dev->data->port_id);
2555 /* Stop the link setup handler before resetting the HW. */
2556 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2558 /* disable uio/vfio intr/eventfd mapping */
2559 rte_intr_disable(intr_handle);
2562 hw->adapter_stopped = 0;
2563 ixgbe_stop_adapter(hw);
2565 /* reinitialize adapter
2566 * this calls reset and start
2568 status = ixgbe_pf_reset_hw(hw);
2571 hw->mac.ops.start_hw(hw);
2572 hw->mac.get_link_status = true;
2574 /* configure PF module if SRIOV enabled */
2575 ixgbe_pf_host_configure(dev);
2577 ixgbe_dev_phy_intr_setup(dev);
2579 /* check and configure queue intr-vector mapping */
2580 if ((rte_intr_cap_multiple(intr_handle) ||
2581 !RTE_ETH_DEV_SRIOV(dev).active) &&
2582 dev->data->dev_conf.intr_conf.rxq != 0) {
2583 intr_vector = dev->data->nb_rx_queues;
2584 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2585 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2586 IXGBE_MAX_INTR_QUEUE_NUM);
2589 if (rte_intr_efd_enable(intr_handle, intr_vector))
2593 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2594 intr_handle->intr_vec =
2595 rte_zmalloc("intr_vec",
2596 dev->data->nb_rx_queues * sizeof(int), 0);
2597 if (intr_handle->intr_vec == NULL) {
2598 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2599 " intr_vec", dev->data->nb_rx_queues);
2604 /* confiugre msix for sleep until rx interrupt */
2605 ixgbe_configure_msix(dev);
2607 /* initialize transmission unit */
2608 ixgbe_dev_tx_init(dev);
2610 /* This can fail when allocating mbufs for descriptor rings */
2611 err = ixgbe_dev_rx_init(dev);
2613 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2617 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2618 ETH_VLAN_EXTEND_MASK;
2619 err = ixgbe_vlan_offload_config(dev, mask);
2621 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2625 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2626 /* Enable vlan filtering for VMDq */
2627 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2630 /* Configure DCB hw */
2631 ixgbe_configure_dcb(dev);
2633 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2634 err = ixgbe_fdir_configure(dev);
2639 /* Restore vf rate limit */
2640 if (vfinfo != NULL) {
2641 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2642 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2643 if (vfinfo[vf].tx_rate[idx] != 0)
2644 ixgbe_set_vf_rate_limit(
2646 vfinfo[vf].tx_rate[idx],
2650 ixgbe_restore_statistics_mapping(dev);
2652 err = ixgbe_dev_rxtx_start(dev);
2654 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2658 /* Skip link setup if loopback mode is enabled. */
2659 if (dev->data->dev_conf.lpbk_mode != 0) {
2660 err = ixgbe_check_supported_loopback_mode(dev);
2662 PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2665 goto skip_link_setup;
2669 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2670 err = hw->mac.ops.setup_sfp(hw);
2675 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2676 /* Turn on the copper */
2677 ixgbe_set_phy_power(hw, true);
2679 /* Turn on the laser */
2680 ixgbe_enable_tx_laser(hw);
2683 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2686 dev->data->dev_link.link_status = link_up;
2688 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2692 switch (hw->mac.type) {
2693 case ixgbe_mac_X550:
2694 case ixgbe_mac_X550EM_x:
2695 case ixgbe_mac_X550EM_a:
2696 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2697 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G |
2701 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2705 link_speeds = &dev->data->dev_conf.link_speeds;
2706 if (*link_speeds & ~allowed_speeds) {
2707 PMD_INIT_LOG(ERR, "Invalid link setting");
2712 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2713 switch (hw->mac.type) {
2714 case ixgbe_mac_82598EB:
2715 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2717 case ixgbe_mac_82599EB:
2718 case ixgbe_mac_X540:
2719 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2721 case ixgbe_mac_X550:
2722 case ixgbe_mac_X550EM_x:
2723 case ixgbe_mac_X550EM_a:
2724 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2727 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2730 if (*link_speeds & ETH_LINK_SPEED_10G)
2731 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2732 if (*link_speeds & ETH_LINK_SPEED_5G)
2733 speed |= IXGBE_LINK_SPEED_5GB_FULL;
2734 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2735 speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2736 if (*link_speeds & ETH_LINK_SPEED_1G)
2737 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2738 if (*link_speeds & ETH_LINK_SPEED_100M)
2739 speed |= IXGBE_LINK_SPEED_100_FULL;
2742 err = ixgbe_setup_link(hw, speed, link_up);
2748 if (rte_intr_allow_others(intr_handle)) {
2749 /* check if lsc interrupt is enabled */
2750 if (dev->data->dev_conf.intr_conf.lsc != 0)
2751 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2753 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2754 ixgbe_dev_macsec_interrupt_setup(dev);
2756 rte_intr_callback_unregister(intr_handle,
2757 ixgbe_dev_interrupt_handler, dev);
2758 if (dev->data->dev_conf.intr_conf.lsc != 0)
2759 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2760 " no intr multiplex");
2763 /* check if rxq interrupt is enabled */
2764 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2765 rte_intr_dp_is_en(intr_handle))
2766 ixgbe_dev_rxq_interrupt_setup(dev);
2768 /* enable uio/vfio intr/eventfd mapping */
2769 rte_intr_enable(intr_handle);
2771 /* resume enabled intr since hw reset */
2772 ixgbe_enable_intr(dev);
2773 ixgbe_l2_tunnel_conf(dev);
2774 ixgbe_filter_restore(dev);
2776 if (tm_conf->root && !tm_conf->committed)
2777 PMD_DRV_LOG(WARNING,
2778 "please call hierarchy_commit() "
2779 "before starting the port");
2782 * Update link status right before return, because it may
2783 * start link configuration process in a separate thread.
2785 ixgbe_dev_link_update(dev, 0);
2790 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2791 ixgbe_dev_clear_queues(dev);
2796 * Stop device: disable rx and tx functions to allow for reconfiguring.
2799 ixgbe_dev_stop(struct rte_eth_dev *dev)
2801 struct rte_eth_link link;
2802 struct ixgbe_adapter *adapter =
2803 (struct ixgbe_adapter *)dev->data->dev_private;
2804 struct ixgbe_hw *hw =
2805 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806 struct ixgbe_vf_info *vfinfo =
2807 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2808 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2809 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2811 struct ixgbe_tm_conf *tm_conf =
2812 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2814 PMD_INIT_FUNC_TRACE();
2816 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
2818 /* disable interrupts */
2819 ixgbe_disable_intr(hw);
2822 ixgbe_pf_reset_hw(hw);
2823 hw->adapter_stopped = 0;
2826 ixgbe_stop_adapter(hw);
2828 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2829 vfinfo[vf].clear_to_send = false;
2831 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2832 /* Turn off the copper */
2833 ixgbe_set_phy_power(hw, false);
2835 /* Turn off the laser */
2836 ixgbe_disable_tx_laser(hw);
2839 ixgbe_dev_clear_queues(dev);
2841 /* Clear stored conf */
2842 dev->data->scattered_rx = 0;
2845 /* Clear recorded link status */
2846 memset(&link, 0, sizeof(link));
2847 rte_eth_linkstatus_set(dev, &link);
2849 if (!rte_intr_allow_others(intr_handle))
2850 /* resume to the default handler */
2851 rte_intr_callback_register(intr_handle,
2852 ixgbe_dev_interrupt_handler,
2855 /* Clean datapath event and queue/vec mapping */
2856 rte_intr_efd_disable(intr_handle);
2857 if (intr_handle->intr_vec != NULL) {
2858 rte_free(intr_handle->intr_vec);
2859 intr_handle->intr_vec = NULL;
2862 /* reset hierarchy commit */
2863 tm_conf->committed = false;
2865 adapter->rss_reta_updated = 0;
2869 * Set device link up: enable tx.
2872 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2874 struct ixgbe_hw *hw =
2875 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876 if (hw->mac.type == ixgbe_mac_82599EB) {
2877 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2878 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2879 /* Not suported in bypass mode */
2880 PMD_INIT_LOG(ERR, "Set link up is not supported "
2881 "by device id 0x%x", hw->device_id);
2887 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2888 /* Turn on the copper */
2889 ixgbe_set_phy_power(hw, true);
2891 /* Turn on the laser */
2892 ixgbe_enable_tx_laser(hw);
2899 * Set device link down: disable tx.
2902 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2904 struct ixgbe_hw *hw =
2905 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2906 if (hw->mac.type == ixgbe_mac_82599EB) {
2907 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2908 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2909 /* Not suported in bypass mode */
2910 PMD_INIT_LOG(ERR, "Set link down is not supported "
2911 "by device id 0x%x", hw->device_id);
2917 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2918 /* Turn off the copper */
2919 ixgbe_set_phy_power(hw, false);
2921 /* Turn off the laser */
2922 ixgbe_disable_tx_laser(hw);
2929 * Reset and stop device.
2932 ixgbe_dev_close(struct rte_eth_dev *dev)
2934 struct ixgbe_hw *hw =
2935 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2937 PMD_INIT_FUNC_TRACE();
2939 ixgbe_pf_reset_hw(hw);
2941 ixgbe_dev_stop(dev);
2942 hw->adapter_stopped = 1;
2944 ixgbe_dev_free_queues(dev);
2946 ixgbe_disable_pcie_master(hw);
2948 /* reprogram the RAR[0] in case user changed it. */
2949 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2956 ixgbe_dev_reset(struct rte_eth_dev *dev)
2960 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2961 * its VF to make them align with it. The detailed notification
2962 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2963 * To avoid unexpected behavior in VF, currently reset of PF with
2964 * SR-IOV activation is not supported. It might be supported later.
2966 if (dev->data->sriov.active)
2969 ret = eth_ixgbe_dev_uninit(dev);
2973 ret = eth_ixgbe_dev_init(dev, NULL);
2979 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2980 struct ixgbe_hw_stats *hw_stats,
2981 struct ixgbe_macsec_stats *macsec_stats,
2982 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2983 uint64_t *total_qprc, uint64_t *total_qprdc)
2985 uint32_t bprc, lxon, lxoff, total;
2986 uint32_t delta_gprc = 0;
2988 /* Workaround for RX byte count not including CRC bytes when CRC
2989 * strip is enabled. CRC bytes are removed from counters when crc_strip
2992 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2993 IXGBE_HLREG0_RXCRCSTRP);
2995 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2996 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2997 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2998 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3000 for (i = 0; i < 8; i++) {
3001 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3003 /* global total per queue */
3004 hw_stats->mpc[i] += mp;
3005 /* Running comprehensive total for stats display */
3006 *total_missed_rx += hw_stats->mpc[i];
3007 if (hw->mac.type == ixgbe_mac_82598EB) {
3008 hw_stats->rnbc[i] +=
3009 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3010 hw_stats->pxonrxc[i] +=
3011 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3012 hw_stats->pxoffrxc[i] +=
3013 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3015 hw_stats->pxonrxc[i] +=
3016 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3017 hw_stats->pxoffrxc[i] +=
3018 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3019 hw_stats->pxon2offc[i] +=
3020 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3022 hw_stats->pxontxc[i] +=
3023 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3024 hw_stats->pxofftxc[i] +=
3025 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3027 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3028 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3029 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3030 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3032 delta_gprc += delta_qprc;
3034 hw_stats->qprc[i] += delta_qprc;
3035 hw_stats->qptc[i] += delta_qptc;
3037 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3038 hw_stats->qbrc[i] +=
3039 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3041 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
3043 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3044 hw_stats->qbtc[i] +=
3045 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3047 hw_stats->qprdc[i] += delta_qprdc;
3048 *total_qprdc += hw_stats->qprdc[i];
3050 *total_qprc += hw_stats->qprc[i];
3051 *total_qbrc += hw_stats->qbrc[i];
3053 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3054 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3055 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3058 * An errata states that gprc actually counts good + missed packets:
3059 * Workaround to set gprc to summated queue packet receives
3061 hw_stats->gprc = *total_qprc;
3063 if (hw->mac.type != ixgbe_mac_82598EB) {
3064 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3065 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3066 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3067 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3068 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3069 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3070 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3071 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3073 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3074 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3075 /* 82598 only has a counter in the high register */
3076 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3077 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3078 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3080 uint64_t old_tpr = hw_stats->tpr;
3082 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3083 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3086 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3088 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3089 hw_stats->gptc += delta_gptc;
3090 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3091 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3094 * Workaround: mprc hardware is incorrectly counting
3095 * broadcasts, so for now we subtract those.
3097 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3098 hw_stats->bprc += bprc;
3099 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3100 if (hw->mac.type == ixgbe_mac_82598EB)
3101 hw_stats->mprc -= bprc;
3103 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3104 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3105 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3106 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3107 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3108 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3110 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3111 hw_stats->lxontxc += lxon;
3112 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3113 hw_stats->lxofftxc += lxoff;
3114 total = lxon + lxoff;
3116 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3117 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3118 hw_stats->gptc -= total;
3119 hw_stats->mptc -= total;
3120 hw_stats->ptc64 -= total;
3121 hw_stats->gotc -= total * ETHER_MIN_LEN;
3123 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3124 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3125 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3126 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3127 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3128 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3129 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3130 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3131 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3132 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3133 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3134 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3135 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3136 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3137 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3138 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3139 /* Only read FCOE on 82599 */
3140 if (hw->mac.type != ixgbe_mac_82598EB) {
3141 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3142 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3143 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3144 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3145 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3148 /* Flow Director Stats registers */
3149 if (hw->mac.type != ixgbe_mac_82598EB) {
3150 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3151 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3152 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3153 IXGBE_FDIRUSTAT) & 0xFFFF;
3154 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3155 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3156 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3157 IXGBE_FDIRFSTAT) & 0xFFFF;
3158 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3159 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3161 /* MACsec Stats registers */
3162 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3163 macsec_stats->out_pkts_encrypted +=
3164 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3165 macsec_stats->out_pkts_protected +=
3166 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3167 macsec_stats->out_octets_encrypted +=
3168 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3169 macsec_stats->out_octets_protected +=
3170 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3171 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3172 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3173 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3174 macsec_stats->in_pkts_unknownsci +=
3175 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3176 macsec_stats->in_octets_decrypted +=
3177 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3178 macsec_stats->in_octets_validated +=
3179 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3180 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3181 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3182 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3183 for (i = 0; i < 2; i++) {
3184 macsec_stats->in_pkts_ok +=
3185 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3186 macsec_stats->in_pkts_invalid +=
3187 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3188 macsec_stats->in_pkts_notvalid +=
3189 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3191 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3192 macsec_stats->in_pkts_notusingsa +=
3193 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3197 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3200 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3202 struct ixgbe_hw *hw =
3203 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204 struct ixgbe_hw_stats *hw_stats =
3205 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3206 struct ixgbe_macsec_stats *macsec_stats =
3207 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3208 dev->data->dev_private);
3209 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3212 total_missed_rx = 0;
3217 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3218 &total_qbrc, &total_qprc, &total_qprdc);
3223 /* Fill out the rte_eth_stats statistics structure */
3224 stats->ipackets = total_qprc;
3225 stats->ibytes = total_qbrc;
3226 stats->opackets = hw_stats->gptc;
3227 stats->obytes = hw_stats->gotc;
3229 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3230 stats->q_ipackets[i] = hw_stats->qprc[i];
3231 stats->q_opackets[i] = hw_stats->qptc[i];
3232 stats->q_ibytes[i] = hw_stats->qbrc[i];
3233 stats->q_obytes[i] = hw_stats->qbtc[i];
3234 stats->q_errors[i] = hw_stats->qprdc[i];
3238 stats->imissed = total_missed_rx;
3239 stats->ierrors = hw_stats->crcerrs +
3256 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3258 struct ixgbe_hw_stats *stats =
3259 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3261 /* HW registers are cleared on read */
3262 ixgbe_dev_stats_get(dev, NULL);
3264 /* Reset software totals */
3265 memset(stats, 0, sizeof(*stats));
3268 /* This function calculates the number of xstats based on the current config */
3270 ixgbe_xstats_calc_num(void) {
3271 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3272 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3273 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3276 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3277 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3279 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3280 unsigned stat, i, count;
3282 if (xstats_names != NULL) {
3285 /* Note: limit >= cnt_stats checked upstream
3286 * in rte_eth_xstats_names()
3289 /* Extended stats from ixgbe_hw_stats */
3290 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3291 snprintf(xstats_names[count].name,
3292 sizeof(xstats_names[count].name),
3294 rte_ixgbe_stats_strings[i].name);
3299 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3300 snprintf(xstats_names[count].name,
3301 sizeof(xstats_names[count].name),
3303 rte_ixgbe_macsec_strings[i].name);
3307 /* RX Priority Stats */
3308 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3309 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3310 snprintf(xstats_names[count].name,
3311 sizeof(xstats_names[count].name),
3312 "rx_priority%u_%s", i,
3313 rte_ixgbe_rxq_strings[stat].name);
3318 /* TX Priority Stats */
3319 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3320 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3321 snprintf(xstats_names[count].name,
3322 sizeof(xstats_names[count].name),
3323 "tx_priority%u_%s", i,
3324 rte_ixgbe_txq_strings[stat].name);
3332 static int ixgbe_dev_xstats_get_names_by_id(
3333 struct rte_eth_dev *dev,
3334 struct rte_eth_xstat_name *xstats_names,
3335 const uint64_t *ids,
3339 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3340 unsigned int stat, i, count;
3342 if (xstats_names != NULL) {
3345 /* Note: limit >= cnt_stats checked upstream
3346 * in rte_eth_xstats_names()
3349 /* Extended stats from ixgbe_hw_stats */
3350 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3351 snprintf(xstats_names[count].name,
3352 sizeof(xstats_names[count].name),
3354 rte_ixgbe_stats_strings[i].name);
3359 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3360 snprintf(xstats_names[count].name,
3361 sizeof(xstats_names[count].name),
3363 rte_ixgbe_macsec_strings[i].name);
3367 /* RX Priority Stats */
3368 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3369 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3370 snprintf(xstats_names[count].name,
3371 sizeof(xstats_names[count].name),
3372 "rx_priority%u_%s", i,
3373 rte_ixgbe_rxq_strings[stat].name);
3378 /* TX Priority Stats */
3379 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3380 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3381 snprintf(xstats_names[count].name,
3382 sizeof(xstats_names[count].name),
3383 "tx_priority%u_%s", i,
3384 rte_ixgbe_txq_strings[stat].name);
3393 uint16_t size = ixgbe_xstats_calc_num();
3394 struct rte_eth_xstat_name xstats_names_copy[size];
3396 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3399 for (i = 0; i < limit; i++) {
3400 if (ids[i] >= size) {
3401 PMD_INIT_LOG(ERR, "id value isn't valid");
3404 strcpy(xstats_names[i].name,
3405 xstats_names_copy[ids[i]].name);
3410 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3411 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3415 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3418 if (xstats_names != NULL)
3419 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3420 snprintf(xstats_names[i].name,
3421 sizeof(xstats_names[i].name),
3422 "%s", rte_ixgbevf_stats_strings[i].name);
3423 return IXGBEVF_NB_XSTATS;
3427 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3430 struct ixgbe_hw *hw =
3431 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3432 struct ixgbe_hw_stats *hw_stats =
3433 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3434 struct ixgbe_macsec_stats *macsec_stats =
3435 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3436 dev->data->dev_private);
3437 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3438 unsigned i, stat, count = 0;
3440 count = ixgbe_xstats_calc_num();
3445 total_missed_rx = 0;
3450 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3451 &total_qbrc, &total_qprc, &total_qprdc);
3453 /* If this is a reset xstats is NULL, and we have cleared the
3454 * registers by reading them.
3459 /* Extended stats from ixgbe_hw_stats */
3461 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3462 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3463 rte_ixgbe_stats_strings[i].offset);
3464 xstats[count].id = count;
3469 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3470 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3471 rte_ixgbe_macsec_strings[i].offset);
3472 xstats[count].id = count;
3476 /* RX Priority Stats */
3477 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3478 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3479 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3480 rte_ixgbe_rxq_strings[stat].offset +
3481 (sizeof(uint64_t) * i));
3482 xstats[count].id = count;
3487 /* TX Priority Stats */
3488 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3489 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3490 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3491 rte_ixgbe_txq_strings[stat].offset +
3492 (sizeof(uint64_t) * i));
3493 xstats[count].id = count;
3501 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3502 uint64_t *values, unsigned int n)
3505 struct ixgbe_hw *hw =
3506 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507 struct ixgbe_hw_stats *hw_stats =
3508 IXGBE_DEV_PRIVATE_TO_STATS(
3509 dev->data->dev_private);
3510 struct ixgbe_macsec_stats *macsec_stats =
3511 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3512 dev->data->dev_private);
3513 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3514 unsigned int i, stat, count = 0;
3516 count = ixgbe_xstats_calc_num();
3518 if (!ids && n < count)
3521 total_missed_rx = 0;
3526 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3527 &total_missed_rx, &total_qbrc, &total_qprc,
3530 /* If this is a reset xstats is NULL, and we have cleared the
3531 * registers by reading them.
3533 if (!ids && !values)
3536 /* Extended stats from ixgbe_hw_stats */
3538 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3539 values[count] = *(uint64_t *)(((char *)hw_stats) +
3540 rte_ixgbe_stats_strings[i].offset);
3545 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3546 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3547 rte_ixgbe_macsec_strings[i].offset);
3551 /* RX Priority Stats */
3552 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3553 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3555 *(uint64_t *)(((char *)hw_stats) +
3556 rte_ixgbe_rxq_strings[stat].offset +
3557 (sizeof(uint64_t) * i));
3562 /* TX Priority Stats */
3563 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3564 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3566 *(uint64_t *)(((char *)hw_stats) +
3567 rte_ixgbe_txq_strings[stat].offset +
3568 (sizeof(uint64_t) * i));
3576 uint16_t size = ixgbe_xstats_calc_num();
3577 uint64_t values_copy[size];
3579 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3581 for (i = 0; i < n; i++) {
3582 if (ids[i] >= size) {
3583 PMD_INIT_LOG(ERR, "id value isn't valid");
3586 values[i] = values_copy[ids[i]];
3592 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3594 struct ixgbe_hw_stats *stats =
3595 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3596 struct ixgbe_macsec_stats *macsec_stats =
3597 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3598 dev->data->dev_private);
3600 unsigned count = ixgbe_xstats_calc_num();
3602 /* HW registers are cleared on read */
3603 ixgbe_dev_xstats_get(dev, NULL, count);
3605 /* Reset software totals */
3606 memset(stats, 0, sizeof(*stats));
3607 memset(macsec_stats, 0, sizeof(*macsec_stats));
3611 ixgbevf_update_stats(struct rte_eth_dev *dev)
3613 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3615 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3617 /* Good Rx packet, include VF loopback */
3618 UPDATE_VF_STAT(IXGBE_VFGPRC,
3619 hw_stats->last_vfgprc, hw_stats->vfgprc);
3621 /* Good Rx octets, include VF loopback */
3622 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3623 hw_stats->last_vfgorc, hw_stats->vfgorc);
3625 /* Good Tx packet, include VF loopback */
3626 UPDATE_VF_STAT(IXGBE_VFGPTC,
3627 hw_stats->last_vfgptc, hw_stats->vfgptc);
3629 /* Good Tx octets, include VF loopback */
3630 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3631 hw_stats->last_vfgotc, hw_stats->vfgotc);
3633 /* Rx Multicst Packet */
3634 UPDATE_VF_STAT(IXGBE_VFMPRC,
3635 hw_stats->last_vfmprc, hw_stats->vfmprc);
3639 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3642 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3643 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3646 if (n < IXGBEVF_NB_XSTATS)
3647 return IXGBEVF_NB_XSTATS;
3649 ixgbevf_update_stats(dev);
3654 /* Extended stats */
3655 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3657 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3658 rte_ixgbevf_stats_strings[i].offset);
3661 return IXGBEVF_NB_XSTATS;
3665 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3667 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3668 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3670 ixgbevf_update_stats(dev);
3675 stats->ipackets = hw_stats->vfgprc;
3676 stats->ibytes = hw_stats->vfgorc;
3677 stats->opackets = hw_stats->vfgptc;
3678 stats->obytes = hw_stats->vfgotc;
3683 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3685 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3686 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3688 /* Sync HW register to the last stats */
3689 ixgbevf_dev_stats_get(dev, NULL);
3691 /* reset HW current stats*/
3692 hw_stats->vfgprc = 0;
3693 hw_stats->vfgorc = 0;
3694 hw_stats->vfgptc = 0;
3695 hw_stats->vfgotc = 0;
3699 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3701 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702 u16 eeprom_verh, eeprom_verl;
3706 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3707 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3709 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3710 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3712 ret += 1; /* add the size of '\0' */
3713 if (fw_size < (u32)ret)
3720 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3722 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3723 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3724 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3726 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3727 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3728 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3730 * When DCB/VT is off, maximum number of queues changes,
3731 * except for 82598EB, which remains constant.
3733 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3734 hw->mac.type != ixgbe_mac_82598EB)
3735 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3737 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3738 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3739 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3740 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3741 dev_info->max_vfs = pci_dev->max_vfs;
3742 if (hw->mac.type == ixgbe_mac_82598EB)
3743 dev_info->max_vmdq_pools = ETH_16_POOLS;
3745 dev_info->max_vmdq_pools = ETH_64_POOLS;
3746 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3747 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3748 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3749 dev_info->rx_queue_offload_capa);
3750 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3751 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3753 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3755 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3756 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3757 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3759 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3764 dev_info->default_txconf = (struct rte_eth_txconf) {
3766 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3767 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3768 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3770 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3771 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3775 dev_info->rx_desc_lim = rx_desc_lim;
3776 dev_info->tx_desc_lim = tx_desc_lim;
3778 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3779 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3780 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3782 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3783 if (hw->mac.type == ixgbe_mac_X540 ||
3784 hw->mac.type == ixgbe_mac_X540_vf ||
3785 hw->mac.type == ixgbe_mac_X550 ||
3786 hw->mac.type == ixgbe_mac_X550_vf) {
3787 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3789 if (hw->mac.type == ixgbe_mac_X550) {
3790 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3791 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3794 /* Driver-preferred Rx/Tx parameters */
3795 dev_info->default_rxportconf.burst_size = 32;
3796 dev_info->default_txportconf.burst_size = 32;
3797 dev_info->default_rxportconf.nb_queues = 1;
3798 dev_info->default_txportconf.nb_queues = 1;
3799 dev_info->default_rxportconf.ring_size = 256;
3800 dev_info->default_txportconf.ring_size = 256;
3803 static const uint32_t *
3804 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3806 static const uint32_t ptypes[] = {
3807 /* For non-vec functions,
3808 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3809 * for vec functions,
3810 * refers to _recv_raw_pkts_vec().
3814 RTE_PTYPE_L3_IPV4_EXT,
3816 RTE_PTYPE_L3_IPV6_EXT,
3820 RTE_PTYPE_TUNNEL_IP,
3821 RTE_PTYPE_INNER_L3_IPV6,
3822 RTE_PTYPE_INNER_L3_IPV6_EXT,
3823 RTE_PTYPE_INNER_L4_TCP,
3824 RTE_PTYPE_INNER_L4_UDP,
3828 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3829 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3830 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3831 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3834 #if defined(RTE_ARCH_X86)
3835 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3836 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3843 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3844 struct rte_eth_dev_info *dev_info)
3846 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3847 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3850 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3851 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3852 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3853 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3854 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3855 dev_info->max_vfs = pci_dev->max_vfs;
3856 if (hw->mac.type == ixgbe_mac_82598EB)
3857 dev_info->max_vmdq_pools = ETH_16_POOLS;
3859 dev_info->max_vmdq_pools = ETH_64_POOLS;
3860 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3861 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3862 dev_info->rx_queue_offload_capa);
3863 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3864 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3866 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3868 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3869 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3870 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3872 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3877 dev_info->default_txconf = (struct rte_eth_txconf) {
3879 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3880 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3881 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3883 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3884 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3888 dev_info->rx_desc_lim = rx_desc_lim;
3889 dev_info->tx_desc_lim = tx_desc_lim;
3893 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3894 int *link_up, int wait_to_complete)
3896 struct ixgbe_mbx_info *mbx = &hw->mbx;
3897 struct ixgbe_mac_info *mac = &hw->mac;
3898 uint32_t links_reg, in_msg;
3901 /* If we were hit with a reset drop the link */
3902 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3903 mac->get_link_status = true;
3905 if (!mac->get_link_status)
3908 /* if link status is down no point in checking to see if pf is up */
3909 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3910 if (!(links_reg & IXGBE_LINKS_UP))
3913 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3914 * before the link status is correct
3916 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
3919 for (i = 0; i < 5; i++) {
3921 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3923 if (!(links_reg & IXGBE_LINKS_UP))
3928 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3929 case IXGBE_LINKS_SPEED_10G_82599:
3930 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3931 if (hw->mac.type >= ixgbe_mac_X550) {
3932 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3933 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3936 case IXGBE_LINKS_SPEED_1G_82599:
3937 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3939 case IXGBE_LINKS_SPEED_100_82599:
3940 *speed = IXGBE_LINK_SPEED_100_FULL;
3941 if (hw->mac.type == ixgbe_mac_X550) {
3942 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3943 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3946 case IXGBE_LINKS_SPEED_10_X550EM_A:
3947 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3948 /* Since Reserved in older MAC's */
3949 if (hw->mac.type >= ixgbe_mac_X550)
3950 *speed = IXGBE_LINK_SPEED_10_FULL;
3953 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3956 /* if the read failed it could just be a mailbox collision, best wait
3957 * until we are called again and don't report an error
3959 if (mbx->ops.read(hw, &in_msg, 1, 0))
3962 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3963 /* msg is not CTS and is NACK we must have lost CTS status */
3964 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3965 mac->get_link_status = false;
3969 /* the pf is talking, if we timed out in the past we reinit */
3970 if (!mbx->timeout) {
3975 /* if we passed all the tests above then the link is up and we no
3976 * longer need to check for link
3978 mac->get_link_status = false;
3981 *link_up = !mac->get_link_status;
3986 ixgbe_dev_setup_link_alarm_handler(void *param)
3988 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3990 struct ixgbe_interrupt *intr =
3991 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3993 bool autoneg = false;
3995 speed = hw->phy.autoneg_advertised;
3997 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3999 ixgbe_setup_link(hw, speed, true);
4001 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4004 /* return 0 means link status changed, -1 means not changed */
4006 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4007 int wait_to_complete, int vf)
4009 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4010 struct rte_eth_link link;
4011 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4012 struct ixgbe_interrupt *intr =
4013 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4018 memset(&link, 0, sizeof(link));
4019 link.link_status = ETH_LINK_DOWN;
4020 link.link_speed = ETH_SPEED_NUM_NONE;
4021 link.link_duplex = ETH_LINK_HALF_DUPLEX;
4022 link.link_autoneg = ETH_LINK_AUTONEG;
4024 hw->mac.get_link_status = true;
4026 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4027 return rte_eth_linkstatus_set(dev, &link);
4029 /* check if it needs to wait to complete, if lsc interrupt is enabled */
4030 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4034 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4036 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4039 link.link_speed = ETH_SPEED_NUM_100M;
4040 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4041 return rte_eth_linkstatus_set(dev, &link);
4045 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4046 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4047 rte_eal_alarm_set(10,
4048 ixgbe_dev_setup_link_alarm_handler, dev);
4050 return rte_eth_linkstatus_set(dev, &link);
4053 link.link_status = ETH_LINK_UP;
4054 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4056 switch (link_speed) {
4058 case IXGBE_LINK_SPEED_UNKNOWN:
4059 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4060 link.link_speed = ETH_SPEED_NUM_100M;
4063 case IXGBE_LINK_SPEED_100_FULL:
4064 link.link_speed = ETH_SPEED_NUM_100M;
4067 case IXGBE_LINK_SPEED_1GB_FULL:
4068 link.link_speed = ETH_SPEED_NUM_1G;
4071 case IXGBE_LINK_SPEED_2_5GB_FULL:
4072 link.link_speed = ETH_SPEED_NUM_2_5G;
4075 case IXGBE_LINK_SPEED_5GB_FULL:
4076 link.link_speed = ETH_SPEED_NUM_5G;
4079 case IXGBE_LINK_SPEED_10GB_FULL:
4080 link.link_speed = ETH_SPEED_NUM_10G;
4084 return rte_eth_linkstatus_set(dev, &link);
4088 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4090 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4094 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4096 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4100 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4105 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4106 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4107 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4111 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4113 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4116 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4117 fctrl &= (~IXGBE_FCTRL_UPE);
4118 if (dev->data->all_multicast == 1)
4119 fctrl |= IXGBE_FCTRL_MPE;
4121 fctrl &= (~IXGBE_FCTRL_MPE);
4122 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4126 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4128 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4131 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4132 fctrl |= IXGBE_FCTRL_MPE;
4133 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4137 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4139 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4142 if (dev->data->promiscuous == 1)
4143 return; /* must remain in all_multicast mode */
4145 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4146 fctrl &= (~IXGBE_FCTRL_MPE);
4147 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4151 * It clears the interrupt causes and enables the interrupt.
4152 * It will be called once only during nic initialized.
4155 * Pointer to struct rte_eth_dev.
4157 * Enable or Disable.
4160 * - On success, zero.
4161 * - On failure, a negative value.
4164 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4166 struct ixgbe_interrupt *intr =
4167 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4169 ixgbe_dev_link_status_print(dev);
4171 intr->mask |= IXGBE_EICR_LSC;
4173 intr->mask &= ~IXGBE_EICR_LSC;
4179 * It clears the interrupt causes and enables the interrupt.
4180 * It will be called once only during nic initialized.
4183 * Pointer to struct rte_eth_dev.
4186 * - On success, zero.
4187 * - On failure, a negative value.
4190 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4192 struct ixgbe_interrupt *intr =
4193 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4195 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4201 * It clears the interrupt causes and enables the interrupt.
4202 * It will be called once only during nic initialized.
4205 * Pointer to struct rte_eth_dev.
4208 * - On success, zero.
4209 * - On failure, a negative value.
4212 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4214 struct ixgbe_interrupt *intr =
4215 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4217 intr->mask |= IXGBE_EICR_LINKSEC;
4223 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4226 * Pointer to struct rte_eth_dev.
4229 * - On success, zero.
4230 * - On failure, a negative value.
4233 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4236 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4237 struct ixgbe_interrupt *intr =
4238 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4240 /* clear all cause mask */
4241 ixgbe_disable_intr(hw);
4243 /* read-on-clear nic registers here */
4244 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4245 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4249 /* set flag for async link update */
4250 if (eicr & IXGBE_EICR_LSC)
4251 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4253 if (eicr & IXGBE_EICR_MAILBOX)
4254 intr->flags |= IXGBE_FLAG_MAILBOX;
4256 if (eicr & IXGBE_EICR_LINKSEC)
4257 intr->flags |= IXGBE_FLAG_MACSEC;
4259 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4260 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4261 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4262 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4268 * It gets and then prints the link status.
4271 * Pointer to struct rte_eth_dev.
4274 * - On success, zero.
4275 * - On failure, a negative value.
4278 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4280 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4281 struct rte_eth_link link;
4283 rte_eth_linkstatus_get(dev, &link);
4285 if (link.link_status) {
4286 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4287 (int)(dev->data->port_id),
4288 (unsigned)link.link_speed,
4289 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4290 "full-duplex" : "half-duplex");
4292 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4293 (int)(dev->data->port_id));
4295 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4296 pci_dev->addr.domain,
4298 pci_dev->addr.devid,
4299 pci_dev->addr.function);
4303 * It executes link_update after knowing an interrupt occurred.
4306 * Pointer to struct rte_eth_dev.
4309 * - On success, zero.
4310 * - On failure, a negative value.
4313 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4315 struct ixgbe_interrupt *intr =
4316 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4318 struct ixgbe_hw *hw =
4319 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4321 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4323 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4324 ixgbe_pf_mbx_process(dev);
4325 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4328 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4329 ixgbe_handle_lasi(hw);
4330 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4333 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4334 struct rte_eth_link link;
4336 /* get the link status before link update, for predicting later */
4337 rte_eth_linkstatus_get(dev, &link);
4339 ixgbe_dev_link_update(dev, 0);
4342 if (!link.link_status)
4343 /* handle it 1 sec later, wait it being stable */
4344 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4345 /* likely to down */
4347 /* handle it 4 sec later, wait it being stable */
4348 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4350 ixgbe_dev_link_status_print(dev);
4351 if (rte_eal_alarm_set(timeout * 1000,
4352 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4353 PMD_DRV_LOG(ERR, "Error setting alarm");
4355 /* remember original mask */
4356 intr->mask_original = intr->mask;
4357 /* only disable lsc interrupt */
4358 intr->mask &= ~IXGBE_EIMS_LSC;
4362 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4363 ixgbe_enable_intr(dev);
4369 * Interrupt handler which shall be registered for alarm callback for delayed
4370 * handling specific interrupt to wait for the stable nic state. As the
4371 * NIC interrupt state is not stable for ixgbe after link is just down,
4372 * it needs to wait 4 seconds to get the stable status.
4375 * Pointer to interrupt handle.
4377 * The address of parameter (struct rte_eth_dev *) regsitered before.
4383 ixgbe_dev_interrupt_delayed_handler(void *param)
4385 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4386 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4387 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4388 struct ixgbe_interrupt *intr =
4389 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4390 struct ixgbe_hw *hw =
4391 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4394 ixgbe_disable_intr(hw);
4396 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4397 if (eicr & IXGBE_EICR_MAILBOX)
4398 ixgbe_pf_mbx_process(dev);
4400 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4401 ixgbe_handle_lasi(hw);
4402 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4405 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4406 ixgbe_dev_link_update(dev, 0);
4407 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4408 ixgbe_dev_link_status_print(dev);
4409 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4413 if (intr->flags & IXGBE_FLAG_MACSEC) {
4414 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4416 intr->flags &= ~IXGBE_FLAG_MACSEC;
4419 /* restore original mask */
4420 intr->mask = intr->mask_original;
4421 intr->mask_original = 0;
4423 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4424 ixgbe_enable_intr(dev);
4425 rte_intr_enable(intr_handle);
4429 * Interrupt handler triggered by NIC for handling
4430 * specific interrupt.
4433 * Pointer to interrupt handle.
4435 * The address of parameter (struct rte_eth_dev *) regsitered before.
4441 ixgbe_dev_interrupt_handler(void *param)
4443 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4445 ixgbe_dev_interrupt_get_status(dev);
4446 ixgbe_dev_interrupt_action(dev);
4450 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4452 struct ixgbe_hw *hw;
4454 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4455 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4459 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4461 struct ixgbe_hw *hw;
4463 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4468 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4470 struct ixgbe_hw *hw;
4476 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478 fc_conf->pause_time = hw->fc.pause_time;
4479 fc_conf->high_water = hw->fc.high_water[0];
4480 fc_conf->low_water = hw->fc.low_water[0];
4481 fc_conf->send_xon = hw->fc.send_xon;
4482 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4485 * Return rx_pause status according to actual setting of
4488 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4489 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4495 * Return tx_pause status according to actual setting of
4498 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4499 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4504 if (rx_pause && tx_pause)
4505 fc_conf->mode = RTE_FC_FULL;
4507 fc_conf->mode = RTE_FC_RX_PAUSE;
4509 fc_conf->mode = RTE_FC_TX_PAUSE;
4511 fc_conf->mode = RTE_FC_NONE;
4517 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4519 struct ixgbe_hw *hw;
4521 uint32_t rx_buf_size;
4522 uint32_t max_high_water;
4524 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4531 PMD_INIT_FUNC_TRACE();
4533 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4534 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4535 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4538 * At least reserve one Ethernet frame for watermark
4539 * high_water/low_water in kilo bytes for ixgbe
4541 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4542 if ((fc_conf->high_water > max_high_water) ||
4543 (fc_conf->high_water < fc_conf->low_water)) {
4544 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4545 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4549 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4550 hw->fc.pause_time = fc_conf->pause_time;
4551 hw->fc.high_water[0] = fc_conf->high_water;
4552 hw->fc.low_water[0] = fc_conf->low_water;
4553 hw->fc.send_xon = fc_conf->send_xon;
4554 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4556 err = ixgbe_fc_enable(hw);
4558 /* Not negotiated is not an error case */
4559 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4561 /* check if we want to forward MAC frames - driver doesn't have native
4562 * capability to do that, so we'll write the registers ourselves */
4564 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4566 /* set or clear MFLCN.PMCF bit depending on configuration */
4567 if (fc_conf->mac_ctrl_frame_fwd != 0)
4568 mflcn |= IXGBE_MFLCN_PMCF;
4570 mflcn &= ~IXGBE_MFLCN_PMCF;
4572 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4573 IXGBE_WRITE_FLUSH(hw);
4578 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4583 * ixgbe_pfc_enable_generic - Enable flow control
4584 * @hw: pointer to hardware structure
4585 * @tc_num: traffic class number
4586 * Enable flow control according to the current settings.
4589 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4592 uint32_t mflcn_reg, fccfg_reg;
4594 uint32_t fcrtl, fcrth;
4598 /* Validate the water mark configuration */
4599 if (!hw->fc.pause_time) {
4600 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4604 /* Low water mark of zero causes XOFF floods */
4605 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4606 /* High/Low water can not be 0 */
4607 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4608 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4609 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4613 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4614 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4615 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4619 /* Negotiate the fc mode to use */
4620 ixgbe_fc_autoneg(hw);
4622 /* Disable any previous flow control settings */
4623 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4624 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4626 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4627 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4629 switch (hw->fc.current_mode) {
4632 * If the count of enabled RX Priority Flow control >1,
4633 * and the TX pause can not be disabled
4636 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4637 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4638 if (reg & IXGBE_FCRTH_FCEN)
4642 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4644 case ixgbe_fc_rx_pause:
4646 * Rx Flow control is enabled and Tx Flow control is
4647 * disabled by software override. Since there really
4648 * isn't a way to advertise that we are capable of RX
4649 * Pause ONLY, we will advertise that we support both
4650 * symmetric and asymmetric Rx PAUSE. Later, we will
4651 * disable the adapter's ability to send PAUSE frames.
4653 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4655 * If the count of enabled RX Priority Flow control >1,
4656 * and the TX pause can not be disabled
4659 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4660 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4661 if (reg & IXGBE_FCRTH_FCEN)
4665 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4667 case ixgbe_fc_tx_pause:
4669 * Tx Flow control is enabled, and Rx Flow control is
4670 * disabled by software override.
4672 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4675 /* Flow control (both Rx and Tx) is enabled by SW override. */
4676 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4677 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4680 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4681 ret_val = IXGBE_ERR_CONFIG;
4685 /* Set 802.3x based flow control settings. */
4686 mflcn_reg |= IXGBE_MFLCN_DPF;
4687 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4688 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4690 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4691 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4692 hw->fc.high_water[tc_num]) {
4693 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4694 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4695 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4697 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4699 * In order to prevent Tx hangs when the internal Tx
4700 * switch is enabled we must set the high water mark
4701 * to the maximum FCRTH value. This allows the Tx
4702 * switch to function even under heavy Rx workloads.
4704 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4706 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4708 /* Configure pause time (2 TCs per register) */
4709 reg = hw->fc.pause_time * 0x00010001;
4710 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4711 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4713 /* Configure flow control refresh threshold value */
4714 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4721 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4723 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4724 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4726 if (hw->mac.type != ixgbe_mac_82598EB) {
4727 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4733 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4736 uint32_t rx_buf_size;
4737 uint32_t max_high_water;
4739 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4740 struct ixgbe_hw *hw =
4741 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4742 struct ixgbe_dcb_config *dcb_config =
4743 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4745 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4752 PMD_INIT_FUNC_TRACE();
4754 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4755 tc_num = map[pfc_conf->priority];
4756 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4757 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4759 * At least reserve one Ethernet frame for watermark
4760 * high_water/low_water in kilo bytes for ixgbe
4762 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4763 if ((pfc_conf->fc.high_water > max_high_water) ||
4764 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4765 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4766 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4770 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4771 hw->fc.pause_time = pfc_conf->fc.pause_time;
4772 hw->fc.send_xon = pfc_conf->fc.send_xon;
4773 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4774 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4776 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4778 /* Not negotiated is not an error case */
4779 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4782 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4787 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4788 struct rte_eth_rss_reta_entry64 *reta_conf,
4791 uint16_t i, sp_reta_size;
4794 uint16_t idx, shift;
4795 struct ixgbe_adapter *adapter =
4796 (struct ixgbe_adapter *)dev->data->dev_private;
4797 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800 PMD_INIT_FUNC_TRACE();
4802 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4803 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4808 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4809 if (reta_size != sp_reta_size) {
4810 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4811 "(%d) doesn't match the number hardware can supported "
4812 "(%d)", reta_size, sp_reta_size);
4816 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4817 idx = i / RTE_RETA_GROUP_SIZE;
4818 shift = i % RTE_RETA_GROUP_SIZE;
4819 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4823 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4824 if (mask == IXGBE_4_BIT_MASK)
4827 r = IXGBE_READ_REG(hw, reta_reg);
4828 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4829 if (mask & (0x1 << j))
4830 reta |= reta_conf[idx].reta[shift + j] <<
4833 reta |= r & (IXGBE_8_BIT_MASK <<
4836 IXGBE_WRITE_REG(hw, reta_reg, reta);
4838 adapter->rss_reta_updated = 1;
4844 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4845 struct rte_eth_rss_reta_entry64 *reta_conf,
4848 uint16_t i, sp_reta_size;
4851 uint16_t idx, shift;
4852 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855 PMD_INIT_FUNC_TRACE();
4856 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4857 if (reta_size != sp_reta_size) {
4858 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4859 "(%d) doesn't match the number hardware can supported "
4860 "(%d)", reta_size, sp_reta_size);
4864 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4865 idx = i / RTE_RETA_GROUP_SIZE;
4866 shift = i % RTE_RETA_GROUP_SIZE;
4867 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4872 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4873 reta = IXGBE_READ_REG(hw, reta_reg);
4874 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4875 if (mask & (0x1 << j))
4876 reta_conf[idx].reta[shift + j] =
4877 ((reta >> (CHAR_BIT * j)) &
4886 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4887 uint32_t index, uint32_t pool)
4889 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4890 uint32_t enable_addr = 1;
4892 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4897 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4899 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4901 ixgbe_clear_rar(hw, index);
4905 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4907 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4909 ixgbe_remove_rar(dev, 0);
4910 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4916 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4918 if (strcmp(dev->device->driver->name, drv->driver.name))
4925 is_ixgbe_supported(struct rte_eth_dev *dev)
4927 return is_device_supported(dev, &rte_ixgbe_pmd);
4931 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4935 struct ixgbe_hw *hw;
4936 struct rte_eth_dev_info dev_info;
4937 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4938 struct rte_eth_dev_data *dev_data = dev->data;
4940 ixgbe_dev_info_get(dev, &dev_info);
4942 /* check that mtu is within the allowed range */
4943 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4946 /* If device is started, refuse mtu that requires the support of
4947 * scattered packets when this feature has not been enabled before.
4949 if (dev_data->dev_started && !dev_data->scattered_rx &&
4950 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4951 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4952 PMD_INIT_LOG(ERR, "Stop port first.");
4956 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4959 /* switch to jumbo mode if needed */
4960 if (frame_size > ETHER_MAX_LEN) {
4961 dev->data->dev_conf.rxmode.offloads |=
4962 DEV_RX_OFFLOAD_JUMBO_FRAME;
4963 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4965 dev->data->dev_conf.rxmode.offloads &=
4966 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4967 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4969 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4971 /* update max frame size */
4972 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4974 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4975 maxfrs &= 0x0000FFFF;
4976 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4977 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4983 * Virtual Function operations
4986 ixgbevf_intr_disable(struct rte_eth_dev *dev)
4988 struct ixgbe_interrupt *intr =
4989 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4990 struct ixgbe_hw *hw =
4991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4993 PMD_INIT_FUNC_TRACE();
4995 /* Clear interrupt mask to stop from interrupts being generated */
4996 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4998 IXGBE_WRITE_FLUSH(hw);
5000 /* Clear mask value. */
5005 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5007 struct ixgbe_interrupt *intr =
5008 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5009 struct ixgbe_hw *hw =
5010 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5012 PMD_INIT_FUNC_TRACE();
5014 /* VF enable interrupt autoclean */
5015 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5016 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5017 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5019 IXGBE_WRITE_FLUSH(hw);
5021 /* Save IXGBE_VTEIMS value to mask. */
5022 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5026 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5028 struct rte_eth_conf *conf = &dev->data->dev_conf;
5029 struct ixgbe_adapter *adapter =
5030 (struct ixgbe_adapter *)dev->data->dev_private;
5032 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5033 dev->data->port_id);
5036 * VF has no ability to enable/disable HW CRC
5037 * Keep the persistent behavior the same as Host PF
5039 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5040 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5041 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5042 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5045 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5046 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5047 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5052 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5053 * allocation or vector Rx preconditions we will reset it.
5055 adapter->rx_bulk_alloc_allowed = true;
5056 adapter->rx_vec_allowed = true;
5062 ixgbevf_dev_start(struct rte_eth_dev *dev)
5064 struct ixgbe_hw *hw =
5065 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5066 uint32_t intr_vector = 0;
5067 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5068 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5072 PMD_INIT_FUNC_TRACE();
5074 /* Stop the link setup handler before resetting the HW. */
5075 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5077 err = hw->mac.ops.reset_hw(hw);
5079 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5082 hw->mac.get_link_status = true;
5084 /* negotiate mailbox API version to use with the PF. */
5085 ixgbevf_negotiate_api(hw);
5087 ixgbevf_dev_tx_init(dev);
5089 /* This can fail when allocating mbufs for descriptor rings */
5090 err = ixgbevf_dev_rx_init(dev);
5092 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5093 ixgbe_dev_clear_queues(dev);
5098 ixgbevf_set_vfta_all(dev, 1);
5101 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5102 ETH_VLAN_EXTEND_MASK;
5103 err = ixgbevf_vlan_offload_config(dev, mask);
5105 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5106 ixgbe_dev_clear_queues(dev);
5110 ixgbevf_dev_rxtx_start(dev);
5112 /* check and configure queue intr-vector mapping */
5113 if (rte_intr_cap_multiple(intr_handle) &&
5114 dev->data->dev_conf.intr_conf.rxq) {
5115 /* According to datasheet, only vector 0/1/2 can be used,
5116 * now only one vector is used for Rx queue
5119 if (rte_intr_efd_enable(intr_handle, intr_vector))
5123 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5124 intr_handle->intr_vec =
5125 rte_zmalloc("intr_vec",
5126 dev->data->nb_rx_queues * sizeof(int), 0);
5127 if (intr_handle->intr_vec == NULL) {
5128 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5129 " intr_vec", dev->data->nb_rx_queues);
5133 ixgbevf_configure_msix(dev);
5135 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5136 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5137 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5138 * is not cleared, it will fail when following rte_intr_enable( ) tries
5139 * to map Rx queue interrupt to other VFIO vectors.
5140 * So clear uio/vfio intr/evevnfd first to avoid failure.
5142 rte_intr_disable(intr_handle);
5144 rte_intr_enable(intr_handle);
5146 /* Re-enable interrupt for VF */
5147 ixgbevf_intr_enable(dev);
5150 * Update link status right before return, because it may
5151 * start link configuration process in a separate thread.
5153 ixgbevf_dev_link_update(dev, 0);
5159 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5161 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5162 struct ixgbe_adapter *adapter =
5163 (struct ixgbe_adapter *)dev->data->dev_private;
5164 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5165 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5167 PMD_INIT_FUNC_TRACE();
5169 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev);
5171 ixgbevf_intr_disable(dev);
5173 hw->adapter_stopped = 1;
5174 ixgbe_stop_adapter(hw);
5177 * Clear what we set, but we still keep shadow_vfta to
5178 * restore after device starts
5180 ixgbevf_set_vfta_all(dev, 0);
5182 /* Clear stored conf */
5183 dev->data->scattered_rx = 0;
5185 ixgbe_dev_clear_queues(dev);
5187 /* Clean datapath event and queue/vec mapping */
5188 rte_intr_efd_disable(intr_handle);
5189 if (intr_handle->intr_vec != NULL) {
5190 rte_free(intr_handle->intr_vec);
5191 intr_handle->intr_vec = NULL;
5194 adapter->rss_reta_updated = 0;
5198 ixgbevf_dev_close(struct rte_eth_dev *dev)
5200 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5202 PMD_INIT_FUNC_TRACE();
5206 ixgbevf_dev_stop(dev);
5208 ixgbe_dev_free_queues(dev);
5211 * Remove the VF MAC address ro ensure
5212 * that the VF traffic goes to the PF
5213 * after stop, close and detach of the VF
5215 ixgbevf_remove_mac_addr(dev, 0);
5222 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5226 ret = eth_ixgbevf_dev_uninit(dev);
5230 ret = eth_ixgbevf_dev_init(dev);
5235 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5237 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5238 struct ixgbe_vfta *shadow_vfta =
5239 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5240 int i = 0, j = 0, vfta = 0, mask = 1;
5242 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5243 vfta = shadow_vfta->vfta[i];
5246 for (j = 0; j < 32; j++) {
5248 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5258 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5260 struct ixgbe_hw *hw =
5261 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5262 struct ixgbe_vfta *shadow_vfta =
5263 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5264 uint32_t vid_idx = 0;
5265 uint32_t vid_bit = 0;
5268 PMD_INIT_FUNC_TRACE();
5270 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5271 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5273 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5276 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5277 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5279 /* Save what we set and retore it after device reset */
5281 shadow_vfta->vfta[vid_idx] |= vid_bit;
5283 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5289 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5291 struct ixgbe_hw *hw =
5292 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5295 PMD_INIT_FUNC_TRACE();
5297 if (queue >= hw->mac.max_rx_queues)
5300 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5302 ctrl |= IXGBE_RXDCTL_VME;
5304 ctrl &= ~IXGBE_RXDCTL_VME;
5305 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5307 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5311 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5313 struct ixgbe_rx_queue *rxq;
5317 /* VF function only support hw strip feature, others are not support */
5318 if (mask & ETH_VLAN_STRIP_MASK) {
5319 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5320 rxq = dev->data->rx_queues[i];
5321 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5322 ixgbevf_vlan_strip_queue_set(dev, i, on);
5330 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5332 ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5334 ixgbevf_vlan_offload_config(dev, mask);
5340 ixgbe_vt_check(struct ixgbe_hw *hw)
5344 /* if Virtualization Technology is enabled */
5345 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5346 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5347 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5355 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5357 uint32_t vector = 0;
5359 switch (hw->mac.mc_filter_type) {
5360 case 0: /* use bits [47:36] of the address */
5361 vector = ((uc_addr->addr_bytes[4] >> 4) |
5362 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5364 case 1: /* use bits [46:35] of the address */
5365 vector = ((uc_addr->addr_bytes[4] >> 3) |
5366 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5368 case 2: /* use bits [45:34] of the address */
5369 vector = ((uc_addr->addr_bytes[4] >> 2) |
5370 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5372 case 3: /* use bits [43:32] of the address */
5373 vector = ((uc_addr->addr_bytes[4]) |
5374 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5376 default: /* Invalid mc_filter_type */
5380 /* vector can only be 12-bits or boundary will be exceeded */
5386 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5394 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5395 const uint32_t ixgbe_uta_bit_shift = 5;
5396 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5397 const uint32_t bit1 = 0x1;
5399 struct ixgbe_hw *hw =
5400 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5401 struct ixgbe_uta_info *uta_info =
5402 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5404 /* The UTA table only exists on 82599 hardware and newer */
5405 if (hw->mac.type < ixgbe_mac_82599EB)
5408 vector = ixgbe_uta_vector(hw, mac_addr);
5409 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5410 uta_shift = vector & ixgbe_uta_bit_mask;
5412 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5416 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5418 uta_info->uta_in_use++;
5419 reg_val |= (bit1 << uta_shift);
5420 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5422 uta_info->uta_in_use--;
5423 reg_val &= ~(bit1 << uta_shift);
5424 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5427 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5429 if (uta_info->uta_in_use > 0)
5430 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5431 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5433 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5439 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5442 struct ixgbe_hw *hw =
5443 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5444 struct ixgbe_uta_info *uta_info =
5445 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5447 /* The UTA table only exists on 82599 hardware and newer */
5448 if (hw->mac.type < ixgbe_mac_82599EB)
5452 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5453 uta_info->uta_shadow[i] = ~0;
5454 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5457 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5458 uta_info->uta_shadow[i] = 0;
5459 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5467 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5469 uint32_t new_val = orig_val;
5471 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5472 new_val |= IXGBE_VMOLR_AUPE;
5473 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5474 new_val |= IXGBE_VMOLR_ROMPE;
5475 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5476 new_val |= IXGBE_VMOLR_ROPE;
5477 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5478 new_val |= IXGBE_VMOLR_BAM;
5479 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5480 new_val |= IXGBE_VMOLR_MPE;
5485 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5486 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5487 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5488 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5489 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5490 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5491 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5494 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5495 struct rte_eth_mirror_conf *mirror_conf,
5496 uint8_t rule_id, uint8_t on)
5498 uint32_t mr_ctl, vlvf;
5499 uint32_t mp_lsb = 0;
5500 uint32_t mv_msb = 0;
5501 uint32_t mv_lsb = 0;
5502 uint32_t mp_msb = 0;
5505 uint64_t vlan_mask = 0;
5507 const uint8_t pool_mask_offset = 32;
5508 const uint8_t vlan_mask_offset = 32;
5509 const uint8_t dst_pool_offset = 8;
5510 const uint8_t rule_mr_offset = 4;
5511 const uint8_t mirror_rule_mask = 0x0F;
5513 struct ixgbe_mirror_info *mr_info =
5514 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5515 struct ixgbe_hw *hw =
5516 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5517 uint8_t mirror_type = 0;
5519 if (ixgbe_vt_check(hw) < 0)
5522 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5525 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5526 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5527 mirror_conf->rule_type);
5531 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5532 mirror_type |= IXGBE_MRCTL_VLME;
5533 /* Check if vlan id is valid and find conresponding VLAN ID
5536 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5537 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5538 /* search vlan id related pool vlan filter
5541 reg_index = ixgbe_find_vlvf_slot(
5543 mirror_conf->vlan.vlan_id[i],
5547 vlvf = IXGBE_READ_REG(hw,
5548 IXGBE_VLVF(reg_index));
5549 if ((vlvf & IXGBE_VLVF_VIEN) &&
5550 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5551 mirror_conf->vlan.vlan_id[i]))
5552 vlan_mask |= (1ULL << reg_index);
5559 mv_lsb = vlan_mask & 0xFFFFFFFF;
5560 mv_msb = vlan_mask >> vlan_mask_offset;
5562 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5563 mirror_conf->vlan.vlan_mask;
5564 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5565 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5566 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5567 mirror_conf->vlan.vlan_id[i];
5572 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5573 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5574 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5579 * if enable pool mirror, write related pool mask register,if disable
5580 * pool mirror, clear PFMRVM register
5582 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5583 mirror_type |= IXGBE_MRCTL_VPME;
5585 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5586 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5587 mr_info->mr_conf[rule_id].pool_mask =
5588 mirror_conf->pool_mask;
5593 mr_info->mr_conf[rule_id].pool_mask = 0;
5596 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5597 mirror_type |= IXGBE_MRCTL_UPME;
5598 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5599 mirror_type |= IXGBE_MRCTL_DPME;
5601 /* read mirror control register and recalculate it */
5602 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5605 mr_ctl |= mirror_type;
5606 mr_ctl &= mirror_rule_mask;
5607 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5609 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5612 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5613 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5615 /* write mirrror control register */
5616 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5618 /* write pool mirrror control register */
5619 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5620 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5621 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5624 /* write VLAN mirrror control register */
5625 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5626 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5627 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5635 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5638 uint32_t lsb_val = 0;
5639 uint32_t msb_val = 0;
5640 const uint8_t rule_mr_offset = 4;
5642 struct ixgbe_hw *hw =
5643 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5644 struct ixgbe_mirror_info *mr_info =
5645 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5647 if (ixgbe_vt_check(hw) < 0)
5650 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5653 memset(&mr_info->mr_conf[rule_id], 0,
5654 sizeof(struct rte_eth_mirror_conf));
5656 /* clear PFVMCTL register */
5657 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5659 /* clear pool mask register */
5660 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5661 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5663 /* clear vlan mask register */
5664 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5665 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5671 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5673 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5674 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5675 struct ixgbe_interrupt *intr =
5676 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5677 struct ixgbe_hw *hw =
5678 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5679 uint32_t vec = IXGBE_MISC_VEC_ID;
5681 if (rte_intr_allow_others(intr_handle))
5682 vec = IXGBE_RX_VEC_START;
5683 intr->mask |= (1 << vec);
5684 RTE_SET_USED(queue_id);
5685 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5687 rte_intr_enable(intr_handle);
5693 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5695 struct ixgbe_interrupt *intr =
5696 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5697 struct ixgbe_hw *hw =
5698 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5699 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5700 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5701 uint32_t vec = IXGBE_MISC_VEC_ID;
5703 if (rte_intr_allow_others(intr_handle))
5704 vec = IXGBE_RX_VEC_START;
5705 intr->mask &= ~(1 << vec);
5706 RTE_SET_USED(queue_id);
5707 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5713 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5715 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5716 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5718 struct ixgbe_hw *hw =
5719 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5720 struct ixgbe_interrupt *intr =
5721 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5723 if (queue_id < 16) {
5724 ixgbe_disable_intr(hw);
5725 intr->mask |= (1 << queue_id);
5726 ixgbe_enable_intr(dev);
5727 } else if (queue_id < 32) {
5728 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5729 mask &= (1 << queue_id);
5730 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5731 } else if (queue_id < 64) {
5732 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5733 mask &= (1 << (queue_id - 32));
5734 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5736 rte_intr_enable(intr_handle);
5742 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5745 struct ixgbe_hw *hw =
5746 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5747 struct ixgbe_interrupt *intr =
5748 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5750 if (queue_id < 16) {
5751 ixgbe_disable_intr(hw);
5752 intr->mask &= ~(1 << queue_id);
5753 ixgbe_enable_intr(dev);
5754 } else if (queue_id < 32) {
5755 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5756 mask &= ~(1 << queue_id);
5757 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5758 } else if (queue_id < 64) {
5759 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5760 mask &= ~(1 << (queue_id - 32));
5761 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5768 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5769 uint8_t queue, uint8_t msix_vector)
5773 if (direction == -1) {
5775 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5776 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5779 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5781 /* rx or tx cause */
5782 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5783 idx = ((16 * (queue & 1)) + (8 * direction));
5784 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5785 tmp &= ~(0xFF << idx);
5786 tmp |= (msix_vector << idx);
5787 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5792 * set the IVAR registers, mapping interrupt causes to vectors
5794 * pointer to ixgbe_hw struct
5796 * 0 for Rx, 1 for Tx, -1 for other causes
5798 * queue to map the corresponding interrupt to
5800 * the vector to map to the corresponding queue
5803 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5804 uint8_t queue, uint8_t msix_vector)
5808 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5809 if (hw->mac.type == ixgbe_mac_82598EB) {
5810 if (direction == -1)
5812 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5813 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5814 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5815 tmp |= (msix_vector << (8 * (queue & 0x3)));
5816 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5817 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5818 (hw->mac.type == ixgbe_mac_X540) ||
5819 (hw->mac.type == ixgbe_mac_X550)) {
5820 if (direction == -1) {
5822 idx = ((queue & 1) * 8);
5823 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5824 tmp &= ~(0xFF << idx);
5825 tmp |= (msix_vector << idx);
5826 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5828 /* rx or tx causes */
5829 idx = ((16 * (queue & 1)) + (8 * direction));
5830 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5831 tmp &= ~(0xFF << idx);
5832 tmp |= (msix_vector << idx);
5833 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5839 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5841 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5842 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5843 struct ixgbe_hw *hw =
5844 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5846 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5847 uint32_t base = IXGBE_MISC_VEC_ID;
5849 /* Configure VF other cause ivar */
5850 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5852 /* won't configure msix register if no mapping is done
5853 * between intr vector and event fd.
5855 if (!rte_intr_dp_is_en(intr_handle))
5858 if (rte_intr_allow_others(intr_handle)) {
5859 base = IXGBE_RX_VEC_START;
5860 vector_idx = IXGBE_RX_VEC_START;
5863 /* Configure all RX queues of VF */
5864 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5865 /* Force all queue use vector 0,
5866 * as IXGBE_VF_MAXMSIVECOTR = 1
5868 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5869 intr_handle->intr_vec[q_idx] = vector_idx;
5870 if (vector_idx < base + intr_handle->nb_efd - 1)
5874 /* As RX queue setting above show, all queues use the vector 0.
5875 * Set only the ITR value of IXGBE_MISC_VEC_ID.
5877 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
5878 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5879 | IXGBE_EITR_CNT_WDIS);
5883 * Sets up the hardware to properly generate MSI-X interrupts
5885 * board private structure
5888 ixgbe_configure_msix(struct rte_eth_dev *dev)
5890 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5891 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5892 struct ixgbe_hw *hw =
5893 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5894 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5895 uint32_t vec = IXGBE_MISC_VEC_ID;
5899 /* won't configure msix register if no mapping is done
5900 * between intr vector and event fd
5901 * but if misx has been enabled already, need to configure
5902 * auto clean, auto mask and throttling.
5904 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5905 if (!rte_intr_dp_is_en(intr_handle) &&
5906 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
5909 if (rte_intr_allow_others(intr_handle))
5910 vec = base = IXGBE_RX_VEC_START;
5912 /* setup GPIE for MSI-x mode */
5913 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5914 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5915 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5916 /* auto clearing and auto setting corresponding bits in EIMS
5917 * when MSI-X interrupt is triggered
5919 if (hw->mac.type == ixgbe_mac_82598EB) {
5920 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5922 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5923 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5925 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5927 /* Populate the IVAR table and set the ITR values to the
5928 * corresponding register.
5930 if (rte_intr_dp_is_en(intr_handle)) {
5931 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5933 /* by default, 1:1 mapping */
5934 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5935 intr_handle->intr_vec[queue_id] = vec;
5936 if (vec < base + intr_handle->nb_efd - 1)
5940 switch (hw->mac.type) {
5941 case ixgbe_mac_82598EB:
5942 ixgbe_set_ivar_map(hw, -1,
5943 IXGBE_IVAR_OTHER_CAUSES_INDEX,
5946 case ixgbe_mac_82599EB:
5947 case ixgbe_mac_X540:
5948 case ixgbe_mac_X550:
5949 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5955 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5956 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
5957 | IXGBE_EITR_CNT_WDIS);
5959 /* set up to autoclear timer, and the vectors */
5960 mask = IXGBE_EIMS_ENABLE_MASK;
5961 mask &= ~(IXGBE_EIMS_OTHER |
5962 IXGBE_EIMS_MAILBOX |
5965 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5969 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5970 uint16_t queue_idx, uint16_t tx_rate)
5972 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5973 struct rte_eth_rxmode *rxmode;
5974 uint32_t rf_dec, rf_int;
5976 uint16_t link_speed = dev->data->dev_link.link_speed;
5978 if (queue_idx >= hw->mac.max_tx_queues)
5982 /* Calculate the rate factor values to set */
5983 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5984 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5985 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5987 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5988 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5989 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5990 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5995 rxmode = &dev->data->dev_conf.rxmode;
5997 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5998 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6001 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6002 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6003 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6004 IXGBE_MMW_SIZE_JUMBO_FRAME);
6006 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6007 IXGBE_MMW_SIZE_DEFAULT);
6009 /* Set RTTBCNRC of queue X */
6010 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6011 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6012 IXGBE_WRITE_FLUSH(hw);
6018 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
6019 __attribute__((unused)) uint32_t index,
6020 __attribute__((unused)) uint32_t pool)
6022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6026 * On a 82599 VF, adding again the same MAC addr is not an idempotent
6027 * operation. Trap this case to avoid exhausting the [very limited]
6028 * set of PF resources used to store VF MAC addresses.
6030 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6032 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6034 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6035 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6036 mac_addr->addr_bytes[0],
6037 mac_addr->addr_bytes[1],
6038 mac_addr->addr_bytes[2],
6039 mac_addr->addr_bytes[3],
6040 mac_addr->addr_bytes[4],
6041 mac_addr->addr_bytes[5],
6047 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6049 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6050 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
6051 struct ether_addr *mac_addr;
6056 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6057 * not support the deletion of a given MAC address.
6058 * Instead, it imposes to delete all MAC addresses, then to add again
6059 * all MAC addresses with the exception of the one to be deleted.
6061 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6064 * Add again all MAC addresses, with the exception of the deleted one
6065 * and of the permanent MAC address.
6067 for (i = 0, mac_addr = dev->data->mac_addrs;
6068 i < hw->mac.num_rar_entries; i++, mac_addr++) {
6069 /* Skip the deleted MAC address */
6072 /* Skip NULL MAC addresses */
6073 if (is_zero_ether_addr(mac_addr))
6075 /* Skip the permanent MAC address */
6076 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
6078 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6081 "Adding again MAC address "
6082 "%02x:%02x:%02x:%02x:%02x:%02x failed "
6084 mac_addr->addr_bytes[0],
6085 mac_addr->addr_bytes[1],
6086 mac_addr->addr_bytes[2],
6087 mac_addr->addr_bytes[3],
6088 mac_addr->addr_bytes[4],
6089 mac_addr->addr_bytes[5],
6095 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6097 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6099 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6105 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6106 struct rte_eth_syn_filter *filter,
6109 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6110 struct ixgbe_filter_info *filter_info =
6111 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6115 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6118 syn_info = filter_info->syn_info;
6121 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6123 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6124 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6126 if (filter->hig_pri)
6127 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6129 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6131 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6132 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6134 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6137 filter_info->syn_info = synqf;
6138 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6139 IXGBE_WRITE_FLUSH(hw);
6144 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6145 struct rte_eth_syn_filter *filter)
6147 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6148 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6150 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6151 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6152 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6159 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6160 enum rte_filter_op filter_op,
6163 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6166 MAC_TYPE_FILTER_SUP(hw->mac.type);
6168 if (filter_op == RTE_ETH_FILTER_NOP)
6172 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6177 switch (filter_op) {
6178 case RTE_ETH_FILTER_ADD:
6179 ret = ixgbe_syn_filter_set(dev,
6180 (struct rte_eth_syn_filter *)arg,
6183 case RTE_ETH_FILTER_DELETE:
6184 ret = ixgbe_syn_filter_set(dev,
6185 (struct rte_eth_syn_filter *)arg,
6188 case RTE_ETH_FILTER_GET:
6189 ret = ixgbe_syn_filter_get(dev,
6190 (struct rte_eth_syn_filter *)arg);
6193 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6202 static inline enum ixgbe_5tuple_protocol
6203 convert_protocol_type(uint8_t protocol_value)
6205 if (protocol_value == IPPROTO_TCP)
6206 return IXGBE_FILTER_PROTOCOL_TCP;
6207 else if (protocol_value == IPPROTO_UDP)
6208 return IXGBE_FILTER_PROTOCOL_UDP;
6209 else if (protocol_value == IPPROTO_SCTP)
6210 return IXGBE_FILTER_PROTOCOL_SCTP;
6212 return IXGBE_FILTER_PROTOCOL_NONE;
6215 /* inject a 5-tuple filter to HW */
6217 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6218 struct ixgbe_5tuple_filter *filter)
6220 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6222 uint32_t ftqf, sdpqf;
6223 uint32_t l34timir = 0;
6224 uint8_t mask = 0xff;
6228 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6229 IXGBE_SDPQF_DSTPORT_SHIFT);
6230 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6232 ftqf = (uint32_t)(filter->filter_info.proto &
6233 IXGBE_FTQF_PROTOCOL_MASK);
6234 ftqf |= (uint32_t)((filter->filter_info.priority &
6235 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6236 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6237 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6238 if (filter->filter_info.dst_ip_mask == 0)
6239 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6240 if (filter->filter_info.src_port_mask == 0)
6241 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6242 if (filter->filter_info.dst_port_mask == 0)
6243 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6244 if (filter->filter_info.proto_mask == 0)
6245 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6246 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6247 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6248 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6250 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6251 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6252 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6253 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6255 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6256 l34timir |= (uint32_t)(filter->queue <<
6257 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6258 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6262 * add a 5tuple filter
6265 * dev: Pointer to struct rte_eth_dev.
6266 * index: the index the filter allocates.
6267 * filter: ponter to the filter that will be added.
6268 * rx_queue: the queue id the filter assigned to.
6271 * - On success, zero.
6272 * - On failure, a negative value.
6275 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6276 struct ixgbe_5tuple_filter *filter)
6278 struct ixgbe_filter_info *filter_info =
6279 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6283 * look for an unused 5tuple filter index,
6284 * and insert the filter to list.
6286 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6287 idx = i / (sizeof(uint32_t) * NBBY);
6288 shift = i % (sizeof(uint32_t) * NBBY);
6289 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6290 filter_info->fivetuple_mask[idx] |= 1 << shift;
6292 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6298 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6299 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6303 ixgbe_inject_5tuple_filter(dev, filter);
6309 * remove a 5tuple filter
6312 * dev: Pointer to struct rte_eth_dev.
6313 * filter: the pointer of the filter will be removed.
6316 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6317 struct ixgbe_5tuple_filter *filter)
6319 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6320 struct ixgbe_filter_info *filter_info =
6321 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6322 uint16_t index = filter->index;
6324 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6325 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6326 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6329 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6330 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6331 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6332 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6333 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6337 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6339 struct ixgbe_hw *hw;
6340 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6341 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6343 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6345 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6348 /* refuse mtu that requires the support of scattered packets when this
6349 * feature has not been enabled before.
6351 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6352 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6353 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6357 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6358 * request of the version 2.0 of the mailbox API.
6359 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6360 * of the mailbox API.
6361 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6362 * prior to 3.11.33 which contains the following change:
6363 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6365 ixgbevf_rlpml_set_vf(hw, max_frame);
6367 /* update max frame size */
6368 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6372 static inline struct ixgbe_5tuple_filter *
6373 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6374 struct ixgbe_5tuple_filter_info *key)
6376 struct ixgbe_5tuple_filter *it;
6378 TAILQ_FOREACH(it, filter_list, entries) {
6379 if (memcmp(key, &it->filter_info,
6380 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6387 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6389 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6390 struct ixgbe_5tuple_filter_info *filter_info)
6392 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6393 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6394 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6397 switch (filter->dst_ip_mask) {
6399 filter_info->dst_ip_mask = 0;
6400 filter_info->dst_ip = filter->dst_ip;
6403 filter_info->dst_ip_mask = 1;
6406 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6410 switch (filter->src_ip_mask) {
6412 filter_info->src_ip_mask = 0;
6413 filter_info->src_ip = filter->src_ip;
6416 filter_info->src_ip_mask = 1;
6419 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6423 switch (filter->dst_port_mask) {
6425 filter_info->dst_port_mask = 0;
6426 filter_info->dst_port = filter->dst_port;
6429 filter_info->dst_port_mask = 1;
6432 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6436 switch (filter->src_port_mask) {
6438 filter_info->src_port_mask = 0;
6439 filter_info->src_port = filter->src_port;
6442 filter_info->src_port_mask = 1;
6445 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6449 switch (filter->proto_mask) {
6451 filter_info->proto_mask = 0;
6452 filter_info->proto =
6453 convert_protocol_type(filter->proto);
6456 filter_info->proto_mask = 1;
6459 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6463 filter_info->priority = (uint8_t)filter->priority;
6468 * add or delete a ntuple filter
6471 * dev: Pointer to struct rte_eth_dev.
6472 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6473 * add: if true, add filter, if false, remove filter
6476 * - On success, zero.
6477 * - On failure, a negative value.
6480 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6481 struct rte_eth_ntuple_filter *ntuple_filter,
6484 struct ixgbe_filter_info *filter_info =
6485 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6486 struct ixgbe_5tuple_filter_info filter_5tuple;
6487 struct ixgbe_5tuple_filter *filter;
6490 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6491 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6495 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6496 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6500 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6502 if (filter != NULL && add) {
6503 PMD_DRV_LOG(ERR, "filter exists.");
6506 if (filter == NULL && !add) {
6507 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6512 filter = rte_zmalloc("ixgbe_5tuple_filter",
6513 sizeof(struct ixgbe_5tuple_filter), 0);
6516 rte_memcpy(&filter->filter_info,
6518 sizeof(struct ixgbe_5tuple_filter_info));
6519 filter->queue = ntuple_filter->queue;
6520 ret = ixgbe_add_5tuple_filter(dev, filter);
6526 ixgbe_remove_5tuple_filter(dev, filter);
6532 * get a ntuple filter
6535 * dev: Pointer to struct rte_eth_dev.
6536 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6539 * - On success, zero.
6540 * - On failure, a negative value.
6543 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6544 struct rte_eth_ntuple_filter *ntuple_filter)
6546 struct ixgbe_filter_info *filter_info =
6547 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6548 struct ixgbe_5tuple_filter_info filter_5tuple;
6549 struct ixgbe_5tuple_filter *filter;
6552 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6553 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6557 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6558 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6562 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6564 if (filter == NULL) {
6565 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6568 ntuple_filter->queue = filter->queue;
6573 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6574 * @dev: pointer to rte_eth_dev structure
6575 * @filter_op:operation will be taken.
6576 * @arg: a pointer to specific structure corresponding to the filter_op
6579 * - On success, zero.
6580 * - On failure, a negative value.
6583 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6584 enum rte_filter_op filter_op,
6587 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6590 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6592 if (filter_op == RTE_ETH_FILTER_NOP)
6596 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6601 switch (filter_op) {
6602 case RTE_ETH_FILTER_ADD:
6603 ret = ixgbe_add_del_ntuple_filter(dev,
6604 (struct rte_eth_ntuple_filter *)arg,
6607 case RTE_ETH_FILTER_DELETE:
6608 ret = ixgbe_add_del_ntuple_filter(dev,
6609 (struct rte_eth_ntuple_filter *)arg,
6612 case RTE_ETH_FILTER_GET:
6613 ret = ixgbe_get_ntuple_filter(dev,
6614 (struct rte_eth_ntuple_filter *)arg);
6617 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6625 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6626 struct rte_eth_ethertype_filter *filter,
6629 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6630 struct ixgbe_filter_info *filter_info =
6631 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6635 struct ixgbe_ethertype_filter ethertype_filter;
6637 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6640 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6641 filter->ether_type == ETHER_TYPE_IPv6) {
6642 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6643 " ethertype filter.", filter->ether_type);
6647 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6648 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6651 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6652 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6656 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6657 if (ret >= 0 && add) {
6658 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6659 filter->ether_type);
6662 if (ret < 0 && !add) {
6663 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6664 filter->ether_type);
6669 etqf = IXGBE_ETQF_FILTER_EN;
6670 etqf |= (uint32_t)filter->ether_type;
6671 etqs |= (uint32_t)((filter->queue <<
6672 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6673 IXGBE_ETQS_RX_QUEUE);
6674 etqs |= IXGBE_ETQS_QUEUE_EN;
6676 ethertype_filter.ethertype = filter->ether_type;
6677 ethertype_filter.etqf = etqf;
6678 ethertype_filter.etqs = etqs;
6679 ethertype_filter.conf = FALSE;
6680 ret = ixgbe_ethertype_filter_insert(filter_info,
6683 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6687 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6691 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6692 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6693 IXGBE_WRITE_FLUSH(hw);
6699 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6700 struct rte_eth_ethertype_filter *filter)
6702 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6703 struct ixgbe_filter_info *filter_info =
6704 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6705 uint32_t etqf, etqs;
6708 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6710 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6711 filter->ether_type);
6715 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6716 if (etqf & IXGBE_ETQF_FILTER_EN) {
6717 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6718 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6720 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6721 IXGBE_ETQS_RX_QUEUE_SHIFT;
6728 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6729 * @dev: pointer to rte_eth_dev structure
6730 * @filter_op:operation will be taken.
6731 * @arg: a pointer to specific structure corresponding to the filter_op
6734 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6735 enum rte_filter_op filter_op,
6738 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6741 MAC_TYPE_FILTER_SUP(hw->mac.type);
6743 if (filter_op == RTE_ETH_FILTER_NOP)
6747 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6752 switch (filter_op) {
6753 case RTE_ETH_FILTER_ADD:
6754 ret = ixgbe_add_del_ethertype_filter(dev,
6755 (struct rte_eth_ethertype_filter *)arg,
6758 case RTE_ETH_FILTER_DELETE:
6759 ret = ixgbe_add_del_ethertype_filter(dev,
6760 (struct rte_eth_ethertype_filter *)arg,
6763 case RTE_ETH_FILTER_GET:
6764 ret = ixgbe_get_ethertype_filter(dev,
6765 (struct rte_eth_ethertype_filter *)arg);
6768 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6776 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6777 enum rte_filter_type filter_type,
6778 enum rte_filter_op filter_op,
6783 switch (filter_type) {
6784 case RTE_ETH_FILTER_NTUPLE:
6785 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6787 case RTE_ETH_FILTER_ETHERTYPE:
6788 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6790 case RTE_ETH_FILTER_SYN:
6791 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6793 case RTE_ETH_FILTER_FDIR:
6794 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6796 case RTE_ETH_FILTER_L2_TUNNEL:
6797 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6799 case RTE_ETH_FILTER_GENERIC:
6800 if (filter_op != RTE_ETH_FILTER_GET)
6802 *(const void **)arg = &ixgbe_flow_ops;
6805 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6815 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6816 u8 **mc_addr_ptr, u32 *vmdq)
6821 mc_addr = *mc_addr_ptr;
6822 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6827 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6828 struct ether_addr *mc_addr_set,
6829 uint32_t nb_mc_addr)
6831 struct ixgbe_hw *hw;
6834 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6835 mc_addr_list = (u8 *)mc_addr_set;
6836 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6837 ixgbe_dev_addr_list_itr, TRUE);
6841 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6843 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6844 uint64_t systime_cycles;
6846 switch (hw->mac.type) {
6847 case ixgbe_mac_X550:
6848 case ixgbe_mac_X550EM_x:
6849 case ixgbe_mac_X550EM_a:
6850 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6851 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6852 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6856 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6857 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6861 return systime_cycles;
6865 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6867 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6868 uint64_t rx_tstamp_cycles;
6870 switch (hw->mac.type) {
6871 case ixgbe_mac_X550:
6872 case ixgbe_mac_X550EM_x:
6873 case ixgbe_mac_X550EM_a:
6874 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6875 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6876 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6880 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6881 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6882 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6886 return rx_tstamp_cycles;
6890 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6892 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893 uint64_t tx_tstamp_cycles;
6895 switch (hw->mac.type) {
6896 case ixgbe_mac_X550:
6897 case ixgbe_mac_X550EM_x:
6898 case ixgbe_mac_X550EM_a:
6899 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6900 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6901 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6905 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6906 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6907 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6911 return tx_tstamp_cycles;
6915 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6917 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6918 struct ixgbe_adapter *adapter =
6919 (struct ixgbe_adapter *)dev->data->dev_private;
6920 struct rte_eth_link link;
6921 uint32_t incval = 0;
6924 /* Get current link speed. */
6925 ixgbe_dev_link_update(dev, 1);
6926 rte_eth_linkstatus_get(dev, &link);
6928 switch (link.link_speed) {
6929 case ETH_SPEED_NUM_100M:
6930 incval = IXGBE_INCVAL_100;
6931 shift = IXGBE_INCVAL_SHIFT_100;
6933 case ETH_SPEED_NUM_1G:
6934 incval = IXGBE_INCVAL_1GB;
6935 shift = IXGBE_INCVAL_SHIFT_1GB;
6937 case ETH_SPEED_NUM_10G:
6939 incval = IXGBE_INCVAL_10GB;
6940 shift = IXGBE_INCVAL_SHIFT_10GB;
6944 switch (hw->mac.type) {
6945 case ixgbe_mac_X550:
6946 case ixgbe_mac_X550EM_x:
6947 case ixgbe_mac_X550EM_a:
6948 /* Independent of link speed. */
6950 /* Cycles read will be interpreted as ns. */
6953 case ixgbe_mac_X540:
6954 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6956 case ixgbe_mac_82599EB:
6957 incval >>= IXGBE_INCVAL_SHIFT_82599;
6958 shift -= IXGBE_INCVAL_SHIFT_82599;
6959 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6960 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6963 /* Not supported. */
6967 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6968 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6969 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6971 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6972 adapter->systime_tc.cc_shift = shift;
6973 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6975 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6976 adapter->rx_tstamp_tc.cc_shift = shift;
6977 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6979 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6980 adapter->tx_tstamp_tc.cc_shift = shift;
6981 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6985 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6987 struct ixgbe_adapter *adapter =
6988 (struct ixgbe_adapter *)dev->data->dev_private;
6990 adapter->systime_tc.nsec += delta;
6991 adapter->rx_tstamp_tc.nsec += delta;
6992 adapter->tx_tstamp_tc.nsec += delta;
6998 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7001 struct ixgbe_adapter *adapter =
7002 (struct ixgbe_adapter *)dev->data->dev_private;
7004 ns = rte_timespec_to_ns(ts);
7005 /* Set the timecounters to a new value. */
7006 adapter->systime_tc.nsec = ns;
7007 adapter->rx_tstamp_tc.nsec = ns;
7008 adapter->tx_tstamp_tc.nsec = ns;
7014 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7016 uint64_t ns, systime_cycles;
7017 struct ixgbe_adapter *adapter =
7018 (struct ixgbe_adapter *)dev->data->dev_private;
7020 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7021 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7022 *ts = rte_ns_to_timespec(ns);
7028 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7030 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7034 /* Stop the timesync system time. */
7035 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7036 /* Reset the timesync system time value. */
7037 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7038 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7040 /* Enable system time for platforms where it isn't on by default. */
7041 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7042 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7043 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7045 ixgbe_start_timecounters(dev);
7047 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7048 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7050 IXGBE_ETQF_FILTER_EN |
7053 /* Enable timestamping of received PTP packets. */
7054 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7055 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7056 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7058 /* Enable timestamping of transmitted PTP packets. */
7059 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7060 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7061 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7063 IXGBE_WRITE_FLUSH(hw);
7069 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7071 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7074 /* Disable timestamping of transmitted PTP packets. */
7075 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7076 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7077 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7079 /* Disable timestamping of received PTP packets. */
7080 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7081 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7082 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7084 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7085 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7087 /* Stop incrementating the System Time registers. */
7088 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7094 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7095 struct timespec *timestamp,
7096 uint32_t flags __rte_unused)
7098 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7099 struct ixgbe_adapter *adapter =
7100 (struct ixgbe_adapter *)dev->data->dev_private;
7101 uint32_t tsync_rxctl;
7102 uint64_t rx_tstamp_cycles;
7105 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7106 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7109 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7110 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7111 *timestamp = rte_ns_to_timespec(ns);
7117 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7118 struct timespec *timestamp)
7120 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7121 struct ixgbe_adapter *adapter =
7122 (struct ixgbe_adapter *)dev->data->dev_private;
7123 uint32_t tsync_txctl;
7124 uint64_t tx_tstamp_cycles;
7127 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7128 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7131 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7132 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7133 *timestamp = rte_ns_to_timespec(ns);
7139 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7141 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7144 const struct reg_info *reg_group;
7145 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7146 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7148 while ((reg_group = reg_set[g_ind++]))
7149 count += ixgbe_regs_group_count(reg_group);
7155 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7159 const struct reg_info *reg_group;
7161 while ((reg_group = ixgbevf_regs[g_ind++]))
7162 count += ixgbe_regs_group_count(reg_group);
7168 ixgbe_get_regs(struct rte_eth_dev *dev,
7169 struct rte_dev_reg_info *regs)
7171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7172 uint32_t *data = regs->data;
7175 const struct reg_info *reg_group;
7176 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7177 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7180 regs->length = ixgbe_get_reg_length(dev);
7181 regs->width = sizeof(uint32_t);
7185 /* Support only full register dump */
7186 if ((regs->length == 0) ||
7187 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7188 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7190 while ((reg_group = reg_set[g_ind++]))
7191 count += ixgbe_read_regs_group(dev, &data[count],
7200 ixgbevf_get_regs(struct rte_eth_dev *dev,
7201 struct rte_dev_reg_info *regs)
7203 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7204 uint32_t *data = regs->data;
7207 const struct reg_info *reg_group;
7210 regs->length = ixgbevf_get_reg_length(dev);
7211 regs->width = sizeof(uint32_t);
7215 /* Support only full register dump */
7216 if ((regs->length == 0) ||
7217 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7218 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7220 while ((reg_group = ixgbevf_regs[g_ind++]))
7221 count += ixgbe_read_regs_group(dev, &data[count],
7230 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7232 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7234 /* Return unit is byte count */
7235 return hw->eeprom.word_size * 2;
7239 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7240 struct rte_dev_eeprom_info *in_eeprom)
7242 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7243 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7244 uint16_t *data = in_eeprom->data;
7247 first = in_eeprom->offset >> 1;
7248 length = in_eeprom->length >> 1;
7249 if ((first > hw->eeprom.word_size) ||
7250 ((first + length) > hw->eeprom.word_size))
7253 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7255 return eeprom->ops.read_buffer(hw, first, length, data);
7259 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7260 struct rte_dev_eeprom_info *in_eeprom)
7262 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7263 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7264 uint16_t *data = in_eeprom->data;
7267 first = in_eeprom->offset >> 1;
7268 length = in_eeprom->length >> 1;
7269 if ((first > hw->eeprom.word_size) ||
7270 ((first + length) > hw->eeprom.word_size))
7273 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7275 return eeprom->ops.write_buffer(hw, first, length, data);
7279 ixgbe_get_module_info(struct rte_eth_dev *dev,
7280 struct rte_eth_dev_module_info *modinfo)
7282 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7284 uint8_t sff8472_rev, addr_mode;
7285 bool page_swap = false;
7287 /* Check whether we support SFF-8472 or not */
7288 status = hw->phy.ops.read_i2c_eeprom(hw,
7289 IXGBE_SFF_SFF_8472_COMP,
7294 /* addressing mode is not supported */
7295 status = hw->phy.ops.read_i2c_eeprom(hw,
7296 IXGBE_SFF_SFF_8472_SWAP,
7301 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7303 "Address change required to access page 0xA2, "
7304 "but not supported. Please report the module "
7305 "type to the driver maintainers.");
7309 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7310 /* We have a SFP, but it does not support SFF-8472 */
7311 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7312 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7314 /* We have a SFP which supports a revision of SFF-8472. */
7315 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7316 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7323 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7324 struct rte_dev_eeprom_info *info)
7326 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7327 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7328 uint8_t databyte = 0xFF;
7329 uint8_t *data = info->data;
7332 if (info->length == 0)
7335 for (i = info->offset; i < info->offset + info->length; i++) {
7336 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7337 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7339 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7344 data[i - info->offset] = databyte;
7351 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7353 case ixgbe_mac_X550:
7354 case ixgbe_mac_X550EM_x:
7355 case ixgbe_mac_X550EM_a:
7356 return ETH_RSS_RETA_SIZE_512;
7357 case ixgbe_mac_X550_vf:
7358 case ixgbe_mac_X550EM_x_vf:
7359 case ixgbe_mac_X550EM_a_vf:
7360 return ETH_RSS_RETA_SIZE_64;
7362 return ETH_RSS_RETA_SIZE_128;
7367 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7369 case ixgbe_mac_X550:
7370 case ixgbe_mac_X550EM_x:
7371 case ixgbe_mac_X550EM_a:
7372 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7373 return IXGBE_RETA(reta_idx >> 2);
7375 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7376 case ixgbe_mac_X550_vf:
7377 case ixgbe_mac_X550EM_x_vf:
7378 case ixgbe_mac_X550EM_a_vf:
7379 return IXGBE_VFRETA(reta_idx >> 2);
7381 return IXGBE_RETA(reta_idx >> 2);
7386 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7388 case ixgbe_mac_X550_vf:
7389 case ixgbe_mac_X550EM_x_vf:
7390 case ixgbe_mac_X550EM_a_vf:
7391 return IXGBE_VFMRQC;
7398 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7400 case ixgbe_mac_X550_vf:
7401 case ixgbe_mac_X550EM_x_vf:
7402 case ixgbe_mac_X550EM_a_vf:
7403 return IXGBE_VFRSSRK(i);
7405 return IXGBE_RSSRK(i);
7410 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7412 case ixgbe_mac_82599_vf:
7413 case ixgbe_mac_X540_vf:
7421 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7422 struct rte_eth_dcb_info *dcb_info)
7424 struct ixgbe_dcb_config *dcb_config =
7425 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7426 struct ixgbe_dcb_tc_config *tc;
7427 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7431 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7432 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7434 dcb_info->nb_tcs = 1;
7436 tc_queue = &dcb_info->tc_queue;
7437 nb_tcs = dcb_info->nb_tcs;
7439 if (dcb_config->vt_mode) { /* vt is enabled*/
7440 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7441 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7442 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7443 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7444 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7445 for (j = 0; j < nb_tcs; j++) {
7446 tc_queue->tc_rxq[0][j].base = j;
7447 tc_queue->tc_rxq[0][j].nb_queue = 1;
7448 tc_queue->tc_txq[0][j].base = j;
7449 tc_queue->tc_txq[0][j].nb_queue = 1;
7452 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7453 for (j = 0; j < nb_tcs; j++) {
7454 tc_queue->tc_rxq[i][j].base =
7456 tc_queue->tc_rxq[i][j].nb_queue = 1;
7457 tc_queue->tc_txq[i][j].base =
7459 tc_queue->tc_txq[i][j].nb_queue = 1;
7463 } else { /* vt is disabled*/
7464 struct rte_eth_dcb_rx_conf *rx_conf =
7465 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7466 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7467 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7468 if (dcb_info->nb_tcs == ETH_4_TCS) {
7469 for (i = 0; i < dcb_info->nb_tcs; i++) {
7470 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7471 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7473 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7474 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7475 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7476 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7477 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7478 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7479 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7480 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7481 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7482 for (i = 0; i < dcb_info->nb_tcs; i++) {
7483 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7484 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7486 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7487 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7488 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7489 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7490 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7491 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7492 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7493 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7494 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7495 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7496 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7497 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7498 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7499 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7500 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7501 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7504 for (i = 0; i < dcb_info->nb_tcs; i++) {
7505 tc = &dcb_config->tc_config[i];
7506 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7511 /* Update e-tag ether type */
7513 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7514 uint16_t ether_type)
7516 uint32_t etag_etype;
7518 if (hw->mac.type != ixgbe_mac_X550 &&
7519 hw->mac.type != ixgbe_mac_X550EM_x &&
7520 hw->mac.type != ixgbe_mac_X550EM_a) {
7524 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7525 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7526 etag_etype |= ether_type;
7527 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7528 IXGBE_WRITE_FLUSH(hw);
7533 /* Config l2 tunnel ether type */
7535 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7536 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7539 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7540 struct ixgbe_l2_tn_info *l2_tn_info =
7541 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7543 if (l2_tunnel == NULL)
7546 switch (l2_tunnel->l2_tunnel_type) {
7547 case RTE_L2_TUNNEL_TYPE_E_TAG:
7548 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7549 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7552 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7560 /* Enable e-tag tunnel */
7562 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7564 uint32_t etag_etype;
7566 if (hw->mac.type != ixgbe_mac_X550 &&
7567 hw->mac.type != ixgbe_mac_X550EM_x &&
7568 hw->mac.type != ixgbe_mac_X550EM_a) {
7572 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7573 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7574 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7575 IXGBE_WRITE_FLUSH(hw);
7580 /* Enable l2 tunnel */
7582 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7583 enum rte_eth_tunnel_type l2_tunnel_type)
7586 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7587 struct ixgbe_l2_tn_info *l2_tn_info =
7588 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7590 switch (l2_tunnel_type) {
7591 case RTE_L2_TUNNEL_TYPE_E_TAG:
7592 l2_tn_info->e_tag_en = TRUE;
7593 ret = ixgbe_e_tag_enable(hw);
7596 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7604 /* Disable e-tag tunnel */
7606 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7608 uint32_t etag_etype;
7610 if (hw->mac.type != ixgbe_mac_X550 &&
7611 hw->mac.type != ixgbe_mac_X550EM_x &&
7612 hw->mac.type != ixgbe_mac_X550EM_a) {
7616 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7617 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7618 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7619 IXGBE_WRITE_FLUSH(hw);
7624 /* Disable l2 tunnel */
7626 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7627 enum rte_eth_tunnel_type l2_tunnel_type)
7630 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7631 struct ixgbe_l2_tn_info *l2_tn_info =
7632 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7634 switch (l2_tunnel_type) {
7635 case RTE_L2_TUNNEL_TYPE_E_TAG:
7636 l2_tn_info->e_tag_en = FALSE;
7637 ret = ixgbe_e_tag_disable(hw);
7640 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7649 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7650 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7653 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7654 uint32_t i, rar_entries;
7655 uint32_t rar_low, rar_high;
7657 if (hw->mac.type != ixgbe_mac_X550 &&
7658 hw->mac.type != ixgbe_mac_X550EM_x &&
7659 hw->mac.type != ixgbe_mac_X550EM_a) {
7663 rar_entries = ixgbe_get_num_rx_addrs(hw);
7665 for (i = 1; i < rar_entries; i++) {
7666 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7667 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7668 if ((rar_high & IXGBE_RAH_AV) &&
7669 (rar_high & IXGBE_RAH_ADTYPE) &&
7670 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7671 l2_tunnel->tunnel_id)) {
7672 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7673 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7675 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7685 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7686 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7689 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7690 uint32_t i, rar_entries;
7691 uint32_t rar_low, rar_high;
7693 if (hw->mac.type != ixgbe_mac_X550 &&
7694 hw->mac.type != ixgbe_mac_X550EM_x &&
7695 hw->mac.type != ixgbe_mac_X550EM_a) {
7699 /* One entry for one tunnel. Try to remove potential existing entry. */
7700 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7702 rar_entries = ixgbe_get_num_rx_addrs(hw);
7704 for (i = 1; i < rar_entries; i++) {
7705 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7706 if (rar_high & IXGBE_RAH_AV) {
7709 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7710 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7711 rar_low = l2_tunnel->tunnel_id;
7713 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7714 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7720 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7721 " Please remove a rule before adding a new one.");
7725 static inline struct ixgbe_l2_tn_filter *
7726 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7727 struct ixgbe_l2_tn_key *key)
7731 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7735 return l2_tn_info->hash_map[ret];
7739 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7740 struct ixgbe_l2_tn_filter *l2_tn_filter)
7744 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7745 &l2_tn_filter->key);
7749 "Failed to insert L2 tunnel filter"
7750 " to hash table %d!",
7755 l2_tn_info->hash_map[ret] = l2_tn_filter;
7757 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7763 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7764 struct ixgbe_l2_tn_key *key)
7767 struct ixgbe_l2_tn_filter *l2_tn_filter;
7769 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7773 "No such L2 tunnel filter to delete %d!",
7778 l2_tn_filter = l2_tn_info->hash_map[ret];
7779 l2_tn_info->hash_map[ret] = NULL;
7781 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7782 rte_free(l2_tn_filter);
7787 /* Add l2 tunnel filter */
7789 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7790 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7794 struct ixgbe_l2_tn_info *l2_tn_info =
7795 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7796 struct ixgbe_l2_tn_key key;
7797 struct ixgbe_l2_tn_filter *node;
7800 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7801 key.tn_id = l2_tunnel->tunnel_id;
7803 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7807 "The L2 tunnel filter already exists!");
7811 node = rte_zmalloc("ixgbe_l2_tn",
7812 sizeof(struct ixgbe_l2_tn_filter),
7817 rte_memcpy(&node->key,
7819 sizeof(struct ixgbe_l2_tn_key));
7820 node->pool = l2_tunnel->pool;
7821 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7828 switch (l2_tunnel->l2_tunnel_type) {
7829 case RTE_L2_TUNNEL_TYPE_E_TAG:
7830 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7833 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7838 if ((!restore) && (ret < 0))
7839 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7844 /* Delete l2 tunnel filter */
7846 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7847 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7850 struct ixgbe_l2_tn_info *l2_tn_info =
7851 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7852 struct ixgbe_l2_tn_key key;
7854 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7855 key.tn_id = l2_tunnel->tunnel_id;
7856 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7860 switch (l2_tunnel->l2_tunnel_type) {
7861 case RTE_L2_TUNNEL_TYPE_E_TAG:
7862 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7865 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7874 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7875 * @dev: pointer to rte_eth_dev structure
7876 * @filter_op:operation will be taken.
7877 * @arg: a pointer to specific structure corresponding to the filter_op
7880 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7881 enum rte_filter_op filter_op,
7886 if (filter_op == RTE_ETH_FILTER_NOP)
7890 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7895 switch (filter_op) {
7896 case RTE_ETH_FILTER_ADD:
7897 ret = ixgbe_dev_l2_tunnel_filter_add
7899 (struct rte_eth_l2_tunnel_conf *)arg,
7902 case RTE_ETH_FILTER_DELETE:
7903 ret = ixgbe_dev_l2_tunnel_filter_del
7905 (struct rte_eth_l2_tunnel_conf *)arg);
7908 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7916 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7920 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7922 if (hw->mac.type != ixgbe_mac_X550 &&
7923 hw->mac.type != ixgbe_mac_X550EM_x &&
7924 hw->mac.type != ixgbe_mac_X550EM_a) {
7928 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7929 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7931 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7932 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7937 /* Enable l2 tunnel forwarding */
7939 ixgbe_dev_l2_tunnel_forwarding_enable
7940 (struct rte_eth_dev *dev,
7941 enum rte_eth_tunnel_type l2_tunnel_type)
7943 struct ixgbe_l2_tn_info *l2_tn_info =
7944 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7947 switch (l2_tunnel_type) {
7948 case RTE_L2_TUNNEL_TYPE_E_TAG:
7949 l2_tn_info->e_tag_fwd_en = TRUE;
7950 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7953 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7961 /* Disable l2 tunnel forwarding */
7963 ixgbe_dev_l2_tunnel_forwarding_disable
7964 (struct rte_eth_dev *dev,
7965 enum rte_eth_tunnel_type l2_tunnel_type)
7967 struct ixgbe_l2_tn_info *l2_tn_info =
7968 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7971 switch (l2_tunnel_type) {
7972 case RTE_L2_TUNNEL_TYPE_E_TAG:
7973 l2_tn_info->e_tag_fwd_en = FALSE;
7974 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7977 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7986 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7987 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7990 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7992 uint32_t vmtir, vmvir;
7993 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7995 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7997 "VF id %u should be less than %u",
8003 if (hw->mac.type != ixgbe_mac_X550 &&
8004 hw->mac.type != ixgbe_mac_X550EM_x &&
8005 hw->mac.type != ixgbe_mac_X550EM_a) {
8010 vmtir = l2_tunnel->tunnel_id;
8014 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8016 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8017 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8019 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8020 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8025 /* Enable l2 tunnel tag insertion */
8027 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8028 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8032 switch (l2_tunnel->l2_tunnel_type) {
8033 case RTE_L2_TUNNEL_TYPE_E_TAG:
8034 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8037 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8045 /* Disable l2 tunnel tag insertion */
8047 ixgbe_dev_l2_tunnel_insertion_disable
8048 (struct rte_eth_dev *dev,
8049 struct rte_eth_l2_tunnel_conf *l2_tunnel)
8053 switch (l2_tunnel->l2_tunnel_type) {
8054 case RTE_L2_TUNNEL_TYPE_E_TAG:
8055 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8058 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8067 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8072 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8074 if (hw->mac.type != ixgbe_mac_X550 &&
8075 hw->mac.type != ixgbe_mac_X550EM_x &&
8076 hw->mac.type != ixgbe_mac_X550EM_a) {
8080 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8082 qde |= IXGBE_QDE_STRIP_TAG;
8084 qde &= ~IXGBE_QDE_STRIP_TAG;
8085 qde &= ~IXGBE_QDE_READ;
8086 qde |= IXGBE_QDE_WRITE;
8087 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8092 /* Enable l2 tunnel tag stripping */
8094 ixgbe_dev_l2_tunnel_stripping_enable
8095 (struct rte_eth_dev *dev,
8096 enum rte_eth_tunnel_type l2_tunnel_type)
8100 switch (l2_tunnel_type) {
8101 case RTE_L2_TUNNEL_TYPE_E_TAG:
8102 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8105 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8113 /* Disable l2 tunnel tag stripping */
8115 ixgbe_dev_l2_tunnel_stripping_disable
8116 (struct rte_eth_dev *dev,
8117 enum rte_eth_tunnel_type l2_tunnel_type)
8121 switch (l2_tunnel_type) {
8122 case RTE_L2_TUNNEL_TYPE_E_TAG:
8123 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8126 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8134 /* Enable/disable l2 tunnel offload functions */
8136 ixgbe_dev_l2_tunnel_offload_set
8137 (struct rte_eth_dev *dev,
8138 struct rte_eth_l2_tunnel_conf *l2_tunnel,
8144 if (l2_tunnel == NULL)
8148 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8150 ret = ixgbe_dev_l2_tunnel_enable(
8152 l2_tunnel->l2_tunnel_type);
8154 ret = ixgbe_dev_l2_tunnel_disable(
8156 l2_tunnel->l2_tunnel_type);
8159 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8161 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8165 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8170 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8172 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8174 l2_tunnel->l2_tunnel_type);
8176 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8178 l2_tunnel->l2_tunnel_type);
8181 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8183 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8185 l2_tunnel->l2_tunnel_type);
8187 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8189 l2_tunnel->l2_tunnel_type);
8196 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8199 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8200 IXGBE_WRITE_FLUSH(hw);
8205 /* There's only one register for VxLAN UDP port.
8206 * So, we cannot add several ports. Will update it.
8209 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8213 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8217 return ixgbe_update_vxlan_port(hw, port);
8220 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8221 * UDP port, it must have a value.
8222 * So, will reset it to the original value 0.
8225 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8230 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8232 if (cur_port != port) {
8233 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8237 return ixgbe_update_vxlan_port(hw, 0);
8240 /* Add UDP tunneling port */
8242 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8243 struct rte_eth_udp_tunnel *udp_tunnel)
8246 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8248 if (hw->mac.type != ixgbe_mac_X550 &&
8249 hw->mac.type != ixgbe_mac_X550EM_x &&
8250 hw->mac.type != ixgbe_mac_X550EM_a) {
8254 if (udp_tunnel == NULL)
8257 switch (udp_tunnel->prot_type) {
8258 case RTE_TUNNEL_TYPE_VXLAN:
8259 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8262 case RTE_TUNNEL_TYPE_GENEVE:
8263 case RTE_TUNNEL_TYPE_TEREDO:
8264 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8269 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8277 /* Remove UDP tunneling port */
8279 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8280 struct rte_eth_udp_tunnel *udp_tunnel)
8283 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8285 if (hw->mac.type != ixgbe_mac_X550 &&
8286 hw->mac.type != ixgbe_mac_X550EM_x &&
8287 hw->mac.type != ixgbe_mac_X550EM_a) {
8291 if (udp_tunnel == NULL)
8294 switch (udp_tunnel->prot_type) {
8295 case RTE_TUNNEL_TYPE_VXLAN:
8296 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8298 case RTE_TUNNEL_TYPE_GENEVE:
8299 case RTE_TUNNEL_TYPE_TEREDO:
8300 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8304 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8313 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8315 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8317 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8321 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8323 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8325 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8328 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8330 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8333 /* peek the message first */
8334 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8336 /* PF reset VF event */
8337 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8338 /* dummy mbx read to ack pf */
8339 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8341 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8347 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8350 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8351 struct ixgbe_interrupt *intr =
8352 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8353 ixgbevf_intr_disable(dev);
8355 /* read-on-clear nic registers here */
8356 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8359 /* only one misc vector supported - mailbox */
8360 eicr &= IXGBE_VTEICR_MASK;
8361 if (eicr == IXGBE_MISC_VEC_ID)
8362 intr->flags |= IXGBE_FLAG_MAILBOX;
8368 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8370 struct ixgbe_interrupt *intr =
8371 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8373 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8374 ixgbevf_mbx_process(dev);
8375 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8378 ixgbevf_intr_enable(dev);
8384 ixgbevf_dev_interrupt_handler(void *param)
8386 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8388 ixgbevf_dev_interrupt_get_status(dev);
8389 ixgbevf_dev_interrupt_action(dev);
8393 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8394 * @hw: pointer to hardware structure
8396 * Stops the transmit data path and waits for the HW to internally empty
8397 * the Tx security block
8399 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8401 #define IXGBE_MAX_SECTX_POLL 40
8406 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8407 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8408 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8409 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8410 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8411 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8413 /* Use interrupt-safe sleep just in case */
8417 /* For informational purposes only */
8418 if (i >= IXGBE_MAX_SECTX_POLL)
8419 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8420 "path fully disabled. Continuing with init.");
8422 return IXGBE_SUCCESS;
8426 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8427 * @hw: pointer to hardware structure
8429 * Enables the transmit data path.
8431 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8435 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8436 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8437 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8438 IXGBE_WRITE_FLUSH(hw);
8440 return IXGBE_SUCCESS;
8443 /* restore n-tuple filter */
8445 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8447 struct ixgbe_filter_info *filter_info =
8448 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8449 struct ixgbe_5tuple_filter *node;
8451 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8452 ixgbe_inject_5tuple_filter(dev, node);
8456 /* restore ethernet type filter */
8458 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8460 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8461 struct ixgbe_filter_info *filter_info =
8462 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8465 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8466 if (filter_info->ethertype_mask & (1 << i)) {
8467 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8468 filter_info->ethertype_filters[i].etqf);
8469 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8470 filter_info->ethertype_filters[i].etqs);
8471 IXGBE_WRITE_FLUSH(hw);
8476 /* restore SYN filter */
8478 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8480 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8481 struct ixgbe_filter_info *filter_info =
8482 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8485 synqf = filter_info->syn_info;
8487 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8488 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8489 IXGBE_WRITE_FLUSH(hw);
8493 /* restore L2 tunnel filter */
8495 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8497 struct ixgbe_l2_tn_info *l2_tn_info =
8498 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8499 struct ixgbe_l2_tn_filter *node;
8500 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8502 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8503 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8504 l2_tn_conf.tunnel_id = node->key.tn_id;
8505 l2_tn_conf.pool = node->pool;
8506 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8510 /* restore rss filter */
8512 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8514 struct ixgbe_filter_info *filter_info =
8515 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8517 if (filter_info->rss_info.conf.queue_num)
8518 ixgbe_config_rss_filter(dev,
8519 &filter_info->rss_info, TRUE);
8523 ixgbe_filter_restore(struct rte_eth_dev *dev)
8525 ixgbe_ntuple_filter_restore(dev);
8526 ixgbe_ethertype_filter_restore(dev);
8527 ixgbe_syn_filter_restore(dev);
8528 ixgbe_fdir_filter_restore(dev);
8529 ixgbe_l2_tn_filter_restore(dev);
8530 ixgbe_rss_filter_restore(dev);
8536 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8538 struct ixgbe_l2_tn_info *l2_tn_info =
8539 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8540 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8542 if (l2_tn_info->e_tag_en)
8543 (void)ixgbe_e_tag_enable(hw);
8545 if (l2_tn_info->e_tag_fwd_en)
8546 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8548 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8551 /* remove all the n-tuple filters */
8553 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8555 struct ixgbe_filter_info *filter_info =
8556 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8557 struct ixgbe_5tuple_filter *p_5tuple;
8559 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8560 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8563 /* remove all the ether type filters */
8565 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8567 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8568 struct ixgbe_filter_info *filter_info =
8569 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8572 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8573 if (filter_info->ethertype_mask & (1 << i) &&
8574 !filter_info->ethertype_filters[i].conf) {
8575 (void)ixgbe_ethertype_filter_remove(filter_info,
8577 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8578 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8579 IXGBE_WRITE_FLUSH(hw);
8584 /* remove the SYN filter */
8586 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8588 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8589 struct ixgbe_filter_info *filter_info =
8590 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8592 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8593 filter_info->syn_info = 0;
8595 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8596 IXGBE_WRITE_FLUSH(hw);
8600 /* remove all the L2 tunnel filters */
8602 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8604 struct ixgbe_l2_tn_info *l2_tn_info =
8605 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8606 struct ixgbe_l2_tn_filter *l2_tn_filter;
8607 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8610 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8611 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8612 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8613 l2_tn_conf.pool = l2_tn_filter->pool;
8614 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8622 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8623 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8624 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8625 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8626 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8627 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8629 RTE_INIT(ixgbe_init_log)
8631 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8632 if (ixgbe_logtype_init >= 0)
8633 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8634 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8635 if (ixgbe_logtype_driver >= 0)
8636 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);