drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 int ixgbe_logtype_init;
 423 int ixgbe_logtype_driver;
 424
 425 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
 426 int ixgbe_logtype_rx;
 427 #endif
 428 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
 429 int ixgbe_logtype_tx;
 430 #endif
 431 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
 432 int ixgbe_logtype_tx_free;
 433 #endif
 434
 435 /*
 436  * The set of PCI devices this driver supports
 437  */
 438 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 487 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 489 #endif
 490         { .vendor_id = 0, /* sentinel */ },
 491 };
 492
 493 /*
 494  * The set of PCI devices this driver supports (for 82599 VF)
 495  */
 496 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 507         { .vendor_id = 0, /* sentinel */ },
 508 };
 509
 510 static const struct rte_eth_desc_lim rx_desc_lim = {
 511         .nb_max = IXGBE_MAX_RING_DESC,
 512         .nb_min = IXGBE_MIN_RING_DESC,
 513         .nb_align = IXGBE_RXD_ALIGN,
 514 };
 515
 516 static const struct rte_eth_desc_lim tx_desc_lim = {
 517         .nb_max = IXGBE_MAX_RING_DESC,
 518         .nb_min = IXGBE_MIN_RING_DESC,
 519         .nb_align = IXGBE_TXD_ALIGN,
 520         .nb_seg_max = IXGBE_TX_MAX_SEG,
 521         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 522 };
 523
 524 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 525         .dev_configure        = ixgbe_dev_configure,
 526         .dev_start            = ixgbe_dev_start,
 527         .dev_stop             = ixgbe_dev_stop,
 528         .dev_set_link_up    = ixgbe_dev_set_link_up,
 529         .dev_set_link_down  = ixgbe_dev_set_link_down,
 530         .dev_close            = ixgbe_dev_close,
 531         .dev_reset            = ixgbe_dev_reset,
 532         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 533         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 534         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 535         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 536         .link_update          = ixgbe_dev_link_update,
 537         .stats_get            = ixgbe_dev_stats_get,
 538         .xstats_get           = ixgbe_dev_xstats_get,
 539         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 540         .stats_reset          = ixgbe_dev_stats_reset,
 541         .xstats_reset         = ixgbe_dev_xstats_reset,
 542         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 543         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 544         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 545         .fw_version_get       = ixgbe_fw_version_get,
 546         .dev_infos_get        = ixgbe_dev_info_get,
 547         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 548         .mtu_set              = ixgbe_dev_mtu_set,
 549         .vlan_filter_set      = ixgbe_vlan_filter_set,
 550         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 551         .vlan_offload_set     = ixgbe_vlan_offload_set,
 552         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 553         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 554         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 555         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 556         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 557         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 558         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 559         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 560         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 561         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 562         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 563         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 564         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 565         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 566         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 567         .dev_led_on           = ixgbe_dev_led_on,
 568         .dev_led_off          = ixgbe_dev_led_off,
 569         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 570         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 571         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 572         .mac_addr_add         = ixgbe_add_rar,
 573         .mac_addr_remove      = ixgbe_remove_rar,
 574         .mac_addr_set         = ixgbe_set_default_mac_addr,
 575         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 576         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 577         .mirror_rule_set      = ixgbe_mirror_rule_set,
 578         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 579         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 580         .reta_update          = ixgbe_dev_rss_reta_update,
 581         .reta_query           = ixgbe_dev_rss_reta_query,
 582         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 583         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 584         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 585         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 586         .rxq_info_get         = ixgbe_rxq_info_get,
 587         .txq_info_get         = ixgbe_txq_info_get,
 588         .timesync_enable      = ixgbe_timesync_enable,
 589         .timesync_disable     = ixgbe_timesync_disable,
 590         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 591         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 592         .get_reg              = ixgbe_get_regs,
 593         .get_eeprom_length    = ixgbe_get_eeprom_length,
 594         .get_eeprom           = ixgbe_get_eeprom,
 595         .set_eeprom           = ixgbe_set_eeprom,
 596         .get_module_info      = ixgbe_get_module_info,
 597         .get_module_eeprom    = ixgbe_get_module_eeprom,
 598         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 599         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 600         .timesync_read_time   = ixgbe_timesync_read_time,
 601         .timesync_write_time  = ixgbe_timesync_write_time,
 602         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 603         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 604         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 605         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 606         .tm_ops_get           = ixgbe_tm_ops_get,
 607         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 608 };
 609
 610 /*
 611  * dev_ops for virtual function, bare necessities for basic vf
 612  * operation have been implemented
 613  */
 614 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 615         .dev_configure        = ixgbevf_dev_configure,
 616         .dev_start            = ixgbevf_dev_start,
 617         .dev_stop             = ixgbevf_dev_stop,
 618         .link_update          = ixgbevf_dev_link_update,
 619         .stats_get            = ixgbevf_dev_stats_get,
 620         .xstats_get           = ixgbevf_dev_xstats_get,
 621         .stats_reset          = ixgbevf_dev_stats_reset,
 622         .xstats_reset         = ixgbevf_dev_stats_reset,
 623         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 624         .dev_close            = ixgbevf_dev_close,
 625         .dev_reset            = ixgbevf_dev_reset,
 626         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 627         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 628         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 629         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 630         .dev_infos_get        = ixgbevf_dev_info_get,
 631         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 632         .mtu_set              = ixgbevf_dev_set_mtu,
 633         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 634         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 635         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 636         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 637         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 638         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 639         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 640         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 641         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 642         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 643         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 644         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 645         .mac_addr_add         = ixgbevf_add_mac_addr,
 646         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 647         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 648         .rxq_info_get         = ixgbe_rxq_info_get,
 649         .txq_info_get         = ixgbe_txq_info_get,
 650         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 651         .get_reg              = ixgbevf_get_regs,
 652         .reta_update          = ixgbe_dev_rss_reta_update,
 653         .reta_query           = ixgbe_dev_rss_reta_query,
 654         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 655         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 656         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 657 };
 658
 659 /* store statistics names and its offset in stats structure */
 660 struct rte_ixgbe_xstats_name_off {
 661         char name[RTE_ETH_XSTATS_NAME_SIZE];
 662         unsigned offset;
 663 };
 664
 665 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 666         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 667         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 668         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 669         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 670         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 671         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 672         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 673         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 674         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 675         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 676         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 677         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 678         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 679         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 680         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 681                 prc1023)},
 682         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 683                 prc1522)},
 684         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 685         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 686         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 687         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 688         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 689         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 690         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 691         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 692         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 693         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 694         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 695         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 696         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 697         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 698         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 699         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 700         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 701                 ptc1023)},
 702         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 703                 ptc1522)},
 704         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 705         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 706         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 707         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 708
 709         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirustat_add)},
 711         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 712                 fdirustat_remove)},
 713         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 714                 fdirfstat_fadd)},
 715         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 716                 fdirfstat_fremove)},
 717         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 718                 fdirmatch)},
 719         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 720                 fdirmiss)},
 721
 722         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 723         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 724         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 725                 fclast)},
 726         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 727         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 728         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 729         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 730         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 731                 fcoe_noddp)},
 732         {"rx_fcoe_no_direct_data_placement_ext_buff",
 733                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 734
 735         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 736                 lxontxc)},
 737         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 738                 lxonrxc)},
 739         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 740                 lxofftxc)},
 741         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 742                 lxoffrxc)},
 743         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 744 };
 745
 746 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 747                            sizeof(rte_ixgbe_stats_strings[0]))
 748
 749 /* MACsec statistics */
 750 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 751         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 752                 out_pkts_untagged)},
 753         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 754                 out_pkts_encrypted)},
 755         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 756                 out_pkts_protected)},
 757         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 758                 out_octets_encrypted)},
 759         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 760                 out_octets_protected)},
 761         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 762                 in_pkts_untagged)},
 763         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 764                 in_pkts_badtag)},
 765         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_nosci)},
 767         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_unknownsci)},
 769         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 770                 in_octets_decrypted)},
 771         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 772                 in_octets_validated)},
 773         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_unchecked)},
 775         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_delayed)},
 777         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_late)},
 779         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_ok)},
 781         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 782                 in_pkts_invalid)},
 783         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 784                 in_pkts_notvalid)},
 785         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 786                 in_pkts_unusedsa)},
 787         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 788                 in_pkts_notusingsa)},
 789 };
 790
 791 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 792                            sizeof(rte_ixgbe_macsec_strings[0]))
 793
 794 /* Per-queue statistics */
 795 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 796         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 797         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 798         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 799         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 800 };
 801
 802 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 803                            sizeof(rte_ixgbe_rxq_strings[0]))
 804 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 805
 806 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 807         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 808         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 809         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 810                 pxon2offc)},
 811 };
 812
 813 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 814                            sizeof(rte_ixgbe_txq_strings[0]))
 815 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 816
 817 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 818         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 819 };
 820
 821 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 822                 sizeof(rte_ixgbevf_stats_strings[0]))
 823
 824 /*
 825  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 826  */
 827 static inline int
 828 ixgbe_is_sfp(struct ixgbe_hw *hw)
 829 {
 830         switch (hw->phy.type) {
 831         case ixgbe_phy_sfp_avago:
 832         case ixgbe_phy_sfp_ftl:
 833         case ixgbe_phy_sfp_intel:
 834         case ixgbe_phy_sfp_unknown:
 835         case ixgbe_phy_sfp_passive_tyco:
 836         case ixgbe_phy_sfp_passive_unknown:
 837                 return 1;
 838         default:
 839                 return 0;
 840         }
 841 }
 842
 843 static inline int32_t
 844 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 845 {
 846         uint32_t ctrl_ext;
 847         int32_t status;
 848
 849         status = ixgbe_reset_hw(hw);
 850
 851         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 852         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 853         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 854         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 855         IXGBE_WRITE_FLUSH(hw);
 856
 857         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 858                 status = IXGBE_SUCCESS;
 859         return status;
 860 }
 861
 862 static inline void
 863 ixgbe_enable_intr(struct rte_eth_dev *dev)
 864 {
 865         struct ixgbe_interrupt *intr =
 866                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 867         struct ixgbe_hw *hw =
 868                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 869
 870         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 871         IXGBE_WRITE_FLUSH(hw);
 872 }
 873
 874 /*
 875  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 876  */
 877 static void
 878 ixgbe_disable_intr(struct ixgbe_hw *hw)
 879 {
 880         PMD_INIT_FUNC_TRACE();
 881
 882         if (hw->mac.type == ixgbe_mac_82598EB) {
 883                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 884         } else {
 885                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 886                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 887                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 888         }
 889         IXGBE_WRITE_FLUSH(hw);
 890 }
 891
 892 /*
 893  * This function resets queue statistics mapping registers.
 894  * From Niantic datasheet, Initialization of Statistics section:
 895  * "...if software requires the queue counters, the RQSMR and TQSM registers
 896  * must be re-programmed following a device reset.
 897  */
 898 static void
 899 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 900 {
 901         uint32_t i;
 902
 903         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 904                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 905                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 906         }
 907 }
 908
 909
 910 static int
 911 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 912                                   uint16_t queue_id,
 913                                   uint8_t stat_idx,
 914                                   uint8_t is_rx)
 915 {
 916 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 917 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 918 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 919
 920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 921         struct ixgbe_stat_mapping_registers *stat_mappings =
 922                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 923         uint32_t qsmr_mask = 0;
 924         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 925         uint32_t q_map;
 926         uint8_t n, offset;
 927
 928         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 929                 (hw->mac.type != ixgbe_mac_X540) &&
 930                 (hw->mac.type != ixgbe_mac_X550) &&
 931                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 932                 (hw->mac.type != ixgbe_mac_X550EM_a))
 933                 return -ENOSYS;
 934
 935         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 936                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 937                      queue_id, stat_idx);
 938
 939         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 940         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 941                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 942                 return -EIO;
 943         }
 944         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 945
 946         /* Now clear any previous stat_idx set */
 947         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 948         if (!is_rx)
 949                 stat_mappings->tqsm[n] &= ~clearing_mask;
 950         else
 951                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 952
 953         q_map = (uint32_t)stat_idx;
 954         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 955         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 956         if (!is_rx)
 957                 stat_mappings->tqsm[n] |= qsmr_mask;
 958         else
 959                 stat_mappings->rqsmr[n] |= qsmr_mask;
 960
 961         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 962                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 963                      queue_id, stat_idx);
 964         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 965                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 966
 967         /* Now write the mapping in the appropriate register */
 968         if (is_rx) {
 969                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 970                              stat_mappings->rqsmr[n], n);
 971                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 972         } else {
 973                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 974                              stat_mappings->tqsm[n], n);
 975                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 976         }
 977         return 0;
 978 }
 979
 980 static void
 981 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 982 {
 983         struct ixgbe_stat_mapping_registers *stat_mappings =
 984                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 985         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 986         int i;
 987
 988         /* write whatever was in stat mapping table to the NIC */
 989         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 990                 /* rx */
 991                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 992
 993                 /* tx */
 994                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 995         }
 996 }
 997
 998 static void
 999 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1000 {
1001         uint8_t i;
1002         struct ixgbe_dcb_tc_config *tc;
1003         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1004
1005         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1006         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1007         for (i = 0; i < dcb_max_tc; i++) {
1008                 tc = &dcb_config->tc_config[i];
1009                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1010                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1011                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1012                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1013                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1014                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1015                 tc->pfc = ixgbe_dcb_pfc_disabled;
1016         }
1017
1018         /* Initialize default user to priority mapping, UPx->TC0 */
1019         tc = &dcb_config->tc_config[0];
1020         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1021         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1022         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1023                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1024                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1025         }
1026         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1027         dcb_config->pfc_mode_enable = false;
1028         dcb_config->vt_mode = true;
1029         dcb_config->round_robin_enable = false;
1030         /* support all DCB capabilities in 82599 */
1031         dcb_config->support.capabilities = 0xFF;
1032
1033         /*we only support 4 Tcs for X540, X550 */
1034         if (hw->mac.type == ixgbe_mac_X540 ||
1035                 hw->mac.type == ixgbe_mac_X550 ||
1036                 hw->mac.type == ixgbe_mac_X550EM_x ||
1037                 hw->mac.type == ixgbe_mac_X550EM_a) {
1038                 dcb_config->num_tcs.pg_tcs = 4;
1039                 dcb_config->num_tcs.pfc_tcs = 4;
1040         }
1041 }
1042
1043 /*
1044  * Ensure that all locks are released before first NVM or PHY access
1045  */
1046 static void
1047 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1048 {
1049         uint16_t mask;
1050
1051         /*
1052          * Phy lock should not fail in this early stage. If this is the case,
1053          * it is due to an improper exit of the application.
1054          * So force the release of the faulty lock. Release of common lock
1055          * is done automatically by swfw_sync function.
1056          */
1057         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1058         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1059                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1060         }
1061         ixgbe_release_swfw_semaphore(hw, mask);
1062
1063         /*
1064          * These ones are more tricky since they are common to all ports; but
1065          * swfw_sync retries last long enough (1s) to be almost sure that if
1066          * lock can not be taken it is due to an improper lock of the
1067          * semaphore.
1068          */
1069         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1070         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1071                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1072         }
1073         ixgbe_release_swfw_semaphore(hw, mask);
1074 }
1075
1076 /*
1077  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1078  * It returns 0 on success.
1079  */
1080 static int
1081 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1082 {
1083         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1084         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1085         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1086         struct ixgbe_hw *hw =
1087                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1088         struct ixgbe_vfta *shadow_vfta =
1089                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1090         struct ixgbe_hwstrip *hwstrip =
1091                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1092         struct ixgbe_dcb_config *dcb_config =
1093                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1094         struct ixgbe_filter_info *filter_info =
1095                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1096         struct ixgbe_bw_conf *bw_conf =
1097                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1098         uint32_t ctrl_ext;
1099         uint16_t csum;
1100         int diag, i;
1101
1102         PMD_INIT_FUNC_TRACE();
1103
1104         ixgbe_dev_macsec_setting_reset(eth_dev);
1105
1106         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1107         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1108         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1109         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1110
1111         /*
1112          * For secondary processes, we don't initialise any further as primary
1113          * has already done this work. Only check we don't need a different
1114          * RX and TX function.
1115          */
1116         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1117                 struct ixgbe_tx_queue *txq;
1118                 /* TX queue function in primary, set by last queue initialized
1119                  * Tx queue may not initialized by primary process
1120                  */
1121                 if (eth_dev->data->tx_queues) {
1122                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1123                         ixgbe_set_tx_function(eth_dev, txq);
1124                 } else {
1125                         /* Use default TX function if we get here */
1126                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1127                                      "Using default TX function.");
1128                 }
1129
1130                 ixgbe_set_rx_function(eth_dev);
1131
1132                 return 0;
1133         }
1134
1135         rte_atomic32_clear(&ad->link_thread_running);
1136         rte_eth_copy_pci_info(eth_dev, pci_dev);
1137
1138         /* Vendor and Device ID need to be set before init of shared code */
1139         hw->device_id = pci_dev->id.device_id;
1140         hw->vendor_id = pci_dev->id.vendor_id;
1141         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1142         hw->allow_unsupported_sfp = 1;
1143
1144         /* Initialize the shared code (base driver) */
1145 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1146         diag = ixgbe_bypass_init_shared_code(hw);
1147 #else
1148         diag = ixgbe_init_shared_code(hw);
1149 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1150
1151         if (diag != IXGBE_SUCCESS) {
1152                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1153                 return -EIO;
1154         }
1155
1156         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1157                 PMD_INIT_LOG(ERR, "\nERROR: "
1158                         "Firmware recovery mode detected. Limiting functionality.\n"
1159                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1160                         "User Guide for details on firmware recovery mode.");
1161                 return -EIO;
1162         }
1163
1164         /* pick up the PCI bus settings for reporting later */
1165         ixgbe_get_bus_info(hw);
1166
1167         /* Unlock any pending hardware semaphore */
1168         ixgbe_swfw_lock_reset(hw);
1169
1170 #ifdef RTE_LIBRTE_SECURITY
1171         /* Initialize security_ctx only for primary process*/
1172         if (ixgbe_ipsec_ctx_create(eth_dev))
1173                 return -ENOMEM;
1174 #endif
1175
1176         /* Initialize DCB configuration*/
1177         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1178         ixgbe_dcb_init(hw, dcb_config);
1179         /* Get Hardware Flow Control setting */
1180         hw->fc.requested_mode = ixgbe_fc_none;
1181         hw->fc.current_mode = ixgbe_fc_none;
1182         hw->fc.pause_time = IXGBE_FC_PAUSE;
1183         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1184                 hw->fc.low_water[i] = IXGBE_FC_LO;
1185                 hw->fc.high_water[i] = IXGBE_FC_HI;
1186         }
1187         hw->fc.send_xon = 1;
1188
1189         /* Make sure we have a good EEPROM before we read from it */
1190         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1191         if (diag != IXGBE_SUCCESS) {
1192                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1193                 return -EIO;
1194         }
1195
1196 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1197         diag = ixgbe_bypass_init_hw(hw);
1198 #else
1199         diag = ixgbe_init_hw(hw);
1200 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1201
1202         /*
1203          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1204          * is called too soon after the kernel driver unbinding/binding occurs.
1205          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1206          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1207          * also called. See ixgbe_identify_phy_82599(). The reason for the
1208          * failure is not known, and only occuts when virtualisation features
1209          * are disabled in the bios. A delay of 100ms  was found to be enough by
1210          * trial-and-error, and is doubled to be safe.
1211          */
1212         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1213                 rte_delay_ms(200);
1214                 diag = ixgbe_init_hw(hw);
1215         }
1216
1217         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1218                 diag = IXGBE_SUCCESS;
1219
1220         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1221                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1222                              "LOM.  Please be aware there may be issues associated "
1223                              "with your hardware.");
1224                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1225                              "please contact your Intel or hardware representative "
1226                              "who provided you with this hardware.");
1227         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1228                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1229         if (diag) {
1230                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1231                 return -EIO;
1232         }
1233
1234         /* Reset the hw statistics */
1235         ixgbe_dev_stats_reset(eth_dev);
1236
1237         /* disable interrupt */
1238         ixgbe_disable_intr(hw);
1239
1240         /* reset mappings for queue statistics hw counters*/
1241         ixgbe_reset_qstat_mappings(hw);
1242
1243         /* Allocate memory for storing MAC addresses */
1244         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1245                                                hw->mac.num_rar_entries, 0);
1246         if (eth_dev->data->mac_addrs == NULL) {
1247                 PMD_INIT_LOG(ERR,
1248                              "Failed to allocate %u bytes needed to store "
1249                              "MAC addresses",
1250                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1251                 return -ENOMEM;
1252         }
1253         /* Copy the permanent MAC address */
1254         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1255                         &eth_dev->data->mac_addrs[0]);
1256
1257         /* Allocate memory for storing hash filter MAC addresses */
1258         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1259                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1260         if (eth_dev->data->hash_mac_addrs == NULL) {
1261                 PMD_INIT_LOG(ERR,
1262                              "Failed to allocate %d bytes needed to store MAC addresses",
1263                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1264                 return -ENOMEM;
1265         }
1266
1267         /* Pass the information to the rte_eth_dev_close() that it should also
1268          * release the private port resources.
1269          */
1270         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1271
1272         /* initialize the vfta */
1273         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1274
1275         /* initialize the hw strip bitmap*/
1276         memset(hwstrip, 0, sizeof(*hwstrip));
1277
1278         /* initialize PF if max_vfs not zero */
1279         ixgbe_pf_host_init(eth_dev);
1280
1281         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1282         /* let hardware know driver is loaded */
1283         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1284         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1285         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1286         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1287         IXGBE_WRITE_FLUSH(hw);
1288
1289         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1290                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1291                              (int) hw->mac.type, (int) hw->phy.type,
1292                              (int) hw->phy.sfp_type);
1293         else
1294                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1295                              (int) hw->mac.type, (int) hw->phy.type);
1296
1297         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1298                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1299                      pci_dev->id.device_id);
1300
1301         rte_intr_callback_register(intr_handle,
1302                                    ixgbe_dev_interrupt_handler, eth_dev);
1303
1304         /* enable uio/vfio intr/eventfd mapping */
1305         rte_intr_enable(intr_handle);
1306
1307         /* enable support intr */
1308         ixgbe_enable_intr(eth_dev);
1309
1310         /* initialize filter info */
1311         memset(filter_info, 0,
1312                sizeof(struct ixgbe_filter_info));
1313
1314         /* initialize 5tuple filter list */
1315         TAILQ_INIT(&filter_info->fivetuple_list);
1316
1317         /* initialize flow director filter list & hash */
1318         ixgbe_fdir_filter_init(eth_dev);
1319
1320         /* initialize l2 tunnel filter list & hash */
1321         ixgbe_l2_tn_filter_init(eth_dev);
1322
1323         /* initialize flow filter lists */
1324         ixgbe_filterlist_init();
1325
1326         /* initialize bandwidth configuration info */
1327         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1328
1329         /* initialize Traffic Manager configuration */
1330         ixgbe_tm_conf_init(eth_dev);
1331
1332         return 0;
1333 }
1334
1335 static int
1336 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1337 {
1338         PMD_INIT_FUNC_TRACE();
1339
1340         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1341                 return 0;
1342
1343         ixgbe_dev_close(eth_dev);
1344
1345         return 0;
1346 }
1347
1348 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1349 {
1350         struct ixgbe_filter_info *filter_info =
1351                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1352         struct ixgbe_5tuple_filter *p_5tuple;
1353
1354         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1355                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1356                              p_5tuple,
1357                              entries);
1358                 rte_free(p_5tuple);
1359         }
1360         memset(filter_info->fivetuple_mask, 0,
1361                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1362
1363         return 0;
1364 }
1365
1366 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1367 {
1368         struct ixgbe_hw_fdir_info *fdir_info =
1369                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1370         struct ixgbe_fdir_filter *fdir_filter;
1371
1372                 if (fdir_info->hash_map)
1373                 rte_free(fdir_info->hash_map);
1374         if (fdir_info->hash_handle)
1375                 rte_hash_free(fdir_info->hash_handle);
1376
1377         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1378                 TAILQ_REMOVE(&fdir_info->fdir_list,
1379                              fdir_filter,
1380                              entries);
1381                 rte_free(fdir_filter);
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1388 {
1389         struct ixgbe_l2_tn_info *l2_tn_info =
1390                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1391         struct ixgbe_l2_tn_filter *l2_tn_filter;
1392
1393         if (l2_tn_info->hash_map)
1394                 rte_free(l2_tn_info->hash_map);
1395         if (l2_tn_info->hash_handle)
1396                 rte_hash_free(l2_tn_info->hash_handle);
1397
1398         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1399                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1400                              l2_tn_filter,
1401                              entries);
1402                 rte_free(l2_tn_filter);
1403         }
1404
1405         return 0;
1406 }
1407
1408 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1409 {
1410         struct ixgbe_hw_fdir_info *fdir_info =
1411                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1412         char fdir_hash_name[RTE_HASH_NAMESIZE];
1413         struct rte_hash_parameters fdir_hash_params = {
1414                 .name = fdir_hash_name,
1415                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1416                 .key_len = sizeof(union ixgbe_atr_input),
1417                 .hash_func = rte_hash_crc,
1418                 .hash_func_init_val = 0,
1419                 .socket_id = rte_socket_id(),
1420         };
1421
1422         TAILQ_INIT(&fdir_info->fdir_list);
1423         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1424                  "fdir_%s", eth_dev->device->name);
1425         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1426         if (!fdir_info->hash_handle) {
1427                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1428                 return -EINVAL;
1429         }
1430         fdir_info->hash_map = rte_zmalloc("ixgbe",
1431                                           sizeof(struct ixgbe_fdir_filter *) *
1432                                           IXGBE_MAX_FDIR_FILTER_NUM,
1433                                           0);
1434         if (!fdir_info->hash_map) {
1435                 PMD_INIT_LOG(ERR,
1436                              "Failed to allocate memory for fdir hash map!");
1437                 return -ENOMEM;
1438         }
1439         fdir_info->mask_added = FALSE;
1440
1441         return 0;
1442 }
1443
1444 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1445 {
1446         struct ixgbe_l2_tn_info *l2_tn_info =
1447                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1448         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1449         struct rte_hash_parameters l2_tn_hash_params = {
1450                 .name = l2_tn_hash_name,
1451                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1452                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1453                 .hash_func = rte_hash_crc,
1454                 .hash_func_init_val = 0,
1455                 .socket_id = rte_socket_id(),
1456         };
1457
1458         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1459         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1460                  "l2_tn_%s", eth_dev->device->name);
1461         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1462         if (!l2_tn_info->hash_handle) {
1463                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1464                 return -EINVAL;
1465         }
1466         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1467                                    sizeof(struct ixgbe_l2_tn_filter *) *
1468                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1469                                    0);
1470         if (!l2_tn_info->hash_map) {
1471                 PMD_INIT_LOG(ERR,
1472                         "Failed to allocate memory for L2 TN hash map!");
1473                 return -ENOMEM;
1474         }
1475         l2_tn_info->e_tag_en = FALSE;
1476         l2_tn_info->e_tag_fwd_en = FALSE;
1477         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1478
1479         return 0;
1480 }
1481 /*
1482  * Negotiate mailbox API version with the PF.
1483  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1484  * Then we try to negotiate starting with the most recent one.
1485  * If all negotiation attempts fail, then we will proceed with
1486  * the default one (ixgbe_mbox_api_10).
1487  */
1488 static void
1489 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1490 {
1491         int32_t i;
1492
1493         /* start with highest supported, proceed down */
1494         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1495                 ixgbe_mbox_api_13,
1496                 ixgbe_mbox_api_12,
1497                 ixgbe_mbox_api_11,
1498                 ixgbe_mbox_api_10,
1499         };
1500
1501         for (i = 0;
1502                         i != RTE_DIM(sup_ver) &&
1503                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1504                         i++)
1505                 ;
1506 }
1507
1508 static void
1509 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1510 {
1511         uint64_t random;
1512
1513         /* Set Organizationally Unique Identifier (OUI) prefix. */
1514         mac_addr->addr_bytes[0] = 0x00;
1515         mac_addr->addr_bytes[1] = 0x09;
1516         mac_addr->addr_bytes[2] = 0xC0;
1517         /* Force indication of locally assigned MAC address. */
1518         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1519         /* Generate the last 3 bytes of the MAC address with a random number. */
1520         random = rte_rand();
1521         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1522 }
1523
1524 static int
1525 devarg_handle_int(__rte_unused const char *key, const char *value,
1526                   void *extra_args)
1527 {
1528         uint16_t *n = extra_args;
1529
1530         if (value == NULL || extra_args == NULL)
1531                 return -EINVAL;
1532
1533         *n = (uint16_t)strtoul(value, NULL, 0);
1534         if (*n == USHRT_MAX && errno == ERANGE)
1535                 return -1;
1536
1537         return 0;
1538 }
1539
1540 static void
1541 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1542                       struct rte_devargs *devargs)
1543 {
1544         struct rte_kvargs *kvlist;
1545         uint16_t pflink_fullchk;
1546
1547         if (devargs == NULL)
1548                 return;
1549
1550         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1551         if (kvlist == NULL)
1552                 return;
1553
1554         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1555             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1556                                devarg_handle_int, &pflink_fullchk) == 0 &&
1557             pflink_fullchk == 1)
1558                 adapter->pflink_fullchk = 1;
1559
1560         rte_kvargs_free(kvlist);
1561 }
1562
1563 /*
1564  * Virtual Function device init
1565  */
1566 static int
1567 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1568 {
1569         int diag;
1570         uint32_t tc, tcs;
1571         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1572         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1574         struct ixgbe_hw *hw =
1575                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1576         struct ixgbe_vfta *shadow_vfta =
1577                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1578         struct ixgbe_hwstrip *hwstrip =
1579                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1580         struct rte_ether_addr *perm_addr =
1581                 (struct rte_ether_addr *)hw->mac.perm_addr;
1582
1583         PMD_INIT_FUNC_TRACE();
1584
1585         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1586         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1587         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1588
1589         /* for secondary processes, we don't initialise any further as primary
1590          * has already done this work. Only check we don't need a different
1591          * RX function
1592          */
1593         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1594                 struct ixgbe_tx_queue *txq;
1595                 /* TX queue function in primary, set by last queue initialized
1596                  * Tx queue may not initialized by primary process
1597                  */
1598                 if (eth_dev->data->tx_queues) {
1599                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1600                         ixgbe_set_tx_function(eth_dev, txq);
1601                 } else {
1602                         /* Use default TX function if we get here */
1603                         PMD_INIT_LOG(NOTICE,
1604                                      "No TX queues configured yet. Using default TX function.");
1605                 }
1606
1607                 ixgbe_set_rx_function(eth_dev);
1608
1609                 return 0;
1610         }
1611
1612         rte_atomic32_clear(&ad->link_thread_running);
1613         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1614                               pci_dev->device.devargs);
1615
1616         rte_eth_copy_pci_info(eth_dev, pci_dev);
1617
1618         hw->device_id = pci_dev->id.device_id;
1619         hw->vendor_id = pci_dev->id.vendor_id;
1620         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1621
1622         /* initialize the vfta */
1623         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1624
1625         /* initialize the hw strip bitmap*/
1626         memset(hwstrip, 0, sizeof(*hwstrip));
1627
1628         /* Initialize the shared code (base driver) */
1629         diag = ixgbe_init_shared_code(hw);
1630         if (diag != IXGBE_SUCCESS) {
1631                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1632                 return -EIO;
1633         }
1634
1635         /* init_mailbox_params */
1636         hw->mbx.ops.init_params(hw);
1637
1638         /* Reset the hw statistics */
1639         ixgbevf_dev_stats_reset(eth_dev);
1640
1641         /* Disable the interrupts for VF */
1642         ixgbevf_intr_disable(eth_dev);
1643
1644         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1645         diag = hw->mac.ops.reset_hw(hw);
1646
1647         /*
1648          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1649          * the underlying PF driver has not assigned a MAC address to the VF.
1650          * In this case, assign a random MAC address.
1651          */
1652         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1653                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1654                 /*
1655                  * This error code will be propagated to the app by
1656                  * rte_eth_dev_reset, so use a public error code rather than
1657                  * the internal-only IXGBE_ERR_RESET_FAILED
1658                  */
1659                 return -EAGAIN;
1660         }
1661
1662         /* negotiate mailbox API version to use with the PF. */
1663         ixgbevf_negotiate_api(hw);
1664
1665         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1666         ixgbevf_get_queues(hw, &tcs, &tc);
1667
1668         /* Allocate memory for storing MAC addresses */
1669         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1670                                                hw->mac.num_rar_entries, 0);
1671         if (eth_dev->data->mac_addrs == NULL) {
1672                 PMD_INIT_LOG(ERR,
1673                              "Failed to allocate %u bytes needed to store "
1674                              "MAC addresses",
1675                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1676                 return -ENOMEM;
1677         }
1678
1679         /* Pass the information to the rte_eth_dev_close() that it should also
1680          * release the private port resources.
1681          */
1682         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1683
1684         /* Generate a random MAC address, if none was assigned by PF. */
1685         if (rte_is_zero_ether_addr(perm_addr)) {
1686                 generate_random_mac_addr(perm_addr);
1687                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1688                 if (diag) {
1689                         rte_free(eth_dev->data->mac_addrs);
1690                         eth_dev->data->mac_addrs = NULL;
1691                         return diag;
1692                 }
1693                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1694                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1695                              "%02x:%02x:%02x:%02x:%02x:%02x",
1696                              perm_addr->addr_bytes[0],
1697                              perm_addr->addr_bytes[1],
1698                              perm_addr->addr_bytes[2],
1699                              perm_addr->addr_bytes[3],
1700                              perm_addr->addr_bytes[4],
1701                              perm_addr->addr_bytes[5]);
1702         }
1703
1704         /* Copy the permanent MAC address */
1705         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1706
1707         /* reset the hardware with the new settings */
1708         diag = hw->mac.ops.start_hw(hw);
1709         switch (diag) {
1710         case  0:
1711                 break;
1712
1713         default:
1714                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1715                 return -EIO;
1716         }
1717
1718         rte_intr_callback_register(intr_handle,
1719                                    ixgbevf_dev_interrupt_handler, eth_dev);
1720         rte_intr_enable(intr_handle);
1721         ixgbevf_intr_enable(eth_dev);
1722
1723         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1724                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1725                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1726
1727         return 0;
1728 }
1729
1730 /* Virtual Function device uninit */
1731
1732 static int
1733 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1734 {
1735         PMD_INIT_FUNC_TRACE();
1736
1737         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1738                 return 0;
1739
1740         ixgbevf_dev_close(eth_dev);
1741
1742         return 0;
1743 }
1744
1745 static int
1746 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1747                 struct rte_pci_device *pci_dev)
1748 {
1749         char name[RTE_ETH_NAME_MAX_LEN];
1750         struct rte_eth_dev *pf_ethdev;
1751         struct rte_eth_devargs eth_da;
1752         int i, retval;
1753
1754         if (pci_dev->device.devargs) {
1755                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1756                                 &eth_da);
1757                 if (retval)
1758                         return retval;
1759         } else
1760                 memset(&eth_da, 0, sizeof(eth_da));
1761
1762         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1763                 sizeof(struct ixgbe_adapter),
1764                 eth_dev_pci_specific_init, pci_dev,
1765                 eth_ixgbe_dev_init, NULL);
1766
1767         if (retval || eth_da.nb_representor_ports < 1)
1768                 return retval;
1769
1770         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1771         if (pf_ethdev == NULL)
1772                 return -ENODEV;
1773
1774         /* probe VF representor ports */
1775         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1776                 struct ixgbe_vf_info *vfinfo;
1777                 struct ixgbe_vf_representor representor;
1778
1779                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1780                         pf_ethdev->data->dev_private);
1781                 if (vfinfo == NULL) {
1782                         PMD_DRV_LOG(ERR,
1783                                 "no virtual functions supported by PF");
1784                         break;
1785                 }
1786
1787                 representor.vf_id = eth_da.representor_ports[i];
1788                 representor.switch_domain_id = vfinfo->switch_domain_id;
1789                 representor.pf_ethdev = pf_ethdev;
1790
1791                 /* representor port net_bdf_port */
1792                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1793                         pci_dev->device.name,
1794                         eth_da.representor_ports[i]);
1795
1796                 retval = rte_eth_dev_create(&pci_dev->device, name,
1797                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1798                         ixgbe_vf_representor_init, &representor);
1799
1800                 if (retval)
1801                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1802                                 "representor %s.", name);
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1809 {
1810         struct rte_eth_dev *ethdev;
1811
1812         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1813         if (!ethdev)
1814                 return 0;
1815
1816         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1817                 return rte_eth_dev_pci_generic_remove(pci_dev,
1818                                         ixgbe_vf_representor_uninit);
1819         else
1820                 return rte_eth_dev_pci_generic_remove(pci_dev,
1821                                                 eth_ixgbe_dev_uninit);
1822 }
1823
1824 static struct rte_pci_driver rte_ixgbe_pmd = {
1825         .id_table = pci_id_ixgbe_map,
1826         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1827         .probe = eth_ixgbe_pci_probe,
1828         .remove = eth_ixgbe_pci_remove,
1829 };
1830
1831 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1832         struct rte_pci_device *pci_dev)
1833 {
1834         return rte_eth_dev_pci_generic_probe(pci_dev,
1835                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1836 }
1837
1838 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1839 {
1840         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1841 }
1842
1843 /*
1844  * virtual function driver struct
1845  */
1846 static struct rte_pci_driver rte_ixgbevf_pmd = {
1847         .id_table = pci_id_ixgbevf_map,
1848         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1849         .probe = eth_ixgbevf_pci_probe,
1850         .remove = eth_ixgbevf_pci_remove,
1851 };
1852
1853 static int
1854 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1855 {
1856         struct ixgbe_hw *hw =
1857                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858         struct ixgbe_vfta *shadow_vfta =
1859                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1860         uint32_t vfta;
1861         uint32_t vid_idx;
1862         uint32_t vid_bit;
1863
1864         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1865         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1866         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1867         if (on)
1868                 vfta |= vid_bit;
1869         else
1870                 vfta &= ~vid_bit;
1871         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1872
1873         /* update local VFTA copy */
1874         shadow_vfta->vfta[vid_idx] = vfta;
1875
1876         return 0;
1877 }
1878
1879 static void
1880 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1881 {
1882         if (on)
1883                 ixgbe_vlan_hw_strip_enable(dev, queue);
1884         else
1885                 ixgbe_vlan_hw_strip_disable(dev, queue);
1886 }
1887
1888 static int
1889 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1890                     enum rte_vlan_type vlan_type,
1891                     uint16_t tpid)
1892 {
1893         struct ixgbe_hw *hw =
1894                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895         int ret = 0;
1896         uint32_t reg;
1897         uint32_t qinq;
1898
1899         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1900         qinq &= IXGBE_DMATXCTL_GDV;
1901
1902         switch (vlan_type) {
1903         case ETH_VLAN_TYPE_INNER:
1904                 if (qinq) {
1905                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1906                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1907                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1908                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1909                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1910                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1911                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1912                 } else {
1913                         ret = -ENOTSUP;
1914                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1915                                     " by single VLAN");
1916                 }
1917                 break;
1918         case ETH_VLAN_TYPE_OUTER:
1919                 if (qinq) {
1920                         /* Only the high 16-bits is valid */
1921                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1922                                         IXGBE_EXVET_VET_EXT_SHIFT);
1923                 } else {
1924                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1925                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1926                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1927                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1928                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1929                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1930                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1931                 }
1932
1933                 break;
1934         default:
1935                 ret = -EINVAL;
1936                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1937                 break;
1938         }
1939
1940         return ret;
1941 }
1942
1943 void
1944 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1945 {
1946         struct ixgbe_hw *hw =
1947                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         uint32_t vlnctrl;
1949
1950         PMD_INIT_FUNC_TRACE();
1951
1952         /* Filter Table Disable */
1953         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1954         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1955
1956         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1957 }
1958
1959 void
1960 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1961 {
1962         struct ixgbe_hw *hw =
1963                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964         struct ixgbe_vfta *shadow_vfta =
1965                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1966         uint32_t vlnctrl;
1967         uint16_t i;
1968
1969         PMD_INIT_FUNC_TRACE();
1970
1971         /* Filter Table Enable */
1972         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1973         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1974         vlnctrl |= IXGBE_VLNCTRL_VFE;
1975
1976         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1977
1978         /* write whatever is in local vfta copy */
1979         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1980                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1981 }
1982
1983 static void
1984 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1985 {
1986         struct ixgbe_hwstrip *hwstrip =
1987                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1988         struct ixgbe_rx_queue *rxq;
1989
1990         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1991                 return;
1992
1993         if (on)
1994                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1995         else
1996                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1997
1998         if (queue >= dev->data->nb_rx_queues)
1999                 return;
2000
2001         rxq = dev->data->rx_queues[queue];
2002
2003         if (on) {
2004                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2005                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2006         } else {
2007                 rxq->vlan_flags = PKT_RX_VLAN;
2008                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2009         }
2010 }
2011
2012 static void
2013 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2014 {
2015         struct ixgbe_hw *hw =
2016                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         uint32_t ctrl;
2018
2019         PMD_INIT_FUNC_TRACE();
2020
2021         if (hw->mac.type == ixgbe_mac_82598EB) {
2022                 /* No queue level support */
2023                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2024                 return;
2025         }
2026
2027         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2028         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2029         ctrl &= ~IXGBE_RXDCTL_VME;
2030         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2031
2032         /* record those setting for HW strip per queue */
2033         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2034 }
2035
2036 static void
2037 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2038 {
2039         struct ixgbe_hw *hw =
2040                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2041         uint32_t ctrl;
2042
2043         PMD_INIT_FUNC_TRACE();
2044
2045         if (hw->mac.type == ixgbe_mac_82598EB) {
2046                 /* No queue level supported */
2047                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2048                 return;
2049         }
2050
2051         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2052         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2053         ctrl |= IXGBE_RXDCTL_VME;
2054         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2055
2056         /* record those setting for HW strip per queue */
2057         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2058 }
2059
2060 static void
2061 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2062 {
2063         struct ixgbe_hw *hw =
2064                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2065         uint32_t ctrl;
2066
2067         PMD_INIT_FUNC_TRACE();
2068
2069         /* DMATXCTRL: Geric Double VLAN Disable */
2070         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2071         ctrl &= ~IXGBE_DMATXCTL_GDV;
2072         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2073
2074         /* CTRL_EXT: Global Double VLAN Disable */
2075         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2076         ctrl &= ~IXGBE_EXTENDED_VLAN;
2077         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2078
2079 }
2080
2081 static void
2082 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2083 {
2084         struct ixgbe_hw *hw =
2085                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2086         uint32_t ctrl;
2087
2088         PMD_INIT_FUNC_TRACE();
2089
2090         /* DMATXCTRL: Geric Double VLAN Enable */
2091         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2092         ctrl |= IXGBE_DMATXCTL_GDV;
2093         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2094
2095         /* CTRL_EXT: Global Double VLAN Enable */
2096         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2097         ctrl |= IXGBE_EXTENDED_VLAN;
2098         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2099
2100         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2101         if (hw->mac.type == ixgbe_mac_X550 ||
2102             hw->mac.type == ixgbe_mac_X550EM_x ||
2103             hw->mac.type == ixgbe_mac_X550EM_a) {
2104                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2105                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2106                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2107         }
2108
2109         /*
2110          * VET EXT field in the EXVET register = 0x8100 by default
2111          * So no need to change. Same to VT field of DMATXCTL register
2112          */
2113 }
2114
2115 void
2116 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2117 {
2118         struct ixgbe_hw *hw =
2119                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2120         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2121         uint32_t ctrl;
2122         uint16_t i;
2123         struct ixgbe_rx_queue *rxq;
2124         bool on;
2125
2126         PMD_INIT_FUNC_TRACE();
2127
2128         if (hw->mac.type == ixgbe_mac_82598EB) {
2129                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2130                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2131                         ctrl |= IXGBE_VLNCTRL_VME;
2132                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2133                 } else {
2134                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2135                         ctrl &= ~IXGBE_VLNCTRL_VME;
2136                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2137                 }
2138         } else {
2139                 /*
2140                  * Other 10G NIC, the VLAN strip can be setup
2141                  * per queue in RXDCTL
2142                  */
2143                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2144                         rxq = dev->data->rx_queues[i];
2145                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2146                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2147                                 ctrl |= IXGBE_RXDCTL_VME;
2148                                 on = TRUE;
2149                         } else {
2150                                 ctrl &= ~IXGBE_RXDCTL_VME;
2151                                 on = FALSE;
2152                         }
2153                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2154
2155                         /* record those setting for HW strip per queue */
2156                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2157                 }
2158         }
2159 }
2160
2161 static void
2162 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2163 {
2164         uint16_t i;
2165         struct rte_eth_rxmode *rxmode;
2166         struct ixgbe_rx_queue *rxq;
2167
2168         if (mask & ETH_VLAN_STRIP_MASK) {
2169                 rxmode = &dev->data->dev_conf.rxmode;
2170                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2171                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2172                                 rxq = dev->data->rx_queues[i];
2173                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2174                         }
2175                 else
2176                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2177                                 rxq = dev->data->rx_queues[i];
2178                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2179                         }
2180         }
2181 }
2182
2183 static int
2184 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2185 {
2186         struct rte_eth_rxmode *rxmode;
2187         rxmode = &dev->data->dev_conf.rxmode;
2188
2189         if (mask & ETH_VLAN_STRIP_MASK) {
2190                 ixgbe_vlan_hw_strip_config(dev);
2191         }
2192
2193         if (mask & ETH_VLAN_FILTER_MASK) {
2194                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2195                         ixgbe_vlan_hw_filter_enable(dev);
2196                 else
2197                         ixgbe_vlan_hw_filter_disable(dev);
2198         }
2199
2200         if (mask & ETH_VLAN_EXTEND_MASK) {
2201                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2202                         ixgbe_vlan_hw_extend_enable(dev);
2203                 else
2204                         ixgbe_vlan_hw_extend_disable(dev);
2205         }
2206
2207         return 0;
2208 }
2209
2210 static int
2211 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2212 {
2213         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2214
2215         ixgbe_vlan_offload_config(dev, mask);
2216
2217         return 0;
2218 }
2219
2220 static void
2221 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2222 {
2223         struct ixgbe_hw *hw =
2224                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2225         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2226         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2227
2228         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2229         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2230 }
2231
2232 static int
2233 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2234 {
2235         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2236
2237         switch (nb_rx_q) {
2238         case 1:
2239         case 2:
2240                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2241                 break;
2242         case 4:
2243                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2244                 break;
2245         default:
2246                 return -EINVAL;
2247         }
2248
2249         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2250                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2251         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2252                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2253         return 0;
2254 }
2255
2256 static int
2257 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2258 {
2259         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2260         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2262         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2263
2264         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2265                 /* check multi-queue mode */
2266                 switch (dev_conf->rxmode.mq_mode) {
2267                 case ETH_MQ_RX_VMDQ_DCB:
2268                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2269                         break;
2270                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2271                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2272                         PMD_INIT_LOG(ERR, "SRIOV active,"
2273                                         " unsupported mq_mode rx %d.",
2274                                         dev_conf->rxmode.mq_mode);
2275                         return -EINVAL;
2276                 case ETH_MQ_RX_RSS:
2277                 case ETH_MQ_RX_VMDQ_RSS:
2278                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2279                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2280                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2281                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2282                                                 " invalid queue number"
2283                                                 " for VMDQ RSS, allowed"
2284                                                 " value are 1, 2 or 4.");
2285                                         return -EINVAL;
2286                                 }
2287                         break;
2288                 case ETH_MQ_RX_VMDQ_ONLY:
2289                 case ETH_MQ_RX_NONE:
2290                         /* if nothing mq mode configure, use default scheme */
2291                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2292                         break;
2293                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2294                         /* SRIOV only works in VMDq enable mode */
2295                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2296                                         " wrong mq_mode rx %d.",
2297                                         dev_conf->rxmode.mq_mode);
2298                         return -EINVAL;
2299                 }
2300
2301                 switch (dev_conf->txmode.mq_mode) {
2302                 case ETH_MQ_TX_VMDQ_DCB:
2303                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2304                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2305                         break;
2306                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2307                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2308                         break;
2309                 }
2310
2311                 /* check valid queue number */
2312                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2313                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2314                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2315                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2316                                         " must be less than or equal to %d.",
2317                                         nb_rx_q, nb_tx_q,
2318                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2319                         return -EINVAL;
2320                 }
2321         } else {
2322                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2323                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2324                                           " not supported.");
2325                         return -EINVAL;
2326                 }
2327                 /* check configuration for vmdb+dcb mode */
2328                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2329                         const struct rte_eth_vmdq_dcb_conf *conf;
2330
2331                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2332                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2333                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2334                                 return -EINVAL;
2335                         }
2336                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2337                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2338                                conf->nb_queue_pools == ETH_32_POOLS)) {
2339                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2340                                                 " nb_queue_pools must be %d or %d.",
2341                                                 ETH_16_POOLS, ETH_32_POOLS);
2342                                 return -EINVAL;
2343                         }
2344                 }
2345                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2346                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2347
2348                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2349                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2350                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2351                                 return -EINVAL;
2352                         }
2353                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2354                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2355                                conf->nb_queue_pools == ETH_32_POOLS)) {
2356                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2357                                                 " nb_queue_pools != %d and"
2358                                                 " nb_queue_pools != %d.",
2359                                                 ETH_16_POOLS, ETH_32_POOLS);
2360                                 return -EINVAL;
2361                         }
2362                 }
2363
2364                 /* For DCB mode check our configuration before we go further */
2365                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2366                         const struct rte_eth_dcb_rx_conf *conf;
2367
2368                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2369                         if (!(conf->nb_tcs == ETH_4_TCS ||
2370                                conf->nb_tcs == ETH_8_TCS)) {
2371                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372                                                 " and nb_tcs != %d.",
2373                                                 ETH_4_TCS, ETH_8_TCS);
2374                                 return -EINVAL;
2375                         }
2376                 }
2377
2378                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2379                         const struct rte_eth_dcb_tx_conf *conf;
2380
2381                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2382                         if (!(conf->nb_tcs == ETH_4_TCS ||
2383                                conf->nb_tcs == ETH_8_TCS)) {
2384                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2385                                                 " and nb_tcs != %d.",
2386                                                 ETH_4_TCS, ETH_8_TCS);
2387                                 return -EINVAL;
2388                         }
2389                 }
2390
2391                 /*
2392                  * When DCB/VT is off, maximum number of queues changes,
2393                  * except for 82598EB, which remains constant.
2394                  */
2395                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2396                                 hw->mac.type != ixgbe_mac_82598EB) {
2397                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2398                                 PMD_INIT_LOG(ERR,
2399                                              "Neither VT nor DCB are enabled, "
2400                                              "nb_tx_q > %d.",
2401                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2402                                 return -EINVAL;
2403                         }
2404                 }
2405         }
2406         return 0;
2407 }
2408
2409 static int
2410 ixgbe_dev_configure(struct rte_eth_dev *dev)
2411 {
2412         struct ixgbe_interrupt *intr =
2413                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2414         struct ixgbe_adapter *adapter = dev->data->dev_private;
2415         int ret;
2416
2417         PMD_INIT_FUNC_TRACE();
2418
2419         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2420                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2421
2422         /* multipe queue mode checking */
2423         ret  = ixgbe_check_mq_mode(dev);
2424         if (ret != 0) {
2425                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2426                             ret);
2427                 return ret;
2428         }
2429
2430         /* set flag to update link status after init */
2431         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2432
2433         /*
2434          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2435          * allocation or vector Rx preconditions we will reset it.
2436          */
2437         adapter->rx_bulk_alloc_allowed = true;
2438         adapter->rx_vec_allowed = true;
2439
2440         return 0;
2441 }
2442
2443 static void
2444 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2445 {
2446         struct ixgbe_hw *hw =
2447                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2448         struct ixgbe_interrupt *intr =
2449                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2450         uint32_t gpie;
2451
2452         /* only set up it on X550EM_X */
2453         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2454                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2455                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2456                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2457                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2458                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2459         }
2460 }
2461
2462 int
2463 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2464                         uint16_t tx_rate, uint64_t q_msk)
2465 {
2466         struct ixgbe_hw *hw;
2467         struct ixgbe_vf_info *vfinfo;
2468         struct rte_eth_link link;
2469         uint8_t  nb_q_per_pool;
2470         uint32_t queue_stride;
2471         uint32_t queue_idx, idx = 0, vf_idx;
2472         uint32_t queue_end;
2473         uint16_t total_rate = 0;
2474         struct rte_pci_device *pci_dev;
2475         int ret;
2476
2477         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2478         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2479         if (ret < 0)
2480                 return ret;
2481
2482         if (vf >= pci_dev->max_vfs)
2483                 return -EINVAL;
2484
2485         if (tx_rate > link.link_speed)
2486                 return -EINVAL;
2487
2488         if (q_msk == 0)
2489                 return 0;
2490
2491         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2493         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2494         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2495         queue_idx = vf * queue_stride;
2496         queue_end = queue_idx + nb_q_per_pool - 1;
2497         if (queue_end >= hw->mac.max_tx_queues)
2498                 return -EINVAL;
2499
2500         if (vfinfo) {
2501                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2502                         if (vf_idx == vf)
2503                                 continue;
2504                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2505                                 idx++)
2506                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2507                 }
2508         } else {
2509                 return -EINVAL;
2510         }
2511
2512         /* Store tx_rate for this vf. */
2513         for (idx = 0; idx < nb_q_per_pool; idx++) {
2514                 if (((uint64_t)0x1 << idx) & q_msk) {
2515                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2516                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2517                         total_rate += tx_rate;
2518                 }
2519         }
2520
2521         if (total_rate > dev->data->dev_link.link_speed) {
2522                 /* Reset stored TX rate of the VF if it causes exceed
2523                  * link speed.
2524                  */
2525                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2526                 return -EINVAL;
2527         }
2528
2529         /* Set RTTBCNRC of each queue/pool for vf X  */
2530         for (; queue_idx <= queue_end; queue_idx++) {
2531                 if (0x1 & q_msk)
2532                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2533                 q_msk = q_msk >> 1;
2534         }
2535
2536         return 0;
2537 }
2538
2539 static int
2540 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2541 {
2542         struct ixgbe_adapter *adapter = dev->data->dev_private;
2543         int err;
2544         uint32_t mflcn;
2545
2546         err = ixgbe_fc_enable(hw);
2547
2548         /* Not negotiated is not an error case */
2549         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2550                 /*
2551                  *check if we want to forward MAC frames - driver doesn't
2552                  *have native capability to do that,
2553                  *so we'll write the registers ourselves
2554                  */
2555
2556                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2557
2558                 /* set or clear MFLCN.PMCF bit depending on configuration */
2559                 if (adapter->mac_ctrl_frame_fwd != 0)
2560                         mflcn |= IXGBE_MFLCN_PMCF;
2561                 else
2562                         mflcn &= ~IXGBE_MFLCN_PMCF;
2563
2564                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2565                 IXGBE_WRITE_FLUSH(hw);
2566
2567                 return 0;
2568         }
2569         return err;
2570 }
2571
2572 /*
2573  * Configure device link speed and setup link.
2574  * It returns 0 on success.
2575  */
2576 static int
2577 ixgbe_dev_start(struct rte_eth_dev *dev)
2578 {
2579         struct ixgbe_hw *hw =
2580                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581         struct ixgbe_vf_info *vfinfo =
2582                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2583         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2584         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2585         uint32_t intr_vector = 0;
2586         int err;
2587         bool link_up = false, negotiate = 0;
2588         uint32_t speed = 0;
2589         uint32_t allowed_speeds = 0;
2590         int mask = 0;
2591         int status;
2592         uint16_t vf, idx;
2593         uint32_t *link_speeds;
2594         struct ixgbe_tm_conf *tm_conf =
2595                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2596         struct ixgbe_macsec_setting *macsec_setting =
2597                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2598
2599         PMD_INIT_FUNC_TRACE();
2600
2601         /* Stop the link setup handler before resetting the HW. */
2602         ixgbe_dev_wait_setup_link_complete(dev, 0);
2603
2604         /* disable uio/vfio intr/eventfd mapping */
2605         rte_intr_disable(intr_handle);
2606
2607         /* stop adapter */
2608         hw->adapter_stopped = 0;
2609         ixgbe_stop_adapter(hw);
2610
2611         /* reinitialize adapter
2612          * this calls reset and start
2613          */
2614         status = ixgbe_pf_reset_hw(hw);
2615         if (status != 0)
2616                 return -1;
2617         hw->mac.ops.start_hw(hw);
2618         hw->mac.get_link_status = true;
2619
2620         /* configure PF module if SRIOV enabled */
2621         ixgbe_pf_host_configure(dev);
2622
2623         ixgbe_dev_phy_intr_setup(dev);
2624
2625         /* check and configure queue intr-vector mapping */
2626         if ((rte_intr_cap_multiple(intr_handle) ||
2627              !RTE_ETH_DEV_SRIOV(dev).active) &&
2628             dev->data->dev_conf.intr_conf.rxq != 0) {
2629                 intr_vector = dev->data->nb_rx_queues;
2630                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2631                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2632                                         IXGBE_MAX_INTR_QUEUE_NUM);
2633                         return -ENOTSUP;
2634                 }
2635                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2636                         return -1;
2637         }
2638
2639         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2640                 intr_handle->intr_vec =
2641                         rte_zmalloc("intr_vec",
2642                                     dev->data->nb_rx_queues * sizeof(int), 0);
2643                 if (intr_handle->intr_vec == NULL) {
2644                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2645                                      " intr_vec", dev->data->nb_rx_queues);
2646                         return -ENOMEM;
2647                 }
2648         }
2649
2650         /* confiugre msix for sleep until rx interrupt */
2651         ixgbe_configure_msix(dev);
2652
2653         /* initialize transmission unit */
2654         ixgbe_dev_tx_init(dev);
2655
2656         /* This can fail when allocating mbufs for descriptor rings */
2657         err = ixgbe_dev_rx_init(dev);
2658         if (err) {
2659                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2660                 goto error;
2661         }
2662
2663         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2664                 ETH_VLAN_EXTEND_MASK;
2665         err = ixgbe_vlan_offload_config(dev, mask);
2666         if (err) {
2667                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2668                 goto error;
2669         }
2670
2671         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2672                 /* Enable vlan filtering for VMDq */
2673                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2674         }
2675
2676         /* Configure DCB hw */
2677         ixgbe_configure_dcb(dev);
2678
2679         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2680                 err = ixgbe_fdir_configure(dev);
2681                 if (err)
2682                         goto error;
2683         }
2684
2685         /* Restore vf rate limit */
2686         if (vfinfo != NULL) {
2687                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2688                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2689                                 if (vfinfo[vf].tx_rate[idx] != 0)
2690                                         ixgbe_set_vf_rate_limit(
2691                                                 dev, vf,
2692                                                 vfinfo[vf].tx_rate[idx],
2693                                                 1 << idx);
2694         }
2695
2696         ixgbe_restore_statistics_mapping(dev);
2697
2698         err = ixgbe_flow_ctrl_enable(dev, hw);
2699         if (err < 0) {
2700                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2701                 goto error;
2702         }
2703
2704         err = ixgbe_dev_rxtx_start(dev);
2705         if (err < 0) {
2706                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2707                 goto error;
2708         }
2709
2710         /* Skip link setup if loopback mode is enabled. */
2711         if (dev->data->dev_conf.lpbk_mode != 0) {
2712                 err = ixgbe_check_supported_loopback_mode(dev);
2713                 if (err < 0) {
2714                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2715                         goto error;
2716                 } else {
2717                         goto skip_link_setup;
2718                 }
2719         }
2720
2721         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2722                 err = hw->mac.ops.setup_sfp(hw);
2723                 if (err)
2724                         goto error;
2725         }
2726
2727         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2728                 /* Turn on the copper */
2729                 ixgbe_set_phy_power(hw, true);
2730         } else {
2731                 /* Turn on the laser */
2732                 ixgbe_enable_tx_laser(hw);
2733         }
2734
2735         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2736         if (err)
2737                 goto error;
2738         dev->data->dev_link.link_status = link_up;
2739
2740         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2741         if (err)
2742                 goto error;
2743
2744         switch (hw->mac.type) {
2745         case ixgbe_mac_X550:
2746         case ixgbe_mac_X550EM_x:
2747         case ixgbe_mac_X550EM_a:
2748                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2749                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2750                         ETH_LINK_SPEED_10G;
2751                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2752                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2753                         allowed_speeds = ETH_LINK_SPEED_10M |
2754                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2755                 break;
2756         default:
2757                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2758                         ETH_LINK_SPEED_10G;
2759         }
2760
2761         link_speeds = &dev->data->dev_conf.link_speeds;
2762
2763         /* Ignore autoneg flag bit and check the validity of
2764          * link_speed
2765          */
2766         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2767                 PMD_INIT_LOG(ERR, "Invalid link setting");
2768                 goto error;
2769         }
2770
2771         speed = 0x0;
2772         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2773                 switch (hw->mac.type) {
2774                 case ixgbe_mac_82598EB:
2775                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2776                         break;
2777                 case ixgbe_mac_82599EB:
2778                 case ixgbe_mac_X540:
2779                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2780                         break;
2781                 case ixgbe_mac_X550:
2782                 case ixgbe_mac_X550EM_x:
2783                 case ixgbe_mac_X550EM_a:
2784                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2785                         break;
2786                 default:
2787                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2788                 }
2789         } else {
2790                 if (*link_speeds & ETH_LINK_SPEED_10G)
2791                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2792                 if (*link_speeds & ETH_LINK_SPEED_5G)
2793                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2794                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2795                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2796                 if (*link_speeds & ETH_LINK_SPEED_1G)
2797                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2798                 if (*link_speeds & ETH_LINK_SPEED_100M)
2799                         speed |= IXGBE_LINK_SPEED_100_FULL;
2800                 if (*link_speeds & ETH_LINK_SPEED_10M)
2801                         speed |= IXGBE_LINK_SPEED_10_FULL;
2802         }
2803
2804         err = ixgbe_setup_link(hw, speed, link_up);
2805         if (err)
2806                 goto error;
2807
2808 skip_link_setup:
2809
2810         if (rte_intr_allow_others(intr_handle)) {
2811                 /* check if lsc interrupt is enabled */
2812                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2813                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2814                 else
2815                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2816                 ixgbe_dev_macsec_interrupt_setup(dev);
2817         } else {
2818                 rte_intr_callback_unregister(intr_handle,
2819                                              ixgbe_dev_interrupt_handler, dev);
2820                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2821                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2822                                      " no intr multiplex");
2823         }
2824
2825         /* check if rxq interrupt is enabled */
2826         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2827             rte_intr_dp_is_en(intr_handle))
2828                 ixgbe_dev_rxq_interrupt_setup(dev);
2829
2830         /* enable uio/vfio intr/eventfd mapping */
2831         rte_intr_enable(intr_handle);
2832
2833         /* resume enabled intr since hw reset */
2834         ixgbe_enable_intr(dev);
2835         ixgbe_l2_tunnel_conf(dev);
2836         ixgbe_filter_restore(dev);
2837
2838         if (tm_conf->root && !tm_conf->committed)
2839                 PMD_DRV_LOG(WARNING,
2840                             "please call hierarchy_commit() "
2841                             "before starting the port");
2842
2843         /* wait for the controller to acquire link */
2844         err = ixgbe_wait_for_link_up(hw);
2845         if (err)
2846                 goto error;
2847
2848         /*
2849          * Update link status right before return, because it may
2850          * start link configuration process in a separate thread.
2851          */
2852         ixgbe_dev_link_update(dev, 0);
2853
2854         /* setup the macsec setting register */
2855         if (macsec_setting->offload_en)
2856                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2857
2858         return 0;
2859
2860 error:
2861         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2862         ixgbe_dev_clear_queues(dev);
2863         return -EIO;
2864 }
2865
2866 /*
2867  * Stop device: disable rx and tx functions to allow for reconfiguring.
2868  */
2869 static void
2870 ixgbe_dev_stop(struct rte_eth_dev *dev)
2871 {
2872         struct rte_eth_link link;
2873         struct ixgbe_adapter *adapter = dev->data->dev_private;
2874         struct ixgbe_hw *hw =
2875                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         struct ixgbe_vf_info *vfinfo =
2877                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2878         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2879         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2880         int vf;
2881         struct ixgbe_tm_conf *tm_conf =
2882                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2883
2884         if (hw->adapter_stopped)
2885                 return;
2886
2887         PMD_INIT_FUNC_TRACE();
2888
2889         ixgbe_dev_wait_setup_link_complete(dev, 0);
2890
2891         /* disable interrupts */
2892         ixgbe_disable_intr(hw);
2893
2894         /* reset the NIC */
2895         ixgbe_pf_reset_hw(hw);
2896         hw->adapter_stopped = 0;
2897
2898         /* stop adapter */
2899         ixgbe_stop_adapter(hw);
2900
2901         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2902                 vfinfo[vf].clear_to_send = false;
2903
2904         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2905                 /* Turn off the copper */
2906                 ixgbe_set_phy_power(hw, false);
2907         } else {
2908                 /* Turn off the laser */
2909                 ixgbe_disable_tx_laser(hw);
2910         }
2911
2912         ixgbe_dev_clear_queues(dev);
2913
2914         /* Clear stored conf */
2915         dev->data->scattered_rx = 0;
2916         dev->data->lro = 0;
2917
2918         /* Clear recorded link status */
2919         memset(&link, 0, sizeof(link));
2920         rte_eth_linkstatus_set(dev, &link);
2921
2922         if (!rte_intr_allow_others(intr_handle))
2923                 /* resume to the default handler */
2924                 rte_intr_callback_register(intr_handle,
2925                                            ixgbe_dev_interrupt_handler,
2926                                            (void *)dev);
2927
2928         /* Clean datapath event and queue/vec mapping */
2929         rte_intr_efd_disable(intr_handle);
2930         if (intr_handle->intr_vec != NULL) {
2931                 rte_free(intr_handle->intr_vec);
2932                 intr_handle->intr_vec = NULL;
2933         }
2934
2935         /* reset hierarchy commit */
2936         tm_conf->committed = false;
2937
2938         adapter->rss_reta_updated = 0;
2939
2940         adapter->mac_ctrl_frame_fwd = 0;
2941
2942         hw->adapter_stopped = true;
2943 }
2944
2945 /*
2946  * Set device link up: enable tx.
2947  */
2948 static int
2949 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2950 {
2951         struct ixgbe_hw *hw =
2952                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2953         if (hw->mac.type == ixgbe_mac_82599EB) {
2954 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2955                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2956                         /* Not suported in bypass mode */
2957                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2958                                      "by device id 0x%x", hw->device_id);
2959                         return -ENOTSUP;
2960                 }
2961 #endif
2962         }
2963
2964         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2965                 /* Turn on the copper */
2966                 ixgbe_set_phy_power(hw, true);
2967         } else {
2968                 /* Turn on the laser */
2969                 ixgbe_enable_tx_laser(hw);
2970                 ixgbe_dev_link_update(dev, 0);
2971         }
2972
2973         return 0;
2974 }
2975
2976 /*
2977  * Set device link down: disable tx.
2978  */
2979 static int
2980 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2981 {
2982         struct ixgbe_hw *hw =
2983                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984         if (hw->mac.type == ixgbe_mac_82599EB) {
2985 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2986                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2987                         /* Not suported in bypass mode */
2988                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2989                                      "by device id 0x%x", hw->device_id);
2990                         return -ENOTSUP;
2991                 }
2992 #endif
2993         }
2994
2995         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2996                 /* Turn off the copper */
2997                 ixgbe_set_phy_power(hw, false);
2998         } else {
2999                 /* Turn off the laser */
3000                 ixgbe_disable_tx_laser(hw);
3001                 ixgbe_dev_link_update(dev, 0);
3002         }
3003
3004         return 0;
3005 }
3006
3007 /*
3008  * Reset and stop device.
3009  */
3010 static void
3011 ixgbe_dev_close(struct rte_eth_dev *dev)
3012 {
3013         struct ixgbe_hw *hw =
3014                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3016         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3017         int retries = 0;
3018         int ret;
3019
3020         PMD_INIT_FUNC_TRACE();
3021
3022         ixgbe_pf_reset_hw(hw);
3023
3024         ixgbe_dev_stop(dev);
3025
3026         ixgbe_dev_free_queues(dev);
3027
3028         ixgbe_disable_pcie_master(hw);
3029
3030         /* reprogram the RAR[0] in case user changed it. */
3031         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3032
3033         dev->dev_ops = NULL;
3034         dev->rx_pkt_burst = NULL;
3035         dev->tx_pkt_burst = NULL;
3036
3037         /* Unlock any pending hardware semaphore */
3038         ixgbe_swfw_lock_reset(hw);
3039
3040         /* disable uio intr before callback unregister */
3041         rte_intr_disable(intr_handle);
3042
3043         do {
3044                 ret = rte_intr_callback_unregister(intr_handle,
3045                                 ixgbe_dev_interrupt_handler, dev);
3046                 if (ret >= 0 || ret == -ENOENT) {
3047                         break;
3048                 } else if (ret != -EAGAIN) {
3049                         PMD_INIT_LOG(ERR,
3050                                 "intr callback unregister failed: %d",
3051                                 ret);
3052                 }
3053                 rte_delay_ms(100);
3054         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3055
3056         /* cancel the delay handler before remove dev */
3057         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3058
3059         /* uninitialize PF if max_vfs not zero */
3060         ixgbe_pf_host_uninit(dev);
3061
3062         /* remove all the fdir filters & hash */
3063         ixgbe_fdir_filter_uninit(dev);
3064
3065         /* remove all the L2 tunnel filters & hash */
3066         ixgbe_l2_tn_filter_uninit(dev);
3067
3068         /* Remove all ntuple filters of the device */
3069         ixgbe_ntuple_filter_uninit(dev);
3070
3071         /* clear all the filters list */
3072         ixgbe_filterlist_flush();
3073
3074         /* Remove all Traffic Manager configuration */
3075         ixgbe_tm_conf_uninit(dev);
3076
3077 #ifdef RTE_LIBRTE_SECURITY
3078         rte_free(dev->security_ctx);
3079 #endif
3080
3081 }
3082
3083 /*
3084  * Reset PF device.
3085  */
3086 static int
3087 ixgbe_dev_reset(struct rte_eth_dev *dev)
3088 {
3089         int ret;
3090
3091         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3092          * its VF to make them align with it. The detailed notification
3093          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3094          * To avoid unexpected behavior in VF, currently reset of PF with
3095          * SR-IOV activation is not supported. It might be supported later.
3096          */
3097         if (dev->data->sriov.active)
3098                 return -ENOTSUP;
3099
3100         ret = eth_ixgbe_dev_uninit(dev);
3101         if (ret)
3102                 return ret;
3103
3104         ret = eth_ixgbe_dev_init(dev, NULL);
3105
3106         return ret;
3107 }
3108
3109 static void
3110 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3111                            struct ixgbe_hw_stats *hw_stats,
3112                            struct ixgbe_macsec_stats *macsec_stats,
3113                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3114                            uint64_t *total_qprc, uint64_t *total_qprdc)
3115 {
3116         uint32_t bprc, lxon, lxoff, total;
3117         uint32_t delta_gprc = 0;
3118         unsigned i;
3119         /* Workaround for RX byte count not including CRC bytes when CRC
3120          * strip is enabled. CRC bytes are removed from counters when crc_strip
3121          * is disabled.
3122          */
3123         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3124                         IXGBE_HLREG0_RXCRCSTRP);
3125
3126         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3127         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3128         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3129         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3130
3131         for (i = 0; i < 8; i++) {
3132                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3133
3134                 /* global total per queue */
3135                 hw_stats->mpc[i] += mp;
3136                 /* Running comprehensive total for stats display */
3137                 *total_missed_rx += hw_stats->mpc[i];
3138                 if (hw->mac.type == ixgbe_mac_82598EB) {
3139                         hw_stats->rnbc[i] +=
3140                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3141                         hw_stats->pxonrxc[i] +=
3142                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3143                         hw_stats->pxoffrxc[i] +=
3144                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3145                 } else {
3146                         hw_stats->pxonrxc[i] +=
3147                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3148                         hw_stats->pxoffrxc[i] +=
3149                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3150                         hw_stats->pxon2offc[i] +=
3151                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3152                 }
3153                 hw_stats->pxontxc[i] +=
3154                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3155                 hw_stats->pxofftxc[i] +=
3156                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3157         }
3158         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3159                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3160                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3161                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3162
3163                 delta_gprc += delta_qprc;
3164
3165                 hw_stats->qprc[i] += delta_qprc;
3166                 hw_stats->qptc[i] += delta_qptc;
3167
3168                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3169                 hw_stats->qbrc[i] +=
3170                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3171                 if (crc_strip == 0)
3172                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3173
3174                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3175                 hw_stats->qbtc[i] +=
3176                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3177
3178                 hw_stats->qprdc[i] += delta_qprdc;
3179                 *total_qprdc += hw_stats->qprdc[i];
3180
3181                 *total_qprc += hw_stats->qprc[i];
3182                 *total_qbrc += hw_stats->qbrc[i];
3183         }
3184         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3185         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3186         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3187
3188         /*
3189          * An errata states that gprc actually counts good + missed packets:
3190          * Workaround to set gprc to summated queue packet receives
3191          */
3192         hw_stats->gprc = *total_qprc;
3193
3194         if (hw->mac.type != ixgbe_mac_82598EB) {
3195                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3196                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3197                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3198                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3199                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3200                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3201                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3202                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3203         } else {
3204                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3205                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3206                 /* 82598 only has a counter in the high register */
3207                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3208                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3209                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3210         }
3211         uint64_t old_tpr = hw_stats->tpr;
3212
3213         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3214         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3215
3216         if (crc_strip == 0)
3217                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3218
3219         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3220         hw_stats->gptc += delta_gptc;
3221         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3222         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3223
3224         /*
3225          * Workaround: mprc hardware is incorrectly counting
3226          * broadcasts, so for now we subtract those.
3227          */
3228         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3229         hw_stats->bprc += bprc;
3230         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3231         if (hw->mac.type == ixgbe_mac_82598EB)
3232                 hw_stats->mprc -= bprc;
3233
3234         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3235         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3236         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3237         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3238         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3239         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3240
3241         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3242         hw_stats->lxontxc += lxon;
3243         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3244         hw_stats->lxofftxc += lxoff;
3245         total = lxon + lxoff;
3246
3247         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3248         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3249         hw_stats->gptc -= total;
3250         hw_stats->mptc -= total;
3251         hw_stats->ptc64 -= total;
3252         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3253
3254         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3255         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3256         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3257         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3258         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3259         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3260         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3261         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3262         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3263         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3264         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3265         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3266         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3267         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3268         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3269         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3270         /* Only read FCOE on 82599 */
3271         if (hw->mac.type != ixgbe_mac_82598EB) {
3272                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3273                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3274                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3275                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3276                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3277         }
3278
3279         /* Flow Director Stats registers */
3280         if (hw->mac.type != ixgbe_mac_82598EB) {
3281                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3282                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3283                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3284                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3285                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3286                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3287                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3288                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3289                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3290                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3291         }
3292         /* MACsec Stats registers */
3293         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3294         macsec_stats->out_pkts_encrypted +=
3295                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3296         macsec_stats->out_pkts_protected +=
3297                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3298         macsec_stats->out_octets_encrypted +=
3299                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3300         macsec_stats->out_octets_protected +=
3301                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3302         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3303         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3304         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3305         macsec_stats->in_pkts_unknownsci +=
3306                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3307         macsec_stats->in_octets_decrypted +=
3308                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3309         macsec_stats->in_octets_validated +=
3310                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3311         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3312         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3313         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3314         for (i = 0; i < 2; i++) {
3315                 macsec_stats->in_pkts_ok +=
3316                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3317                 macsec_stats->in_pkts_invalid +=
3318                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3319                 macsec_stats->in_pkts_notvalid +=
3320                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3321         }
3322         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3323         macsec_stats->in_pkts_notusingsa +=
3324                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3325 }
3326
3327 /*
3328  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3329  */
3330 static int
3331 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3332 {
3333         struct ixgbe_hw *hw =
3334                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3335         struct ixgbe_hw_stats *hw_stats =
3336                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3337         struct ixgbe_macsec_stats *macsec_stats =
3338                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3339                                 dev->data->dev_private);
3340         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3341         unsigned i;
3342
3343         total_missed_rx = 0;
3344         total_qbrc = 0;
3345         total_qprc = 0;
3346         total_qprdc = 0;
3347
3348         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3349                         &total_qbrc, &total_qprc, &total_qprdc);
3350
3351         if (stats == NULL)
3352                 return -EINVAL;
3353
3354         /* Fill out the rte_eth_stats statistics structure */
3355         stats->ipackets = total_qprc;
3356         stats->ibytes = total_qbrc;
3357         stats->opackets = hw_stats->gptc;
3358         stats->obytes = hw_stats->gotc;
3359
3360         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3361                 stats->q_ipackets[i] = hw_stats->qprc[i];
3362                 stats->q_opackets[i] = hw_stats->qptc[i];
3363                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3364                 stats->q_obytes[i] = hw_stats->qbtc[i];
3365                 stats->q_errors[i] = hw_stats->qprdc[i];
3366         }
3367
3368         /* Rx Errors */
3369         stats->imissed  = total_missed_rx;
3370         stats->ierrors  = hw_stats->crcerrs +
3371                           hw_stats->mspdc +
3372                           hw_stats->rlec +
3373                           hw_stats->ruc +
3374                           hw_stats->roc +
3375                           hw_stats->illerrc +
3376                           hw_stats->errbc +
3377                           hw_stats->rfc +
3378                           hw_stats->fccrc +
3379                           hw_stats->fclast;
3380
3381         /* Tx Errors */
3382         stats->oerrors  = 0;
3383         return 0;
3384 }
3385
3386 static int
3387 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3388 {
3389         struct ixgbe_hw_stats *stats =
3390                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3391
3392         /* HW registers are cleared on read */
3393         ixgbe_dev_stats_get(dev, NULL);
3394
3395         /* Reset software totals */
3396         memset(stats, 0, sizeof(*stats));
3397
3398         return 0;
3399 }
3400
3401 /* This function calculates the number of xstats based on the current config */
3402 static unsigned
3403 ixgbe_xstats_calc_num(void) {
3404         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3405                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3406                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3407 }
3408
3409 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3410         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3411 {
3412         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3413         unsigned stat, i, count;
3414
3415         if (xstats_names != NULL) {
3416                 count = 0;
3417
3418                 /* Note: limit >= cnt_stats checked upstream
3419                  * in rte_eth_xstats_names()
3420                  */
3421
3422                 /* Extended stats from ixgbe_hw_stats */
3423                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3424                         strlcpy(xstats_names[count].name,
3425                                 rte_ixgbe_stats_strings[i].name,
3426                                 sizeof(xstats_names[count].name));
3427                         count++;
3428                 }
3429
3430                 /* MACsec Stats */
3431                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3432                         strlcpy(xstats_names[count].name,
3433                                 rte_ixgbe_macsec_strings[i].name,
3434                                 sizeof(xstats_names[count].name));
3435                         count++;
3436                 }
3437
3438                 /* RX Priority Stats */
3439                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3440                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3441                                 snprintf(xstats_names[count].name,
3442                                         sizeof(xstats_names[count].name),
3443                                         "rx_priority%u_%s", i,
3444                                         rte_ixgbe_rxq_strings[stat].name);
3445                                 count++;
3446                         }
3447                 }
3448
3449                 /* TX Priority Stats */
3450                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3451                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3452                                 snprintf(xstats_names[count].name,
3453                                         sizeof(xstats_names[count].name),
3454                                         "tx_priority%u_%s", i,
3455                                         rte_ixgbe_txq_strings[stat].name);
3456                                 count++;
3457                         }
3458                 }
3459         }
3460         return cnt_stats;
3461 }
3462
3463 static int ixgbe_dev_xstats_get_names_by_id(
3464         struct rte_eth_dev *dev,
3465         struct rte_eth_xstat_name *xstats_names,
3466         const uint64_t *ids,
3467         unsigned int limit)
3468 {
3469         if (!ids) {
3470                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3471                 unsigned int stat, i, count;
3472
3473                 if (xstats_names != NULL) {
3474                         count = 0;
3475
3476                         /* Note: limit >= cnt_stats checked upstream
3477                          * in rte_eth_xstats_names()
3478                          */
3479
3480                         /* Extended stats from ixgbe_hw_stats */
3481                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3482                                 strlcpy(xstats_names[count].name,
3483                                         rte_ixgbe_stats_strings[i].name,
3484                                         sizeof(xstats_names[count].name));
3485                                 count++;
3486                         }
3487
3488                         /* MACsec Stats */
3489                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3490                                 strlcpy(xstats_names[count].name,
3491                                         rte_ixgbe_macsec_strings[i].name,
3492                                         sizeof(xstats_names[count].name));
3493                                 count++;
3494                         }
3495
3496                         /* RX Priority Stats */
3497                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3498                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3499                                         snprintf(xstats_names[count].name,
3500                                             sizeof(xstats_names[count].name),
3501                                             "rx_priority%u_%s", i,
3502                                             rte_ixgbe_rxq_strings[stat].name);
3503                                         count++;
3504                                 }
3505                         }
3506
3507                         /* TX Priority Stats */
3508                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3509                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3510                                         snprintf(xstats_names[count].name,
3511                                             sizeof(xstats_names[count].name),
3512                                             "tx_priority%u_%s", i,
3513                                             rte_ixgbe_txq_strings[stat].name);
3514                                         count++;
3515                                 }
3516                         }
3517                 }
3518                 return cnt_stats;
3519         }
3520
3521         uint16_t i;
3522         uint16_t size = ixgbe_xstats_calc_num();
3523         struct rte_eth_xstat_name xstats_names_copy[size];
3524
3525         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3526                         size);
3527
3528         for (i = 0; i < limit; i++) {
3529                 if (ids[i] >= size) {
3530                         PMD_INIT_LOG(ERR, "id value isn't valid");
3531                         return -1;
3532                 }
3533                 strcpy(xstats_names[i].name,
3534                                 xstats_names_copy[ids[i]].name);
3535         }
3536         return limit;
3537 }
3538
3539 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3540         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3541 {
3542         unsigned i;
3543
3544         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3545                 return -ENOMEM;
3546
3547         if (xstats_names != NULL)
3548                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3549                         strlcpy(xstats_names[i].name,
3550                                 rte_ixgbevf_stats_strings[i].name,
3551                                 sizeof(xstats_names[i].name));
3552         return IXGBEVF_NB_XSTATS;
3553 }
3554
3555 static int
3556 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3557                                          unsigned n)
3558 {
3559         struct ixgbe_hw *hw =
3560                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3561         struct ixgbe_hw_stats *hw_stats =
3562                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3563         struct ixgbe_macsec_stats *macsec_stats =
3564                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3565                                 dev->data->dev_private);
3566         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3567         unsigned i, stat, count = 0;
3568
3569         count = ixgbe_xstats_calc_num();
3570
3571         if (n < count)
3572                 return count;
3573
3574         total_missed_rx = 0;
3575         total_qbrc = 0;
3576         total_qprc = 0;
3577         total_qprdc = 0;
3578
3579         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3580                         &total_qbrc, &total_qprc, &total_qprdc);
3581
3582         /* If this is a reset xstats is NULL, and we have cleared the
3583          * registers by reading them.
3584          */
3585         if (!xstats)
3586                 return 0;
3587
3588         /* Extended stats from ixgbe_hw_stats */
3589         count = 0;
3590         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3591                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3592                                 rte_ixgbe_stats_strings[i].offset);
3593                 xstats[count].id = count;
3594                 count++;
3595         }
3596
3597         /* MACsec Stats */
3598         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3599                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3600                                 rte_ixgbe_macsec_strings[i].offset);
3601                 xstats[count].id = count;
3602                 count++;
3603         }
3604
3605         /* RX Priority Stats */
3606         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3607                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3608                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3609                                         rte_ixgbe_rxq_strings[stat].offset +
3610                                         (sizeof(uint64_t) * i));
3611                         xstats[count].id = count;
3612                         count++;
3613                 }
3614         }
3615
3616         /* TX Priority Stats */
3617         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3618                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3619                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3620                                         rte_ixgbe_txq_strings[stat].offset +
3621                                         (sizeof(uint64_t) * i));
3622                         xstats[count].id = count;
3623                         count++;
3624                 }
3625         }
3626         return count;
3627 }
3628
3629 static int
3630 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3631                 uint64_t *values, unsigned int n)
3632 {
3633         if (!ids) {
3634                 struct ixgbe_hw *hw =
3635                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3636                 struct ixgbe_hw_stats *hw_stats =
3637                                 IXGBE_DEV_PRIVATE_TO_STATS(
3638                                                 dev->data->dev_private);
3639                 struct ixgbe_macsec_stats *macsec_stats =
3640                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3641                                         dev->data->dev_private);
3642                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3643                 unsigned int i, stat, count = 0;
3644
3645                 count = ixgbe_xstats_calc_num();
3646
3647                 if (!ids && n < count)
3648                         return count;
3649
3650                 total_missed_rx = 0;
3651                 total_qbrc = 0;
3652                 total_qprc = 0;
3653                 total_qprdc = 0;
3654
3655                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3656                                 &total_missed_rx, &total_qbrc, &total_qprc,
3657                                 &total_qprdc);
3658
3659                 /* If this is a reset xstats is NULL, and we have cleared the
3660                  * registers by reading them.
3661                  */
3662                 if (!ids && !values)
3663                         return 0;
3664
3665                 /* Extended stats from ixgbe_hw_stats */
3666                 count = 0;
3667                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3668                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3669                                         rte_ixgbe_stats_strings[i].offset);
3670                         count++;
3671                 }
3672
3673                 /* MACsec Stats */
3674                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3675                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3676                                         rte_ixgbe_macsec_strings[i].offset);
3677                         count++;
3678                 }
3679
3680                 /* RX Priority Stats */
3681                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3682                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3683                                 values[count] =
3684                                         *(uint64_t *)(((char *)hw_stats) +
3685                                         rte_ixgbe_rxq_strings[stat].offset +
3686                                         (sizeof(uint64_t) * i));
3687                                 count++;
3688                         }
3689                 }
3690
3691                 /* TX Priority Stats */
3692                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3693                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3694                                 values[count] =
3695                                         *(uint64_t *)(((char *)hw_stats) +
3696                                         rte_ixgbe_txq_strings[stat].offset +
3697                                         (sizeof(uint64_t) * i));
3698                                 count++;
3699                         }
3700                 }
3701                 return count;
3702         }
3703
3704         uint16_t i;
3705         uint16_t size = ixgbe_xstats_calc_num();
3706         uint64_t values_copy[size];
3707
3708         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3709
3710         for (i = 0; i < n; i++) {
3711                 if (ids[i] >= size) {
3712                         PMD_INIT_LOG(ERR, "id value isn't valid");
3713                         return -1;
3714                 }
3715                 values[i] = values_copy[ids[i]];
3716         }
3717         return n;
3718 }
3719
3720 static int
3721 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3722 {
3723         struct ixgbe_hw_stats *stats =
3724                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3725         struct ixgbe_macsec_stats *macsec_stats =
3726                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3727                                 dev->data->dev_private);
3728
3729         unsigned count = ixgbe_xstats_calc_num();
3730
3731         /* HW registers are cleared on read */
3732         ixgbe_dev_xstats_get(dev, NULL, count);
3733
3734         /* Reset software totals */
3735         memset(stats, 0, sizeof(*stats));
3736         memset(macsec_stats, 0, sizeof(*macsec_stats));
3737
3738         return 0;
3739 }
3740
3741 static void
3742 ixgbevf_update_stats(struct rte_eth_dev *dev)
3743 {
3744         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3745         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3746                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3747
3748         /* Good Rx packet, include VF loopback */
3749         UPDATE_VF_STAT(IXGBE_VFGPRC,
3750             hw_stats->last_vfgprc, hw_stats->vfgprc);
3751
3752         /* Good Rx octets, include VF loopback */
3753         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3754             hw_stats->last_vfgorc, hw_stats->vfgorc);
3755
3756         /* Good Tx packet, include VF loopback */
3757         UPDATE_VF_STAT(IXGBE_VFGPTC,
3758             hw_stats->last_vfgptc, hw_stats->vfgptc);
3759
3760         /* Good Tx octets, include VF loopback */
3761         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3762             hw_stats->last_vfgotc, hw_stats->vfgotc);
3763
3764         /* Rx Multicst Packet */
3765         UPDATE_VF_STAT(IXGBE_VFMPRC,
3766             hw_stats->last_vfmprc, hw_stats->vfmprc);
3767 }
3768
3769 static int
3770 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3771                        unsigned n)
3772 {
3773         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3774                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3775         unsigned i;
3776
3777         if (n < IXGBEVF_NB_XSTATS)
3778                 return IXGBEVF_NB_XSTATS;
3779
3780         ixgbevf_update_stats(dev);
3781
3782         if (!xstats)
3783                 return 0;
3784
3785         /* Extended stats */
3786         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3787                 xstats[i].id = i;
3788                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3789                         rte_ixgbevf_stats_strings[i].offset);
3790         }
3791
3792         return IXGBEVF_NB_XSTATS;
3793 }
3794
3795 static int
3796 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3797 {
3798         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3799                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3800
3801         ixgbevf_update_stats(dev);
3802
3803         if (stats == NULL)
3804                 return -EINVAL;
3805
3806         stats->ipackets = hw_stats->vfgprc;
3807         stats->ibytes = hw_stats->vfgorc;
3808         stats->opackets = hw_stats->vfgptc;
3809         stats->obytes = hw_stats->vfgotc;
3810         return 0;
3811 }
3812
3813 static int
3814 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3815 {
3816         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3817                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3818
3819         /* Sync HW register to the last stats */
3820         ixgbevf_dev_stats_get(dev, NULL);
3821
3822         /* reset HW current stats*/
3823         hw_stats->vfgprc = 0;
3824         hw_stats->vfgorc = 0;
3825         hw_stats->vfgptc = 0;
3826         hw_stats->vfgotc = 0;
3827
3828         return 0;
3829 }
3830
3831 static int
3832 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3833 {
3834         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3835         u16 eeprom_verh, eeprom_verl;
3836         u32 etrack_id;
3837         int ret;
3838
3839         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3840         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3841
3842         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3843         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3844
3845         ret += 1; /* add the size of '\0' */
3846         if (fw_size < (u32)ret)
3847                 return ret;
3848         else
3849                 return 0;
3850 }
3851
3852 static int
3853 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3854 {
3855         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3858
3859         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3860         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3861         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3862                 /*
3863                  * When DCB/VT is off, maximum number of queues changes,
3864                  * except for 82598EB, which remains constant.
3865                  */
3866                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3867                                 hw->mac.type != ixgbe_mac_82598EB)
3868                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3869         }
3870         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3871         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3872         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3873         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3874         dev_info->max_vfs = pci_dev->max_vfs;
3875         if (hw->mac.type == ixgbe_mac_82598EB)
3876                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3877         else
3878                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3879         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3880         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3881         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3882         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3883         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3884                                      dev_info->rx_queue_offload_capa);
3885         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3886         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3887
3888         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3889                 .rx_thresh = {
3890                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3891                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3892                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3893                 },
3894                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3895                 .rx_drop_en = 0,
3896                 .offloads = 0,
3897         };
3898
3899         dev_info->default_txconf = (struct rte_eth_txconf) {
3900                 .tx_thresh = {
3901                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3902                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3903                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3904                 },
3905                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3906                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3907                 .offloads = 0,
3908         };
3909
3910         dev_info->rx_desc_lim = rx_desc_lim;
3911         dev_info->tx_desc_lim = tx_desc_lim;
3912
3913         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3914         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3915         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3916
3917         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3918         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3919                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3920                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3921                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3922
3923         if (hw->mac.type == ixgbe_mac_X540 ||
3924             hw->mac.type == ixgbe_mac_X540_vf ||
3925             hw->mac.type == ixgbe_mac_X550 ||
3926             hw->mac.type == ixgbe_mac_X550_vf) {
3927                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3928         }
3929         if (hw->mac.type == ixgbe_mac_X550) {
3930                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3931                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3932         }
3933
3934         /* Driver-preferred Rx/Tx parameters */
3935         dev_info->default_rxportconf.burst_size = 32;
3936         dev_info->default_txportconf.burst_size = 32;
3937         dev_info->default_rxportconf.nb_queues = 1;
3938         dev_info->default_txportconf.nb_queues = 1;
3939         dev_info->default_rxportconf.ring_size = 256;
3940         dev_info->default_txportconf.ring_size = 256;
3941
3942         return 0;
3943 }
3944
3945 static const uint32_t *
3946 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3947 {
3948         static const uint32_t ptypes[] = {
3949                 /* For non-vec functions,
3950                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3951                  * for vec functions,
3952                  * refers to _recv_raw_pkts_vec().
3953                  */
3954                 RTE_PTYPE_L2_ETHER,
3955                 RTE_PTYPE_L3_IPV4,
3956                 RTE_PTYPE_L3_IPV4_EXT,
3957                 RTE_PTYPE_L3_IPV6,
3958                 RTE_PTYPE_L3_IPV6_EXT,
3959                 RTE_PTYPE_L4_SCTP,
3960                 RTE_PTYPE_L4_TCP,
3961                 RTE_PTYPE_L4_UDP,
3962                 RTE_PTYPE_TUNNEL_IP,
3963                 RTE_PTYPE_INNER_L3_IPV6,
3964                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3965                 RTE_PTYPE_INNER_L4_TCP,
3966                 RTE_PTYPE_INNER_L4_UDP,
3967                 RTE_PTYPE_UNKNOWN
3968         };
3969
3970         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3971             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3972             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3973             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3974                 return ptypes;
3975
3976 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3977         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3978             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3979                 return ptypes;
3980 #endif
3981         return NULL;
3982 }
3983
3984 static int
3985 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3986                      struct rte_eth_dev_info *dev_info)
3987 {
3988         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3989         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3990
3991         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3992         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3993         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3994         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3995         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3996         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3997         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3998         dev_info->max_vfs = pci_dev->max_vfs;
3999         if (hw->mac.type == ixgbe_mac_82598EB)
4000                 dev_info->max_vmdq_pools = ETH_16_POOLS;
4001         else
4002                 dev_info->max_vmdq_pools = ETH_64_POOLS;
4003         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
4004         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
4005                                      dev_info->rx_queue_offload_capa);
4006         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
4007         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
4008         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
4009         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
4010         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
4011
4012         dev_info->default_rxconf = (struct rte_eth_rxconf) {
4013                 .rx_thresh = {
4014                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4015                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4016                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4017                 },
4018                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4019                 .rx_drop_en = 0,
4020                 .offloads = 0,
4021         };
4022
4023         dev_info->default_txconf = (struct rte_eth_txconf) {
4024                 .tx_thresh = {
4025                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4026                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4027                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4028                 },
4029                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4030                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4031                 .offloads = 0,
4032         };
4033
4034         dev_info->rx_desc_lim = rx_desc_lim;
4035         dev_info->tx_desc_lim = tx_desc_lim;
4036
4037         return 0;
4038 }
4039
4040 static int
4041 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4042                    bool *link_up, int wait_to_complete)
4043 {
4044         struct ixgbe_adapter *adapter = container_of(hw,
4045                                                      struct ixgbe_adapter, hw);
4046         struct ixgbe_mbx_info *mbx = &hw->mbx;
4047         struct ixgbe_mac_info *mac = &hw->mac;
4048         uint32_t links_reg, in_msg;
4049         int ret_val = 0;
4050
4051         /* If we were hit with a reset drop the link */
4052         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4053                 mac->get_link_status = true;
4054
4055         if (!mac->get_link_status)
4056                 goto out;
4057
4058         /* if link status is down no point in checking to see if pf is up */
4059         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4060         if (!(links_reg & IXGBE_LINKS_UP))
4061                 goto out;
4062
4063         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4064          * before the link status is correct
4065          */
4066         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4067                 int i;
4068
4069                 for (i = 0; i < 5; i++) {
4070                         rte_delay_us(100);
4071                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4072
4073                         if (!(links_reg & IXGBE_LINKS_UP))
4074                                 goto out;
4075                 }
4076         }
4077
4078         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4079         case IXGBE_LINKS_SPEED_10G_82599:
4080                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4081                 if (hw->mac.type >= ixgbe_mac_X550) {
4082                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4083                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4084                 }
4085                 break;
4086         case IXGBE_LINKS_SPEED_1G_82599:
4087                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4088                 break;
4089         case IXGBE_LINKS_SPEED_100_82599:
4090                 *speed = IXGBE_LINK_SPEED_100_FULL;
4091                 if (hw->mac.type == ixgbe_mac_X550) {
4092                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4093                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4094                 }
4095                 break;
4096         case IXGBE_LINKS_SPEED_10_X550EM_A:
4097                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4098                 /* Since Reserved in older MAC's */
4099                 if (hw->mac.type >= ixgbe_mac_X550)
4100                         *speed = IXGBE_LINK_SPEED_10_FULL;
4101                 break;
4102         default:
4103                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4104         }
4105
4106         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4107                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4108                         mac->get_link_status = true;
4109                 else
4110                         mac->get_link_status = false;
4111
4112                 goto out;
4113         }
4114
4115         /* if the read failed it could just be a mailbox collision, best wait
4116          * until we are called again and don't report an error
4117          */
4118         if (mbx->ops.read(hw, &in_msg, 1, 0))
4119                 goto out;
4120
4121         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4122                 /* msg is not CTS and is NACK we must have lost CTS status */
4123                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4124                         mac->get_link_status = false;
4125                 goto out;
4126         }
4127
4128         /* the pf is talking, if we timed out in the past we reinit */
4129         if (!mbx->timeout) {
4130                 ret_val = -1;
4131                 goto out;
4132         }
4133
4134         /* if we passed all the tests above then the link is up and we no
4135          * longer need to check for link
4136          */
4137         mac->get_link_status = false;
4138
4139 out:
4140         *link_up = !mac->get_link_status;
4141         return ret_val;
4142 }
4143
4144 /*
4145  * If @timeout_ms was 0, it means that it will not return until link complete.
4146  * It returns 1 on complete, return 0 on timeout.
4147  */
4148 static int
4149 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4150 {
4151 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4152         struct ixgbe_adapter *ad = dev->data->dev_private;
4153         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4154
4155         while (rte_atomic32_read(&ad->link_thread_running)) {
4156                 msec_delay(1);
4157                 timeout--;
4158
4159                 if (timeout_ms) {
4160                         if (!timeout)
4161                                 return 0;
4162                 } else if (!timeout) {
4163                         /* It will not return until link complete */
4164                         timeout = WARNING_TIMEOUT;
4165                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4166                 }
4167         }
4168
4169         return 1;
4170 }
4171
4172 static void *
4173 ixgbe_dev_setup_link_thread_handler(void *param)
4174 {
4175         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4176         struct ixgbe_adapter *ad = dev->data->dev_private;
4177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4178         struct ixgbe_interrupt *intr =
4179                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4180         u32 speed;
4181         bool autoneg = false;
4182
4183         pthread_detach(pthread_self());
4184         speed = hw->phy.autoneg_advertised;
4185         if (!speed)
4186                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4187
4188         ixgbe_setup_link(hw, speed, true);
4189
4190         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4191         rte_atomic32_clear(&ad->link_thread_running);
4192         return NULL;
4193 }
4194
4195 /*
4196  * In freebsd environment, nic_uio drivers do not support interrupts,
4197  * rte_intr_callback_register() will fail to register interrupts.
4198  * We can not make link status to change from down to up by interrupt
4199  * callback. So we need to wait for the controller to acquire link
4200  * when ports start.
4201  * It returns 0 on link up.
4202  */
4203 static int
4204 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4205 {
4206 #ifdef RTE_EXEC_ENV_FREEBSD
4207         int err, i;
4208         bool link_up = false;
4209         uint32_t speed = 0;
4210         const int nb_iter = 25;
4211
4212         for (i = 0; i < nb_iter; i++) {
4213                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4214                 if (err)
4215                         return err;
4216                 if (link_up)
4217                         return 0;
4218                 msec_delay(200);
4219         }
4220
4221         return 0;
4222 #else
4223         RTE_SET_USED(hw);
4224         return 0;
4225 #endif
4226 }
4227
4228 /* return 0 means link status changed, -1 means not changed */
4229 int
4230 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4231                             int wait_to_complete, int vf)
4232 {
4233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234         struct ixgbe_adapter *ad = dev->data->dev_private;
4235         struct rte_eth_link link;
4236         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4237         struct ixgbe_interrupt *intr =
4238                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4239         bool link_up;
4240         int diag;
4241         int wait = 1;
4242         u32 esdp_reg;
4243
4244         memset(&link, 0, sizeof(link));
4245         link.link_status = ETH_LINK_DOWN;
4246         link.link_speed = ETH_SPEED_NUM_NONE;
4247         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4248         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4249                         ETH_LINK_SPEED_FIXED);
4250
4251         hw->mac.get_link_status = true;
4252
4253         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4254                 return rte_eth_linkstatus_set(dev, &link);
4255
4256         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4257         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4258                 wait = 0;
4259
4260 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4261 #ifdef RTE_EXEC_ENV_FREEBSD
4262         wait = 1;
4263 #endif
4264
4265         if (vf)
4266                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4267         else
4268                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4269
4270         if (diag != 0) {
4271                 link.link_speed = ETH_SPEED_NUM_100M;
4272                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4273                 return rte_eth_linkstatus_set(dev, &link);
4274         }
4275
4276         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4277                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4278                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4279                         link_up = 0;
4280         }
4281
4282         if (link_up == 0) {
4283                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4284                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4285                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4286                                 /* To avoid race condition between threads, set
4287                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4288                                  * when there is no link thread running.
4289                                  */
4290                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4291                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4292                                         "ixgbe-link-handler",
4293                                         NULL,
4294                                         ixgbe_dev_setup_link_thread_handler,
4295                                         dev) < 0) {
4296                                         PMD_DRV_LOG(ERR,
4297                                                 "Create link thread failed!");
4298                                         rte_atomic32_clear(&ad->link_thread_running);
4299                                 }
4300                         } else {
4301                                 PMD_DRV_LOG(ERR,
4302                                         "Other link thread is running now!");
4303                         }
4304                 }
4305                 return rte_eth_linkstatus_set(dev, &link);
4306         }
4307
4308         link.link_status = ETH_LINK_UP;
4309         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4310
4311         switch (link_speed) {
4312         default:
4313         case IXGBE_LINK_SPEED_UNKNOWN:
4314                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4315                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4316                         link.link_speed = ETH_SPEED_NUM_10M;
4317                 else
4318                         link.link_speed = ETH_SPEED_NUM_100M;
4319                 break;
4320
4321         case IXGBE_LINK_SPEED_100_FULL:
4322                 link.link_speed = ETH_SPEED_NUM_100M;
4323                 break;
4324
4325         case IXGBE_LINK_SPEED_1GB_FULL:
4326                 link.link_speed = ETH_SPEED_NUM_1G;
4327                 break;
4328
4329         case IXGBE_LINK_SPEED_2_5GB_FULL:
4330                 link.link_speed = ETH_SPEED_NUM_2_5G;
4331                 break;
4332
4333         case IXGBE_LINK_SPEED_5GB_FULL:
4334                 link.link_speed = ETH_SPEED_NUM_5G;
4335                 break;
4336
4337         case IXGBE_LINK_SPEED_10GB_FULL:
4338                 link.link_speed = ETH_SPEED_NUM_10G;
4339                 break;
4340         }
4341
4342         return rte_eth_linkstatus_set(dev, &link);
4343 }
4344
4345 static int
4346 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4347 {
4348         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4349 }
4350
4351 static int
4352 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4353 {
4354         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4355 }
4356
4357 static int
4358 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4359 {
4360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361         uint32_t fctrl;
4362
4363         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4364         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4365         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4366
4367         return 0;
4368 }
4369
4370 static int
4371 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4372 {
4373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4374         uint32_t fctrl;
4375
4376         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4377         fctrl &= (~IXGBE_FCTRL_UPE);
4378         if (dev->data->all_multicast == 1)
4379                 fctrl |= IXGBE_FCTRL_MPE;
4380         else
4381                 fctrl &= (~IXGBE_FCTRL_MPE);
4382         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4383
4384         return 0;
4385 }
4386
4387 static int
4388 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4389 {
4390         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4391         uint32_t fctrl;
4392
4393         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4394         fctrl |= IXGBE_FCTRL_MPE;
4395         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4396
4397         return 0;
4398 }
4399
4400 static int
4401 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4402 {
4403         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4404         uint32_t fctrl;
4405
4406         if (dev->data->promiscuous == 1)
4407                 return 0; /* must remain in all_multicast mode */
4408
4409         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4410         fctrl &= (~IXGBE_FCTRL_MPE);
4411         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4412
4413         return 0;
4414 }
4415
4416 /**
4417  * It clears the interrupt causes and enables the interrupt.
4418  * It will be called once only during nic initialized.
4419  *
4420  * @param dev
4421  *  Pointer to struct rte_eth_dev.
4422  * @param on
4423  *  Enable or Disable.
4424  *
4425  * @return
4426  *  - On success, zero.
4427  *  - On failure, a negative value.
4428  */
4429 static int
4430 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4431 {
4432         struct ixgbe_interrupt *intr =
4433                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4434
4435         ixgbe_dev_link_status_print(dev);
4436         if (on)
4437                 intr->mask |= IXGBE_EICR_LSC;
4438         else
4439                 intr->mask &= ~IXGBE_EICR_LSC;
4440
4441         return 0;
4442 }
4443
4444 /**
4445  * It clears the interrupt causes and enables the interrupt.
4446  * It will be called once only during nic initialized.
4447  *
4448  * @param dev
4449  *  Pointer to struct rte_eth_dev.
4450  *
4451  * @return
4452  *  - On success, zero.
4453  *  - On failure, a negative value.
4454  */
4455 static int
4456 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4457 {
4458         struct ixgbe_interrupt *intr =
4459                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4460
4461         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4462
4463         return 0;
4464 }
4465
4466 /**
4467  * It clears the interrupt causes and enables the interrupt.
4468  * It will be called once only during nic initialized.
4469  *
4470  * @param dev
4471  *  Pointer to struct rte_eth_dev.
4472  *
4473  * @return
4474  *  - On success, zero.
4475  *  - On failure, a negative value.
4476  */
4477 static int
4478 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4479 {
4480         struct ixgbe_interrupt *intr =
4481                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4482
4483         intr->mask |= IXGBE_EICR_LINKSEC;
4484
4485         return 0;
4486 }
4487
4488 /*
4489  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4490  *
4491  * @param dev
4492  *  Pointer to struct rte_eth_dev.
4493  *
4494  * @return
4495  *  - On success, zero.
4496  *  - On failure, a negative value.
4497  */
4498 static int
4499 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4500 {
4501         uint32_t eicr;
4502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4503         struct ixgbe_interrupt *intr =
4504                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4505
4506         /* clear all cause mask */
4507         ixgbe_disable_intr(hw);
4508
4509         /* read-on-clear nic registers here */
4510         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4511         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4512
4513         intr->flags = 0;
4514
4515         /* set flag for async link update */
4516         if (eicr & IXGBE_EICR_LSC)
4517                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4518
4519         if (eicr & IXGBE_EICR_MAILBOX)
4520                 intr->flags |= IXGBE_FLAG_MAILBOX;
4521
4522         if (eicr & IXGBE_EICR_LINKSEC)
4523                 intr->flags |= IXGBE_FLAG_MACSEC;
4524
4525         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4526             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4527             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4528                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4529
4530         return 0;
4531 }
4532
4533 /**
4534  * It gets and then prints the link status.
4535  *
4536  * @param dev
4537  *  Pointer to struct rte_eth_dev.
4538  *
4539  * @return
4540  *  - On success, zero.
4541  *  - On failure, a negative value.
4542  */
4543 static void
4544 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4545 {
4546         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4547         struct rte_eth_link link;
4548
4549         rte_eth_linkstatus_get(dev, &link);
4550
4551         if (link.link_status) {
4552                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4553                                         (int)(dev->data->port_id),
4554                                         (unsigned)link.link_speed,
4555                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4556                                         "full-duplex" : "half-duplex");
4557         } else {
4558                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4559                                 (int)(dev->data->port_id));
4560         }
4561         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4562                                 pci_dev->addr.domain,
4563                                 pci_dev->addr.bus,
4564                                 pci_dev->addr.devid,
4565                                 pci_dev->addr.function);
4566 }
4567
4568 /*
4569  * It executes link_update after knowing an interrupt occurred.
4570  *
4571  * @param dev
4572  *  Pointer to struct rte_eth_dev.
4573  *
4574  * @return
4575  *  - On success, zero.
4576  *  - On failure, a negative value.
4577  */
4578 static int
4579 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4580 {
4581         struct ixgbe_interrupt *intr =
4582                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4583         int64_t timeout;
4584         struct ixgbe_hw *hw =
4585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4586
4587         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4588
4589         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4590                 ixgbe_pf_mbx_process(dev);
4591                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4592         }
4593
4594         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4595                 ixgbe_handle_lasi(hw);
4596                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4597         }
4598
4599         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4600                 struct rte_eth_link link;
4601
4602                 /* get the link status before link update, for predicting later */
4603                 rte_eth_linkstatus_get(dev, &link);
4604
4605                 ixgbe_dev_link_update(dev, 0);
4606
4607                 /* likely to up */
4608                 if (!link.link_status)
4609                         /* handle it 1 sec later, wait it being stable */
4610                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4611                 /* likely to down */
4612                 else
4613                         /* handle it 4 sec later, wait it being stable */
4614                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4615
4616                 ixgbe_dev_link_status_print(dev);
4617                 if (rte_eal_alarm_set(timeout * 1000,
4618                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4619                         PMD_DRV_LOG(ERR, "Error setting alarm");
4620                 else {
4621                         /* remember original mask */
4622                         intr->mask_original = intr->mask;
4623                         /* only disable lsc interrupt */
4624                         intr->mask &= ~IXGBE_EIMS_LSC;
4625                 }
4626         }
4627
4628         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4629         ixgbe_enable_intr(dev);
4630
4631         return 0;
4632 }
4633
4634 /**
4635  * Interrupt handler which shall be registered for alarm callback for delayed
4636  * handling specific interrupt to wait for the stable nic state. As the
4637  * NIC interrupt state is not stable for ixgbe after link is just down,
4638  * it needs to wait 4 seconds to get the stable status.
4639  *
4640  * @param handle
4641  *  Pointer to interrupt handle.
4642  * @param param
4643  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4644  *
4645  * @return
4646  *  void
4647  */
4648 static void
4649 ixgbe_dev_interrupt_delayed_handler(void *param)
4650 {
4651         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4652         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4653         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4654         struct ixgbe_interrupt *intr =
4655                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4656         struct ixgbe_hw *hw =
4657                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658         uint32_t eicr;
4659
4660         ixgbe_disable_intr(hw);
4661
4662         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4663         if (eicr & IXGBE_EICR_MAILBOX)
4664                 ixgbe_pf_mbx_process(dev);
4665
4666         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4667                 ixgbe_handle_lasi(hw);
4668                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4669         }
4670
4671         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4672                 ixgbe_dev_link_update(dev, 0);
4673                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4674                 ixgbe_dev_link_status_print(dev);
4675                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4676                                               NULL);
4677         }
4678
4679         if (intr->flags & IXGBE_FLAG_MACSEC) {
4680                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4681                                               NULL);
4682                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4683         }
4684
4685         /* restore original mask */
4686         intr->mask = intr->mask_original;
4687         intr->mask_original = 0;
4688
4689         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4690         ixgbe_enable_intr(dev);
4691         rte_intr_ack(intr_handle);
4692 }
4693
4694 /**
4695  * Interrupt handler triggered by NIC  for handling
4696  * specific interrupt.
4697  *
4698  * @param handle
4699  *  Pointer to interrupt handle.
4700  * @param param
4701  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4702  *
4703  * @return
4704  *  void
4705  */
4706 static void
4707 ixgbe_dev_interrupt_handler(void *param)
4708 {
4709         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4710
4711         ixgbe_dev_interrupt_get_status(dev);
4712         ixgbe_dev_interrupt_action(dev);
4713 }
4714
4715 static int
4716 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4717 {
4718         struct ixgbe_hw *hw;
4719
4720         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4721         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4722 }
4723
4724 static int
4725 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4726 {
4727         struct ixgbe_hw *hw;
4728
4729         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4730         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4731 }
4732
4733 static int
4734 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4735 {
4736         struct ixgbe_hw *hw;
4737         uint32_t mflcn_reg;
4738         uint32_t fccfg_reg;
4739         int rx_pause;
4740         int tx_pause;
4741
4742         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4743
4744         fc_conf->pause_time = hw->fc.pause_time;
4745         fc_conf->high_water = hw->fc.high_water[0];
4746         fc_conf->low_water = hw->fc.low_water[0];
4747         fc_conf->send_xon = hw->fc.send_xon;
4748         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4749
4750         /*
4751          * Return rx_pause status according to actual setting of
4752          * MFLCN register.
4753          */
4754         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4755         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4756                 rx_pause = 1;
4757         else
4758                 rx_pause = 0;
4759
4760         /*
4761          * Return tx_pause status according to actual setting of
4762          * FCCFG register.
4763          */
4764         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4765         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4766                 tx_pause = 1;
4767         else
4768                 tx_pause = 0;
4769
4770         if (rx_pause && tx_pause)
4771                 fc_conf->mode = RTE_FC_FULL;
4772         else if (rx_pause)
4773                 fc_conf->mode = RTE_FC_RX_PAUSE;
4774         else if (tx_pause)
4775                 fc_conf->mode = RTE_FC_TX_PAUSE;
4776         else
4777                 fc_conf->mode = RTE_FC_NONE;
4778
4779         return 0;
4780 }
4781
4782 static int
4783 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4784 {
4785         struct ixgbe_hw *hw;
4786         struct ixgbe_adapter *adapter = dev->data->dev_private;
4787         int err;
4788         uint32_t rx_buf_size;
4789         uint32_t max_high_water;
4790         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4791                 ixgbe_fc_none,
4792                 ixgbe_fc_rx_pause,
4793                 ixgbe_fc_tx_pause,
4794                 ixgbe_fc_full
4795         };
4796
4797         PMD_INIT_FUNC_TRACE();
4798
4799         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4801         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4802
4803         /*
4804          * At least reserve one Ethernet frame for watermark
4805          * high_water/low_water in kilo bytes for ixgbe
4806          */
4807         max_high_water = (rx_buf_size -
4808                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4809         if ((fc_conf->high_water > max_high_water) ||
4810                 (fc_conf->high_water < fc_conf->low_water)) {
4811                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4812                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4813                 return -EINVAL;
4814         }
4815
4816         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4817         hw->fc.pause_time     = fc_conf->pause_time;
4818         hw->fc.high_water[0]  = fc_conf->high_water;
4819         hw->fc.low_water[0]   = fc_conf->low_water;
4820         hw->fc.send_xon       = fc_conf->send_xon;
4821         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4822         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4823
4824         err = ixgbe_flow_ctrl_enable(dev, hw);
4825         if (err < 0) {
4826                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4827                 return -EIO;
4828         }
4829         return err;
4830 }
4831
4832 /**
4833  *  ixgbe_pfc_enable_generic - Enable flow control
4834  *  @hw: pointer to hardware structure
4835  *  @tc_num: traffic class number
4836  *  Enable flow control according to the current settings.
4837  */
4838 static int
4839 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4840 {
4841         int ret_val = 0;
4842         uint32_t mflcn_reg, fccfg_reg;
4843         uint32_t reg;
4844         uint32_t fcrtl, fcrth;
4845         uint8_t i;
4846         uint8_t nb_rx_en;
4847
4848         /* Validate the water mark configuration */
4849         if (!hw->fc.pause_time) {
4850                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4851                 goto out;
4852         }
4853
4854         /* Low water mark of zero causes XOFF floods */
4855         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4856                  /* High/Low water can not be 0 */
4857                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4858                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4859                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4860                         goto out;
4861                 }
4862
4863                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4864                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4865                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4866                         goto out;
4867                 }
4868         }
4869         /* Negotiate the fc mode to use */
4870         ixgbe_fc_autoneg(hw);
4871
4872         /* Disable any previous flow control settings */
4873         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4874         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4875
4876         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4877         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4878
4879         switch (hw->fc.current_mode) {
4880         case ixgbe_fc_none:
4881                 /*
4882                  * If the count of enabled RX Priority Flow control >1,
4883                  * and the TX pause can not be disabled
4884                  */
4885                 nb_rx_en = 0;
4886                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4887                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4888                         if (reg & IXGBE_FCRTH_FCEN)
4889                                 nb_rx_en++;
4890                 }
4891                 if (nb_rx_en > 1)
4892                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4893                 break;
4894         case ixgbe_fc_rx_pause:
4895                 /*
4896                  * Rx Flow control is enabled and Tx Flow control is
4897                  * disabled by software override. Since there really
4898                  * isn't a way to advertise that we are capable of RX
4899                  * Pause ONLY, we will advertise that we support both
4900                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4901                  * disable the adapter's ability to send PAUSE frames.
4902                  */
4903                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4904                 /*
4905                  * If the count of enabled RX Priority Flow control >1,
4906                  * and the TX pause can not be disabled
4907                  */
4908                 nb_rx_en = 0;
4909                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4910                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4911                         if (reg & IXGBE_FCRTH_FCEN)
4912                                 nb_rx_en++;
4913                 }
4914                 if (nb_rx_en > 1)
4915                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4916                 break;
4917         case ixgbe_fc_tx_pause:
4918                 /*
4919                  * Tx Flow control is enabled, and Rx Flow control is
4920                  * disabled by software override.
4921                  */
4922                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4923                 break;
4924         case ixgbe_fc_full:
4925                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4926                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4927                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4928                 break;
4929         default:
4930                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4931                 ret_val = IXGBE_ERR_CONFIG;
4932                 goto out;
4933         }
4934
4935         /* Set 802.3x based flow control settings. */
4936         mflcn_reg |= IXGBE_MFLCN_DPF;
4937         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4938         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4939
4940         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4941         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4942                 hw->fc.high_water[tc_num]) {
4943                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4944                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4945                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4946         } else {
4947                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4948                 /*
4949                  * In order to prevent Tx hangs when the internal Tx
4950                  * switch is enabled we must set the high water mark
4951                  * to the maximum FCRTH value.  This allows the Tx
4952                  * switch to function even under heavy Rx workloads.
4953                  */
4954                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4955         }
4956         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4957
4958         /* Configure pause time (2 TCs per register) */
4959         reg = hw->fc.pause_time * 0x00010001;
4960         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4961                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4962
4963         /* Configure flow control refresh threshold value */
4964         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4965
4966 out:
4967         return ret_val;
4968 }
4969
4970 static int
4971 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4972 {
4973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4974         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4975
4976         if (hw->mac.type != ixgbe_mac_82598EB) {
4977                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4978         }
4979         return ret_val;
4980 }
4981
4982 static int
4983 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4984 {
4985         int err;
4986         uint32_t rx_buf_size;
4987         uint32_t max_high_water;
4988         uint8_t tc_num;
4989         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4990         struct ixgbe_hw *hw =
4991                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992         struct ixgbe_dcb_config *dcb_config =
4993                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4994
4995         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4996                 ixgbe_fc_none,
4997                 ixgbe_fc_rx_pause,
4998                 ixgbe_fc_tx_pause,
4999                 ixgbe_fc_full
5000         };
5001
5002         PMD_INIT_FUNC_TRACE();
5003
5004         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
5005         tc_num = map[pfc_conf->priority];
5006         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
5007         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
5008         /*
5009          * At least reserve one Ethernet frame for watermark
5010          * high_water/low_water in kilo bytes for ixgbe
5011          */
5012         max_high_water = (rx_buf_size -
5013                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5014         if ((pfc_conf->fc.high_water > max_high_water) ||
5015             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5016                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5017                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5018                 return -EINVAL;
5019         }
5020
5021         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5022         hw->fc.pause_time = pfc_conf->fc.pause_time;
5023         hw->fc.send_xon = pfc_conf->fc.send_xon;
5024         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5025         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5026
5027         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5028
5029         /* Not negotiated is not an error case */
5030         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5031                 return 0;
5032
5033         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5034         return -EIO;
5035 }
5036
5037 static int
5038 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5039                           struct rte_eth_rss_reta_entry64 *reta_conf,
5040                           uint16_t reta_size)
5041 {
5042         uint16_t i, sp_reta_size;
5043         uint8_t j, mask;
5044         uint32_t reta, r;
5045         uint16_t idx, shift;
5046         struct ixgbe_adapter *adapter = dev->data->dev_private;
5047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5048         uint32_t reta_reg;
5049
5050         PMD_INIT_FUNC_TRACE();
5051
5052         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5053                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5054                         "NIC.");
5055                 return -ENOTSUP;
5056         }
5057
5058         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5059         if (reta_size != sp_reta_size) {
5060                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5061                         "(%d) doesn't match the number hardware can supported "
5062                         "(%d)", reta_size, sp_reta_size);
5063                 return -EINVAL;
5064         }
5065
5066         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5067                 idx = i / RTE_RETA_GROUP_SIZE;
5068                 shift = i % RTE_RETA_GROUP_SIZE;
5069                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5070                                                 IXGBE_4_BIT_MASK);
5071                 if (!mask)
5072                         continue;
5073                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5074                 if (mask == IXGBE_4_BIT_MASK)
5075                         r = 0;
5076                 else
5077                         r = IXGBE_READ_REG(hw, reta_reg);
5078                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5079                         if (mask & (0x1 << j))
5080                                 reta |= reta_conf[idx].reta[shift + j] <<
5081                                                         (CHAR_BIT * j);
5082                         else
5083                                 reta |= r & (IXGBE_8_BIT_MASK <<
5084                                                 (CHAR_BIT * j));
5085                 }
5086                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5087         }
5088         adapter->rss_reta_updated = 1;
5089
5090         return 0;
5091 }
5092
5093 static int
5094 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5095                          struct rte_eth_rss_reta_entry64 *reta_conf,
5096                          uint16_t reta_size)
5097 {
5098         uint16_t i, sp_reta_size;
5099         uint8_t j, mask;
5100         uint32_t reta;
5101         uint16_t idx, shift;
5102         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5103         uint32_t reta_reg;
5104
5105         PMD_INIT_FUNC_TRACE();
5106         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5107         if (reta_size != sp_reta_size) {
5108                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5109                         "(%d) doesn't match the number hardware can supported "
5110                         "(%d)", reta_size, sp_reta_size);
5111                 return -EINVAL;
5112         }
5113
5114         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5115                 idx = i / RTE_RETA_GROUP_SIZE;
5116                 shift = i % RTE_RETA_GROUP_SIZE;
5117                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5118                                                 IXGBE_4_BIT_MASK);
5119                 if (!mask)
5120                         continue;
5121
5122                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5123                 reta = IXGBE_READ_REG(hw, reta_reg);
5124                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5125                         if (mask & (0x1 << j))
5126                                 reta_conf[idx].reta[shift + j] =
5127                                         ((reta >> (CHAR_BIT * j)) &
5128                                                 IXGBE_8_BIT_MASK);
5129                 }
5130         }
5131
5132         return 0;
5133 }
5134
5135 static int
5136 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5137                                 uint32_t index, uint32_t pool)
5138 {
5139         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5140         uint32_t enable_addr = 1;
5141
5142         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5143                              pool, enable_addr);
5144 }
5145
5146 static void
5147 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5148 {
5149         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5150
5151         ixgbe_clear_rar(hw, index);
5152 }
5153
5154 static int
5155 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5156 {
5157         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5158
5159         ixgbe_remove_rar(dev, 0);
5160         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5161
5162         return 0;
5163 }
5164
5165 static bool
5166 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5167 {
5168         if (strcmp(dev->device->driver->name, drv->driver.name))
5169                 return false;
5170
5171         return true;
5172 }
5173
5174 bool
5175 is_ixgbe_supported(struct rte_eth_dev *dev)
5176 {
5177         return is_device_supported(dev, &rte_ixgbe_pmd);
5178 }
5179
5180 static int
5181 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5182 {
5183         uint32_t hlreg0;
5184         uint32_t maxfrs;
5185         struct ixgbe_hw *hw;
5186         struct rte_eth_dev_info dev_info;
5187         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5188         struct rte_eth_dev_data *dev_data = dev->data;
5189         int ret;
5190
5191         ret = ixgbe_dev_info_get(dev, &dev_info);
5192         if (ret != 0)
5193                 return ret;
5194
5195         /* check that mtu is within the allowed range */
5196         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5197                 return -EINVAL;
5198
5199         /* If device is started, refuse mtu that requires the support of
5200          * scattered packets when this feature has not been enabled before.
5201          */
5202         if (dev_data->dev_started && !dev_data->scattered_rx &&
5203             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5204              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5205                 PMD_INIT_LOG(ERR, "Stop port first.");
5206                 return -EINVAL;
5207         }
5208
5209         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5210         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5211
5212         /* switch to jumbo mode if needed */
5213         if (frame_size > RTE_ETHER_MAX_LEN) {
5214                 dev->data->dev_conf.rxmode.offloads |=
5215                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5216                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5217         } else {
5218                 dev->data->dev_conf.rxmode.offloads &=
5219                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5220                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5221         }
5222         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5223
5224         /* update max frame size */
5225         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5226
5227         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5228         maxfrs &= 0x0000FFFF;
5229         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5230         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5231
5232         return 0;
5233 }
5234
5235 /*
5236  * Virtual Function operations
5237  */
5238 static void
5239 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5240 {
5241         struct ixgbe_interrupt *intr =
5242                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5243         struct ixgbe_hw *hw =
5244                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5245
5246         PMD_INIT_FUNC_TRACE();
5247
5248         /* Clear interrupt mask to stop from interrupts being generated */
5249         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5250
5251         IXGBE_WRITE_FLUSH(hw);
5252
5253         /* Clear mask value. */
5254         intr->mask = 0;
5255 }
5256
5257 static void
5258 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5259 {
5260         struct ixgbe_interrupt *intr =
5261                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5262         struct ixgbe_hw *hw =
5263                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5264
5265         PMD_INIT_FUNC_TRACE();
5266
5267         /* VF enable interrupt autoclean */
5268         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5269         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5270         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5271
5272         IXGBE_WRITE_FLUSH(hw);
5273
5274         /* Save IXGBE_VTEIMS value to mask. */
5275         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5276 }
5277
5278 static int
5279 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5280 {
5281         struct rte_eth_conf *conf = &dev->data->dev_conf;
5282         struct ixgbe_adapter *adapter = dev->data->dev_private;
5283
5284         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5285                      dev->data->port_id);
5286
5287         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5288                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5289
5290         /*
5291          * VF has no ability to enable/disable HW CRC
5292          * Keep the persistent behavior the same as Host PF
5293          */
5294 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5295         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5296                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5297                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5298         }
5299 #else
5300         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5301                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5302                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5303         }
5304 #endif
5305
5306         /*
5307          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5308          * allocation or vector Rx preconditions we will reset it.
5309          */
5310         adapter->rx_bulk_alloc_allowed = true;
5311         adapter->rx_vec_allowed = true;
5312
5313         return 0;
5314 }
5315
5316 static int
5317 ixgbevf_dev_start(struct rte_eth_dev *dev)
5318 {
5319         struct ixgbe_hw *hw =
5320                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5321         uint32_t intr_vector = 0;
5322         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5323         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5324
5325         int err, mask = 0;
5326
5327         PMD_INIT_FUNC_TRACE();
5328
5329         /* Stop the link setup handler before resetting the HW. */
5330         ixgbe_dev_wait_setup_link_complete(dev, 0);
5331
5332         err = hw->mac.ops.reset_hw(hw);
5333         if (err) {
5334                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5335                 return err;
5336         }
5337         hw->mac.get_link_status = true;
5338
5339         /* negotiate mailbox API version to use with the PF. */
5340         ixgbevf_negotiate_api(hw);
5341
5342         ixgbevf_dev_tx_init(dev);
5343
5344         /* This can fail when allocating mbufs for descriptor rings */
5345         err = ixgbevf_dev_rx_init(dev);
5346         if (err) {
5347                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5348                 ixgbe_dev_clear_queues(dev);
5349                 return err;
5350         }
5351
5352         /* Set vfta */
5353         ixgbevf_set_vfta_all(dev, 1);
5354
5355         /* Set HW strip */
5356         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5357                 ETH_VLAN_EXTEND_MASK;
5358         err = ixgbevf_vlan_offload_config(dev, mask);
5359         if (err) {
5360                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5361                 ixgbe_dev_clear_queues(dev);
5362                 return err;
5363         }
5364
5365         ixgbevf_dev_rxtx_start(dev);
5366
5367         /* check and configure queue intr-vector mapping */
5368         if (rte_intr_cap_multiple(intr_handle) &&
5369             dev->data->dev_conf.intr_conf.rxq) {
5370                 /* According to datasheet, only vector 0/1/2 can be used,
5371                  * now only one vector is used for Rx queue
5372                  */
5373                 intr_vector = 1;
5374                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5375                         return -1;
5376         }
5377
5378         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5379                 intr_handle->intr_vec =
5380                         rte_zmalloc("intr_vec",
5381                                     dev->data->nb_rx_queues * sizeof(int), 0);
5382                 if (intr_handle->intr_vec == NULL) {
5383                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5384                                      " intr_vec", dev->data->nb_rx_queues);
5385                         return -ENOMEM;
5386                 }
5387         }
5388         ixgbevf_configure_msix(dev);
5389
5390         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5391          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5392          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5393          * is not cleared, it will fail when following rte_intr_enable( ) tries
5394          * to map Rx queue interrupt to other VFIO vectors.
5395          * So clear uio/vfio intr/evevnfd first to avoid failure.
5396          */
5397         rte_intr_disable(intr_handle);
5398
5399         rte_intr_enable(intr_handle);
5400
5401         /* Re-enable interrupt for VF */
5402         ixgbevf_intr_enable(dev);
5403
5404         /*
5405          * Update link status right before return, because it may
5406          * start link configuration process in a separate thread.
5407          */
5408         ixgbevf_dev_link_update(dev, 0);
5409
5410         hw->adapter_stopped = false;
5411
5412         return 0;
5413 }
5414
5415 static void
5416 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5417 {
5418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5419         struct ixgbe_adapter *adapter = dev->data->dev_private;
5420         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5421         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5422
5423         if (hw->adapter_stopped)
5424                 return;
5425
5426         PMD_INIT_FUNC_TRACE();
5427
5428         ixgbe_dev_wait_setup_link_complete(dev, 0);
5429
5430         ixgbevf_intr_disable(dev);
5431
5432         hw->adapter_stopped = 1;
5433         ixgbe_stop_adapter(hw);
5434
5435         /*
5436           * Clear what we set, but we still keep shadow_vfta to
5437           * restore after device starts
5438           */
5439         ixgbevf_set_vfta_all(dev, 0);
5440
5441         /* Clear stored conf */
5442         dev->data->scattered_rx = 0;
5443
5444         ixgbe_dev_clear_queues(dev);
5445
5446         /* Clean datapath event and queue/vec mapping */
5447         rte_intr_efd_disable(intr_handle);
5448         if (intr_handle->intr_vec != NULL) {
5449                 rte_free(intr_handle->intr_vec);
5450                 intr_handle->intr_vec = NULL;
5451         }
5452
5453         adapter->rss_reta_updated = 0;
5454 }
5455
5456 static void
5457 ixgbevf_dev_close(struct rte_eth_dev *dev)
5458 {
5459         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5460         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5461         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5462
5463         PMD_INIT_FUNC_TRACE();
5464
5465         ixgbe_reset_hw(hw);
5466
5467         ixgbevf_dev_stop(dev);
5468
5469         ixgbe_dev_free_queues(dev);
5470
5471         /**
5472          * Remove the VF MAC address ro ensure
5473          * that the VF traffic goes to the PF
5474          * after stop, close and detach of the VF
5475          **/
5476         ixgbevf_remove_mac_addr(dev, 0);
5477
5478         dev->dev_ops = NULL;
5479         dev->rx_pkt_burst = NULL;
5480         dev->tx_pkt_burst = NULL;
5481
5482         rte_intr_disable(intr_handle);
5483         rte_intr_callback_unregister(intr_handle,
5484                                      ixgbevf_dev_interrupt_handler, dev);
5485 }
5486
5487 /*
5488  * Reset VF device
5489  */
5490 static int
5491 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5492 {
5493         int ret;
5494
5495         ret = eth_ixgbevf_dev_uninit(dev);
5496         if (ret)
5497                 return ret;
5498
5499         ret = eth_ixgbevf_dev_init(dev);
5500
5501         return ret;
5502 }
5503
5504 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5505 {
5506         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5507         struct ixgbe_vfta *shadow_vfta =
5508                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5509         int i = 0, j = 0, vfta = 0, mask = 1;
5510
5511         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5512                 vfta = shadow_vfta->vfta[i];
5513                 if (vfta) {
5514                         mask = 1;
5515                         for (j = 0; j < 32; j++) {
5516                                 if (vfta & mask)
5517                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5518                                                        on, false);
5519                                 mask <<= 1;
5520                         }
5521                 }
5522         }
5523
5524 }
5525
5526 static int
5527 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5528 {
5529         struct ixgbe_hw *hw =
5530                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5531         struct ixgbe_vfta *shadow_vfta =
5532                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5533         uint32_t vid_idx = 0;
5534         uint32_t vid_bit = 0;
5535         int ret = 0;
5536
5537         PMD_INIT_FUNC_TRACE();
5538
5539         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5540         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5541         if (ret) {
5542                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5543                 return ret;
5544         }
5545         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5546         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5547
5548         /* Save what we set and retore it after device reset */
5549         if (on)
5550                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5551         else
5552                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5553
5554         return 0;
5555 }
5556
5557 static void
5558 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5559 {
5560         struct ixgbe_hw *hw =
5561                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5562         uint32_t ctrl;
5563
5564         PMD_INIT_FUNC_TRACE();
5565
5566         if (queue >= hw->mac.max_rx_queues)
5567                 return;
5568
5569         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5570         if (on)
5571                 ctrl |= IXGBE_RXDCTL_VME;
5572         else
5573                 ctrl &= ~IXGBE_RXDCTL_VME;
5574         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5575
5576         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5577 }
5578
5579 static int
5580 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5581 {
5582         struct ixgbe_rx_queue *rxq;
5583         uint16_t i;
5584         int on = 0;
5585
5586         /* VF function only support hw strip feature, others are not support */
5587         if (mask & ETH_VLAN_STRIP_MASK) {
5588                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5589                         rxq = dev->data->rx_queues[i];
5590                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5591                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5592                 }
5593         }
5594
5595         return 0;
5596 }
5597
5598 static int
5599 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5600 {
5601         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5602
5603         ixgbevf_vlan_offload_config(dev, mask);
5604
5605         return 0;
5606 }
5607
5608 int
5609 ixgbe_vt_check(struct ixgbe_hw *hw)
5610 {
5611         uint32_t reg_val;
5612
5613         /* if Virtualization Technology is enabled */
5614         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5615         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5616                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5617                 return -1;
5618         }
5619
5620         return 0;
5621 }
5622
5623 static uint32_t
5624 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5625 {
5626         uint32_t vector = 0;
5627
5628         switch (hw->mac.mc_filter_type) {
5629         case 0:   /* use bits [47:36] of the address */
5630                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5631                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5632                 break;
5633         case 1:   /* use bits [46:35] of the address */
5634                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5635                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5636                 break;
5637         case 2:   /* use bits [45:34] of the address */
5638                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5639                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5640                 break;
5641         case 3:   /* use bits [43:32] of the address */
5642                 vector = ((uc_addr->addr_bytes[4]) |
5643                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5644                 break;
5645         default:  /* Invalid mc_filter_type */
5646                 break;
5647         }
5648
5649         /* vector can only be 12-bits or boundary will be exceeded */
5650         vector &= 0xFFF;
5651         return vector;
5652 }
5653
5654 static int
5655 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5656                         struct rte_ether_addr *mac_addr, uint8_t on)
5657 {
5658         uint32_t vector;
5659         uint32_t uta_idx;
5660         uint32_t reg_val;
5661         uint32_t uta_shift;
5662         uint32_t rc;
5663         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5664         const uint32_t ixgbe_uta_bit_shift = 5;
5665         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5666         const uint32_t bit1 = 0x1;
5667
5668         struct ixgbe_hw *hw =
5669                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5670         struct ixgbe_uta_info *uta_info =
5671                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5672
5673         /* The UTA table only exists on 82599 hardware and newer */
5674         if (hw->mac.type < ixgbe_mac_82599EB)
5675                 return -ENOTSUP;
5676
5677         vector = ixgbe_uta_vector(hw, mac_addr);
5678         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5679         uta_shift = vector & ixgbe_uta_bit_mask;
5680
5681         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5682         if (rc == on)
5683                 return 0;
5684
5685         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5686         if (on) {
5687                 uta_info->uta_in_use++;
5688                 reg_val |= (bit1 << uta_shift);
5689                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5690         } else {
5691                 uta_info->uta_in_use--;
5692                 reg_val &= ~(bit1 << uta_shift);
5693                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5694         }
5695
5696         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5697
5698         if (uta_info->uta_in_use > 0)
5699                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5700                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5701         else
5702                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5703
5704         return 0;
5705 }
5706
5707 static int
5708 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5709 {
5710         int i;
5711         struct ixgbe_hw *hw =
5712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5713         struct ixgbe_uta_info *uta_info =
5714                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5715
5716         /* The UTA table only exists on 82599 hardware and newer */
5717         if (hw->mac.type < ixgbe_mac_82599EB)
5718                 return -ENOTSUP;
5719
5720         if (on) {
5721                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5722                         uta_info->uta_shadow[i] = ~0;
5723                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5724                 }
5725         } else {
5726                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5727                         uta_info->uta_shadow[i] = 0;
5728                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5729                 }
5730         }
5731         return 0;
5732
5733 }
5734
5735 uint32_t
5736 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5737 {
5738         uint32_t new_val = orig_val;
5739
5740         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5741                 new_val |= IXGBE_VMOLR_AUPE;
5742         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5743                 new_val |= IXGBE_VMOLR_ROMPE;
5744         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5745                 new_val |= IXGBE_VMOLR_ROPE;
5746         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5747                 new_val |= IXGBE_VMOLR_BAM;
5748         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5749                 new_val |= IXGBE_VMOLR_MPE;
5750
5751         return new_val;
5752 }
5753
5754 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5755 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5756 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5757 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5758 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5759         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5760         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5761
5762 static int
5763 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5764                       struct rte_eth_mirror_conf *mirror_conf,
5765                       uint8_t rule_id, uint8_t on)
5766 {
5767         uint32_t mr_ctl, vlvf;
5768         uint32_t mp_lsb = 0;
5769         uint32_t mv_msb = 0;
5770         uint32_t mv_lsb = 0;
5771         uint32_t mp_msb = 0;
5772         uint8_t i = 0;
5773         int reg_index = 0;
5774         uint64_t vlan_mask = 0;
5775
5776         const uint8_t pool_mask_offset = 32;
5777         const uint8_t vlan_mask_offset = 32;
5778         const uint8_t dst_pool_offset = 8;
5779         const uint8_t rule_mr_offset  = 4;
5780         const uint8_t mirror_rule_mask = 0x0F;
5781
5782         struct ixgbe_mirror_info *mr_info =
5783                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5784         struct ixgbe_hw *hw =
5785                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5786         uint8_t mirror_type = 0;
5787
5788         if (ixgbe_vt_check(hw) < 0)
5789                 return -ENOTSUP;
5790
5791         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5792                 return -EINVAL;
5793
5794         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5795                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5796                             mirror_conf->rule_type);
5797                 return -EINVAL;
5798         }
5799
5800         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5801                 mirror_type |= IXGBE_MRCTL_VLME;
5802                 /* Check if vlan id is valid and find conresponding VLAN ID
5803                  * index in VLVF
5804                  */
5805                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5806                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5807                                 /* search vlan id related pool vlan filter
5808                                  * index
5809                                  */
5810                                 reg_index = ixgbe_find_vlvf_slot(
5811                                                 hw,
5812                                                 mirror_conf->vlan.vlan_id[i],
5813                                                 false);
5814                                 if (reg_index < 0)
5815                                         return -EINVAL;
5816                                 vlvf = IXGBE_READ_REG(hw,
5817                                                       IXGBE_VLVF(reg_index));
5818                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5819                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5820                                       mirror_conf->vlan.vlan_id[i]))
5821                                         vlan_mask |= (1ULL << reg_index);
5822                                 else
5823                                         return -EINVAL;
5824                         }
5825                 }
5826
5827                 if (on) {
5828                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5829                         mv_msb = vlan_mask >> vlan_mask_offset;
5830
5831                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5832                                                 mirror_conf->vlan.vlan_mask;
5833                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5834                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5835                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5836                                                 mirror_conf->vlan.vlan_id[i];
5837                         }
5838                 } else {
5839                         mv_lsb = 0;
5840                         mv_msb = 0;
5841                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5842                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5843                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5844                 }
5845         }
5846
5847         /**
5848          * if enable pool mirror, write related pool mask register,if disable
5849          * pool mirror, clear PFMRVM register
5850          */
5851         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5852                 mirror_type |= IXGBE_MRCTL_VPME;
5853                 if (on) {
5854                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5855                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5856                         mr_info->mr_conf[rule_id].pool_mask =
5857                                         mirror_conf->pool_mask;
5858
5859                 } else {
5860                         mp_lsb = 0;
5861                         mp_msb = 0;
5862                         mr_info->mr_conf[rule_id].pool_mask = 0;
5863                 }
5864         }
5865         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5866                 mirror_type |= IXGBE_MRCTL_UPME;
5867         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5868                 mirror_type |= IXGBE_MRCTL_DPME;
5869
5870         /* read  mirror control register and recalculate it */
5871         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5872
5873         if (on) {
5874                 mr_ctl |= mirror_type;
5875                 mr_ctl &= mirror_rule_mask;
5876                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5877         } else {
5878                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5879         }
5880
5881         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5882         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5883
5884         /* write mirrror control  register */
5885         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5886
5887         /* write pool mirrror control  register */
5888         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5889                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5890                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5891                                 mp_msb);
5892         }
5893         /* write VLAN mirrror control  register */
5894         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5895                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5896                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5897                                 mv_msb);
5898         }
5899
5900         return 0;
5901 }
5902
5903 static int
5904 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5905 {
5906         int mr_ctl = 0;
5907         uint32_t lsb_val = 0;
5908         uint32_t msb_val = 0;
5909         const uint8_t rule_mr_offset = 4;
5910
5911         struct ixgbe_hw *hw =
5912                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5913         struct ixgbe_mirror_info *mr_info =
5914                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5915
5916         if (ixgbe_vt_check(hw) < 0)
5917                 return -ENOTSUP;
5918
5919         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5920                 return -EINVAL;
5921
5922         memset(&mr_info->mr_conf[rule_id], 0,
5923                sizeof(struct rte_eth_mirror_conf));
5924
5925         /* clear PFVMCTL register */
5926         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5927
5928         /* clear pool mask register */
5929         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5930         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5931
5932         /* clear vlan mask register */
5933         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5934         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5935
5936         return 0;
5937 }
5938
5939 static int
5940 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5941 {
5942         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5943         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5944         struct ixgbe_interrupt *intr =
5945                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5946         struct ixgbe_hw *hw =
5947                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948         uint32_t vec = IXGBE_MISC_VEC_ID;
5949
5950         if (rte_intr_allow_others(intr_handle))
5951                 vec = IXGBE_RX_VEC_START;
5952         intr->mask |= (1 << vec);
5953         RTE_SET_USED(queue_id);
5954         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5955
5956         rte_intr_ack(intr_handle);
5957
5958         return 0;
5959 }
5960
5961 static int
5962 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5963 {
5964         struct ixgbe_interrupt *intr =
5965                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5966         struct ixgbe_hw *hw =
5967                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5968         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5969         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5970         uint32_t vec = IXGBE_MISC_VEC_ID;
5971
5972         if (rte_intr_allow_others(intr_handle))
5973                 vec = IXGBE_RX_VEC_START;
5974         intr->mask &= ~(1 << vec);
5975         RTE_SET_USED(queue_id);
5976         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5977
5978         return 0;
5979 }
5980
5981 static int
5982 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5983 {
5984         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5985         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5986         uint32_t mask;
5987         struct ixgbe_hw *hw =
5988                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5989         struct ixgbe_interrupt *intr =
5990                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5991
5992         if (queue_id < 16) {
5993                 ixgbe_disable_intr(hw);
5994                 intr->mask |= (1 << queue_id);
5995                 ixgbe_enable_intr(dev);
5996         } else if (queue_id < 32) {
5997                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5998                 mask &= (1 << queue_id);
5999                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6000         } else if (queue_id < 64) {
6001                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6002                 mask &= (1 << (queue_id - 32));
6003                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6004         }
6005         rte_intr_ack(intr_handle);
6006
6007         return 0;
6008 }
6009
6010 static int
6011 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6012 {
6013         uint32_t mask;
6014         struct ixgbe_hw *hw =
6015                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6016         struct ixgbe_interrupt *intr =
6017                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6018
6019         if (queue_id < 16) {
6020                 ixgbe_disable_intr(hw);
6021                 intr->mask &= ~(1 << queue_id);
6022                 ixgbe_enable_intr(dev);
6023         } else if (queue_id < 32) {
6024                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6025                 mask &= ~(1 << queue_id);
6026                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6027         } else if (queue_id < 64) {
6028                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6029                 mask &= ~(1 << (queue_id - 32));
6030                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6031         }
6032
6033         return 0;
6034 }
6035
6036 static void
6037 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6038                      uint8_t queue, uint8_t msix_vector)
6039 {
6040         uint32_t tmp, idx;
6041
6042         if (direction == -1) {
6043                 /* other causes */
6044                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6045                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6046                 tmp &= ~0xFF;
6047                 tmp |= msix_vector;
6048                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6049         } else {
6050                 /* rx or tx cause */
6051                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6052                 idx = ((16 * (queue & 1)) + (8 * direction));
6053                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6054                 tmp &= ~(0xFF << idx);
6055                 tmp |= (msix_vector << idx);
6056                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6057         }
6058 }
6059
6060 /**
6061  * set the IVAR registers, mapping interrupt causes to vectors
6062  * @param hw
6063  *  pointer to ixgbe_hw struct
6064  * @direction
6065  *  0 for Rx, 1 for Tx, -1 for other causes
6066  * @queue
6067  *  queue to map the corresponding interrupt to
6068  * @msix_vector
6069  *  the vector to map to the corresponding queue
6070  */
6071 static void
6072 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6073                    uint8_t queue, uint8_t msix_vector)
6074 {
6075         uint32_t tmp, idx;
6076
6077         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6078         if (hw->mac.type == ixgbe_mac_82598EB) {
6079                 if (direction == -1)
6080                         direction = 0;
6081                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6082                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6083                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6084                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6085                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6086         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6087                         (hw->mac.type == ixgbe_mac_X540) ||
6088                         (hw->mac.type == ixgbe_mac_X550) ||
6089                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6090                 if (direction == -1) {
6091                         /* other causes */
6092                         idx = ((queue & 1) * 8);
6093                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6094                         tmp &= ~(0xFF << idx);
6095                         tmp |= (msix_vector << idx);
6096                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6097                 } else {
6098                         /* rx or tx causes */
6099                         idx = ((16 * (queue & 1)) + (8 * direction));
6100                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6101                         tmp &= ~(0xFF << idx);
6102                         tmp |= (msix_vector << idx);
6103                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6104                 }
6105         }
6106 }
6107
6108 static void
6109 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6110 {
6111         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6112         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6113         struct ixgbe_hw *hw =
6114                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6115         uint32_t q_idx;
6116         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6117         uint32_t base = IXGBE_MISC_VEC_ID;
6118
6119         /* Configure VF other cause ivar */
6120         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6121
6122         /* won't configure msix register if no mapping is done
6123          * between intr vector and event fd.
6124          */
6125         if (!rte_intr_dp_is_en(intr_handle))
6126                 return;
6127
6128         if (rte_intr_allow_others(intr_handle)) {
6129                 base = IXGBE_RX_VEC_START;
6130                 vector_idx = IXGBE_RX_VEC_START;
6131         }
6132
6133         /* Configure all RX queues of VF */
6134         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6135                 /* Force all queue use vector 0,
6136                  * as IXGBE_VF_MAXMSIVECOTR = 1
6137                  */
6138                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6139                 intr_handle->intr_vec[q_idx] = vector_idx;
6140                 if (vector_idx < base + intr_handle->nb_efd - 1)
6141                         vector_idx++;
6142         }
6143
6144         /* As RX queue setting above show, all queues use the vector 0.
6145          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6146          */
6147         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6148                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6149                         | IXGBE_EITR_CNT_WDIS);
6150 }
6151
6152 /**
6153  * Sets up the hardware to properly generate MSI-X interrupts
6154  * @hw
6155  *  board private structure
6156  */
6157 static void
6158 ixgbe_configure_msix(struct rte_eth_dev *dev)
6159 {
6160         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6161         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6162         struct ixgbe_hw *hw =
6163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6164         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6165         uint32_t vec = IXGBE_MISC_VEC_ID;
6166         uint32_t mask;
6167         uint32_t gpie;
6168
6169         /* won't configure msix register if no mapping is done
6170          * between intr vector and event fd
6171          * but if misx has been enabled already, need to configure
6172          * auto clean, auto mask and throttling.
6173          */
6174         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6175         if (!rte_intr_dp_is_en(intr_handle) &&
6176             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6177                 return;
6178
6179         if (rte_intr_allow_others(intr_handle))
6180                 vec = base = IXGBE_RX_VEC_START;
6181
6182         /* setup GPIE for MSI-x mode */
6183         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6184         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6185                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6186         /* auto clearing and auto setting corresponding bits in EIMS
6187          * when MSI-X interrupt is triggered
6188          */
6189         if (hw->mac.type == ixgbe_mac_82598EB) {
6190                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6191         } else {
6192                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6193                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6194         }
6195         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6196
6197         /* Populate the IVAR table and set the ITR values to the
6198          * corresponding register.
6199          */
6200         if (rte_intr_dp_is_en(intr_handle)) {
6201                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6202                         queue_id++) {
6203                         /* by default, 1:1 mapping */
6204                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6205                         intr_handle->intr_vec[queue_id] = vec;
6206                         if (vec < base + intr_handle->nb_efd - 1)
6207                                 vec++;
6208                 }
6209
6210                 switch (hw->mac.type) {
6211                 case ixgbe_mac_82598EB:
6212                         ixgbe_set_ivar_map(hw, -1,
6213                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6214                                            IXGBE_MISC_VEC_ID);
6215                         break;
6216                 case ixgbe_mac_82599EB:
6217                 case ixgbe_mac_X540:
6218                 case ixgbe_mac_X550:
6219                 case ixgbe_mac_X550EM_x:
6220                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6221                         break;
6222                 default:
6223                         break;
6224                 }
6225         }
6226         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6227                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6228                         | IXGBE_EITR_CNT_WDIS);
6229
6230         /* set up to autoclear timer, and the vectors */
6231         mask = IXGBE_EIMS_ENABLE_MASK;
6232         mask &= ~(IXGBE_EIMS_OTHER |
6233                   IXGBE_EIMS_MAILBOX |
6234                   IXGBE_EIMS_LSC);
6235
6236         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6237 }
6238
6239 int
6240 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6241                            uint16_t queue_idx, uint16_t tx_rate)
6242 {
6243         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6244         struct rte_eth_rxmode *rxmode;
6245         uint32_t rf_dec, rf_int;
6246         uint32_t bcnrc_val;
6247         uint16_t link_speed = dev->data->dev_link.link_speed;
6248
6249         if (queue_idx >= hw->mac.max_tx_queues)
6250                 return -EINVAL;
6251
6252         if (tx_rate != 0) {
6253                 /* Calculate the rate factor values to set */
6254                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6255                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6256                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6257
6258                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6259                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6260                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6261                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6262         } else {
6263                 bcnrc_val = 0;
6264         }
6265
6266         rxmode = &dev->data->dev_conf.rxmode;
6267         /*
6268          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6269          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6270          * set as 0x4.
6271          */
6272         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6273             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6274                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6275                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6276         else
6277                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6278                         IXGBE_MMW_SIZE_DEFAULT);
6279
6280         /* Set RTTBCNRC of queue X */
6281         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6282         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6283         IXGBE_WRITE_FLUSH(hw);
6284
6285         return 0;
6286 }
6287
6288 static int
6289 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6290                      __rte_unused uint32_t index,
6291                      __rte_unused uint32_t pool)
6292 {
6293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6294         int diag;
6295
6296         /*
6297          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6298          * operation. Trap this case to avoid exhausting the [very limited]
6299          * set of PF resources used to store VF MAC addresses.
6300          */
6301         if (memcmp(hw->mac.perm_addr, mac_addr,
6302                         sizeof(struct rte_ether_addr)) == 0)
6303                 return -1;
6304         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6305         if (diag != 0)
6306                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6307                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6308                             mac_addr->addr_bytes[0],
6309                             mac_addr->addr_bytes[1],
6310                             mac_addr->addr_bytes[2],
6311                             mac_addr->addr_bytes[3],
6312                             mac_addr->addr_bytes[4],
6313                             mac_addr->addr_bytes[5],
6314                             diag);
6315         return diag;
6316 }
6317
6318 static void
6319 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6320 {
6321         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6322         struct rte_ether_addr *perm_addr =
6323                 (struct rte_ether_addr *)hw->mac.perm_addr;
6324         struct rte_ether_addr *mac_addr;
6325         uint32_t i;
6326         int diag;
6327
6328         /*
6329          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6330          * not support the deletion of a given MAC address.
6331          * Instead, it imposes to delete all MAC addresses, then to add again
6332          * all MAC addresses with the exception of the one to be deleted.
6333          */
6334         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6335
6336         /*
6337          * Add again all MAC addresses, with the exception of the deleted one
6338          * and of the permanent MAC address.
6339          */
6340         for (i = 0, mac_addr = dev->data->mac_addrs;
6341              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6342                 /* Skip the deleted MAC address */
6343                 if (i == index)
6344                         continue;
6345                 /* Skip NULL MAC addresses */
6346                 if (rte_is_zero_ether_addr(mac_addr))
6347                         continue;
6348                 /* Skip the permanent MAC address */
6349                 if (memcmp(perm_addr, mac_addr,
6350                                 sizeof(struct rte_ether_addr)) == 0)
6351                         continue;
6352                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6353                 if (diag != 0)
6354                         PMD_DRV_LOG(ERR,
6355                                     "Adding again MAC address "
6356                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6357                                     "diag=%d",
6358                                     mac_addr->addr_bytes[0],
6359                                     mac_addr->addr_bytes[1],
6360                                     mac_addr->addr_bytes[2],
6361                                     mac_addr->addr_bytes[3],
6362                                     mac_addr->addr_bytes[4],
6363                                     mac_addr->addr_bytes[5],
6364                                     diag);
6365         }
6366 }
6367
6368 static int
6369 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6370                         struct rte_ether_addr *addr)
6371 {
6372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6373
6374         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6375
6376         return 0;
6377 }
6378
6379 int
6380 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6381                         struct rte_eth_syn_filter *filter,
6382                         bool add)
6383 {
6384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6385         struct ixgbe_filter_info *filter_info =
6386                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6387         uint32_t syn_info;
6388         uint32_t synqf;
6389
6390         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6391                 return -EINVAL;
6392
6393         syn_info = filter_info->syn_info;
6394
6395         if (add) {
6396                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6397                         return -EINVAL;
6398                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6399                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6400
6401                 if (filter->hig_pri)
6402                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6403                 else
6404                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6405         } else {
6406                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6407                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6408                         return -ENOENT;
6409                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6410         }
6411
6412         filter_info->syn_info = synqf;
6413         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6414         IXGBE_WRITE_FLUSH(hw);
6415         return 0;
6416 }
6417
6418 static int
6419 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6420                         struct rte_eth_syn_filter *filter)
6421 {
6422         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6423         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6424
6425         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6426                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6427                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6428                 return 0;
6429         }
6430         return -ENOENT;
6431 }
6432
6433 static int
6434 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6435                         enum rte_filter_op filter_op,
6436                         void *arg)
6437 {
6438         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6439         int ret;
6440
6441         MAC_TYPE_FILTER_SUP(hw->mac.type);
6442
6443         if (filter_op == RTE_ETH_FILTER_NOP)
6444                 return 0;
6445
6446         if (arg == NULL) {
6447                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6448                             filter_op);
6449                 return -EINVAL;
6450         }
6451
6452         switch (filter_op) {
6453         case RTE_ETH_FILTER_ADD:
6454                 ret = ixgbe_syn_filter_set(dev,
6455                                 (struct rte_eth_syn_filter *)arg,
6456                                 TRUE);
6457                 break;
6458         case RTE_ETH_FILTER_DELETE:
6459                 ret = ixgbe_syn_filter_set(dev,
6460                                 (struct rte_eth_syn_filter *)arg,
6461                                 FALSE);
6462                 break;
6463         case RTE_ETH_FILTER_GET:
6464                 ret = ixgbe_syn_filter_get(dev,
6465                                 (struct rte_eth_syn_filter *)arg);
6466                 break;
6467         default:
6468                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6469                 ret = -EINVAL;
6470                 break;
6471         }
6472
6473         return ret;
6474 }
6475
6476
6477 static inline enum ixgbe_5tuple_protocol
6478 convert_protocol_type(uint8_t protocol_value)
6479 {
6480         if (protocol_value == IPPROTO_TCP)
6481                 return IXGBE_FILTER_PROTOCOL_TCP;
6482         else if (protocol_value == IPPROTO_UDP)
6483                 return IXGBE_FILTER_PROTOCOL_UDP;
6484         else if (protocol_value == IPPROTO_SCTP)
6485                 return IXGBE_FILTER_PROTOCOL_SCTP;
6486         else
6487                 return IXGBE_FILTER_PROTOCOL_NONE;
6488 }
6489
6490 /* inject a 5-tuple filter to HW */
6491 static inline void
6492 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6493                            struct ixgbe_5tuple_filter *filter)
6494 {
6495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6496         int i;
6497         uint32_t ftqf, sdpqf;
6498         uint32_t l34timir = 0;
6499         uint8_t mask = 0xff;
6500
6501         i = filter->index;
6502
6503         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6504                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6505         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6506
6507         ftqf = (uint32_t)(filter->filter_info.proto &
6508                 IXGBE_FTQF_PROTOCOL_MASK);
6509         ftqf |= (uint32_t)((filter->filter_info.priority &
6510                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6511         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6512                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6513         if (filter->filter_info.dst_ip_mask == 0)
6514                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6515         if (filter->filter_info.src_port_mask == 0)
6516                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6517         if (filter->filter_info.dst_port_mask == 0)
6518                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6519         if (filter->filter_info.proto_mask == 0)
6520                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6521         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6522         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6523         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6524
6525         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6526         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6527         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6528         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6529
6530         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6531         l34timir |= (uint32_t)(filter->queue <<
6532                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6533         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6534 }
6535
6536 /*
6537  * add a 5tuple filter
6538  *
6539  * @param
6540  * dev: Pointer to struct rte_eth_dev.
6541  * index: the index the filter allocates.
6542  * filter: ponter to the filter that will be added.
6543  * rx_queue: the queue id the filter assigned to.
6544  *
6545  * @return
6546  *    - On success, zero.
6547  *    - On failure, a negative value.
6548  */
6549 static int
6550 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6551                         struct ixgbe_5tuple_filter *filter)
6552 {
6553         struct ixgbe_filter_info *filter_info =
6554                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6555         int i, idx, shift;
6556
6557         /*
6558          * look for an unused 5tuple filter index,
6559          * and insert the filter to list.
6560          */
6561         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6562                 idx = i / (sizeof(uint32_t) * NBBY);
6563                 shift = i % (sizeof(uint32_t) * NBBY);
6564                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6565                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6566                         filter->index = i;
6567                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6568                                           filter,
6569                                           entries);
6570                         break;
6571                 }
6572         }
6573         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6574                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6575                 return -ENOSYS;
6576         }
6577
6578         ixgbe_inject_5tuple_filter(dev, filter);
6579
6580         return 0;
6581 }
6582
6583 /*
6584  * remove a 5tuple filter
6585  *
6586  * @param
6587  * dev: Pointer to struct rte_eth_dev.
6588  * filter: the pointer of the filter will be removed.
6589  */
6590 static void
6591 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6592                         struct ixgbe_5tuple_filter *filter)
6593 {
6594         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6595         struct ixgbe_filter_info *filter_info =
6596                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6597         uint16_t index = filter->index;
6598
6599         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6600                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6601         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6602         rte_free(filter);
6603
6604         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6605         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6606         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6607         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6608         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6609 }
6610
6611 static int
6612 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6613 {
6614         struct ixgbe_hw *hw;
6615         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6616         struct rte_eth_dev_data *dev_data = dev->data;
6617
6618         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6619
6620         if (mtu < RTE_ETHER_MIN_MTU ||
6621                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6622                 return -EINVAL;
6623
6624         /* If device is started, refuse mtu that requires the support of
6625          * scattered packets when this feature has not been enabled before.
6626          */
6627         if (dev_data->dev_started && !dev_data->scattered_rx &&
6628             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6629              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6630                 PMD_INIT_LOG(ERR, "Stop port first.");
6631                 return -EINVAL;
6632         }
6633
6634         /*
6635          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6636          * request of the version 2.0 of the mailbox API.
6637          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6638          * of the mailbox API.
6639          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6640          * prior to 3.11.33 which contains the following change:
6641          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6642          */
6643         ixgbevf_rlpml_set_vf(hw, max_frame);
6644
6645         /* update max frame size */
6646         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6647         return 0;
6648 }
6649
6650 static inline struct ixgbe_5tuple_filter *
6651 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6652                         struct ixgbe_5tuple_filter_info *key)
6653 {
6654         struct ixgbe_5tuple_filter *it;
6655
6656         TAILQ_FOREACH(it, filter_list, entries) {
6657                 if (memcmp(key, &it->filter_info,
6658                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6659                         return it;
6660                 }
6661         }
6662         return NULL;
6663 }
6664
6665 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6666 static inline int
6667 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6668                         struct ixgbe_5tuple_filter_info *filter_info)
6669 {
6670         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6671                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6672                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6673                 return -EINVAL;
6674
6675         switch (filter->dst_ip_mask) {
6676         case UINT32_MAX:
6677                 filter_info->dst_ip_mask = 0;
6678                 filter_info->dst_ip = filter->dst_ip;
6679                 break;
6680         case 0:
6681                 filter_info->dst_ip_mask = 1;
6682                 break;
6683         default:
6684                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6685                 return -EINVAL;
6686         }
6687
6688         switch (filter->src_ip_mask) {
6689         case UINT32_MAX:
6690                 filter_info->src_ip_mask = 0;
6691                 filter_info->src_ip = filter->src_ip;
6692                 break;
6693         case 0:
6694                 filter_info->src_ip_mask = 1;
6695                 break;
6696         default:
6697                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6698                 return -EINVAL;
6699         }
6700
6701         switch (filter->dst_port_mask) {
6702         case UINT16_MAX:
6703                 filter_info->dst_port_mask = 0;
6704                 filter_info->dst_port = filter->dst_port;
6705                 break;
6706         case 0:
6707                 filter_info->dst_port_mask = 1;
6708                 break;
6709         default:
6710                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6711                 return -EINVAL;
6712         }
6713
6714         switch (filter->src_port_mask) {
6715         case UINT16_MAX:
6716                 filter_info->src_port_mask = 0;
6717                 filter_info->src_port = filter->src_port;
6718                 break;
6719         case 0:
6720                 filter_info->src_port_mask = 1;
6721                 break;
6722         default:
6723                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6724                 return -EINVAL;
6725         }
6726
6727         switch (filter->proto_mask) {
6728         case UINT8_MAX:
6729                 filter_info->proto_mask = 0;
6730                 filter_info->proto =
6731                         convert_protocol_type(filter->proto);
6732                 break;
6733         case 0:
6734                 filter_info->proto_mask = 1;
6735                 break;
6736         default:
6737                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6738                 return -EINVAL;
6739         }
6740
6741         filter_info->priority = (uint8_t)filter->priority;
6742         return 0;
6743 }
6744
6745 /*
6746  * add or delete a ntuple filter
6747  *
6748  * @param
6749  * dev: Pointer to struct rte_eth_dev.
6750  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6751  * add: if true, add filter, if false, remove filter
6752  *
6753  * @return
6754  *    - On success, zero.
6755  *    - On failure, a negative value.
6756  */
6757 int
6758 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6759                         struct rte_eth_ntuple_filter *ntuple_filter,
6760                         bool add)
6761 {
6762         struct ixgbe_filter_info *filter_info =
6763                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6764         struct ixgbe_5tuple_filter_info filter_5tuple;
6765         struct ixgbe_5tuple_filter *filter;
6766         int ret;
6767
6768         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6769                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6770                 return -EINVAL;
6771         }
6772
6773         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6774         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6775         if (ret < 0)
6776                 return ret;
6777
6778         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6779                                          &filter_5tuple);
6780         if (filter != NULL && add) {
6781                 PMD_DRV_LOG(ERR, "filter exists.");
6782                 return -EEXIST;
6783         }
6784         if (filter == NULL && !add) {
6785                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6786                 return -ENOENT;
6787         }
6788
6789         if (add) {
6790                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6791                                 sizeof(struct ixgbe_5tuple_filter), 0);
6792                 if (filter == NULL)
6793                         return -ENOMEM;
6794                 rte_memcpy(&filter->filter_info,
6795                                  &filter_5tuple,
6796                                  sizeof(struct ixgbe_5tuple_filter_info));
6797                 filter->queue = ntuple_filter->queue;
6798                 ret = ixgbe_add_5tuple_filter(dev, filter);
6799                 if (ret < 0) {
6800                         rte_free(filter);
6801                         return ret;
6802                 }
6803         } else
6804                 ixgbe_remove_5tuple_filter(dev, filter);
6805
6806         return 0;
6807 }
6808
6809 /*
6810  * get a ntuple filter
6811  *
6812  * @param
6813  * dev: Pointer to struct rte_eth_dev.
6814  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6815  *
6816  * @return
6817  *    - On success, zero.
6818  *    - On failure, a negative value.
6819  */
6820 static int
6821 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6822                         struct rte_eth_ntuple_filter *ntuple_filter)
6823 {
6824         struct ixgbe_filter_info *filter_info =
6825                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6826         struct ixgbe_5tuple_filter_info filter_5tuple;
6827         struct ixgbe_5tuple_filter *filter;
6828         int ret;
6829
6830         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6831                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6832                 return -EINVAL;
6833         }
6834
6835         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6836         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6837         if (ret < 0)
6838                 return ret;
6839
6840         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6841                                          &filter_5tuple);
6842         if (filter == NULL) {
6843                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6844                 return -ENOENT;
6845         }
6846         ntuple_filter->queue = filter->queue;
6847         return 0;
6848 }
6849
6850 /*
6851  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6852  * @dev: pointer to rte_eth_dev structure
6853  * @filter_op:operation will be taken.
6854  * @arg: a pointer to specific structure corresponding to the filter_op
6855  *
6856  * @return
6857  *    - On success, zero.
6858  *    - On failure, a negative value.
6859  */
6860 static int
6861 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6862                                 enum rte_filter_op filter_op,
6863                                 void *arg)
6864 {
6865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6866         int ret;
6867
6868         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6869
6870         if (filter_op == RTE_ETH_FILTER_NOP)
6871                 return 0;
6872
6873         if (arg == NULL) {
6874                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6875                             filter_op);
6876                 return -EINVAL;
6877         }
6878
6879         switch (filter_op) {
6880         case RTE_ETH_FILTER_ADD:
6881                 ret = ixgbe_add_del_ntuple_filter(dev,
6882                         (struct rte_eth_ntuple_filter *)arg,
6883                         TRUE);
6884                 break;
6885         case RTE_ETH_FILTER_DELETE:
6886                 ret = ixgbe_add_del_ntuple_filter(dev,
6887                         (struct rte_eth_ntuple_filter *)arg,
6888                         FALSE);
6889                 break;
6890         case RTE_ETH_FILTER_GET:
6891                 ret = ixgbe_get_ntuple_filter(dev,
6892                         (struct rte_eth_ntuple_filter *)arg);
6893                 break;
6894         default:
6895                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6896                 ret = -EINVAL;
6897                 break;
6898         }
6899         return ret;
6900 }
6901
6902 int
6903 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6904                         struct rte_eth_ethertype_filter *filter,
6905                         bool add)
6906 {
6907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6908         struct ixgbe_filter_info *filter_info =
6909                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6910         uint32_t etqf = 0;
6911         uint32_t etqs = 0;
6912         int ret;
6913         struct ixgbe_ethertype_filter ethertype_filter;
6914
6915         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6916                 return -EINVAL;
6917
6918         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6919                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6920                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6921                         " ethertype filter.", filter->ether_type);
6922                 return -EINVAL;
6923         }
6924
6925         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6926                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6927                 return -EINVAL;
6928         }
6929         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6930                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6931                 return -EINVAL;
6932         }
6933
6934         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6935         if (ret >= 0 && add) {
6936                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6937                             filter->ether_type);
6938                 return -EEXIST;
6939         }
6940         if (ret < 0 && !add) {
6941                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6942                             filter->ether_type);
6943                 return -ENOENT;
6944         }
6945
6946         if (add) {
6947                 etqf = IXGBE_ETQF_FILTER_EN;
6948                 etqf |= (uint32_t)filter->ether_type;
6949                 etqs |= (uint32_t)((filter->queue <<
6950                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6951                                     IXGBE_ETQS_RX_QUEUE);
6952                 etqs |= IXGBE_ETQS_QUEUE_EN;
6953
6954                 ethertype_filter.ethertype = filter->ether_type;
6955                 ethertype_filter.etqf = etqf;
6956                 ethertype_filter.etqs = etqs;
6957                 ethertype_filter.conf = FALSE;
6958                 ret = ixgbe_ethertype_filter_insert(filter_info,
6959                                                     &ethertype_filter);
6960                 if (ret < 0) {
6961                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6962                         return -ENOSPC;
6963                 }
6964         } else {
6965                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6966                 if (ret < 0)
6967                         return -ENOSYS;
6968         }
6969         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6970         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6971         IXGBE_WRITE_FLUSH(hw);
6972
6973         return 0;
6974 }
6975
6976 static int
6977 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6978                         struct rte_eth_ethertype_filter *filter)
6979 {
6980         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981         struct ixgbe_filter_info *filter_info =
6982                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6983         uint32_t etqf, etqs;
6984         int ret;
6985
6986         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6987         if (ret < 0) {
6988                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6989                             filter->ether_type);
6990                 return -ENOENT;
6991         }
6992
6993         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6994         if (etqf & IXGBE_ETQF_FILTER_EN) {
6995                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6996                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6997                 filter->flags = 0;
6998                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6999                                IXGBE_ETQS_RX_QUEUE_SHIFT;
7000                 return 0;
7001         }
7002         return -ENOENT;
7003 }
7004
7005 /*
7006  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
7007  * @dev: pointer to rte_eth_dev structure
7008  * @filter_op:operation will be taken.
7009  * @arg: a pointer to specific structure corresponding to the filter_op
7010  */
7011 static int
7012 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7013                                 enum rte_filter_op filter_op,
7014                                 void *arg)
7015 {
7016         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7017         int ret;
7018
7019         MAC_TYPE_FILTER_SUP(hw->mac.type);
7020
7021         if (filter_op == RTE_ETH_FILTER_NOP)
7022                 return 0;
7023
7024         if (arg == NULL) {
7025                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7026                             filter_op);
7027                 return -EINVAL;
7028         }
7029
7030         switch (filter_op) {
7031         case RTE_ETH_FILTER_ADD:
7032                 ret = ixgbe_add_del_ethertype_filter(dev,
7033                         (struct rte_eth_ethertype_filter *)arg,
7034                         TRUE);
7035                 break;
7036         case RTE_ETH_FILTER_DELETE:
7037                 ret = ixgbe_add_del_ethertype_filter(dev,
7038                         (struct rte_eth_ethertype_filter *)arg,
7039                         FALSE);
7040                 break;
7041         case RTE_ETH_FILTER_GET:
7042                 ret = ixgbe_get_ethertype_filter(dev,
7043                         (struct rte_eth_ethertype_filter *)arg);
7044                 break;
7045         default:
7046                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7047                 ret = -EINVAL;
7048                 break;
7049         }
7050         return ret;
7051 }
7052
7053 static int
7054 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7055                      enum rte_filter_type filter_type,
7056                      enum rte_filter_op filter_op,
7057                      void *arg)
7058 {
7059         int ret = 0;
7060
7061         switch (filter_type) {
7062         case RTE_ETH_FILTER_NTUPLE:
7063                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7064                 break;
7065         case RTE_ETH_FILTER_ETHERTYPE:
7066                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7067                 break;
7068         case RTE_ETH_FILTER_SYN:
7069                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7070                 break;
7071         case RTE_ETH_FILTER_FDIR:
7072                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7073                 break;
7074         case RTE_ETH_FILTER_L2_TUNNEL:
7075                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7076                 break;
7077         case RTE_ETH_FILTER_GENERIC:
7078                 if (filter_op != RTE_ETH_FILTER_GET)
7079                         return -EINVAL;
7080                 *(const void **)arg = &ixgbe_flow_ops;
7081                 break;
7082         default:
7083                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7084                                                         filter_type);
7085                 ret = -EINVAL;
7086                 break;
7087         }
7088
7089         return ret;
7090 }
7091
7092 static u8 *
7093 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7094                         u8 **mc_addr_ptr, u32 *vmdq)
7095 {
7096         u8 *mc_addr;
7097
7098         *vmdq = 0;
7099         mc_addr = *mc_addr_ptr;
7100         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7101         return mc_addr;
7102 }
7103
7104 static int
7105 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7106                           struct rte_ether_addr *mc_addr_set,
7107                           uint32_t nb_mc_addr)
7108 {
7109         struct ixgbe_hw *hw;
7110         u8 *mc_addr_list;
7111
7112         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7113         mc_addr_list = (u8 *)mc_addr_set;
7114         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7115                                          ixgbe_dev_addr_list_itr, TRUE);
7116 }
7117
7118 static uint64_t
7119 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7120 {
7121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122         uint64_t systime_cycles;
7123
7124         switch (hw->mac.type) {
7125         case ixgbe_mac_X550:
7126         case ixgbe_mac_X550EM_x:
7127         case ixgbe_mac_X550EM_a:
7128                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7129                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7130                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7131                                 * NSEC_PER_SEC;
7132                 break;
7133         default:
7134                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7135                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7136                                 << 32;
7137         }
7138
7139         return systime_cycles;
7140 }
7141
7142 static uint64_t
7143 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7144 {
7145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7146         uint64_t rx_tstamp_cycles;
7147
7148         switch (hw->mac.type) {
7149         case ixgbe_mac_X550:
7150         case ixgbe_mac_X550EM_x:
7151         case ixgbe_mac_X550EM_a:
7152                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7153                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7154                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7155                                 * NSEC_PER_SEC;
7156                 break;
7157         default:
7158                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7159                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7160                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7161                                 << 32;
7162         }
7163
7164         return rx_tstamp_cycles;
7165 }
7166
7167 static uint64_t
7168 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7169 {
7170         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7171         uint64_t tx_tstamp_cycles;
7172
7173         switch (hw->mac.type) {
7174         case ixgbe_mac_X550:
7175         case ixgbe_mac_X550EM_x:
7176         case ixgbe_mac_X550EM_a:
7177                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7178                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7179                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7180                                 * NSEC_PER_SEC;
7181                 break;
7182         default:
7183                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7184                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7185                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7186                                 << 32;
7187         }
7188
7189         return tx_tstamp_cycles;
7190 }
7191
7192 static void
7193 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7194 {
7195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7196         struct ixgbe_adapter *adapter = dev->data->dev_private;
7197         struct rte_eth_link link;
7198         uint32_t incval = 0;
7199         uint32_t shift = 0;
7200
7201         /* Get current link speed. */
7202         ixgbe_dev_link_update(dev, 1);
7203         rte_eth_linkstatus_get(dev, &link);
7204
7205         switch (link.link_speed) {
7206         case ETH_SPEED_NUM_100M:
7207                 incval = IXGBE_INCVAL_100;
7208                 shift = IXGBE_INCVAL_SHIFT_100;
7209                 break;
7210         case ETH_SPEED_NUM_1G:
7211                 incval = IXGBE_INCVAL_1GB;
7212                 shift = IXGBE_INCVAL_SHIFT_1GB;
7213                 break;
7214         case ETH_SPEED_NUM_10G:
7215         default:
7216                 incval = IXGBE_INCVAL_10GB;
7217                 shift = IXGBE_INCVAL_SHIFT_10GB;
7218                 break;
7219         }
7220
7221         switch (hw->mac.type) {
7222         case ixgbe_mac_X550:
7223         case ixgbe_mac_X550EM_x:
7224         case ixgbe_mac_X550EM_a:
7225                 /* Independent of link speed. */
7226                 incval = 1;
7227                 /* Cycles read will be interpreted as ns. */
7228                 shift = 0;
7229                 /* Fall-through */
7230         case ixgbe_mac_X540:
7231                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7232                 break;
7233         case ixgbe_mac_82599EB:
7234                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7235                 shift -= IXGBE_INCVAL_SHIFT_82599;
7236                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7237                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7238                 break;
7239         default:
7240                 /* Not supported. */
7241                 return;
7242         }
7243
7244         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7245         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7246         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7247
7248         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7249         adapter->systime_tc.cc_shift = shift;
7250         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7251
7252         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7253         adapter->rx_tstamp_tc.cc_shift = shift;
7254         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7255
7256         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7257         adapter->tx_tstamp_tc.cc_shift = shift;
7258         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7259 }
7260
7261 static int
7262 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7263 {
7264         struct ixgbe_adapter *adapter = dev->data->dev_private;
7265
7266         adapter->systime_tc.nsec += delta;
7267         adapter->rx_tstamp_tc.nsec += delta;
7268         adapter->tx_tstamp_tc.nsec += delta;
7269
7270         return 0;
7271 }
7272
7273 static int
7274 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7275 {
7276         uint64_t ns;
7277         struct ixgbe_adapter *adapter = dev->data->dev_private;
7278
7279         ns = rte_timespec_to_ns(ts);
7280         /* Set the timecounters to a new value. */
7281         adapter->systime_tc.nsec = ns;
7282         adapter->rx_tstamp_tc.nsec = ns;
7283         adapter->tx_tstamp_tc.nsec = ns;
7284
7285         return 0;
7286 }
7287
7288 static int
7289 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7290 {
7291         uint64_t ns, systime_cycles;
7292         struct ixgbe_adapter *adapter = dev->data->dev_private;
7293
7294         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7295         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7296         *ts = rte_ns_to_timespec(ns);
7297
7298         return 0;
7299 }
7300
7301 static int
7302 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7303 {
7304         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7305         uint32_t tsync_ctl;
7306         uint32_t tsauxc;
7307
7308         /* Stop the timesync system time. */
7309         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7310         /* Reset the timesync system time value. */
7311         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7312         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7313
7314         /* Enable system time for platforms where it isn't on by default. */
7315         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7316         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7317         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7318
7319         ixgbe_start_timecounters(dev);
7320
7321         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7322         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7323                         (RTE_ETHER_TYPE_1588 |
7324                          IXGBE_ETQF_FILTER_EN |
7325                          IXGBE_ETQF_1588));
7326
7327         /* Enable timestamping of received PTP packets. */
7328         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7329         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7330         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7331
7332         /* Enable timestamping of transmitted PTP packets. */
7333         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7334         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7335         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7336
7337         IXGBE_WRITE_FLUSH(hw);
7338
7339         return 0;
7340 }
7341
7342 static int
7343 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7344 {
7345         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7346         uint32_t tsync_ctl;
7347
7348         /* Disable timestamping of transmitted PTP packets. */
7349         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7350         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7351         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7352
7353         /* Disable timestamping of received PTP packets. */
7354         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7355         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7356         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7357
7358         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7359         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7360
7361         /* Stop incrementating the System Time registers. */
7362         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7363
7364         return 0;
7365 }
7366
7367 static int
7368 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7369                                  struct timespec *timestamp,
7370                                  uint32_t flags __rte_unused)
7371 {
7372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7373         struct ixgbe_adapter *adapter = dev->data->dev_private;
7374         uint32_t tsync_rxctl;
7375         uint64_t rx_tstamp_cycles;
7376         uint64_t ns;
7377
7378         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7379         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7380                 return -EINVAL;
7381
7382         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7383         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7384         *timestamp = rte_ns_to_timespec(ns);
7385
7386         return  0;
7387 }
7388
7389 static int
7390 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7391                                  struct timespec *timestamp)
7392 {
7393         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7394         struct ixgbe_adapter *adapter = dev->data->dev_private;
7395         uint32_t tsync_txctl;
7396         uint64_t tx_tstamp_cycles;
7397         uint64_t ns;
7398
7399         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7400         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7401                 return -EINVAL;
7402
7403         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7404         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7405         *timestamp = rte_ns_to_timespec(ns);
7406
7407         return 0;
7408 }
7409
7410 static int
7411 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7412 {
7413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7414         int count = 0;
7415         int g_ind = 0;
7416         const struct reg_info *reg_group;
7417         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7418                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7419
7420         while ((reg_group = reg_set[g_ind++]))
7421                 count += ixgbe_regs_group_count(reg_group);
7422
7423         return count;
7424 }
7425
7426 static int
7427 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7428 {
7429         int count = 0;
7430         int g_ind = 0;
7431         const struct reg_info *reg_group;
7432
7433         while ((reg_group = ixgbevf_regs[g_ind++]))
7434                 count += ixgbe_regs_group_count(reg_group);
7435
7436         return count;
7437 }
7438
7439 static int
7440 ixgbe_get_regs(struct rte_eth_dev *dev,
7441               struct rte_dev_reg_info *regs)
7442 {
7443         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7444         uint32_t *data = regs->data;
7445         int g_ind = 0;
7446         int count = 0;
7447         const struct reg_info *reg_group;
7448         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7449                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7450
7451         if (data == NULL) {
7452                 regs->length = ixgbe_get_reg_length(dev);
7453                 regs->width = sizeof(uint32_t);
7454                 return 0;
7455         }
7456
7457         /* Support only full register dump */
7458         if ((regs->length == 0) ||
7459             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7460                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7461                         hw->device_id;
7462                 while ((reg_group = reg_set[g_ind++]))
7463                         count += ixgbe_read_regs_group(dev, &data[count],
7464                                 reg_group);
7465                 return 0;
7466         }
7467
7468         return -ENOTSUP;
7469 }
7470
7471 static int
7472 ixgbevf_get_regs(struct rte_eth_dev *dev,
7473                 struct rte_dev_reg_info *regs)
7474 {
7475         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7476         uint32_t *data = regs->data;
7477         int g_ind = 0;
7478         int count = 0;
7479         const struct reg_info *reg_group;
7480
7481         if (data == NULL) {
7482                 regs->length = ixgbevf_get_reg_length(dev);
7483                 regs->width = sizeof(uint32_t);
7484                 return 0;
7485         }
7486
7487         /* Support only full register dump */
7488         if ((regs->length == 0) ||
7489             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7490                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7491                         hw->device_id;
7492                 while ((reg_group = ixgbevf_regs[g_ind++]))
7493                         count += ixgbe_read_regs_group(dev, &data[count],
7494                                                       reg_group);
7495                 return 0;
7496         }
7497
7498         return -ENOTSUP;
7499 }
7500
7501 static int
7502 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7503 {
7504         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7505
7506         /* Return unit is byte count */
7507         return hw->eeprom.word_size * 2;
7508 }
7509
7510 static int
7511 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7512                 struct rte_dev_eeprom_info *in_eeprom)
7513 {
7514         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7515         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7516         uint16_t *data = in_eeprom->data;
7517         int first, length;
7518
7519         first = in_eeprom->offset >> 1;
7520         length = in_eeprom->length >> 1;
7521         if ((first > hw->eeprom.word_size) ||
7522             ((first + length) > hw->eeprom.word_size))
7523                 return -EINVAL;
7524
7525         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7526
7527         return eeprom->ops.read_buffer(hw, first, length, data);
7528 }
7529
7530 static int
7531 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7532                 struct rte_dev_eeprom_info *in_eeprom)
7533 {
7534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7535         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7536         uint16_t *data = in_eeprom->data;
7537         int first, length;
7538
7539         first = in_eeprom->offset >> 1;
7540         length = in_eeprom->length >> 1;
7541         if ((first > hw->eeprom.word_size) ||
7542             ((first + length) > hw->eeprom.word_size))
7543                 return -EINVAL;
7544
7545         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7546
7547         return eeprom->ops.write_buffer(hw,  first, length, data);
7548 }
7549
7550 static int
7551 ixgbe_get_module_info(struct rte_eth_dev *dev,
7552                       struct rte_eth_dev_module_info *modinfo)
7553 {
7554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7555         uint32_t status;
7556         uint8_t sff8472_rev, addr_mode;
7557         bool page_swap = false;
7558
7559         /* Check whether we support SFF-8472 or not */
7560         status = hw->phy.ops.read_i2c_eeprom(hw,
7561                                              IXGBE_SFF_SFF_8472_COMP,
7562                                              &sff8472_rev);
7563         if (status != 0)
7564                 return -EIO;
7565
7566         /* addressing mode is not supported */
7567         status = hw->phy.ops.read_i2c_eeprom(hw,
7568                                              IXGBE_SFF_SFF_8472_SWAP,
7569                                              &addr_mode);
7570         if (status != 0)
7571                 return -EIO;
7572
7573         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7574                 PMD_DRV_LOG(ERR,
7575                             "Address change required to access page 0xA2, "
7576                             "but not supported. Please report the module "
7577                             "type to the driver maintainers.");
7578                 page_swap = true;
7579         }
7580
7581         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7582                 /* We have a SFP, but it does not support SFF-8472 */
7583                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7584                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7585         } else {
7586                 /* We have a SFP which supports a revision of SFF-8472. */
7587                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7588                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7589         }
7590
7591         return 0;
7592 }
7593
7594 static int
7595 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7596                         struct rte_dev_eeprom_info *info)
7597 {
7598         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7599         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7600         uint8_t databyte = 0xFF;
7601         uint8_t *data = info->data;
7602         uint32_t i = 0;
7603
7604         if (info->length == 0)
7605                 return -EINVAL;
7606
7607         for (i = info->offset; i < info->offset + info->length; i++) {
7608                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7609                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7610                 else
7611                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7612
7613                 if (status != 0)
7614                         return -EIO;
7615
7616                 data[i - info->offset] = databyte;
7617         }
7618
7619         return 0;
7620 }
7621
7622 uint16_t
7623 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7624         switch (mac_type) {
7625         case ixgbe_mac_X550:
7626         case ixgbe_mac_X550EM_x:
7627         case ixgbe_mac_X550EM_a:
7628                 return ETH_RSS_RETA_SIZE_512;
7629         case ixgbe_mac_X550_vf:
7630         case ixgbe_mac_X550EM_x_vf:
7631         case ixgbe_mac_X550EM_a_vf:
7632                 return ETH_RSS_RETA_SIZE_64;
7633         case ixgbe_mac_X540_vf:
7634         case ixgbe_mac_82599_vf:
7635                 return 0;
7636         default:
7637                 return ETH_RSS_RETA_SIZE_128;
7638         }
7639 }
7640
7641 uint32_t
7642 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7643         switch (mac_type) {
7644         case ixgbe_mac_X550:
7645         case ixgbe_mac_X550EM_x:
7646         case ixgbe_mac_X550EM_a:
7647                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7648                         return IXGBE_RETA(reta_idx >> 2);
7649                 else
7650                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7651         case ixgbe_mac_X550_vf:
7652         case ixgbe_mac_X550EM_x_vf:
7653         case ixgbe_mac_X550EM_a_vf:
7654                 return IXGBE_VFRETA(reta_idx >> 2);
7655         default:
7656                 return IXGBE_RETA(reta_idx >> 2);
7657         }
7658 }
7659
7660 uint32_t
7661 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7662         switch (mac_type) {
7663         case ixgbe_mac_X550_vf:
7664         case ixgbe_mac_X550EM_x_vf:
7665         case ixgbe_mac_X550EM_a_vf:
7666                 return IXGBE_VFMRQC;
7667         default:
7668                 return IXGBE_MRQC;
7669         }
7670 }
7671
7672 uint32_t
7673 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7674         switch (mac_type) {
7675         case ixgbe_mac_X550_vf:
7676         case ixgbe_mac_X550EM_x_vf:
7677         case ixgbe_mac_X550EM_a_vf:
7678                 return IXGBE_VFRSSRK(i);
7679         default:
7680                 return IXGBE_RSSRK(i);
7681         }
7682 }
7683
7684 bool
7685 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7686         switch (mac_type) {
7687         case ixgbe_mac_82599_vf:
7688         case ixgbe_mac_X540_vf:
7689                 return 0;
7690         default:
7691                 return 1;
7692         }
7693 }
7694
7695 static int
7696 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7697                         struct rte_eth_dcb_info *dcb_info)
7698 {
7699         struct ixgbe_dcb_config *dcb_config =
7700                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7701         struct ixgbe_dcb_tc_config *tc;
7702         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7703         uint8_t nb_tcs;
7704         uint8_t i, j;
7705
7706         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7707                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7708         else
7709                 dcb_info->nb_tcs = 1;
7710
7711         tc_queue = &dcb_info->tc_queue;
7712         nb_tcs = dcb_info->nb_tcs;
7713
7714         if (dcb_config->vt_mode) { /* vt is enabled*/
7715                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7716                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7717                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7718                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7719                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7720                         for (j = 0; j < nb_tcs; j++) {
7721                                 tc_queue->tc_rxq[0][j].base = j;
7722                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7723                                 tc_queue->tc_txq[0][j].base = j;
7724                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7725                         }
7726                 } else {
7727                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7728                                 for (j = 0; j < nb_tcs; j++) {
7729                                         tc_queue->tc_rxq[i][j].base =
7730                                                 i * nb_tcs + j;
7731                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7732                                         tc_queue->tc_txq[i][j].base =
7733                                                 i * nb_tcs + j;
7734                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7735                                 }
7736                         }
7737                 }
7738         } else { /* vt is disabled*/
7739                 struct rte_eth_dcb_rx_conf *rx_conf =
7740                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7741                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7742                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7743                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7744                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7745                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7746                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7747                         }
7748                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7749                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7750                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7751                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7752                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7753                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7754                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7755                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7756                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7757                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7758                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7759                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7760                         }
7761                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7762                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7763                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7764                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7765                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7766                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7767                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7768                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7769                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7770                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7771                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7772                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7773                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7774                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7775                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7776                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7777                 }
7778         }
7779         for (i = 0; i < dcb_info->nb_tcs; i++) {
7780                 tc = &dcb_config->tc_config[i];
7781                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7782         }
7783         return 0;
7784 }
7785
7786 /* Update e-tag ether type */
7787 static int
7788 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7789                             uint16_t ether_type)
7790 {
7791         uint32_t etag_etype;
7792
7793         if (hw->mac.type != ixgbe_mac_X550 &&
7794             hw->mac.type != ixgbe_mac_X550EM_x &&
7795             hw->mac.type != ixgbe_mac_X550EM_a) {
7796                 return -ENOTSUP;
7797         }
7798
7799         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7800         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7801         etag_etype |= ether_type;
7802         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7803         IXGBE_WRITE_FLUSH(hw);
7804
7805         return 0;
7806 }
7807
7808 /* Config l2 tunnel ether type */
7809 static int
7810 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7811                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7812 {
7813         int ret = 0;
7814         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7815         struct ixgbe_l2_tn_info *l2_tn_info =
7816                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7817
7818         if (l2_tunnel == NULL)
7819                 return -EINVAL;
7820
7821         switch (l2_tunnel->l2_tunnel_type) {
7822         case RTE_L2_TUNNEL_TYPE_E_TAG:
7823                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7824                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7825                 break;
7826         default:
7827                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7828                 ret = -EINVAL;
7829                 break;
7830         }
7831
7832         return ret;
7833 }
7834
7835 /* Enable e-tag tunnel */
7836 static int
7837 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7838 {
7839         uint32_t etag_etype;
7840
7841         if (hw->mac.type != ixgbe_mac_X550 &&
7842             hw->mac.type != ixgbe_mac_X550EM_x &&
7843             hw->mac.type != ixgbe_mac_X550EM_a) {
7844                 return -ENOTSUP;
7845         }
7846
7847         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7848         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7849         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7850         IXGBE_WRITE_FLUSH(hw);
7851
7852         return 0;
7853 }
7854
7855 /* Enable l2 tunnel */
7856 static int
7857 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7858                            enum rte_eth_tunnel_type l2_tunnel_type)
7859 {
7860         int ret = 0;
7861         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7862         struct ixgbe_l2_tn_info *l2_tn_info =
7863                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7864
7865         switch (l2_tunnel_type) {
7866         case RTE_L2_TUNNEL_TYPE_E_TAG:
7867                 l2_tn_info->e_tag_en = TRUE;
7868                 ret = ixgbe_e_tag_enable(hw);
7869                 break;
7870         default:
7871                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7872                 ret = -EINVAL;
7873                 break;
7874         }
7875
7876         return ret;
7877 }
7878
7879 /* Disable e-tag tunnel */
7880 static int
7881 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7882 {
7883         uint32_t etag_etype;
7884
7885         if (hw->mac.type != ixgbe_mac_X550 &&
7886             hw->mac.type != ixgbe_mac_X550EM_x &&
7887             hw->mac.type != ixgbe_mac_X550EM_a) {
7888                 return -ENOTSUP;
7889         }
7890
7891         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7892         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7893         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7894         IXGBE_WRITE_FLUSH(hw);
7895
7896         return 0;
7897 }
7898
7899 /* Disable l2 tunnel */
7900 static int
7901 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7902                             enum rte_eth_tunnel_type l2_tunnel_type)
7903 {
7904         int ret = 0;
7905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7906         struct ixgbe_l2_tn_info *l2_tn_info =
7907                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7908
7909         switch (l2_tunnel_type) {
7910         case RTE_L2_TUNNEL_TYPE_E_TAG:
7911                 l2_tn_info->e_tag_en = FALSE;
7912                 ret = ixgbe_e_tag_disable(hw);
7913                 break;
7914         default:
7915                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7916                 ret = -EINVAL;
7917                 break;
7918         }
7919
7920         return ret;
7921 }
7922
7923 static int
7924 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7925                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7926 {
7927         int ret = 0;
7928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7929         uint32_t i, rar_entries;
7930         uint32_t rar_low, rar_high;
7931
7932         if (hw->mac.type != ixgbe_mac_X550 &&
7933             hw->mac.type != ixgbe_mac_X550EM_x &&
7934             hw->mac.type != ixgbe_mac_X550EM_a) {
7935                 return -ENOTSUP;
7936         }
7937
7938         rar_entries = ixgbe_get_num_rx_addrs(hw);
7939
7940         for (i = 1; i < rar_entries; i++) {
7941                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7942                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7943                 if ((rar_high & IXGBE_RAH_AV) &&
7944                     (rar_high & IXGBE_RAH_ADTYPE) &&
7945                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7946                      l2_tunnel->tunnel_id)) {
7947                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7948                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7949
7950                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7951
7952                         return ret;
7953                 }
7954         }
7955
7956         return ret;
7957 }
7958
7959 static int
7960 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7961                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7962 {
7963         int ret = 0;
7964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7965         uint32_t i, rar_entries;
7966         uint32_t rar_low, rar_high;
7967
7968         if (hw->mac.type != ixgbe_mac_X550 &&
7969             hw->mac.type != ixgbe_mac_X550EM_x &&
7970             hw->mac.type != ixgbe_mac_X550EM_a) {
7971                 return -ENOTSUP;
7972         }
7973
7974         /* One entry for one tunnel. Try to remove potential existing entry. */
7975         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7976
7977         rar_entries = ixgbe_get_num_rx_addrs(hw);
7978
7979         for (i = 1; i < rar_entries; i++) {
7980                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7981                 if (rar_high & IXGBE_RAH_AV) {
7982                         continue;
7983                 } else {
7984                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7985                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7986                         rar_low = l2_tunnel->tunnel_id;
7987
7988                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7989                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7990
7991                         return ret;
7992                 }
7993         }
7994
7995         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7996                      " Please remove a rule before adding a new one.");
7997         return -EINVAL;
7998 }
7999
8000 static inline struct ixgbe_l2_tn_filter *
8001 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
8002                           struct ixgbe_l2_tn_key *key)
8003 {
8004         int ret;
8005
8006         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
8007         if (ret < 0)
8008                 return NULL;
8009
8010         return l2_tn_info->hash_map[ret];
8011 }
8012
8013 static inline int
8014 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8015                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8016 {
8017         int ret;
8018
8019         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8020                                &l2_tn_filter->key);
8021
8022         if (ret < 0) {
8023                 PMD_DRV_LOG(ERR,
8024                             "Failed to insert L2 tunnel filter"
8025                             " to hash table %d!",
8026                             ret);
8027                 return ret;
8028         }
8029
8030         l2_tn_info->hash_map[ret] = l2_tn_filter;
8031
8032         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8033
8034         return 0;
8035 }
8036
8037 static inline int
8038 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8039                           struct ixgbe_l2_tn_key *key)
8040 {
8041         int ret;
8042         struct ixgbe_l2_tn_filter *l2_tn_filter;
8043
8044         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8045
8046         if (ret < 0) {
8047                 PMD_DRV_LOG(ERR,
8048                             "No such L2 tunnel filter to delete %d!",
8049                             ret);
8050                 return ret;
8051         }
8052
8053         l2_tn_filter = l2_tn_info->hash_map[ret];
8054         l2_tn_info->hash_map[ret] = NULL;
8055
8056         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8057         rte_free(l2_tn_filter);
8058
8059         return 0;
8060 }
8061
8062 /* Add l2 tunnel filter */
8063 int
8064 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8065                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8066                                bool restore)
8067 {
8068         int ret;
8069         struct ixgbe_l2_tn_info *l2_tn_info =
8070                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8071         struct ixgbe_l2_tn_key key;
8072         struct ixgbe_l2_tn_filter *node;
8073
8074         if (!restore) {
8075                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8076                 key.tn_id = l2_tunnel->tunnel_id;
8077
8078                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8079
8080                 if (node) {
8081                         PMD_DRV_LOG(ERR,
8082                                     "The L2 tunnel filter already exists!");
8083                         return -EINVAL;
8084                 }
8085
8086                 node = rte_zmalloc("ixgbe_l2_tn",
8087                                    sizeof(struct ixgbe_l2_tn_filter),
8088                                    0);
8089                 if (!node)
8090                         return -ENOMEM;
8091
8092                 rte_memcpy(&node->key,
8093                                  &key,
8094                                  sizeof(struct ixgbe_l2_tn_key));
8095                 node->pool = l2_tunnel->pool;
8096                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8097                 if (ret < 0) {
8098                         rte_free(node);
8099                         return ret;
8100                 }
8101         }
8102
8103         switch (l2_tunnel->l2_tunnel_type) {
8104         case RTE_L2_TUNNEL_TYPE_E_TAG:
8105                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8106                 break;
8107         default:
8108                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8109                 ret = -EINVAL;
8110                 break;
8111         }
8112
8113         if ((!restore) && (ret < 0))
8114                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8115
8116         return ret;
8117 }
8118
8119 /* Delete l2 tunnel filter */
8120 int
8121 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8122                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8123 {
8124         int ret;
8125         struct ixgbe_l2_tn_info *l2_tn_info =
8126                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8127         struct ixgbe_l2_tn_key key;
8128
8129         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8130         key.tn_id = l2_tunnel->tunnel_id;
8131         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8132         if (ret < 0)
8133                 return ret;
8134
8135         switch (l2_tunnel->l2_tunnel_type) {
8136         case RTE_L2_TUNNEL_TYPE_E_TAG:
8137                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8138                 break;
8139         default:
8140                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8141                 ret = -EINVAL;
8142                 break;
8143         }
8144
8145         return ret;
8146 }
8147
8148 /**
8149  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8150  * @dev: pointer to rte_eth_dev structure
8151  * @filter_op:operation will be taken.
8152  * @arg: a pointer to specific structure corresponding to the filter_op
8153  */
8154 static int
8155 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8156                                   enum rte_filter_op filter_op,
8157                                   void *arg)
8158 {
8159         int ret;
8160
8161         if (filter_op == RTE_ETH_FILTER_NOP)
8162                 return 0;
8163
8164         if (arg == NULL) {
8165                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8166                             filter_op);
8167                 return -EINVAL;
8168         }
8169
8170         switch (filter_op) {
8171         case RTE_ETH_FILTER_ADD:
8172                 ret = ixgbe_dev_l2_tunnel_filter_add
8173                         (dev,
8174                          (struct rte_eth_l2_tunnel_conf *)arg,
8175                          FALSE);
8176                 break;
8177         case RTE_ETH_FILTER_DELETE:
8178                 ret = ixgbe_dev_l2_tunnel_filter_del
8179                         (dev,
8180                          (struct rte_eth_l2_tunnel_conf *)arg);
8181                 break;
8182         default:
8183                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8184                 ret = -EINVAL;
8185                 break;
8186         }
8187         return ret;
8188 }
8189
8190 static int
8191 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8192 {
8193         int ret = 0;
8194         uint32_t ctrl;
8195         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8196
8197         if (hw->mac.type != ixgbe_mac_X550 &&
8198             hw->mac.type != ixgbe_mac_X550EM_x &&
8199             hw->mac.type != ixgbe_mac_X550EM_a) {
8200                 return -ENOTSUP;
8201         }
8202
8203         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8204         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8205         if (en)
8206                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8207         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8208
8209         return ret;
8210 }
8211
8212 /* Enable l2 tunnel forwarding */
8213 static int
8214 ixgbe_dev_l2_tunnel_forwarding_enable
8215         (struct rte_eth_dev *dev,
8216          enum rte_eth_tunnel_type l2_tunnel_type)
8217 {
8218         struct ixgbe_l2_tn_info *l2_tn_info =
8219                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8220         int ret = 0;
8221
8222         switch (l2_tunnel_type) {
8223         case RTE_L2_TUNNEL_TYPE_E_TAG:
8224                 l2_tn_info->e_tag_fwd_en = TRUE;
8225                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8226                 break;
8227         default:
8228                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8229                 ret = -EINVAL;
8230                 break;
8231         }
8232
8233         return ret;
8234 }
8235
8236 /* Disable l2 tunnel forwarding */
8237 static int
8238 ixgbe_dev_l2_tunnel_forwarding_disable
8239         (struct rte_eth_dev *dev,
8240          enum rte_eth_tunnel_type l2_tunnel_type)
8241 {
8242         struct ixgbe_l2_tn_info *l2_tn_info =
8243                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8244         int ret = 0;
8245
8246         switch (l2_tunnel_type) {
8247         case RTE_L2_TUNNEL_TYPE_E_TAG:
8248                 l2_tn_info->e_tag_fwd_en = FALSE;
8249                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8250                 break;
8251         default:
8252                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8253                 ret = -EINVAL;
8254                 break;
8255         }
8256
8257         return ret;
8258 }
8259
8260 static int
8261 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8262                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8263                              bool en)
8264 {
8265         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8266         int ret = 0;
8267         uint32_t vmtir, vmvir;
8268         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8269
8270         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8271                 PMD_DRV_LOG(ERR,
8272                             "VF id %u should be less than %u",
8273                             l2_tunnel->vf_id,
8274                             pci_dev->max_vfs);
8275                 return -EINVAL;
8276         }
8277
8278         if (hw->mac.type != ixgbe_mac_X550 &&
8279             hw->mac.type != ixgbe_mac_X550EM_x &&
8280             hw->mac.type != ixgbe_mac_X550EM_a) {
8281                 return -ENOTSUP;
8282         }
8283
8284         if (en)
8285                 vmtir = l2_tunnel->tunnel_id;
8286         else
8287                 vmtir = 0;
8288
8289         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8290
8291         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8292         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8293         if (en)
8294                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8295         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8296
8297         return ret;
8298 }
8299
8300 /* Enable l2 tunnel tag insertion */
8301 static int
8302 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8303                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8304 {
8305         int ret = 0;
8306
8307         switch (l2_tunnel->l2_tunnel_type) {
8308         case RTE_L2_TUNNEL_TYPE_E_TAG:
8309                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8310                 break;
8311         default:
8312                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8313                 ret = -EINVAL;
8314                 break;
8315         }
8316
8317         return ret;
8318 }
8319
8320 /* Disable l2 tunnel tag insertion */
8321 static int
8322 ixgbe_dev_l2_tunnel_insertion_disable
8323         (struct rte_eth_dev *dev,
8324          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8325 {
8326         int ret = 0;
8327
8328         switch (l2_tunnel->l2_tunnel_type) {
8329         case RTE_L2_TUNNEL_TYPE_E_TAG:
8330                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8331                 break;
8332         default:
8333                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8334                 ret = -EINVAL;
8335                 break;
8336         }
8337
8338         return ret;
8339 }
8340
8341 static int
8342 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8343                              bool en)
8344 {
8345         int ret = 0;
8346         uint32_t qde;
8347         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8348
8349         if (hw->mac.type != ixgbe_mac_X550 &&
8350             hw->mac.type != ixgbe_mac_X550EM_x &&
8351             hw->mac.type != ixgbe_mac_X550EM_a) {
8352                 return -ENOTSUP;
8353         }
8354
8355         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8356         if (en)
8357                 qde |= IXGBE_QDE_STRIP_TAG;
8358         else
8359                 qde &= ~IXGBE_QDE_STRIP_TAG;
8360         qde &= ~IXGBE_QDE_READ;
8361         qde |= IXGBE_QDE_WRITE;
8362         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8363
8364         return ret;
8365 }
8366
8367 /* Enable l2 tunnel tag stripping */
8368 static int
8369 ixgbe_dev_l2_tunnel_stripping_enable
8370         (struct rte_eth_dev *dev,
8371          enum rte_eth_tunnel_type l2_tunnel_type)
8372 {
8373         int ret = 0;
8374
8375         switch (l2_tunnel_type) {
8376         case RTE_L2_TUNNEL_TYPE_E_TAG:
8377                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8378                 break;
8379         default:
8380                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8381                 ret = -EINVAL;
8382                 break;
8383         }
8384
8385         return ret;
8386 }
8387
8388 /* Disable l2 tunnel tag stripping */
8389 static int
8390 ixgbe_dev_l2_tunnel_stripping_disable
8391         (struct rte_eth_dev *dev,
8392          enum rte_eth_tunnel_type l2_tunnel_type)
8393 {
8394         int ret = 0;
8395
8396         switch (l2_tunnel_type) {
8397         case RTE_L2_TUNNEL_TYPE_E_TAG:
8398                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8399                 break;
8400         default:
8401                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8402                 ret = -EINVAL;
8403                 break;
8404         }
8405
8406         return ret;
8407 }
8408
8409 /* Enable/disable l2 tunnel offload functions */
8410 static int
8411 ixgbe_dev_l2_tunnel_offload_set
8412         (struct rte_eth_dev *dev,
8413          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8414          uint32_t mask,
8415          uint8_t en)
8416 {
8417         int ret = 0;
8418
8419         if (l2_tunnel == NULL)
8420                 return -EINVAL;
8421
8422         ret = -EINVAL;
8423         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8424                 if (en)
8425                         ret = ixgbe_dev_l2_tunnel_enable(
8426                                 dev,
8427                                 l2_tunnel->l2_tunnel_type);
8428                 else
8429                         ret = ixgbe_dev_l2_tunnel_disable(
8430                                 dev,
8431                                 l2_tunnel->l2_tunnel_type);
8432         }
8433
8434         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8435                 if (en)
8436                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8437                                 dev,
8438                                 l2_tunnel);
8439                 else
8440                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8441                                 dev,
8442                                 l2_tunnel);
8443         }
8444
8445         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8446                 if (en)
8447                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8448                                 dev,
8449                                 l2_tunnel->l2_tunnel_type);
8450                 else
8451                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8452                                 dev,
8453                                 l2_tunnel->l2_tunnel_type);
8454         }
8455
8456         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8457                 if (en)
8458                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8459                                 dev,
8460                                 l2_tunnel->l2_tunnel_type);
8461                 else
8462                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8463                                 dev,
8464                                 l2_tunnel->l2_tunnel_type);
8465         }
8466
8467         return ret;
8468 }
8469
8470 static int
8471 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8472                         uint16_t port)
8473 {
8474         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8475         IXGBE_WRITE_FLUSH(hw);
8476
8477         return 0;
8478 }
8479
8480 /* There's only one register for VxLAN UDP port.
8481  * So, we cannot add several ports. Will update it.
8482  */
8483 static int
8484 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8485                      uint16_t port)
8486 {
8487         if (port == 0) {
8488                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8489                 return -EINVAL;
8490         }
8491
8492         return ixgbe_update_vxlan_port(hw, port);
8493 }
8494
8495 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8496  * UDP port, it must have a value.
8497  * So, will reset it to the original value 0.
8498  */
8499 static int
8500 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8501                      uint16_t port)
8502 {
8503         uint16_t cur_port;
8504
8505         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8506
8507         if (cur_port != port) {
8508                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8509                 return -EINVAL;
8510         }
8511
8512         return ixgbe_update_vxlan_port(hw, 0);
8513 }
8514
8515 /* Add UDP tunneling port */
8516 static int
8517 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8518                               struct rte_eth_udp_tunnel *udp_tunnel)
8519 {
8520         int ret = 0;
8521         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8522
8523         if (hw->mac.type != ixgbe_mac_X550 &&
8524             hw->mac.type != ixgbe_mac_X550EM_x &&
8525             hw->mac.type != ixgbe_mac_X550EM_a) {
8526                 return -ENOTSUP;
8527         }
8528
8529         if (udp_tunnel == NULL)
8530                 return -EINVAL;
8531
8532         switch (udp_tunnel->prot_type) {
8533         case RTE_TUNNEL_TYPE_VXLAN:
8534                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8535                 break;
8536
8537         case RTE_TUNNEL_TYPE_GENEVE:
8538         case RTE_TUNNEL_TYPE_TEREDO:
8539                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8540                 ret = -EINVAL;
8541                 break;
8542
8543         default:
8544                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8545                 ret = -EINVAL;
8546                 break;
8547         }
8548
8549         return ret;
8550 }
8551
8552 /* Remove UDP tunneling port */
8553 static int
8554 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8555                               struct rte_eth_udp_tunnel *udp_tunnel)
8556 {
8557         int ret = 0;
8558         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8559
8560         if (hw->mac.type != ixgbe_mac_X550 &&
8561             hw->mac.type != ixgbe_mac_X550EM_x &&
8562             hw->mac.type != ixgbe_mac_X550EM_a) {
8563                 return -ENOTSUP;
8564         }
8565
8566         if (udp_tunnel == NULL)
8567                 return -EINVAL;
8568
8569         switch (udp_tunnel->prot_type) {
8570         case RTE_TUNNEL_TYPE_VXLAN:
8571                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8572                 break;
8573         case RTE_TUNNEL_TYPE_GENEVE:
8574         case RTE_TUNNEL_TYPE_TEREDO:
8575                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8576                 ret = -EINVAL;
8577                 break;
8578         default:
8579                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8580                 ret = -EINVAL;
8581                 break;
8582         }
8583
8584         return ret;
8585 }
8586
8587 static int
8588 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8589 {
8590         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8591         int ret;
8592
8593         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8594         case IXGBE_SUCCESS:
8595                 ret = 0;
8596                 break;
8597         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8598                 ret = -ENOTSUP;
8599                 break;
8600         default:
8601                 ret = -EAGAIN;
8602                 break;
8603         }
8604
8605         return ret;
8606 }
8607
8608 static int
8609 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8610 {
8611         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8612         int ret;
8613
8614         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8615         case IXGBE_SUCCESS:
8616                 ret = 0;
8617                 break;
8618         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8619                 ret = -ENOTSUP;
8620                 break;
8621         default:
8622                 ret = -EAGAIN;
8623                 break;
8624         }
8625
8626         return ret;
8627 }
8628
8629 static int
8630 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8631 {
8632         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8633         int ret;
8634         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8635
8636         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8637         case IXGBE_SUCCESS:
8638                 ret = 0;
8639                 break;
8640         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8641                 ret = -ENOTSUP;
8642                 break;
8643         default:
8644                 ret = -EAGAIN;
8645                 break;
8646         }
8647
8648         return ret;
8649 }
8650
8651 static int
8652 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8653 {
8654         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8655         int ret;
8656
8657         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8658         case IXGBE_SUCCESS:
8659                 ret = 0;
8660                 break;
8661         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8662                 ret = -ENOTSUP;
8663                 break;
8664         default:
8665                 ret = -EAGAIN;
8666                 break;
8667         }
8668
8669         return ret;
8670 }
8671
8672 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8673 {
8674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8675         u32 in_msg = 0;
8676
8677         /* peek the message first */
8678         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8679
8680         /* PF reset VF event */
8681         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8682                 /* dummy mbx read to ack pf */
8683                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8684                         return;
8685                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8686                                               NULL);
8687         }
8688 }
8689
8690 static int
8691 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8692 {
8693         uint32_t eicr;
8694         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8695         struct ixgbe_interrupt *intr =
8696                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8697         ixgbevf_intr_disable(dev);
8698
8699         /* read-on-clear nic registers here */
8700         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8701         intr->flags = 0;
8702
8703         /* only one misc vector supported - mailbox */
8704         eicr &= IXGBE_VTEICR_MASK;
8705         if (eicr == IXGBE_MISC_VEC_ID)
8706                 intr->flags |= IXGBE_FLAG_MAILBOX;
8707
8708         return 0;
8709 }
8710
8711 static int
8712 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8713 {
8714         struct ixgbe_interrupt *intr =
8715                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8716
8717         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8718                 ixgbevf_mbx_process(dev);
8719                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8720         }
8721
8722         ixgbevf_intr_enable(dev);
8723
8724         return 0;
8725 }
8726
8727 static void
8728 ixgbevf_dev_interrupt_handler(void *param)
8729 {
8730         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8731
8732         ixgbevf_dev_interrupt_get_status(dev);
8733         ixgbevf_dev_interrupt_action(dev);
8734 }
8735
8736 /**
8737  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8738  *  @hw: pointer to hardware structure
8739  *
8740  *  Stops the transmit data path and waits for the HW to internally empty
8741  *  the Tx security block
8742  **/
8743 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8744 {
8745 #define IXGBE_MAX_SECTX_POLL 40
8746
8747         int i;
8748         int sectxreg;
8749
8750         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8751         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8752         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8753         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8754                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8755                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8756                         break;
8757                 /* Use interrupt-safe sleep just in case */
8758                 usec_delay(1000);
8759         }
8760
8761         /* For informational purposes only */
8762         if (i >= IXGBE_MAX_SECTX_POLL)
8763                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8764                          "path fully disabled.  Continuing with init.");
8765
8766         return IXGBE_SUCCESS;
8767 }
8768
8769 /**
8770  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8771  *  @hw: pointer to hardware structure
8772  *
8773  *  Enables the transmit data path.
8774  **/
8775 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8776 {
8777         uint32_t sectxreg;
8778
8779         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8780         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8781         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8782         IXGBE_WRITE_FLUSH(hw);
8783
8784         return IXGBE_SUCCESS;
8785 }
8786
8787 /* restore n-tuple filter */
8788 static inline void
8789 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8790 {
8791         struct ixgbe_filter_info *filter_info =
8792                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8793         struct ixgbe_5tuple_filter *node;
8794
8795         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8796                 ixgbe_inject_5tuple_filter(dev, node);
8797         }
8798 }
8799
8800 /* restore ethernet type filter */
8801 static inline void
8802 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8803 {
8804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8805         struct ixgbe_filter_info *filter_info =
8806                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8807         int i;
8808
8809         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8810                 if (filter_info->ethertype_mask & (1 << i)) {
8811                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8812                                         filter_info->ethertype_filters[i].etqf);
8813                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8814                                         filter_info->ethertype_filters[i].etqs);
8815                         IXGBE_WRITE_FLUSH(hw);
8816                 }
8817         }
8818 }
8819
8820 /* restore SYN filter */
8821 static inline void
8822 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8823 {
8824         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8825         struct ixgbe_filter_info *filter_info =
8826                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8827         uint32_t synqf;
8828
8829         synqf = filter_info->syn_info;
8830
8831         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8832                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8833                 IXGBE_WRITE_FLUSH(hw);
8834         }
8835 }
8836
8837 /* restore L2 tunnel filter */
8838 static inline void
8839 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8840 {
8841         struct ixgbe_l2_tn_info *l2_tn_info =
8842                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8843         struct ixgbe_l2_tn_filter *node;
8844         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8845
8846         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8847                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8848                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8849                 l2_tn_conf.pool           = node->pool;
8850                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8851         }
8852 }
8853
8854 /* restore rss filter */
8855 static inline void
8856 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8857 {
8858         struct ixgbe_filter_info *filter_info =
8859                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8860
8861         if (filter_info->rss_info.conf.queue_num)
8862                 ixgbe_config_rss_filter(dev,
8863                         &filter_info->rss_info, TRUE);
8864 }
8865
8866 static int
8867 ixgbe_filter_restore(struct rte_eth_dev *dev)
8868 {
8869         ixgbe_ntuple_filter_restore(dev);
8870         ixgbe_ethertype_filter_restore(dev);
8871         ixgbe_syn_filter_restore(dev);
8872         ixgbe_fdir_filter_restore(dev);
8873         ixgbe_l2_tn_filter_restore(dev);
8874         ixgbe_rss_filter_restore(dev);
8875
8876         return 0;
8877 }
8878
8879 static void
8880 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8881 {
8882         struct ixgbe_l2_tn_info *l2_tn_info =
8883                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8884         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8885
8886         if (l2_tn_info->e_tag_en)
8887                 (void)ixgbe_e_tag_enable(hw);
8888
8889         if (l2_tn_info->e_tag_fwd_en)
8890                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8891
8892         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8893 }
8894
8895 /* remove all the n-tuple filters */
8896 void
8897 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8898 {
8899         struct ixgbe_filter_info *filter_info =
8900                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8901         struct ixgbe_5tuple_filter *p_5tuple;
8902
8903         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8904                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8905 }
8906
8907 /* remove all the ether type filters */
8908 void
8909 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8910 {
8911         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8912         struct ixgbe_filter_info *filter_info =
8913                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8914         int i;
8915
8916         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8917                 if (filter_info->ethertype_mask & (1 << i) &&
8918                     !filter_info->ethertype_filters[i].conf) {
8919                         (void)ixgbe_ethertype_filter_remove(filter_info,
8920                                                             (uint8_t)i);
8921                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8922                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8923                         IXGBE_WRITE_FLUSH(hw);
8924                 }
8925         }
8926 }
8927
8928 /* remove the SYN filter */
8929 void
8930 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8931 {
8932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8933         struct ixgbe_filter_info *filter_info =
8934                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8935
8936         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8937                 filter_info->syn_info = 0;
8938
8939                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8940                 IXGBE_WRITE_FLUSH(hw);
8941         }
8942 }
8943
8944 /* remove all the L2 tunnel filters */
8945 int
8946 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8947 {
8948         struct ixgbe_l2_tn_info *l2_tn_info =
8949                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8950         struct ixgbe_l2_tn_filter *l2_tn_filter;
8951         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8952         int ret = 0;
8953
8954         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8955                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8956                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8957                 l2_tn_conf.pool           = l2_tn_filter->pool;
8958                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8959                 if (ret < 0)
8960                         return ret;
8961         }
8962
8963         return 0;
8964 }
8965
8966 void
8967 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8968                                 struct ixgbe_macsec_setting *macsec_setting)
8969 {
8970         struct ixgbe_macsec_setting *macsec =
8971                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8972
8973         macsec->offload_en = macsec_setting->offload_en;
8974         macsec->encrypt_en = macsec_setting->encrypt_en;
8975         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8976 }
8977
8978 void
8979 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8980 {
8981         struct ixgbe_macsec_setting *macsec =
8982                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8983
8984         macsec->offload_en = 0;
8985         macsec->encrypt_en = 0;
8986         macsec->replayprotect_en = 0;
8987 }
8988
8989 void
8990 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8991                                 struct ixgbe_macsec_setting *macsec_setting)
8992 {
8993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8994         uint32_t ctrl;
8995         uint8_t en = macsec_setting->encrypt_en;
8996         uint8_t rp = macsec_setting->replayprotect_en;
8997
8998         /**
8999          * Workaround:
9000          * As no ixgbe_disable_sec_rx_path equivalent is
9001          * implemented for tx in the base code, and we are
9002          * not allowed to modify the base code in DPDK, so
9003          * just call the hand-written one directly for now.
9004          * The hardware support has been checked by
9005          * ixgbe_disable_sec_rx_path().
9006          */
9007         ixgbe_disable_sec_tx_path_generic(hw);
9008
9009         /* Enable Ethernet CRC (required by MACsec offload) */
9010         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9011         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9012         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9013
9014         /* Enable the TX and RX crypto engines */
9015         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9016         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9017         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9018
9019         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9020         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9021         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9022
9023         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9024         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9025         ctrl |= 0x3;
9026         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9027
9028         /* Enable SA lookup */
9029         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9030         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9031         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9032                      IXGBE_LSECTXCTRL_AUTH;
9033         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9034         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9035         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9036         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9037
9038         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9039         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9040         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9041         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9042         if (rp)
9043                 ctrl |= IXGBE_LSECRXCTRL_RP;
9044         else
9045                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9046         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9047
9048         /* Start the data paths */
9049         ixgbe_enable_sec_rx_path(hw);
9050         /**
9051          * Workaround:
9052          * As no ixgbe_enable_sec_rx_path equivalent is
9053          * implemented for tx in the base code, and we are
9054          * not allowed to modify the base code in DPDK, so
9055          * just call the hand-written one directly for now.
9056          */
9057         ixgbe_enable_sec_tx_path_generic(hw);
9058 }
9059
9060 void
9061 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9062 {
9063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9064         uint32_t ctrl;
9065
9066         /**
9067          * Workaround:
9068          * As no ixgbe_disable_sec_rx_path equivalent is
9069          * implemented for tx in the base code, and we are
9070          * not allowed to modify the base code in DPDK, so
9071          * just call the hand-written one directly for now.
9072          * The hardware support has been checked by
9073          * ixgbe_disable_sec_rx_path().
9074          */
9075         ixgbe_disable_sec_tx_path_generic(hw);
9076
9077         /* Disable the TX and RX crypto engines */
9078         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9079         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9080         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9081
9082         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9083         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9084         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9085
9086         /* Disable SA lookup */
9087         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9088         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9089         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9090         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9091
9092         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9093         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9094         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9095         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9096
9097         /* Start the data paths */
9098         ixgbe_enable_sec_rx_path(hw);
9099         /**
9100          * Workaround:
9101          * As no ixgbe_enable_sec_rx_path equivalent is
9102          * implemented for tx in the base code, and we are
9103          * not allowed to modify the base code in DPDK, so
9104          * just call the hand-written one directly for now.
9105          */
9106         ixgbe_enable_sec_tx_path_generic(hw);
9107 }
9108
9109 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9110 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9111 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9112 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9113 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9114 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9115 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9116                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9117
9118 RTE_INIT(ixgbe_init_log)
9119 {
9120         ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
9121         if (ixgbe_logtype_init >= 0)
9122                 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
9123         ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
9124         if (ixgbe_logtype_driver >= 0)
9125                 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);
9126 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9127         ixgbe_logtype_rx = rte_log_register("pmd.net.ixgbe.rx");
9128         if (ixgbe_logtype_rx >= 0)
9129                 rte_log_set_level(ixgbe_logtype_rx, RTE_LOG_DEBUG);
9130 #endif
9131
9132 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9133         ixgbe_logtype_tx = rte_log_register("pmd.net.ixgbe.tx");
9134         if (ixgbe_logtype_tx >= 0)
9135                 rte_log_set_level(ixgbe_logtype_tx, RTE_LOG_DEBUG);
9136 #endif
9137
9138 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9139         ixgbe_logtype_tx_free = rte_log_register("pmd.net.ixgbe.tx_free");
9140         if (ixgbe_logtype_tx_free >= 0)
9141                 rte_log_set_level(ixgbe_logtype_tx_free, RTE_LOG_DEBUG);
9142 #endif
9143 }