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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
43 /* need update link, bit flag */
44 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
45 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
46 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
47 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
50 * Defines that were not part of ixgbe_type.h as they are not used by the
53 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
54 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
55 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
56 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
57 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
58 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
59 #define IXGBE_NB_STAT_MAPPING_REGS 32
60 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
61 #define IXGBE_VFTA_SIZE 128
62 #define IXGBE_VLAN_TAG_SIZE 4
63 #define IXGBE_MAX_RX_QUEUE_NUM 128
64 #define IXGBE_MAX_INTR_QUEUE_NUM 15
65 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
66 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
67 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
70 #define NBBY 8 /* number of bits in a byte */
72 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
74 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
75 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
76 #define IXGBE_EITR_ITR_INT_SHIFT 3
77 #define IXGBE_EITR_INTERVAL_US(us) \
78 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
79 IXGBE_EITR_ITR_INT_MASK)
82 /* Loopback operation modes */
83 /* 82599 specific loopback operation types */
84 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
85 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
87 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
89 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
90 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
91 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
93 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
95 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
96 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
97 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
98 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
100 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
101 #define IXGBE_ETQF_SHIFT 16
102 #define IXGBE_ETQF_UP_EN 0x00080000
103 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
104 #define IXGBE_ETQF_MAX_PRI 7
106 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
107 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
108 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
110 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
111 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
112 #define IXGBE_L34T_IMIR_LLI 0x00100000
113 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
114 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
115 #define IXGBE_5TUPLE_MAX_PRI 7
116 #define IXGBE_5TUPLE_MIN_PRI 1
118 #define IXGBE_RSS_OFFLOAD_ALL ( \
120 ETH_RSS_NONFRAG_IPV4_TCP | \
121 ETH_RSS_NONFRAG_IPV4_UDP | \
123 ETH_RSS_NONFRAG_IPV6_TCP | \
124 ETH_RSS_NONFRAG_IPV6_UDP | \
126 ETH_RSS_IPV6_TCP_EX | \
129 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
130 #define IXGBE_VF_MAXMSIVECTOR 1
132 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
133 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
135 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
137 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
139 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
140 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
143 * Information about the fdir mode.
145 struct ixgbe_hw_fdir_mask {
146 uint16_t vlan_tci_mask;
147 uint32_t src_ipv4_mask;
148 uint32_t dst_ipv4_mask;
149 uint16_t src_ipv6_mask;
150 uint16_t dst_ipv6_mask;
151 uint16_t src_port_mask;
152 uint16_t dst_port_mask;
153 uint16_t flex_bytes_mask;
154 uint8_t mac_addr_byte_mask;
155 uint32_t tunnel_id_mask;
156 uint8_t tunnel_type_mask;
159 struct ixgbe_fdir_filter {
160 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
161 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
162 uint32_t fdirflags; /* drop or forward */
163 uint32_t fdirhash; /* hash value for fdir */
164 uint8_t queue; /* assigned rx queue */
167 /* list of fdir filters */
168 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
170 struct ixgbe_fdir_rule {
171 struct ixgbe_hw_fdir_mask mask;
172 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
173 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
174 bool b_mask; /* If TRUE, mask has meaning. */
175 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
176 uint32_t fdirflags; /* drop or forward */
177 uint32_t soft_id; /* an unique value for this rule */
178 uint8_t queue; /* assigned rx queue */
181 struct ixgbe_hw_fdir_info {
182 struct ixgbe_hw_fdir_mask mask;
183 uint8_t flex_bytes_offset;
192 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
193 /* store the pointers of the filters, index is the hash value. */
194 struct ixgbe_fdir_filter **hash_map;
195 struct rte_hash *hash_handle; /* cuckoo hash handler */
196 bool mask_added; /* If already got mask from consistent filter */
199 /* structure for interrupt relative data */
200 struct ixgbe_interrupt {
205 struct ixgbe_stat_mapping_registers {
206 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
207 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
211 uint32_t vfta[IXGBE_VFTA_SIZE];
214 struct ixgbe_hwstrip {
215 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
219 * VF data which used by PF host only
221 #define IXGBE_MAX_VF_MC_ENTRIES 30
222 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
223 #define IXGBE_MAX_UTA 128
225 struct ixgbe_uta_info {
226 uint8_t uc_filter_type;
228 uint32_t uta_shadow[IXGBE_MAX_UTA];
231 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
233 struct ixgbe_mirror_info {
234 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
235 /**< store PF mirror rules configuration*/
238 struct ixgbe_vf_info {
239 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
240 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
241 uint16_t num_vf_mc_hashes;
242 uint16_t default_vf_vlan_id;
243 uint16_t vlans_enabled;
245 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
247 uint8_t spoofchk_enabled;
252 * Possible l4type of 5tuple filters.
254 enum ixgbe_5tuple_protocol {
255 IXGBE_FILTER_PROTOCOL_TCP = 0,
256 IXGBE_FILTER_PROTOCOL_UDP,
257 IXGBE_FILTER_PROTOCOL_SCTP,
258 IXGBE_FILTER_PROTOCOL_NONE,
261 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
263 struct ixgbe_5tuple_filter_info {
268 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
269 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
270 used when more than one filter matches. */
271 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
272 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
273 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
274 src_port_mask:1, /* if mask is 1b, do not compare src port. */
275 proto_mask:1; /* if mask is 1b, do not compare protocol. */
278 /* 5tuple filter structure */
279 struct ixgbe_5tuple_filter {
280 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
281 uint16_t index; /* the index of 5tuple filter */
282 struct ixgbe_5tuple_filter_info filter_info;
283 uint16_t queue; /* rx queue assigned to */
286 #define IXGBE_5TUPLE_ARRAY_SIZE \
287 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
288 (sizeof(uint32_t) * NBBY))
290 struct ixgbe_ethertype_filter {
295 * If this filter is added by configuration,
296 * it should not be removed.
302 * Structure to store filters' info.
304 struct ixgbe_filter_info {
305 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
306 /* store used ethertype filters*/
307 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
308 /* Bit mask for every used 5tuple filter */
309 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
310 struct ixgbe_5tuple_filter_list fivetuple_list;
311 /* store the SYN filter info */
315 struct ixgbe_l2_tn_key {
316 enum rte_eth_tunnel_type l2_tn_type;
320 struct ixgbe_l2_tn_filter {
321 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
322 struct ixgbe_l2_tn_key key;
326 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
328 struct ixgbe_l2_tn_info {
329 struct ixgbe_l2_tn_filter_list l2_tn_list;
330 struct ixgbe_l2_tn_filter **hash_map;
331 struct rte_hash *hash_handle;
332 bool e_tag_en; /* e-tag enabled */
333 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
334 bool e_tag_ether_type; /* ether type for e-tag */
338 enum rte_filter_type filter_type;
341 /* ntuple filter list structure */
342 struct ixgbe_ntuple_filter_ele {
343 TAILQ_ENTRY(ixgbe_ntuple_filter_ele) entries;
344 struct rte_eth_ntuple_filter filter_info;
346 /* ethertype filter list structure */
347 struct ixgbe_ethertype_filter_ele {
348 TAILQ_ENTRY(ixgbe_ethertype_filter_ele) entries;
349 struct rte_eth_ethertype_filter filter_info;
351 /* syn filter list structure */
352 struct ixgbe_eth_syn_filter_ele {
353 TAILQ_ENTRY(ixgbe_eth_syn_filter_ele) entries;
354 struct rte_eth_syn_filter filter_info;
356 /* fdir filter list structure */
357 struct ixgbe_fdir_rule_ele {
358 TAILQ_ENTRY(ixgbe_fdir_rule_ele) entries;
359 struct ixgbe_fdir_rule filter_info;
361 /* l2_tunnel filter list structure */
362 struct ixgbe_eth_l2_tunnel_conf_ele {
363 TAILQ_ENTRY(ixgbe_eth_l2_tunnel_conf_ele) entries;
364 struct rte_eth_l2_tunnel_conf filter_info;
366 /* ixgbe_flow memory list structure */
367 struct ixgbe_flow_mem {
368 TAILQ_ENTRY(ixgbe_flow_mem) entries;
369 struct rte_flow *flow;
372 TAILQ_HEAD(ixgbe_ntuple_filter_list, ixgbe_ntuple_filter_ele);
373 struct ixgbe_ntuple_filter_list filter_ntuple_list;
374 TAILQ_HEAD(ixgbe_ethertype_filter_list, ixgbe_ethertype_filter_ele);
375 struct ixgbe_ethertype_filter_list filter_ethertype_list;
376 TAILQ_HEAD(ixgbe_syn_filter_list, ixgbe_eth_syn_filter_ele);
377 struct ixgbe_syn_filter_list filter_syn_list;
378 TAILQ_HEAD(ixgbe_fdir_rule_filter_list, ixgbe_fdir_rule_ele);
379 struct ixgbe_fdir_rule_filter_list filter_fdir_list;
380 TAILQ_HEAD(ixgbe_l2_tunnel_filter_list, ixgbe_eth_l2_tunnel_conf_ele);
381 struct ixgbe_l2_tunnel_filter_list filter_l2_tunnel_list;
382 TAILQ_HEAD(ixgbe_flow_mem_list, ixgbe_flow_mem);
383 struct ixgbe_flow_mem_list ixgbe_flow_list;
386 * Statistics counters collected by the MACsec
388 struct ixgbe_macsec_stats {
389 /* TX port statistics */
390 uint64_t out_pkts_untagged;
391 uint64_t out_pkts_encrypted;
392 uint64_t out_pkts_protected;
393 uint64_t out_octets_encrypted;
394 uint64_t out_octets_protected;
396 /* RX port statistics */
397 uint64_t in_pkts_untagged;
398 uint64_t in_pkts_badtag;
399 uint64_t in_pkts_nosci;
400 uint64_t in_pkts_unknownsci;
401 uint64_t in_octets_decrypted;
402 uint64_t in_octets_validated;
404 /* RX SC statistics */
405 uint64_t in_pkts_unchecked;
406 uint64_t in_pkts_delayed;
407 uint64_t in_pkts_late;
409 /* RX SA statistics */
411 uint64_t in_pkts_invalid;
412 uint64_t in_pkts_notvalid;
413 uint64_t in_pkts_unusedsa;
414 uint64_t in_pkts_notusingsa;
418 * Structure to store private data for each driver instance (for each port).
420 struct ixgbe_adapter {
422 struct ixgbe_hw_stats stats;
423 struct ixgbe_macsec_stats macsec_stats;
424 struct ixgbe_hw_fdir_info fdir;
425 struct ixgbe_interrupt intr;
426 struct ixgbe_stat_mapping_registers stat_mappings;
427 struct ixgbe_vfta shadow_vfta;
428 struct ixgbe_hwstrip hwstrip;
429 struct ixgbe_dcb_config dcb_config;
430 struct ixgbe_mirror_info mr_data;
431 struct ixgbe_vf_info *vfdata;
432 struct ixgbe_uta_info uta_info;
433 #ifdef RTE_NIC_BYPASS
434 struct ixgbe_bypass_info bps;
435 #endif /* RTE_NIC_BYPASS */
436 struct ixgbe_filter_info filter;
437 struct ixgbe_l2_tn_info l2_tn;
439 bool rx_bulk_alloc_allowed;
441 struct rte_timecounter systime_tc;
442 struct rte_timecounter rx_tstamp_tc;
443 struct rte_timecounter tx_tstamp_tc;
446 #define IXGBE_DEV_TO_PCI(eth_dev) \
447 RTE_DEV_TO_PCI((eth_dev)->device)
449 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
450 (&((struct ixgbe_adapter *)adapter)->hw)
452 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
453 (&((struct ixgbe_adapter *)adapter)->stats)
455 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
456 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
458 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
459 (&((struct ixgbe_adapter *)adapter)->intr)
461 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
462 (&((struct ixgbe_adapter *)adapter)->fdir)
464 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
465 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
467 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
468 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
470 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
471 (&((struct ixgbe_adapter *)adapter)->hwstrip)
473 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
474 (&((struct ixgbe_adapter *)adapter)->dcb_config)
476 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
477 (&((struct ixgbe_adapter *)adapter)->vfdata)
479 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
480 (&((struct ixgbe_adapter *)adapter)->mr_data)
482 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
483 (&((struct ixgbe_adapter *)adapter)->uta_info)
485 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
486 (&((struct ixgbe_adapter *)adapter)->filter)
488 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
489 (&((struct ixgbe_adapter *)adapter)->l2_tn)
492 * RX/TX function prototypes
494 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
496 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
498 void ixgbe_dev_rx_queue_release(void *rxq);
500 void ixgbe_dev_tx_queue_release(void *txq);
502 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
503 uint16_t nb_rx_desc, unsigned int socket_id,
504 const struct rte_eth_rxconf *rx_conf,
505 struct rte_mempool *mb_pool);
507 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
508 uint16_t nb_tx_desc, unsigned int socket_id,
509 const struct rte_eth_txconf *tx_conf);
511 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
512 uint16_t rx_queue_id);
514 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
515 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
517 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
519 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
521 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
523 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
525 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
527 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
529 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
531 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
532 struct rte_eth_rxq_info *qinfo);
534 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
535 struct rte_eth_txq_info *qinfo);
537 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
539 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
541 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
543 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
546 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
549 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
550 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
551 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
552 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
554 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
557 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
560 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
563 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
564 struct rte_eth_rss_conf *rss_conf);
566 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
567 struct rte_eth_rss_conf *rss_conf);
569 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
571 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
573 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
575 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
577 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
579 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
580 struct rte_eth_ntuple_filter *filter,
582 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
583 struct rte_eth_ethertype_filter *filter,
585 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
586 struct rte_eth_syn_filter *filter,
589 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
590 struct rte_eth_l2_tunnel_conf *l2_tunnel,
593 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
594 struct rte_eth_l2_tunnel_conf *l2_tunnel);
596 * Flow director function prototypes
598 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
599 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
600 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
601 struct ixgbe_fdir_rule *rule,
602 bool del, bool update);
604 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
607 * misc function prototypes
609 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
611 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
613 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
615 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
617 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
619 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
621 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
623 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
625 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
627 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
628 enum rte_filter_op filter_op, void *arg);
629 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
630 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
632 extern const struct rte_flow_ops ixgbe_flow_ops;
634 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
635 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
636 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
637 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
639 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
641 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
644 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
649 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
650 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
651 (filter_info->ethertype_mask & (1 << i)))
658 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
659 struct ixgbe_ethertype_filter *ethertype_filter)
663 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
664 if (!(filter_info->ethertype_mask & (1 << i))) {
665 filter_info->ethertype_mask |= 1 << i;
666 filter_info->ethertype_filters[i].ethertype =
667 ethertype_filter->ethertype;
668 filter_info->ethertype_filters[i].etqf =
669 ethertype_filter->etqf;
670 filter_info->ethertype_filters[i].etqs =
671 ethertype_filter->etqs;
672 filter_info->ethertype_filters[i].conf =
673 ethertype_filter->conf;
681 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
684 if (idx >= IXGBE_MAX_ETQF_FILTERS)
686 filter_info->ethertype_mask &= ~(1 << idx);
687 filter_info->ethertype_filters[idx].ethertype = 0;
688 filter_info->ethertype_filters[idx].etqf = 0;
689 filter_info->ethertype_filters[idx].etqs = 0;
690 filter_info->ethertype_filters[idx].etqs = FALSE;
694 #endif /* _IXGBE_ETHDEV_H_ */