4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
43 /* need update link, bit flag */
44 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
45 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
46 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
47 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
48 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
51 * Defines that were not part of ixgbe_type.h as they are not used by the
54 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
55 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
56 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
57 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
58 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
59 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
60 #define IXGBE_NB_STAT_MAPPING_REGS 32
61 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
62 #define IXGBE_VFTA_SIZE 128
63 #define IXGBE_VLAN_TAG_SIZE 4
64 #define IXGBE_MAX_RX_QUEUE_NUM 128
65 #define IXGBE_MAX_INTR_QUEUE_NUM 15
66 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
67 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
68 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
71 #define NBBY 8 /* number of bits in a byte */
73 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
75 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
76 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
77 #define IXGBE_EITR_ITR_INT_SHIFT 3
78 #define IXGBE_EITR_INTERVAL_US(us) \
79 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
80 IXGBE_EITR_ITR_INT_MASK)
83 /* Loopback operation modes */
84 /* 82599 specific loopback operation types */
85 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
86 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
88 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
90 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
91 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
92 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
94 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
96 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
97 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
98 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
99 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
101 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
102 #define IXGBE_ETQF_SHIFT 16
103 #define IXGBE_ETQF_UP_EN 0x00080000
104 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
105 #define IXGBE_ETQF_MAX_PRI 7
107 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
108 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
109 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
111 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
112 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
113 #define IXGBE_L34T_IMIR_LLI 0x00100000
114 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
115 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
116 #define IXGBE_5TUPLE_MAX_PRI 7
117 #define IXGBE_5TUPLE_MIN_PRI 1
119 #define IXGBE_RSS_OFFLOAD_ALL ( \
121 ETH_RSS_NONFRAG_IPV4_TCP | \
122 ETH_RSS_NONFRAG_IPV4_UDP | \
124 ETH_RSS_NONFRAG_IPV6_TCP | \
125 ETH_RSS_NONFRAG_IPV6_UDP | \
127 ETH_RSS_IPV6_TCP_EX | \
130 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
131 #define IXGBE_VF_MAXMSIVECTOR 1
133 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
134 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
136 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
138 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
140 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
141 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
143 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
144 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
148 #define MAC_TYPE_FILTER_SUP(type) do {\
149 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
150 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
151 (type) != ixgbe_mac_X550EM_a)\
156 * Information about the fdir mode.
158 struct ixgbe_hw_fdir_mask {
159 uint16_t vlan_tci_mask;
160 uint32_t src_ipv4_mask;
161 uint32_t dst_ipv4_mask;
162 uint16_t src_ipv6_mask;
163 uint16_t dst_ipv6_mask;
164 uint16_t src_port_mask;
165 uint16_t dst_port_mask;
166 uint16_t flex_bytes_mask;
167 uint8_t mac_addr_byte_mask;
168 uint32_t tunnel_id_mask;
169 uint8_t tunnel_type_mask;
172 struct ixgbe_fdir_filter {
173 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
174 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
175 uint32_t fdirflags; /* drop or forward */
176 uint32_t fdirhash; /* hash value for fdir */
177 uint8_t queue; /* assigned rx queue */
180 /* list of fdir filters */
181 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
183 struct ixgbe_fdir_rule {
184 struct ixgbe_hw_fdir_mask mask;
185 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
186 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
187 bool b_mask; /* If TRUE, mask has meaning. */
188 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
189 uint32_t fdirflags; /* drop or forward */
190 uint32_t soft_id; /* an unique value for this rule */
191 uint8_t queue; /* assigned rx queue */
194 struct ixgbe_hw_fdir_info {
195 struct ixgbe_hw_fdir_mask mask;
196 uint8_t flex_bytes_offset;
205 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
206 /* store the pointers of the filters, index is the hash value. */
207 struct ixgbe_fdir_filter **hash_map;
208 struct rte_hash *hash_handle; /* cuckoo hash handler */
209 bool mask_added; /* If already got mask from consistent filter */
212 /* structure for interrupt relative data */
213 struct ixgbe_interrupt {
216 /*to save original mask during delayed handler */
217 uint32_t mask_original;
220 struct ixgbe_stat_mapping_registers {
221 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
222 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
226 uint32_t vfta[IXGBE_VFTA_SIZE];
229 struct ixgbe_hwstrip {
230 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
234 * VF data which used by PF host only
236 #define IXGBE_MAX_VF_MC_ENTRIES 30
237 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
238 #define IXGBE_MAX_UTA 128
240 struct ixgbe_uta_info {
241 uint8_t uc_filter_type;
243 uint32_t uta_shadow[IXGBE_MAX_UTA];
246 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
248 struct ixgbe_mirror_info {
249 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
250 /**< store PF mirror rules configuration*/
253 struct ixgbe_vf_info {
254 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
255 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
256 uint16_t num_vf_mc_hashes;
257 uint16_t default_vf_vlan_id;
258 uint16_t vlans_enabled;
260 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
262 uint8_t spoofchk_enabled;
267 * Possible l4type of 5tuple filters.
269 enum ixgbe_5tuple_protocol {
270 IXGBE_FILTER_PROTOCOL_TCP = 0,
271 IXGBE_FILTER_PROTOCOL_UDP,
272 IXGBE_FILTER_PROTOCOL_SCTP,
273 IXGBE_FILTER_PROTOCOL_NONE,
276 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
278 struct ixgbe_5tuple_filter_info {
283 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
284 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
285 used when more than one filter matches. */
286 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
287 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
288 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
289 src_port_mask:1, /* if mask is 1b, do not compare src port. */
290 proto_mask:1; /* if mask is 1b, do not compare protocol. */
293 /* 5tuple filter structure */
294 struct ixgbe_5tuple_filter {
295 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
296 uint16_t index; /* the index of 5tuple filter */
297 struct ixgbe_5tuple_filter_info filter_info;
298 uint16_t queue; /* rx queue assigned to */
301 #define IXGBE_5TUPLE_ARRAY_SIZE \
302 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
303 (sizeof(uint32_t) * NBBY))
305 struct ixgbe_ethertype_filter {
310 * If this filter is added by configuration,
311 * it should not be removed.
317 * Structure to store filters' info.
319 struct ixgbe_filter_info {
320 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
321 /* store used ethertype filters*/
322 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
323 /* Bit mask for every used 5tuple filter */
324 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
325 struct ixgbe_5tuple_filter_list fivetuple_list;
326 /* store the SYN filter info */
330 struct ixgbe_l2_tn_key {
331 enum rte_eth_tunnel_type l2_tn_type;
335 struct ixgbe_l2_tn_filter {
336 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
337 struct ixgbe_l2_tn_key key;
341 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
343 struct ixgbe_l2_tn_info {
344 struct ixgbe_l2_tn_filter_list l2_tn_list;
345 struct ixgbe_l2_tn_filter **hash_map;
346 struct rte_hash *hash_handle;
347 bool e_tag_en; /* e-tag enabled */
348 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
349 bool e_tag_ether_type; /* ether type for e-tag */
353 enum rte_filter_type filter_type;
356 /* ntuple filter list structure */
357 struct ixgbe_ntuple_filter_ele {
358 TAILQ_ENTRY(ixgbe_ntuple_filter_ele) entries;
359 struct rte_eth_ntuple_filter filter_info;
361 /* ethertype filter list structure */
362 struct ixgbe_ethertype_filter_ele {
363 TAILQ_ENTRY(ixgbe_ethertype_filter_ele) entries;
364 struct rte_eth_ethertype_filter filter_info;
366 /* syn filter list structure */
367 struct ixgbe_eth_syn_filter_ele {
368 TAILQ_ENTRY(ixgbe_eth_syn_filter_ele) entries;
369 struct rte_eth_syn_filter filter_info;
371 /* fdir filter list structure */
372 struct ixgbe_fdir_rule_ele {
373 TAILQ_ENTRY(ixgbe_fdir_rule_ele) entries;
374 struct ixgbe_fdir_rule filter_info;
376 /* l2_tunnel filter list structure */
377 struct ixgbe_eth_l2_tunnel_conf_ele {
378 TAILQ_ENTRY(ixgbe_eth_l2_tunnel_conf_ele) entries;
379 struct rte_eth_l2_tunnel_conf filter_info;
381 /* ixgbe_flow memory list structure */
382 struct ixgbe_flow_mem {
383 TAILQ_ENTRY(ixgbe_flow_mem) entries;
384 struct rte_flow *flow;
387 TAILQ_HEAD(ixgbe_ntuple_filter_list, ixgbe_ntuple_filter_ele);
388 struct ixgbe_ntuple_filter_list filter_ntuple_list;
389 TAILQ_HEAD(ixgbe_ethertype_filter_list, ixgbe_ethertype_filter_ele);
390 struct ixgbe_ethertype_filter_list filter_ethertype_list;
391 TAILQ_HEAD(ixgbe_syn_filter_list, ixgbe_eth_syn_filter_ele);
392 struct ixgbe_syn_filter_list filter_syn_list;
393 TAILQ_HEAD(ixgbe_fdir_rule_filter_list, ixgbe_fdir_rule_ele);
394 struct ixgbe_fdir_rule_filter_list filter_fdir_list;
395 TAILQ_HEAD(ixgbe_l2_tunnel_filter_list, ixgbe_eth_l2_tunnel_conf_ele);
396 struct ixgbe_l2_tunnel_filter_list filter_l2_tunnel_list;
397 TAILQ_HEAD(ixgbe_flow_mem_list, ixgbe_flow_mem);
398 struct ixgbe_flow_mem_list ixgbe_flow_list;
401 * Statistics counters collected by the MACsec
403 struct ixgbe_macsec_stats {
404 /* TX port statistics */
405 uint64_t out_pkts_untagged;
406 uint64_t out_pkts_encrypted;
407 uint64_t out_pkts_protected;
408 uint64_t out_octets_encrypted;
409 uint64_t out_octets_protected;
411 /* RX port statistics */
412 uint64_t in_pkts_untagged;
413 uint64_t in_pkts_badtag;
414 uint64_t in_pkts_nosci;
415 uint64_t in_pkts_unknownsci;
416 uint64_t in_octets_decrypted;
417 uint64_t in_octets_validated;
419 /* RX SC statistics */
420 uint64_t in_pkts_unchecked;
421 uint64_t in_pkts_delayed;
422 uint64_t in_pkts_late;
424 /* RX SA statistics */
426 uint64_t in_pkts_invalid;
427 uint64_t in_pkts_notvalid;
428 uint64_t in_pkts_unusedsa;
429 uint64_t in_pkts_notusingsa;
432 /* The configuration of bandwidth */
433 struct ixgbe_bw_conf {
434 uint8_t tc_num; /* Number of TCs. */
438 * Structure to store private data for each driver instance (for each port).
440 struct ixgbe_adapter {
442 struct ixgbe_hw_stats stats;
443 struct ixgbe_macsec_stats macsec_stats;
444 struct ixgbe_hw_fdir_info fdir;
445 struct ixgbe_interrupt intr;
446 struct ixgbe_stat_mapping_registers stat_mappings;
447 struct ixgbe_vfta shadow_vfta;
448 struct ixgbe_hwstrip hwstrip;
449 struct ixgbe_dcb_config dcb_config;
450 struct ixgbe_mirror_info mr_data;
451 struct ixgbe_vf_info *vfdata;
452 struct ixgbe_uta_info uta_info;
453 #ifdef RTE_NIC_BYPASS
454 struct ixgbe_bypass_info bps;
455 #endif /* RTE_NIC_BYPASS */
456 struct ixgbe_filter_info filter;
457 struct ixgbe_l2_tn_info l2_tn;
458 struct ixgbe_bw_conf bw_conf;
460 bool rx_bulk_alloc_allowed;
462 struct rte_timecounter systime_tc;
463 struct rte_timecounter rx_tstamp_tc;
464 struct rte_timecounter tx_tstamp_tc;
467 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
468 (&((struct ixgbe_adapter *)adapter)->hw)
470 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
471 (&((struct ixgbe_adapter *)adapter)->stats)
473 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
474 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
476 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
477 (&((struct ixgbe_adapter *)adapter)->intr)
479 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
480 (&((struct ixgbe_adapter *)adapter)->fdir)
482 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
483 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
485 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
486 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
488 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
489 (&((struct ixgbe_adapter *)adapter)->hwstrip)
491 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
492 (&((struct ixgbe_adapter *)adapter)->dcb_config)
494 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
495 (&((struct ixgbe_adapter *)adapter)->vfdata)
497 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
498 (&((struct ixgbe_adapter *)adapter)->mr_data)
500 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
501 (&((struct ixgbe_adapter *)adapter)->uta_info)
503 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
504 (&((struct ixgbe_adapter *)adapter)->filter)
506 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
507 (&((struct ixgbe_adapter *)adapter)->l2_tn)
509 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \
510 (&((struct ixgbe_adapter *)adapter)->bw_conf)
513 * RX/TX function prototypes
515 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
517 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
519 void ixgbe_dev_rx_queue_release(void *rxq);
521 void ixgbe_dev_tx_queue_release(void *txq);
523 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
524 uint16_t nb_rx_desc, unsigned int socket_id,
525 const struct rte_eth_rxconf *rx_conf,
526 struct rte_mempool *mb_pool);
528 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
529 uint16_t nb_tx_desc, unsigned int socket_id,
530 const struct rte_eth_txconf *tx_conf);
532 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
533 uint16_t rx_queue_id);
535 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
537 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
538 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
540 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
542 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
544 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
546 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
548 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
550 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
552 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
554 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
555 struct rte_eth_rxq_info *qinfo);
557 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
558 struct rte_eth_txq_info *qinfo);
560 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
562 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
564 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
566 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
569 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
572 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
573 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
574 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
575 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
577 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
580 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
583 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
586 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
587 struct rte_eth_rss_conf *rss_conf);
589 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
590 struct rte_eth_rss_conf *rss_conf);
592 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
594 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
596 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
598 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
600 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
602 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
603 struct rte_eth_ntuple_filter *filter,
605 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
606 struct rte_eth_ethertype_filter *filter,
608 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
609 struct rte_eth_syn_filter *filter,
612 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
613 struct rte_eth_l2_tunnel_conf *l2_tunnel,
616 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
617 struct rte_eth_l2_tunnel_conf *l2_tunnel);
618 void ixgbe_filterlist_flush(void);
620 * Flow director function prototypes
622 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
623 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
624 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
625 struct ixgbe_fdir_rule *rule,
626 bool del, bool update);
628 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
631 * misc function prototypes
633 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
635 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
637 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
639 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
641 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
643 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
645 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
647 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
649 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
651 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
652 enum rte_filter_op filter_op, void *arg);
653 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
654 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
656 extern const struct rte_flow_ops ixgbe_flow_ops;
658 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
659 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
660 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
661 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
663 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
665 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
667 int ixgbe_vt_check(struct ixgbe_hw *hw);
668 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
669 uint16_t tx_rate, uint64_t q_msk);
670 bool is_ixgbe_supported(struct rte_eth_dev *dev);
673 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
678 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
679 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
680 (filter_info->ethertype_mask & (1 << i)))
687 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
688 struct ixgbe_ethertype_filter *ethertype_filter)
692 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
693 if (!(filter_info->ethertype_mask & (1 << i))) {
694 filter_info->ethertype_mask |= 1 << i;
695 filter_info->ethertype_filters[i].ethertype =
696 ethertype_filter->ethertype;
697 filter_info->ethertype_filters[i].etqf =
698 ethertype_filter->etqf;
699 filter_info->ethertype_filters[i].etqs =
700 ethertype_filter->etqs;
701 filter_info->ethertype_filters[i].conf =
702 ethertype_filter->conf;
710 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
713 if (idx >= IXGBE_MAX_ETQF_FILTERS)
715 filter_info->ethertype_mask &= ~(1 << idx);
716 filter_info->ethertype_filters[idx].ethertype = 0;
717 filter_info->ethertype_filters[idx].etqf = 0;
718 filter_info->ethertype_filters[idx].etqs = 0;
719 filter_info->ethertype_filters[idx].etqs = FALSE;
723 #endif /* _IXGBE_ETHDEV_H_ */