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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
43 /* need update link, bit flag */
44 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
45 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
46 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
47 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
50 * Defines that were not part of ixgbe_type.h as they are not used by the
53 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
54 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
55 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
56 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
57 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
58 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
59 #define IXGBE_NB_STAT_MAPPING_REGS 32
60 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
61 #define IXGBE_VFTA_SIZE 128
62 #define IXGBE_VLAN_TAG_SIZE 4
63 #define IXGBE_MAX_RX_QUEUE_NUM 128
64 #define IXGBE_MAX_INTR_QUEUE_NUM 15
65 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
66 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
67 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
70 #define NBBY 8 /* number of bits in a byte */
72 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
74 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
75 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
76 #define IXGBE_EITR_ITR_INT_SHIFT 3
77 #define IXGBE_EITR_INTERVAL_US(us) \
78 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
79 IXGBE_EITR_ITR_INT_MASK)
82 /* Loopback operation modes */
83 /* 82599 specific loopback operation types */
84 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
85 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
87 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
89 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
90 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
91 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
93 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
95 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
96 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
97 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
98 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
100 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
101 #define IXGBE_ETQF_SHIFT 16
102 #define IXGBE_ETQF_UP_EN 0x00080000
103 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
104 #define IXGBE_ETQF_MAX_PRI 7
106 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
107 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
108 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
110 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
111 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
112 #define IXGBE_L34T_IMIR_LLI 0x00100000
113 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
114 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
115 #define IXGBE_5TUPLE_MAX_PRI 7
116 #define IXGBE_5TUPLE_MIN_PRI 1
118 #define IXGBE_RSS_OFFLOAD_ALL ( \
120 ETH_RSS_NONFRAG_IPV4_TCP | \
121 ETH_RSS_NONFRAG_IPV4_UDP | \
123 ETH_RSS_NONFRAG_IPV6_TCP | \
124 ETH_RSS_NONFRAG_IPV6_UDP | \
126 ETH_RSS_IPV6_TCP_EX | \
129 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
130 #define IXGBE_VF_MAXMSIVECTOR 1
132 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
133 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
135 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
137 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
139 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
142 * Information about the fdir mode.
144 struct ixgbe_hw_fdir_mask {
145 uint16_t vlan_tci_mask;
146 uint32_t src_ipv4_mask;
147 uint32_t dst_ipv4_mask;
148 uint16_t src_ipv6_mask;
149 uint16_t dst_ipv6_mask;
150 uint16_t src_port_mask;
151 uint16_t dst_port_mask;
152 uint16_t flex_bytes_mask;
153 uint8_t mac_addr_byte_mask;
154 uint32_t tunnel_id_mask;
155 uint8_t tunnel_type_mask;
158 struct ixgbe_fdir_filter {
159 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
160 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
161 uint32_t fdirflags; /* drop or forward */
162 uint32_t fdirhash; /* hash value for fdir */
163 uint8_t queue; /* assigned rx queue */
166 /* list of fdir filters */
167 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
169 struct ixgbe_hw_fdir_info {
170 struct ixgbe_hw_fdir_mask mask;
171 uint8_t flex_bytes_offset;
180 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
181 /* store the pointers of the filters, index is the hash value. */
182 struct ixgbe_fdir_filter **hash_map;
183 struct rte_hash *hash_handle; /* cuckoo hash handler */
186 /* structure for interrupt relative data */
187 struct ixgbe_interrupt {
192 struct ixgbe_stat_mapping_registers {
193 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
194 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
198 uint32_t vfta[IXGBE_VFTA_SIZE];
201 struct ixgbe_hwstrip {
202 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
206 * VF data which used by PF host only
208 #define IXGBE_MAX_VF_MC_ENTRIES 30
209 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
210 #define IXGBE_MAX_UTA 128
212 struct ixgbe_uta_info {
213 uint8_t uc_filter_type;
215 uint32_t uta_shadow[IXGBE_MAX_UTA];
218 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
220 struct ixgbe_mirror_info {
221 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
222 /**< store PF mirror rules configuration*/
225 struct ixgbe_vf_info {
226 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
227 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
228 uint16_t num_vf_mc_hashes;
229 uint16_t default_vf_vlan_id;
230 uint16_t vlans_enabled;
232 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
234 uint8_t spoofchk_enabled;
239 * Possible l4type of 5tuple filters.
241 enum ixgbe_5tuple_protocol {
242 IXGBE_FILTER_PROTOCOL_TCP = 0,
243 IXGBE_FILTER_PROTOCOL_UDP,
244 IXGBE_FILTER_PROTOCOL_SCTP,
245 IXGBE_FILTER_PROTOCOL_NONE,
248 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
250 struct ixgbe_5tuple_filter_info {
255 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
256 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
257 used when more than one filter matches. */
258 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
259 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
260 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
261 src_port_mask:1, /* if mask is 1b, do not compare src port. */
262 proto_mask:1; /* if mask is 1b, do not compare protocol. */
265 /* 5tuple filter structure */
266 struct ixgbe_5tuple_filter {
267 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
268 uint16_t index; /* the index of 5tuple filter */
269 struct ixgbe_5tuple_filter_info filter_info;
270 uint16_t queue; /* rx queue assigned to */
273 #define IXGBE_5TUPLE_ARRAY_SIZE \
274 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
275 (sizeof(uint32_t) * NBBY))
278 * Structure to store filters' info.
280 struct ixgbe_filter_info {
281 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
282 /* store used ethertype filters*/
283 uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
284 /* Bit mask for every used 5tuple filter */
285 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
286 struct ixgbe_5tuple_filter_list fivetuple_list;
287 /* store the SYN filter info */
292 * Statistics counters collected by the MACsec
294 struct ixgbe_macsec_stats {
295 /* TX port statistics */
296 uint64_t out_pkts_untagged;
297 uint64_t out_pkts_encrypted;
298 uint64_t out_pkts_protected;
299 uint64_t out_octets_encrypted;
300 uint64_t out_octets_protected;
302 /* RX port statistics */
303 uint64_t in_pkts_untagged;
304 uint64_t in_pkts_badtag;
305 uint64_t in_pkts_nosci;
306 uint64_t in_pkts_unknownsci;
307 uint64_t in_octets_decrypted;
308 uint64_t in_octets_validated;
310 /* RX SC statistics */
311 uint64_t in_pkts_unchecked;
312 uint64_t in_pkts_delayed;
313 uint64_t in_pkts_late;
315 /* RX SA statistics */
317 uint64_t in_pkts_invalid;
318 uint64_t in_pkts_notvalid;
319 uint64_t in_pkts_unusedsa;
320 uint64_t in_pkts_notusingsa;
324 * Structure to store private data for each driver instance (for each port).
326 struct ixgbe_adapter {
328 struct ixgbe_hw_stats stats;
329 struct ixgbe_macsec_stats macsec_stats;
330 struct ixgbe_hw_fdir_info fdir;
331 struct ixgbe_interrupt intr;
332 struct ixgbe_stat_mapping_registers stat_mappings;
333 struct ixgbe_vfta shadow_vfta;
334 struct ixgbe_hwstrip hwstrip;
335 struct ixgbe_dcb_config dcb_config;
336 struct ixgbe_mirror_info mr_data;
337 struct ixgbe_vf_info *vfdata;
338 struct ixgbe_uta_info uta_info;
339 #ifdef RTE_NIC_BYPASS
340 struct ixgbe_bypass_info bps;
341 #endif /* RTE_NIC_BYPASS */
342 struct ixgbe_filter_info filter;
344 bool rx_bulk_alloc_allowed;
346 struct rte_timecounter systime_tc;
347 struct rte_timecounter rx_tstamp_tc;
348 struct rte_timecounter tx_tstamp_tc;
351 #define IXGBE_DEV_TO_PCI(eth_dev) \
352 RTE_DEV_TO_PCI((eth_dev)->device)
354 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
355 (&((struct ixgbe_adapter *)adapter)->hw)
357 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
358 (&((struct ixgbe_adapter *)adapter)->stats)
360 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
361 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
363 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
364 (&((struct ixgbe_adapter *)adapter)->intr)
366 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
367 (&((struct ixgbe_adapter *)adapter)->fdir)
369 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
370 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
372 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
373 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
375 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
376 (&((struct ixgbe_adapter *)adapter)->hwstrip)
378 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
379 (&((struct ixgbe_adapter *)adapter)->dcb_config)
381 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
382 (&((struct ixgbe_adapter *)adapter)->vfdata)
384 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
385 (&((struct ixgbe_adapter *)adapter)->mr_data)
387 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
388 (&((struct ixgbe_adapter *)adapter)->uta_info)
390 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
391 (&((struct ixgbe_adapter *)adapter)->filter)
394 * RX/TX function prototypes
396 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
398 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
400 void ixgbe_dev_rx_queue_release(void *rxq);
402 void ixgbe_dev_tx_queue_release(void *txq);
404 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
405 uint16_t nb_rx_desc, unsigned int socket_id,
406 const struct rte_eth_rxconf *rx_conf,
407 struct rte_mempool *mb_pool);
409 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
410 uint16_t nb_tx_desc, unsigned int socket_id,
411 const struct rte_eth_txconf *tx_conf);
413 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
414 uint16_t rx_queue_id);
416 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
417 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
419 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
421 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
423 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
425 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
427 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
429 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
431 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
433 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
434 struct rte_eth_rxq_info *qinfo);
436 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
437 struct rte_eth_txq_info *qinfo);
439 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
441 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
443 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
445 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
448 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
451 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
452 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
453 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
454 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
456 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
459 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
462 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
465 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
466 struct rte_eth_rss_conf *rss_conf);
468 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
469 struct rte_eth_rss_conf *rss_conf);
471 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
473 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
475 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
477 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
479 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
482 * Flow director function prototypes
484 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
486 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
489 * misc function prototypes
491 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
493 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
495 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
497 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
499 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
501 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
503 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
505 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
507 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
509 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
510 enum rte_filter_op filter_op, void *arg);
512 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
514 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
515 #endif /* _IXGBE_ETHDEV_H_ */