1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
5 #ifndef _IXGBE_ETHDEV_H_
6 #define _IXGBE_ETHDEV_H_
10 #include "base/ixgbe_type.h"
11 #include "base/ixgbe_dcb.h"
12 #include "base/ixgbe_dcb_82599.h"
13 #include "base/ixgbe_dcb_82598.h"
14 #include "ixgbe_bypass.h"
15 #ifdef RTE_LIBRTE_SECURITY
16 #include "ixgbe_ipsec.h"
22 #include <rte_bus_pci.h>
23 #include <rte_tm_driver.h>
25 /* need update link, bit flag */
26 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
27 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
28 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
29 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
30 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
33 * Defines that were not part of ixgbe_type.h as they are not used by the
36 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
37 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
38 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
39 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
40 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
41 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
42 #define IXGBE_NB_STAT_MAPPING_REGS 32
43 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
44 #define IXGBE_VFTA_SIZE 128
45 #define IXGBE_VLAN_TAG_SIZE 4
46 #define IXGBE_HKEY_MAX_INDEX 10
47 #define IXGBE_MAX_RX_QUEUE_NUM 128
48 #define IXGBE_MAX_INTR_QUEUE_NUM 15
49 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
50 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
51 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
54 #define NBBY 8 /* number of bits in a byte */
56 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
58 /* EITR Interval is in 2048ns uinits for 1G and 10G link */
59 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
60 #define IXGBE_EITR_ITR_INT_SHIFT 3
61 #define IXGBE_EITR_INTERVAL_US(us) \
62 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
63 IXGBE_EITR_ITR_INT_MASK)
65 #define IXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
67 /* Loopback operation modes */
68 #define IXGBE_LPBK_NONE 0x0 /* Default value. Loopback is disabled. */
69 #define IXGBE_LPBK_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
70 /* X540-X550 specific loopback operations */
71 #define IXGBE_MII_AUTONEG_ENABLE 0x1000 /* Auto-negociation enable (default = 1) */
73 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
75 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
76 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
77 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
79 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
81 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
82 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
83 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
84 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
86 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
87 #define IXGBE_ETQF_SHIFT 16
88 #define IXGBE_ETQF_UP_EN 0x00080000
89 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
90 #define IXGBE_ETQF_MAX_PRI 7
92 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
93 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
94 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
96 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
97 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
98 #define IXGBE_L34T_IMIR_LLI 0x00100000
99 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
100 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
101 #define IXGBE_5TUPLE_MAX_PRI 7
102 #define IXGBE_5TUPLE_MIN_PRI 1
104 /* bit of VXLAN tunnel type | 7 bits of zeros | 8 bits of zeros*/
105 #define IXGBE_FDIR_VXLAN_TUNNEL_TYPE 0x8000
106 /* bit of NVGRE tunnel type | 7 bits of zeros | 8 bits of zeros*/
107 #define IXGBE_FDIR_NVGRE_TUNNEL_TYPE 0x0
109 #define IXGBE_RSS_OFFLOAD_ALL ( \
111 ETH_RSS_NONFRAG_IPV4_TCP | \
112 ETH_RSS_NONFRAG_IPV4_UDP | \
114 ETH_RSS_NONFRAG_IPV6_TCP | \
115 ETH_RSS_NONFRAG_IPV6_UDP | \
117 ETH_RSS_IPV6_TCP_EX | \
120 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
121 #define IXGBE_VF_MAXMSIVECTOR 1
123 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
124 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
126 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
128 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
130 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
131 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
133 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
134 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
138 #define MAC_TYPE_FILTER_SUP(type) do {\
139 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
140 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
141 (type) != ixgbe_mac_X550EM_a)\
145 /* Link speed for X550 auto negotiation */
146 #define IXGBE_LINK_SPEED_X550_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
147 IXGBE_LINK_SPEED_1GB_FULL | \
148 IXGBE_LINK_SPEED_2_5GB_FULL | \
149 IXGBE_LINK_SPEED_5GB_FULL | \
150 IXGBE_LINK_SPEED_10GB_FULL)
153 * Information about the fdir mode.
155 struct ixgbe_hw_fdir_mask {
156 uint16_t vlan_tci_mask;
157 uint32_t src_ipv4_mask;
158 uint32_t dst_ipv4_mask;
159 uint16_t src_ipv6_mask;
160 uint16_t dst_ipv6_mask;
161 uint16_t src_port_mask;
162 uint16_t dst_port_mask;
163 uint16_t flex_bytes_mask;
164 uint8_t mac_addr_byte_mask;
165 uint32_t tunnel_id_mask;
166 uint8_t tunnel_type_mask;
169 struct ixgbe_fdir_filter {
170 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
171 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
172 uint32_t fdirflags; /* drop or forward */
173 uint32_t fdirhash; /* hash value for fdir */
174 uint8_t queue; /* assigned rx queue */
177 /* list of fdir filters */
178 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
180 struct ixgbe_fdir_rule {
181 struct ixgbe_hw_fdir_mask mask;
182 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
183 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
184 bool b_mask; /* If TRUE, mask has meaning. */
185 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
186 uint32_t fdirflags; /* drop or forward */
187 uint32_t soft_id; /* an unique value for this rule */
188 uint8_t queue; /* assigned rx queue */
189 uint8_t flex_bytes_offset;
192 struct ixgbe_hw_fdir_info {
193 struct ixgbe_hw_fdir_mask mask;
194 uint8_t flex_bytes_offset;
203 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
204 /* store the pointers of the filters, index is the hash value. */
205 struct ixgbe_fdir_filter **hash_map;
206 struct rte_hash *hash_handle; /* cuckoo hash handler */
207 bool mask_added; /* If already got mask from consistent filter */
210 struct ixgbe_rte_flow_rss_conf {
211 struct rte_flow_action_rss conf; /**< RSS parameters. */
212 uint8_t key[IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
213 uint16_t queue[IXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
216 /* structure for interrupt relative data */
217 struct ixgbe_interrupt {
220 /*to save original mask during delayed handler */
221 uint32_t mask_original;
224 struct ixgbe_stat_mapping_registers {
225 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
226 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
230 uint32_t vfta[IXGBE_VFTA_SIZE];
233 struct ixgbe_hwstrip {
234 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
238 * VF data which used by PF host only
240 #define IXGBE_MAX_VF_MC_ENTRIES 30
241 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
242 #define IXGBE_MAX_UTA 128
244 struct ixgbe_uta_info {
245 uint8_t uc_filter_type;
247 uint32_t uta_shadow[IXGBE_MAX_UTA];
250 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
252 struct ixgbe_mirror_info {
253 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
254 /**< store PF mirror rules configuration*/
257 struct ixgbe_vf_info {
258 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
259 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
260 uint16_t num_vf_mc_hashes;
261 uint16_t default_vf_vlan_id;
262 uint16_t vlans_enabled;
264 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
266 uint8_t spoofchk_enabled;
268 uint16_t switch_domain_id;
273 * Possible l4type of 5tuple filters.
275 enum ixgbe_5tuple_protocol {
276 IXGBE_FILTER_PROTOCOL_TCP = 0,
277 IXGBE_FILTER_PROTOCOL_UDP,
278 IXGBE_FILTER_PROTOCOL_SCTP,
279 IXGBE_FILTER_PROTOCOL_NONE,
282 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
284 struct ixgbe_5tuple_filter_info {
289 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
290 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
291 used when more than one filter matches. */
292 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
293 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
294 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
295 src_port_mask:1, /* if mask is 1b, do not compare src port. */
296 proto_mask:1; /* if mask is 1b, do not compare protocol. */
299 /* 5tuple filter structure */
300 struct ixgbe_5tuple_filter {
301 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
302 uint16_t index; /* the index of 5tuple filter */
303 struct ixgbe_5tuple_filter_info filter_info;
304 uint16_t queue; /* rx queue assigned to */
307 #define IXGBE_5TUPLE_ARRAY_SIZE \
308 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
309 (sizeof(uint32_t) * NBBY))
311 struct ixgbe_ethertype_filter {
316 * If this filter is added by configuration,
317 * it should not be removed.
323 * Structure to store filters' info.
325 struct ixgbe_filter_info {
326 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
327 /* store used ethertype filters*/
328 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
329 /* Bit mask for every used 5tuple filter */
330 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
331 struct ixgbe_5tuple_filter_list fivetuple_list;
332 /* store the SYN filter info */
334 /* store the rss filter info */
335 struct ixgbe_rte_flow_rss_conf rss_info;
338 struct ixgbe_l2_tn_key {
339 enum rte_eth_tunnel_type l2_tn_type;
343 struct ixgbe_l2_tn_filter {
344 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
345 struct ixgbe_l2_tn_key key;
349 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
351 struct ixgbe_l2_tn_info {
352 struct ixgbe_l2_tn_filter_list l2_tn_list;
353 struct ixgbe_l2_tn_filter **hash_map;
354 struct rte_hash *hash_handle;
355 bool e_tag_en; /* e-tag enabled */
356 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
357 bool e_tag_ether_type; /* ether type for e-tag */
361 enum rte_filter_type filter_type;
366 * Statistics counters collected by the MACsec
368 struct ixgbe_macsec_stats {
369 /* TX port statistics */
370 uint64_t out_pkts_untagged;
371 uint64_t out_pkts_encrypted;
372 uint64_t out_pkts_protected;
373 uint64_t out_octets_encrypted;
374 uint64_t out_octets_protected;
376 /* RX port statistics */
377 uint64_t in_pkts_untagged;
378 uint64_t in_pkts_badtag;
379 uint64_t in_pkts_nosci;
380 uint64_t in_pkts_unknownsci;
381 uint64_t in_octets_decrypted;
382 uint64_t in_octets_validated;
384 /* RX SC statistics */
385 uint64_t in_pkts_unchecked;
386 uint64_t in_pkts_delayed;
387 uint64_t in_pkts_late;
389 /* RX SA statistics */
391 uint64_t in_pkts_invalid;
392 uint64_t in_pkts_notvalid;
393 uint64_t in_pkts_unusedsa;
394 uint64_t in_pkts_notusingsa;
397 /* The configuration of bandwidth */
398 struct ixgbe_bw_conf {
399 uint8_t tc_num; /* Number of TCs. */
402 /* Struct to store Traffic Manager shaper profile. */
403 struct ixgbe_tm_shaper_profile {
404 TAILQ_ENTRY(ixgbe_tm_shaper_profile) node;
405 uint32_t shaper_profile_id;
406 uint32_t reference_count;
407 struct rte_tm_shaper_params profile;
410 TAILQ_HEAD(ixgbe_shaper_profile_list, ixgbe_tm_shaper_profile);
412 /* node type of Traffic Manager */
413 enum ixgbe_tm_node_type {
414 IXGBE_TM_NODE_TYPE_PORT,
415 IXGBE_TM_NODE_TYPE_TC,
416 IXGBE_TM_NODE_TYPE_QUEUE,
417 IXGBE_TM_NODE_TYPE_MAX,
420 /* Struct to store Traffic Manager node configuration. */
421 struct ixgbe_tm_node {
422 TAILQ_ENTRY(ixgbe_tm_node) node;
426 uint32_t reference_count;
428 struct ixgbe_tm_node *parent;
429 struct ixgbe_tm_shaper_profile *shaper_profile;
430 struct rte_tm_node_params params;
433 TAILQ_HEAD(ixgbe_tm_node_list, ixgbe_tm_node);
435 /* The configuration of Traffic Manager */
436 struct ixgbe_tm_conf {
437 struct ixgbe_shaper_profile_list shaper_profile_list;
438 struct ixgbe_tm_node *root; /* root node - port */
439 struct ixgbe_tm_node_list tc_list; /* node list for all the TCs */
440 struct ixgbe_tm_node_list queue_list; /* node list for all the queues */
442 * The number of added TC nodes.
443 * It should be no more than the TC number of this port.
447 * The number of added queue nodes.
448 * It should be no more than the queue number of this port.
450 uint32_t nb_queue_node;
452 * This flag is used to check if APP can change the TM node
454 * When it's true, means the configuration is applied to HW,
455 * APP should not change the configuration.
456 * As we don't support on-the-fly configuration, when starting
457 * the port, APP should call the hierarchy_commit API to set this
458 * flag to true. When stopping the port, this flag should be set
465 * Structure to store private data for each driver instance (for each port).
467 struct ixgbe_adapter {
469 struct ixgbe_hw_stats stats;
470 struct ixgbe_macsec_stats macsec_stats;
471 struct ixgbe_hw_fdir_info fdir;
472 struct ixgbe_interrupt intr;
473 struct ixgbe_stat_mapping_registers stat_mappings;
474 struct ixgbe_vfta shadow_vfta;
475 struct ixgbe_hwstrip hwstrip;
476 struct ixgbe_dcb_config dcb_config;
477 struct ixgbe_mirror_info mr_data;
478 struct ixgbe_vf_info *vfdata;
479 struct ixgbe_uta_info uta_info;
480 #ifdef RTE_LIBRTE_IXGBE_BYPASS
481 struct ixgbe_bypass_info bps;
482 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
483 struct ixgbe_filter_info filter;
484 struct ixgbe_l2_tn_info l2_tn;
485 struct ixgbe_bw_conf bw_conf;
486 #ifdef RTE_LIBRTE_SECURITY
487 struct ixgbe_ipsec ipsec;
489 bool rx_bulk_alloc_allowed;
491 struct rte_timecounter systime_tc;
492 struct rte_timecounter rx_tstamp_tc;
493 struct rte_timecounter tx_tstamp_tc;
494 struct ixgbe_tm_conf tm_conf;
496 /* For RSS reta table update */
497 uint8_t rss_reta_updated;
500 struct ixgbe_vf_representor {
502 uint16_t switch_domain_id;
503 struct rte_eth_dev *pf_ethdev;
506 int ixgbe_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
507 int ixgbe_vf_representor_uninit(struct rte_eth_dev *ethdev);
509 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
510 (&((struct ixgbe_adapter *)adapter)->hw)
512 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
513 (&((struct ixgbe_adapter *)adapter)->stats)
515 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
516 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
518 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
519 (&((struct ixgbe_adapter *)adapter)->intr)
521 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
522 (&((struct ixgbe_adapter *)adapter)->fdir)
524 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
525 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
527 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
528 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
530 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
531 (&((struct ixgbe_adapter *)adapter)->hwstrip)
533 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
534 (&((struct ixgbe_adapter *)adapter)->dcb_config)
536 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
537 (&((struct ixgbe_adapter *)adapter)->vfdata)
539 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
540 (&((struct ixgbe_adapter *)adapter)->mr_data)
542 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
543 (&((struct ixgbe_adapter *)adapter)->uta_info)
545 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
546 (&((struct ixgbe_adapter *)adapter)->filter)
548 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
549 (&((struct ixgbe_adapter *)adapter)->l2_tn)
551 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \
552 (&((struct ixgbe_adapter *)adapter)->bw_conf)
554 #define IXGBE_DEV_PRIVATE_TO_TM_CONF(adapter) \
555 (&((struct ixgbe_adapter *)adapter)->tm_conf)
557 #define IXGBE_DEV_PRIVATE_TO_IPSEC(adapter)\
558 (&((struct ixgbe_adapter *)adapter)->ipsec)
561 * RX/TX function prototypes
563 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
565 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
567 void ixgbe_dev_rx_queue_release(void *rxq);
569 void ixgbe_dev_tx_queue_release(void *txq);
571 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
572 uint16_t nb_rx_desc, unsigned int socket_id,
573 const struct rte_eth_rxconf *rx_conf,
574 struct rte_mempool *mb_pool);
576 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
577 uint16_t nb_tx_desc, unsigned int socket_id,
578 const struct rte_eth_txconf *tx_conf);
580 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
581 uint16_t rx_queue_id);
583 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
585 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
586 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
588 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
590 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
592 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
594 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
596 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
598 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
600 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
602 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
603 struct rte_eth_rxq_info *qinfo);
605 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
606 struct rte_eth_txq_info *qinfo);
608 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
610 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
612 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
614 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
617 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
620 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
621 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
622 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
623 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
625 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
628 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
631 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
634 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
635 struct rte_eth_rss_conf *rss_conf);
637 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
638 struct rte_eth_rss_conf *rss_conf);
640 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
642 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
644 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
646 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
648 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
650 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
651 struct rte_eth_ntuple_filter *filter,
653 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
654 struct rte_eth_ethertype_filter *filter,
656 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
657 struct rte_eth_syn_filter *filter,
660 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
661 struct rte_eth_l2_tunnel_conf *l2_tunnel,
664 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
665 struct rte_eth_l2_tunnel_conf *l2_tunnel);
666 void ixgbe_filterlist_init(void);
667 void ixgbe_filterlist_flush(void);
669 * Flow director function prototypes
671 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
672 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
673 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
675 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
676 struct ixgbe_fdir_rule *rule,
677 bool del, bool update);
679 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
682 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
683 int wait_to_complete, int vf);
686 * misc function prototypes
688 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
690 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
692 void ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
694 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
696 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
698 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
700 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
702 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
704 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
705 enum rte_filter_op filter_op, void *arg);
706 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
707 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
709 extern const struct rte_flow_ops ixgbe_flow_ops;
711 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
712 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
713 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
714 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
716 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
718 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
720 int ixgbe_vt_check(struct ixgbe_hw *hw);
721 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
722 uint16_t tx_rate, uint64_t q_msk);
723 bool is_ixgbe_supported(struct rte_eth_dev *dev);
724 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
725 void ixgbe_tm_conf_init(struct rte_eth_dev *dev);
726 void ixgbe_tm_conf_uninit(struct rte_eth_dev *dev);
727 int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
729 int ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out,
730 const struct rte_flow_action_rss *in);
731 int ixgbe_action_rss_same(const struct rte_flow_action_rss *comp,
732 const struct rte_flow_action_rss *with);
733 int ixgbe_config_rss_filter(struct rte_eth_dev *dev,
734 struct ixgbe_rte_flow_rss_conf *conf, bool add);
737 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
742 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
743 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
744 (filter_info->ethertype_mask & (1 << i)))
751 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
752 struct ixgbe_ethertype_filter *ethertype_filter)
756 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
757 if (!(filter_info->ethertype_mask & (1 << i))) {
758 filter_info->ethertype_mask |= 1 << i;
759 filter_info->ethertype_filters[i].ethertype =
760 ethertype_filter->ethertype;
761 filter_info->ethertype_filters[i].etqf =
762 ethertype_filter->etqf;
763 filter_info->ethertype_filters[i].etqs =
764 ethertype_filter->etqs;
765 filter_info->ethertype_filters[i].conf =
766 ethertype_filter->conf;
774 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
777 if (idx >= IXGBE_MAX_ETQF_FILTERS)
779 filter_info->ethertype_mask &= ~(1 << idx);
780 filter_info->ethertype_filters[idx].ethertype = 0;
781 filter_info->ethertype_filters[idx].etqf = 0;
782 filter_info->ethertype_filters[idx].etqs = 0;
783 filter_info->ethertype_filters[idx].etqs = FALSE;
787 #endif /* _IXGBE_ETHDEV_H_ */