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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
42 /* need update link, bit flag */
43 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
44 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
45 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
48 * Defines that were not part of ixgbe_type.h as they are not used by the
51 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
52 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
53 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
54 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
55 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
56 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
57 #define IXGBE_NB_STAT_MAPPING_REGS 32
58 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
59 #define IXGBE_VFTA_SIZE 128
60 #define IXGBE_VLAN_TAG_SIZE 4
61 #define IXGBE_MAX_RX_QUEUE_NUM 128
62 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
63 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
66 #define NBBY 8 /* number of bits in a byte */
68 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
70 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
71 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
72 #define IXGBE_EITR_ITR_INT_SHIFT 3
73 #define IXGBE_EITR_INTERVAL_US(us) \
74 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
75 IXGBE_EITR_ITR_INT_MASK)
78 /* Loopback operation modes */
79 /* 82599 specific loopback operation types */
80 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
81 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
83 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
85 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
86 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
87 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
89 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
91 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
92 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
93 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
94 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
96 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
97 #define IXGBE_ETQF_SHIFT 16
98 #define IXGBE_ETQF_UP_EN 0x00080000
99 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
100 #define IXGBE_ETQF_MAX_PRI 7
102 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
103 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
104 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
106 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
107 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
108 #define IXGBE_L34T_IMIR_LLI 0x00100000
109 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
110 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
111 #define IXGBE_5TUPLE_MAX_PRI 7
112 #define IXGBE_5TUPLE_MIN_PRI 1
114 #define IXGBE_RSS_OFFLOAD_ALL ( \
116 ETH_RSS_NONFRAG_IPV4_TCP | \
117 ETH_RSS_NONFRAG_IPV4_UDP | \
119 ETH_RSS_NONFRAG_IPV6_TCP | \
120 ETH_RSS_NONFRAG_IPV6_UDP | \
122 ETH_RSS_IPV6_TCP_EX | \
125 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
126 #define IXGBE_VF_MAXMSIVECTOR 1
128 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
129 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
132 * Information about the fdir mode.
135 struct ixgbe_hw_fdir_mask {
136 uint16_t vlan_tci_mask;
137 uint32_t src_ipv4_mask;
138 uint32_t dst_ipv4_mask;
139 uint16_t src_ipv6_mask;
140 uint16_t dst_ipv6_mask;
141 uint16_t src_port_mask;
142 uint16_t dst_port_mask;
143 uint16_t flex_bytes_mask;
144 uint8_t mac_addr_byte_mask;
145 uint32_t tunnel_id_mask;
146 uint8_t tunnel_type_mask;
149 struct ixgbe_hw_fdir_info {
150 struct ixgbe_hw_fdir_mask mask;
151 uint8_t flex_bytes_offset;
162 /* structure for interrupt relative data */
163 struct ixgbe_interrupt {
168 struct ixgbe_stat_mapping_registers {
169 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
170 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
174 uint32_t vfta[IXGBE_VFTA_SIZE];
177 struct ixgbe_hwstrip {
178 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
182 * VF data which used by PF host only
184 #define IXGBE_MAX_VF_MC_ENTRIES 30
185 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
186 #define IXGBE_MAX_UTA 128
188 struct ixgbe_uta_info {
189 uint8_t uc_filter_type;
191 uint32_t uta_shadow[IXGBE_MAX_UTA];
194 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
196 struct ixgbe_mirror_info {
197 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
198 /**< store PF mirror rules configuration*/
201 struct ixgbe_vf_info {
202 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
203 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
204 uint16_t num_vf_mc_hashes;
205 uint16_t default_vf_vlan_id;
206 uint16_t vlans_enabled;
208 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
210 uint8_t spoofchk_enabled;
215 * Possible l4type of 5tuple filters.
217 enum ixgbe_5tuple_protocol {
218 IXGBE_FILTER_PROTOCOL_TCP = 0,
219 IXGBE_FILTER_PROTOCOL_UDP,
220 IXGBE_FILTER_PROTOCOL_SCTP,
221 IXGBE_FILTER_PROTOCOL_NONE,
224 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
226 struct ixgbe_5tuple_filter_info {
231 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
232 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
233 used when more than one filter matches. */
234 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
235 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
236 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
237 src_port_mask:1, /* if mask is 1b, do not compare src port. */
238 proto_mask:1; /* if mask is 1b, do not compare protocol. */
241 /* 5tuple filter structure */
242 struct ixgbe_5tuple_filter {
243 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
244 uint16_t index; /* the index of 5tuple filter */
245 struct ixgbe_5tuple_filter_info filter_info;
246 uint16_t queue; /* rx queue assigned to */
249 #define IXGBE_5TUPLE_ARRAY_SIZE \
250 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
251 (sizeof(uint32_t) * NBBY))
254 * Structure to store filters' info.
256 struct ixgbe_filter_info {
257 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
258 /* store used ethertype filters*/
259 uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
260 /* Bit mask for every used 5tuple filter */
261 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
262 struct ixgbe_5tuple_filter_list fivetuple_list;
266 * Structure to store private data for each driver instance (for each port).
268 struct ixgbe_adapter {
270 struct ixgbe_hw_stats stats;
271 struct ixgbe_hw_fdir_info fdir;
272 struct ixgbe_interrupt intr;
273 struct ixgbe_stat_mapping_registers stat_mappings;
274 struct ixgbe_vfta shadow_vfta;
275 struct ixgbe_hwstrip hwstrip;
276 struct ixgbe_dcb_config dcb_config;
277 struct ixgbe_mirror_info mr_data;
278 struct ixgbe_vf_info *vfdata;
279 struct ixgbe_uta_info uta_info;
280 #ifdef RTE_NIC_BYPASS
281 struct ixgbe_bypass_info bps;
282 #endif /* RTE_NIC_BYPASS */
283 struct ixgbe_filter_info filter;
285 bool rx_bulk_alloc_allowed;
287 struct rte_timecounter systime_tc;
288 struct rte_timecounter rx_tstamp_tc;
289 struct rte_timecounter tx_tstamp_tc;
292 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
293 (&((struct ixgbe_adapter *)adapter)->hw)
295 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
296 (&((struct ixgbe_adapter *)adapter)->stats)
298 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
299 (&((struct ixgbe_adapter *)adapter)->intr)
301 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
302 (&((struct ixgbe_adapter *)adapter)->fdir)
304 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
305 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
307 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
308 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
310 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
311 (&((struct ixgbe_adapter *)adapter)->hwstrip)
313 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
314 (&((struct ixgbe_adapter *)adapter)->dcb_config)
316 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
317 (&((struct ixgbe_adapter *)adapter)->vfdata)
319 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
320 (&((struct ixgbe_adapter *)adapter)->mr_data)
322 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
323 (&((struct ixgbe_adapter *)adapter)->uta_info)
325 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
326 (&((struct ixgbe_adapter *)adapter)->filter)
329 * RX/TX function prototypes
331 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
333 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
335 void ixgbe_dev_rx_queue_release(void *rxq);
337 void ixgbe_dev_tx_queue_release(void *txq);
339 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
340 uint16_t nb_rx_desc, unsigned int socket_id,
341 const struct rte_eth_rxconf *rx_conf,
342 struct rte_mempool *mb_pool);
344 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
345 uint16_t nb_tx_desc, unsigned int socket_id,
346 const struct rte_eth_txconf *tx_conf);
348 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
349 uint16_t rx_queue_id);
351 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
352 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
354 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
356 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
358 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
360 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
362 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
364 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
366 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
368 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
369 struct rte_eth_rxq_info *qinfo);
371 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
372 struct rte_eth_txq_info *qinfo);
374 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
376 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
378 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
380 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
383 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
384 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
385 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
386 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
388 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
391 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
394 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
395 struct rte_eth_rss_conf *rss_conf);
397 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
398 struct rte_eth_rss_conf *rss_conf);
400 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
402 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
404 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
406 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
408 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
411 * Flow director function prototypes
413 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
415 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
418 * misc function prototypes
420 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
422 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
424 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
426 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
428 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
430 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
432 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
434 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
436 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
438 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
439 enum rte_filter_op filter_op, void *arg);
440 #endif /* _IXGBE_ETHDEV_H_ */