4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
43 /* need update link, bit flag */
44 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
45 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
46 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
47 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
50 * Defines that were not part of ixgbe_type.h as they are not used by the
53 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
54 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
55 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
56 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
57 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
58 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
59 #define IXGBE_NB_STAT_MAPPING_REGS 32
60 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
61 #define IXGBE_VFTA_SIZE 128
62 #define IXGBE_VLAN_TAG_SIZE 4
63 #define IXGBE_MAX_RX_QUEUE_NUM 128
64 #define IXGBE_MAX_INTR_QUEUE_NUM 15
65 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
66 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
67 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
70 #define NBBY 8 /* number of bits in a byte */
72 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
74 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
75 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
76 #define IXGBE_EITR_ITR_INT_SHIFT 3
77 #define IXGBE_EITR_INTERVAL_US(us) \
78 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
79 IXGBE_EITR_ITR_INT_MASK)
82 /* Loopback operation modes */
83 /* 82599 specific loopback operation types */
84 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
85 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
87 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
89 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
90 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
91 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
93 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
95 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
96 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
97 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
98 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
100 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
101 #define IXGBE_ETQF_SHIFT 16
102 #define IXGBE_ETQF_UP_EN 0x00080000
103 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
104 #define IXGBE_ETQF_MAX_PRI 7
106 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
107 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
108 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
110 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
111 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
112 #define IXGBE_L34T_IMIR_LLI 0x00100000
113 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
114 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
115 #define IXGBE_5TUPLE_MAX_PRI 7
116 #define IXGBE_5TUPLE_MIN_PRI 1
118 #define IXGBE_RSS_OFFLOAD_ALL ( \
120 ETH_RSS_NONFRAG_IPV4_TCP | \
121 ETH_RSS_NONFRAG_IPV4_UDP | \
123 ETH_RSS_NONFRAG_IPV6_TCP | \
124 ETH_RSS_NONFRAG_IPV6_UDP | \
126 ETH_RSS_IPV6_TCP_EX | \
129 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
130 #define IXGBE_VF_MAXMSIVECTOR 1
132 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
133 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
135 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
137 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
139 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
140 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
143 * Information about the fdir mode.
145 struct ixgbe_hw_fdir_mask {
146 uint16_t vlan_tci_mask;
147 uint32_t src_ipv4_mask;
148 uint32_t dst_ipv4_mask;
149 uint16_t src_ipv6_mask;
150 uint16_t dst_ipv6_mask;
151 uint16_t src_port_mask;
152 uint16_t dst_port_mask;
153 uint16_t flex_bytes_mask;
154 uint8_t mac_addr_byte_mask;
155 uint32_t tunnel_id_mask;
156 uint8_t tunnel_type_mask;
159 struct ixgbe_fdir_filter {
160 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
161 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
162 uint32_t fdirflags; /* drop or forward */
163 uint32_t fdirhash; /* hash value for fdir */
164 uint8_t queue; /* assigned rx queue */
167 /* list of fdir filters */
168 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
170 struct ixgbe_fdir_rule {
171 struct ixgbe_hw_fdir_mask mask;
172 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
173 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
174 bool b_mask; /* If TRUE, mask has meaning. */
175 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
176 uint32_t fdirflags; /* drop or forward */
177 uint32_t soft_id; /* an unique value for this rule */
178 uint8_t queue; /* assigned rx queue */
181 struct ixgbe_hw_fdir_info {
182 struct ixgbe_hw_fdir_mask mask;
183 uint8_t flex_bytes_offset;
192 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
193 /* store the pointers of the filters, index is the hash value. */
194 struct ixgbe_fdir_filter **hash_map;
195 struct rte_hash *hash_handle; /* cuckoo hash handler */
196 bool mask_added; /* If already got mask from consistent filter */
199 /* structure for interrupt relative data */
200 struct ixgbe_interrupt {
203 /*to save original mask during delayed handler */
204 uint32_t mask_original;
207 struct ixgbe_stat_mapping_registers {
208 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
209 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
213 uint32_t vfta[IXGBE_VFTA_SIZE];
216 struct ixgbe_hwstrip {
217 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
221 * VF data which used by PF host only
223 #define IXGBE_MAX_VF_MC_ENTRIES 30
224 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
225 #define IXGBE_MAX_UTA 128
227 struct ixgbe_uta_info {
228 uint8_t uc_filter_type;
230 uint32_t uta_shadow[IXGBE_MAX_UTA];
233 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
235 struct ixgbe_mirror_info {
236 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
237 /**< store PF mirror rules configuration*/
240 struct ixgbe_vf_info {
241 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
242 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
243 uint16_t num_vf_mc_hashes;
244 uint16_t default_vf_vlan_id;
245 uint16_t vlans_enabled;
247 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
249 uint8_t spoofchk_enabled;
254 * Possible l4type of 5tuple filters.
256 enum ixgbe_5tuple_protocol {
257 IXGBE_FILTER_PROTOCOL_TCP = 0,
258 IXGBE_FILTER_PROTOCOL_UDP,
259 IXGBE_FILTER_PROTOCOL_SCTP,
260 IXGBE_FILTER_PROTOCOL_NONE,
263 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
265 struct ixgbe_5tuple_filter_info {
270 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
271 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
272 used when more than one filter matches. */
273 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
274 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
275 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
276 src_port_mask:1, /* if mask is 1b, do not compare src port. */
277 proto_mask:1; /* if mask is 1b, do not compare protocol. */
280 /* 5tuple filter structure */
281 struct ixgbe_5tuple_filter {
282 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
283 uint16_t index; /* the index of 5tuple filter */
284 struct ixgbe_5tuple_filter_info filter_info;
285 uint16_t queue; /* rx queue assigned to */
288 #define IXGBE_5TUPLE_ARRAY_SIZE \
289 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
290 (sizeof(uint32_t) * NBBY))
292 struct ixgbe_ethertype_filter {
297 * If this filter is added by configuration,
298 * it should not be removed.
304 * Structure to store filters' info.
306 struct ixgbe_filter_info {
307 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
308 /* store used ethertype filters*/
309 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
310 /* Bit mask for every used 5tuple filter */
311 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
312 struct ixgbe_5tuple_filter_list fivetuple_list;
313 /* store the SYN filter info */
317 struct ixgbe_l2_tn_key {
318 enum rte_eth_tunnel_type l2_tn_type;
322 struct ixgbe_l2_tn_filter {
323 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
324 struct ixgbe_l2_tn_key key;
328 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
330 struct ixgbe_l2_tn_info {
331 struct ixgbe_l2_tn_filter_list l2_tn_list;
332 struct ixgbe_l2_tn_filter **hash_map;
333 struct rte_hash *hash_handle;
334 bool e_tag_en; /* e-tag enabled */
335 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
336 bool e_tag_ether_type; /* ether type for e-tag */
340 enum rte_filter_type filter_type;
343 /* ntuple filter list structure */
344 struct ixgbe_ntuple_filter_ele {
345 TAILQ_ENTRY(ixgbe_ntuple_filter_ele) entries;
346 struct rte_eth_ntuple_filter filter_info;
348 /* ethertype filter list structure */
349 struct ixgbe_ethertype_filter_ele {
350 TAILQ_ENTRY(ixgbe_ethertype_filter_ele) entries;
351 struct rte_eth_ethertype_filter filter_info;
353 /* syn filter list structure */
354 struct ixgbe_eth_syn_filter_ele {
355 TAILQ_ENTRY(ixgbe_eth_syn_filter_ele) entries;
356 struct rte_eth_syn_filter filter_info;
358 /* fdir filter list structure */
359 struct ixgbe_fdir_rule_ele {
360 TAILQ_ENTRY(ixgbe_fdir_rule_ele) entries;
361 struct ixgbe_fdir_rule filter_info;
363 /* l2_tunnel filter list structure */
364 struct ixgbe_eth_l2_tunnel_conf_ele {
365 TAILQ_ENTRY(ixgbe_eth_l2_tunnel_conf_ele) entries;
366 struct rte_eth_l2_tunnel_conf filter_info;
368 /* ixgbe_flow memory list structure */
369 struct ixgbe_flow_mem {
370 TAILQ_ENTRY(ixgbe_flow_mem) entries;
371 struct rte_flow *flow;
374 TAILQ_HEAD(ixgbe_ntuple_filter_list, ixgbe_ntuple_filter_ele);
375 struct ixgbe_ntuple_filter_list filter_ntuple_list;
376 TAILQ_HEAD(ixgbe_ethertype_filter_list, ixgbe_ethertype_filter_ele);
377 struct ixgbe_ethertype_filter_list filter_ethertype_list;
378 TAILQ_HEAD(ixgbe_syn_filter_list, ixgbe_eth_syn_filter_ele);
379 struct ixgbe_syn_filter_list filter_syn_list;
380 TAILQ_HEAD(ixgbe_fdir_rule_filter_list, ixgbe_fdir_rule_ele);
381 struct ixgbe_fdir_rule_filter_list filter_fdir_list;
382 TAILQ_HEAD(ixgbe_l2_tunnel_filter_list, ixgbe_eth_l2_tunnel_conf_ele);
383 struct ixgbe_l2_tunnel_filter_list filter_l2_tunnel_list;
384 TAILQ_HEAD(ixgbe_flow_mem_list, ixgbe_flow_mem);
385 struct ixgbe_flow_mem_list ixgbe_flow_list;
388 * Statistics counters collected by the MACsec
390 struct ixgbe_macsec_stats {
391 /* TX port statistics */
392 uint64_t out_pkts_untagged;
393 uint64_t out_pkts_encrypted;
394 uint64_t out_pkts_protected;
395 uint64_t out_octets_encrypted;
396 uint64_t out_octets_protected;
398 /* RX port statistics */
399 uint64_t in_pkts_untagged;
400 uint64_t in_pkts_badtag;
401 uint64_t in_pkts_nosci;
402 uint64_t in_pkts_unknownsci;
403 uint64_t in_octets_decrypted;
404 uint64_t in_octets_validated;
406 /* RX SC statistics */
407 uint64_t in_pkts_unchecked;
408 uint64_t in_pkts_delayed;
409 uint64_t in_pkts_late;
411 /* RX SA statistics */
413 uint64_t in_pkts_invalid;
414 uint64_t in_pkts_notvalid;
415 uint64_t in_pkts_unusedsa;
416 uint64_t in_pkts_notusingsa;
420 * Structure to store private data for each driver instance (for each port).
422 struct ixgbe_adapter {
424 struct ixgbe_hw_stats stats;
425 struct ixgbe_macsec_stats macsec_stats;
426 struct ixgbe_hw_fdir_info fdir;
427 struct ixgbe_interrupt intr;
428 struct ixgbe_stat_mapping_registers stat_mappings;
429 struct ixgbe_vfta shadow_vfta;
430 struct ixgbe_hwstrip hwstrip;
431 struct ixgbe_dcb_config dcb_config;
432 struct ixgbe_mirror_info mr_data;
433 struct ixgbe_vf_info *vfdata;
434 struct ixgbe_uta_info uta_info;
435 #ifdef RTE_NIC_BYPASS
436 struct ixgbe_bypass_info bps;
437 #endif /* RTE_NIC_BYPASS */
438 struct ixgbe_filter_info filter;
439 struct ixgbe_l2_tn_info l2_tn;
441 bool rx_bulk_alloc_allowed;
443 struct rte_timecounter systime_tc;
444 struct rte_timecounter rx_tstamp_tc;
445 struct rte_timecounter tx_tstamp_tc;
448 #define IXGBE_DEV_TO_PCI(eth_dev) \
449 RTE_DEV_TO_PCI((eth_dev)->device)
451 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
452 (&((struct ixgbe_adapter *)adapter)->hw)
454 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
455 (&((struct ixgbe_adapter *)adapter)->stats)
457 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
458 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
460 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
461 (&((struct ixgbe_adapter *)adapter)->intr)
463 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
464 (&((struct ixgbe_adapter *)adapter)->fdir)
466 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
467 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
469 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
470 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
472 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
473 (&((struct ixgbe_adapter *)adapter)->hwstrip)
475 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
476 (&((struct ixgbe_adapter *)adapter)->dcb_config)
478 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
479 (&((struct ixgbe_adapter *)adapter)->vfdata)
481 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
482 (&((struct ixgbe_adapter *)adapter)->mr_data)
484 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
485 (&((struct ixgbe_adapter *)adapter)->uta_info)
487 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
488 (&((struct ixgbe_adapter *)adapter)->filter)
490 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
491 (&((struct ixgbe_adapter *)adapter)->l2_tn)
494 * RX/TX function prototypes
496 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
498 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
500 void ixgbe_dev_rx_queue_release(void *rxq);
502 void ixgbe_dev_tx_queue_release(void *txq);
504 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
505 uint16_t nb_rx_desc, unsigned int socket_id,
506 const struct rte_eth_rxconf *rx_conf,
507 struct rte_mempool *mb_pool);
509 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
510 uint16_t nb_tx_desc, unsigned int socket_id,
511 const struct rte_eth_txconf *tx_conf);
513 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
514 uint16_t rx_queue_id);
516 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
517 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
519 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
521 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
523 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
525 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
527 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
529 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
531 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
533 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
534 struct rte_eth_rxq_info *qinfo);
536 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
537 struct rte_eth_txq_info *qinfo);
539 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
541 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
543 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
545 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
548 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
551 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
552 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
553 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
554 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
556 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
559 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
562 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
565 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
566 struct rte_eth_rss_conf *rss_conf);
568 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
569 struct rte_eth_rss_conf *rss_conf);
571 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
573 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
575 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
577 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
579 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
581 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
582 struct rte_eth_ntuple_filter *filter,
584 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
585 struct rte_eth_ethertype_filter *filter,
587 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
588 struct rte_eth_syn_filter *filter,
591 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
592 struct rte_eth_l2_tunnel_conf *l2_tunnel,
595 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
596 struct rte_eth_l2_tunnel_conf *l2_tunnel);
597 void ixgbe_filterlist_flush(void);
599 * Flow director function prototypes
601 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
602 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
603 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
604 struct ixgbe_fdir_rule *rule,
605 bool del, bool update);
607 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
610 * misc function prototypes
612 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
614 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
616 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
618 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
620 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
622 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
624 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
626 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
628 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
630 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
631 enum rte_filter_op filter_op, void *arg);
632 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
633 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
635 extern const struct rte_flow_ops ixgbe_flow_ops;
637 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
638 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
639 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
640 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
642 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
644 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
647 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
652 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
653 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
654 (filter_info->ethertype_mask & (1 << i)))
661 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
662 struct ixgbe_ethertype_filter *ethertype_filter)
666 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
667 if (!(filter_info->ethertype_mask & (1 << i))) {
668 filter_info->ethertype_mask |= 1 << i;
669 filter_info->ethertype_filters[i].ethertype =
670 ethertype_filter->ethertype;
671 filter_info->ethertype_filters[i].etqf =
672 ethertype_filter->etqf;
673 filter_info->ethertype_filters[i].etqs =
674 ethertype_filter->etqs;
675 filter_info->ethertype_filters[i].conf =
676 ethertype_filter->conf;
684 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
687 if (idx >= IXGBE_MAX_ETQF_FILTERS)
689 filter_info->ethertype_mask &= ~(1 << idx);
690 filter_info->ethertype_filters[idx].ethertype = 0;
691 filter_info->ethertype_filters[idx].etqf = 0;
692 filter_info->ethertype_filters[idx].etqs = 0;
693 filter_info->ethertype_filters[idx].etqs = FALSE;
697 #endif /* _IXGBE_ETHDEV_H_ */