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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
41 /* need update link, bit flag */
42 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
43 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
46 * Defines that were not part of ixgbe_type.h as they are not used by the
49 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
50 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
51 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
52 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
53 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
54 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
55 #define IXGBE_NB_STAT_MAPPING_REGS 32
56 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
57 #define IXGBE_VFTA_SIZE 128
58 #define IXGBE_VLAN_TAG_SIZE 4
59 #define IXGBE_MAX_RX_QUEUE_NUM 128
61 #define NBBY 8 /* number of bits in a byte */
63 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
65 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
66 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
67 #define IXGBE_EITR_ITR_INT_SHIFT 3
68 #define IXGBE_EITR_INTERVAL_US(us) \
69 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
70 IXGBE_EITR_ITR_INT_MASK)
73 /* Loopback operation modes */
74 /* 82599 specific loopback operation types */
75 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
76 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
78 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
80 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
81 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
82 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
84 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
86 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
87 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
88 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
89 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
91 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
92 #define IXGBE_ETQF_SHIFT 16
93 #define IXGBE_ETQF_UP_EN 0x00080000
94 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
95 #define IXGBE_ETQF_MAX_PRI 7
97 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
98 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
99 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
101 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
102 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
103 #define IXGBE_L34T_IMIR_LLI 0x00100000
104 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
105 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
106 #define IXGBE_5TUPLE_MAX_PRI 7
107 #define IXGBE_5TUPLE_MIN_PRI 1
109 #define IXGBE_RSS_OFFLOAD_ALL ( \
111 ETH_RSS_NONFRAG_IPV4_TCP | \
112 ETH_RSS_NONFRAG_IPV4_UDP | \
114 ETH_RSS_NONFRAG_IPV6_TCP | \
115 ETH_RSS_NONFRAG_IPV6_UDP | \
117 ETH_RSS_IPV6_TCP_EX | \
120 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
121 #define IXGBE_VF_MAXMSIVECTOR 1
124 * Information about the fdir mode.
127 struct ixgbe_hw_fdir_mask {
128 uint16_t vlan_tci_mask;
129 uint32_t src_ipv4_mask;
130 uint32_t dst_ipv4_mask;
131 uint16_t src_ipv6_mask;
132 uint16_t dst_ipv6_mask;
133 uint16_t src_port_mask;
134 uint16_t dst_port_mask;
135 uint16_t flex_bytes_mask;
138 struct ixgbe_hw_fdir_info {
139 struct ixgbe_hw_fdir_mask mask;
140 uint8_t flex_bytes_offset;
151 /* structure for interrupt relative data */
152 struct ixgbe_interrupt {
157 struct ixgbe_stat_mapping_registers {
158 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
159 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
163 uint32_t vfta[IXGBE_VFTA_SIZE];
166 struct ixgbe_hwstrip {
167 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
171 * VF data which used by PF host only
173 #define IXGBE_MAX_VF_MC_ENTRIES 30
174 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
175 #define IXGBE_MAX_UTA 128
177 struct ixgbe_uta_info {
178 uint8_t uc_filter_type;
180 uint32_t uta_shadow[IXGBE_MAX_UTA];
183 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
185 struct ixgbe_mirror_info {
186 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
187 /**< store PF mirror rules configuration*/
190 struct ixgbe_vf_info {
191 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
192 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
193 uint16_t num_vf_mc_hashes;
194 uint16_t default_vf_vlan_id;
195 uint16_t vlans_enabled;
197 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
199 uint8_t spoofchk_enabled;
204 * Possible l4type of 5tuple filters.
206 enum ixgbe_5tuple_protocol {
207 IXGBE_FILTER_PROTOCOL_TCP = 0,
208 IXGBE_FILTER_PROTOCOL_UDP,
209 IXGBE_FILTER_PROTOCOL_SCTP,
210 IXGBE_FILTER_PROTOCOL_NONE,
213 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
215 struct ixgbe_5tuple_filter_info {
220 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
221 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
222 used when more than one filter matches. */
223 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
224 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
225 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
226 src_port_mask:1, /* if mask is 1b, do not compare src port. */
227 proto_mask:1; /* if mask is 1b, do not compare protocol. */
230 /* 5tuple filter structure */
231 struct ixgbe_5tuple_filter {
232 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
233 uint16_t index; /* the index of 5tuple filter */
234 struct ixgbe_5tuple_filter_info filter_info;
235 uint16_t queue; /* rx queue assigned to */
238 #define IXGBE_5TUPLE_ARRAY_SIZE \
239 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
240 (sizeof(uint32_t) * NBBY))
243 * Structure to store filters' info.
245 struct ixgbe_filter_info {
246 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
247 /* store used ethertype filters*/
248 uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
249 /* Bit mask for every used 5tuple filter */
250 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
251 struct ixgbe_5tuple_filter_list fivetuple_list;
255 * Structure to store private data for each driver instance (for each port).
257 struct ixgbe_adapter {
259 struct ixgbe_hw_stats stats;
260 struct ixgbe_hw_fdir_info fdir;
261 struct ixgbe_interrupt intr;
262 struct ixgbe_stat_mapping_registers stat_mappings;
263 struct ixgbe_vfta shadow_vfta;
264 struct ixgbe_hwstrip hwstrip;
265 struct ixgbe_dcb_config dcb_config;
266 struct ixgbe_mirror_info mr_data;
267 struct ixgbe_vf_info *vfdata;
268 struct ixgbe_uta_info uta_info;
269 #ifdef RTE_NIC_BYPASS
270 struct ixgbe_bypass_info bps;
271 #endif /* RTE_NIC_BYPASS */
272 struct ixgbe_filter_info filter;
274 bool rx_bulk_alloc_allowed;
278 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
279 (&((struct ixgbe_adapter *)adapter)->hw)
281 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
282 (&((struct ixgbe_adapter *)adapter)->stats)
284 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
285 (&((struct ixgbe_adapter *)adapter)->intr)
287 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
288 (&((struct ixgbe_adapter *)adapter)->fdir)
290 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
291 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
293 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
294 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
296 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
297 (&((struct ixgbe_adapter *)adapter)->hwstrip)
299 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
300 (&((struct ixgbe_adapter *)adapter)->dcb_config)
302 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
303 (&((struct ixgbe_adapter *)adapter)->vfdata)
305 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
306 (&((struct ixgbe_adapter *)adapter)->mr_data)
308 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
309 (&((struct ixgbe_adapter *)adapter)->uta_info)
311 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
312 (&((struct ixgbe_adapter *)adapter)->filter)
315 * RX/TX function prototypes
317 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
319 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
321 void ixgbe_dev_rx_queue_release(void *rxq);
323 void ixgbe_dev_tx_queue_release(void *txq);
325 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
326 uint16_t nb_rx_desc, unsigned int socket_id,
327 const struct rte_eth_rxconf *rx_conf,
328 struct rte_mempool *mb_pool);
330 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
331 uint16_t nb_tx_desc, unsigned int socket_id,
332 const struct rte_eth_txconf *tx_conf);
334 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
335 uint16_t rx_queue_id);
337 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
338 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
340 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
342 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
344 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
346 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
348 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
350 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
352 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
354 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
356 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
358 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
360 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
363 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
364 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
365 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
366 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
368 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
371 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
374 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
375 struct rte_eth_rss_conf *rss_conf);
377 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
378 struct rte_eth_rss_conf *rss_conf);
381 * Flow director function prototypes
383 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
385 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
388 * misc function prototypes
390 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
392 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
394 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
396 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
398 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
400 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
402 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
404 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
406 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
408 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
409 enum rte_filter_op filter_op, void *arg);
410 #endif /* _IXGBE_ETHDEV_H_ */