1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
5 #ifndef _IXGBE_ETHDEV_H_
6 #define _IXGBE_ETHDEV_H_
10 #include "base/ixgbe_type.h"
11 #include "base/ixgbe_dcb.h"
12 #include "base/ixgbe_dcb_82599.h"
13 #include "base/ixgbe_dcb_82598.h"
14 #include "ixgbe_bypass.h"
15 #ifdef RTE_LIBRTE_SECURITY
16 #include "ixgbe_ipsec.h"
22 #include <rte_bus_pci.h>
23 #include <rte_tm_driver.h>
25 /* need update link, bit flag */
26 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
27 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
28 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
29 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
30 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
33 * Defines that were not part of ixgbe_type.h as they are not used by the
36 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
37 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
38 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
39 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
40 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
41 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
42 #define IXGBE_NB_STAT_MAPPING_REGS 32
43 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
44 #define IXGBE_VFTA_SIZE 128
45 #define IXGBE_VLAN_TAG_SIZE 4
46 #define IXGBE_HKEY_MAX_INDEX 10
47 #define IXGBE_MAX_RX_QUEUE_NUM 128
48 #define IXGBE_MAX_INTR_QUEUE_NUM 15
49 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
50 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
51 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
54 #define NBBY 8 /* number of bits in a byte */
56 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
58 /* EITR Interval is in 2048ns uinits for 1G and 10G link */
59 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
60 #define IXGBE_EITR_ITR_INT_SHIFT 3
61 #define IXGBE_EITR_INTERVAL_US(us) \
62 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
63 IXGBE_EITR_ITR_INT_MASK)
65 #define IXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
67 /* Loopback operation modes */
68 /* 82599 specific loopback operation types */
69 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
70 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
72 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
74 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
75 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
76 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
78 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
80 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
81 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
82 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
83 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
85 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
86 #define IXGBE_ETQF_SHIFT 16
87 #define IXGBE_ETQF_UP_EN 0x00080000
88 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
89 #define IXGBE_ETQF_MAX_PRI 7
91 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
92 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
93 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
95 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
96 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
97 #define IXGBE_L34T_IMIR_LLI 0x00100000
98 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
99 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
100 #define IXGBE_5TUPLE_MAX_PRI 7
101 #define IXGBE_5TUPLE_MIN_PRI 1
103 /* bit of VXLAN tunnel type | 7 bits of zeros | 8 bits of zeros*/
104 #define IXGBE_FDIR_VXLAN_TUNNEL_TYPE 0x8000
105 /* bit of NVGRE tunnel type | 7 bits of zeros | 8 bits of zeros*/
106 #define IXGBE_FDIR_NVGRE_TUNNEL_TYPE 0x0
108 #define IXGBE_RSS_OFFLOAD_ALL ( \
110 ETH_RSS_NONFRAG_IPV4_TCP | \
111 ETH_RSS_NONFRAG_IPV4_UDP | \
113 ETH_RSS_NONFRAG_IPV6_TCP | \
114 ETH_RSS_NONFRAG_IPV6_UDP | \
116 ETH_RSS_IPV6_TCP_EX | \
119 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
120 #define IXGBE_VF_MAXMSIVECTOR 1
122 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
123 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
125 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
127 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
129 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
130 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
132 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
133 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
137 #define MAC_TYPE_FILTER_SUP(type) do {\
138 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
139 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
140 (type) != ixgbe_mac_X550EM_a)\
144 /* Link speed for X550 auto negotiation */
145 #define IXGBE_LINK_SPEED_X550_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
146 IXGBE_LINK_SPEED_1GB_FULL | \
147 IXGBE_LINK_SPEED_2_5GB_FULL | \
148 IXGBE_LINK_SPEED_5GB_FULL | \
149 IXGBE_LINK_SPEED_10GB_FULL)
152 * Information about the fdir mode.
154 struct ixgbe_hw_fdir_mask {
155 uint16_t vlan_tci_mask;
156 uint32_t src_ipv4_mask;
157 uint32_t dst_ipv4_mask;
158 uint16_t src_ipv6_mask;
159 uint16_t dst_ipv6_mask;
160 uint16_t src_port_mask;
161 uint16_t dst_port_mask;
162 uint16_t flex_bytes_mask;
163 uint8_t mac_addr_byte_mask;
164 uint32_t tunnel_id_mask;
165 uint8_t tunnel_type_mask;
168 struct ixgbe_fdir_filter {
169 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
170 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
171 uint32_t fdirflags; /* drop or forward */
172 uint32_t fdirhash; /* hash value for fdir */
173 uint8_t queue; /* assigned rx queue */
176 /* list of fdir filters */
177 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
179 struct ixgbe_fdir_rule {
180 struct ixgbe_hw_fdir_mask mask;
181 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
182 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
183 bool b_mask; /* If TRUE, mask has meaning. */
184 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
185 uint32_t fdirflags; /* drop or forward */
186 uint32_t soft_id; /* an unique value for this rule */
187 uint8_t queue; /* assigned rx queue */
188 uint8_t flex_bytes_offset;
191 struct ixgbe_hw_fdir_info {
192 struct ixgbe_hw_fdir_mask mask;
193 uint8_t flex_bytes_offset;
202 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
203 /* store the pointers of the filters, index is the hash value. */
204 struct ixgbe_fdir_filter **hash_map;
205 struct rte_hash *hash_handle; /* cuckoo hash handler */
206 bool mask_added; /* If already got mask from consistent filter */
209 struct ixgbe_rte_flow_rss_conf {
210 struct rte_flow_action_rss conf; /**< RSS parameters. */
211 uint8_t key[IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
212 uint16_t queue[IXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
215 /* structure for interrupt relative data */
216 struct ixgbe_interrupt {
219 /*to save original mask during delayed handler */
220 uint32_t mask_original;
223 struct ixgbe_stat_mapping_registers {
224 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
225 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
229 uint32_t vfta[IXGBE_VFTA_SIZE];
232 struct ixgbe_hwstrip {
233 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
237 * VF data which used by PF host only
239 #define IXGBE_MAX_VF_MC_ENTRIES 30
240 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
241 #define IXGBE_MAX_UTA 128
243 struct ixgbe_uta_info {
244 uint8_t uc_filter_type;
246 uint32_t uta_shadow[IXGBE_MAX_UTA];
249 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
251 struct ixgbe_mirror_info {
252 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
253 /**< store PF mirror rules configuration*/
256 struct ixgbe_vf_info {
257 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
258 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
259 uint16_t num_vf_mc_hashes;
260 uint16_t default_vf_vlan_id;
261 uint16_t vlans_enabled;
263 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
265 uint8_t spoofchk_enabled;
267 uint16_t switch_domain_id;
271 * Possible l4type of 5tuple filters.
273 enum ixgbe_5tuple_protocol {
274 IXGBE_FILTER_PROTOCOL_TCP = 0,
275 IXGBE_FILTER_PROTOCOL_UDP,
276 IXGBE_FILTER_PROTOCOL_SCTP,
277 IXGBE_FILTER_PROTOCOL_NONE,
280 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
282 struct ixgbe_5tuple_filter_info {
287 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
288 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
289 used when more than one filter matches. */
290 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
291 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
292 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
293 src_port_mask:1, /* if mask is 1b, do not compare src port. */
294 proto_mask:1; /* if mask is 1b, do not compare protocol. */
297 /* 5tuple filter structure */
298 struct ixgbe_5tuple_filter {
299 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
300 uint16_t index; /* the index of 5tuple filter */
301 struct ixgbe_5tuple_filter_info filter_info;
302 uint16_t queue; /* rx queue assigned to */
305 #define IXGBE_5TUPLE_ARRAY_SIZE \
306 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
307 (sizeof(uint32_t) * NBBY))
309 struct ixgbe_ethertype_filter {
314 * If this filter is added by configuration,
315 * it should not be removed.
321 * Structure to store filters' info.
323 struct ixgbe_filter_info {
324 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
325 /* store used ethertype filters*/
326 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
327 /* Bit mask for every used 5tuple filter */
328 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
329 struct ixgbe_5tuple_filter_list fivetuple_list;
330 /* store the SYN filter info */
332 /* store the rss filter info */
333 struct ixgbe_rte_flow_rss_conf rss_info;
336 struct ixgbe_l2_tn_key {
337 enum rte_eth_tunnel_type l2_tn_type;
341 struct ixgbe_l2_tn_filter {
342 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
343 struct ixgbe_l2_tn_key key;
347 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
349 struct ixgbe_l2_tn_info {
350 struct ixgbe_l2_tn_filter_list l2_tn_list;
351 struct ixgbe_l2_tn_filter **hash_map;
352 struct rte_hash *hash_handle;
353 bool e_tag_en; /* e-tag enabled */
354 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
355 bool e_tag_ether_type; /* ether type for e-tag */
359 enum rte_filter_type filter_type;
364 * Statistics counters collected by the MACsec
366 struct ixgbe_macsec_stats {
367 /* TX port statistics */
368 uint64_t out_pkts_untagged;
369 uint64_t out_pkts_encrypted;
370 uint64_t out_pkts_protected;
371 uint64_t out_octets_encrypted;
372 uint64_t out_octets_protected;
374 /* RX port statistics */
375 uint64_t in_pkts_untagged;
376 uint64_t in_pkts_badtag;
377 uint64_t in_pkts_nosci;
378 uint64_t in_pkts_unknownsci;
379 uint64_t in_octets_decrypted;
380 uint64_t in_octets_validated;
382 /* RX SC statistics */
383 uint64_t in_pkts_unchecked;
384 uint64_t in_pkts_delayed;
385 uint64_t in_pkts_late;
387 /* RX SA statistics */
389 uint64_t in_pkts_invalid;
390 uint64_t in_pkts_notvalid;
391 uint64_t in_pkts_unusedsa;
392 uint64_t in_pkts_notusingsa;
395 /* The configuration of bandwidth */
396 struct ixgbe_bw_conf {
397 uint8_t tc_num; /* Number of TCs. */
400 /* Struct to store Traffic Manager shaper profile. */
401 struct ixgbe_tm_shaper_profile {
402 TAILQ_ENTRY(ixgbe_tm_shaper_profile) node;
403 uint32_t shaper_profile_id;
404 uint32_t reference_count;
405 struct rte_tm_shaper_params profile;
408 TAILQ_HEAD(ixgbe_shaper_profile_list, ixgbe_tm_shaper_profile);
410 /* node type of Traffic Manager */
411 enum ixgbe_tm_node_type {
412 IXGBE_TM_NODE_TYPE_PORT,
413 IXGBE_TM_NODE_TYPE_TC,
414 IXGBE_TM_NODE_TYPE_QUEUE,
415 IXGBE_TM_NODE_TYPE_MAX,
418 /* Struct to store Traffic Manager node configuration. */
419 struct ixgbe_tm_node {
420 TAILQ_ENTRY(ixgbe_tm_node) node;
424 uint32_t reference_count;
426 struct ixgbe_tm_node *parent;
427 struct ixgbe_tm_shaper_profile *shaper_profile;
428 struct rte_tm_node_params params;
431 TAILQ_HEAD(ixgbe_tm_node_list, ixgbe_tm_node);
433 /* The configuration of Traffic Manager */
434 struct ixgbe_tm_conf {
435 struct ixgbe_shaper_profile_list shaper_profile_list;
436 struct ixgbe_tm_node *root; /* root node - port */
437 struct ixgbe_tm_node_list tc_list; /* node list for all the TCs */
438 struct ixgbe_tm_node_list queue_list; /* node list for all the queues */
440 * The number of added TC nodes.
441 * It should be no more than the TC number of this port.
445 * The number of added queue nodes.
446 * It should be no more than the queue number of this port.
448 uint32_t nb_queue_node;
450 * This flag is used to check if APP can change the TM node
452 * When it's true, means the configuration is applied to HW,
453 * APP should not change the configuration.
454 * As we don't support on-the-fly configuration, when starting
455 * the port, APP should call the hierarchy_commit API to set this
456 * flag to true. When stopping the port, this flag should be set
463 * Structure to store private data for each driver instance (for each port).
465 struct ixgbe_adapter {
467 struct ixgbe_hw_stats stats;
468 struct ixgbe_macsec_stats macsec_stats;
469 struct ixgbe_hw_fdir_info fdir;
470 struct ixgbe_interrupt intr;
471 struct ixgbe_stat_mapping_registers stat_mappings;
472 struct ixgbe_vfta shadow_vfta;
473 struct ixgbe_hwstrip hwstrip;
474 struct ixgbe_dcb_config dcb_config;
475 struct ixgbe_mirror_info mr_data;
476 struct ixgbe_vf_info *vfdata;
477 struct ixgbe_uta_info uta_info;
478 #ifdef RTE_LIBRTE_IXGBE_BYPASS
479 struct ixgbe_bypass_info bps;
480 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
481 struct ixgbe_filter_info filter;
482 struct ixgbe_l2_tn_info l2_tn;
483 struct ixgbe_bw_conf bw_conf;
484 #ifdef RTE_LIBRTE_SECURITY
485 struct ixgbe_ipsec ipsec;
487 bool rx_bulk_alloc_allowed;
489 struct rte_timecounter systime_tc;
490 struct rte_timecounter rx_tstamp_tc;
491 struct rte_timecounter tx_tstamp_tc;
492 struct ixgbe_tm_conf tm_conf;
495 struct ixgbe_vf_representor {
497 uint16_t switch_domain_id;
498 struct rte_eth_dev *pf_ethdev;
501 int ixgbe_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
502 int ixgbe_vf_representor_uninit(struct rte_eth_dev *ethdev);
504 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
505 (&((struct ixgbe_adapter *)adapter)->hw)
507 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
508 (&((struct ixgbe_adapter *)adapter)->stats)
510 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
511 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
513 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
514 (&((struct ixgbe_adapter *)adapter)->intr)
516 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
517 (&((struct ixgbe_adapter *)adapter)->fdir)
519 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
520 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
522 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
523 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
525 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
526 (&((struct ixgbe_adapter *)adapter)->hwstrip)
528 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
529 (&((struct ixgbe_adapter *)adapter)->dcb_config)
531 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
532 (&((struct ixgbe_adapter *)adapter)->vfdata)
534 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
535 (&((struct ixgbe_adapter *)adapter)->mr_data)
537 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
538 (&((struct ixgbe_adapter *)adapter)->uta_info)
540 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
541 (&((struct ixgbe_adapter *)adapter)->filter)
543 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
544 (&((struct ixgbe_adapter *)adapter)->l2_tn)
546 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \
547 (&((struct ixgbe_adapter *)adapter)->bw_conf)
549 #define IXGBE_DEV_PRIVATE_TO_TM_CONF(adapter) \
550 (&((struct ixgbe_adapter *)adapter)->tm_conf)
552 #define IXGBE_DEV_PRIVATE_TO_IPSEC(adapter)\
553 (&((struct ixgbe_adapter *)adapter)->ipsec)
556 * RX/TX function prototypes
558 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
560 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
562 void ixgbe_dev_rx_queue_release(void *rxq);
564 void ixgbe_dev_tx_queue_release(void *txq);
566 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
567 uint16_t nb_rx_desc, unsigned int socket_id,
568 const struct rte_eth_rxconf *rx_conf,
569 struct rte_mempool *mb_pool);
571 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
572 uint16_t nb_tx_desc, unsigned int socket_id,
573 const struct rte_eth_txconf *tx_conf);
575 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
576 uint16_t rx_queue_id);
578 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
580 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
581 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
583 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
585 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
587 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
589 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
591 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
593 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
595 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
597 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
598 struct rte_eth_rxq_info *qinfo);
600 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
601 struct rte_eth_txq_info *qinfo);
603 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
605 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
607 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
609 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
612 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
615 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
616 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
617 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
618 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
620 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
623 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
626 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
629 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
630 struct rte_eth_rss_conf *rss_conf);
632 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
633 struct rte_eth_rss_conf *rss_conf);
635 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
637 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
639 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
641 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
643 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
645 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
646 struct rte_eth_ntuple_filter *filter,
648 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
649 struct rte_eth_ethertype_filter *filter,
651 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
652 struct rte_eth_syn_filter *filter,
655 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
656 struct rte_eth_l2_tunnel_conf *l2_tunnel,
659 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
660 struct rte_eth_l2_tunnel_conf *l2_tunnel);
661 void ixgbe_filterlist_init(void);
662 void ixgbe_filterlist_flush(void);
664 * Flow director function prototypes
666 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
667 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
668 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
670 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
671 struct ixgbe_fdir_rule *rule,
672 bool del, bool update);
674 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
677 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
678 int wait_to_complete, int vf);
681 * misc function prototypes
683 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
685 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
687 void ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
689 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
691 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
693 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
695 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
697 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
699 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
700 enum rte_filter_op filter_op, void *arg);
701 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
702 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
704 extern const struct rte_flow_ops ixgbe_flow_ops;
706 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
707 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
708 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
709 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
711 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
713 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
715 int ixgbe_vt_check(struct ixgbe_hw *hw);
716 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
717 uint16_t tx_rate, uint64_t q_msk);
718 bool is_ixgbe_supported(struct rte_eth_dev *dev);
719 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
720 void ixgbe_tm_conf_init(struct rte_eth_dev *dev);
721 void ixgbe_tm_conf_uninit(struct rte_eth_dev *dev);
722 int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
724 int ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out,
725 const struct rte_flow_action_rss *in);
726 int ixgbe_action_rss_same(const struct rte_flow_action_rss *comp,
727 const struct rte_flow_action_rss *with);
728 int ixgbe_config_rss_filter(struct rte_eth_dev *dev,
729 struct ixgbe_rte_flow_rss_conf *conf, bool add);
732 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
737 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
738 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
739 (filter_info->ethertype_mask & (1 << i)))
746 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
747 struct ixgbe_ethertype_filter *ethertype_filter)
751 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
752 if (!(filter_info->ethertype_mask & (1 << i))) {
753 filter_info->ethertype_mask |= 1 << i;
754 filter_info->ethertype_filters[i].ethertype =
755 ethertype_filter->ethertype;
756 filter_info->ethertype_filters[i].etqf =
757 ethertype_filter->etqf;
758 filter_info->ethertype_filters[i].etqs =
759 ethertype_filter->etqs;
760 filter_info->ethertype_filters[i].conf =
761 ethertype_filter->conf;
769 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
772 if (idx >= IXGBE_MAX_ETQF_FILTERS)
774 filter_info->ethertype_mask &= ~(1 << idx);
775 filter_info->ethertype_filters[idx].ethertype = 0;
776 filter_info->ethertype_filters[idx].etqf = 0;
777 filter_info->ethertype_filters[idx].etqs = 0;
778 filter_info->ethertype_filters[idx].etqs = FALSE;
782 #endif /* _IXGBE_ETHDEV_H_ */