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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
42 /* need update link, bit flag */
43 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
44 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
47 * Defines that were not part of ixgbe_type.h as they are not used by the
50 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
51 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
52 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
53 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
54 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
55 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
56 #define IXGBE_NB_STAT_MAPPING_REGS 32
57 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
58 #define IXGBE_VFTA_SIZE 128
59 #define IXGBE_VLAN_TAG_SIZE 4
60 #define IXGBE_MAX_RX_QUEUE_NUM 128
61 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
62 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
65 #define NBBY 8 /* number of bits in a byte */
67 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
69 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
70 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
71 #define IXGBE_EITR_ITR_INT_SHIFT 3
72 #define IXGBE_EITR_INTERVAL_US(us) \
73 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
74 IXGBE_EITR_ITR_INT_MASK)
77 /* Loopback operation modes */
78 /* 82599 specific loopback operation types */
79 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
80 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
82 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
84 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
85 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
86 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
88 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
90 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
91 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
92 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
93 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
95 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
96 #define IXGBE_ETQF_SHIFT 16
97 #define IXGBE_ETQF_UP_EN 0x00080000
98 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
99 #define IXGBE_ETQF_MAX_PRI 7
101 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
102 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
103 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
105 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
106 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
107 #define IXGBE_L34T_IMIR_LLI 0x00100000
108 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
109 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
110 #define IXGBE_5TUPLE_MAX_PRI 7
111 #define IXGBE_5TUPLE_MIN_PRI 1
113 #define IXGBE_RSS_OFFLOAD_ALL ( \
115 ETH_RSS_NONFRAG_IPV4_TCP | \
116 ETH_RSS_NONFRAG_IPV4_UDP | \
118 ETH_RSS_NONFRAG_IPV6_TCP | \
119 ETH_RSS_NONFRAG_IPV6_UDP | \
121 ETH_RSS_IPV6_TCP_EX | \
124 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
125 #define IXGBE_VF_MAXMSIVECTOR 1
127 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
128 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
131 * Information about the fdir mode.
134 struct ixgbe_hw_fdir_mask {
135 uint16_t vlan_tci_mask;
136 uint32_t src_ipv4_mask;
137 uint32_t dst_ipv4_mask;
138 uint16_t src_ipv6_mask;
139 uint16_t dst_ipv6_mask;
140 uint16_t src_port_mask;
141 uint16_t dst_port_mask;
142 uint16_t flex_bytes_mask;
143 uint8_t mac_addr_byte_mask;
144 uint32_t tunnel_id_mask;
145 uint8_t tunnel_type_mask;
148 struct ixgbe_hw_fdir_info {
149 struct ixgbe_hw_fdir_mask mask;
150 uint8_t flex_bytes_offset;
161 /* structure for interrupt relative data */
162 struct ixgbe_interrupt {
167 struct ixgbe_stat_mapping_registers {
168 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
169 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
173 uint32_t vfta[IXGBE_VFTA_SIZE];
176 struct ixgbe_hwstrip {
177 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
181 * VF data which used by PF host only
183 #define IXGBE_MAX_VF_MC_ENTRIES 30
184 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
185 #define IXGBE_MAX_UTA 128
187 struct ixgbe_uta_info {
188 uint8_t uc_filter_type;
190 uint32_t uta_shadow[IXGBE_MAX_UTA];
193 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
195 struct ixgbe_mirror_info {
196 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
197 /**< store PF mirror rules configuration*/
200 struct ixgbe_vf_info {
201 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
202 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
203 uint16_t num_vf_mc_hashes;
204 uint16_t default_vf_vlan_id;
205 uint16_t vlans_enabled;
207 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
209 uint8_t spoofchk_enabled;
214 * Possible l4type of 5tuple filters.
216 enum ixgbe_5tuple_protocol {
217 IXGBE_FILTER_PROTOCOL_TCP = 0,
218 IXGBE_FILTER_PROTOCOL_UDP,
219 IXGBE_FILTER_PROTOCOL_SCTP,
220 IXGBE_FILTER_PROTOCOL_NONE,
223 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
225 struct ixgbe_5tuple_filter_info {
230 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
231 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
232 used when more than one filter matches. */
233 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
234 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
235 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
236 src_port_mask:1, /* if mask is 1b, do not compare src port. */
237 proto_mask:1; /* if mask is 1b, do not compare protocol. */
240 /* 5tuple filter structure */
241 struct ixgbe_5tuple_filter {
242 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
243 uint16_t index; /* the index of 5tuple filter */
244 struct ixgbe_5tuple_filter_info filter_info;
245 uint16_t queue; /* rx queue assigned to */
248 #define IXGBE_5TUPLE_ARRAY_SIZE \
249 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
250 (sizeof(uint32_t) * NBBY))
253 * Structure to store filters' info.
255 struct ixgbe_filter_info {
256 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
257 /* store used ethertype filters*/
258 uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
259 /* Bit mask for every used 5tuple filter */
260 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
261 struct ixgbe_5tuple_filter_list fivetuple_list;
265 * Structure to store private data for each driver instance (for each port).
267 struct ixgbe_adapter {
269 struct ixgbe_hw_stats stats;
270 struct ixgbe_hw_fdir_info fdir;
271 struct ixgbe_interrupt intr;
272 struct ixgbe_stat_mapping_registers stat_mappings;
273 struct ixgbe_vfta shadow_vfta;
274 struct ixgbe_hwstrip hwstrip;
275 struct ixgbe_dcb_config dcb_config;
276 struct ixgbe_mirror_info mr_data;
277 struct ixgbe_vf_info *vfdata;
278 struct ixgbe_uta_info uta_info;
279 #ifdef RTE_NIC_BYPASS
280 struct ixgbe_bypass_info bps;
281 #endif /* RTE_NIC_BYPASS */
282 struct ixgbe_filter_info filter;
284 bool rx_bulk_alloc_allowed;
286 struct rte_timecounter systime_tc;
287 struct rte_timecounter rx_tstamp_tc;
288 struct rte_timecounter tx_tstamp_tc;
291 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
292 (&((struct ixgbe_adapter *)adapter)->hw)
294 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
295 (&((struct ixgbe_adapter *)adapter)->stats)
297 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
298 (&((struct ixgbe_adapter *)adapter)->intr)
300 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
301 (&((struct ixgbe_adapter *)adapter)->fdir)
303 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
304 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
306 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
307 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
309 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
310 (&((struct ixgbe_adapter *)adapter)->hwstrip)
312 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
313 (&((struct ixgbe_adapter *)adapter)->dcb_config)
315 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
316 (&((struct ixgbe_adapter *)adapter)->vfdata)
318 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
319 (&((struct ixgbe_adapter *)adapter)->mr_data)
321 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
322 (&((struct ixgbe_adapter *)adapter)->uta_info)
324 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
325 (&((struct ixgbe_adapter *)adapter)->filter)
328 * RX/TX function prototypes
330 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
332 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
334 void ixgbe_dev_rx_queue_release(void *rxq);
336 void ixgbe_dev_tx_queue_release(void *txq);
338 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
339 uint16_t nb_rx_desc, unsigned int socket_id,
340 const struct rte_eth_rxconf *rx_conf,
341 struct rte_mempool *mb_pool);
343 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
344 uint16_t nb_tx_desc, unsigned int socket_id,
345 const struct rte_eth_txconf *tx_conf);
347 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
348 uint16_t rx_queue_id);
350 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
351 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
353 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
355 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
357 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
359 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
361 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
363 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
365 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
367 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
368 struct rte_eth_rxq_info *qinfo);
370 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
371 struct rte_eth_txq_info *qinfo);
373 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
375 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
377 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
379 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
382 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
383 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
384 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
385 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
387 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
390 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
393 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
394 struct rte_eth_rss_conf *rss_conf);
396 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
397 struct rte_eth_rss_conf *rss_conf);
399 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
401 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
403 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
405 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
407 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
410 * Flow director function prototypes
412 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
414 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
417 * misc function prototypes
419 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
421 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
423 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
425 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
427 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
429 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
431 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
433 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
435 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
437 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
438 enum rte_filter_op filter_op, void *arg);
439 #endif /* _IXGBE_ETHDEV_H_ */