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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
43 /* need update link, bit flag */
44 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
45 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
46 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
47 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
50 * Defines that were not part of ixgbe_type.h as they are not used by the
53 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
54 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
55 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
56 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
57 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
58 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
59 #define IXGBE_NB_STAT_MAPPING_REGS 32
60 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
61 #define IXGBE_VFTA_SIZE 128
62 #define IXGBE_VLAN_TAG_SIZE 4
63 #define IXGBE_MAX_RX_QUEUE_NUM 128
64 #define IXGBE_MAX_INTR_QUEUE_NUM 15
65 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
66 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
67 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
70 #define NBBY 8 /* number of bits in a byte */
72 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
74 /* EITR Inteval is in 2048ns uinits for 1G and 10G link */
75 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
76 #define IXGBE_EITR_ITR_INT_SHIFT 3
77 #define IXGBE_EITR_INTERVAL_US(us) \
78 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
79 IXGBE_EITR_ITR_INT_MASK)
82 /* Loopback operation modes */
83 /* 82599 specific loopback operation types */
84 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
85 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
87 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
89 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
90 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
91 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
93 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
95 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
96 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
97 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
98 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
100 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
101 #define IXGBE_ETQF_SHIFT 16
102 #define IXGBE_ETQF_UP_EN 0x00080000
103 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
104 #define IXGBE_ETQF_MAX_PRI 7
106 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
107 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
108 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
110 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
111 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
112 #define IXGBE_L34T_IMIR_LLI 0x00100000
113 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
114 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
115 #define IXGBE_5TUPLE_MAX_PRI 7
116 #define IXGBE_5TUPLE_MIN_PRI 1
118 #define IXGBE_RSS_OFFLOAD_ALL ( \
120 ETH_RSS_NONFRAG_IPV4_TCP | \
121 ETH_RSS_NONFRAG_IPV4_UDP | \
123 ETH_RSS_NONFRAG_IPV6_TCP | \
124 ETH_RSS_NONFRAG_IPV6_UDP | \
126 ETH_RSS_IPV6_TCP_EX | \
129 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
130 #define IXGBE_VF_MAXMSIVECTOR 1
132 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
133 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
135 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
137 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
139 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
140 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
143 * Information about the fdir mode.
145 struct ixgbe_hw_fdir_mask {
146 uint16_t vlan_tci_mask;
147 uint32_t src_ipv4_mask;
148 uint32_t dst_ipv4_mask;
149 uint16_t src_ipv6_mask;
150 uint16_t dst_ipv6_mask;
151 uint16_t src_port_mask;
152 uint16_t dst_port_mask;
153 uint16_t flex_bytes_mask;
154 uint8_t mac_addr_byte_mask;
155 uint32_t tunnel_id_mask;
156 uint8_t tunnel_type_mask;
159 struct ixgbe_fdir_filter {
160 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
161 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
162 uint32_t fdirflags; /* drop or forward */
163 uint32_t fdirhash; /* hash value for fdir */
164 uint8_t queue; /* assigned rx queue */
167 /* list of fdir filters */
168 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
170 struct ixgbe_fdir_rule {
171 struct ixgbe_hw_fdir_mask mask;
172 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
173 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
174 bool b_mask; /* If TRUE, mask has meaning. */
175 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
176 uint32_t fdirflags; /* drop or forward */
177 uint32_t soft_id; /* an unique value for this rule */
178 uint8_t queue; /* assigned rx queue */
181 struct ixgbe_hw_fdir_info {
182 struct ixgbe_hw_fdir_mask mask;
183 uint8_t flex_bytes_offset;
192 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
193 /* store the pointers of the filters, index is the hash value. */
194 struct ixgbe_fdir_filter **hash_map;
195 struct rte_hash *hash_handle; /* cuckoo hash handler */
196 bool mask_added; /* If already got mask from consistent filter */
199 /* structure for interrupt relative data */
200 struct ixgbe_interrupt {
205 struct ixgbe_stat_mapping_registers {
206 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
207 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
211 uint32_t vfta[IXGBE_VFTA_SIZE];
214 struct ixgbe_hwstrip {
215 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
219 * VF data which used by PF host only
221 #define IXGBE_MAX_VF_MC_ENTRIES 30
222 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
223 #define IXGBE_MAX_UTA 128
225 struct ixgbe_uta_info {
226 uint8_t uc_filter_type;
228 uint32_t uta_shadow[IXGBE_MAX_UTA];
231 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
233 struct ixgbe_mirror_info {
234 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
235 /**< store PF mirror rules configuration*/
238 struct ixgbe_vf_info {
239 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
240 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
241 uint16_t num_vf_mc_hashes;
242 uint16_t default_vf_vlan_id;
243 uint16_t vlans_enabled;
245 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
247 uint8_t spoofchk_enabled;
252 * Possible l4type of 5tuple filters.
254 enum ixgbe_5tuple_protocol {
255 IXGBE_FILTER_PROTOCOL_TCP = 0,
256 IXGBE_FILTER_PROTOCOL_UDP,
257 IXGBE_FILTER_PROTOCOL_SCTP,
258 IXGBE_FILTER_PROTOCOL_NONE,
261 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
263 struct ixgbe_5tuple_filter_info {
268 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
269 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
270 used when more than one filter matches. */
271 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
272 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
273 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
274 src_port_mask:1, /* if mask is 1b, do not compare src port. */
275 proto_mask:1; /* if mask is 1b, do not compare protocol. */
278 /* 5tuple filter structure */
279 struct ixgbe_5tuple_filter {
280 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
281 uint16_t index; /* the index of 5tuple filter */
282 struct ixgbe_5tuple_filter_info filter_info;
283 uint16_t queue; /* rx queue assigned to */
286 #define IXGBE_5TUPLE_ARRAY_SIZE \
287 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
288 (sizeof(uint32_t) * NBBY))
290 struct ixgbe_ethertype_filter {
295 * If this filter is added by configuration,
296 * it should not be removed.
302 * Structure to store filters' info.
304 struct ixgbe_filter_info {
305 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
306 /* store used ethertype filters*/
307 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
308 /* Bit mask for every used 5tuple filter */
309 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
310 struct ixgbe_5tuple_filter_list fivetuple_list;
311 /* store the SYN filter info */
315 struct ixgbe_l2_tn_key {
316 enum rte_eth_tunnel_type l2_tn_type;
320 struct ixgbe_l2_tn_filter {
321 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
322 struct ixgbe_l2_tn_key key;
326 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
328 struct ixgbe_l2_tn_info {
329 struct ixgbe_l2_tn_filter_list l2_tn_list;
330 struct ixgbe_l2_tn_filter **hash_map;
331 struct rte_hash *hash_handle;
332 bool e_tag_en; /* e-tag enabled */
333 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
334 bool e_tag_ether_type; /* ether type for e-tag */
338 * Statistics counters collected by the MACsec
340 struct ixgbe_macsec_stats {
341 /* TX port statistics */
342 uint64_t out_pkts_untagged;
343 uint64_t out_pkts_encrypted;
344 uint64_t out_pkts_protected;
345 uint64_t out_octets_encrypted;
346 uint64_t out_octets_protected;
348 /* RX port statistics */
349 uint64_t in_pkts_untagged;
350 uint64_t in_pkts_badtag;
351 uint64_t in_pkts_nosci;
352 uint64_t in_pkts_unknownsci;
353 uint64_t in_octets_decrypted;
354 uint64_t in_octets_validated;
356 /* RX SC statistics */
357 uint64_t in_pkts_unchecked;
358 uint64_t in_pkts_delayed;
359 uint64_t in_pkts_late;
361 /* RX SA statistics */
363 uint64_t in_pkts_invalid;
364 uint64_t in_pkts_notvalid;
365 uint64_t in_pkts_unusedsa;
366 uint64_t in_pkts_notusingsa;
370 * Structure to store private data for each driver instance (for each port).
372 struct ixgbe_adapter {
374 struct ixgbe_hw_stats stats;
375 struct ixgbe_macsec_stats macsec_stats;
376 struct ixgbe_hw_fdir_info fdir;
377 struct ixgbe_interrupt intr;
378 struct ixgbe_stat_mapping_registers stat_mappings;
379 struct ixgbe_vfta shadow_vfta;
380 struct ixgbe_hwstrip hwstrip;
381 struct ixgbe_dcb_config dcb_config;
382 struct ixgbe_mirror_info mr_data;
383 struct ixgbe_vf_info *vfdata;
384 struct ixgbe_uta_info uta_info;
385 #ifdef RTE_NIC_BYPASS
386 struct ixgbe_bypass_info bps;
387 #endif /* RTE_NIC_BYPASS */
388 struct ixgbe_filter_info filter;
389 struct ixgbe_l2_tn_info l2_tn;
391 bool rx_bulk_alloc_allowed;
393 struct rte_timecounter systime_tc;
394 struct rte_timecounter rx_tstamp_tc;
395 struct rte_timecounter tx_tstamp_tc;
398 #define IXGBE_DEV_TO_PCI(eth_dev) \
399 RTE_DEV_TO_PCI((eth_dev)->device)
401 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
402 (&((struct ixgbe_adapter *)adapter)->hw)
404 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
405 (&((struct ixgbe_adapter *)adapter)->stats)
407 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
408 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
410 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
411 (&((struct ixgbe_adapter *)adapter)->intr)
413 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
414 (&((struct ixgbe_adapter *)adapter)->fdir)
416 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
417 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
419 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
420 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
422 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
423 (&((struct ixgbe_adapter *)adapter)->hwstrip)
425 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
426 (&((struct ixgbe_adapter *)adapter)->dcb_config)
428 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
429 (&((struct ixgbe_adapter *)adapter)->vfdata)
431 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
432 (&((struct ixgbe_adapter *)adapter)->mr_data)
434 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
435 (&((struct ixgbe_adapter *)adapter)->uta_info)
437 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
438 (&((struct ixgbe_adapter *)adapter)->filter)
440 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
441 (&((struct ixgbe_adapter *)adapter)->l2_tn)
444 * RX/TX function prototypes
446 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
448 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
450 void ixgbe_dev_rx_queue_release(void *rxq);
452 void ixgbe_dev_tx_queue_release(void *txq);
454 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
455 uint16_t nb_rx_desc, unsigned int socket_id,
456 const struct rte_eth_rxconf *rx_conf,
457 struct rte_mempool *mb_pool);
459 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
460 uint16_t nb_tx_desc, unsigned int socket_id,
461 const struct rte_eth_txconf *tx_conf);
463 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
464 uint16_t rx_queue_id);
466 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
467 int ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
469 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
471 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
473 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
475 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
477 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
479 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
481 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
483 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
484 struct rte_eth_rxq_info *qinfo);
486 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
487 struct rte_eth_txq_info *qinfo);
489 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
491 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
493 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
495 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
498 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
501 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
502 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
503 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
504 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
506 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
509 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
512 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
515 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
516 struct rte_eth_rss_conf *rss_conf);
518 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
519 struct rte_eth_rss_conf *rss_conf);
521 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
523 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
525 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
527 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
529 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
532 * Flow director function prototypes
534 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
535 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
536 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
537 struct ixgbe_fdir_rule *rule,
538 bool del, bool update);
540 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
543 * misc function prototypes
545 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
547 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
549 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
551 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
553 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
555 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
557 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
559 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
561 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
563 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
564 enum rte_filter_op filter_op, void *arg);
565 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
566 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
568 extern const struct rte_flow_ops ixgbe_flow_ops;
570 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
571 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
572 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
573 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
575 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
577 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
580 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
585 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
586 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
587 (filter_info->ethertype_mask & (1 << i)))
594 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
595 struct ixgbe_ethertype_filter *ethertype_filter)
599 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
600 if (!(filter_info->ethertype_mask & (1 << i))) {
601 filter_info->ethertype_mask |= 1 << i;
602 filter_info->ethertype_filters[i].ethertype =
603 ethertype_filter->ethertype;
604 filter_info->ethertype_filters[i].etqf =
605 ethertype_filter->etqf;
606 filter_info->ethertype_filters[i].etqs =
607 ethertype_filter->etqs;
608 filter_info->ethertype_filters[i].conf =
609 ethertype_filter->conf;
617 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
620 if (idx >= IXGBE_MAX_ETQF_FILTERS)
622 filter_info->ethertype_mask &= ~(1 << idx);
623 filter_info->ethertype_filters[idx].ethertype = 0;
624 filter_info->ethertype_filters[idx].etqf = 0;
625 filter_info->ethertype_filters[idx].etqs = 0;
626 filter_info->ethertype_filters[idx].etqs = FALSE;
630 #endif /* _IXGBE_ETHDEV_H_ */