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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_type.h"
37 #include "base/ixgbe_dcb.h"
38 #include "base/ixgbe_dcb_82599.h"
39 #include "base/ixgbe_dcb_82598.h"
40 #include "ixgbe_bypass.h"
41 #include "ixgbe_ipsec.h"
45 #include <rte_tm_driver.h>
47 /* need update link, bit flag */
48 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
49 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
50 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
51 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
52 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
55 * Defines that were not part of ixgbe_type.h as they are not used by the
58 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
59 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
60 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
61 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
62 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
63 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
64 #define IXGBE_NB_STAT_MAPPING_REGS 32
65 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
66 #define IXGBE_VFTA_SIZE 128
67 #define IXGBE_VLAN_TAG_SIZE 4
68 #define IXGBE_MAX_RX_QUEUE_NUM 128
69 #define IXGBE_MAX_INTR_QUEUE_NUM 15
70 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
71 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
72 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
75 #define NBBY 8 /* number of bits in a byte */
77 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
79 /* EITR Interval is in 2048ns uinits for 1G and 10G link */
80 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
81 #define IXGBE_EITR_ITR_INT_SHIFT 3
82 #define IXGBE_EITR_INTERVAL_US(us) \
83 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
84 IXGBE_EITR_ITR_INT_MASK)
87 /* Loopback operation modes */
88 /* 82599 specific loopback operation types */
89 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
90 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
92 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
94 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
95 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
96 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
98 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
100 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
101 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
102 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
103 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
105 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
106 #define IXGBE_ETQF_SHIFT 16
107 #define IXGBE_ETQF_UP_EN 0x00080000
108 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
109 #define IXGBE_ETQF_MAX_PRI 7
111 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
112 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
113 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
115 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
116 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
117 #define IXGBE_L34T_IMIR_LLI 0x00100000
118 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
119 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
120 #define IXGBE_5TUPLE_MAX_PRI 7
121 #define IXGBE_5TUPLE_MIN_PRI 1
123 #define IXGBE_RSS_OFFLOAD_ALL ( \
125 ETH_RSS_NONFRAG_IPV4_TCP | \
126 ETH_RSS_NONFRAG_IPV4_UDP | \
128 ETH_RSS_NONFRAG_IPV6_TCP | \
129 ETH_RSS_NONFRAG_IPV6_UDP | \
131 ETH_RSS_IPV6_TCP_EX | \
134 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
135 #define IXGBE_VF_MAXMSIVECTOR 1
137 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
138 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
140 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
142 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
144 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
145 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
147 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
148 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
152 #define MAC_TYPE_FILTER_SUP(type) do {\
153 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
154 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
155 (type) != ixgbe_mac_X550EM_a)\
159 /* Link speed for X550 auto negotiation */
160 #define IXGBE_LINK_SPEED_X550_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
161 IXGBE_LINK_SPEED_1GB_FULL | \
162 IXGBE_LINK_SPEED_2_5GB_FULL | \
163 IXGBE_LINK_SPEED_5GB_FULL | \
164 IXGBE_LINK_SPEED_10GB_FULL)
167 * Information about the fdir mode.
169 struct ixgbe_hw_fdir_mask {
170 uint16_t vlan_tci_mask;
171 uint32_t src_ipv4_mask;
172 uint32_t dst_ipv4_mask;
173 uint16_t src_ipv6_mask;
174 uint16_t dst_ipv6_mask;
175 uint16_t src_port_mask;
176 uint16_t dst_port_mask;
177 uint16_t flex_bytes_mask;
178 uint8_t mac_addr_byte_mask;
179 uint32_t tunnel_id_mask;
180 uint8_t tunnel_type_mask;
183 struct ixgbe_fdir_filter {
184 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
185 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
186 uint32_t fdirflags; /* drop or forward */
187 uint32_t fdirhash; /* hash value for fdir */
188 uint8_t queue; /* assigned rx queue */
191 /* list of fdir filters */
192 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
194 struct ixgbe_fdir_rule {
195 struct ixgbe_hw_fdir_mask mask;
196 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
197 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
198 bool b_mask; /* If TRUE, mask has meaning. */
199 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
200 uint32_t fdirflags; /* drop or forward */
201 uint32_t soft_id; /* an unique value for this rule */
202 uint8_t queue; /* assigned rx queue */
203 uint8_t flex_bytes_offset;
206 struct ixgbe_hw_fdir_info {
207 struct ixgbe_hw_fdir_mask mask;
208 uint8_t flex_bytes_offset;
217 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
218 /* store the pointers of the filters, index is the hash value. */
219 struct ixgbe_fdir_filter **hash_map;
220 struct rte_hash *hash_handle; /* cuckoo hash handler */
221 bool mask_added; /* If already got mask from consistent filter */
224 /* structure for interrupt relative data */
225 struct ixgbe_interrupt {
228 /*to save original mask during delayed handler */
229 uint32_t mask_original;
232 struct ixgbe_stat_mapping_registers {
233 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
234 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
238 uint32_t vfta[IXGBE_VFTA_SIZE];
241 struct ixgbe_hwstrip {
242 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
246 * VF data which used by PF host only
248 #define IXGBE_MAX_VF_MC_ENTRIES 30
249 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
250 #define IXGBE_MAX_UTA 128
252 struct ixgbe_uta_info {
253 uint8_t uc_filter_type;
255 uint32_t uta_shadow[IXGBE_MAX_UTA];
258 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
260 struct ixgbe_mirror_info {
261 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
262 /**< store PF mirror rules configuration*/
265 struct ixgbe_vf_info {
266 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
267 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
268 uint16_t num_vf_mc_hashes;
269 uint16_t default_vf_vlan_id;
270 uint16_t vlans_enabled;
272 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
274 uint8_t spoofchk_enabled;
279 * Possible l4type of 5tuple filters.
281 enum ixgbe_5tuple_protocol {
282 IXGBE_FILTER_PROTOCOL_TCP = 0,
283 IXGBE_FILTER_PROTOCOL_UDP,
284 IXGBE_FILTER_PROTOCOL_SCTP,
285 IXGBE_FILTER_PROTOCOL_NONE,
288 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
290 struct ixgbe_5tuple_filter_info {
295 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
296 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
297 used when more than one filter matches. */
298 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
299 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
300 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
301 src_port_mask:1, /* if mask is 1b, do not compare src port. */
302 proto_mask:1; /* if mask is 1b, do not compare protocol. */
305 /* 5tuple filter structure */
306 struct ixgbe_5tuple_filter {
307 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
308 uint16_t index; /* the index of 5tuple filter */
309 struct ixgbe_5tuple_filter_info filter_info;
310 uint16_t queue; /* rx queue assigned to */
313 #define IXGBE_5TUPLE_ARRAY_SIZE \
314 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
315 (sizeof(uint32_t) * NBBY))
317 struct ixgbe_ethertype_filter {
322 * If this filter is added by configuration,
323 * it should not be removed.
329 * Structure to store filters' info.
331 struct ixgbe_filter_info {
332 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
333 /* store used ethertype filters*/
334 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
335 /* Bit mask for every used 5tuple filter */
336 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
337 struct ixgbe_5tuple_filter_list fivetuple_list;
338 /* store the SYN filter info */
342 struct ixgbe_l2_tn_key {
343 enum rte_eth_tunnel_type l2_tn_type;
347 struct ixgbe_l2_tn_filter {
348 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
349 struct ixgbe_l2_tn_key key;
353 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
355 struct ixgbe_l2_tn_info {
356 struct ixgbe_l2_tn_filter_list l2_tn_list;
357 struct ixgbe_l2_tn_filter **hash_map;
358 struct rte_hash *hash_handle;
359 bool e_tag_en; /* e-tag enabled */
360 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
361 bool e_tag_ether_type; /* ether type for e-tag */
365 enum rte_filter_type filter_type;
370 * Statistics counters collected by the MACsec
372 struct ixgbe_macsec_stats {
373 /* TX port statistics */
374 uint64_t out_pkts_untagged;
375 uint64_t out_pkts_encrypted;
376 uint64_t out_pkts_protected;
377 uint64_t out_octets_encrypted;
378 uint64_t out_octets_protected;
380 /* RX port statistics */
381 uint64_t in_pkts_untagged;
382 uint64_t in_pkts_badtag;
383 uint64_t in_pkts_nosci;
384 uint64_t in_pkts_unknownsci;
385 uint64_t in_octets_decrypted;
386 uint64_t in_octets_validated;
388 /* RX SC statistics */
389 uint64_t in_pkts_unchecked;
390 uint64_t in_pkts_delayed;
391 uint64_t in_pkts_late;
393 /* RX SA statistics */
395 uint64_t in_pkts_invalid;
396 uint64_t in_pkts_notvalid;
397 uint64_t in_pkts_unusedsa;
398 uint64_t in_pkts_notusingsa;
401 /* The configuration of bandwidth */
402 struct ixgbe_bw_conf {
403 uint8_t tc_num; /* Number of TCs. */
406 /* Struct to store Traffic Manager shaper profile. */
407 struct ixgbe_tm_shaper_profile {
408 TAILQ_ENTRY(ixgbe_tm_shaper_profile) node;
409 uint32_t shaper_profile_id;
410 uint32_t reference_count;
411 struct rte_tm_shaper_params profile;
414 TAILQ_HEAD(ixgbe_shaper_profile_list, ixgbe_tm_shaper_profile);
416 /* node type of Traffic Manager */
417 enum ixgbe_tm_node_type {
418 IXGBE_TM_NODE_TYPE_PORT,
419 IXGBE_TM_NODE_TYPE_TC,
420 IXGBE_TM_NODE_TYPE_QUEUE,
421 IXGBE_TM_NODE_TYPE_MAX,
424 /* Struct to store Traffic Manager node configuration. */
425 struct ixgbe_tm_node {
426 TAILQ_ENTRY(ixgbe_tm_node) node;
430 uint32_t reference_count;
432 struct ixgbe_tm_node *parent;
433 struct ixgbe_tm_shaper_profile *shaper_profile;
434 struct rte_tm_node_params params;
437 TAILQ_HEAD(ixgbe_tm_node_list, ixgbe_tm_node);
439 /* The configuration of Traffic Manager */
440 struct ixgbe_tm_conf {
441 struct ixgbe_shaper_profile_list shaper_profile_list;
442 struct ixgbe_tm_node *root; /* root node - port */
443 struct ixgbe_tm_node_list tc_list; /* node list for all the TCs */
444 struct ixgbe_tm_node_list queue_list; /* node list for all the queues */
446 * The number of added TC nodes.
447 * It should be no more than the TC number of this port.
451 * The number of added queue nodes.
452 * It should be no more than the queue number of this port.
454 uint32_t nb_queue_node;
456 * This flag is used to check if APP can change the TM node
458 * When it's true, means the configuration is applied to HW,
459 * APP should not change the configuration.
460 * As we don't support on-the-fly configuration, when starting
461 * the port, APP should call the hierarchy_commit API to set this
462 * flag to true. When stopping the port, this flag should be set
469 * Structure to store private data for each driver instance (for each port).
471 struct ixgbe_adapter {
473 struct ixgbe_hw_stats stats;
474 struct ixgbe_macsec_stats macsec_stats;
475 struct ixgbe_hw_fdir_info fdir;
476 struct ixgbe_interrupt intr;
477 struct ixgbe_stat_mapping_registers stat_mappings;
478 struct ixgbe_vfta shadow_vfta;
479 struct ixgbe_hwstrip hwstrip;
480 struct ixgbe_dcb_config dcb_config;
481 struct ixgbe_mirror_info mr_data;
482 struct ixgbe_vf_info *vfdata;
483 struct ixgbe_uta_info uta_info;
484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
485 struct ixgbe_bypass_info bps;
486 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
487 struct ixgbe_filter_info filter;
488 struct ixgbe_l2_tn_info l2_tn;
489 struct ixgbe_bw_conf bw_conf;
490 struct ixgbe_ipsec ipsec;
491 bool rx_bulk_alloc_allowed;
493 struct rte_timecounter systime_tc;
494 struct rte_timecounter rx_tstamp_tc;
495 struct rte_timecounter tx_tstamp_tc;
496 struct ixgbe_tm_conf tm_conf;
499 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
500 (&((struct ixgbe_adapter *)adapter)->hw)
502 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
503 (&((struct ixgbe_adapter *)adapter)->stats)
505 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
506 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
508 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
509 (&((struct ixgbe_adapter *)adapter)->intr)
511 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
512 (&((struct ixgbe_adapter *)adapter)->fdir)
514 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
515 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
517 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
518 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
520 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
521 (&((struct ixgbe_adapter *)adapter)->hwstrip)
523 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
524 (&((struct ixgbe_adapter *)adapter)->dcb_config)
526 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
527 (&((struct ixgbe_adapter *)adapter)->vfdata)
529 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
530 (&((struct ixgbe_adapter *)adapter)->mr_data)
532 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
533 (&((struct ixgbe_adapter *)adapter)->uta_info)
535 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
536 (&((struct ixgbe_adapter *)adapter)->filter)
538 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
539 (&((struct ixgbe_adapter *)adapter)->l2_tn)
541 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \
542 (&((struct ixgbe_adapter *)adapter)->bw_conf)
544 #define IXGBE_DEV_PRIVATE_TO_TM_CONF(adapter) \
545 (&((struct ixgbe_adapter *)adapter)->tm_conf)
547 #define IXGBE_DEV_PRIVATE_TO_IPSEC(adapter)\
548 (&((struct ixgbe_adapter *)adapter)->ipsec)
551 * RX/TX function prototypes
553 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
555 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
557 void ixgbe_dev_rx_queue_release(void *rxq);
559 void ixgbe_dev_tx_queue_release(void *txq);
561 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
562 uint16_t nb_rx_desc, unsigned int socket_id,
563 const struct rte_eth_rxconf *rx_conf,
564 struct rte_mempool *mb_pool);
566 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
567 uint16_t nb_tx_desc, unsigned int socket_id,
568 const struct rte_eth_txconf *tx_conf);
570 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
571 uint16_t rx_queue_id);
573 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
575 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
576 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
578 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
580 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
582 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
584 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
586 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
588 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
590 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
592 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
593 struct rte_eth_rxq_info *qinfo);
595 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
596 struct rte_eth_txq_info *qinfo);
598 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
600 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
602 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
604 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
607 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
610 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
611 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
612 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
613 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
615 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
618 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
621 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
624 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
625 struct rte_eth_rss_conf *rss_conf);
627 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
628 struct rte_eth_rss_conf *rss_conf);
630 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
632 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
634 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
636 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
638 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
640 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
641 struct rte_eth_ntuple_filter *filter,
643 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
644 struct rte_eth_ethertype_filter *filter,
646 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
647 struct rte_eth_syn_filter *filter,
650 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
651 struct rte_eth_l2_tunnel_conf *l2_tunnel,
654 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
655 struct rte_eth_l2_tunnel_conf *l2_tunnel);
656 void ixgbe_filterlist_init(void);
657 void ixgbe_filterlist_flush(void);
659 * Flow director function prototypes
661 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
662 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
663 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
665 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
666 struct ixgbe_fdir_rule *rule,
667 bool del, bool update);
669 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
672 * misc function prototypes
674 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
676 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
678 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
680 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
682 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
684 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
686 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
688 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
690 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
692 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
693 enum rte_filter_op filter_op, void *arg);
694 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
695 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
697 extern const struct rte_flow_ops ixgbe_flow_ops;
699 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
700 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
701 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
702 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
704 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
706 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
708 int ixgbe_vt_check(struct ixgbe_hw *hw);
709 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
710 uint16_t tx_rate, uint64_t q_msk);
711 bool is_ixgbe_supported(struct rte_eth_dev *dev);
712 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
713 void ixgbe_tm_conf_init(struct rte_eth_dev *dev);
714 void ixgbe_tm_conf_uninit(struct rte_eth_dev *dev);
715 int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
719 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
724 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
725 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
726 (filter_info->ethertype_mask & (1 << i)))
733 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
734 struct ixgbe_ethertype_filter *ethertype_filter)
738 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
739 if (!(filter_info->ethertype_mask & (1 << i))) {
740 filter_info->ethertype_mask |= 1 << i;
741 filter_info->ethertype_filters[i].ethertype =
742 ethertype_filter->ethertype;
743 filter_info->ethertype_filters[i].etqf =
744 ethertype_filter->etqf;
745 filter_info->ethertype_filters[i].etqs =
746 ethertype_filter->etqs;
747 filter_info->ethertype_filters[i].conf =
748 ethertype_filter->conf;
756 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
759 if (idx >= IXGBE_MAX_ETQF_FILTERS)
761 filter_info->ethertype_mask &= ~(1 << idx);
762 filter_info->ethertype_filters[idx].ethertype = 0;
763 filter_info->ethertype_filters[idx].etqf = 0;
764 filter_info->ethertype_filters[idx].etqs = 0;
765 filter_info->ethertype_filters[idx].etqs = FALSE;
769 #endif /* _IXGBE_ETHDEV_H_ */