drivers/net/ixgbe/ixgbe_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdint.h>
  36 #include <stdarg.h>
  37 #include <errno.h>
  38 #include <sys/queue.h>
  39
  40 #include <rte_interrupts.h>
  41 #include <rte_log.h>
  42 #include <rte_debug.h>
  43 #include <rte_pci.h>
  44 #include <rte_ether.h>
  45 #include <rte_ethdev.h>
  46 #include <rte_malloc.h>
  47
  48 #include "ixgbe_logs.h"
  49 #include "base/ixgbe_api.h"
  50 #include "base/ixgbe_common.h"
  51 #include "ixgbe_ethdev.h"
  52
  53 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
  54 #define FDIRCTRL_PBALLOC_MASK           0x03
  55
  56 /* For calculating memory required for FDIR filters */
  57 #define PBALLOC_SIZE_SHIFT              15
  58
  59 /* Number of bits used to mask bucket hash for different pballoc sizes */
  60 #define PERFECT_BUCKET_64KB_HASH_MASK   0x07FF  /* 11 bits */
  61 #define PERFECT_BUCKET_128KB_HASH_MASK  0x0FFF  /* 12 bits */
  62 #define PERFECT_BUCKET_256KB_HASH_MASK  0x1FFF  /* 13 bits */
  63 #define SIG_BUCKET_64KB_HASH_MASK       0x1FFF  /* 13 bits */
  64 #define SIG_BUCKET_128KB_HASH_MASK      0x3FFF  /* 14 bits */
  65 #define SIG_BUCKET_256KB_HASH_MASK      0x7FFF  /* 15 bits */
  66 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET  12 /* default flexbytes offset in bytes */
  67 #define IXGBE_FDIR_MAX_FLEX_LEN         2 /* len in bytes of flexbytes */
  68 #define IXGBE_MAX_FLX_SOURCE_OFF        62
  69 #define IXGBE_FDIRCTRL_FLEX_MASK        (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
  70 #define IXGBE_FDIRCMD_CMD_INTERVAL_US   10
  71
  72 #define IXGBE_FDIR_FLOW_TYPES ( \
  73         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  74         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  75         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  76         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  77         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
  78         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
  79         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
  80         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
  81
  82 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
  83         uint8_t ipv6_addr[16]; \
  84         uint8_t i; \
  85         rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
  86         (ipv6m) = 0; \
  87         for (i = 0; i < sizeof(ipv6_addr); i++) { \
  88                 if (ipv6_addr[i] == UINT8_MAX) \
  89                         (ipv6m) |= 1 << i; \
  90                 else if (ipv6_addr[i] != 0) { \
  91                         PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
  92                         return -EINVAL; \
  93                 } \
  94         } \
  95 } while (0)
  96
  97 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
  98         uint8_t ipv6_addr[16]; \
  99         uint8_t i; \
 100         for (i = 0; i < sizeof(ipv6_addr); i++) { \
 101                 if ((ipv6m) & (1 << i)) \
 102                         ipv6_addr[i] = UINT8_MAX; \
 103                 else \
 104                         ipv6_addr[i] = 0; \
 105         } \
 106         rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
 107 } while (0)
 108
 109 #define DEFAULT_VXLAN_PORT 4789
 110 #define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4
 111
 112 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
 113 static int fdir_set_input_mask(struct rte_eth_dev *dev,
 114                                const struct rte_eth_fdir_masks *input_mask);
 115 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev);
 116 static int fdir_set_input_mask_x550(struct rte_eth_dev *dev);
 117 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
 118                 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);
 119 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
 120 static int ixgbe_fdir_filter_to_atr_input(
 121                 const struct rte_eth_fdir_filter *fdir_filter,
 122                 union ixgbe_atr_input *input,
 123                 enum rte_fdir_mode mode);
 124 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
 125                                  uint32_t key);
 126 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
 127                 enum rte_fdir_pballoc_type pballoc);
 128 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 129                 enum rte_fdir_pballoc_type pballoc);
 130 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 131                         union ixgbe_atr_input *input, uint8_t queue,
 132                         uint32_t fdircmd, uint32_t fdirhash,
 133                         enum rte_fdir_mode mode);
 134 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 135                 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
 136                 uint32_t fdirhash);
 137 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
 138                               const struct rte_eth_fdir_filter *fdir_filter,
 139                               bool del,
 140                               bool update);
 141 static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
 142 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
 143                         struct rte_eth_fdir_info *fdir_info);
 144 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
 145                         struct rte_eth_fdir_stats *fdir_stats);
 146
 147 /**
 148  * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.
 149  * It adds extra configuration of fdirctrl that is common for all filter types.
 150  *
 151  *  Initialize Flow Director control registers
 152  *  @hw: pointer to hardware structure
 153  *  @fdirctrl: value to write to flow director control register
 154  **/
 155 static int
 156 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
 157 {
 158         int i;
 159
 160         PMD_INIT_FUNC_TRACE();
 161
 162         /* Prime the keys for hashing */
 163         IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
 164         IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 165
 166         /*
 167          * Continue setup of fdirctrl register bits:
 168          *  Set the maximum length per hash bucket to 0xA filters
 169          *  Send interrupt when 64 filters are left
 170          */
 171         fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
 172                     (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
 173
 174         /*
 175          * Poll init-done after we write the register.  Estimated times:
 176          *      10G: PBALLOC = 11b, timing is 60us
 177          *       1G: PBALLOC = 11b, timing is 600us
 178          *     100M: PBALLOC = 11b, timing is 6ms
 179          *
 180          *     Multiple these timings by 4 if under full Rx load
 181          *
 182          * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 183          * 1 msec per poll time.  If we're at line rate and drop to 100M, then
 184          * this might not finish in our poll time, but we can live with that
 185          * for now.
 186          */
 187         IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 188         IXGBE_WRITE_FLUSH(hw);
 189         for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 190                 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
 191                                    IXGBE_FDIRCTRL_INIT_DONE)
 192                         break;
 193                 msec_delay(1);
 194         }
 195
 196         if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
 197                 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded during enabling!");
 198                 return -ETIMEDOUT;
 199         }
 200         return 0;
 201 }
 202
 203 /*
 204  * Set appropriate bits in fdirctrl for: variable reporting levels, moving
 205  * flexbytes matching field, and drop queue (only for perfect matching mode).
 206  */
 207 static inline int
 208 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
 209 {
 210         *fdirctrl = 0;
 211
 212         switch (conf->pballoc) {
 213         case RTE_FDIR_PBALLOC_64K:
 214                 /* 8k - 1 signature filters */
 215                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
 216                 break;
 217         case RTE_FDIR_PBALLOC_128K:
 218                 /* 16k - 1 signature filters */
 219                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
 220                 break;
 221         case RTE_FDIR_PBALLOC_256K:
 222                 /* 32k - 1 signature filters */
 223                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
 224                 break;
 225         default:
 226                 /* bad value */
 227                 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
 228                 return -EINVAL;
 229         };
 230
 231         /* status flags: write hash & swindex in the rx descriptor */
 232         switch (conf->status) {
 233         case RTE_FDIR_NO_REPORT_STATUS:
 234                 /* do nothing, default mode */
 235                 break;
 236         case RTE_FDIR_REPORT_STATUS:
 237                 /* report status when the packet matches a fdir rule */
 238                 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
 239                 break;
 240         case RTE_FDIR_REPORT_STATUS_ALWAYS:
 241                 /* always report status */
 242                 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
 243                 break;
 244         default:
 245                 /* bad value */
 246                 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
 247                 return -EINVAL;
 248         };
 249
 250         *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
 251                      IXGBE_FDIRCTRL_FLEX_SHIFT;
 252
 253         if (conf->mode >= RTE_FDIR_MODE_PERFECT &&
 254             conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
 255                 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
 256                 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
 257                 if (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
 258                         *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN
 259                                         << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
 260                 else if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
 261                         *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD
 262                                         << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
 263         }
 264
 265         return 0;
 266 }
 267
 268 /**
 269  * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
 270  *
 271  *  @hi_dword: Bits 31:16 mask to be bit swapped.
 272  *  @lo_dword: Bits 15:0  mask to be bit swapped.
 273  *
 274  *  Flow director uses several registers to store 2 x 16 bit masks with the
 275  *  bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
 276  *  mask affects the MS bit/byte of the target. This function reverses the
 277  *  bits in these masks.
 278  *  **/
 279 static inline uint32_t
 280 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
 281 {
 282         uint32_t mask = hi_dword << 16;
 283
 284         mask |= lo_dword;
 285         mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
 286         mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
 287         mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
 288         return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
 289 }
 290
 291 /*
 292  * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
 293  * but makes use of the rte_fdir_masks structure to see which bits to set.
 294  */
 295 static int
 296 fdir_set_input_mask_82599(struct rte_eth_dev *dev)
 297 {
 298         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 299         struct ixgbe_hw_fdir_info *info =
 300                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 301         /*
 302          * mask VM pool and DIPv6 since there are currently not supported
 303          * mask FLEX byte, it will be set in flex_conf
 304          */
 305         uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
 306         uint32_t fdirtcpm;  /* TCP source and destination port masks. */
 307         uint32_t fdiripv6m; /* IPv6 source and destination masks. */
 308         volatile uint32_t *reg;
 309
 310         PMD_INIT_FUNC_TRACE();
 311
 312         /*
 313          * Program the relevant mask registers.  If src/dst_port or src/dst_addr
 314          * are zero, then assume a full mask for that field. Also assume that
 315          * a VLAN of 0 is unspecified, so mask that out as well.  L4type
 316          * cannot be masked out in this implementation.
 317          */
 318         if (info->mask.dst_port_mask == 0 && info->mask.src_port_mask == 0)
 319                 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
 320                 fdirm |= IXGBE_FDIRM_L4P;
 321
 322         if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
 323                 /* mask VLAN Priority */
 324                 fdirm |= IXGBE_FDIRM_VLANP;
 325         else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
 326                 /* mask VLAN ID */
 327                 fdirm |= IXGBE_FDIRM_VLANID;
 328         else if (info->mask.vlan_tci_mask == 0)
 329                 /* mask VLAN ID and Priority */
 330                 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
 331         else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
 332                 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
 333                 return -EINVAL;
 334         }
 335
 336         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 337
 338         /* store the TCP/UDP port masks, bit reversed from port layout */
 339         fdirtcpm = reverse_fdir_bitmasks(
 340                         rte_be_to_cpu_16(info->mask.dst_port_mask),
 341                         rte_be_to_cpu_16(info->mask.src_port_mask));
 342
 343         /* write all the same so that UDP, TCP and SCTP use the same mask
 344          * (little-endian)
 345          */
 346         IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
 347         IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
 348         IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
 349
 350         /* Store source and destination IPv4 masks (big-endian),
 351          * can not use IXGBE_WRITE_REG.
 352          */
 353         reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRSIP4M);
 354         *reg = ~(info->mask.src_ipv4_mask);
 355         reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRDIP4M);
 356         *reg = ~(info->mask.dst_ipv4_mask);
 357
 358         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
 359                 /*
 360                  * Store source and destination IPv6 masks (bit reversed)
 361                  */
 362                 fdiripv6m = (info->mask.dst_ipv6_mask << 16) |
 363                             info->mask.src_ipv6_mask;
 364
 365                 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
 366         }
 367
 368         return IXGBE_SUCCESS;
 369 }
 370
 371 /*
 372  * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
 373  * but makes use of the rte_fdir_masks structure to see which bits to set.
 374  */
 375 static int
 376 fdir_set_input_mask_x550(struct rte_eth_dev *dev)
 377 {
 378         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 379         struct ixgbe_hw_fdir_info *info =
 380                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 381         /* mask VM pool and DIPv6 since there are currently not supported
 382          * mask FLEX byte, it will be set in flex_conf
 383          */
 384         uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 |
 385                          IXGBE_FDIRM_FLEX;
 386         uint32_t fdiripv6m;
 387         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 388         uint16_t mac_mask;
 389
 390         PMD_INIT_FUNC_TRACE();
 391
 392         /* set the default UDP port for VxLAN */
 393         if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
 394                 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT);
 395
 396         /* some bits must be set for mac vlan or tunnel mode */
 397         fdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P;
 398
 399         if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
 400                 /* mask VLAN Priority */
 401                 fdirm |= IXGBE_FDIRM_VLANP;
 402         else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
 403                 /* mask VLAN ID */
 404                 fdirm |= IXGBE_FDIRM_VLANID;
 405         else if (info->mask.vlan_tci_mask == 0)
 406                 /* mask VLAN ID and Priority */
 407                 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
 408         else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
 409                 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
 410                 return -EINVAL;
 411         }
 412
 413         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 414
 415         fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
 416         fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
 417         if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
 418                 fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |
 419                                 IXGBE_FDIRIP6M_TNI_VNI;
 420
 421         if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
 422                 mac_mask = info->mask.mac_addr_byte_mask;
 423                 fdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT)
 424                                 & IXGBE_FDIRIP6M_INNER_MAC;
 425
 426                 switch (info->mask.tunnel_type_mask) {
 427                 case 0:
 428                         /* Mask turnnel type */
 429                         fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
 430                         break;
 431                 case 1:
 432                         break;
 433                 default:
 434                         PMD_INIT_LOG(ERR, "invalid tunnel_type_mask");
 435                         return -EINVAL;
 436                 }
 437
 438                 switch (rte_be_to_cpu_32(info->mask.tunnel_id_mask)) {
 439                 case 0x0:
 440                         /* Mask vxlan id */
 441                         fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI;
 442                         break;
 443                 case 0x00FFFFFF:
 444                         fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
 445                         break;
 446                 case 0xFFFFFFFF:
 447                         break;
 448                 default:
 449                         PMD_INIT_LOG(ERR, "invalid tunnel_id_mask");
 450                         return -EINVAL;
 451                 }
 452         }
 453
 454         IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m);
 455         IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
 456         IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
 457         IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
 458         IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
 459         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
 460
 461         return IXGBE_SUCCESS;
 462 }
 463
 464 static int
 465 ixgbe_fdir_store_input_mask_82599(struct rte_eth_dev *dev,
 466                                   const struct rte_eth_fdir_masks *input_mask)
 467 {
 468         struct ixgbe_hw_fdir_info *info =
 469                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 470         uint16_t dst_ipv6m = 0;
 471         uint16_t src_ipv6m = 0;
 472
 473         memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
 474         info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 475         info->mask.src_port_mask = input_mask->src_port_mask;
 476         info->mask.dst_port_mask = input_mask->dst_port_mask;
 477         info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
 478         info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
 479         IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
 480         IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
 481         info->mask.src_ipv6_mask = src_ipv6m;
 482         info->mask.dst_ipv6_mask = dst_ipv6m;
 483
 484         return IXGBE_SUCCESS;
 485 }
 486
 487 static int
 488 ixgbe_fdir_store_input_mask_x550(struct rte_eth_dev *dev,
 489                                  const struct rte_eth_fdir_masks *input_mask)
 490 {
 491         struct ixgbe_hw_fdir_info *info =
 492                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 493
 494         memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
 495         info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 496         info->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask;
 497         info->mask.tunnel_type_mask = input_mask->tunnel_type_mask;
 498         info->mask.tunnel_id_mask = input_mask->tunnel_id_mask;
 499
 500         return IXGBE_SUCCESS;
 501 }
 502
 503 static int
 504 ixgbe_fdir_store_input_mask(struct rte_eth_dev *dev,
 505                             const struct rte_eth_fdir_masks *input_mask)
 506 {
 507         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 508
 509         if (mode >= RTE_FDIR_MODE_SIGNATURE &&
 510             mode <= RTE_FDIR_MODE_PERFECT)
 511                 return ixgbe_fdir_store_input_mask_82599(dev, input_mask);
 512         else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 513                  mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
 514                 return ixgbe_fdir_store_input_mask_x550(dev, input_mask);
 515
 516         PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
 517         return -ENOTSUP;
 518 }
 519
 520 int
 521 ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev)
 522 {
 523         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 524
 525         if (mode >= RTE_FDIR_MODE_SIGNATURE &&
 526             mode <= RTE_FDIR_MODE_PERFECT)
 527                 return fdir_set_input_mask_82599(dev);
 528         else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 529                  mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
 530                 return fdir_set_input_mask_x550(dev);
 531
 532         PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
 533         return -ENOTSUP;
 534 }
 535
 536 static int
 537 fdir_set_input_mask(struct rte_eth_dev *dev,
 538                     const struct rte_eth_fdir_masks *input_mask)
 539 {
 540         int ret;
 541
 542         ret = ixgbe_fdir_store_input_mask(dev, input_mask);
 543         if (ret)
 544                 return ret;
 545
 546         return ixgbe_fdir_set_input_mask(dev);
 547 }
 548
 549 /*
 550  * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
 551  * arguments are valid
 552  */
 553 static int
 554 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
 555                 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl)
 556 {
 557         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 558         struct ixgbe_hw_fdir_info *info =
 559                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 560         const struct rte_eth_flex_payload_cfg *flex_cfg;
 561         const struct rte_eth_fdir_flex_mask *flex_mask;
 562         uint32_t fdirm;
 563         uint16_t flexbytes = 0;
 564         uint16_t i;
 565
 566         fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
 567
 568         if (conf == NULL) {
 569                 PMD_DRV_LOG(ERR, "NULL pointer.");
 570                 return -EINVAL;
 571         }
 572
 573         for (i = 0; i < conf->nb_payloads; i++) {
 574                 flex_cfg = &conf->flex_set[i];
 575                 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
 576                         PMD_DRV_LOG(ERR, "unsupported payload type.");
 577                         return -EINVAL;
 578                 }
 579                 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
 580                     (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
 581                     (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
 582                         *fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
 583                         *fdirctrl |=
 584                                 (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
 585                                         IXGBE_FDIRCTRL_FLEX_SHIFT;
 586                 } else {
 587                         PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
 588                         return -EINVAL;
 589                 }
 590         }
 591
 592         for (i = 0; i < conf->nb_flexmasks; i++) {
 593                 flex_mask = &conf->flex_mask[i];
 594                 if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
 595                         PMD_DRV_LOG(ERR, "flexmask should be set globally.");
 596                         return -EINVAL;
 597                 }
 598                 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
 599                                         ((flex_mask->mask[1]) & 0xFF));
 600                 if (flexbytes == UINT16_MAX)
 601                         fdirm &= ~IXGBE_FDIRM_FLEX;
 602                 else if (flexbytes != 0) {
 603                         /* IXGBE_FDIRM_FLEX is set by default when set mask */
 604                         PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
 605                         return -EINVAL;
 606                 }
 607         }
 608         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 609         info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
 610         info->flex_bytes_offset = (uint8_t)((*fdirctrl &
 611                                             IXGBE_FDIRCTRL_FLEX_MASK) >>
 612                                             IXGBE_FDIRCTRL_FLEX_SHIFT);
 613         return 0;
 614 }
 615
 616 int
 617 ixgbe_fdir_configure(struct rte_eth_dev *dev)
 618 {
 619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 620         int err;
 621         uint32_t fdirctrl, pbsize;
 622         int i;
 623         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 624
 625         PMD_INIT_FUNC_TRACE();
 626
 627         if (hw->mac.type != ixgbe_mac_82599EB &&
 628                 hw->mac.type != ixgbe_mac_X540 &&
 629                 hw->mac.type != ixgbe_mac_X550 &&
 630                 hw->mac.type != ixgbe_mac_X550EM_x &&
 631                 hw->mac.type != ixgbe_mac_X550EM_a)
 632                 return -ENOSYS;
 633
 634         /* x550 supports mac-vlan and tunnel mode but other NICs not */
 635         if (hw->mac.type != ixgbe_mac_X550 &&
 636             hw->mac.type != ixgbe_mac_X550EM_x &&
 637             hw->mac.type != ixgbe_mac_X550EM_a &&
 638             mode != RTE_FDIR_MODE_SIGNATURE &&
 639             mode != RTE_FDIR_MODE_PERFECT)
 640                 return -ENOSYS;
 641
 642         err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
 643         if (err)
 644                 return err;
 645
 646         /*
 647          * Before enabling Flow Director, the Rx Packet Buffer size
 648          * must be reduced.  The new value is the current size minus
 649          * flow director memory usage size.
 650          */
 651         pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
 652         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
 653             (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
 654
 655         /*
 656          * The defaults in the HW for RX PB 1-7 are not zero and so should be
 657          * intialized to zero for non DCB mode otherwise actual total RX PB
 658          * would be bigger than programmed and filter space would run into
 659          * the PB 0 region.
 660          */
 661         for (i = 1; i < 8; i++)
 662                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
 663
 664         err = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask);
 665         if (err < 0) {
 666                 PMD_INIT_LOG(ERR, " Error on setting FD mask");
 667                 return err;
 668         }
 669         err = ixgbe_set_fdir_flex_conf(dev,
 670                 &dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl);
 671         if (err < 0) {
 672                 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
 673                 return err;
 674         }
 675
 676         err = fdir_enable_82599(hw, fdirctrl);
 677         if (err < 0) {
 678                 PMD_INIT_LOG(ERR, " Error on enabling FD.");
 679                 return err;
 680         }
 681         return 0;
 682 }
 683
 684 /*
 685  * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
 686  * by the IXGBE driver code.
 687  */
 688 static int
 689 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
 690                 union ixgbe_atr_input *input, enum rte_fdir_mode mode)
 691 {
 692         input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
 693         input->formatted.flex_bytes = (uint16_t)(
 694                 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
 695                 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
 696
 697         switch (fdir_filter->input.flow_type) {
 698         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 699                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
 700                 break;
 701         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 702                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
 703                 break;
 704         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 705                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
 706                 break;
 707         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 708                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
 709                 break;
 710         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 711                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
 712                 break;
 713         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 714                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
 715                 break;
 716         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 717                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
 718                 break;
 719         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 720                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
 721                 break;
 722         default:
 723                 break;
 724         }
 725
 726         switch (fdir_filter->input.flow_type) {
 727         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 728         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 729                 input->formatted.src_port =
 730                         fdir_filter->input.flow.udp4_flow.src_port;
 731                 input->formatted.dst_port =
 732                         fdir_filter->input.flow.udp4_flow.dst_port;
 733         /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
 734         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 735         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 736                 input->formatted.src_ip[0] =
 737                         fdir_filter->input.flow.ip4_flow.src_ip;
 738                 input->formatted.dst_ip[0] =
 739                         fdir_filter->input.flow.ip4_flow.dst_ip;
 740                 break;
 741
 742         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 743         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 744                 input->formatted.src_port =
 745                         fdir_filter->input.flow.udp6_flow.src_port;
 746                 input->formatted.dst_port =
 747                         fdir_filter->input.flow.udp6_flow.dst_port;
 748         /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
 749         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 750         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 751                 rte_memcpy(input->formatted.src_ip,
 752                            fdir_filter->input.flow.ipv6_flow.src_ip,
 753                            sizeof(input->formatted.src_ip));
 754                 rte_memcpy(input->formatted.dst_ip,
 755                            fdir_filter->input.flow.ipv6_flow.dst_ip,
 756                            sizeof(input->formatted.dst_ip));
 757                 break;
 758         default:
 759                 break;
 760         }
 761
 762         if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
 763                 rte_memcpy(
 764                         input->formatted.inner_mac,
 765                         fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes,
 766                         sizeof(input->formatted.inner_mac));
 767         } else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
 768                 rte_memcpy(
 769                         input->formatted.inner_mac,
 770                         fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes,
 771                         sizeof(input->formatted.inner_mac));
 772                 input->formatted.tunnel_type =
 773                         fdir_filter->input.flow.tunnel_flow.tunnel_type;
 774                 input->formatted.tni_vni =
 775                         fdir_filter->input.flow.tunnel_flow.tunnel_id;
 776         }
 777
 778         return 0;
 779 }
 780
 781 /*
 782  * The below function is taken from the FreeBSD IXGBE drivers release
 783  * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
 784  * before returning, as the signature hash can use 16bits.
 785  *
 786  * The newer driver has optimised functions for calculating bucket and
 787  * signature hashes. However they don't support IPv6 type packets for signature
 788  * filters so are not used here.
 789  *
 790  * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
 791  * set.
 792  *
 793  * Compute the hashes for SW ATR
 794  *  @stream: input bitstream to compute the hash on
 795  *  @key: 32-bit hash key
 796  **/
 797 static uint32_t
 798 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
 799                                  uint32_t key)
 800 {
 801         /*
 802          * The algorithm is as follows:
 803          *    Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
 804          *    where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
 805          *    and A[n] x B[n] is bitwise AND between same length strings
 806          *
 807          *    K[n] is 16 bits, defined as:
 808          *       for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
 809          *       for n modulo 32 < 15, K[n] =
 810          *             K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
 811          *
 812          *    S[n] is 16 bits, defined as:
 813          *       for n >= 15, S[n] = S[n:n - 15]
 814          *       for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
 815          *
 816          *    To simplify for programming, the algorithm is implemented
 817          *    in software this way:
 818          *
 819          *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
 820          *
 821          *    for (i = 0; i < 352; i+=32)
 822          *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
 823          *
 824          *    lo_hash_dword[15:0]  ^= Stream[15:0];
 825          *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
 826          *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
 827          *
 828          *    hi_hash_dword[31:0]  ^= Stream[351:320];
 829          *
 830          *    if (key[0])
 831          *        hash[15:0] ^= Stream[15:0];
 832          *
 833          *    for (i = 0; i < 16; i++) {
 834          *        if (key[i])
 835          *            hash[15:0] ^= lo_hash_dword[(i+15):i];
 836          *        if (key[i + 16])
 837          *            hash[15:0] ^= hi_hash_dword[(i+15):i];
 838          *    }
 839          *
 840          */
 841         __be32 common_hash_dword = 0;
 842         u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
 843         u32 hash_result = 0;
 844         u8 i;
 845
 846         /* record the flow_vm_vlan bits as they are a key part to the hash */
 847         flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
 848
 849         /* generate common hash dword */
 850         for (i = 1; i <= 13; i++)
 851                 common_hash_dword ^= atr_input->dword_stream[i];
 852
 853         hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
 854
 855         /* low dword is word swapped version of common */
 856         lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 857
 858         /* apply flow ID/VM pool/VLAN ID bits to hash words */
 859         hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 860
 861         /* Process bits 0 and 16 */
 862         if (key & 0x0001)
 863                 hash_result ^= lo_hash_dword;
 864         if (key & 0x00010000)
 865                 hash_result ^= hi_hash_dword;
 866
 867         /*
 868          * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
 869          * delay this because bit 0 of the stream should not be processed
 870          * so we do not add the vlan until after bit 0 was processed
 871          */
 872         lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 873
 874
 875         /* process the remaining 30 bits in the key 2 bits at a time */
 876         for (i = 15; i; i--) {
 877                 if (key & (0x0001 << i))
 878                         hash_result ^= lo_hash_dword >> i;
 879                 if (key & (0x00010000 << i))
 880                         hash_result ^= hi_hash_dword >> i;
 881         }
 882
 883         return hash_result;
 884 }
 885
 886 static uint32_t
 887 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 888                 enum rte_fdir_pballoc_type pballoc)
 889 {
 890         if (pballoc == RTE_FDIR_PBALLOC_256K)
 891                 return ixgbe_atr_compute_hash_82599(input,
 892                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 893                                 PERFECT_BUCKET_256KB_HASH_MASK;
 894         else if (pballoc == RTE_FDIR_PBALLOC_128K)
 895                 return ixgbe_atr_compute_hash_82599(input,
 896                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 897                                 PERFECT_BUCKET_128KB_HASH_MASK;
 898         else
 899                 return ixgbe_atr_compute_hash_82599(input,
 900                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 901                                 PERFECT_BUCKET_64KB_HASH_MASK;
 902 }
 903
 904 /**
 905  * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
 906  * @hw: pointer to hardware structure
 907  */
 908 static inline int
 909 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
 910 {
 911         int i;
 912
 913         for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
 914                 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
 915                 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
 916                         return 0;
 917                 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
 918         }
 919
 920         return -ETIMEDOUT;
 921 }
 922
 923 /*
 924  * Calculate the hash value needed for signature-match filters. In the FreeBSD
 925  * driver, this is done by the optimised function
 926  * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
 927  * doesn't support calculating a hash for an IPv6 filter.
 928  */
 929 static uint32_t
 930 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
 931                 enum rte_fdir_pballoc_type pballoc)
 932 {
 933         uint32_t bucket_hash, sig_hash;
 934
 935         if (pballoc == RTE_FDIR_PBALLOC_256K)
 936                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 937                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 938                                 SIG_BUCKET_256KB_HASH_MASK;
 939         else if (pballoc == RTE_FDIR_PBALLOC_128K)
 940                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 941                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 942                                 SIG_BUCKET_128KB_HASH_MASK;
 943         else
 944                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 945                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 946                                 SIG_BUCKET_64KB_HASH_MASK;
 947
 948         sig_hash = ixgbe_atr_compute_hash_82599(input,
 949                         IXGBE_ATR_SIGNATURE_HASH_KEY);
 950
 951         return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
 952 }
 953
 954 /*
 955  * This is based on ixgbe_fdir_write_perfect_filter_82599() in
 956  * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
 957  * added, and IPv6 support also added. The hash value is also pre-calculated
 958  * as the pballoc value is needed to do it.
 959  */
 960 static int
 961 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 962                         union ixgbe_atr_input *input, uint8_t queue,
 963                         uint32_t fdircmd, uint32_t fdirhash,
 964                         enum rte_fdir_mode mode)
 965 {
 966         uint32_t fdirport, fdirvlan;
 967         u32 addr_low, addr_high;
 968         u32 tunnel_type = 0;
 969         int err = 0;
 970         volatile uint32_t *reg;
 971
 972         if (mode == RTE_FDIR_MODE_PERFECT) {
 973                 /* record the IPv4 address (big-endian)
 974                  * can not use IXGBE_WRITE_REG.
 975                  */
 976                 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPSA);
 977                 *reg = input->formatted.src_ip[0];
 978                 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPDA);
 979                 *reg = input->formatted.dst_ip[0];
 980
 981                 /* record source and destination port (little-endian)*/
 982                 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
 983                 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
 984                 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
 985                 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
 986         } else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 987                    mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
 988                 /* for mac vlan and tunnel modes */
 989                 addr_low = ((u32)input->formatted.inner_mac[0] |
 990                             ((u32)input->formatted.inner_mac[1] << 8) |
 991                             ((u32)input->formatted.inner_mac[2] << 16) |
 992                             ((u32)input->formatted.inner_mac[3] << 24));
 993                 addr_high = ((u32)input->formatted.inner_mac[4] |
 994                              ((u32)input->formatted.inner_mac[5] << 8));
 995
 996                 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
 997                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
 998                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high);
 999                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0);
1000                 } else {
1001                         /* tunnel mode */
1002                         if (input->formatted.tunnel_type !=
1003                                 RTE_FDIR_TUNNEL_TYPE_NVGRE)
1004                                 tunnel_type = 0x80000000;
1005                         tunnel_type |= addr_high;
1006                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1007                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type);
1008                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2),
1009                                         input->formatted.tni_vni);
1010                 }
1011         }
1012
1013         /* record vlan (little-endian) and flex_bytes(big-endian) */
1014         fdirvlan = input->formatted.flex_bytes;
1015         fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1016         fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1017         IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1018
1019         /* configure FDIRHASH register */
1020         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1021
1022         /*
1023          * flush all previous writes to make certain registers are
1024          * programmed prior to issuing the command
1025          */
1026         IXGBE_WRITE_FLUSH(hw);
1027
1028         /* configure FDIRCMD register */
1029         fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1030                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1031         fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1032         fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1033         fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1034
1035         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1036
1037         PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1038
1039         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1040         if (err < 0)
1041                 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1042
1043         return err;
1044 }
1045
1046 /**
1047  * This function is based on ixgbe_atr_add_signature_filter_82599() in
1048  * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
1049  * setting extra fields in the FDIRCMD register, and removes the code that was
1050  * verifying the flow_type field. According to the documentation, a flow type of
1051  * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
1052  * work ok...
1053  *
1054  *  Adds a signature hash filter
1055  *  @hw: pointer to hardware structure
1056  *  @input: unique input dword
1057  *  @queue: queue index to direct traffic to
1058  *  @fdircmd: any extra flags to set in fdircmd register
1059  *  @fdirhash: pre-calculated hash value for the filter
1060  **/
1061 static int
1062 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1063                 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
1064                 uint32_t fdirhash)
1065 {
1066         int err = 0;
1067
1068         PMD_INIT_FUNC_TRACE();
1069
1070         /* configure FDIRCMD register */
1071         fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1072                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1073         fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1074         fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1075
1076         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1077         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1078
1079         PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1080
1081         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1082         if (err < 0)
1083                 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1084
1085         return err;
1086 }
1087
1088 /*
1089  * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
1090  * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so
1091  * that it can be used for removing signature and perfect filters.
1092  */
1093 static int
1094 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
1095 {
1096         uint32_t fdircmd = 0;
1097         int err = 0;
1098
1099         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1100
1101         /* flush hash to HW */
1102         IXGBE_WRITE_FLUSH(hw);
1103
1104         /* Query if filter is present */
1105         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1106
1107         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1108         if (err < 0) {
1109                 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
1110                 return err;
1111         }
1112
1113         /* if filter exists in hardware then remove it */
1114         if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1115                 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1116                 IXGBE_WRITE_FLUSH(hw);
1117                 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1118                                 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1119         }
1120         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1121         if (err < 0)
1122                 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
1123         return err;
1124
1125 }
1126
1127 static inline struct ixgbe_fdir_filter *
1128 ixgbe_fdir_filter_lookup(struct ixgbe_hw_fdir_info *fdir_info,
1129                          union ixgbe_atr_input *key)
1130 {
1131         int ret;
1132
1133         ret = rte_hash_lookup(fdir_info->hash_handle, (const void *)key);
1134         if (ret < 0)
1135                 return NULL;
1136
1137         return fdir_info->hash_map[ret];
1138 }
1139
1140 static inline int
1141 ixgbe_insert_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1142                          struct ixgbe_fdir_filter *fdir_filter)
1143 {
1144         int ret;
1145
1146         ret = rte_hash_add_key(fdir_info->hash_handle,
1147                                &fdir_filter->ixgbe_fdir);
1148
1149         if (ret < 0) {
1150                 PMD_DRV_LOG(ERR,
1151                             "Failed to insert fdir filter to hash table %d!",
1152                             ret);
1153                 return ret;
1154         }
1155
1156         fdir_info->hash_map[ret] = fdir_filter;
1157
1158         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, fdir_filter, entries);
1159
1160         return 0;
1161 }
1162
1163 static inline int
1164 ixgbe_remove_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1165                          union ixgbe_atr_input *key)
1166 {
1167         int ret;
1168         struct ixgbe_fdir_filter *fdir_filter;
1169
1170         ret = rte_hash_del_key(fdir_info->hash_handle, key);
1171
1172         if (ret < 0) {
1173                 PMD_DRV_LOG(ERR, "No such fdir filter to delete %d!", ret);
1174                 return ret;
1175         }
1176
1177         fdir_filter = fdir_info->hash_map[ret];
1178         fdir_info->hash_map[ret] = NULL;
1179
1180         TAILQ_REMOVE(&fdir_info->fdir_list, fdir_filter, entries);
1181         rte_free(fdir_filter);
1182
1183         return 0;
1184 }
1185
1186 static int
1187 ixgbe_interpret_fdir_filter(struct rte_eth_dev *dev,
1188                             const struct rte_eth_fdir_filter *fdir_filter,
1189                             struct ixgbe_fdir_rule *rule)
1190 {
1191         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1192         int err;
1193
1194         memset(rule, 0, sizeof(struct ixgbe_fdir_rule));
1195
1196         err = ixgbe_fdir_filter_to_atr_input(fdir_filter,
1197                                              &rule->ixgbe_fdir,
1198                                              fdir_mode);
1199         if (err)
1200                 return err;
1201
1202         rule->mode = fdir_mode;
1203         if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT)
1204                 rule->fdirflags = IXGBE_FDIRCMD_DROP;
1205         rule->queue = fdir_filter->action.rx_queue;
1206         rule->soft_id = fdir_filter->soft_id;
1207
1208         return 0;
1209 }
1210
1211 int
1212 ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
1213                           struct ixgbe_fdir_rule *rule,
1214                           bool del,
1215                           bool update)
1216 {
1217         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1218         uint32_t fdircmd_flags;
1219         uint32_t fdirhash;
1220         uint8_t queue;
1221         bool is_perfect = FALSE;
1222         int err;
1223         struct ixgbe_hw_fdir_info *info =
1224                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1225         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1226         struct ixgbe_fdir_filter *node;
1227         bool add_node = FALSE;
1228
1229         if (fdir_mode == RTE_FDIR_MODE_NONE ||
1230             fdir_mode != rule->mode)
1231                 return -ENOTSUP;
1232
1233         /*
1234          * Sanity check for x550.
1235          * When adding a new filter with flow type set to IPv4-other,
1236          * the flow director mask should be configed before,
1237          * and the L4 protocol and ports are masked.
1238          */
1239         if ((!del) &&
1240             (hw->mac.type == ixgbe_mac_X550 ||
1241              hw->mac.type == ixgbe_mac_X550EM_x ||
1242              hw->mac.type == ixgbe_mac_X550EM_a) &&
1243             (rule->ixgbe_fdir.formatted.flow_type ==
1244              RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) &&
1245             (info->mask.src_port_mask != 0 ||
1246              info->mask.dst_port_mask != 0)) {
1247                 PMD_DRV_LOG(ERR, "By this device,"
1248                             " IPv4-other is not supported without"
1249                             " L4 protocol and ports masked!");
1250                 return -ENOTSUP;
1251         }
1252
1253         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1254             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1255                 is_perfect = TRUE;
1256
1257         if (is_perfect) {
1258                 if (rule->ixgbe_fdir.formatted.flow_type &
1259                     IXGBE_ATR_L4TYPE_IPV6_MASK) {
1260                         PMD_DRV_LOG(ERR, "IPv6 is not supported in"
1261                                     " perfect mode!");
1262                         return -ENOTSUP;
1263                 }
1264                 fdirhash = atr_compute_perfect_hash_82599(&rule->ixgbe_fdir,
1265                                                           dev->data->dev_conf.fdir_conf.pballoc);
1266                 fdirhash |= rule->soft_id <<
1267                         IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1268         } else
1269                 fdirhash = atr_compute_sig_hash_82599(&rule->ixgbe_fdir,
1270                                                       dev->data->dev_conf.fdir_conf.pballoc);
1271
1272         if (del) {
1273                 err = ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1274                 if (err < 0)
1275                         return err;
1276
1277                 err = fdir_erase_filter_82599(hw, fdirhash);
1278                 if (err < 0)
1279                         PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
1280                 else
1281                         PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
1282                 return err;
1283         }
1284         /* add or update an fdir filter*/
1285         fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
1286         if (rule->fdirflags & IXGBE_FDIRCMD_DROP) {
1287                 if (is_perfect) {
1288                         queue = dev->data->dev_conf.fdir_conf.drop_queue;
1289                         fdircmd_flags |= IXGBE_FDIRCMD_DROP;
1290                 } else {
1291                         PMD_DRV_LOG(ERR, "Drop option is not supported in"
1292                                     " signature mode.");
1293                         return -EINVAL;
1294                 }
1295         } else if (rule->queue < IXGBE_MAX_RX_QUEUE_NUM)
1296                 queue = (uint8_t)rule->queue;
1297         else
1298                 return -EINVAL;
1299
1300         node = ixgbe_fdir_filter_lookup(info, &rule->ixgbe_fdir);
1301         if (node) {
1302                 if (update) {
1303                         node->fdirflags = fdircmd_flags;
1304                         node->fdirhash = fdirhash;
1305                         node->queue = queue;
1306                 } else {
1307                         PMD_DRV_LOG(ERR, "Conflict with existing fdir filter!");
1308                         return -EINVAL;
1309                 }
1310         } else {
1311                 add_node = TRUE;
1312                 node = rte_zmalloc("ixgbe_fdir",
1313                                    sizeof(struct ixgbe_fdir_filter),
1314                                    0);
1315                 if (!node)
1316                         return -ENOMEM;
1317                 (void)rte_memcpy(&node->ixgbe_fdir,
1318                                  &rule->ixgbe_fdir,
1319                                  sizeof(union ixgbe_atr_input));
1320                 node->fdirflags = fdircmd_flags;
1321                 node->fdirhash = fdirhash;
1322                 node->queue = queue;
1323
1324                 err = ixgbe_insert_fdir_filter(info, node);
1325                 if (err < 0) {
1326                         rte_free(node);
1327                         return err;
1328                 }
1329         }
1330
1331         if (is_perfect) {
1332                 err = fdir_write_perfect_filter_82599(hw, &rule->ixgbe_fdir,
1333                                                       queue, fdircmd_flags,
1334                                                       fdirhash, fdir_mode);
1335         } else {
1336                 err = fdir_add_signature_filter_82599(hw, &rule->ixgbe_fdir,
1337                                                       queue, fdircmd_flags,
1338                                                       fdirhash);
1339         }
1340         if (err < 0) {
1341                 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
1342
1343                 if (add_node)
1344                         (void)ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1345         } else {
1346                 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
1347         }
1348
1349         return err;
1350 }
1351
1352 /* ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
1353  * @dev: pointer to the structure rte_eth_dev
1354  * @fdir_filter: fdir filter entry
1355  * @del: 1 - delete, 0 - add
1356  * @update: 1 - update
1357  */
1358 static int
1359 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
1360                           const struct rte_eth_fdir_filter *fdir_filter,
1361                           bool del,
1362                           bool update)
1363 {
1364         struct ixgbe_fdir_rule rule;
1365         int err;
1366
1367         err = ixgbe_interpret_fdir_filter(dev, fdir_filter, &rule);
1368
1369         if (err)
1370                 return err;
1371
1372         return ixgbe_fdir_filter_program(dev, &rule, del, update);
1373 }
1374
1375 static int
1376 ixgbe_fdir_flush(struct rte_eth_dev *dev)
1377 {
1378         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1379         struct ixgbe_hw_fdir_info *info =
1380                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1381         int ret;
1382
1383         ret = ixgbe_reinit_fdir_tables_82599(hw);
1384         if (ret < 0) {
1385                 PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
1386                 return ret;
1387         }
1388
1389         info->f_add = 0;
1390         info->f_remove = 0;
1391         info->add = 0;
1392         info->remove = 0;
1393
1394         return ret;
1395 }
1396
1397 #define FDIRENTRIES_NUM_SHIFT 10
1398 static void
1399 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
1400 {
1401         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402         struct ixgbe_hw_fdir_info *info =
1403                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1404         uint32_t fdirctrl, max_num;
1405         uint8_t offset;
1406
1407         fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1408         offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
1409                         IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
1410
1411         fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
1412         max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1413                         (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
1414         if (fdir_info->mode >= RTE_FDIR_MODE_PERFECT &&
1415             fdir_info->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1416                 fdir_info->guarant_spc = max_num;
1417         else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
1418                 fdir_info->guarant_spc = max_num * 4;
1419
1420         fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
1421         fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
1422         fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
1423         IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
1424                         fdir_info->mask.ipv6_mask.src_ip);
1425         IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
1426                         fdir_info->mask.ipv6_mask.dst_ip);
1427         fdir_info->mask.src_port_mask = info->mask.src_port_mask;
1428         fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
1429         fdir_info->mask.mac_addr_byte_mask = info->mask.mac_addr_byte_mask;
1430         fdir_info->mask.tunnel_id_mask = info->mask.tunnel_id_mask;
1431         fdir_info->mask.tunnel_type_mask = info->mask.tunnel_type_mask;
1432         fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
1433
1434         if (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN ||
1435             fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
1436                 fdir_info->flow_types_mask[0] = 0;
1437         else
1438                 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1439
1440         fdir_info->flex_payload_unit = sizeof(uint16_t);
1441         fdir_info->max_flex_payload_segment_num = 1;
1442         fdir_info->flex_payload_limit = IXGBE_MAX_FLX_SOURCE_OFF;
1443         fdir_info->flex_conf.nb_payloads = 1;
1444         fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1445         fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1446         fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1447         fdir_info->flex_conf.nb_flexmasks = 1;
1448         fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;
1449         fdir_info->flex_conf.flex_mask[0].mask[0] =
1450                         (uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1451         fdir_info->flex_conf.flex_mask[0].mask[1] =
1452                         (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1453 }
1454
1455 static void
1456 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1457 {
1458         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1459         struct ixgbe_hw_fdir_info *info =
1460                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1461         uint32_t reg, max_num;
1462         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1463
1464         /* Get the information from registers */
1465         reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1466         info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1467                                      IXGBE_FDIRFREE_COLL_SHIFT);
1468         info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1469                                 IXGBE_FDIRFREE_FREE_SHIFT);
1470
1471         reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1472         info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1473                                    IXGBE_FDIRLEN_MAXHASH_SHIFT);
1474         info->maxlen  = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1475                                   IXGBE_FDIRLEN_MAXLEN_SHIFT);
1476
1477         reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1478         info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1479                 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1480         info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1481                 IXGBE_FDIRUSTAT_ADD_SHIFT;
1482
1483         reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1484         info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1485                 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1486         info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1487                 IXGBE_FDIRFSTAT_FADD_SHIFT;
1488
1489         /*  Copy the new information in the fdir parameter */
1490         fdir_stats->collision = info->collision;
1491         fdir_stats->free = info->free;
1492         fdir_stats->maxhash = info->maxhash;
1493         fdir_stats->maxlen = info->maxlen;
1494         fdir_stats->remove = info->remove;
1495         fdir_stats->add = info->add;
1496         fdir_stats->f_remove = info->f_remove;
1497         fdir_stats->f_add = info->f_add;
1498
1499         reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1500         max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1501                          (reg & FDIRCTRL_PBALLOC_MASK)));
1502         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1503             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1504                 fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1505         else if (fdir_mode == RTE_FDIR_MODE_SIGNATURE)
1506                 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1507
1508 }
1509
1510 /*
1511  * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1512  * @dev: pointer to the structure rte_eth_dev
1513  * @filter_op:operation will be taken
1514  * @arg: a pointer to specific structure corresponding to the filter_op
1515  */
1516 int
1517 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1518                         enum rte_filter_op filter_op, void *arg)
1519 {
1520         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1521         int ret = 0;
1522
1523         if (hw->mac.type != ixgbe_mac_82599EB &&
1524                 hw->mac.type != ixgbe_mac_X540 &&
1525                 hw->mac.type != ixgbe_mac_X550 &&
1526                 hw->mac.type != ixgbe_mac_X550EM_x &&
1527                 hw->mac.type != ixgbe_mac_X550EM_a)
1528                 return -ENOTSUP;
1529
1530         if (filter_op == RTE_ETH_FILTER_NOP)
1531                 return 0;
1532
1533         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1534                 return -EINVAL;
1535
1536         switch (filter_op) {
1537         case RTE_ETH_FILTER_ADD:
1538                 ret = ixgbe_add_del_fdir_filter(dev,
1539                         (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1540                 break;
1541         case RTE_ETH_FILTER_UPDATE:
1542                 ret = ixgbe_add_del_fdir_filter(dev,
1543                         (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1544                 break;
1545         case RTE_ETH_FILTER_DELETE:
1546                 ret = ixgbe_add_del_fdir_filter(dev,
1547                         (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1548                 break;
1549         case RTE_ETH_FILTER_FLUSH:
1550                 ret = ixgbe_fdir_flush(dev);
1551                 break;
1552         case RTE_ETH_FILTER_INFO:
1553                 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1554                 break;
1555         case RTE_ETH_FILTER_STATS:
1556                 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1557                 break;
1558         default:
1559                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1560                 ret = -EINVAL;
1561                 break;
1562         }
1563         return ret;
1564 }
1565
1566 /* restore flow director filter */
1567 void
1568 ixgbe_fdir_filter_restore(struct rte_eth_dev *dev)
1569 {
1570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571         struct ixgbe_hw_fdir_info *fdir_info =
1572                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1573         struct ixgbe_fdir_filter *node;
1574         bool is_perfect = FALSE;
1575         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1576
1577         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1578             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1579                 is_perfect = TRUE;
1580
1581         if (is_perfect) {
1582                 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1583                         (void)fdir_write_perfect_filter_82599(hw,
1584                                                               &node->ixgbe_fdir,
1585                                                               node->queue,
1586                                                               node->fdirflags,
1587                                                               node->fdirhash,
1588                                                               fdir_mode);
1589                 }
1590         } else {
1591                 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1592                         (void)fdir_add_signature_filter_82599(hw,
1593                                                               &node->ixgbe_fdir,
1594                                                               node->queue,
1595                                                               node->fdirflags,
1596                                                               node->fdirhash);
1597                 }
1598         }
1599 }
1600
1601 /* remove all the flow director filters */
1602 int
1603 ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev)
1604 {
1605         struct ixgbe_hw_fdir_info *fdir_info =
1606                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1607         struct ixgbe_fdir_filter *fdir_filter;
1608         struct ixgbe_fdir_filter *filter_flag;
1609         int ret = 0;
1610
1611         /* flush flow director */
1612         rte_hash_reset(fdir_info->hash_handle);
1613         memset(fdir_info->hash_map, 0,
1614                sizeof(struct ixgbe_fdir_filter *) * IXGBE_MAX_FDIR_FILTER_NUM);
1615         filter_flag = TAILQ_FIRST(&fdir_info->fdir_list);
1616         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1617                 TAILQ_REMOVE(&fdir_info->fdir_list,
1618                              fdir_filter,
1619                              entries);
1620                 rte_free(fdir_filter);
1621         }
1622
1623         if (filter_flag != NULL)
1624                 ret = ixgbe_fdir_flush(dev);
1625
1626         return ret;
1627 }