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38 #include <sys/queue.h>
40 #include <rte_interrupts.h>
42 #include <rte_debug.h>
44 #include <rte_ether.h>
45 #include <rte_ethdev.h>
46 #include <rte_malloc.h>
48 #include "ixgbe_logs.h"
49 #include "base/ixgbe_api.h"
50 #include "base/ixgbe_common.h"
51 #include "ixgbe_ethdev.h"
53 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
54 #define FDIRCTRL_PBALLOC_MASK 0x03
56 /* For calculating memory required for FDIR filters */
57 #define PBALLOC_SIZE_SHIFT 15
59 /* Number of bits used to mask bucket hash for different pballoc sizes */
60 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
61 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
62 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
64 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
65 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
66 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET 12 /* default flexbytes offset in bytes */
67 #define IXGBE_FDIR_MAX_FLEX_LEN 2 /* len in bytes of flexbytes */
68 #define IXGBE_MAX_FLX_SOURCE_OFF 62
69 #define IXGBE_FDIRCTRL_FLEX_MASK (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
70 #define IXGBE_FDIRCMD_CMD_INTERVAL_US 10
72 #define IXGBE_FDIR_FLOW_TYPES ( \
73 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
74 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
75 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
76 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
77 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
78 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
79 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
80 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
82 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
83 uint8_t ipv6_addr[16]; \
85 rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
87 for (i = 0; i < sizeof(ipv6_addr); i++) { \
88 if (ipv6_addr[i] == UINT8_MAX) \
90 else if (ipv6_addr[i] != 0) { \
91 PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
97 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
98 uint8_t ipv6_addr[16]; \
100 for (i = 0; i < sizeof(ipv6_addr); i++) { \
101 if ((ipv6m) & (1 << i)) \
102 ipv6_addr[i] = UINT8_MAX; \
106 rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
109 #define DEFAULT_VXLAN_PORT 4789
110 #define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4
112 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
113 static int fdir_set_input_mask(struct rte_eth_dev *dev,
114 const struct rte_eth_fdir_masks *input_mask);
115 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev);
116 static int fdir_set_input_mask_x550(struct rte_eth_dev *dev);
117 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
118 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);
119 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
120 static int ixgbe_fdir_filter_to_atr_input(
121 const struct rte_eth_fdir_filter *fdir_filter,
122 union ixgbe_atr_input *input,
123 enum rte_fdir_mode mode);
124 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
126 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
127 enum rte_fdir_pballoc_type pballoc);
128 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
129 enum rte_fdir_pballoc_type pballoc);
130 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
131 union ixgbe_atr_input *input, uint8_t queue,
132 uint32_t fdircmd, uint32_t fdirhash,
133 enum rte_fdir_mode mode);
134 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
135 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
137 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
138 const struct rte_eth_fdir_filter *fdir_filter,
141 static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
142 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
143 struct rte_eth_fdir_info *fdir_info);
144 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
145 struct rte_eth_fdir_stats *fdir_stats);
148 * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.
149 * It adds extra configuration of fdirctrl that is common for all filter types.
151 * Initialize Flow Director control registers
152 * @hw: pointer to hardware structure
153 * @fdirctrl: value to write to flow director control register
156 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
160 PMD_INIT_FUNC_TRACE();
162 /* Prime the keys for hashing */
163 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
164 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
167 * Continue setup of fdirctrl register bits:
168 * Set the maximum length per hash bucket to 0xA filters
169 * Send interrupt when 64 filters are left
171 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
172 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
175 * Poll init-done after we write the register. Estimated times:
176 * 10G: PBALLOC = 11b, timing is 60us
177 * 1G: PBALLOC = 11b, timing is 600us
178 * 100M: PBALLOC = 11b, timing is 6ms
180 * Multiple these timings by 4 if under full Rx load
182 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
183 * 1 msec per poll time. If we're at line rate and drop to 100M, then
184 * this might not finish in our poll time, but we can live with that
187 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
188 IXGBE_WRITE_FLUSH(hw);
189 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
190 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
191 IXGBE_FDIRCTRL_INIT_DONE)
196 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
197 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded during enabling!");
204 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
205 * flexbytes matching field, and drop queue (only for perfect matching mode).
208 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
212 switch (conf->pballoc) {
213 case RTE_FDIR_PBALLOC_64K:
214 /* 8k - 1 signature filters */
215 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
217 case RTE_FDIR_PBALLOC_128K:
218 /* 16k - 1 signature filters */
219 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
221 case RTE_FDIR_PBALLOC_256K:
222 /* 32k - 1 signature filters */
223 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
227 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
231 /* status flags: write hash & swindex in the rx descriptor */
232 switch (conf->status) {
233 case RTE_FDIR_NO_REPORT_STATUS:
234 /* do nothing, default mode */
236 case RTE_FDIR_REPORT_STATUS:
237 /* report status when the packet matches a fdir rule */
238 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
240 case RTE_FDIR_REPORT_STATUS_ALWAYS:
241 /* always report status */
242 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
246 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
250 *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
251 IXGBE_FDIRCTRL_FLEX_SHIFT;
253 if (conf->mode >= RTE_FDIR_MODE_PERFECT &&
254 conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
255 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
256 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
257 if (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
258 *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN
259 << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
260 else if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
261 *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD
262 << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
269 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
271 * @hi_dword: Bits 31:16 mask to be bit swapped.
272 * @lo_dword: Bits 15:0 mask to be bit swapped.
274 * Flow director uses several registers to store 2 x 16 bit masks with the
275 * bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
276 * mask affects the MS bit/byte of the target. This function reverses the
277 * bits in these masks.
279 static inline uint32_t
280 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
282 uint32_t mask = hi_dword << 16;
285 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
286 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
287 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
288 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
292 * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
293 * but makes use of the rte_fdir_masks structure to see which bits to set.
296 fdir_set_input_mask_82599(struct rte_eth_dev *dev)
298 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
299 struct ixgbe_hw_fdir_info *info =
300 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
302 * mask VM pool and DIPv6 since there are currently not supported
303 * mask FLEX byte, it will be set in flex_conf
305 uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
306 uint32_t fdirtcpm; /* TCP source and destination port masks. */
307 uint32_t fdiripv6m; /* IPv6 source and destination masks. */
308 volatile uint32_t *reg;
310 PMD_INIT_FUNC_TRACE();
313 * Program the relevant mask registers. If src/dst_port or src/dst_addr
314 * are zero, then assume a full mask for that field. Also assume that
315 * a VLAN of 0 is unspecified, so mask that out as well. L4type
316 * cannot be masked out in this implementation.
318 if (info->mask.dst_port_mask == 0 && info->mask.src_port_mask == 0)
319 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
320 fdirm |= IXGBE_FDIRM_L4P;
322 if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
323 /* mask VLAN Priority */
324 fdirm |= IXGBE_FDIRM_VLANP;
325 else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
327 fdirm |= IXGBE_FDIRM_VLANID;
328 else if (info->mask.vlan_tci_mask == 0)
329 /* mask VLAN ID and Priority */
330 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
331 else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
332 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
336 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
338 /* store the TCP/UDP port masks, bit reversed from port layout */
339 fdirtcpm = reverse_fdir_bitmasks(
340 rte_be_to_cpu_16(info->mask.dst_port_mask),
341 rte_be_to_cpu_16(info->mask.src_port_mask));
343 /* write all the same so that UDP, TCP and SCTP use the same mask
346 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
347 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
348 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
350 /* Store source and destination IPv4 masks (big-endian),
351 * can not use IXGBE_WRITE_REG.
353 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRSIP4M);
354 *reg = ~(info->mask.src_ipv4_mask);
355 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRDIP4M);
356 *reg = ~(info->mask.dst_ipv4_mask);
358 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
360 * Store source and destination IPv6 masks (bit reversed)
362 fdiripv6m = (info->mask.dst_ipv6_mask << 16) |
363 info->mask.src_ipv6_mask;
365 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
368 return IXGBE_SUCCESS;
372 * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
373 * but makes use of the rte_fdir_masks structure to see which bits to set.
376 fdir_set_input_mask_x550(struct rte_eth_dev *dev)
378 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
379 struct ixgbe_hw_fdir_info *info =
380 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
381 /* mask VM pool and DIPv6 since there are currently not supported
382 * mask FLEX byte, it will be set in flex_conf
384 uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 |
387 enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
390 PMD_INIT_FUNC_TRACE();
392 /* set the default UDP port for VxLAN */
393 if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
394 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT);
396 /* some bits must be set for mac vlan or tunnel mode */
397 fdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P;
399 if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
400 /* mask VLAN Priority */
401 fdirm |= IXGBE_FDIRM_VLANP;
402 else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
404 fdirm |= IXGBE_FDIRM_VLANID;
405 else if (info->mask.vlan_tci_mask == 0)
406 /* mask VLAN ID and Priority */
407 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
408 else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
409 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
413 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
415 fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
416 fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
417 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
418 fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |
419 IXGBE_FDIRIP6M_TNI_VNI;
421 if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
422 mac_mask = info->mask.mac_addr_byte_mask;
423 fdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT)
424 & IXGBE_FDIRIP6M_INNER_MAC;
426 switch (info->mask.tunnel_type_mask) {
428 /* Mask turnnel type */
429 fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
434 PMD_INIT_LOG(ERR, "invalid tunnel_type_mask");
438 switch (rte_be_to_cpu_32(info->mask.tunnel_id_mask)) {
441 fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI;
444 fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
449 PMD_INIT_LOG(ERR, "invalid tunnel_id_mask");
454 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m);
455 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
456 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
457 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
458 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
459 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
461 return IXGBE_SUCCESS;
465 ixgbe_fdir_store_input_mask_82599(struct rte_eth_dev *dev,
466 const struct rte_eth_fdir_masks *input_mask)
468 struct ixgbe_hw_fdir_info *info =
469 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
470 uint16_t dst_ipv6m = 0;
471 uint16_t src_ipv6m = 0;
473 memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
474 info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
475 info->mask.src_port_mask = input_mask->src_port_mask;
476 info->mask.dst_port_mask = input_mask->dst_port_mask;
477 info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
478 info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
479 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
480 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
481 info->mask.src_ipv6_mask = src_ipv6m;
482 info->mask.dst_ipv6_mask = dst_ipv6m;
484 return IXGBE_SUCCESS;
488 ixgbe_fdir_store_input_mask_x550(struct rte_eth_dev *dev,
489 const struct rte_eth_fdir_masks *input_mask)
491 struct ixgbe_hw_fdir_info *info =
492 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
494 memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
495 info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
496 info->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask;
497 info->mask.tunnel_type_mask = input_mask->tunnel_type_mask;
498 info->mask.tunnel_id_mask = input_mask->tunnel_id_mask;
500 return IXGBE_SUCCESS;
504 ixgbe_fdir_store_input_mask(struct rte_eth_dev *dev,
505 const struct rte_eth_fdir_masks *input_mask)
507 enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
509 if (mode >= RTE_FDIR_MODE_SIGNATURE &&
510 mode <= RTE_FDIR_MODE_PERFECT)
511 return ixgbe_fdir_store_input_mask_82599(dev, input_mask);
512 else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
513 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
514 return ixgbe_fdir_store_input_mask_x550(dev, input_mask);
516 PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
521 ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev)
523 enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
525 if (mode >= RTE_FDIR_MODE_SIGNATURE &&
526 mode <= RTE_FDIR_MODE_PERFECT)
527 return fdir_set_input_mask_82599(dev);
528 else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
529 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
530 return fdir_set_input_mask_x550(dev);
532 PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
537 fdir_set_input_mask(struct rte_eth_dev *dev,
538 const struct rte_eth_fdir_masks *input_mask)
542 ret = ixgbe_fdir_store_input_mask(dev, input_mask);
546 return ixgbe_fdir_set_input_mask(dev);
550 * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
551 * arguments are valid
554 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
555 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl)
557 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
558 struct ixgbe_hw_fdir_info *info =
559 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
560 const struct rte_eth_flex_payload_cfg *flex_cfg;
561 const struct rte_eth_fdir_flex_mask *flex_mask;
563 uint16_t flexbytes = 0;
566 fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
569 PMD_DRV_LOG(ERR, "NULL pointer.");
573 for (i = 0; i < conf->nb_payloads; i++) {
574 flex_cfg = &conf->flex_set[i];
575 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
576 PMD_DRV_LOG(ERR, "unsupported payload type.");
579 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
580 (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
581 (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
582 *fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
584 (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
585 IXGBE_FDIRCTRL_FLEX_SHIFT;
587 PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
592 for (i = 0; i < conf->nb_flexmasks; i++) {
593 flex_mask = &conf->flex_mask[i];
594 if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
595 PMD_DRV_LOG(ERR, "flexmask should be set globally.");
598 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
599 ((flex_mask->mask[1]) & 0xFF));
600 if (flexbytes == UINT16_MAX)
601 fdirm &= ~IXGBE_FDIRM_FLEX;
602 else if (flexbytes != 0) {
603 /* IXGBE_FDIRM_FLEX is set by default when set mask */
604 PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
608 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
609 info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
610 info->flex_bytes_offset = (uint8_t)((*fdirctrl &
611 IXGBE_FDIRCTRL_FLEX_MASK) >>
612 IXGBE_FDIRCTRL_FLEX_SHIFT);
617 ixgbe_fdir_configure(struct rte_eth_dev *dev)
619 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
621 uint32_t fdirctrl, pbsize;
623 enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
625 PMD_INIT_FUNC_TRACE();
627 if (hw->mac.type != ixgbe_mac_82599EB &&
628 hw->mac.type != ixgbe_mac_X540 &&
629 hw->mac.type != ixgbe_mac_X550 &&
630 hw->mac.type != ixgbe_mac_X550EM_x &&
631 hw->mac.type != ixgbe_mac_X550EM_a)
634 /* x550 supports mac-vlan and tunnel mode but other NICs not */
635 if (hw->mac.type != ixgbe_mac_X550 &&
636 hw->mac.type != ixgbe_mac_X550EM_x &&
637 hw->mac.type != ixgbe_mac_X550EM_a &&
638 mode != RTE_FDIR_MODE_SIGNATURE &&
639 mode != RTE_FDIR_MODE_PERFECT)
642 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
647 * Before enabling Flow Director, the Rx Packet Buffer size
648 * must be reduced. The new value is the current size minus
649 * flow director memory usage size.
651 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
652 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
653 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
656 * The defaults in the HW for RX PB 1-7 are not zero and so should be
657 * intialized to zero for non DCB mode otherwise actual total RX PB
658 * would be bigger than programmed and filter space would run into
661 for (i = 1; i < 8; i++)
662 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
664 err = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask);
666 PMD_INIT_LOG(ERR, " Error on setting FD mask");
669 err = ixgbe_set_fdir_flex_conf(dev,
670 &dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl);
672 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
676 err = fdir_enable_82599(hw, fdirctrl);
678 PMD_INIT_LOG(ERR, " Error on enabling FD.");
685 * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
686 * by the IXGBE driver code.
689 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
690 union ixgbe_atr_input *input, enum rte_fdir_mode mode)
692 input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
693 input->formatted.flex_bytes = (uint16_t)(
694 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
695 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
697 switch (fdir_filter->input.flow_type) {
698 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
699 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
701 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
702 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
704 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
705 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
707 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
708 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
710 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
711 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
713 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
714 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
716 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
717 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
719 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
720 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
726 switch (fdir_filter->input.flow_type) {
727 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
728 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
729 input->formatted.src_port =
730 fdir_filter->input.flow.udp4_flow.src_port;
731 input->formatted.dst_port =
732 fdir_filter->input.flow.udp4_flow.dst_port;
734 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
735 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
736 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
737 input->formatted.src_ip[0] =
738 fdir_filter->input.flow.ip4_flow.src_ip;
739 input->formatted.dst_ip[0] =
740 fdir_filter->input.flow.ip4_flow.dst_ip;
743 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
744 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
745 input->formatted.src_port =
746 fdir_filter->input.flow.udp6_flow.src_port;
747 input->formatted.dst_port =
748 fdir_filter->input.flow.udp6_flow.dst_port;
750 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
751 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
752 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
753 rte_memcpy(input->formatted.src_ip,
754 fdir_filter->input.flow.ipv6_flow.src_ip,
755 sizeof(input->formatted.src_ip));
756 rte_memcpy(input->formatted.dst_ip,
757 fdir_filter->input.flow.ipv6_flow.dst_ip,
758 sizeof(input->formatted.dst_ip));
764 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
766 input->formatted.inner_mac,
767 fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes,
768 sizeof(input->formatted.inner_mac));
769 } else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
771 input->formatted.inner_mac,
772 fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes,
773 sizeof(input->formatted.inner_mac));
774 input->formatted.tunnel_type =
775 fdir_filter->input.flow.tunnel_flow.tunnel_type;
776 input->formatted.tni_vni =
777 fdir_filter->input.flow.tunnel_flow.tunnel_id;
784 * The below function is taken from the FreeBSD IXGBE drivers release
785 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
786 * before returning, as the signature hash can use 16bits.
788 * The newer driver has optimised functions for calculating bucket and
789 * signature hashes. However they don't support IPv6 type packets for signature
790 * filters so are not used here.
792 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
795 * Compute the hashes for SW ATR
796 * @stream: input bitstream to compute the hash on
797 * @key: 32-bit hash key
800 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
804 * The algorithm is as follows:
805 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
806 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
807 * and A[n] x B[n] is bitwise AND between same length strings
809 * K[n] is 16 bits, defined as:
810 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
811 * for n modulo 32 < 15, K[n] =
812 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
814 * S[n] is 16 bits, defined as:
815 * for n >= 15, S[n] = S[n:n - 15]
816 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
818 * To simplify for programming, the algorithm is implemented
819 * in software this way:
821 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
823 * for (i = 0; i < 352; i+=32)
824 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
826 * lo_hash_dword[15:0] ^= Stream[15:0];
827 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
828 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
830 * hi_hash_dword[31:0] ^= Stream[351:320];
833 * hash[15:0] ^= Stream[15:0];
835 * for (i = 0; i < 16; i++) {
837 * hash[15:0] ^= lo_hash_dword[(i+15):i];
839 * hash[15:0] ^= hi_hash_dword[(i+15):i];
843 __be32 common_hash_dword = 0;
844 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
848 /* record the flow_vm_vlan bits as they are a key part to the hash */
849 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
851 /* generate common hash dword */
852 for (i = 1; i <= 13; i++)
853 common_hash_dword ^= atr_input->dword_stream[i];
855 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
857 /* low dword is word swapped version of common */
858 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
860 /* apply flow ID/VM pool/VLAN ID bits to hash words */
861 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
863 /* Process bits 0 and 16 */
865 hash_result ^= lo_hash_dword;
866 if (key & 0x00010000)
867 hash_result ^= hi_hash_dword;
870 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
871 * delay this because bit 0 of the stream should not be processed
872 * so we do not add the vlan until after bit 0 was processed
874 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
877 /* process the remaining 30 bits in the key 2 bits at a time */
878 for (i = 15; i; i--) {
879 if (key & (0x0001 << i))
880 hash_result ^= lo_hash_dword >> i;
881 if (key & (0x00010000 << i))
882 hash_result ^= hi_hash_dword >> i;
889 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
890 enum rte_fdir_pballoc_type pballoc)
892 if (pballoc == RTE_FDIR_PBALLOC_256K)
893 return ixgbe_atr_compute_hash_82599(input,
894 IXGBE_ATR_BUCKET_HASH_KEY) &
895 PERFECT_BUCKET_256KB_HASH_MASK;
896 else if (pballoc == RTE_FDIR_PBALLOC_128K)
897 return ixgbe_atr_compute_hash_82599(input,
898 IXGBE_ATR_BUCKET_HASH_KEY) &
899 PERFECT_BUCKET_128KB_HASH_MASK;
901 return ixgbe_atr_compute_hash_82599(input,
902 IXGBE_ATR_BUCKET_HASH_KEY) &
903 PERFECT_BUCKET_64KB_HASH_MASK;
907 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
908 * @hw: pointer to hardware structure
911 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
915 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
916 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
917 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
919 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
926 * Calculate the hash value needed for signature-match filters. In the FreeBSD
927 * driver, this is done by the optimised function
928 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
929 * doesn't support calculating a hash for an IPv6 filter.
932 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
933 enum rte_fdir_pballoc_type pballoc)
935 uint32_t bucket_hash, sig_hash;
937 if (pballoc == RTE_FDIR_PBALLOC_256K)
938 bucket_hash = ixgbe_atr_compute_hash_82599(input,
939 IXGBE_ATR_BUCKET_HASH_KEY) &
940 SIG_BUCKET_256KB_HASH_MASK;
941 else if (pballoc == RTE_FDIR_PBALLOC_128K)
942 bucket_hash = ixgbe_atr_compute_hash_82599(input,
943 IXGBE_ATR_BUCKET_HASH_KEY) &
944 SIG_BUCKET_128KB_HASH_MASK;
946 bucket_hash = ixgbe_atr_compute_hash_82599(input,
947 IXGBE_ATR_BUCKET_HASH_KEY) &
948 SIG_BUCKET_64KB_HASH_MASK;
950 sig_hash = ixgbe_atr_compute_hash_82599(input,
951 IXGBE_ATR_SIGNATURE_HASH_KEY);
953 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
957 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
958 * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
959 * added, and IPv6 support also added. The hash value is also pre-calculated
960 * as the pballoc value is needed to do it.
963 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
964 union ixgbe_atr_input *input, uint8_t queue,
965 uint32_t fdircmd, uint32_t fdirhash,
966 enum rte_fdir_mode mode)
968 uint32_t fdirport, fdirvlan;
969 u32 addr_low, addr_high;
972 volatile uint32_t *reg;
974 if (mode == RTE_FDIR_MODE_PERFECT) {
975 /* record the IPv4 address (big-endian)
976 * can not use IXGBE_WRITE_REG.
978 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPSA);
979 *reg = input->formatted.src_ip[0];
980 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPDA);
981 *reg = input->formatted.dst_ip[0];
983 /* record source and destination port (little-endian)*/
984 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
985 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
986 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
987 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
988 } else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
989 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
990 /* for mac vlan and tunnel modes */
991 addr_low = ((u32)input->formatted.inner_mac[0] |
992 ((u32)input->formatted.inner_mac[1] << 8) |
993 ((u32)input->formatted.inner_mac[2] << 16) |
994 ((u32)input->formatted.inner_mac[3] << 24));
995 addr_high = ((u32)input->formatted.inner_mac[4] |
996 ((u32)input->formatted.inner_mac[5] << 8));
998 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
999 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1000 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high);
1001 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0);
1004 if (input->formatted.tunnel_type !=
1005 RTE_FDIR_TUNNEL_TYPE_NVGRE)
1006 tunnel_type = 0x80000000;
1007 tunnel_type |= addr_high;
1008 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1009 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type);
1010 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2),
1011 input->formatted.tni_vni);
1015 /* record vlan (little-endian) and flex_bytes(big-endian) */
1016 fdirvlan = input->formatted.flex_bytes;
1017 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1018 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1019 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1021 /* configure FDIRHASH register */
1022 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1025 * flush all previous writes to make certain registers are
1026 * programmed prior to issuing the command
1028 IXGBE_WRITE_FLUSH(hw);
1030 /* configure FDIRCMD register */
1031 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1032 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1033 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1034 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1035 fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1037 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1039 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1041 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1043 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1049 * This function is based on ixgbe_atr_add_signature_filter_82599() in
1050 * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
1051 * setting extra fields in the FDIRCMD register, and removes the code that was
1052 * verifying the flow_type field. According to the documentation, a flow type of
1053 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
1056 * Adds a signature hash filter
1057 * @hw: pointer to hardware structure
1058 * @input: unique input dword
1059 * @queue: queue index to direct traffic to
1060 * @fdircmd: any extra flags to set in fdircmd register
1061 * @fdirhash: pre-calculated hash value for the filter
1064 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1065 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
1070 PMD_INIT_FUNC_TRACE();
1072 /* configure FDIRCMD register */
1073 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1074 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1075 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1076 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1078 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1079 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1081 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1083 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1085 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1091 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
1092 * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so
1093 * that it can be used for removing signature and perfect filters.
1096 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
1098 uint32_t fdircmd = 0;
1101 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1103 /* flush hash to HW */
1104 IXGBE_WRITE_FLUSH(hw);
1106 /* Query if filter is present */
1107 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1109 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1111 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
1115 /* if filter exists in hardware then remove it */
1116 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1117 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1118 IXGBE_WRITE_FLUSH(hw);
1119 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1120 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1122 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1124 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
1129 static inline struct ixgbe_fdir_filter *
1130 ixgbe_fdir_filter_lookup(struct ixgbe_hw_fdir_info *fdir_info,
1131 union ixgbe_atr_input *key)
1135 ret = rte_hash_lookup(fdir_info->hash_handle, (const void *)key);
1139 return fdir_info->hash_map[ret];
1143 ixgbe_insert_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1144 struct ixgbe_fdir_filter *fdir_filter)
1148 ret = rte_hash_add_key(fdir_info->hash_handle,
1149 &fdir_filter->ixgbe_fdir);
1153 "Failed to insert fdir filter to hash table %d!",
1158 fdir_info->hash_map[ret] = fdir_filter;
1160 TAILQ_INSERT_TAIL(&fdir_info->fdir_list, fdir_filter, entries);
1166 ixgbe_remove_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1167 union ixgbe_atr_input *key)
1170 struct ixgbe_fdir_filter *fdir_filter;
1172 ret = rte_hash_del_key(fdir_info->hash_handle, key);
1175 PMD_DRV_LOG(ERR, "No such fdir filter to delete %d!", ret);
1179 fdir_filter = fdir_info->hash_map[ret];
1180 fdir_info->hash_map[ret] = NULL;
1182 TAILQ_REMOVE(&fdir_info->fdir_list, fdir_filter, entries);
1183 rte_free(fdir_filter);
1189 ixgbe_interpret_fdir_filter(struct rte_eth_dev *dev,
1190 const struct rte_eth_fdir_filter *fdir_filter,
1191 struct ixgbe_fdir_rule *rule)
1193 enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1196 memset(rule, 0, sizeof(struct ixgbe_fdir_rule));
1198 err = ixgbe_fdir_filter_to_atr_input(fdir_filter,
1204 rule->mode = fdir_mode;
1205 if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT)
1206 rule->fdirflags = IXGBE_FDIRCMD_DROP;
1207 rule->queue = fdir_filter->action.rx_queue;
1208 rule->soft_id = fdir_filter->soft_id;
1214 ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
1215 struct ixgbe_fdir_rule *rule,
1219 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1220 uint32_t fdircmd_flags;
1223 bool is_perfect = FALSE;
1225 struct ixgbe_hw_fdir_info *info =
1226 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1227 enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1228 struct ixgbe_fdir_filter *node;
1229 bool add_node = FALSE;
1231 if (fdir_mode == RTE_FDIR_MODE_NONE ||
1232 fdir_mode != rule->mode)
1236 * Sanity check for x550.
1237 * When adding a new filter with flow type set to IPv4,
1238 * the flow director mask should be configed before,
1239 * and the L4 protocol and ports are masked.
1242 (hw->mac.type == ixgbe_mac_X550 ||
1243 hw->mac.type == ixgbe_mac_X550EM_x ||
1244 hw->mac.type == ixgbe_mac_X550EM_a) &&
1245 (rule->ixgbe_fdir.formatted.flow_type ==
1246 IXGBE_ATR_FLOW_TYPE_IPV4) &&
1247 (info->mask.src_port_mask != 0 ||
1248 info->mask.dst_port_mask != 0)) {
1249 PMD_DRV_LOG(ERR, "By this device,"
1250 " IPv4 is not supported without"
1251 " L4 protocol and ports masked!");
1255 if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1256 fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1260 if (rule->ixgbe_fdir.formatted.flow_type &
1261 IXGBE_ATR_L4TYPE_IPV6_MASK) {
1262 PMD_DRV_LOG(ERR, "IPv6 is not supported in"
1266 fdirhash = atr_compute_perfect_hash_82599(&rule->ixgbe_fdir,
1267 dev->data->dev_conf.fdir_conf.pballoc);
1268 fdirhash |= rule->soft_id <<
1269 IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1271 fdirhash = atr_compute_sig_hash_82599(&rule->ixgbe_fdir,
1272 dev->data->dev_conf.fdir_conf.pballoc);
1275 err = ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1279 err = fdir_erase_filter_82599(hw, fdirhash);
1281 PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
1283 PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
1286 /* add or update an fdir filter*/
1287 fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
1288 if (rule->fdirflags & IXGBE_FDIRCMD_DROP) {
1290 queue = dev->data->dev_conf.fdir_conf.drop_queue;
1291 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
1293 PMD_DRV_LOG(ERR, "Drop option is not supported in"
1294 " signature mode.");
1297 } else if (rule->queue < IXGBE_MAX_RX_QUEUE_NUM)
1298 queue = (uint8_t)rule->queue;
1302 node = ixgbe_fdir_filter_lookup(info, &rule->ixgbe_fdir);
1305 node->fdirflags = fdircmd_flags;
1306 node->fdirhash = fdirhash;
1307 node->queue = queue;
1309 PMD_DRV_LOG(ERR, "Conflict with existing fdir filter!");
1314 node = rte_zmalloc("ixgbe_fdir",
1315 sizeof(struct ixgbe_fdir_filter),
1319 (void)rte_memcpy(&node->ixgbe_fdir,
1321 sizeof(union ixgbe_atr_input));
1322 node->fdirflags = fdircmd_flags;
1323 node->fdirhash = fdirhash;
1324 node->queue = queue;
1326 err = ixgbe_insert_fdir_filter(info, node);
1334 err = fdir_write_perfect_filter_82599(hw, &rule->ixgbe_fdir,
1335 queue, fdircmd_flags,
1336 fdirhash, fdir_mode);
1338 err = fdir_add_signature_filter_82599(hw, &rule->ixgbe_fdir,
1339 queue, fdircmd_flags,
1343 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
1346 (void)ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1348 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
1354 /* ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
1355 * @dev: pointer to the structure rte_eth_dev
1356 * @fdir_filter: fdir filter entry
1357 * @del: 1 - delete, 0 - add
1358 * @update: 1 - update
1361 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
1362 const struct rte_eth_fdir_filter *fdir_filter,
1366 struct ixgbe_fdir_rule rule;
1369 err = ixgbe_interpret_fdir_filter(dev, fdir_filter, &rule);
1374 return ixgbe_fdir_filter_program(dev, &rule, del, update);
1378 ixgbe_fdir_flush(struct rte_eth_dev *dev)
1380 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1381 struct ixgbe_hw_fdir_info *info =
1382 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1385 ret = ixgbe_reinit_fdir_tables_82599(hw);
1387 PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
1399 #define FDIRENTRIES_NUM_SHIFT 10
1401 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
1403 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1404 struct ixgbe_hw_fdir_info *info =
1405 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1406 uint32_t fdirctrl, max_num;
1409 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1410 offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
1411 IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
1413 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
1414 max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1415 (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
1416 if (fdir_info->mode >= RTE_FDIR_MODE_PERFECT &&
1417 fdir_info->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1418 fdir_info->guarant_spc = max_num;
1419 else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
1420 fdir_info->guarant_spc = max_num * 4;
1422 fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
1423 fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
1424 fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
1425 IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
1426 fdir_info->mask.ipv6_mask.src_ip);
1427 IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
1428 fdir_info->mask.ipv6_mask.dst_ip);
1429 fdir_info->mask.src_port_mask = info->mask.src_port_mask;
1430 fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
1431 fdir_info->mask.mac_addr_byte_mask = info->mask.mac_addr_byte_mask;
1432 fdir_info->mask.tunnel_id_mask = info->mask.tunnel_id_mask;
1433 fdir_info->mask.tunnel_type_mask = info->mask.tunnel_type_mask;
1434 fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
1436 if (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN ||
1437 fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
1438 fdir_info->flow_types_mask[0] = 0;
1440 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1442 fdir_info->flex_payload_unit = sizeof(uint16_t);
1443 fdir_info->max_flex_payload_segment_num = 1;
1444 fdir_info->flex_payload_limit = IXGBE_MAX_FLX_SOURCE_OFF;
1445 fdir_info->flex_conf.nb_payloads = 1;
1446 fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1447 fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1448 fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1449 fdir_info->flex_conf.nb_flexmasks = 1;
1450 fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;
1451 fdir_info->flex_conf.flex_mask[0].mask[0] =
1452 (uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1453 fdir_info->flex_conf.flex_mask[0].mask[1] =
1454 (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1458 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1460 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461 struct ixgbe_hw_fdir_info *info =
1462 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1463 uint32_t reg, max_num;
1464 enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1466 /* Get the information from registers */
1467 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1468 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1469 IXGBE_FDIRFREE_COLL_SHIFT);
1470 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1471 IXGBE_FDIRFREE_FREE_SHIFT);
1473 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1474 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1475 IXGBE_FDIRLEN_MAXHASH_SHIFT);
1476 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1477 IXGBE_FDIRLEN_MAXLEN_SHIFT);
1479 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1480 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1481 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1482 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1483 IXGBE_FDIRUSTAT_ADD_SHIFT;
1485 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1486 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1487 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1488 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1489 IXGBE_FDIRFSTAT_FADD_SHIFT;
1491 /* Copy the new information in the fdir parameter */
1492 fdir_stats->collision = info->collision;
1493 fdir_stats->free = info->free;
1494 fdir_stats->maxhash = info->maxhash;
1495 fdir_stats->maxlen = info->maxlen;
1496 fdir_stats->remove = info->remove;
1497 fdir_stats->add = info->add;
1498 fdir_stats->f_remove = info->f_remove;
1499 fdir_stats->f_add = info->f_add;
1501 reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1502 max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1503 (reg & FDIRCTRL_PBALLOC_MASK)));
1504 if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1505 fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1506 fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1507 else if (fdir_mode == RTE_FDIR_MODE_SIGNATURE)
1508 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1513 * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1514 * @dev: pointer to the structure rte_eth_dev
1515 * @filter_op:operation will be taken
1516 * @arg: a pointer to specific structure corresponding to the filter_op
1519 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1520 enum rte_filter_op filter_op, void *arg)
1522 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1525 if (hw->mac.type != ixgbe_mac_82599EB &&
1526 hw->mac.type != ixgbe_mac_X540 &&
1527 hw->mac.type != ixgbe_mac_X550 &&
1528 hw->mac.type != ixgbe_mac_X550EM_x &&
1529 hw->mac.type != ixgbe_mac_X550EM_a)
1532 if (filter_op == RTE_ETH_FILTER_NOP)
1535 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1538 switch (filter_op) {
1539 case RTE_ETH_FILTER_ADD:
1540 ret = ixgbe_add_del_fdir_filter(dev,
1541 (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1543 case RTE_ETH_FILTER_UPDATE:
1544 ret = ixgbe_add_del_fdir_filter(dev,
1545 (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1547 case RTE_ETH_FILTER_DELETE:
1548 ret = ixgbe_add_del_fdir_filter(dev,
1549 (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1551 case RTE_ETH_FILTER_FLUSH:
1552 ret = ixgbe_fdir_flush(dev);
1554 case RTE_ETH_FILTER_INFO:
1555 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1557 case RTE_ETH_FILTER_STATS:
1558 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1561 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1568 /* restore flow director filter */
1570 ixgbe_fdir_filter_restore(struct rte_eth_dev *dev)
1572 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573 struct ixgbe_hw_fdir_info *fdir_info =
1574 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1575 struct ixgbe_fdir_filter *node;
1576 bool is_perfect = FALSE;
1577 enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1579 if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1580 fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1584 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1585 (void)fdir_write_perfect_filter_82599(hw,
1593 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1594 (void)fdir_add_signature_filter_82599(hw,
1603 /* remove all the flow director filters */
1605 ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev)
1607 struct ixgbe_hw_fdir_info *fdir_info =
1608 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1609 struct ixgbe_fdir_filter *fdir_filter;
1610 struct ixgbe_fdir_filter *filter_flag;
1613 /* flush flow director */
1614 rte_hash_reset(fdir_info->hash_handle);
1615 memset(fdir_info->hash_map, 0,
1616 sizeof(struct ixgbe_fdir_filter *) * IXGBE_MAX_FDIR_FILTER_NUM);
1617 filter_flag = TAILQ_FIRST(&fdir_info->fdir_list);
1618 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1619 TAILQ_REMOVE(&fdir_info->fdir_list,
1622 rte_free(fdir_filter);
1625 if (filter_flag != NULL)
1626 ret = ixgbe_fdir_flush(dev);