4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <sys/queue.h>
40 #include <rte_interrupts.h>
42 #include <rte_debug.h>
44 #include <rte_ether.h>
45 #include <rte_ethdev.h>
47 #include "ixgbe_logs.h"
48 #include "base/ixgbe_api.h"
49 #include "base/ixgbe_common.h"
50 #include "ixgbe_ethdev.h"
52 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
53 #define FDIRCTRL_PBALLOC_MASK 0x03
55 /* For calculating memory required for FDIR filters */
56 #define PBALLOC_SIZE_SHIFT 15
58 /* Number of bits used to mask bucket hash for different pballoc sizes */
59 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
60 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
61 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
62 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
64 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
65 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET 12 /* default flexbytes offset in bytes */
66 #define IXGBE_FDIR_MAX_FLEX_LEN 2 /* len in bytes of flexbytes */
67 #define IXGBE_MAX_FLX_SOURCE_OFF 62
68 #define IXGBE_FDIRCTRL_FLEX_MASK (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
69 #define IXGBE_FDIRCMD_CMD_INTERVAL_US 10
71 #define IXGBE_FDIR_FLOW_TYPES ( \
72 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
73 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
74 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
75 (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
76 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
77 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
78 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
79 (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
81 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
82 uint8_t ipv6_addr[16]; \
84 rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
86 for (i = 0; i < sizeof(ipv6_addr); i++) { \
87 if (ipv6_addr[i] == UINT8_MAX) \
89 else if (ipv6_addr[i] != 0) { \
90 PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
96 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
97 uint8_t ipv6_addr[16]; \
99 for (i = 0; i < sizeof(ipv6_addr); i++) { \
100 if ((ipv6m) & (1 << i)) \
101 ipv6_addr[i] = UINT8_MAX; \
105 rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
108 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
109 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev,
110 const struct rte_eth_fdir_masks *input_mask);
111 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
112 const struct rte_eth_fdir_flex_conf *conf);
113 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
114 static int ixgbe_fdir_filter_to_atr_input(
115 const struct rte_eth_fdir_filter *fdir_filter,
116 union ixgbe_atr_input *input);
117 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
119 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
120 enum rte_fdir_pballoc_type pballoc);
121 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
122 enum rte_fdir_pballoc_type pballoc);
123 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
124 union ixgbe_atr_input *input, uint8_t queue,
125 uint32_t fdircmd, uint32_t fdirhash);
126 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
127 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
129 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
130 const struct rte_eth_fdir_filter *fdir_filter,
133 static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
134 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
135 struct rte_eth_fdir_info *fdir_info);
136 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
137 struct rte_eth_fdir_stats *fdir_stats);
140 * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.
141 * It adds extra configuration of fdirctrl that is common for all filter types.
143 * Initialize Flow Director control registers
144 * @hw: pointer to hardware structure
145 * @fdirctrl: value to write to flow director control register
148 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
152 PMD_INIT_FUNC_TRACE();
154 /* Prime the keys for hashing */
155 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
156 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
159 * Continue setup of fdirctrl register bits:
160 * Set the maximum length per hash bucket to 0xA filters
161 * Send interrupt when 64 filters are left
163 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
164 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
167 * Poll init-done after we write the register. Estimated times:
168 * 10G: PBALLOC = 11b, timing is 60us
169 * 1G: PBALLOC = 11b, timing is 600us
170 * 100M: PBALLOC = 11b, timing is 6ms
172 * Multiple these timings by 4 if under full Rx load
174 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
175 * 1 msec per poll time. If we're at line rate and drop to 100M, then
176 * this might not finish in our poll time, but we can live with that
179 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
180 IXGBE_WRITE_FLUSH(hw);
181 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
182 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
183 IXGBE_FDIRCTRL_INIT_DONE)
188 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
189 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded "
197 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
198 * flexbytes matching field, and drop queue (only for perfect matching mode).
201 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
205 switch (conf->pballoc) {
206 case RTE_FDIR_PBALLOC_64K:
207 /* 8k - 1 signature filters */
208 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
210 case RTE_FDIR_PBALLOC_128K:
211 /* 16k - 1 signature filters */
212 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
214 case RTE_FDIR_PBALLOC_256K:
215 /* 32k - 1 signature filters */
216 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
220 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
224 /* status flags: write hash & swindex in the rx descriptor */
225 switch (conf->status) {
226 case RTE_FDIR_NO_REPORT_STATUS:
227 /* do nothing, default mode */
229 case RTE_FDIR_REPORT_STATUS:
230 /* report status when the packet matches a fdir rule */
231 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
233 case RTE_FDIR_REPORT_STATUS_ALWAYS:
234 /* always report status */
235 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
239 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
243 *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
244 IXGBE_FDIRCTRL_FLEX_SHIFT;
246 if (conf->mode == RTE_FDIR_MODE_PERFECT) {
247 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
248 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
251 * Continue setup of fdirctrl register bits:
252 * Set the maximum length per hash bucket to 0xA filters
253 * Send interrupt when 64 filters are left
255 *fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
256 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
262 * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
264 * @hi_dword: Bits 31:16 mask to be bit swapped.
265 * @lo_dword: Bits 15:0 mask to be bit swapped.
267 * Flow director uses several registers to store 2 x 16 bit masks with the
268 * bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
269 * mask affects the MS bit/byte of the target. This function reverses the
270 * bits in these masks.
272 static inline uint32_t
273 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
275 uint32_t mask = hi_dword << 16;
277 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
278 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
279 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
280 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
284 * This is based on ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
285 * but makes use of the rte_fdir_masks structure to see which bits to set.
288 fdir_set_input_mask_82599(struct rte_eth_dev *dev,
289 const struct rte_eth_fdir_masks *input_mask)
291 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
292 struct ixgbe_hw_fdir_info *info =
293 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
295 * mask VM pool and DIPv6 since there are currently not supported
296 * mask FLEX byte, it will be set in flex_conf
298 uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
299 uint32_t fdirtcpm; /* TCP source and destination port masks. */
300 uint32_t fdiripv6m; /* IPv6 source and destination masks. */
301 uint16_t dst_ipv6m = 0;
302 uint16_t src_ipv6m = 0;
304 PMD_INIT_FUNC_TRACE();
307 * Program the relevant mask registers. If src/dst_port or src/dst_addr
308 * are zero, then assume a full mask for that field. Also assume that
309 * a VLAN of 0 is unspecified, so mask that out as well. L4type
310 * cannot be masked out in this implementation.
312 if (input_mask->dst_port_mask == 0 && input_mask->src_port_mask == 0)
313 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
314 fdirm |= IXGBE_FDIRM_L4P;
316 if (input_mask->vlan_tci_mask == 0x0FFF)
317 /* mask VLAN Priority */
318 fdirm |= IXGBE_FDIRM_VLANP;
319 else if (input_mask->vlan_tci_mask == 0xE000)
321 fdirm |= IXGBE_FDIRM_VLANID;
322 else if (input_mask->vlan_tci_mask == 0)
323 /* mask VLAN ID and Priority */
324 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
325 else if (input_mask->vlan_tci_mask != 0xEFFF) {
326 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
329 info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
331 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
333 /* store the TCP/UDP port masks, bit reversed from port layout */
334 fdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask,
335 input_mask->src_port_mask);
337 /* write both the same so that UDP and TCP use the same mask */
338 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
339 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
340 info->mask.src_port_mask = input_mask->src_port_mask;
341 info->mask.dst_port_mask = input_mask->dst_port_mask;
343 /* Store source and destination IPv4 masks (big-endian) */
344 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, ~(input_mask->ipv4_mask.src_ip));
345 IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, ~(input_mask->ipv4_mask.dst_ip));
346 info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
347 info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
349 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
351 * IPv6 mask is only meaningful in signature mode
352 * Store source and destination IPv6 masks (bit reversed)
354 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
355 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
356 fdiripv6m = (dst_ipv6m << 16) | src_ipv6m;
358 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
359 info->mask.src_ipv6_mask = src_ipv6m;
360 info->mask.dst_ipv6_mask = dst_ipv6m;
363 return IXGBE_SUCCESS;
367 * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
368 * arguments are valid
371 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
372 const struct rte_eth_fdir_flex_conf *conf)
374 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
375 struct ixgbe_hw_fdir_info *info =
376 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
377 const struct rte_eth_flex_payload_cfg *flex_cfg;
378 const struct rte_eth_fdir_flex_mask *flex_mask;
379 uint32_t fdirctrl, fdirm;
380 uint16_t flexbytes = 0;
383 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
384 fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
387 PMD_DRV_LOG(INFO, "NULL pointer.");
391 for (i = 0; i < conf->nb_payloads; i++) {
392 flex_cfg = &conf->flex_set[i];
393 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
394 PMD_DRV_LOG(ERR, "unsupported payload type.");
397 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
398 (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
399 (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
400 fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
401 fdirctrl |= (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
402 IXGBE_FDIRCTRL_FLEX_SHIFT;
404 PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
409 for (i = 0; i < conf->nb_flexmasks; i++) {
410 flex_mask = &conf->flex_mask[i];
411 if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
412 PMD_DRV_LOG(ERR, "flexmask should be set globally.");
415 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
416 ((flex_mask->mask[1]) & 0xFF));
417 if (flexbytes == UINT16_MAX)
418 fdirm &= ~IXGBE_FDIRM_FLEX;
419 else if (flexbytes != 0) {
420 /* IXGBE_FDIRM_FLEX is set by default when set mask */
421 PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
425 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
426 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
427 info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
428 info->flex_bytes_offset = (uint8_t)((fdirctrl &
429 IXGBE_FDIRCTRL_FLEX_MASK) >>
430 IXGBE_FDIRCTRL_FLEX_SHIFT);
435 ixgbe_fdir_configure(struct rte_eth_dev *dev)
437 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
439 uint32_t fdirctrl, pbsize;
442 PMD_INIT_FUNC_TRACE();
444 if (hw->mac.type != ixgbe_mac_82599EB &&
445 hw->mac.type != ixgbe_mac_X540 &&
446 hw->mac.type != ixgbe_mac_X550 &&
447 hw->mac.type != ixgbe_mac_X550EM_x)
450 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
455 * Before enabling Flow Director, the Rx Packet Buffer size
456 * must be reduced. The new value is the current size minus
457 * flow director memory usage size.
459 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
460 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
461 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
464 * The defaults in the HW for RX PB 1-7 are not zero and so should be
465 * intialized to zero for non DCB mode otherwise actual total RX PB
466 * would be bigger than programmed and filter space would run into
469 for (i = 1; i < 8; i++)
470 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
472 err = fdir_set_input_mask_82599(dev, &dev->data->dev_conf.fdir_conf.mask);
474 PMD_INIT_LOG(ERR, " Error on setting FD mask");
477 err = ixgbe_set_fdir_flex_conf(dev,
478 &dev->data->dev_conf.fdir_conf.flex_conf);
480 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
484 err = fdir_enable_82599(hw, fdirctrl);
486 PMD_INIT_LOG(ERR, " Error on enabling FD.");
493 * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
494 * by the IXGBE driver code.
497 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
498 union ixgbe_atr_input *input)
500 input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
501 input->formatted.flex_bytes = (uint16_t)(
502 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
503 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
505 switch (fdir_filter->input.flow_type) {
506 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
507 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
509 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
510 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
512 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
513 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
515 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
516 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
518 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
519 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
521 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
522 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
524 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
525 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
527 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
528 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
531 PMD_DRV_LOG(ERR, " Error on flow_type input");
535 switch (fdir_filter->input.flow_type) {
536 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
537 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
538 input->formatted.src_port =
539 fdir_filter->input.flow.udp4_flow.src_port;
540 input->formatted.dst_port =
541 fdir_filter->input.flow.udp4_flow.dst_port;
542 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
543 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
544 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
545 input->formatted.src_ip[0] =
546 fdir_filter->input.flow.ip4_flow.src_ip;
547 input->formatted.dst_ip[0] =
548 fdir_filter->input.flow.ip4_flow.dst_ip;
551 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
552 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
553 input->formatted.src_port =
554 fdir_filter->input.flow.udp6_flow.src_port;
555 input->formatted.dst_port =
556 fdir_filter->input.flow.udp6_flow.dst_port;
557 /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
558 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
559 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
560 rte_memcpy(input->formatted.src_ip,
561 fdir_filter->input.flow.ipv6_flow.src_ip,
562 sizeof(input->formatted.src_ip));
563 rte_memcpy(input->formatted.dst_ip,
564 fdir_filter->input.flow.ipv6_flow.dst_ip,
565 sizeof(input->formatted.dst_ip));
568 PMD_DRV_LOG(ERR, " Error on flow_type input");
576 * The below function is taken from the FreeBSD IXGBE drivers release
577 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
578 * before returning, as the signature hash can use 16bits.
580 * The newer driver has optimised functions for calculating bucket and
581 * signature hashes. However they don't support IPv6 type packets for signature
582 * filters so are not used here.
584 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
587 * Compute the hashes for SW ATR
588 * @stream: input bitstream to compute the hash on
589 * @key: 32-bit hash key
592 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
596 * The algorithm is as follows:
597 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
598 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
599 * and A[n] x B[n] is bitwise AND between same length strings
601 * K[n] is 16 bits, defined as:
602 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
603 * for n modulo 32 < 15, K[n] =
604 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
606 * S[n] is 16 bits, defined as:
607 * for n >= 15, S[n] = S[n:n - 15]
608 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
610 * To simplify for programming, the algorithm is implemented
611 * in software this way:
613 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
615 * for (i = 0; i < 352; i+=32)
616 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
618 * lo_hash_dword[15:0] ^= Stream[15:0];
619 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
620 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
622 * hi_hash_dword[31:0] ^= Stream[351:320];
625 * hash[15:0] ^= Stream[15:0];
627 * for (i = 0; i < 16; i++) {
629 * hash[15:0] ^= lo_hash_dword[(i+15):i];
631 * hash[15:0] ^= hi_hash_dword[(i+15):i];
635 __be32 common_hash_dword = 0;
636 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
640 /* record the flow_vm_vlan bits as they are a key part to the hash */
641 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
643 /* generate common hash dword */
644 for (i = 1; i <= 13; i++)
645 common_hash_dword ^= atr_input->dword_stream[i];
647 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
649 /* low dword is word swapped version of common */
650 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
652 /* apply flow ID/VM pool/VLAN ID bits to hash words */
653 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
655 /* Process bits 0 and 16 */
656 if (key & 0x0001) hash_result ^= lo_hash_dword;
657 if (key & 0x00010000) hash_result ^= hi_hash_dword;
660 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
661 * delay this because bit 0 of the stream should not be processed
662 * so we do not add the vlan until after bit 0 was processed
664 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
667 /* process the remaining 30 bits in the key 2 bits at a time */
668 for (i = 15; i; i-- ) {
669 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
670 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
677 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
678 enum rte_fdir_pballoc_type pballoc)
680 if (pballoc == RTE_FDIR_PBALLOC_256K)
681 return ixgbe_atr_compute_hash_82599(input,
682 IXGBE_ATR_BUCKET_HASH_KEY) &
683 PERFECT_BUCKET_256KB_HASH_MASK;
684 else if (pballoc == RTE_FDIR_PBALLOC_128K)
685 return ixgbe_atr_compute_hash_82599(input,
686 IXGBE_ATR_BUCKET_HASH_KEY) &
687 PERFECT_BUCKET_128KB_HASH_MASK;
689 return ixgbe_atr_compute_hash_82599(input,
690 IXGBE_ATR_BUCKET_HASH_KEY) &
691 PERFECT_BUCKET_64KB_HASH_MASK;
695 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
696 * @hw: pointer to hardware structure
699 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
703 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
704 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
705 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
707 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
714 * Calculate the hash value needed for signature-match filters. In the FreeBSD
715 * driver, this is done by the optimised function
716 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
717 * doesn't support calculating a hash for an IPv6 filter.
720 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
721 enum rte_fdir_pballoc_type pballoc)
723 uint32_t bucket_hash, sig_hash;
725 if (pballoc == RTE_FDIR_PBALLOC_256K)
726 bucket_hash = ixgbe_atr_compute_hash_82599(input,
727 IXGBE_ATR_BUCKET_HASH_KEY) &
728 SIG_BUCKET_256KB_HASH_MASK;
729 else if (pballoc == RTE_FDIR_PBALLOC_128K)
730 bucket_hash = ixgbe_atr_compute_hash_82599(input,
731 IXGBE_ATR_BUCKET_HASH_KEY) &
732 SIG_BUCKET_128KB_HASH_MASK;
734 bucket_hash = ixgbe_atr_compute_hash_82599(input,
735 IXGBE_ATR_BUCKET_HASH_KEY) &
736 SIG_BUCKET_64KB_HASH_MASK;
738 sig_hash = ixgbe_atr_compute_hash_82599(input,
739 IXGBE_ATR_SIGNATURE_HASH_KEY);
741 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
745 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
746 * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
747 * added, and IPv6 support also added. The hash value is also pre-calculated
748 * as the pballoc value is needed to do it.
751 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
752 union ixgbe_atr_input *input, uint8_t queue,
753 uint32_t fdircmd, uint32_t fdirhash)
755 uint32_t fdirport, fdirvlan;
758 /* record the IPv4 address (big-endian) */
759 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
760 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
762 /* record source and destination port (little-endian)*/
763 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
764 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
765 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
766 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
768 /* record vlan (little-endian) and flex_bytes(big-endian) */
769 fdirvlan = input->formatted.flex_bytes;
770 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
771 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
772 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
774 /* configure FDIRHASH register */
775 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
778 * flush all previous writes to make certain registers are
779 * programmed prior to issuing the command
781 IXGBE_WRITE_FLUSH(hw);
783 /* configure FDIRCMD register */
784 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
785 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
786 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
787 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
788 fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
790 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
792 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
794 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
796 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
802 * This function is based on ixgbe_atr_add_signature_filter_82599() in
803 * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
804 * setting extra fields in the FDIRCMD register, and removes the code that was
805 * verifying the flow_type field. According to the documentation, a flow type of
806 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
809 * Adds a signature hash filter
810 * @hw: pointer to hardware structure
811 * @input: unique input dword
812 * @queue: queue index to direct traffic to
813 * @fdircmd: any extra flags to set in fdircmd register
814 * @fdirhash: pre-calculated hash value for the filter
817 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
818 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
823 PMD_INIT_FUNC_TRACE();
825 /* configure FDIRCMD register */
826 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
827 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
828 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
829 fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
831 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
832 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
834 PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
836 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
838 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
844 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
845 * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so
846 * that it can be used for removing signature and perfect filters.
849 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
851 uint32_t fdircmd = 0;
854 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
856 /* flush hash to HW */
857 IXGBE_WRITE_FLUSH(hw);
859 /* Query if filter is present */
860 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
862 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
864 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
868 /* if filter exists in hardware then remove it */
869 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
870 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
871 IXGBE_WRITE_FLUSH(hw);
872 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
873 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
875 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
877 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
883 * ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
884 * @dev: pointer to the structure rte_eth_dev
885 * @fdir_filter: fdir filter entry
886 * @del: 1 - delete, 0 - add
887 * @update: 1 - update
890 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
891 const struct rte_eth_fdir_filter *fdir_filter,
895 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
896 uint32_t fdircmd_flags;
898 union ixgbe_atr_input input;
900 bool is_perfect = FALSE;
903 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_NONE)
906 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
909 memset(&input, 0, sizeof(input));
911 err = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input);
916 if (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
917 PMD_DRV_LOG(ERR, "IPv6 is not supported in"
921 fdirhash = atr_compute_perfect_hash_82599(&input,
922 dev->data->dev_conf.fdir_conf.pballoc);
923 fdirhash |= fdir_filter->soft_id <<
924 IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
926 fdirhash = atr_compute_sig_hash_82599(&input,
927 dev->data->dev_conf.fdir_conf.pballoc);
930 err = fdir_erase_filter_82599(hw, fdirhash);
932 PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
934 PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
937 /* add or update an fdir filter*/
938 fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
939 if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) {
941 queue = dev->data->dev_conf.fdir_conf.drop_queue;
942 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
944 PMD_DRV_LOG(ERR, "Drop option is not supported in"
948 } else if (fdir_filter->action.rx_queue < IXGBE_MAX_RX_QUEUE_NUM)
949 queue = (uint8_t)fdir_filter->action.rx_queue;
954 err = fdir_write_perfect_filter_82599(hw, &input, queue,
955 fdircmd_flags, fdirhash);
957 err = fdir_add_signature_filter_82599(hw, &input, queue,
958 fdircmd_flags, fdirhash);
961 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
963 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
969 ixgbe_fdir_flush(struct rte_eth_dev *dev)
971 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
972 struct ixgbe_hw_fdir_info *info =
973 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
976 ret = ixgbe_reinit_fdir_tables_82599(hw);
978 PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
990 #define FDIRENTRIES_NUM_SHIFT 10
992 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
994 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
995 struct ixgbe_hw_fdir_info *info =
996 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
997 uint32_t fdirctrl, max_num;
1000 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1001 offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
1002 IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
1004 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
1005 max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1006 (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
1007 if (fdir_info->mode == RTE_FDIR_MODE_PERFECT)
1008 fdir_info->guarant_spc = max_num;
1009 else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
1010 fdir_info->guarant_spc = max_num * 4;
1012 fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
1013 fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
1014 fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
1015 IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
1016 fdir_info->mask.ipv6_mask.src_ip);
1017 IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
1018 fdir_info->mask.ipv6_mask.dst_ip);
1019 fdir_info->mask.src_port_mask = info->mask.src_port_mask;
1020 fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
1021 fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
1022 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1023 fdir_info->flex_payload_unit = sizeof(uint16_t);
1024 fdir_info->max_flex_payload_segment_num = 1;
1025 fdir_info->flex_payload_limit = 62;
1026 fdir_info->flex_conf.nb_payloads = 1;
1027 fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1028 fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1029 fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1030 fdir_info->flex_conf.nb_flexmasks = 1;
1031 fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;
1032 fdir_info->flex_conf.flex_mask[0].mask[0] =
1033 (uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1034 fdir_info->flex_conf.flex_mask[0].mask[1] =
1035 (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1039 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1041 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1042 struct ixgbe_hw_fdir_info *info =
1043 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1044 uint32_t reg, max_num;
1046 /* Get the information from registers */
1047 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1048 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1049 IXGBE_FDIRFREE_COLL_SHIFT);
1050 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1051 IXGBE_FDIRFREE_FREE_SHIFT);
1053 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1054 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1055 IXGBE_FDIRLEN_MAXHASH_SHIFT);
1056 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1057 IXGBE_FDIRLEN_MAXLEN_SHIFT);
1059 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1060 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1061 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1062 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1063 IXGBE_FDIRUSTAT_ADD_SHIFT;
1065 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1066 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1067 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1068 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1069 IXGBE_FDIRFSTAT_FADD_SHIFT;
1071 /* Copy the new information in the fdir parameter */
1072 fdir_stats->collision = info->collision;
1073 fdir_stats->free = info->free;
1074 fdir_stats->maxhash = info->maxhash;
1075 fdir_stats->maxlen = info->maxlen;
1076 fdir_stats->remove = info->remove;
1077 fdir_stats->add = info->add;
1078 fdir_stats->f_remove = info->f_remove;
1079 fdir_stats->f_add = info->f_add;
1081 reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1082 max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1083 (reg & FDIRCTRL_PBALLOC_MASK)));
1084 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1085 fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1086 else if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE)
1087 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1092 * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1093 * @dev: pointer to the structure rte_eth_dev
1094 * @filter_op:operation will be taken
1095 * @arg: a pointer to specific structure corresponding to the filter_op
1098 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1099 enum rte_filter_op filter_op, void *arg)
1101 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1104 if (hw->mac.type != ixgbe_mac_82599EB &&
1105 hw->mac.type != ixgbe_mac_X540 &&
1106 hw->mac.type != ixgbe_mac_X550 &&
1107 hw->mac.type != ixgbe_mac_X550EM_x)
1110 if (filter_op == RTE_ETH_FILTER_NOP)
1113 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1116 switch (filter_op) {
1117 case RTE_ETH_FILTER_ADD:
1118 ret = ixgbe_add_del_fdir_filter(dev,
1119 (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1121 case RTE_ETH_FILTER_UPDATE:
1122 ret = ixgbe_add_del_fdir_filter(dev,
1123 (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1125 case RTE_ETH_FILTER_DELETE:
1126 ret = ixgbe_add_del_fdir_filter(dev,
1127 (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1129 case RTE_ETH_FILTER_FLUSH:
1130 ret = ixgbe_fdir_flush(dev);
1132 case RTE_ETH_FILTER_INFO:
1133 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1135 case RTE_ETH_FILTER_STATS:
1136 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1139 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);