drivers/net/ixgbe/ixgbe_fdir.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2015 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdint.h>
   7 #include <stdarg.h>
   8 #include <errno.h>
   9 #include <sys/queue.h>
  10
  11 #include <rte_interrupts.h>
  12 #include <rte_log.h>
  13 #include <rte_debug.h>
  14 #include <rte_pci.h>
  15 #include <rte_ether.h>
  16 #include <rte_ethdev_driver.h>
  17 #include <rte_malloc.h>
  18
  19 #include "ixgbe_logs.h"
  20 #include "base/ixgbe_api.h"
  21 #include "base/ixgbe_common.h"
  22 #include "ixgbe_ethdev.h"
  23
  24 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
  25 #define FDIRCTRL_PBALLOC_MASK           0x03
  26
  27 /* For calculating memory required for FDIR filters */
  28 #define PBALLOC_SIZE_SHIFT              15
  29
  30 /* Number of bits used to mask bucket hash for different pballoc sizes */
  31 #define PERFECT_BUCKET_64KB_HASH_MASK   0x07FF  /* 11 bits */
  32 #define PERFECT_BUCKET_128KB_HASH_MASK  0x0FFF  /* 12 bits */
  33 #define PERFECT_BUCKET_256KB_HASH_MASK  0x1FFF  /* 13 bits */
  34 #define SIG_BUCKET_64KB_HASH_MASK       0x1FFF  /* 13 bits */
  35 #define SIG_BUCKET_128KB_HASH_MASK      0x3FFF  /* 14 bits */
  36 #define SIG_BUCKET_256KB_HASH_MASK      0x7FFF  /* 15 bits */
  37 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET  12 /* default flexbytes offset in bytes */
  38 #define IXGBE_FDIR_MAX_FLEX_LEN         2 /* len in bytes of flexbytes */
  39 #define IXGBE_MAX_FLX_SOURCE_OFF        62
  40 #define IXGBE_FDIRCTRL_FLEX_MASK        (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
  41 #define IXGBE_FDIRCMD_CMD_INTERVAL_US   10
  42
  43 #define IXGBE_FDIR_FLOW_TYPES ( \
  44         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  45         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  46         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  47         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  48         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
  49         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
  50         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
  51         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
  52
  53 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
  54         uint8_t ipv6_addr[16]; \
  55         uint8_t i; \
  56         rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
  57         (ipv6m) = 0; \
  58         for (i = 0; i < sizeof(ipv6_addr); i++) { \
  59                 if (ipv6_addr[i] == UINT8_MAX) \
  60                         (ipv6m) |= 1 << i; \
  61                 else if (ipv6_addr[i] != 0) { \
  62                         PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
  63                         return -EINVAL; \
  64                 } \
  65         } \
  66 } while (0)
  67
  68 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
  69         uint8_t ipv6_addr[16]; \
  70         uint8_t i; \
  71         for (i = 0; i < sizeof(ipv6_addr); i++) { \
  72                 if ((ipv6m) & (1 << i)) \
  73                         ipv6_addr[i] = UINT8_MAX; \
  74                 else \
  75                         ipv6_addr[i] = 0; \
  76         } \
  77         rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
  78 } while (0)
  79
  80 #define DEFAULT_VXLAN_PORT 4789
  81 #define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4
  82
  83 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
  84 static int fdir_set_input_mask(struct rte_eth_dev *dev,
  85                                const struct rte_eth_fdir_masks *input_mask);
  86 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev);
  87 static int fdir_set_input_mask_x550(struct rte_eth_dev *dev);
  88 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
  89                 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);
  90 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
  91 static int ixgbe_fdir_filter_to_atr_input(
  92                 const struct rte_eth_fdir_filter *fdir_filter,
  93                 union ixgbe_atr_input *input,
  94                 enum rte_fdir_mode mode);
  95 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
  96                                  uint32_t key);
  97 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
  98                 enum rte_fdir_pballoc_type pballoc);
  99 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 100                 enum rte_fdir_pballoc_type pballoc);
 101 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 102                         union ixgbe_atr_input *input, uint8_t queue,
 103                         uint32_t fdircmd, uint32_t fdirhash,
 104                         enum rte_fdir_mode mode);
 105 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 106                 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
 107                 uint32_t fdirhash);
 108 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
 109                               const struct rte_eth_fdir_filter *fdir_filter,
 110                               bool del,
 111                               bool update);
 112 static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
 113 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
 114                         struct rte_eth_fdir_info *fdir_info);
 115 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
 116                         struct rte_eth_fdir_stats *fdir_stats);
 117
 118 /**
 119  * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.
 120  * It adds extra configuration of fdirctrl that is common for all filter types.
 121  *
 122  *  Initialize Flow Director control registers
 123  *  @hw: pointer to hardware structure
 124  *  @fdirctrl: value to write to flow director control register
 125  **/
 126 static int
 127 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
 128 {
 129         int i;
 130
 131         PMD_INIT_FUNC_TRACE();
 132
 133         /* Prime the keys for hashing */
 134         IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
 135         IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 136
 137         /*
 138          * Continue setup of fdirctrl register bits:
 139          *  Set the maximum length per hash bucket to 0xA filters
 140          *  Send interrupt when 64 filters are left
 141          */
 142         fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
 143                     (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
 144
 145         /*
 146          * Poll init-done after we write the register.  Estimated times:
 147          *      10G: PBALLOC = 11b, timing is 60us
 148          *       1G: PBALLOC = 11b, timing is 600us
 149          *     100M: PBALLOC = 11b, timing is 6ms
 150          *
 151          *     Multiple these timings by 4 if under full Rx load
 152          *
 153          * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 154          * 1 msec per poll time.  If we're at line rate and drop to 100M, then
 155          * this might not finish in our poll time, but we can live with that
 156          * for now.
 157          */
 158         IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 159         IXGBE_WRITE_FLUSH(hw);
 160         for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 161                 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
 162                                    IXGBE_FDIRCTRL_INIT_DONE)
 163                         break;
 164                 msec_delay(1);
 165         }
 166
 167         if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
 168                 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded during enabling!");
 169                 return -ETIMEDOUT;
 170         }
 171         return 0;
 172 }
 173
 174 /*
 175  * Set appropriate bits in fdirctrl for: variable reporting levels, moving
 176  * flexbytes matching field, and drop queue (only for perfect matching mode).
 177  */
 178 static inline int
 179 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
 180 {
 181         *fdirctrl = 0;
 182
 183         switch (conf->pballoc) {
 184         case RTE_FDIR_PBALLOC_64K:
 185                 /* 8k - 1 signature filters */
 186                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
 187                 break;
 188         case RTE_FDIR_PBALLOC_128K:
 189                 /* 16k - 1 signature filters */
 190                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
 191                 break;
 192         case RTE_FDIR_PBALLOC_256K:
 193                 /* 32k - 1 signature filters */
 194                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
 195                 break;
 196         default:
 197                 /* bad value */
 198                 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
 199                 return -EINVAL;
 200         };
 201
 202         /* status flags: write hash & swindex in the rx descriptor */
 203         switch (conf->status) {
 204         case RTE_FDIR_NO_REPORT_STATUS:
 205                 /* do nothing, default mode */
 206                 break;
 207         case RTE_FDIR_REPORT_STATUS:
 208                 /* report status when the packet matches a fdir rule */
 209                 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
 210                 break;
 211         case RTE_FDIR_REPORT_STATUS_ALWAYS:
 212                 /* always report status */
 213                 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
 214                 break;
 215         default:
 216                 /* bad value */
 217                 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
 218                 return -EINVAL;
 219         };
 220
 221         *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
 222                      IXGBE_FDIRCTRL_FLEX_SHIFT;
 223
 224         if (conf->mode >= RTE_FDIR_MODE_PERFECT &&
 225             conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
 226                 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
 227                 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
 228                 if (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
 229                         *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN
 230                                         << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
 231                 else if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
 232                         *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD
 233                                         << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
 234         }
 235
 236         return 0;
 237 }
 238
 239 /**
 240  * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
 241  *
 242  *  @hi_dword: Bits 31:16 mask to be bit swapped.
 243  *  @lo_dword: Bits 15:0  mask to be bit swapped.
 244  *
 245  *  Flow director uses several registers to store 2 x 16 bit masks with the
 246  *  bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
 247  *  mask affects the MS bit/byte of the target. This function reverses the
 248  *  bits in these masks.
 249  *  **/
 250 static inline uint32_t
 251 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
 252 {
 253         uint32_t mask = hi_dword << 16;
 254
 255         mask |= lo_dword;
 256         mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
 257         mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
 258         mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
 259         return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
 260 }
 261
 262 /*
 263  * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
 264  * but makes use of the rte_fdir_masks structure to see which bits to set.
 265  */
 266 static int
 267 fdir_set_input_mask_82599(struct rte_eth_dev *dev)
 268 {
 269         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 270         struct ixgbe_hw_fdir_info *info =
 271                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 272         /*
 273          * mask VM pool and DIPv6 since there are currently not supported
 274          * mask FLEX byte, it will be set in flex_conf
 275          */
 276         uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
 277         uint32_t fdirtcpm;  /* TCP source and destination port masks. */
 278         uint32_t fdiripv6m; /* IPv6 source and destination masks. */
 279         volatile uint32_t *reg;
 280
 281         PMD_INIT_FUNC_TRACE();
 282
 283         /*
 284          * Program the relevant mask registers.  If src/dst_port or src/dst_addr
 285          * are zero, then assume a full mask for that field. Also assume that
 286          * a VLAN of 0 is unspecified, so mask that out as well.  L4type
 287          * cannot be masked out in this implementation.
 288          */
 289         if (info->mask.dst_port_mask == 0 && info->mask.src_port_mask == 0)
 290                 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
 291                 fdirm |= IXGBE_FDIRM_L4P;
 292
 293         if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
 294                 /* mask VLAN Priority */
 295                 fdirm |= IXGBE_FDIRM_VLANP;
 296         else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
 297                 /* mask VLAN ID */
 298                 fdirm |= IXGBE_FDIRM_VLANID;
 299         else if (info->mask.vlan_tci_mask == 0)
 300                 /* mask VLAN ID and Priority */
 301                 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
 302         else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
 303                 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
 304                 return -EINVAL;
 305         }
 306
 307         /* flex byte mask */
 308         if (info->mask.flex_bytes_mask == 0)
 309                 fdirm |= IXGBE_FDIRM_FLEX;
 310
 311         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 312
 313         /* store the TCP/UDP port masks, bit reversed from port layout */
 314         fdirtcpm = reverse_fdir_bitmasks(
 315                         rte_be_to_cpu_16(info->mask.dst_port_mask),
 316                         rte_be_to_cpu_16(info->mask.src_port_mask));
 317
 318         /* write all the same so that UDP, TCP and SCTP use the same mask
 319          * (little-endian)
 320          */
 321         IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
 322         IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
 323         IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
 324
 325         /* Store source and destination IPv4 masks (big-endian),
 326          * can not use IXGBE_WRITE_REG.
 327          */
 328         reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRSIP4M);
 329         *reg = ~(info->mask.src_ipv4_mask);
 330         reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRDIP4M);
 331         *reg = ~(info->mask.dst_ipv4_mask);
 332
 333         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
 334                 /*
 335                  * Store source and destination IPv6 masks (bit reversed)
 336                  */
 337                 fdiripv6m = (info->mask.dst_ipv6_mask << 16) |
 338                             info->mask.src_ipv6_mask;
 339
 340                 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
 341         }
 342
 343         return IXGBE_SUCCESS;
 344 }
 345
 346 /*
 347  * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
 348  * but makes use of the rte_fdir_masks structure to see which bits to set.
 349  */
 350 static int
 351 fdir_set_input_mask_x550(struct rte_eth_dev *dev)
 352 {
 353         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 354         struct ixgbe_hw_fdir_info *info =
 355                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 356         /* mask VM pool and DIPv6 since there are currently not supported
 357          * mask FLEX byte, it will be set in flex_conf
 358          */
 359         uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 |
 360                          IXGBE_FDIRM_FLEX;
 361         uint32_t fdiripv6m;
 362         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 363         uint16_t mac_mask;
 364
 365         PMD_INIT_FUNC_TRACE();
 366
 367         /* set the default UDP port for VxLAN */
 368         if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
 369                 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT);
 370
 371         /* some bits must be set for mac vlan or tunnel mode */
 372         fdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P;
 373
 374         if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
 375                 /* mask VLAN Priority */
 376                 fdirm |= IXGBE_FDIRM_VLANP;
 377         else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
 378                 /* mask VLAN ID */
 379                 fdirm |= IXGBE_FDIRM_VLANID;
 380         else if (info->mask.vlan_tci_mask == 0)
 381                 /* mask VLAN ID and Priority */
 382                 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
 383         else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
 384                 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
 385                 return -EINVAL;
 386         }
 387
 388         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 389
 390         fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
 391         fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
 392         if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
 393                 fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |
 394                                 IXGBE_FDIRIP6M_TNI_VNI;
 395
 396         if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
 397                 fdiripv6m |= IXGBE_FDIRIP6M_INNER_MAC;
 398                 mac_mask = info->mask.mac_addr_byte_mask &
 399                         (IXGBE_FDIRIP6M_INNER_MAC >>
 400                         IXGBE_FDIRIP6M_INNER_MAC_SHIFT);
 401                 fdiripv6m &= ~((mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT) &
 402                                 IXGBE_FDIRIP6M_INNER_MAC);
 403
 404                 switch (info->mask.tunnel_type_mask) {
 405                 case 0:
 406                         /* Mask turnnel type */
 407                         fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
 408                         break;
 409                 case 1:
 410                         break;
 411                 default:
 412                         PMD_INIT_LOG(ERR, "invalid tunnel_type_mask");
 413                         return -EINVAL;
 414                 }
 415
 416                 switch (rte_be_to_cpu_32(info->mask.tunnel_id_mask)) {
 417                 case 0x0:
 418                         /* Mask vxlan id */
 419                         fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI;
 420                         break;
 421                 case 0x00FFFFFF:
 422                         fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
 423                         break;
 424                 case 0xFFFFFFFF:
 425                         break;
 426                 default:
 427                         PMD_INIT_LOG(ERR, "invalid tunnel_id_mask");
 428                         return -EINVAL;
 429                 }
 430         }
 431
 432         IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m);
 433         IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
 434         IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
 435         IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
 436         IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
 437         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
 438
 439         return IXGBE_SUCCESS;
 440 }
 441
 442 static int
 443 ixgbe_fdir_store_input_mask_82599(struct rte_eth_dev *dev,
 444                                   const struct rte_eth_fdir_masks *input_mask)
 445 {
 446         struct ixgbe_hw_fdir_info *info =
 447                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 448         uint16_t dst_ipv6m = 0;
 449         uint16_t src_ipv6m = 0;
 450
 451         memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
 452         info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 453         info->mask.src_port_mask = input_mask->src_port_mask;
 454         info->mask.dst_port_mask = input_mask->dst_port_mask;
 455         info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
 456         info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
 457         IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
 458         IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
 459         info->mask.src_ipv6_mask = src_ipv6m;
 460         info->mask.dst_ipv6_mask = dst_ipv6m;
 461
 462         return IXGBE_SUCCESS;
 463 }
 464
 465 static int
 466 ixgbe_fdir_store_input_mask_x550(struct rte_eth_dev *dev,
 467                                  const struct rte_eth_fdir_masks *input_mask)
 468 {
 469         struct ixgbe_hw_fdir_info *info =
 470                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 471
 472         memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
 473         info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 474         info->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask;
 475         info->mask.tunnel_type_mask = input_mask->tunnel_type_mask;
 476         info->mask.tunnel_id_mask = input_mask->tunnel_id_mask;
 477
 478         return IXGBE_SUCCESS;
 479 }
 480
 481 static int
 482 ixgbe_fdir_store_input_mask(struct rte_eth_dev *dev,
 483                             const struct rte_eth_fdir_masks *input_mask)
 484 {
 485         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 486
 487         if (mode >= RTE_FDIR_MODE_SIGNATURE &&
 488             mode <= RTE_FDIR_MODE_PERFECT)
 489                 return ixgbe_fdir_store_input_mask_82599(dev, input_mask);
 490         else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 491                  mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
 492                 return ixgbe_fdir_store_input_mask_x550(dev, input_mask);
 493
 494         PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
 495         return -ENOTSUP;
 496 }
 497
 498 int
 499 ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev)
 500 {
 501         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 502
 503         if (mode >= RTE_FDIR_MODE_SIGNATURE &&
 504             mode <= RTE_FDIR_MODE_PERFECT)
 505                 return fdir_set_input_mask_82599(dev);
 506         else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 507                  mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
 508                 return fdir_set_input_mask_x550(dev);
 509
 510         PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
 511         return -ENOTSUP;
 512 }
 513
 514 int
 515 ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
 516                                 uint16_t offset)
 517 {
 518         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 519         uint32_t fdirctrl;
 520         int i;
 521
 522         fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
 523
 524         fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
 525         fdirctrl |= ((offset >> 1) /* convert to word offset */
 526                 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 527
 528         IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 529         IXGBE_WRITE_FLUSH(hw);
 530         for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 531                 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
 532                         IXGBE_FDIRCTRL_INIT_DONE)
 533                         break;
 534                 msec_delay(1);
 535         }
 536         return 0;
 537 }
 538
 539 static int
 540 fdir_set_input_mask(struct rte_eth_dev *dev,
 541                     const struct rte_eth_fdir_masks *input_mask)
 542 {
 543         int ret;
 544
 545         ret = ixgbe_fdir_store_input_mask(dev, input_mask);
 546         if (ret)
 547                 return ret;
 548
 549         return ixgbe_fdir_set_input_mask(dev);
 550 }
 551
 552 /*
 553  * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
 554  * arguments are valid
 555  */
 556 static int
 557 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
 558                 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl)
 559 {
 560         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 561         struct ixgbe_hw_fdir_info *info =
 562                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 563         const struct rte_eth_flex_payload_cfg *flex_cfg;
 564         const struct rte_eth_fdir_flex_mask *flex_mask;
 565         uint32_t fdirm;
 566         uint16_t flexbytes = 0;
 567         uint16_t i;
 568
 569         fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
 570
 571         if (conf == NULL) {
 572                 PMD_DRV_LOG(ERR, "NULL pointer.");
 573                 return -EINVAL;
 574         }
 575
 576         for (i = 0; i < conf->nb_payloads; i++) {
 577                 flex_cfg = &conf->flex_set[i];
 578                 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
 579                         PMD_DRV_LOG(ERR, "unsupported payload type.");
 580                         return -EINVAL;
 581                 }
 582                 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
 583                     (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
 584                     (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
 585                         *fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
 586                         *fdirctrl |=
 587                                 (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
 588                                         IXGBE_FDIRCTRL_FLEX_SHIFT;
 589                 } else {
 590                         PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
 591                         return -EINVAL;
 592                 }
 593         }
 594
 595         for (i = 0; i < conf->nb_flexmasks; i++) {
 596                 flex_mask = &conf->flex_mask[i];
 597                 if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
 598                         PMD_DRV_LOG(ERR, "flexmask should be set globally.");
 599                         return -EINVAL;
 600                 }
 601                 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
 602                                         ((flex_mask->mask[1]) & 0xFF));
 603                 if (flexbytes == UINT16_MAX)
 604                         fdirm &= ~IXGBE_FDIRM_FLEX;
 605                 else if (flexbytes != 0) {
 606                         /* IXGBE_FDIRM_FLEX is set by default when set mask */
 607                         PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
 608                         return -EINVAL;
 609                 }
 610         }
 611         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 612         info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
 613         info->flex_bytes_offset = (uint8_t)((*fdirctrl &
 614                                             IXGBE_FDIRCTRL_FLEX_MASK) >>
 615                                             IXGBE_FDIRCTRL_FLEX_SHIFT);
 616         return 0;
 617 }
 618
 619 int
 620 ixgbe_fdir_configure(struct rte_eth_dev *dev)
 621 {
 622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 623         int err;
 624         uint32_t fdirctrl, pbsize;
 625         int i;
 626         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 627
 628         PMD_INIT_FUNC_TRACE();
 629
 630         if (hw->mac.type != ixgbe_mac_82599EB &&
 631                 hw->mac.type != ixgbe_mac_X540 &&
 632                 hw->mac.type != ixgbe_mac_X550 &&
 633                 hw->mac.type != ixgbe_mac_X550EM_x &&
 634                 hw->mac.type != ixgbe_mac_X550EM_a)
 635                 return -ENOSYS;
 636
 637         /* x550 supports mac-vlan and tunnel mode but other NICs not */
 638         if (hw->mac.type != ixgbe_mac_X550 &&
 639             hw->mac.type != ixgbe_mac_X550EM_x &&
 640             hw->mac.type != ixgbe_mac_X550EM_a &&
 641             mode != RTE_FDIR_MODE_SIGNATURE &&
 642             mode != RTE_FDIR_MODE_PERFECT)
 643                 return -ENOSYS;
 644
 645         err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
 646         if (err)
 647                 return err;
 648
 649         /*
 650          * Before enabling Flow Director, the Rx Packet Buffer size
 651          * must be reduced.  The new value is the current size minus
 652          * flow director memory usage size.
 653          */
 654         pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
 655         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
 656             (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
 657
 658         /*
 659          * The defaults in the HW for RX PB 1-7 are not zero and so should be
 660          * initialized to zero for non DCB mode otherwise actual total RX PB
 661          * would be bigger than programmed and filter space would run into
 662          * the PB 0 region.
 663          */
 664         for (i = 1; i < 8; i++)
 665                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
 666
 667         err = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask);
 668         if (err < 0) {
 669                 PMD_INIT_LOG(ERR, " Error on setting FD mask");
 670                 return err;
 671         }
 672         err = ixgbe_set_fdir_flex_conf(dev,
 673                 &dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl);
 674         if (err < 0) {
 675                 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
 676                 return err;
 677         }
 678
 679         err = fdir_enable_82599(hw, fdirctrl);
 680         if (err < 0) {
 681                 PMD_INIT_LOG(ERR, " Error on enabling FD.");
 682                 return err;
 683         }
 684         return 0;
 685 }
 686
 687 /*
 688  * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
 689  * by the IXGBE driver code.
 690  */
 691 static int
 692 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
 693                 union ixgbe_atr_input *input, enum rte_fdir_mode mode)
 694 {
 695         input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
 696         input->formatted.flex_bytes = (uint16_t)(
 697                 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
 698                 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
 699
 700         switch (fdir_filter->input.flow_type) {
 701         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 702                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
 703                 break;
 704         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 705                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
 706                 break;
 707         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 708                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
 709                 break;
 710         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 711                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
 712                 break;
 713         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 714                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
 715                 break;
 716         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 717                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
 718                 break;
 719         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 720                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
 721                 break;
 722         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 723                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
 724                 break;
 725         default:
 726                 break;
 727         }
 728
 729         switch (fdir_filter->input.flow_type) {
 730         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 731         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 732                 input->formatted.src_port =
 733                         fdir_filter->input.flow.udp4_flow.src_port;
 734                 input->formatted.dst_port =
 735                         fdir_filter->input.flow.udp4_flow.dst_port;
 736                 /* fall-through */
 737         /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
 738         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 739         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 740                 input->formatted.src_ip[0] =
 741                         fdir_filter->input.flow.ip4_flow.src_ip;
 742                 input->formatted.dst_ip[0] =
 743                         fdir_filter->input.flow.ip4_flow.dst_ip;
 744                 break;
 745
 746         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 747         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 748                 input->formatted.src_port =
 749                         fdir_filter->input.flow.udp6_flow.src_port;
 750                 input->formatted.dst_port =
 751                         fdir_filter->input.flow.udp6_flow.dst_port;
 752                 /* fall-through */
 753         /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
 754         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 755         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 756                 rte_memcpy(input->formatted.src_ip,
 757                            fdir_filter->input.flow.ipv6_flow.src_ip,
 758                            sizeof(input->formatted.src_ip));
 759                 rte_memcpy(input->formatted.dst_ip,
 760                            fdir_filter->input.flow.ipv6_flow.dst_ip,
 761                            sizeof(input->formatted.dst_ip));
 762                 break;
 763         default:
 764                 break;
 765         }
 766
 767         if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
 768                 rte_memcpy(
 769                         input->formatted.inner_mac,
 770                         fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes,
 771                         sizeof(input->formatted.inner_mac));
 772         } else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
 773                 rte_memcpy(
 774                         input->formatted.inner_mac,
 775                         fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes,
 776                         sizeof(input->formatted.inner_mac));
 777                 if (fdir_filter->input.flow.tunnel_flow.tunnel_type ==
 778                                 RTE_FDIR_TUNNEL_TYPE_VXLAN)
 779                         input->formatted.tunnel_type =
 780                                         IXGBE_FDIR_VXLAN_TUNNEL_TYPE;
 781                 else if (fdir_filter->input.flow.tunnel_flow.tunnel_type ==
 782                                 RTE_FDIR_TUNNEL_TYPE_NVGRE)
 783                         input->formatted.tunnel_type =
 784                                         IXGBE_FDIR_NVGRE_TUNNEL_TYPE;
 785                 else
 786                         PMD_DRV_LOG(ERR, " invalid tunnel type arguments.");
 787
 788                 input->formatted.tni_vni =
 789                         fdir_filter->input.flow.tunnel_flow.tunnel_id >> 8;
 790         }
 791
 792         return 0;
 793 }
 794
 795 /*
 796  * The below function is taken from the FreeBSD IXGBE drivers release
 797  * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
 798  * before returning, as the signature hash can use 16bits.
 799  *
 800  * The newer driver has optimised functions for calculating bucket and
 801  * signature hashes. However they don't support IPv6 type packets for signature
 802  * filters so are not used here.
 803  *
 804  * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
 805  * set.
 806  *
 807  * Compute the hashes for SW ATR
 808  *  @stream: input bitstream to compute the hash on
 809  *  @key: 32-bit hash key
 810  **/
 811 static uint32_t
 812 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
 813                                  uint32_t key)
 814 {
 815         /*
 816          * The algorithm is as follows:
 817          *    Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
 818          *    where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
 819          *    and A[n] x B[n] is bitwise AND between same length strings
 820          *
 821          *    K[n] is 16 bits, defined as:
 822          *       for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
 823          *       for n modulo 32 < 15, K[n] =
 824          *             K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
 825          *
 826          *    S[n] is 16 bits, defined as:
 827          *       for n >= 15, S[n] = S[n:n - 15]
 828          *       for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
 829          *
 830          *    To simplify for programming, the algorithm is implemented
 831          *    in software this way:
 832          *
 833          *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
 834          *
 835          *    for (i = 0; i < 352; i+=32)
 836          *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
 837          *
 838          *    lo_hash_dword[15:0]  ^= Stream[15:0];
 839          *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
 840          *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
 841          *
 842          *    hi_hash_dword[31:0]  ^= Stream[351:320];
 843          *
 844          *    if (key[0])
 845          *        hash[15:0] ^= Stream[15:0];
 846          *
 847          *    for (i = 0; i < 16; i++) {
 848          *        if (key[i])
 849          *            hash[15:0] ^= lo_hash_dword[(i+15):i];
 850          *        if (key[i + 16])
 851          *            hash[15:0] ^= hi_hash_dword[(i+15):i];
 852          *    }
 853          *
 854          */
 855         __be32 common_hash_dword = 0;
 856         u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
 857         u32 hash_result = 0;
 858         u8 i;
 859
 860         /* record the flow_vm_vlan bits as they are a key part to the hash */
 861         flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
 862
 863         /* generate common hash dword */
 864         for (i = 1; i <= 13; i++)
 865                 common_hash_dword ^= atr_input->dword_stream[i];
 866
 867         hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
 868
 869         /* low dword is word swapped version of common */
 870         lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 871
 872         /* apply flow ID/VM pool/VLAN ID bits to hash words */
 873         hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 874
 875         /* Process bits 0 and 16 */
 876         if (key & 0x0001)
 877                 hash_result ^= lo_hash_dword;
 878         if (key & 0x00010000)
 879                 hash_result ^= hi_hash_dword;
 880
 881         /*
 882          * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
 883          * delay this because bit 0 of the stream should not be processed
 884          * so we do not add the vlan until after bit 0 was processed
 885          */
 886         lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 887
 888
 889         /* process the remaining 30 bits in the key 2 bits at a time */
 890         for (i = 15; i; i--) {
 891                 if (key & (0x0001 << i))
 892                         hash_result ^= lo_hash_dword >> i;
 893                 if (key & (0x00010000 << i))
 894                         hash_result ^= hi_hash_dword >> i;
 895         }
 896
 897         return hash_result;
 898 }
 899
 900 static uint32_t
 901 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 902                 enum rte_fdir_pballoc_type pballoc)
 903 {
 904         if (pballoc == RTE_FDIR_PBALLOC_256K)
 905                 return ixgbe_atr_compute_hash_82599(input,
 906                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 907                                 PERFECT_BUCKET_256KB_HASH_MASK;
 908         else if (pballoc == RTE_FDIR_PBALLOC_128K)
 909                 return ixgbe_atr_compute_hash_82599(input,
 910                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 911                                 PERFECT_BUCKET_128KB_HASH_MASK;
 912         else
 913                 return ixgbe_atr_compute_hash_82599(input,
 914                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 915                                 PERFECT_BUCKET_64KB_HASH_MASK;
 916 }
 917
 918 /**
 919  * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
 920  * @hw: pointer to hardware structure
 921  */
 922 static inline int
 923 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
 924 {
 925         int i;
 926
 927         for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
 928                 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
 929                 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
 930                         return 0;
 931                 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
 932         }
 933
 934         return -ETIMEDOUT;
 935 }
 936
 937 /*
 938  * Calculate the hash value needed for signature-match filters. In the FreeBSD
 939  * driver, this is done by the optimised function
 940  * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
 941  * doesn't support calculating a hash for an IPv6 filter.
 942  */
 943 static uint32_t
 944 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
 945                 enum rte_fdir_pballoc_type pballoc)
 946 {
 947         uint32_t bucket_hash, sig_hash;
 948
 949         if (pballoc == RTE_FDIR_PBALLOC_256K)
 950                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 951                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 952                                 SIG_BUCKET_256KB_HASH_MASK;
 953         else if (pballoc == RTE_FDIR_PBALLOC_128K)
 954                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 955                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 956                                 SIG_BUCKET_128KB_HASH_MASK;
 957         else
 958                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 959                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 960                                 SIG_BUCKET_64KB_HASH_MASK;
 961
 962         sig_hash = ixgbe_atr_compute_hash_82599(input,
 963                         IXGBE_ATR_SIGNATURE_HASH_KEY);
 964
 965         return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
 966 }
 967
 968 /*
 969  * This is based on ixgbe_fdir_write_perfect_filter_82599() in
 970  * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
 971  * added, and IPv6 support also added. The hash value is also pre-calculated
 972  * as the pballoc value is needed to do it.
 973  */
 974 static int
 975 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 976                         union ixgbe_atr_input *input, uint8_t queue,
 977                         uint32_t fdircmd, uint32_t fdirhash,
 978                         enum rte_fdir_mode mode)
 979 {
 980         uint32_t fdirport, fdirvlan;
 981         u32 addr_low, addr_high;
 982         u32 tunnel_type = 0;
 983         int err = 0;
 984         volatile uint32_t *reg;
 985
 986         if (mode == RTE_FDIR_MODE_PERFECT) {
 987                 /* record the IPv4 address (big-endian)
 988                  * can not use IXGBE_WRITE_REG.
 989                  */
 990                 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPSA);
 991                 *reg = input->formatted.src_ip[0];
 992                 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPDA);
 993                 *reg = input->formatted.dst_ip[0];
 994
 995                 /* record source and destination port (little-endian)*/
 996                 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
 997                 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
 998                 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
 999                 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1000         } else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
1001                    mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
1002                 /* for mac vlan and tunnel modes */
1003                 addr_low = ((u32)input->formatted.inner_mac[0] |
1004                             ((u32)input->formatted.inner_mac[1] << 8) |
1005                             ((u32)input->formatted.inner_mac[2] << 16) |
1006                             ((u32)input->formatted.inner_mac[3] << 24));
1007                 addr_high = ((u32)input->formatted.inner_mac[4] |
1008                              ((u32)input->formatted.inner_mac[5] << 8));
1009
1010                 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
1011                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1012                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high);
1013                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0);
1014                 } else {
1015                         /* tunnel mode */
1016                         if (input->formatted.tunnel_type)
1017                                 tunnel_type = 0x80000000;
1018                         tunnel_type |= addr_high;
1019                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1020                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type);
1021                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2),
1022                                         input->formatted.tni_vni);
1023                 }
1024                 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, 0);
1025                 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, 0);
1026                 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, 0);
1027         }
1028
1029         /* record vlan (little-endian) and flex_bytes(big-endian) */
1030         fdirvlan = input->formatted.flex_bytes;
1031         fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1032         fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1033         IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1034
1035         /* configure FDIRHASH register */
1036         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1037
1038         /*
1039          * flush all previous writes to make certain registers are
1040          * programmed prior to issuing the command
1041          */
1042         IXGBE_WRITE_FLUSH(hw);
1043
1044         /* configure FDIRCMD register */
1045         fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1046                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1047         fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1048         fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1049         fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1050
1051         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1052
1053         PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1054
1055         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1056         if (err < 0)
1057                 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1058
1059         return err;
1060 }
1061
1062 /**
1063  * This function is based on ixgbe_atr_add_signature_filter_82599() in
1064  * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
1065  * setting extra fields in the FDIRCMD register, and removes the code that was
1066  * verifying the flow_type field. According to the documentation, a flow type of
1067  * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
1068  * work ok...
1069  *
1070  *  Adds a signature hash filter
1071  *  @hw: pointer to hardware structure
1072  *  @input: unique input dword
1073  *  @queue: queue index to direct traffic to
1074  *  @fdircmd: any extra flags to set in fdircmd register
1075  *  @fdirhash: pre-calculated hash value for the filter
1076  **/
1077 static int
1078 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1079                 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
1080                 uint32_t fdirhash)
1081 {
1082         int err = 0;
1083
1084         PMD_INIT_FUNC_TRACE();
1085
1086         /* configure FDIRCMD register */
1087         fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1088                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1089         fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1090         fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1091
1092         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1093         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1094
1095         PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1096
1097         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1098         if (err < 0)
1099                 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1100
1101         return err;
1102 }
1103
1104 /*
1105  * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
1106  * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so
1107  * that it can be used for removing signature and perfect filters.
1108  */
1109 static int
1110 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
1111 {
1112         uint32_t fdircmd = 0;
1113         int err = 0;
1114
1115         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1116
1117         /* flush hash to HW */
1118         IXGBE_WRITE_FLUSH(hw);
1119
1120         /* Query if filter is present */
1121         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1122
1123         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1124         if (err < 0) {
1125                 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
1126                 return err;
1127         }
1128
1129         /* if filter exists in hardware then remove it */
1130         if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1131                 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1132                 IXGBE_WRITE_FLUSH(hw);
1133                 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1134                                 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1135         }
1136         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1137         if (err < 0)
1138                 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
1139         return err;
1140
1141 }
1142
1143 static inline struct ixgbe_fdir_filter *
1144 ixgbe_fdir_filter_lookup(struct ixgbe_hw_fdir_info *fdir_info,
1145                          union ixgbe_atr_input *key)
1146 {
1147         int ret;
1148
1149         ret = rte_hash_lookup(fdir_info->hash_handle, (const void *)key);
1150         if (ret < 0)
1151                 return NULL;
1152
1153         return fdir_info->hash_map[ret];
1154 }
1155
1156 static inline int
1157 ixgbe_insert_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1158                          struct ixgbe_fdir_filter *fdir_filter)
1159 {
1160         int ret;
1161
1162         ret = rte_hash_add_key(fdir_info->hash_handle,
1163                                &fdir_filter->ixgbe_fdir);
1164
1165         if (ret < 0) {
1166                 PMD_DRV_LOG(ERR,
1167                             "Failed to insert fdir filter to hash table %d!",
1168                             ret);
1169                 return ret;
1170         }
1171
1172         fdir_info->hash_map[ret] = fdir_filter;
1173
1174         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, fdir_filter, entries);
1175
1176         return 0;
1177 }
1178
1179 static inline int
1180 ixgbe_remove_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1181                          union ixgbe_atr_input *key)
1182 {
1183         int ret;
1184         struct ixgbe_fdir_filter *fdir_filter;
1185
1186         ret = rte_hash_del_key(fdir_info->hash_handle, key);
1187
1188         if (ret < 0) {
1189                 PMD_DRV_LOG(ERR, "No such fdir filter to delete %d!", ret);
1190                 return ret;
1191         }
1192
1193         fdir_filter = fdir_info->hash_map[ret];
1194         fdir_info->hash_map[ret] = NULL;
1195
1196         TAILQ_REMOVE(&fdir_info->fdir_list, fdir_filter, entries);
1197         rte_free(fdir_filter);
1198
1199         return 0;
1200 }
1201
1202 static int
1203 ixgbe_interpret_fdir_filter(struct rte_eth_dev *dev,
1204                             const struct rte_eth_fdir_filter *fdir_filter,
1205                             struct ixgbe_fdir_rule *rule)
1206 {
1207         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1208         int err;
1209
1210         memset(rule, 0, sizeof(struct ixgbe_fdir_rule));
1211
1212         err = ixgbe_fdir_filter_to_atr_input(fdir_filter,
1213                                              &rule->ixgbe_fdir,
1214                                              fdir_mode);
1215         if (err)
1216                 return err;
1217
1218         rule->mode = fdir_mode;
1219         if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT)
1220                 rule->fdirflags = IXGBE_FDIRCMD_DROP;
1221         rule->queue = fdir_filter->action.rx_queue;
1222         rule->soft_id = fdir_filter->soft_id;
1223
1224         return 0;
1225 }
1226
1227 int
1228 ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
1229                           struct ixgbe_fdir_rule *rule,
1230                           bool del,
1231                           bool update)
1232 {
1233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234         uint32_t fdircmd_flags;
1235         uint32_t fdirhash;
1236         uint8_t queue;
1237         bool is_perfect = FALSE;
1238         int err;
1239         struct ixgbe_hw_fdir_info *info =
1240                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1241         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1242         struct ixgbe_fdir_filter *node;
1243         bool add_node = FALSE;
1244
1245         if (fdir_mode == RTE_FDIR_MODE_NONE ||
1246             fdir_mode != rule->mode)
1247                 return -ENOTSUP;
1248
1249         /*
1250          * Sanity check for x550.
1251          * When adding a new filter with flow type set to IPv4,
1252          * the flow director mask should be configed before,
1253          * and the L4 protocol and ports are masked.
1254          */
1255         if ((!del) &&
1256             (hw->mac.type == ixgbe_mac_X550 ||
1257              hw->mac.type == ixgbe_mac_X550EM_x ||
1258              hw->mac.type == ixgbe_mac_X550EM_a) &&
1259             (rule->ixgbe_fdir.formatted.flow_type ==
1260              IXGBE_ATR_FLOW_TYPE_IPV4 ||
1261              rule->ixgbe_fdir.formatted.flow_type ==
1262              IXGBE_ATR_FLOW_TYPE_IPV6) &&
1263             (info->mask.src_port_mask != 0 ||
1264              info->mask.dst_port_mask != 0) &&
1265             (rule->mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
1266              rule->mode != RTE_FDIR_MODE_PERFECT_TUNNEL)) {
1267                 PMD_DRV_LOG(ERR, "By this device,"
1268                             " IPv4 is not supported without"
1269                             " L4 protocol and ports masked!");
1270                 return -ENOTSUP;
1271         }
1272
1273         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1274             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1275                 is_perfect = TRUE;
1276
1277         if (is_perfect) {
1278                 if (rule->ixgbe_fdir.formatted.flow_type &
1279                     IXGBE_ATR_L4TYPE_IPV6_MASK) {
1280                         PMD_DRV_LOG(ERR, "IPv6 is not supported in"
1281                                     " perfect mode!");
1282                         return -ENOTSUP;
1283                 }
1284                 fdirhash = atr_compute_perfect_hash_82599(&rule->ixgbe_fdir,
1285                                                           dev->data->dev_conf.fdir_conf.pballoc);
1286                 fdirhash |= rule->soft_id <<
1287                         IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1288         } else
1289                 fdirhash = atr_compute_sig_hash_82599(&rule->ixgbe_fdir,
1290                                                       dev->data->dev_conf.fdir_conf.pballoc);
1291
1292         if (del) {
1293                 err = ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1294                 if (err < 0)
1295                         return err;
1296
1297                 err = fdir_erase_filter_82599(hw, fdirhash);
1298                 if (err < 0)
1299                         PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
1300                 else
1301                         PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
1302                 return err;
1303         }
1304         /* add or update an fdir filter*/
1305         fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
1306         if (rule->fdirflags & IXGBE_FDIRCMD_DROP) {
1307                 if (is_perfect) {
1308                         queue = dev->data->dev_conf.fdir_conf.drop_queue;
1309                         fdircmd_flags |= IXGBE_FDIRCMD_DROP;
1310                 } else {
1311                         PMD_DRV_LOG(ERR, "Drop option is not supported in"
1312                                     " signature mode.");
1313                         return -EINVAL;
1314                 }
1315         } else if (rule->queue < IXGBE_MAX_RX_QUEUE_NUM)
1316                 queue = (uint8_t)rule->queue;
1317         else
1318                 return -EINVAL;
1319
1320         node = ixgbe_fdir_filter_lookup(info, &rule->ixgbe_fdir);
1321         if (node) {
1322                 if (update) {
1323                         node->fdirflags = fdircmd_flags;
1324                         node->fdirhash = fdirhash;
1325                         node->queue = queue;
1326                 } else {
1327                         PMD_DRV_LOG(ERR, "Conflict with existing fdir filter!");
1328                         return -EINVAL;
1329                 }
1330         } else {
1331                 add_node = TRUE;
1332                 node = rte_zmalloc("ixgbe_fdir",
1333                                    sizeof(struct ixgbe_fdir_filter),
1334                                    0);
1335                 if (!node)
1336                         return -ENOMEM;
1337                 rte_memcpy(&node->ixgbe_fdir,
1338                                  &rule->ixgbe_fdir,
1339                                  sizeof(union ixgbe_atr_input));
1340                 node->fdirflags = fdircmd_flags;
1341                 node->fdirhash = fdirhash;
1342                 node->queue = queue;
1343
1344                 err = ixgbe_insert_fdir_filter(info, node);
1345                 if (err < 0) {
1346                         rte_free(node);
1347                         return err;
1348                 }
1349         }
1350
1351         if (is_perfect) {
1352                 err = fdir_write_perfect_filter_82599(hw, &rule->ixgbe_fdir,
1353                                                       queue, fdircmd_flags,
1354                                                       fdirhash, fdir_mode);
1355         } else {
1356                 err = fdir_add_signature_filter_82599(hw, &rule->ixgbe_fdir,
1357                                                       queue, fdircmd_flags,
1358                                                       fdirhash);
1359         }
1360         if (err < 0) {
1361                 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
1362
1363                 if (add_node)
1364                         (void)ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
1365         } else {
1366                 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
1367         }
1368
1369         return err;
1370 }
1371
1372 /* ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
1373  * @dev: pointer to the structure rte_eth_dev
1374  * @fdir_filter: fdir filter entry
1375  * @del: 1 - delete, 0 - add
1376  * @update: 1 - update
1377  */
1378 static int
1379 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
1380                           const struct rte_eth_fdir_filter *fdir_filter,
1381                           bool del,
1382                           bool update)
1383 {
1384         struct ixgbe_fdir_rule rule;
1385         int err;
1386
1387         err = ixgbe_interpret_fdir_filter(dev, fdir_filter, &rule);
1388
1389         if (err)
1390                 return err;
1391
1392         return ixgbe_fdir_filter_program(dev, &rule, del, update);
1393 }
1394
1395 static int
1396 ixgbe_fdir_flush(struct rte_eth_dev *dev)
1397 {
1398         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1399         struct ixgbe_hw_fdir_info *info =
1400                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1401         int ret;
1402
1403         ret = ixgbe_reinit_fdir_tables_82599(hw);
1404         if (ret < 0) {
1405                 PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
1406                 return ret;
1407         }
1408
1409         info->f_add = 0;
1410         info->f_remove = 0;
1411         info->add = 0;
1412         info->remove = 0;
1413
1414         return ret;
1415 }
1416
1417 #define FDIRENTRIES_NUM_SHIFT 10
1418 static void
1419 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
1420 {
1421         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422         struct ixgbe_hw_fdir_info *info =
1423                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1424         uint32_t fdirctrl, max_num, i;
1425         uint8_t offset;
1426
1427         fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1428         offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
1429                         IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
1430
1431         fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
1432         max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1433                         (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
1434         if (fdir_info->mode >= RTE_FDIR_MODE_PERFECT &&
1435             fdir_info->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1436                 fdir_info->guarant_spc = max_num;
1437         else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
1438                 fdir_info->guarant_spc = max_num * 4;
1439
1440         fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
1441         fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
1442         fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
1443         IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
1444                         fdir_info->mask.ipv6_mask.src_ip);
1445         IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
1446                         fdir_info->mask.ipv6_mask.dst_ip);
1447         fdir_info->mask.src_port_mask = info->mask.src_port_mask;
1448         fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
1449         fdir_info->mask.mac_addr_byte_mask = info->mask.mac_addr_byte_mask;
1450         fdir_info->mask.tunnel_id_mask = info->mask.tunnel_id_mask;
1451         fdir_info->mask.tunnel_type_mask = info->mask.tunnel_type_mask;
1452         fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
1453
1454         if (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN ||
1455             fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
1456                 fdir_info->flow_types_mask[0] = 0ULL;
1457         else
1458                 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1459         for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
1460                 fdir_info->flow_types_mask[i] = 0ULL;
1461
1462         fdir_info->flex_payload_unit = sizeof(uint16_t);
1463         fdir_info->max_flex_payload_segment_num = 1;
1464         fdir_info->flex_payload_limit = IXGBE_MAX_FLX_SOURCE_OFF;
1465         fdir_info->flex_conf.nb_payloads = 1;
1466         fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1467         fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1468         fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1469         fdir_info->flex_conf.nb_flexmasks = 1;
1470         fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;
1471         fdir_info->flex_conf.flex_mask[0].mask[0] =
1472                         (uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1473         fdir_info->flex_conf.flex_mask[0].mask[1] =
1474                         (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1475 }
1476
1477 static void
1478 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1479 {
1480         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481         struct ixgbe_hw_fdir_info *info =
1482                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1483         uint32_t reg, max_num;
1484         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1485
1486         /* Get the information from registers */
1487         reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1488         info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1489                                      IXGBE_FDIRFREE_COLL_SHIFT);
1490         info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1491                                 IXGBE_FDIRFREE_FREE_SHIFT);
1492
1493         reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1494         info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1495                                    IXGBE_FDIRLEN_MAXHASH_SHIFT);
1496         info->maxlen  = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1497                                   IXGBE_FDIRLEN_MAXLEN_SHIFT);
1498
1499         reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1500         info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1501                 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1502         info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1503                 IXGBE_FDIRUSTAT_ADD_SHIFT;
1504
1505         reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1506         info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1507                 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1508         info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1509                 IXGBE_FDIRFSTAT_FADD_SHIFT;
1510
1511         /*  Copy the new information in the fdir parameter */
1512         fdir_stats->collision = info->collision;
1513         fdir_stats->free = info->free;
1514         fdir_stats->maxhash = info->maxhash;
1515         fdir_stats->maxlen = info->maxlen;
1516         fdir_stats->remove = info->remove;
1517         fdir_stats->add = info->add;
1518         fdir_stats->f_remove = info->f_remove;
1519         fdir_stats->f_add = info->f_add;
1520
1521         reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1522         max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1523                          (reg & FDIRCTRL_PBALLOC_MASK)));
1524         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1525             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1526                 fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1527         else if (fdir_mode == RTE_FDIR_MODE_SIGNATURE)
1528                 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1529
1530 }
1531
1532 /*
1533  * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1534  * @dev: pointer to the structure rte_eth_dev
1535  * @filter_op:operation will be taken
1536  * @arg: a pointer to specific structure corresponding to the filter_op
1537  */
1538 int
1539 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1540                         enum rte_filter_op filter_op, void *arg)
1541 {
1542         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1543         int ret = 0;
1544
1545         if (hw->mac.type != ixgbe_mac_82599EB &&
1546                 hw->mac.type != ixgbe_mac_X540 &&
1547                 hw->mac.type != ixgbe_mac_X550 &&
1548                 hw->mac.type != ixgbe_mac_X550EM_x &&
1549                 hw->mac.type != ixgbe_mac_X550EM_a)
1550                 return -ENOTSUP;
1551
1552         if (filter_op == RTE_ETH_FILTER_NOP)
1553                 return 0;
1554
1555         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1556                 return -EINVAL;
1557
1558         switch (filter_op) {
1559         case RTE_ETH_FILTER_ADD:
1560                 ret = ixgbe_add_del_fdir_filter(dev,
1561                         (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1562                 break;
1563         case RTE_ETH_FILTER_UPDATE:
1564                 ret = ixgbe_add_del_fdir_filter(dev,
1565                         (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1566                 break;
1567         case RTE_ETH_FILTER_DELETE:
1568                 ret = ixgbe_add_del_fdir_filter(dev,
1569                         (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1570                 break;
1571         case RTE_ETH_FILTER_FLUSH:
1572                 ret = ixgbe_fdir_flush(dev);
1573                 break;
1574         case RTE_ETH_FILTER_INFO:
1575                 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1576                 break;
1577         case RTE_ETH_FILTER_STATS:
1578                 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1579                 break;
1580         default:
1581                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1582                 ret = -EINVAL;
1583                 break;
1584         }
1585         return ret;
1586 }
1587
1588 /* restore flow director filter */
1589 void
1590 ixgbe_fdir_filter_restore(struct rte_eth_dev *dev)
1591 {
1592         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1593         struct ixgbe_hw_fdir_info *fdir_info =
1594                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1595         struct ixgbe_fdir_filter *node;
1596         bool is_perfect = FALSE;
1597         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1598
1599         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1600             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1601                 is_perfect = TRUE;
1602
1603         if (is_perfect) {
1604                 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1605                         (void)fdir_write_perfect_filter_82599(hw,
1606                                                               &node->ixgbe_fdir,
1607                                                               node->queue,
1608                                                               node->fdirflags,
1609                                                               node->fdirhash,
1610                                                               fdir_mode);
1611                 }
1612         } else {
1613                 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1614                         (void)fdir_add_signature_filter_82599(hw,
1615                                                               &node->ixgbe_fdir,
1616                                                               node->queue,
1617                                                               node->fdirflags,
1618                                                               node->fdirhash);
1619                 }
1620         }
1621 }
1622
1623 /* remove all the flow director filters */
1624 int
1625 ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev)
1626 {
1627         struct ixgbe_hw_fdir_info *fdir_info =
1628                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1629         struct ixgbe_fdir_filter *fdir_filter;
1630         struct ixgbe_fdir_filter *filter_flag;
1631         int ret = 0;
1632
1633         /* flush flow director */
1634         rte_hash_reset(fdir_info->hash_handle);
1635         memset(fdir_info->hash_map, 0,
1636                sizeof(struct ixgbe_fdir_filter *) * IXGBE_MAX_FDIR_FILTER_NUM);
1637         filter_flag = TAILQ_FIRST(&fdir_info->fdir_list);
1638         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1639                 TAILQ_REMOVE(&fdir_info->fdir_list,
1640                              fdir_filter,
1641                              entries);
1642                 rte_free(fdir_filter);
1643         }
1644
1645         if (filter_flag != NULL)
1646                 ret = ixgbe_fdir_flush(dev);
1647
1648         return ret;
1649 }