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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "base/ixgbe_common.h"
53 #include "ixgbe_ethdev.h"
54 #include "rte_pmd_ixgbe.h"
56 #define IXGBE_MAX_VFTA (128)
57 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
58 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
59 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
61 static inline uint16_t
62 dev_num_vf(struct rte_eth_dev *eth_dev)
64 struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
66 return pci_dev->max_vfs;
70 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
72 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
73 struct ixgbe_vf_info *vfinfo =
74 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
77 for (vfn = 0; vfn < vf_num; vfn++) {
78 eth_random_addr(vf_mac_addr);
79 /* keep the random address as default */
80 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
88 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
90 struct ixgbe_interrupt *intr =
91 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
93 intr->mask |= IXGBE_EICR_MAILBOX;
98 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
100 struct ixgbe_vf_info **vfinfo =
101 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
102 struct ixgbe_mirror_info *mirror_info =
103 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
104 struct ixgbe_uta_info *uta_info =
105 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
106 struct ixgbe_hw *hw =
107 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
111 PMD_INIT_FUNC_TRACE();
113 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
114 vf_num = dev_num_vf(eth_dev);
118 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
120 rte_panic("Cannot allocate memory for private VF data\n");
122 memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
123 memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
124 hw->mac.mc_filter_type = 0;
126 if (vf_num >= ETH_32_POOLS) {
128 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
129 } else if (vf_num >= ETH_16_POOLS) {
131 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
134 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
137 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
138 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
139 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
141 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
143 /* init_mailbox_params */
144 hw->mbx.ops.init_params(hw);
146 /* set mb interrupt mask */
147 ixgbe_mb_intr_setup(eth_dev);
150 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
152 struct ixgbe_vf_info **vfinfo;
155 PMD_INIT_FUNC_TRACE();
157 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
159 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
160 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
161 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
162 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
164 vf_num = dev_num_vf(eth_dev);
173 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
175 struct ixgbe_hw *hw =
176 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
177 struct ixgbe_filter_info *filter_info =
178 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
181 struct ixgbe_ethertype_filter ethertype_filter;
183 if (!hw->mac.ops.set_ethertype_anti_spoofing) {
184 RTE_LOG(INFO, PMD, "ether type anti-spoofing is not"
189 i = ixgbe_ethertype_filter_lookup(filter_info,
190 IXGBE_ETHERTYPE_FLOW_CTRL);
192 RTE_LOG(ERR, PMD, "A ether type filter"
193 " entity for flow control already exists!\n");
197 ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL;
198 ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN |
199 IXGBE_ETQF_TX_ANTISPOOF |
200 IXGBE_ETHERTYPE_FLOW_CTRL;
201 ethertype_filter.etqs = 0;
202 ethertype_filter.conf = TRUE;
203 i = ixgbe_ethertype_filter_insert(filter_info,
206 RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter"
207 " entity for flow control.\n");
211 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
212 (IXGBE_ETQF_FILTER_EN |
213 IXGBE_ETQF_TX_ANTISPOOF |
214 IXGBE_ETHERTYPE_FLOW_CTRL));
216 vf_num = dev_num_vf(eth_dev);
217 for (i = 0; i < vf_num; i++)
218 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
221 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
223 uint32_t vtctl, fcrth;
224 uint32_t vfre_slot, vfre_offset;
226 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
227 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
228 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
229 uint32_t gpie, gcr_ext;
233 vf_num = dev_num_vf(eth_dev);
237 /* enable VMDq and set the default pool for PF */
238 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
239 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
240 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
241 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
242 << IXGBE_VT_CTL_POOL_SHIFT;
243 vtctl |= IXGBE_VT_CTL_REPLEN;
244 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
246 vfre_offset = vf_num & VFRE_MASK;
247 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
249 /* Enable pools reserved to PF only */
250 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
251 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
252 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
253 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
255 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
256 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
258 /* clear VMDq map to perment rar 0 */
259 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
261 /* clear VMDq map to scan rar 127 */
262 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
263 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
265 /* set VMDq map to default PF pool */
266 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
269 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
271 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
272 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
274 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
275 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
276 gpie |= IXGBE_GPIE_MSIX_MODE;
278 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
280 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
281 gpie |= IXGBE_GPIE_VTMODE_64;
284 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
285 gpie |= IXGBE_GPIE_VTMODE_32;
288 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
289 gpie |= IXGBE_GPIE_VTMODE_16;
293 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
294 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
297 * enable vlan filtering and allow all vlan tags through
299 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
300 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
301 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
303 /* VFTA - enable all vlan filters */
304 for (i = 0; i < IXGBE_MAX_VFTA; i++)
305 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
307 /* Enable MAC Anti-Spoofing */
308 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
310 /* set flow control threshold to max to avoid tx switch hang */
311 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
312 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
313 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
314 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
317 ixgbe_add_tx_flow_control_drop_filter(eth_dev);
323 set_rx_mode(struct rte_eth_dev *dev)
325 struct rte_eth_dev_data *dev_data = dev->data;
326 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
327 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
328 uint16_t vfn = dev_num_vf(dev);
330 /* Check for Promiscuous and All Multicast modes */
331 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
333 /* set all bits that we expect to always be set */
334 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
335 fctrl |= IXGBE_FCTRL_BAM;
337 /* clear the bits we are changing the status of */
338 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
340 if (dev_data->promiscuous) {
341 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
342 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
344 if (dev_data->all_multicast) {
345 fctrl |= IXGBE_FCTRL_MPE;
346 vmolr |= IXGBE_VMOLR_MPE;
348 vmolr |= IXGBE_VMOLR_ROMPE;
352 if (hw->mac.type != ixgbe_mac_82598EB) {
353 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
354 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
356 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
359 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
361 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
362 ixgbe_vlan_hw_strip_enable_all(dev);
364 ixgbe_vlan_hw_strip_disable_all(dev);
368 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
370 struct ixgbe_hw *hw =
371 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
372 struct ixgbe_vf_info *vfinfo =
373 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
374 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
375 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
377 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
378 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
379 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
381 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
383 /* reset multicast table array for vf */
384 vfinfo[vf].num_vf_mc_hashes = 0;
389 hw->mac.ops.clear_rar(hw, rar_entry);
393 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
395 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
397 uint32_t reg_offset, vf_shift;
398 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
399 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
401 vf_shift = vf & VFRE_MASK;
402 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
404 /* enable transmit and receive for vf */
405 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
406 reg |= (reg | (1 << vf_shift));
407 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
409 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
410 reg |= (reg | (1 << vf_shift));
411 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
413 /* Enable counting of spoofed packets in the SSVPC register */
414 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
415 reg |= (1 << vf_shift);
416 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
418 ixgbe_vf_reset_event(dev, vf);
422 ixgbe_enable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
424 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
427 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
429 RTE_LOG(INFO, PMD, "VF %u: enabling multicast promiscuous\n", vf);
431 vmolr |= IXGBE_VMOLR_MPE;
433 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
439 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
441 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
444 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
446 RTE_LOG(INFO, PMD, "VF %u: disabling multicast promiscuous\n", vf);
448 vmolr &= ~IXGBE_VMOLR_MPE;
450 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
456 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
458 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
459 struct ixgbe_vf_info *vfinfo =
460 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
461 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
462 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
463 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
465 ixgbe_vf_reset_msg(dev, vf);
467 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
469 /* Disable multicast promiscuous at reset */
470 ixgbe_disable_vf_mc_promisc(dev, vf);
472 /* reply to reset with ack and vf mac address */
473 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
474 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
476 * Piggyback the multicast filter type so VF can compute the
479 msgbuf[3] = hw->mac.mc_filter_type;
480 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
486 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
489 struct ixgbe_vf_info *vfinfo =
490 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
491 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
492 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
494 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
495 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
496 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
502 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
504 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
505 struct ixgbe_vf_info *vfinfo =
506 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
507 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
508 IXGBE_VT_MSGINFO_SHIFT;
509 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
512 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
513 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
514 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
518 /* Disable multicast promiscuous first */
519 ixgbe_disable_vf_mc_promisc(dev, vf);
521 /* only so many hash values supported */
522 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
524 /* store the mc entries */
525 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
526 for (i = 0; i < nb_entries; i++) {
527 vfinfo->vf_mc_hashes[i] = hash_list[i];
530 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
531 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
532 & IXGBE_MTA_INDEX_MASK;
533 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
534 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
535 reg_val |= (1 << mta_shift);
536 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
543 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
546 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
547 struct ixgbe_vf_info *vfinfo =
548 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
550 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
551 >> IXGBE_VT_MSGINFO_SHIFT;
552 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
555 vfinfo[vf].vlan_count++;
556 else if (vfinfo[vf].vlan_count)
557 vfinfo[vf].vlan_count--;
558 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
562 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
564 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
565 uint32_t new_mtu = msgbuf[1];
567 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
569 /* X540 and X550 support jumbo frames in IOV mode */
570 if (hw->mac.type != ixgbe_mac_X540 &&
571 hw->mac.type != ixgbe_mac_X550 &&
572 hw->mac.type != ixgbe_mac_X550EM_x &&
573 hw->mac.type != ixgbe_mac_X550EM_a)
576 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
579 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
580 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
581 if (max_frs < new_mtu) {
582 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
583 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
590 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
592 uint32_t api_version = msgbuf[1];
593 struct ixgbe_vf_info *vfinfo =
594 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
596 switch (api_version) {
597 case ixgbe_mbox_api_10:
598 case ixgbe_mbox_api_11:
599 case ixgbe_mbox_api_12:
600 vfinfo[vf].api_version = (uint8_t)api_version;
606 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
613 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
615 struct ixgbe_vf_info *vfinfo =
616 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
617 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
619 /* Verify if the PF supports the mbox APIs version or not */
620 switch (vfinfo[vf].api_version) {
621 case ixgbe_mbox_api_20:
622 case ixgbe_mbox_api_11:
623 case ixgbe_mbox_api_12:
629 /* Notify VF of Rx and Tx queue number */
630 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
631 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
633 /* Notify VF of default queue */
634 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
637 * FIX ME if it needs fill msgbuf[IXGBE_VF_TRANS_VLAN]
638 * for VLAN strip or VMDQ_DCB or VMDQ_DCB_RSS
645 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
647 struct ixgbe_vf_info *vfinfo =
648 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
649 bool enable = !!msgbuf[1]; /* msgbuf contains the flag to enable */
651 switch (vfinfo[vf].api_version) {
652 case ixgbe_mbox_api_12:
659 return ixgbe_enable_vf_mc_promisc(dev, vf);
661 return ixgbe_disable_vf_mc_promisc(dev, vf);
665 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
667 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
668 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
669 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
671 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
672 struct ixgbe_vf_info *vfinfo =
673 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
674 struct rte_pmd_ixgbe_mb_event_param cb_param;
676 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
678 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
682 /* do nothing with the message already been processed */
683 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
686 /* flush the ack before we write any messages back */
687 IXGBE_WRITE_FLUSH(hw);
690 * initialise structure to send to user application
691 * will return response from user in retval field
693 cb_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
695 cb_param.msg_type = msgbuf[0] & 0xFFFF;
696 cb_param.msg = (void *)msgbuf;
698 /* perform VF reset */
699 if (msgbuf[0] == IXGBE_VF_RESET) {
700 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
702 vfinfo[vf].clear_to_send = true;
704 /* notify application about VF reset */
705 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &cb_param);
710 * ask user application if we allowed to perform those functions
711 * if we get cb_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
712 * then business as usual,
713 * if 0, do nothing and send ACK to VF
714 * if cb_param.retval > 1, do nothing and send NAK to VF
716 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &cb_param);
718 retval = cb_param.retval;
720 /* check & process VF to PF mailbox message */
721 switch ((msgbuf[0] & 0xFFFF)) {
722 case IXGBE_VF_SET_MAC_ADDR:
723 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
724 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
726 case IXGBE_VF_SET_MULTICAST:
727 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
728 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
730 case IXGBE_VF_SET_LPE:
731 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
732 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
734 case IXGBE_VF_SET_VLAN:
735 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
736 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
738 case IXGBE_VF_API_NEGOTIATE:
739 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
741 case IXGBE_VF_GET_QUEUES:
742 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
743 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
745 case IXGBE_VF_UPDATE_XCAST_MODE:
746 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
747 retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
750 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
751 retval = IXGBE_ERR_MBX;
755 /* response the VF according to the message process result */
757 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
759 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
761 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
763 ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
769 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
771 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
772 struct ixgbe_hw *hw =
773 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
774 struct ixgbe_vf_info *vfinfo =
775 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
777 if (!vfinfo[vf].clear_to_send)
778 ixgbe_write_mbx(hw, &msg, 1, vf);
781 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
784 struct ixgbe_hw *hw =
785 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
787 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
788 /* check & process vf function level reset */
789 if (!ixgbe_check_for_rst(hw, vf))
790 ixgbe_vf_reset_event(eth_dev, vf);
792 /* check & process vf mailbox messages */
793 if (!ixgbe_check_for_msg(hw, vf))
794 ixgbe_rcv_msg_from_vf(eth_dev, vf);
796 /* check & process acks from vf */
797 if (!ixgbe_check_for_ack(hw, vf))
798 ixgbe_rcv_ack_from_vf(eth_dev, vf);