net/i40e: fix request queue in VF
[dpdk.git] / drivers / net / ixgbe / ixgbe_pf.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2016 Intel Corporation
3  */
4
5 #include <stdio.h>
6 #include <errno.h>
7 #include <stdint.h>
8 #include <stdlib.h>
9 #include <unistd.h>
10 #include <stdarg.h>
11 #include <inttypes.h>
12
13 #include <rte_interrupts.h>
14 #include <rte_log.h>
15 #include <rte_debug.h>
16 #include <rte_eal.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_memcpy.h>
20 #include <rte_malloc.h>
21 #include <rte_random.h>
22
23 #include "base/ixgbe_common.h"
24 #include "ixgbe_ethdev.h"
25 #include "rte_pmd_ixgbe.h"
26
27 #define IXGBE_MAX_VFTA     (128)
28 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
29 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
30 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
31
32 static inline uint16_t
33 dev_num_vf(struct rte_eth_dev *eth_dev)
34 {
35         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
36
37         return pci_dev->max_vfs;
38 }
39
40 static inline
41 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
42 {
43         unsigned char vf_mac_addr[RTE_ETHER_ADDR_LEN];
44         struct ixgbe_vf_info *vfinfo =
45                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
46         uint16_t vfn;
47
48         for (vfn = 0; vfn < vf_num; vfn++) {
49                 rte_eth_random_addr(vf_mac_addr);
50                 /* keep the random address as default */
51                 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
52                            RTE_ETHER_ADDR_LEN);
53         }
54
55         return 0;
56 }
57
58 static inline int
59 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
60 {
61         struct ixgbe_interrupt *intr =
62                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
63
64         intr->mask |= IXGBE_EICR_MAILBOX;
65
66         return 0;
67 }
68
69 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
70 {
71         struct ixgbe_vf_info **vfinfo =
72                 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
73         struct ixgbe_mirror_info *mirror_info =
74         IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
75         struct ixgbe_uta_info *uta_info =
76         IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
77         struct ixgbe_hw *hw =
78                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
79         uint16_t vf_num;
80         uint8_t nb_queue;
81
82         PMD_INIT_FUNC_TRACE();
83
84         RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
85         vf_num = dev_num_vf(eth_dev);
86         if (vf_num == 0)
87                 return;
88
89         *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
90         if (*vfinfo == NULL)
91                 rte_panic("Cannot allocate memory for private VF data\n");
92
93         rte_eth_switch_domain_alloc(&(*vfinfo)->switch_domain_id);
94
95         memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
96         memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
97         hw->mac.mc_filter_type = 0;
98
99         if (vf_num >= ETH_32_POOLS) {
100                 nb_queue = 2;
101                 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
102         } else if (vf_num >= ETH_16_POOLS) {
103                 nb_queue = 4;
104                 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
105         } else {
106                 nb_queue = 8;
107                 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
108         }
109
110         RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
111         RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
112         RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
113
114         ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
115
116         /* init_mailbox_params */
117         hw->mbx.ops.init_params(hw);
118
119         /* set mb interrupt mask */
120         ixgbe_mb_intr_setup(eth_dev);
121 }
122
123 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
124 {
125         struct ixgbe_vf_info **vfinfo;
126         uint16_t vf_num;
127         int ret;
128
129         PMD_INIT_FUNC_TRACE();
130
131         RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
132         RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
133         RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
134         RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
135
136         vf_num = dev_num_vf(eth_dev);
137         if (vf_num == 0)
138                 return;
139
140         vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
141         if (*vfinfo == NULL)
142                 return;
143
144         ret = rte_eth_switch_domain_free((*vfinfo)->switch_domain_id);
145         if (ret)
146                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
147
148         rte_free(*vfinfo);
149         *vfinfo = NULL;
150 }
151
152 static void
153 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
154 {
155         struct ixgbe_hw *hw =
156                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
157         struct ixgbe_filter_info *filter_info =
158                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
159         uint16_t vf_num;
160         int i;
161         struct ixgbe_ethertype_filter ethertype_filter;
162
163         if (!hw->mac.ops.set_ethertype_anti_spoofing) {
164                 RTE_LOG(INFO, PMD, "ether type anti-spoofing is not"
165                         " supported.\n");
166                 return;
167         }
168
169         i = ixgbe_ethertype_filter_lookup(filter_info,
170                                           IXGBE_ETHERTYPE_FLOW_CTRL);
171         if (i >= 0) {
172                 RTE_LOG(ERR, PMD, "A ether type filter"
173                         " entity for flow control already exists!\n");
174                 return;
175         }
176
177         ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL;
178         ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN |
179                                 IXGBE_ETQF_TX_ANTISPOOF |
180                                 IXGBE_ETHERTYPE_FLOW_CTRL;
181         ethertype_filter.etqs = 0;
182         ethertype_filter.conf = TRUE;
183         i = ixgbe_ethertype_filter_insert(filter_info,
184                                           &ethertype_filter);
185         if (i < 0) {
186                 RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter"
187                         " entity for flow control.\n");
188                 return;
189         }
190
191         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
192                         (IXGBE_ETQF_FILTER_EN |
193                         IXGBE_ETQF_TX_ANTISPOOF |
194                         IXGBE_ETHERTYPE_FLOW_CTRL));
195
196         vf_num = dev_num_vf(eth_dev);
197         for (i = 0; i < vf_num; i++)
198                 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
199 }
200
201 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
202 {
203         uint32_t vtctl, fcrth;
204         uint32_t vfre_slot, vfre_offset;
205         uint16_t vf_num;
206         const uint8_t VFRE_SHIFT = 5;  /* VFRE 32 bits per slot */
207         const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
208         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
209         uint32_t gpie, gcr_ext;
210         uint32_t vlanctrl;
211         int i;
212
213         vf_num = dev_num_vf(eth_dev);
214         if (vf_num == 0)
215                 return -1;
216
217         /* enable VMDq and set the default pool for PF */
218         vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
219         vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
220         vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
221         vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
222                 << IXGBE_VT_CTL_POOL_SHIFT;
223         vtctl |= IXGBE_VT_CTL_REPLEN;
224         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
225
226         vfre_offset = vf_num & VFRE_MASK;
227         vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
228
229         /* Enable pools reserved to PF only */
230         IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
231         IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
232         IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
233         IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
234
235         /* PFDMA Tx General Switch Control Enables VMDQ loopback */
236         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
237
238         /* clear VMDq map to perment rar 0 */
239         hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
240
241         /* clear VMDq map to scan rar 127 */
242         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
243         IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
244
245         /* set VMDq map to default PF pool */
246         hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
247
248         /*
249          * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
250          */
251         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
252         gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
253
254         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
255         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
256         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT;
257
258         switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
259         case ETH_64_POOLS:
260                 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
261                 gpie |= IXGBE_GPIE_VTMODE_64;
262                 break;
263         case ETH_32_POOLS:
264                 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
265                 gpie |= IXGBE_GPIE_VTMODE_32;
266                 break;
267         case ETH_16_POOLS:
268                 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
269                 gpie |= IXGBE_GPIE_VTMODE_16;
270                 break;
271         }
272
273         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
274         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
275
276         /*
277          * enable vlan filtering and allow all vlan tags through
278          */
279         vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
280         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
281         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
282
283         /* VFTA - enable all vlan filters */
284         for (i = 0; i < IXGBE_MAX_VFTA; i++)
285                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
286
287         /* Enable MAC Anti-Spoofing */
288         hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
289
290         /* set flow control threshold to max to avoid tx switch hang */
291         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
292                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
293                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
294                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
295         }
296
297         ixgbe_add_tx_flow_control_drop_filter(eth_dev);
298
299         return 0;
300 }
301
302 static void
303 set_rx_mode(struct rte_eth_dev *dev)
304 {
305         struct rte_eth_dev_data *dev_data = dev->data;
306         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
307         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
308         uint16_t vfn = dev_num_vf(dev);
309
310         /* Check for Promiscuous and All Multicast modes */
311         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
312
313         /* set all bits that we expect to always be set */
314         fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
315         fctrl |= IXGBE_FCTRL_BAM;
316
317         /* clear the bits we are changing the status of */
318         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
319
320         if (dev_data->promiscuous) {
321                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
322                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
323         } else {
324                 if (dev_data->all_multicast) {
325                         fctrl |= IXGBE_FCTRL_MPE;
326                         vmolr |= IXGBE_VMOLR_MPE;
327                 } else {
328                         vmolr |= IXGBE_VMOLR_ROMPE;
329                 }
330         }
331
332         if (hw->mac.type != ixgbe_mac_82598EB) {
333                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
334                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
335                            IXGBE_VMOLR_ROPE);
336                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
337         }
338
339         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
340
341         ixgbe_vlan_hw_strip_config(dev);
342 }
343
344 static inline void
345 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
346 {
347         struct ixgbe_hw *hw =
348                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
349         struct ixgbe_vf_info *vfinfo =
350                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
351         int rar_entry = hw->mac.num_rar_entries - (vf + 1);
352         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
353
354         vmolr |= (IXGBE_VMOLR_ROPE |
355                         IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
356         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
357
358         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
359
360         /* reset multicast table array for vf */
361         vfinfo[vf].num_vf_mc_hashes = 0;
362
363         /* reset rx mode */
364         set_rx_mode(dev);
365
366         hw->mac.ops.clear_rar(hw, rar_entry);
367 }
368
369 static inline void
370 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
371 {
372         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
373         uint32_t reg;
374         uint32_t reg_offset, vf_shift;
375         const uint8_t VFRE_SHIFT = 5;  /* VFRE 32 bits per slot */
376         const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
377         uint8_t  nb_q_per_pool;
378         int i;
379
380         vf_shift = vf & VFRE_MASK;
381         reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
382
383         /* enable transmit for vf */
384         reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
385         reg |= (reg | (1 << vf_shift));
386         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
387
388         /* enable all queue drop for IOV */
389         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
390         for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) {
391                 IXGBE_WRITE_FLUSH(hw);
392                 reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE;
393                 reg |= i << IXGBE_QDE_IDX_SHIFT;
394                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg);
395         }
396
397         /* enable receive for vf */
398         reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
399         reg |= (reg | (1 << vf_shift));
400         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
401
402         /* Enable counting of spoofed packets in the SSVPC register */
403         reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
404         reg |= (1 << vf_shift);
405         IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
406
407         ixgbe_vf_reset_event(dev, vf);
408 }
409
410 static int
411 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
412 {
413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
414         uint32_t vmolr;
415
416         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
417
418         RTE_LOG(INFO, PMD, "VF %u: disabling multicast promiscuous\n", vf);
419
420         vmolr &= ~IXGBE_VMOLR_MPE;
421
422         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
423
424         return 0;
425 }
426
427 static int
428 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
429 {
430         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
431         struct ixgbe_vf_info *vfinfo =
432                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
433         unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
434         int rar_entry = hw->mac.num_rar_entries - (vf + 1);
435         uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
436
437         ixgbe_vf_reset_msg(dev, vf);
438
439         hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
440
441         /* Disable multicast promiscuous at reset */
442         ixgbe_disable_vf_mc_promisc(dev, vf);
443
444         /* reply to reset with ack and vf mac address */
445         msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
446         rte_memcpy(new_mac, vf_mac, RTE_ETHER_ADDR_LEN);
447         /*
448          * Piggyback the multicast filter type so VF can compute the
449          * correct vectors
450          */
451         msgbuf[3] = hw->mac.mc_filter_type;
452         ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
453
454         return 0;
455 }
456
457 static int
458 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
459 {
460         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
461         struct ixgbe_vf_info *vfinfo =
462                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
463         int rar_entry = hw->mac.num_rar_entries - (vf + 1);
464         uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
465
466         if (rte_is_valid_assigned_ether_addr(
467                         (struct rte_ether_addr *)new_mac)) {
468                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
469                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
470         }
471         return -1;
472 }
473
474 static int
475 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
476 {
477         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
478         struct ixgbe_vf_info *vfinfo =
479                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
480         int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
481                 IXGBE_VT_MSGINFO_SHIFT;
482         uint16_t *hash_list = (uint16_t *)&msgbuf[1];
483         uint32_t mta_idx;
484         uint32_t mta_shift;
485         const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
486         const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
487         const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
488         uint32_t reg_val;
489         int i;
490         u32 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
491
492         /* Disable multicast promiscuous first */
493         ixgbe_disable_vf_mc_promisc(dev, vf);
494
495         /* only so many hash values supported */
496         nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
497
498         /* store the mc entries  */
499         vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
500         for (i = 0; i < nb_entries; i++) {
501                 vfinfo->vf_mc_hashes[i] = hash_list[i];
502         }
503
504         if (nb_entries == 0) {
505                 vmolr &= ~IXGBE_VMOLR_ROMPE;
506                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
507                 return 0;
508         }
509
510         for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
511                 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
512                                 & IXGBE_MTA_INDEX_MASK;
513                 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
514                 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
515                 reg_val |= (1 << mta_shift);
516                 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
517         }
518
519         vmolr |= IXGBE_VMOLR_ROMPE;
520         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
521
522         return 0;
523 }
524
525 static int
526 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
527 {
528         int add, vid;
529         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
530         struct ixgbe_vf_info *vfinfo =
531                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
532
533         add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
534                 >> IXGBE_VT_MSGINFO_SHIFT;
535         vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
536
537         if (add)
538                 vfinfo[vf].vlan_count++;
539         else if (vfinfo[vf].vlan_count)
540                 vfinfo[vf].vlan_count--;
541         return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
542 }
543
544 static int
545 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
546 {
547         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
548         uint32_t new_mtu = msgbuf[1];
549         uint32_t max_frs;
550         int max_frame = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
551
552         /* X540 and X550 support jumbo frames in IOV mode */
553         if (hw->mac.type != ixgbe_mac_X540 &&
554                 hw->mac.type != ixgbe_mac_X550 &&
555                 hw->mac.type != ixgbe_mac_X550EM_x &&
556                 hw->mac.type != ixgbe_mac_X550EM_a)
557                 return -1;
558
559         if (max_frame < RTE_ETHER_MIN_LEN ||
560                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
561                 return -1;
562
563         max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
564                    IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
565         if (max_frs < new_mtu) {
566                 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
567                 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
568         }
569
570         return 0;
571 }
572
573 static int
574 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
575 {
576         uint32_t api_version = msgbuf[1];
577         struct ixgbe_vf_info *vfinfo =
578                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
579
580         switch (api_version) {
581         case ixgbe_mbox_api_10:
582         case ixgbe_mbox_api_11:
583         case ixgbe_mbox_api_12:
584         case ixgbe_mbox_api_13:
585                 vfinfo[vf].api_version = (uint8_t)api_version;
586                 return 0;
587         default:
588                 break;
589         }
590
591         RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
592                 api_version, vf);
593
594         return -1;
595 }
596
597 static int
598 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
599 {
600         struct ixgbe_vf_info *vfinfo =
601                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
602         uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
603         struct rte_eth_conf *eth_conf;
604         struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf;
605         u8 num_tcs;
606         struct ixgbe_hw *hw;
607         u32 vmvir;
608 #define IXGBE_VMVIR_VLANA_MASK          0xC0000000
609 #define IXGBE_VMVIR_VLAN_VID_MASK       0x00000FFF
610 #define IXGBE_VMVIR_VLAN_UP_MASK        0x0000E000
611 #define VLAN_PRIO_SHIFT                 13
612         u32 vlana;
613         u32 vid;
614         u32 user_priority;
615
616         /* Verify if the PF supports the mbox APIs version or not */
617         switch (vfinfo[vf].api_version) {
618         case ixgbe_mbox_api_20:
619         case ixgbe_mbox_api_11:
620         case ixgbe_mbox_api_12:
621                 break;
622         default:
623                 return -1;
624         }
625
626         /* Notify VF of Rx and Tx queue number */
627         msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
628         msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
629
630         /* Notify VF of default queue */
631         msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
632
633         /* Notify VF of number of DCB traffic classes */
634         eth_conf = &dev->data->dev_conf;
635         switch (eth_conf->txmode.mq_mode) {
636         case ETH_MQ_TX_NONE:
637         case ETH_MQ_TX_DCB:
638                 RTE_LOG(ERR, PMD, "PF must work with virtualization for VF %u"
639                         ", but its tx mode = %d\n", vf,
640                         eth_conf->txmode.mq_mode);
641                 return -1;
642
643         case ETH_MQ_TX_VMDQ_DCB:
644                 vmdq_dcb_tx_conf = &eth_conf->tx_adv_conf.vmdq_dcb_tx_conf;
645                 switch (vmdq_dcb_tx_conf->nb_queue_pools) {
646                 case ETH_16_POOLS:
647                         num_tcs = ETH_8_TCS;
648                         break;
649                 case ETH_32_POOLS:
650                         num_tcs = ETH_4_TCS;
651                         break;
652                 default:
653                         return -1;
654                 }
655                 break;
656
657         /* ETH_MQ_TX_VMDQ_ONLY,  DCB not enabled */
658         case ETH_MQ_TX_VMDQ_ONLY:
659                 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
660                 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
661                 vlana = vmvir & IXGBE_VMVIR_VLANA_MASK;
662                 vid = vmvir & IXGBE_VMVIR_VLAN_VID_MASK;
663                 user_priority =
664                         (vmvir & IXGBE_VMVIR_VLAN_UP_MASK) >> VLAN_PRIO_SHIFT;
665                 if ((vlana == IXGBE_VMVIR_VLANA_DEFAULT) &&
666                         ((vid !=  0) || (user_priority != 0)))
667                         num_tcs = 1;
668                 else
669                         num_tcs = 0;
670                 break;
671
672         default:
673                 RTE_LOG(ERR, PMD, "PF work with invalid mode = %d\n",
674                         eth_conf->txmode.mq_mode);
675                 return -1;
676         }
677         msgbuf[IXGBE_VF_TRANS_VLAN] = num_tcs;
678
679         return 0;
680 }
681
682 static int
683 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
684 {
685         struct ixgbe_vf_info *vfinfo =
686                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
688         int xcast_mode = msgbuf[1];     /* msgbuf contains the flag to enable */
689         u32 vmolr, fctrl, disable, enable;
690
691         switch (vfinfo[vf].api_version) {
692         case ixgbe_mbox_api_12:
693                 /* promisc introduced in 1.3 version */
694                 if (xcast_mode == IXGBEVF_XCAST_MODE_PROMISC)
695                         return -EOPNOTSUPP;
696                 break;
697                 /* Fall threw */
698         case ixgbe_mbox_api_13:
699                 break;
700         default:
701                 return -1;
702         }
703
704         if (vfinfo[vf].xcast_mode == xcast_mode)
705                 goto out;
706
707         switch (xcast_mode) {
708         case IXGBEVF_XCAST_MODE_NONE:
709                 disable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE |
710                           IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
711                 enable = 0;
712                 break;
713         case IXGBEVF_XCAST_MODE_MULTI:
714                 disable = IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
715                 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE;
716                 break;
717         case IXGBEVF_XCAST_MODE_ALLMULTI:
718                 disable = IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
719                 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_MPE;
720                 break;
721         case IXGBEVF_XCAST_MODE_PROMISC:
722                 if (hw->mac.type <= ixgbe_mac_82599EB)
723                         return -1;
724
725                 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
726                 if (!(fctrl & IXGBE_FCTRL_UPE)) {
727                         /* VF promisc requires PF in promisc */
728                         RTE_LOG(ERR, PMD,
729                                "Enabling VF promisc requires PF in promisc\n");
730                         return -1;
731                 }
732
733                 disable = 0;
734                 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE |
735                          IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
736                 break;
737         default:
738                 return -1;
739         }
740
741         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
742         vmolr &= ~disable;
743         vmolr |= enable;
744         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
745         vfinfo[vf].xcast_mode = xcast_mode;
746
747 out:
748         msgbuf[1] = xcast_mode;
749
750         return 0;
751 }
752
753 static int
754 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
755 {
756         uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
757         uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
758         uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
759         int32_t retval;
760         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
761         struct ixgbe_vf_info *vfinfo =
762                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
763         struct rte_pmd_ixgbe_mb_event_param ret_param;
764
765         retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
766         if (retval) {
767                 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
768                 return retval;
769         }
770
771         /* do nothing with the message already been processed */
772         if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
773                 return retval;
774
775         /* flush the ack before we write any messages back */
776         IXGBE_WRITE_FLUSH(hw);
777
778         /**
779          * initialise structure to send to user application
780          * will return response from user in retval field
781          */
782         ret_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
783         ret_param.vfid = vf;
784         ret_param.msg_type = msgbuf[0] & 0xFFFF;
785         ret_param.msg = (void *)msgbuf;
786
787         /* perform VF reset */
788         if (msgbuf[0] == IXGBE_VF_RESET) {
789                 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
790
791                 vfinfo[vf].clear_to_send = true;
792
793                 /* notify application about VF reset */
794                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
795                                               &ret_param);
796                 return ret;
797         }
798
799         /**
800          * ask user application if we allowed to perform those functions
801          * if we get ret_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
802          * then business as usual,
803          * if 0, do nothing and send ACK to VF
804          * if ret_param.retval > 1, do nothing and send NAK to VF
805          */
806         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
807                                       &ret_param);
808
809         retval = ret_param.retval;
810
811         /* check & process VF to PF mailbox message */
812         switch ((msgbuf[0] & 0xFFFF)) {
813         case IXGBE_VF_SET_MAC_ADDR:
814                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
815                         retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
816                 break;
817         case IXGBE_VF_SET_MULTICAST:
818                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
819                         retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
820                 break;
821         case IXGBE_VF_SET_LPE:
822                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
823                         retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
824                 break;
825         case IXGBE_VF_SET_VLAN:
826                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
827                         retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
828                 break;
829         case IXGBE_VF_API_NEGOTIATE:
830                 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
831                 break;
832         case IXGBE_VF_GET_QUEUES:
833                 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
834                 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
835                 break;
836         case IXGBE_VF_UPDATE_XCAST_MODE:
837                 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
838                         retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
839                 break;
840         default:
841                 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
842                 retval = IXGBE_ERR_MBX;
843                 break;
844         }
845
846         /* response the VF according to the message process result */
847         if (retval)
848                 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
849         else
850                 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
851
852         msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
853
854         ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
855
856         return retval;
857 }
858
859 static inline void
860 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
861 {
862         uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
863         struct ixgbe_hw *hw =
864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
865         struct ixgbe_vf_info *vfinfo =
866                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
867
868         if (!vfinfo[vf].clear_to_send)
869                 ixgbe_write_mbx(hw, &msg, 1, vf);
870 }
871
872 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
873 {
874         uint16_t vf;
875         struct ixgbe_hw *hw =
876                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
877
878         for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
879                 /* check & process vf function level reset */
880                 if (!ixgbe_check_for_rst(hw, vf))
881                         ixgbe_vf_reset_event(eth_dev, vf);
882
883                 /* check & process vf mailbox messages */
884                 if (!ixgbe_check_for_msg(hw, vf))
885                         ixgbe_rcv_msg_from_vf(eth_dev, vf);
886
887                 /* check & process acks from vf */
888                 if (!ixgbe_check_for_ack(hw, vf))
889                         ixgbe_rcv_ack_from_vf(eth_dev, vf);
890         }
891 }