1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_interrupts.h>
15 #include <rte_debug.h>
17 #include <rte_ether.h>
18 #include <rte_ethdev_driver.h>
19 #include <rte_memcpy.h>
20 #include <rte_malloc.h>
21 #include <rte_random.h>
23 #include "base/ixgbe_common.h"
24 #include "ixgbe_ethdev.h"
25 #include "rte_pmd_ixgbe.h"
27 #define IXGBE_MAX_VFTA (128)
28 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
29 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
30 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
32 static inline uint16_t
33 dev_num_vf(struct rte_eth_dev *eth_dev)
35 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
37 return pci_dev->max_vfs;
41 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
43 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
44 struct ixgbe_vf_info *vfinfo =
45 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
48 for (vfn = 0; vfn < vf_num; vfn++) {
49 eth_random_addr(vf_mac_addr);
50 /* keep the random address as default */
51 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
59 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
61 struct ixgbe_interrupt *intr =
62 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
64 intr->mask |= IXGBE_EICR_MAILBOX;
69 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
71 struct ixgbe_vf_info **vfinfo =
72 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
73 struct ixgbe_mirror_info *mirror_info =
74 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
75 struct ixgbe_uta_info *uta_info =
76 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
78 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
82 PMD_INIT_FUNC_TRACE();
84 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
85 vf_num = dev_num_vf(eth_dev);
89 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
91 rte_panic("Cannot allocate memory for private VF data\n");
93 memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
94 memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
95 hw->mac.mc_filter_type = 0;
97 if (vf_num >= ETH_32_POOLS) {
99 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
100 } else if (vf_num >= ETH_16_POOLS) {
102 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
105 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
108 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
109 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
110 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
112 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
114 /* init_mailbox_params */
115 hw->mbx.ops.init_params(hw);
117 /* set mb interrupt mask */
118 ixgbe_mb_intr_setup(eth_dev);
121 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
123 struct ixgbe_vf_info **vfinfo;
126 PMD_INIT_FUNC_TRACE();
128 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
130 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
131 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
132 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
133 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
135 vf_num = dev_num_vf(eth_dev);
144 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
146 struct ixgbe_hw *hw =
147 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
148 struct ixgbe_filter_info *filter_info =
149 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
152 struct ixgbe_ethertype_filter ethertype_filter;
154 if (!hw->mac.ops.set_ethertype_anti_spoofing) {
155 RTE_LOG(INFO, PMD, "ether type anti-spoofing is not"
160 i = ixgbe_ethertype_filter_lookup(filter_info,
161 IXGBE_ETHERTYPE_FLOW_CTRL);
163 RTE_LOG(ERR, PMD, "A ether type filter"
164 " entity for flow control already exists!\n");
168 ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL;
169 ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN |
170 IXGBE_ETQF_TX_ANTISPOOF |
171 IXGBE_ETHERTYPE_FLOW_CTRL;
172 ethertype_filter.etqs = 0;
173 ethertype_filter.conf = TRUE;
174 i = ixgbe_ethertype_filter_insert(filter_info,
177 RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter"
178 " entity for flow control.\n");
182 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
183 (IXGBE_ETQF_FILTER_EN |
184 IXGBE_ETQF_TX_ANTISPOOF |
185 IXGBE_ETHERTYPE_FLOW_CTRL));
187 vf_num = dev_num_vf(eth_dev);
188 for (i = 0; i < vf_num; i++)
189 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
192 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
194 uint32_t vtctl, fcrth;
195 uint32_t vfre_slot, vfre_offset;
197 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
198 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
199 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
200 uint32_t gpie, gcr_ext;
204 vf_num = dev_num_vf(eth_dev);
208 /* enable VMDq and set the default pool for PF */
209 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
210 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
211 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
212 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
213 << IXGBE_VT_CTL_POOL_SHIFT;
214 vtctl |= IXGBE_VT_CTL_REPLEN;
215 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
217 vfre_offset = vf_num & VFRE_MASK;
218 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
220 /* Enable pools reserved to PF only */
221 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
222 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
223 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
224 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
226 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
227 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
229 /* clear VMDq map to perment rar 0 */
230 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
232 /* clear VMDq map to scan rar 127 */
233 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
234 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
236 /* set VMDq map to default PF pool */
237 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
240 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
242 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
243 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
245 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
246 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
247 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT;
249 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
251 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
252 gpie |= IXGBE_GPIE_VTMODE_64;
255 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
256 gpie |= IXGBE_GPIE_VTMODE_32;
259 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
260 gpie |= IXGBE_GPIE_VTMODE_16;
264 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
265 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
268 * enable vlan filtering and allow all vlan tags through
270 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
271 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
272 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
274 /* VFTA - enable all vlan filters */
275 for (i = 0; i < IXGBE_MAX_VFTA; i++)
276 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
278 /* Enable MAC Anti-Spoofing */
279 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
281 /* set flow control threshold to max to avoid tx switch hang */
282 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
283 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
284 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
285 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
288 ixgbe_add_tx_flow_control_drop_filter(eth_dev);
294 set_rx_mode(struct rte_eth_dev *dev)
296 struct rte_eth_dev_data *dev_data = dev->data;
297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
298 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
299 uint16_t vfn = dev_num_vf(dev);
301 /* Check for Promiscuous and All Multicast modes */
302 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
304 /* set all bits that we expect to always be set */
305 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
306 fctrl |= IXGBE_FCTRL_BAM;
308 /* clear the bits we are changing the status of */
309 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
311 if (dev_data->promiscuous) {
312 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
313 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
315 if (dev_data->all_multicast) {
316 fctrl |= IXGBE_FCTRL_MPE;
317 vmolr |= IXGBE_VMOLR_MPE;
319 vmolr |= IXGBE_VMOLR_ROMPE;
323 if (hw->mac.type != ixgbe_mac_82598EB) {
324 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
325 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
327 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
330 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
332 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
333 ixgbe_vlan_hw_strip_enable_all(dev);
335 ixgbe_vlan_hw_strip_disable_all(dev);
339 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
341 struct ixgbe_hw *hw =
342 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
343 struct ixgbe_vf_info *vfinfo =
344 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
345 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
346 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
348 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
349 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
350 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
352 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
354 /* reset multicast table array for vf */
355 vfinfo[vf].num_vf_mc_hashes = 0;
360 hw->mac.ops.clear_rar(hw, rar_entry);
364 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
366 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
368 uint32_t reg_offset, vf_shift;
369 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
370 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
371 uint8_t nb_q_per_pool;
374 vf_shift = vf & VFRE_MASK;
375 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
377 /* enable transmit for vf */
378 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
379 reg |= (reg | (1 << vf_shift));
380 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
382 /* enable all queue drop for IOV */
383 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
384 for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) {
385 IXGBE_WRITE_FLUSH(hw);
386 reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE;
387 reg |= i << IXGBE_QDE_IDX_SHIFT;
388 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg);
391 /* enable receive for vf */
392 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
393 reg |= (reg | (1 << vf_shift));
394 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
396 /* Enable counting of spoofed packets in the SSVPC register */
397 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
398 reg |= (1 << vf_shift);
399 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
401 ixgbe_vf_reset_event(dev, vf);
405 ixgbe_enable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
407 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
410 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
412 RTE_LOG(INFO, PMD, "VF %u: enabling multicast promiscuous\n", vf);
414 vmolr |= IXGBE_VMOLR_MPE;
416 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
422 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
424 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
427 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
429 RTE_LOG(INFO, PMD, "VF %u: disabling multicast promiscuous\n", vf);
431 vmolr &= ~IXGBE_VMOLR_MPE;
433 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
439 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
441 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
442 struct ixgbe_vf_info *vfinfo =
443 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
444 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
445 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
446 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
448 ixgbe_vf_reset_msg(dev, vf);
450 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
452 /* Disable multicast promiscuous at reset */
453 ixgbe_disable_vf_mc_promisc(dev, vf);
455 /* reply to reset with ack and vf mac address */
456 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
457 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
459 * Piggyback the multicast filter type so VF can compute the
462 msgbuf[3] = hw->mac.mc_filter_type;
463 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
469 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
472 struct ixgbe_vf_info *vfinfo =
473 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
474 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
475 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
477 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
478 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
479 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
485 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
487 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
488 struct ixgbe_vf_info *vfinfo =
489 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
490 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
491 IXGBE_VT_MSGINFO_SHIFT;
492 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
495 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
496 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
497 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
501 /* Disable multicast promiscuous first */
502 ixgbe_disable_vf_mc_promisc(dev, vf);
504 /* only so many hash values supported */
505 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
507 /* store the mc entries */
508 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
509 for (i = 0; i < nb_entries; i++) {
510 vfinfo->vf_mc_hashes[i] = hash_list[i];
513 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
514 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
515 & IXGBE_MTA_INDEX_MASK;
516 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
517 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
518 reg_val |= (1 << mta_shift);
519 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
526 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
529 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
530 struct ixgbe_vf_info *vfinfo =
531 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
533 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
534 >> IXGBE_VT_MSGINFO_SHIFT;
535 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
538 vfinfo[vf].vlan_count++;
539 else if (vfinfo[vf].vlan_count)
540 vfinfo[vf].vlan_count--;
541 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
545 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
547 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
548 uint32_t new_mtu = msgbuf[1];
550 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
552 /* X540 and X550 support jumbo frames in IOV mode */
553 if (hw->mac.type != ixgbe_mac_X540 &&
554 hw->mac.type != ixgbe_mac_X550 &&
555 hw->mac.type != ixgbe_mac_X550EM_x &&
556 hw->mac.type != ixgbe_mac_X550EM_a)
559 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
562 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
563 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
564 if (max_frs < new_mtu) {
565 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
566 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
573 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
575 uint32_t api_version = msgbuf[1];
576 struct ixgbe_vf_info *vfinfo =
577 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
579 switch (api_version) {
580 case ixgbe_mbox_api_10:
581 case ixgbe_mbox_api_11:
582 case ixgbe_mbox_api_12:
583 vfinfo[vf].api_version = (uint8_t)api_version;
589 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
596 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
598 struct ixgbe_vf_info *vfinfo =
599 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
600 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
601 struct rte_eth_conf *eth_conf;
602 struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf;
606 #define IXGBE_VMVIR_VLANA_MASK 0xC0000000
607 #define IXGBE_VMVIR_VLAN_VID_MASK 0x00000FFF
608 #define IXGBE_VMVIR_VLAN_UP_MASK 0x0000E000
609 #define VLAN_PRIO_SHIFT 13
614 /* Verify if the PF supports the mbox APIs version or not */
615 switch (vfinfo[vf].api_version) {
616 case ixgbe_mbox_api_20:
617 case ixgbe_mbox_api_11:
618 case ixgbe_mbox_api_12:
624 /* Notify VF of Rx and Tx queue number */
625 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
626 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
628 /* Notify VF of default queue */
629 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
631 /* Notify VF of number of DCB traffic classes */
632 eth_conf = &dev->data->dev_conf;
633 switch (eth_conf->txmode.mq_mode) {
636 RTE_LOG(ERR, PMD, "PF must work with virtualization for VF %u"
637 ", but its tx mode = %d\n", vf,
638 eth_conf->txmode.mq_mode);
641 case ETH_MQ_TX_VMDQ_DCB:
642 vmdq_dcb_tx_conf = ð_conf->tx_adv_conf.vmdq_dcb_tx_conf;
643 switch (vmdq_dcb_tx_conf->nb_queue_pools) {
655 /* ETH_MQ_TX_VMDQ_ONLY, DCB not enabled */
656 case ETH_MQ_TX_VMDQ_ONLY:
657 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
658 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
659 vlana = vmvir & IXGBE_VMVIR_VLANA_MASK;
660 vid = vmvir & IXGBE_VMVIR_VLAN_VID_MASK;
662 (vmvir & IXGBE_VMVIR_VLAN_UP_MASK) >> VLAN_PRIO_SHIFT;
663 if ((vlana == IXGBE_VMVIR_VLANA_DEFAULT) &&
664 ((vid != 0) || (user_priority != 0)))
671 RTE_LOG(ERR, PMD, "PF work with invalid mode = %d\n",
672 eth_conf->txmode.mq_mode);
675 msgbuf[IXGBE_VF_TRANS_VLAN] = num_tcs;
681 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
683 struct ixgbe_vf_info *vfinfo =
684 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
685 bool enable = !!msgbuf[1]; /* msgbuf contains the flag to enable */
687 switch (vfinfo[vf].api_version) {
688 case ixgbe_mbox_api_12:
695 return ixgbe_enable_vf_mc_promisc(dev, vf);
697 return ixgbe_disable_vf_mc_promisc(dev, vf);
701 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
703 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
704 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
705 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
707 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
708 struct ixgbe_vf_info *vfinfo =
709 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
710 struct rte_pmd_ixgbe_mb_event_param ret_param;
712 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
714 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
718 /* do nothing with the message already been processed */
719 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
722 /* flush the ack before we write any messages back */
723 IXGBE_WRITE_FLUSH(hw);
726 * initialise structure to send to user application
727 * will return response from user in retval field
729 ret_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
731 ret_param.msg_type = msgbuf[0] & 0xFFFF;
732 ret_param.msg = (void *)msgbuf;
734 /* perform VF reset */
735 if (msgbuf[0] == IXGBE_VF_RESET) {
736 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
738 vfinfo[vf].clear_to_send = true;
740 /* notify application about VF reset */
741 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
747 * ask user application if we allowed to perform those functions
748 * if we get ret_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
749 * then business as usual,
750 * if 0, do nothing and send ACK to VF
751 * if ret_param.retval > 1, do nothing and send NAK to VF
753 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
756 retval = ret_param.retval;
758 /* check & process VF to PF mailbox message */
759 switch ((msgbuf[0] & 0xFFFF)) {
760 case IXGBE_VF_SET_MAC_ADDR:
761 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
762 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
764 case IXGBE_VF_SET_MULTICAST:
765 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
766 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
768 case IXGBE_VF_SET_LPE:
769 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
770 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
772 case IXGBE_VF_SET_VLAN:
773 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
774 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
776 case IXGBE_VF_API_NEGOTIATE:
777 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
779 case IXGBE_VF_GET_QUEUES:
780 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
781 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
783 case IXGBE_VF_UPDATE_XCAST_MODE:
784 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
785 retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
788 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
789 retval = IXGBE_ERR_MBX;
793 /* response the VF according to the message process result */
795 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
797 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
799 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
801 ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
807 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
809 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
810 struct ixgbe_hw *hw =
811 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
812 struct ixgbe_vf_info *vfinfo =
813 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
815 if (!vfinfo[vf].clear_to_send)
816 ixgbe_write_mbx(hw, &msg, 1, vf);
819 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
822 struct ixgbe_hw *hw =
823 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
825 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
826 /* check & process vf function level reset */
827 if (!ixgbe_check_for_rst(hw, vf))
828 ixgbe_vf_reset_event(eth_dev, vf);
830 /* check & process vf mailbox messages */
831 if (!ixgbe_check_for_msg(hw, vf))
832 ixgbe_rcv_msg_from_vf(eth_dev, vf);
834 /* check & process acks from vf */
835 if (!ixgbe_check_for_ack(hw, vf))
836 ixgbe_rcv_ack_from_vf(eth_dev, vf);