1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
13 #include <rte_interrupts.h>
15 #include <rte_debug.h>
17 #include <rte_ether.h>
18 #include <ethdev_driver.h>
19 #include <rte_memcpy.h>
20 #include <rte_malloc.h>
21 #include <rte_random.h>
23 #include "base/ixgbe_common.h"
24 #include "ixgbe_ethdev.h"
25 #include "rte_pmd_ixgbe.h"
27 #define IXGBE_MAX_VFTA (128)
28 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
29 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
30 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
32 static inline uint16_t
33 dev_num_vf(struct rte_eth_dev *eth_dev)
35 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
37 return pci_dev->max_vfs;
41 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
43 unsigned char vf_mac_addr[RTE_ETHER_ADDR_LEN];
44 struct ixgbe_vf_info *vfinfo =
45 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
48 for (vfn = 0; vfn < vf_num; vfn++) {
49 rte_eth_random_addr(vf_mac_addr);
50 /* keep the random address as default */
51 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
59 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
61 struct ixgbe_interrupt *intr =
62 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
64 intr->mask |= IXGBE_EICR_MAILBOX;
69 int ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
71 struct ixgbe_vf_info **vfinfo =
72 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
73 struct ixgbe_mirror_info *mirror_info =
74 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
75 struct ixgbe_uta_info *uta_info =
76 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
78 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
83 PMD_INIT_FUNC_TRACE();
85 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
86 vf_num = dev_num_vf(eth_dev);
90 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
91 if (*vfinfo == NULL) {
93 "Cannot allocate memory for private VF data");
97 ret = rte_eth_switch_domain_alloc(&(*vfinfo)->switch_domain_id);
100 "failed to allocate switch domain for device %d", ret);
106 memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
107 memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
108 hw->mac.mc_filter_type = 0;
110 if (vf_num >= ETH_32_POOLS) {
112 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
113 } else if (vf_num >= ETH_16_POOLS) {
115 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
118 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
121 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
122 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
123 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
125 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
127 /* init_mailbox_params */
128 hw->mbx.ops.init_params(hw);
130 /* set mb interrupt mask */
131 ixgbe_mb_intr_setup(eth_dev);
136 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
138 struct ixgbe_vf_info **vfinfo;
142 PMD_INIT_FUNC_TRACE();
144 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
145 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
146 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
147 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
149 vf_num = dev_num_vf(eth_dev);
153 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
157 ret = rte_eth_switch_domain_free((*vfinfo)->switch_domain_id);
159 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
166 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
168 struct ixgbe_hw *hw =
169 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
170 struct ixgbe_filter_info *filter_info =
171 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
174 struct ixgbe_ethertype_filter ethertype_filter;
176 if (!hw->mac.ops.set_ethertype_anti_spoofing) {
177 PMD_DRV_LOG(INFO, "ether type anti-spoofing is not supported.\n");
181 i = ixgbe_ethertype_filter_lookup(filter_info,
182 IXGBE_ETHERTYPE_FLOW_CTRL);
184 PMD_DRV_LOG(ERR, "A ether type filter entity for flow control already exists!\n");
188 ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL;
189 ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN |
190 IXGBE_ETQF_TX_ANTISPOOF |
191 IXGBE_ETHERTYPE_FLOW_CTRL;
192 ethertype_filter.etqs = 0;
193 ethertype_filter.conf = TRUE;
194 i = ixgbe_ethertype_filter_insert(filter_info,
197 PMD_DRV_LOG(ERR, "Cannot find an unused ether type filter entity for flow control.\n");
201 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
202 (IXGBE_ETQF_FILTER_EN |
203 IXGBE_ETQF_TX_ANTISPOOF |
204 IXGBE_ETHERTYPE_FLOW_CTRL));
206 vf_num = dev_num_vf(eth_dev);
207 for (i = 0; i < vf_num; i++)
208 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
211 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
213 uint32_t vtctl, fcrth;
214 uint32_t vfre_slot, vfre_offset;
216 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
217 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
218 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
219 uint32_t gpie, gcr_ext;
223 vf_num = dev_num_vf(eth_dev);
227 /* enable VMDq and set the default pool for PF */
228 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
229 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
230 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
231 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
232 << IXGBE_VT_CTL_POOL_SHIFT;
233 vtctl |= IXGBE_VT_CTL_REPLEN;
234 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
236 vfre_offset = vf_num & VFRE_MASK;
237 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
239 /* Enable pools reserved to PF only */
240 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
241 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
242 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
243 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
245 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
246 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
248 /* clear VMDq map to perment rar 0 */
249 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
251 /* clear VMDq map to scan rar 127 */
252 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
253 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
255 /* set VMDq map to default PF pool */
256 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
259 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
261 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
262 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
264 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
265 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
266 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT;
268 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
270 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
271 gpie |= IXGBE_GPIE_VTMODE_64;
274 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
275 gpie |= IXGBE_GPIE_VTMODE_32;
278 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
279 gpie |= IXGBE_GPIE_VTMODE_16;
283 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
284 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
287 * enable vlan filtering and allow all vlan tags through
289 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
290 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
291 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
293 /* VFTA - enable all vlan filters */
294 for (i = 0; i < IXGBE_MAX_VFTA; i++)
295 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
297 /* Enable MAC Anti-Spoofing */
298 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
300 /* set flow control threshold to max to avoid tx switch hang */
301 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
302 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
303 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
304 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
307 ixgbe_add_tx_flow_control_drop_filter(eth_dev);
313 set_rx_mode(struct rte_eth_dev *dev)
315 struct rte_eth_dev_data *dev_data = dev->data;
316 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
317 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
318 uint16_t vfn = dev_num_vf(dev);
320 /* Check for Promiscuous and All Multicast modes */
321 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
323 /* set all bits that we expect to always be set */
324 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
325 fctrl |= IXGBE_FCTRL_BAM;
327 /* clear the bits we are changing the status of */
328 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
330 if (dev_data->promiscuous) {
331 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
332 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
334 if (dev_data->all_multicast) {
335 fctrl |= IXGBE_FCTRL_MPE;
336 vmolr |= IXGBE_VMOLR_MPE;
338 vmolr |= IXGBE_VMOLR_ROMPE;
342 if (hw->mac.type != ixgbe_mac_82598EB) {
343 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
344 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
346 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
349 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
351 ixgbe_vlan_hw_strip_config(dev);
355 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
357 struct ixgbe_hw *hw =
358 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
359 struct ixgbe_vf_info *vfinfo =
360 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
361 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
362 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
364 vmolr |= (IXGBE_VMOLR_ROPE |
365 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
366 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
368 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
370 /* reset multicast table array for vf */
371 vfinfo[vf].num_vf_mc_hashes = 0;
376 hw->mac.ops.clear_rar(hw, rar_entry);
380 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
382 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
384 uint32_t reg_offset, vf_shift;
385 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
386 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
387 uint8_t nb_q_per_pool;
390 vf_shift = vf & VFRE_MASK;
391 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
393 /* enable transmit for vf */
394 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
395 reg |= (reg | (1 << vf_shift));
396 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
398 /* enable all queue drop for IOV */
399 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
400 for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) {
401 IXGBE_WRITE_FLUSH(hw);
402 reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE;
403 reg |= i << IXGBE_QDE_IDX_SHIFT;
404 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg);
407 /* enable receive for vf */
408 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
409 reg |= (reg | (1 << vf_shift));
410 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
412 /* Enable counting of spoofed packets in the SSVPC register */
413 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
414 reg |= (1 << vf_shift);
415 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
417 ixgbe_vf_reset_event(dev, vf);
421 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
423 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
426 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
428 PMD_DRV_LOG(INFO, "VF %u: disabling multicast promiscuous\n", vf);
430 vmolr &= ~IXGBE_VMOLR_MPE;
432 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
438 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
440 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
441 struct ixgbe_vf_info *vfinfo =
442 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
443 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
444 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
445 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
447 ixgbe_vf_reset_msg(dev, vf);
449 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
451 /* Disable multicast promiscuous at reset */
452 ixgbe_disable_vf_mc_promisc(dev, vf);
454 /* reply to reset with ack and vf mac address */
455 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
456 rte_memcpy(new_mac, vf_mac, RTE_ETHER_ADDR_LEN);
458 * Piggyback the multicast filter type so VF can compute the
461 msgbuf[3] = hw->mac.mc_filter_type;
462 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
468 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
470 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
471 struct ixgbe_vf_info *vfinfo =
472 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
473 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
474 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
476 if (rte_is_valid_assigned_ether_addr(
477 (struct rte_ether_addr *)new_mac)) {
478 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
479 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
485 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
487 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
488 struct ixgbe_vf_info *vfinfo =
489 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
490 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
491 IXGBE_VT_MSGINFO_SHIFT;
492 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
495 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
496 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
497 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
500 u32 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
502 /* Disable multicast promiscuous first */
503 ixgbe_disable_vf_mc_promisc(dev, vf);
505 /* only so many hash values supported */
506 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
508 /* store the mc entries */
509 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
510 for (i = 0; i < nb_entries; i++) {
511 vfinfo->vf_mc_hashes[i] = hash_list[i];
514 if (nb_entries == 0) {
515 vmolr &= ~IXGBE_VMOLR_ROMPE;
516 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
520 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
521 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
522 & IXGBE_MTA_INDEX_MASK;
523 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
524 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
525 reg_val |= (1 << mta_shift);
526 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
529 vmolr |= IXGBE_VMOLR_ROMPE;
530 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
536 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
539 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
540 struct ixgbe_vf_info *vfinfo =
541 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
543 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
544 >> IXGBE_VT_MSGINFO_SHIFT;
545 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
548 vfinfo[vf].vlan_count++;
549 else if (vfinfo[vf].vlan_count)
550 vfinfo[vf].vlan_count--;
551 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
555 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
557 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
558 uint32_t max_frame = msgbuf[1];
562 /* X540 and X550 support jumbo frames in IOV mode */
563 if (hw->mac.type != ixgbe_mac_X540 &&
564 hw->mac.type != ixgbe_mac_X550 &&
565 hw->mac.type != ixgbe_mac_X550EM_x &&
566 hw->mac.type != ixgbe_mac_X550EM_a) {
567 struct ixgbe_vf_info *vfinfo =
568 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
570 switch (vfinfo[vf].api_version) {
571 case ixgbe_mbox_api_11:
572 case ixgbe_mbox_api_12:
573 case ixgbe_mbox_api_13:
575 * Version 1.1&1.2&1.3 supports jumbo frames on VFs
576 * if PF has jumbo frames enabled which means legacy
579 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
585 * If the PF or VF are running w/ jumbo frames enabled,
586 * we return -1 as we cannot support jumbo frames on
589 if (max_frame > IXGBE_ETH_MAX_LEN ||
590 dev->data->dev_conf.rxmode.max_rx_pkt_len >
597 if (max_frame < RTE_ETHER_MIN_LEN ||
598 max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
601 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
602 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
603 if (max_frs < max_frame) {
604 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
605 if (max_frame > IXGBE_ETH_MAX_LEN) {
606 dev->data->dev_conf.rxmode.offloads |=
607 DEV_RX_OFFLOAD_JUMBO_FRAME;
608 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
610 dev->data->dev_conf.rxmode.offloads &=
611 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
612 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
614 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
616 max_frs = max_frame << IXGBE_MHADD_MFS_SHIFT;
617 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
624 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
626 uint32_t api_version = msgbuf[1];
627 struct ixgbe_vf_info *vfinfo =
628 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
630 switch (api_version) {
631 case ixgbe_mbox_api_10:
632 case ixgbe_mbox_api_11:
633 case ixgbe_mbox_api_12:
634 case ixgbe_mbox_api_13:
635 vfinfo[vf].api_version = (uint8_t)api_version;
641 PMD_DRV_LOG(ERR, "Negotiate invalid api version %u from VF %d\n",
648 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
650 struct ixgbe_vf_info *vfinfo =
651 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
652 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
653 struct rte_eth_conf *eth_conf;
654 struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf;
658 #define IXGBE_VMVIR_VLANA_MASK 0xC0000000
659 #define IXGBE_VMVIR_VLAN_VID_MASK 0x00000FFF
660 #define IXGBE_VMVIR_VLAN_UP_MASK 0x0000E000
661 #define VLAN_PRIO_SHIFT 13
666 /* Verify if the PF supports the mbox APIs version or not */
667 switch (vfinfo[vf].api_version) {
668 case ixgbe_mbox_api_20:
669 case ixgbe_mbox_api_11:
670 case ixgbe_mbox_api_12:
671 case ixgbe_mbox_api_13:
677 /* Notify VF of Rx and Tx queue number */
678 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
679 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
681 /* Notify VF of default queue */
682 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
684 /* Notify VF of number of DCB traffic classes */
685 eth_conf = &dev->data->dev_conf;
686 switch (eth_conf->txmode.mq_mode) {
689 PMD_DRV_LOG(ERR, "PF must work with virtualization for VF %u"
690 ", but its tx mode = %d\n", vf,
691 eth_conf->txmode.mq_mode);
694 case ETH_MQ_TX_VMDQ_DCB:
695 vmdq_dcb_tx_conf = ð_conf->tx_adv_conf.vmdq_dcb_tx_conf;
696 switch (vmdq_dcb_tx_conf->nb_queue_pools) {
708 /* ETH_MQ_TX_VMDQ_ONLY, DCB not enabled */
709 case ETH_MQ_TX_VMDQ_ONLY:
710 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
711 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
712 vlana = vmvir & IXGBE_VMVIR_VLANA_MASK;
713 vid = vmvir & IXGBE_VMVIR_VLAN_VID_MASK;
715 (vmvir & IXGBE_VMVIR_VLAN_UP_MASK) >> VLAN_PRIO_SHIFT;
716 if ((vlana == IXGBE_VMVIR_VLANA_DEFAULT) &&
717 ((vid != 0) || (user_priority != 0)))
724 PMD_DRV_LOG(ERR, "PF work with invalid mode = %d\n",
725 eth_conf->txmode.mq_mode);
728 msgbuf[IXGBE_VF_TRANS_VLAN] = num_tcs;
734 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
736 struct ixgbe_vf_info *vfinfo =
737 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
738 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
739 int xcast_mode = msgbuf[1]; /* msgbuf contains the flag to enable */
740 u32 vmolr, fctrl, disable, enable;
742 switch (vfinfo[vf].api_version) {
743 case ixgbe_mbox_api_12:
744 /* promisc introduced in 1.3 version */
745 if (xcast_mode == IXGBEVF_XCAST_MODE_PROMISC)
749 case ixgbe_mbox_api_13:
755 if (vfinfo[vf].xcast_mode == xcast_mode)
758 switch (xcast_mode) {
759 case IXGBEVF_XCAST_MODE_NONE:
760 disable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE |
761 IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
764 case IXGBEVF_XCAST_MODE_MULTI:
765 disable = IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
766 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE;
768 case IXGBEVF_XCAST_MODE_ALLMULTI:
769 disable = IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
770 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_MPE;
772 case IXGBEVF_XCAST_MODE_PROMISC:
773 if (hw->mac.type <= ixgbe_mac_82599EB)
776 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
777 if (!(fctrl & IXGBE_FCTRL_UPE)) {
778 /* VF promisc requires PF in promisc */
780 "Enabling VF promisc requires PF in promisc\n");
785 enable = IXGBE_VMOLR_BAM | IXGBE_VMOLR_ROMPE |
786 IXGBE_VMOLR_MPE | IXGBE_VMOLR_UPE | IXGBE_VMOLR_VPE;
792 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
795 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
796 vfinfo[vf].xcast_mode = xcast_mode;
799 msgbuf[1] = xcast_mode;
805 ixgbe_set_vf_macvlan_msg(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
808 struct ixgbe_vf_info *vf_info =
809 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
810 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
811 int index = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
812 IXGBE_VT_MSGINFO_SHIFT;
815 if (!rte_is_valid_assigned_ether_addr(
816 (struct rte_ether_addr *)new_mac)) {
817 PMD_DRV_LOG(ERR, "set invalid mac vf:%d\n", vf);
821 vf_info[vf].mac_count++;
823 hw->mac.ops.set_rar(hw, vf_info[vf].mac_count,
824 new_mac, vf, IXGBE_RAH_AV);
826 if (vf_info[vf].mac_count) {
827 hw->mac.ops.clear_rar(hw, vf_info[vf].mac_count);
828 vf_info[vf].mac_count = 0;
835 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
837 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
838 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
839 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
841 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
842 struct ixgbe_vf_info *vfinfo =
843 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
844 struct rte_pmd_ixgbe_mb_event_param ret_param;
846 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
848 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
852 /* do nothing with the message already been processed */
853 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
856 /* flush the ack before we write any messages back */
857 IXGBE_WRITE_FLUSH(hw);
860 * initialise structure to send to user application
861 * will return response from user in retval field
863 ret_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
865 ret_param.msg_type = msgbuf[0] & 0xFFFF;
866 ret_param.msg = (void *)msgbuf;
868 /* perform VF reset */
869 if (msgbuf[0] == IXGBE_VF_RESET) {
870 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
872 vfinfo[vf].clear_to_send = true;
874 /* notify application about VF reset */
875 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX,
881 * ask user application if we allowed to perform those functions
882 * if we get ret_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
883 * then business as usual,
884 * if 0, do nothing and send ACK to VF
885 * if ret_param.retval > 1, do nothing and send NAK to VF
887 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &ret_param);
889 retval = ret_param.retval;
891 /* check & process VF to PF mailbox message */
892 switch ((msgbuf[0] & 0xFFFF)) {
893 case IXGBE_VF_SET_MAC_ADDR:
894 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
895 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
897 case IXGBE_VF_SET_MULTICAST:
898 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
899 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
901 case IXGBE_VF_SET_LPE:
902 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
903 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
905 case IXGBE_VF_SET_VLAN:
906 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
907 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
909 case IXGBE_VF_API_NEGOTIATE:
910 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
912 case IXGBE_VF_GET_QUEUES:
913 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
914 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
916 case IXGBE_VF_UPDATE_XCAST_MODE:
917 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
918 retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
920 case IXGBE_VF_SET_MACVLAN:
921 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
922 retval = ixgbe_set_vf_macvlan_msg(dev, vf, msgbuf);
925 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
926 retval = IXGBE_ERR_MBX;
930 /* response the VF according to the message process result */
932 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
934 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
936 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
938 ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
944 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
946 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
947 struct ixgbe_hw *hw =
948 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
949 struct ixgbe_vf_info *vfinfo =
950 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
952 if (!vfinfo[vf].clear_to_send)
953 ixgbe_write_mbx(hw, &msg, 1, vf);
956 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
959 struct ixgbe_hw *hw =
960 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
962 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
963 /* check & process vf function level reset */
964 if (!ixgbe_check_for_rst(hw, vf))
965 ixgbe_vf_reset_event(eth_dev, vf);
967 /* check & process vf mailbox messages */
968 if (!ixgbe_check_for_msg(hw, vf))
969 ixgbe_rcv_msg_from_vf(eth_dev, vf);
971 /* check & process acks from vf */
972 if (!ixgbe_check_for_ack(hw, vf))
973 ixgbe_rcv_ack_from_vf(eth_dev, vf);