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42 #include <rte_interrupts.h>
44 #include <rte_debug.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memcpy.h>
49 #include <rte_malloc.h>
50 #include <rte_random.h>
52 #include "base/ixgbe_common.h"
53 #include "ixgbe_ethdev.h"
55 #define IXGBE_MAX_VFTA (128)
56 #define IXGBE_VF_MSG_SIZE_DEFAULT 1
57 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
59 static inline uint16_t
60 dev_num_vf(struct rte_eth_dev *eth_dev)
62 return eth_dev->pci_dev->max_vfs;
66 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
68 unsigned char vf_mac_addr[ETHER_ADDR_LEN];
69 struct ixgbe_vf_info *vfinfo =
70 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
73 for (vfn = 0; vfn < vf_num; vfn++) {
74 eth_random_addr(vf_mac_addr);
75 /* keep the random address as default */
76 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
84 ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
86 struct ixgbe_interrupt *intr =
87 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
89 intr->mask |= IXGBE_EICR_MAILBOX;
94 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
96 struct ixgbe_vf_info **vfinfo =
97 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
98 struct ixgbe_mirror_info *mirror_info =
99 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
100 struct ixgbe_uta_info *uta_info =
101 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
102 struct ixgbe_hw *hw =
103 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
107 PMD_INIT_FUNC_TRACE();
109 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
110 if (0 == (vf_num = dev_num_vf(eth_dev)))
113 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
115 rte_panic("Cannot allocate memory for private VF data\n");
117 memset(mirror_info,0,sizeof(struct ixgbe_mirror_info));
118 memset(uta_info,0,sizeof(struct ixgbe_uta_info));
119 hw->mac.mc_filter_type = 0;
121 if (vf_num >= ETH_32_POOLS) {
123 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
124 } else if (vf_num >= ETH_16_POOLS) {
126 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
129 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
132 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
133 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
134 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
136 ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
138 /* init_mailbox_params */
139 hw->mbx.ops.init_params(hw);
141 /* set mb interrupt mask */
142 ixgbe_mb_intr_setup(eth_dev);
147 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
149 struct ixgbe_vf_info **vfinfo;
152 PMD_INIT_FUNC_TRACE();
154 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
156 RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
157 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
158 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
159 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
161 vf_num = dev_num_vf(eth_dev);
169 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
171 uint32_t vtctl, fcrth;
172 uint32_t vfre_slot, vfre_offset;
174 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
175 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
176 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
177 uint32_t gpie, gcr_ext;
181 if (0 == (vf_num = dev_num_vf(eth_dev)))
184 /* enable VMDq and set the default pool for PF */
185 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
186 vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
187 vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
188 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
189 << IXGBE_VT_CTL_POOL_SHIFT;
190 vtctl |= IXGBE_VT_CTL_REPLEN;
191 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
193 vfre_offset = vf_num & VFRE_MASK;
194 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
196 /* Enable pools reserved to PF only */
197 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0) << vfre_offset);
198 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
199 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0) << vfre_offset);
200 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
202 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
203 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
205 /* clear VMDq map to perment rar 0 */
206 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
208 /* clear VMDq map to scan rar 127 */
209 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
210 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
212 /* set VMDq map to default PF pool */
213 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
216 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
218 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
219 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
221 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
222 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
223 gpie |= IXGBE_GPIE_MSIX_MODE;
225 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
227 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
228 gpie |= IXGBE_GPIE_VTMODE_64;
231 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
232 gpie |= IXGBE_GPIE_VTMODE_32;
235 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
236 gpie |= IXGBE_GPIE_VTMODE_16;
240 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
241 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
244 * enable vlan filtering and allow all vlan tags through
246 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
247 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
248 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
250 /* VFTA - enable all vlan filters */
251 for (i = 0; i < IXGBE_MAX_VFTA; i++) {
252 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
255 /* Enable MAC Anti-Spoofing */
256 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
258 /* set flow control threshold to max to avoid tx switch hang */
259 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
260 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
261 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
262 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
269 set_rx_mode(struct rte_eth_dev *dev)
271 struct rte_eth_dev_data *dev_data =
272 (struct rte_eth_dev_data*)dev->data->dev_private;
273 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
274 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
275 uint16_t vfn = dev_num_vf(dev);
277 /* Check for Promiscuous and All Multicast modes */
278 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
280 /* set all bits that we expect to always be set */
281 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
282 fctrl |= IXGBE_FCTRL_BAM;
284 /* clear the bits we are changing the status of */
285 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
287 if (dev_data->promiscuous) {
288 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
289 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
291 if (dev_data->all_multicast) {
292 fctrl |= IXGBE_FCTRL_MPE;
293 vmolr |= IXGBE_VMOLR_MPE;
295 vmolr |= IXGBE_VMOLR_ROMPE;
299 if (hw->mac.type != ixgbe_mac_82598EB) {
300 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
301 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
303 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
306 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
308 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
309 ixgbe_vlan_hw_strip_enable_all(dev);
311 ixgbe_vlan_hw_strip_disable_all(dev);
315 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
317 struct ixgbe_hw *hw =
318 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
319 struct ixgbe_vf_info *vfinfo =
320 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
321 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
322 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
324 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
325 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
326 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
328 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
330 /* reset multicast table array for vf */
331 vfinfo[vf].num_vf_mc_hashes = 0;
336 hw->mac.ops.clear_rar(hw, rar_entry);
340 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
342 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
344 uint32_t reg_offset, vf_shift;
345 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */
346 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
348 vf_shift = vf & VFRE_MASK;
349 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
351 /* enable transmit and receive for vf */
352 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
353 reg |= (reg | (1 << vf_shift));
354 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
356 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
357 reg |= (reg | (1 << vf_shift));
358 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
360 /* Enable counting of spoofed packets in the SSVPC register */
361 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
362 reg |= (1 << vf_shift);
363 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
365 ixgbe_vf_reset_event(dev, vf);
369 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
371 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
372 struct ixgbe_vf_info *vfinfo =
373 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
374 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
375 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
376 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
378 ixgbe_vf_reset_msg(dev, vf);
380 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
382 /* reply to reset with ack and vf mac address */
383 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
384 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
386 * Piggyback the multicast filter type so VF can compute the
389 msgbuf[3] = hw->mac.mc_filter_type;
390 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
396 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
398 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
399 struct ixgbe_vf_info *vfinfo =
400 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
401 int rar_entry = hw->mac.num_rar_entries - (vf + 1);
402 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
404 if (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {
405 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
406 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
412 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
415 struct ixgbe_vf_info *vfinfo =
416 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
417 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
418 IXGBE_VT_MSGINFO_SHIFT;
419 uint16_t *hash_list = (uint16_t *)&msgbuf[1];
422 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
423 const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
424 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
428 /* only so many hash values supported */
429 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
431 /* store the mc entries */
432 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
433 for (i = 0; i < nb_entries; i++) {
434 vfinfo->vf_mc_hashes[i] = hash_list[i];
437 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
438 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
439 & IXGBE_MTA_INDEX_MASK;
440 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
441 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
442 reg_val |= (1 << mta_shift);
443 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
450 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
453 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
454 struct ixgbe_vf_info *vfinfo =
455 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
457 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
458 >> IXGBE_VT_MSGINFO_SHIFT;
459 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
462 vfinfo[vf].vlan_count++;
463 else if (vfinfo[vf].vlan_count)
464 vfinfo[vf].vlan_count--;
465 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add);
469 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
471 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
472 uint32_t new_mtu = msgbuf[1];
474 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
476 /* X540 and X550 support jumbo frames in IOV mode */
477 if (hw->mac.type != ixgbe_mac_X540 &&
478 hw->mac.type != ixgbe_mac_X550 &&
479 hw->mac.type != ixgbe_mac_X550EM_x)
482 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
485 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
486 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
487 if (max_frs < new_mtu) {
488 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
489 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
496 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
498 uint32_t api_version = msgbuf[1];
499 struct ixgbe_vf_info *vfinfo =
500 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
502 switch (api_version) {
503 case ixgbe_mbox_api_10:
504 case ixgbe_mbox_api_11:
505 vfinfo[vf].api_version = (uint8_t)api_version;
511 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
518 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
520 struct ixgbe_vf_info *vfinfo =
521 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
522 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
524 /* Verify if the PF supports the mbox APIs version or not */
525 switch (vfinfo[vf].api_version) {
526 case ixgbe_mbox_api_20:
527 case ixgbe_mbox_api_11:
533 /* Notify VF of Rx and Tx queue number */
534 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
535 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
537 /* Notify VF of default queue */
538 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
541 * FIX ME if it needs fill msgbuf[IXGBE_VF_TRANS_VLAN]
542 * for VLAN strip or VMDQ_DCB or VMDQ_DCB_RSS
549 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
551 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
552 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
553 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
555 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
556 struct ixgbe_vf_info *vfinfo =
557 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
559 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
561 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
565 /* do nothing with the message already been processed */
566 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
569 /* flush the ack before we write any messages back */
570 IXGBE_WRITE_FLUSH(hw);
572 /* perform VF reset */
573 if (msgbuf[0] == IXGBE_VF_RESET) {
574 int ret = ixgbe_vf_reset(dev, vf, msgbuf);
575 vfinfo[vf].clear_to_send = true;
579 /* check & process VF to PF mailbox message */
580 switch ((msgbuf[0] & 0xFFFF)) {
581 case IXGBE_VF_SET_MAC_ADDR:
582 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
584 case IXGBE_VF_SET_MULTICAST:
585 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
587 case IXGBE_VF_SET_LPE:
588 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
590 case IXGBE_VF_SET_VLAN:
591 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
593 case IXGBE_VF_API_NEGOTIATE:
594 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
596 case IXGBE_VF_GET_QUEUES:
597 retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
598 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
601 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
602 retval = IXGBE_ERR_MBX;
606 /* response the VF according to the message process result */
608 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
610 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
612 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
614 ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
620 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
622 uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
623 struct ixgbe_hw *hw =
624 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
625 struct ixgbe_vf_info *vfinfo =
626 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
628 if (!vfinfo[vf].clear_to_send)
629 ixgbe_write_mbx(hw, &msg, 1, vf);
632 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
635 struct ixgbe_hw *hw =
636 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
638 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
639 /* check & process vf function level reset */
640 if (!ixgbe_check_for_rst(hw, vf))
641 ixgbe_vf_reset_event(eth_dev, vf);
643 /* check & process vf mailbox messages */
644 if (!ixgbe_check_for_msg(hw, vf))
645 ixgbe_rcv_msg_from_vf(eth_dev, vf);
647 /* check & process acks from vf */
648 if (!ixgbe_check_for_ack(hw, vf))
649 ixgbe_rcv_ack_from_vf(eth_dev, vf);